drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <drm/i915_drm.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_RGB565,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 /* Primary plane formats for vlv/chv */
 116 static const u32 vlv_primary_formats[] = {
 117         DRM_FORMAT_C8,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_XRGB8888,
 120         DRM_FORMAT_XBGR8888,
 121         DRM_FORMAT_ARGB8888,
 122         DRM_FORMAT_ABGR8888,
 123         DRM_FORMAT_XRGB2101010,
 124         DRM_FORMAT_XBGR2101010,
 125         DRM_FORMAT_ARGB2101010,
 126         DRM_FORMAT_ABGR2101010,
 127         DRM_FORMAT_XBGR16161616F,
 128 };
 129
 130 static const u64 i9xx_format_modifiers[] = {
 131         I915_FORMAT_MOD_X_TILED,
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 /* Cursor formats */
 137 static const u32 intel_cursor_formats[] = {
 138         DRM_FORMAT_ARGB8888,
 139 };
 140
 141 static const u64 cursor_format_modifiers[] = {
 142         DRM_FORMAT_MOD_LINEAR,
 143         DRM_FORMAT_MOD_INVALID
 144 };
 145
 146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 147                                 struct intel_crtc_state *pipe_config);
 148 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 149                                    struct intel_crtc_state *pipe_config);
 150
 151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 152                                   struct drm_i915_gem_object *obj,
 153                                   struct drm_mode_fb_cmd2 *mode_cmd);
 154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 157                                          const struct intel_link_m_n *m_n,
 158                                          const struct intel_link_m_n *m2_n2);
 159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 160 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 161 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
 162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 163 static void vlv_prepare_pll(struct intel_crtc *crtc,
 164                             const struct intel_crtc_state *pipe_config);
 165 static void chv_prepare_pll(struct intel_crtc *crtc,
 166                             const struct intel_crtc_state *pipe_config);
 167 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 168                                     struct intel_crtc_state *crtc_state);
 169 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
 170 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 171 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 173                                          struct drm_modeset_acquire_ctx *ctx);
 174 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 175
 176 struct intel_limit {
 177         struct {
 178                 int min, max;
 179         } dot, vco, n, m, m1, m2, p, p1;
 180
 181         struct {
 182                 int dot_limit;
 183                 int p2_slow, p2_fast;
 184         } p2;
 185 };
 186
 187 /* returns HPLL frequency in kHz */
 188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 189 {
 190         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 191
 192         /* Obtain SKU information */
 193         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 194                 CCK_FUSE_HPLL_FREQ_MASK;
 195
 196         return vco_freq[hpll_freq] * 1000;
 197 }
 198
 199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 200                       const char *name, u32 reg, int ref_freq)
 201 {
 202         u32 val;
 203         int divider;
 204
 205         val = vlv_cck_read(dev_priv, reg);
 206         divider = val & CCK_FREQUENCY_VALUES;
 207
 208         WARN((val & CCK_FREQUENCY_STATUS) !=
 209              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 210              "%s change in progress\n", name);
 211
 212         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 213 }
 214
 215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 216                            const char *name, u32 reg)
 217 {
 218         int hpll;
 219
 220         vlv_cck_get(dev_priv);
 221
 222         if (dev_priv->hpll_freq == 0)
 223                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 224
 225         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 226
 227         vlv_cck_put(dev_priv);
 228
 229         return hpll;
 230 }
 231
 232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 233 {
 234         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 235                 return;
 236
 237         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 238                                                       CCK_CZ_CLOCK_CONTROL);
 239
 240         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 241 }
 242
 243 static inline u32 /* units of 100MHz */
 244 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 245                     const struct intel_crtc_state *pipe_config)
 246 {
 247         if (HAS_DDI(dev_priv))
 248                 return pipe_config->port_clock; /* SPLL */
 249         else
 250                 return dev_priv->fdi_pll_freq;
 251 }
 252
 253 static const struct intel_limit intel_limits_i8xx_dac = {
 254         .dot = { .min = 25000, .max = 350000 },
 255         .vco = { .min = 908000, .max = 1512000 },
 256         .n = { .min = 2, .max = 16 },
 257         .m = { .min = 96, .max = 140 },
 258         .m1 = { .min = 18, .max = 26 },
 259         .m2 = { .min = 6, .max = 16 },
 260         .p = { .min = 4, .max = 128 },
 261         .p1 = { .min = 2, .max = 33 },
 262         .p2 = { .dot_limit = 165000,
 263                 .p2_slow = 4, .p2_fast = 2 },
 264 };
 265
 266 static const struct intel_limit intel_limits_i8xx_dvo = {
 267         .dot = { .min = 25000, .max = 350000 },
 268         .vco = { .min = 908000, .max = 1512000 },
 269         .n = { .min = 2, .max = 16 },
 270         .m = { .min = 96, .max = 140 },
 271         .m1 = { .min = 18, .max = 26 },
 272         .m2 = { .min = 6, .max = 16 },
 273         .p = { .min = 4, .max = 128 },
 274         .p1 = { .min = 2, .max = 33 },
 275         .p2 = { .dot_limit = 165000,
 276                 .p2_slow = 4, .p2_fast = 4 },
 277 };
 278
 279 static const struct intel_limit intel_limits_i8xx_lvds = {
 280         .dot = { .min = 25000, .max = 350000 },
 281         .vco = { .min = 908000, .max = 1512000 },
 282         .n = { .min = 2, .max = 16 },
 283         .m = { .min = 96, .max = 140 },
 284         .m1 = { .min = 18, .max = 26 },
 285         .m2 = { .min = 6, .max = 16 },
 286         .p = { .min = 4, .max = 128 },
 287         .p1 = { .min = 1, .max = 6 },
 288         .p2 = { .dot_limit = 165000,
 289                 .p2_slow = 14, .p2_fast = 7 },
 290 };
 291
 292 static const struct intel_limit intel_limits_i9xx_sdvo = {
 293         .dot = { .min = 20000, .max = 400000 },
 294         .vco = { .min = 1400000, .max = 2800000 },
 295         .n = { .min = 1, .max = 6 },
 296         .m = { .min = 70, .max = 120 },
 297         .m1 = { .min = 8, .max = 18 },
 298         .m2 = { .min = 3, .max = 7 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 200000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303 };
 304
 305 static const struct intel_limit intel_limits_i9xx_lvds = {
 306         .dot = { .min = 20000, .max = 400000 },
 307         .vco = { .min = 1400000, .max = 2800000 },
 308         .n = { .min = 1, .max = 6 },
 309         .m = { .min = 70, .max = 120 },
 310         .m1 = { .min = 8, .max = 18 },
 311         .m2 = { .min = 3, .max = 7 },
 312         .p = { .min = 7, .max = 98 },
 313         .p1 = { .min = 1, .max = 8 },
 314         .p2 = { .dot_limit = 112000,
 315                 .p2_slow = 14, .p2_fast = 7 },
 316 };
 317
 318
 319 static const struct intel_limit intel_limits_g4x_sdvo = {
 320         .dot = { .min = 25000, .max = 270000 },
 321         .vco = { .min = 1750000, .max = 3500000},
 322         .n = { .min = 1, .max = 4 },
 323         .m = { .min = 104, .max = 138 },
 324         .m1 = { .min = 17, .max = 23 },
 325         .m2 = { .min = 5, .max = 11 },
 326         .p = { .min = 10, .max = 30 },
 327         .p1 = { .min = 1, .max = 3},
 328         .p2 = { .dot_limit = 270000,
 329                 .p2_slow = 10,
 330                 .p2_fast = 10
 331         },
 332 };
 333
 334 static const struct intel_limit intel_limits_g4x_hdmi = {
 335         .dot = { .min = 22000, .max = 400000 },
 336         .vco = { .min = 1750000, .max = 3500000},
 337         .n = { .min = 1, .max = 4 },
 338         .m = { .min = 104, .max = 138 },
 339         .m1 = { .min = 16, .max = 23 },
 340         .m2 = { .min = 5, .max = 11 },
 341         .p = { .min = 5, .max = 80 },
 342         .p1 = { .min = 1, .max = 8},
 343         .p2 = { .dot_limit = 165000,
 344                 .p2_slow = 10, .p2_fast = 5 },
 345 };
 346
 347 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 348         .dot = { .min = 20000, .max = 115000 },
 349         .vco = { .min = 1750000, .max = 3500000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 104, .max = 138 },
 352         .m1 = { .min = 17, .max = 23 },
 353         .m2 = { .min = 5, .max = 11 },
 354         .p = { .min = 28, .max = 112 },
 355         .p1 = { .min = 2, .max = 8 },
 356         .p2 = { .dot_limit = 0,
 357                 .p2_slow = 14, .p2_fast = 14
 358         },
 359 };
 360
 361 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 362         .dot = { .min = 80000, .max = 224000 },
 363         .vco = { .min = 1750000, .max = 3500000 },
 364         .n = { .min = 1, .max = 3 },
 365         .m = { .min = 104, .max = 138 },
 366         .m1 = { .min = 17, .max = 23 },
 367         .m2 = { .min = 5, .max = 11 },
 368         .p = { .min = 14, .max = 42 },
 369         .p1 = { .min = 2, .max = 6 },
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 7, .p2_fast = 7
 372         },
 373 };
 374
 375 static const struct intel_limit intel_limits_pineview_sdvo = {
 376         .dot = { .min = 20000, .max = 400000},
 377         .vco = { .min = 1700000, .max = 3500000 },
 378         /* Pineview's Ncounter is a ring counter */
 379         .n = { .min = 3, .max = 6 },
 380         .m = { .min = 2, .max = 256 },
 381         /* Pineview only has one combined m divider, which we treat as m2. */
 382         .m1 = { .min = 0, .max = 0 },
 383         .m2 = { .min = 0, .max = 254 },
 384         .p = { .min = 5, .max = 80 },
 385         .p1 = { .min = 1, .max = 8 },
 386         .p2 = { .dot_limit = 200000,
 387                 .p2_slow = 10, .p2_fast = 5 },
 388 };
 389
 390 static const struct intel_limit intel_limits_pineview_lvds = {
 391         .dot = { .min = 20000, .max = 400000 },
 392         .vco = { .min = 1700000, .max = 3500000 },
 393         .n = { .min = 3, .max = 6 },
 394         .m = { .min = 2, .max = 256 },
 395         .m1 = { .min = 0, .max = 0 },
 396         .m2 = { .min = 0, .max = 254 },
 397         .p = { .min = 7, .max = 112 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 112000,
 400                 .p2_slow = 14, .p2_fast = 14 },
 401 };
 402
 403 /* Ironlake / Sandybridge
 404  *
 405  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 406  * the range value for them is (actual_value - 2).
 407  */
 408 static const struct intel_limit intel_limits_ironlake_dac = {
 409         .dot = { .min = 25000, .max = 350000 },
 410         .vco = { .min = 1760000, .max = 3510000 },
 411         .n = { .min = 1, .max = 5 },
 412         .m = { .min = 79, .max = 127 },
 413         .m1 = { .min = 12, .max = 22 },
 414         .m2 = { .min = 5, .max = 9 },
 415         .p = { .min = 5, .max = 80 },
 416         .p1 = { .min = 1, .max = 8 },
 417         .p2 = { .dot_limit = 225000,
 418                 .p2_slow = 10, .p2_fast = 5 },
 419 };
 420
 421 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 422         .dot = { .min = 25000, .max = 350000 },
 423         .vco = { .min = 1760000, .max = 3510000 },
 424         .n = { .min = 1, .max = 3 },
 425         .m = { .min = 79, .max = 118 },
 426         .m1 = { .min = 12, .max = 22 },
 427         .m2 = { .min = 5, .max = 9 },
 428         .p = { .min = 28, .max = 112 },
 429         .p1 = { .min = 2, .max = 8 },
 430         .p2 = { .dot_limit = 225000,
 431                 .p2_slow = 14, .p2_fast = 14 },
 432 };
 433
 434 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 435         .dot = { .min = 25000, .max = 350000 },
 436         .vco = { .min = 1760000, .max = 3510000 },
 437         .n = { .min = 1, .max = 3 },
 438         .m = { .min = 79, .max = 127 },
 439         .m1 = { .min = 12, .max = 22 },
 440         .m2 = { .min = 5, .max = 9 },
 441         .p = { .min = 14, .max = 56 },
 442         .p1 = { .min = 2, .max = 8 },
 443         .p2 = { .dot_limit = 225000,
 444                 .p2_slow = 7, .p2_fast = 7 },
 445 };
 446
 447 /* LVDS 100mhz refclk limits. */
 448 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 449         .dot = { .min = 25000, .max = 350000 },
 450         .vco = { .min = 1760000, .max = 3510000 },
 451         .n = { .min = 1, .max = 2 },
 452         .m = { .min = 79, .max = 126 },
 453         .m1 = { .min = 12, .max = 22 },
 454         .m2 = { .min = 5, .max = 9 },
 455         .p = { .min = 28, .max = 112 },
 456         .p1 = { .min = 2, .max = 8 },
 457         .p2 = { .dot_limit = 225000,
 458                 .p2_slow = 14, .p2_fast = 14 },
 459 };
 460
 461 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 462         .dot = { .min = 25000, .max = 350000 },
 463         .vco = { .min = 1760000, .max = 3510000 },
 464         .n = { .min = 1, .max = 3 },
 465         .m = { .min = 79, .max = 126 },
 466         .m1 = { .min = 12, .max = 22 },
 467         .m2 = { .min = 5, .max = 9 },
 468         .p = { .min = 14, .max = 42 },
 469         .p1 = { .min = 2, .max = 6 },
 470         .p2 = { .dot_limit = 225000,
 471                 .p2_slow = 7, .p2_fast = 7 },
 472 };
 473
 474 static const struct intel_limit intel_limits_vlv = {
 475          /*
 476           * These are the data rate limits (measured in fast clocks)
 477           * since those are the strictest limits we have. The fast
 478           * clock and actual rate limits are more relaxed, so checking
 479           * them would make no difference.
 480           */
 481         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 482         .vco = { .min = 4000000, .max = 6000000 },
 483         .n = { .min = 1, .max = 7 },
 484         .m1 = { .min = 2, .max = 3 },
 485         .m2 = { .min = 11, .max = 156 },
 486         .p1 = { .min = 2, .max = 3 },
 487         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 488 };
 489
 490 static const struct intel_limit intel_limits_chv = {
 491         /*
 492          * These are the data rate limits (measured in fast clocks)
 493          * since those are the strictest limits we have.  The fast
 494          * clock and actual rate limits are more relaxed, so checking
 495          * them would make no difference.
 496          */
 497         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 498         .vco = { .min = 4800000, .max = 6480000 },
 499         .n = { .min = 1, .max = 1 },
 500         .m1 = { .min = 2, .max = 2 },
 501         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 502         .p1 = { .min = 2, .max = 4 },
 503         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 504 };
 505
 506 static const struct intel_limit intel_limits_bxt = {
 507         /* FIXME: find real dot limits */
 508         .dot = { .min = 0, .max = INT_MAX },
 509         .vco = { .min = 4800000, .max = 6700000 },
 510         .n = { .min = 1, .max = 1 },
 511         .m1 = { .min = 2, .max = 2 },
 512         /* FIXME: find real m2 limits */
 513         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 514         .p1 = { .min = 2, .max = 4 },
 515         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 516 };
 517
 518 /* WA Display #0827: Gen9:all */
 519 static void
 520 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 521 {
 522         if (enable)
 523                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 524                            I915_READ(CLKGATE_DIS_PSL(pipe)) |
 525                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 526         else
 527                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 528                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 529                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 530 }
 531
 532 /* Wa_2006604312:icl */
 533 static void
 534 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 535                        bool enable)
 536 {
 537         if (enable)
 538                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 539                            I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 540         else
 541                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 542                            I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 543 }
 544
 545 static bool
 546 needs_modeset(const struct intel_crtc_state *state)
 547 {
 548         return drm_atomic_crtc_needs_modeset(&state->uapi);
 549 }
 550
 551 bool
 552 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 553 {
 554         return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
 555                 crtc_state->sync_mode_slaves_mask);
 556 }
 557
 558 static bool
 559 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 560 {
 561         return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
 562                 crtc_state->sync_mode_slaves_mask);
 563 }
 564
 565 /*
 566  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 567  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 568  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 569  * The helpers' return value is the rate of the clock that is fed to the
 570  * display engine's pipe which can be the above fast dot clock rate or a
 571  * divided-down version of it.
 572  */
 573 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 574 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 575 {
 576         clock->m = clock->m2 + 2;
 577         clock->p = clock->p1 * clock->p2;
 578         if (WARN_ON(clock->n == 0 || clock->p == 0))
 579                 return 0;
 580         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 581         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 582
 583         return clock->dot;
 584 }
 585
 586 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 587 {
 588         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 589 }
 590
 591 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 592 {
 593         clock->m = i9xx_dpll_compute_m(clock);
 594         clock->p = clock->p1 * clock->p2;
 595         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 596                 return 0;
 597         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 598         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 599
 600         return clock->dot;
 601 }
 602
 603 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 604 {
 605         clock->m = clock->m1 * clock->m2;
 606         clock->p = clock->p1 * clock->p2;
 607         if (WARN_ON(clock->n == 0 || clock->p == 0))
 608                 return 0;
 609         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 610         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 611
 612         return clock->dot / 5;
 613 }
 614
 615 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 616 {
 617         clock->m = clock->m1 * clock->m2;
 618         clock->p = clock->p1 * clock->p2;
 619         if (WARN_ON(clock->n == 0 || clock->p == 0))
 620                 return 0;
 621         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 622                                            clock->n << 22);
 623         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 624
 625         return clock->dot / 5;
 626 }
 627
 628 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 629
 630 /*
 631  * Returns whether the given set of divisors are valid for a given refclk with
 632  * the given connectors.
 633  */
 634 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 635                                const struct intel_limit *limit,
 636                                const struct dpll *clock)
 637 {
 638         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 639                 INTELPllInvalid("n out of range\n");
 640         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 641                 INTELPllInvalid("p1 out of range\n");
 642         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 643                 INTELPllInvalid("m2 out of range\n");
 644         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 645                 INTELPllInvalid("m1 out of range\n");
 646
 647         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 648             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 649                 if (clock->m1 <= clock->m2)
 650                         INTELPllInvalid("m1 <= m2\n");
 651
 652         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 653             !IS_GEN9_LP(dev_priv)) {
 654                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 655                         INTELPllInvalid("p out of range\n");
 656                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 657                         INTELPllInvalid("m out of range\n");
 658         }
 659
 660         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 661                 INTELPllInvalid("vco out of range\n");
 662         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 663          * connector, etc., rather than just a single range.
 664          */
 665         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 666                 INTELPllInvalid("dot out of range\n");
 667
 668         return true;
 669 }
 670
 671 static int
 672 i9xx_select_p2_div(const struct intel_limit *limit,
 673                    const struct intel_crtc_state *crtc_state,
 674                    int target)
 675 {
 676         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 677
 678         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 679                 /*
 680                  * For LVDS just rely on its current settings for dual-channel.
 681                  * We haven't figured out how to reliably set up different
 682                  * single/dual channel state, if we even can.
 683                  */
 684                 if (intel_is_dual_link_lvds(dev_priv))
 685                         return limit->p2.p2_fast;
 686                 else
 687                         return limit->p2.p2_slow;
 688         } else {
 689                 if (target < limit->p2.dot_limit)
 690                         return limit->p2.p2_slow;
 691                 else
 692                         return limit->p2.p2_fast;
 693         }
 694 }
 695
 696 /*
 697  * Returns a set of divisors for the desired target clock with the given
 698  * refclk, or FALSE.  The returned values represent the clock equation:
 699  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 700  *
 701  * Target and reference clocks are specified in kHz.
 702  *
 703  * If match_clock is provided, then best_clock P divider must match the P
 704  * divider from @match_clock used for LVDS downclocking.
 705  */
 706 static bool
 707 i9xx_find_best_dpll(const struct intel_limit *limit,
 708                     struct intel_crtc_state *crtc_state,
 709                     int target, int refclk, struct dpll *match_clock,
 710                     struct dpll *best_clock)
 711 {
 712         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 713         struct dpll clock;
 714         int err = target;
 715
 716         memset(best_clock, 0, sizeof(*best_clock));
 717
 718         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 719
 720         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 721              clock.m1++) {
 722                 for (clock.m2 = limit->m2.min;
 723                      clock.m2 <= limit->m2.max; clock.m2++) {
 724                         if (clock.m2 >= clock.m1)
 725                                 break;
 726                         for (clock.n = limit->n.min;
 727                              clock.n <= limit->n.max; clock.n++) {
 728                                 for (clock.p1 = limit->p1.min;
 729                                         clock.p1 <= limit->p1.max; clock.p1++) {
 730                                         int this_err;
 731
 732                                         i9xx_calc_dpll_params(refclk, &clock);
 733                                         if (!intel_PLL_is_valid(to_i915(dev),
 734                                                                 limit,
 735                                                                 &clock))
 736                                                 continue;
 737                                         if (match_clock &&
 738                                             clock.p != match_clock->p)
 739                                                 continue;
 740
 741                                         this_err = abs(clock.dot - target);
 742                                         if (this_err < err) {
 743                                                 *best_clock = clock;
 744                                                 err = this_err;
 745                                         }
 746                                 }
 747                         }
 748                 }
 749         }
 750
 751         return (err != target);
 752 }
 753
 754 /*
 755  * Returns a set of divisors for the desired target clock with the given
 756  * refclk, or FALSE.  The returned values represent the clock equation:
 757  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 758  *
 759  * Target and reference clocks are specified in kHz.
 760  *
 761  * If match_clock is provided, then best_clock P divider must match the P
 762  * divider from @match_clock used for LVDS downclocking.
 763  */
 764 static bool
 765 pnv_find_best_dpll(const struct intel_limit *limit,
 766                    struct intel_crtc_state *crtc_state,
 767                    int target, int refclk, struct dpll *match_clock,
 768                    struct dpll *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 771         struct dpll clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         for (clock.n = limit->n.min;
 783                              clock.n <= limit->n.max; clock.n++) {
 784                                 for (clock.p1 = limit->p1.min;
 785                                         clock.p1 <= limit->p1.max; clock.p1++) {
 786                                         int this_err;
 787
 788                                         pnv_calc_dpll_params(refclk, &clock);
 789                                         if (!intel_PLL_is_valid(to_i915(dev),
 790                                                                 limit,
 791                                                                 &clock))
 792                                                 continue;
 793                                         if (match_clock &&
 794                                             clock.p != match_clock->p)
 795                                                 continue;
 796
 797                                         this_err = abs(clock.dot - target);
 798                                         if (this_err < err) {
 799                                                 *best_clock = clock;
 800                                                 err = this_err;
 801                                         }
 802                                 }
 803                         }
 804                 }
 805         }
 806
 807         return (err != target);
 808 }
 809
 810 /*
 811  * Returns a set of divisors for the desired target clock with the given
 812  * refclk, or FALSE.  The returned values represent the clock equation:
 813  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 814  *
 815  * Target and reference clocks are specified in kHz.
 816  *
 817  * If match_clock is provided, then best_clock P divider must match the P
 818  * divider from @match_clock used for LVDS downclocking.
 819  */
 820 static bool
 821 g4x_find_best_dpll(const struct intel_limit *limit,
 822                    struct intel_crtc_state *crtc_state,
 823                    int target, int refclk, struct dpll *match_clock,
 824                    struct dpll *best_clock)
 825 {
 826         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 827         struct dpll clock;
 828         int max_n;
 829         bool found = false;
 830         /* approximately equals target * 0.00585 */
 831         int err_most = (target >> 8) + (target >> 9);
 832
 833         memset(best_clock, 0, sizeof(*best_clock));
 834
 835         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 836
 837         max_n = limit->n.max;
 838         /* based on hardware requirement, prefer smaller n to precision */
 839         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 840                 /* based on hardware requirement, prefere larger m1,m2 */
 841                 for (clock.m1 = limit->m1.max;
 842                      clock.m1 >= limit->m1.min; clock.m1--) {
 843                         for (clock.m2 = limit->m2.max;
 844                              clock.m2 >= limit->m2.min; clock.m2--) {
 845                                 for (clock.p1 = limit->p1.max;
 846                                      clock.p1 >= limit->p1.min; clock.p1--) {
 847                                         int this_err;
 848
 849                                         i9xx_calc_dpll_params(refclk, &clock);
 850                                         if (!intel_PLL_is_valid(to_i915(dev),
 851                                                                 limit,
 852                                                                 &clock))
 853                                                 continue;
 854
 855                                         this_err = abs(clock.dot - target);
 856                                         if (this_err < err_most) {
 857                                                 *best_clock = clock;
 858                                                 err_most = this_err;
 859                                                 max_n = clock.n;
 860                                                 found = true;
 861                                         }
 862                                 }
 863                         }
 864                 }
 865         }
 866         return found;
 867 }
 868
 869 /*
 870  * Check if the calculated PLL configuration is more optimal compared to the
 871  * best configuration and error found so far. Return the calculated error.
 872  */
 873 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 874                                const struct dpll *calculated_clock,
 875                                const struct dpll *best_clock,
 876                                unsigned int best_error_ppm,
 877                                unsigned int *error_ppm)
 878 {
 879         /*
 880          * For CHV ignore the error and consider only the P value.
 881          * Prefer a bigger P value based on HW requirements.
 882          */
 883         if (IS_CHERRYVIEW(to_i915(dev))) {
 884                 *error_ppm = 0;
 885
 886                 return calculated_clock->p > best_clock->p;
 887         }
 888
 889         if (WARN_ON_ONCE(!target_freq))
 890                 return false;
 891
 892         *error_ppm = div_u64(1000000ULL *
 893                                 abs(target_freq - calculated_clock->dot),
 894                              target_freq);
 895         /*
 896          * Prefer a better P value over a better (smaller) error if the error
 897          * is small. Ensure this preference for future configurations too by
 898          * setting the error to 0.
 899          */
 900         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 901                 *error_ppm = 0;
 902
 903                 return true;
 904         }
 905
 906         return *error_ppm + 10 < best_error_ppm;
 907 }
 908
 909 /*
 910  * Returns a set of divisors for the desired target clock with the given
 911  * refclk, or FALSE.  The returned values represent the clock equation:
 912  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 913  */
 914 static bool
 915 vlv_find_best_dpll(const struct intel_limit *limit,
 916                    struct intel_crtc_state *crtc_state,
 917                    int target, int refclk, struct dpll *match_clock,
 918                    struct dpll *best_clock)
 919 {
 920         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 921         struct drm_device *dev = crtc->base.dev;
 922         struct dpll clock;
 923         unsigned int bestppm = 1000000;
 924         /* min update 19.2 MHz */
 925         int max_n = min(limit->n.max, refclk / 19200);
 926         bool found = false;
 927
 928         target *= 5; /* fast clock */
 929
 930         memset(best_clock, 0, sizeof(*best_clock));
 931
 932         /* based on hardware requirement, prefer smaller n to precision */
 933         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 934                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 935                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 936                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 937                                 clock.p = clock.p1 * clock.p2;
 938                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 939                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 940                                         unsigned int ppm;
 941
 942                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 943                                                                      refclk * clock.m1);
 944
 945                                         vlv_calc_dpll_params(refclk, &clock);
 946
 947                                         if (!intel_PLL_is_valid(to_i915(dev),
 948                                                                 limit,
 949                                                                 &clock))
 950                                                 continue;
 951
 952                                         if (!vlv_PLL_is_optimal(dev, target,
 953                                                                 &clock,
 954                                                                 best_clock,
 955                                                                 bestppm, &ppm))
 956                                                 continue;
 957
 958                                         *best_clock = clock;
 959                                         bestppm = ppm;
 960                                         found = true;
 961                                 }
 962                         }
 963                 }
 964         }
 965
 966         return found;
 967 }
 968
 969 /*
 970  * Returns a set of divisors for the desired target clock with the given
 971  * refclk, or FALSE.  The returned values represent the clock equation:
 972  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 973  */
 974 static bool
 975 chv_find_best_dpll(const struct intel_limit *limit,
 976                    struct intel_crtc_state *crtc_state,
 977                    int target, int refclk, struct dpll *match_clock,
 978                    struct dpll *best_clock)
 979 {
 980         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 981         struct drm_device *dev = crtc->base.dev;
 982         unsigned int best_error_ppm;
 983         struct dpll clock;
 984         u64 m2;
 985         int found = false;
 986
 987         memset(best_clock, 0, sizeof(*best_clock));
 988         best_error_ppm = 1000000;
 989
 990         /*
 991          * Based on hardware doc, the n always set to 1, and m1 always
 992          * set to 2.  If requires to support 200Mhz refclk, we need to
 993          * revisit this because n may not 1 anymore.
 994          */
 995         clock.n = 1, clock.m1 = 2;
 996         target *= 5;    /* fast clock */
 997
 998         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 999                 for (clock.p2 = limit->p2.p2_fast;
1000                                 clock.p2 >= limit->p2.p2_slow;
1001                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1002                         unsigned int error_ppm;
1003
1004                         clock.p = clock.p1 * clock.p2;
1005
1006                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1007                                                    refclk * clock.m1);
1008
1009                         if (m2 > INT_MAX/clock.m1)
1010                                 continue;
1011
1012                         clock.m2 = m2;
1013
1014                         chv_calc_dpll_params(refclk, &clock);
1015
1016                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1017                                 continue;
1018
1019                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1020                                                 best_error_ppm, &error_ppm))
1021                                 continue;
1022
1023                         *best_clock = clock;
1024                         best_error_ppm = error_ppm;
1025                         found = true;
1026                 }
1027         }
1028
1029         return found;
1030 }
1031
1032 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1033                         struct dpll *best_clock)
1034 {
1035         int refclk = 100000;
1036         const struct intel_limit *limit = &intel_limits_bxt;
1037
1038         return chv_find_best_dpll(limit, crtc_state,
1039                                   crtc_state->port_clock, refclk,
1040                                   NULL, best_clock);
1041 }
1042
1043 bool intel_crtc_active(struct intel_crtc *crtc)
1044 {
1045         /* Be paranoid as we can arrive here with only partial
1046          * state retrieved from the hardware during setup.
1047          *
1048          * We can ditch the adjusted_mode.crtc_clock check as soon
1049          * as Haswell has gained clock readout/fastboot support.
1050          *
1051          * We can ditch the crtc->primary->state->fb check as soon as we can
1052          * properly reconstruct framebuffers.
1053          *
1054          * FIXME: The intel_crtc->active here should be switched to
1055          * crtc->state->active once we have proper CRTC states wired up
1056          * for atomic.
1057          */
1058         return crtc->active && crtc->base.primary->state->fb &&
1059                 crtc->config->hw.adjusted_mode.crtc_clock;
1060 }
1061
1062 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1063                                              enum pipe pipe)
1064 {
1065         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1066
1067         return crtc->config->cpu_transcoder;
1068 }
1069
1070 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1071                                     enum pipe pipe)
1072 {
1073         i915_reg_t reg = PIPEDSL(pipe);
1074         u32 line1, line2;
1075         u32 line_mask;
1076
1077         if (IS_GEN(dev_priv, 2))
1078                 line_mask = DSL_LINEMASK_GEN2;
1079         else
1080                 line_mask = DSL_LINEMASK_GEN3;
1081
1082         line1 = I915_READ(reg) & line_mask;
1083         msleep(5);
1084         line2 = I915_READ(reg) & line_mask;
1085
1086         return line1 != line2;
1087 }
1088
1089 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1090 {
1091         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092         enum pipe pipe = crtc->pipe;
1093
1094         /* Wait for the display line to settle/start moving */
1095         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1096                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1097                           pipe_name(pipe), onoff(state));
1098 }
1099
1100 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1101 {
1102         wait_for_pipe_scanline_moving(crtc, false);
1103 }
1104
1105 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1106 {
1107         wait_for_pipe_scanline_moving(crtc, true);
1108 }
1109
1110 static void
1111 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1112 {
1113         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1114         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1115
1116         if (INTEL_GEN(dev_priv) >= 4) {
1117                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1118                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1119
1120                 /* Wait for the Pipe State to go off */
1121                 if (intel_de_wait_for_clear(dev_priv, reg,
1122                                             I965_PIPECONF_ACTIVE, 100))
1123                         WARN(1, "pipe_off wait timed out\n");
1124         } else {
1125                 intel_wait_for_pipe_scanline_stopped(crtc);
1126         }
1127 }
1128
1129 /* Only for pre-ILK configs */
1130 void assert_pll(struct drm_i915_private *dev_priv,
1131                 enum pipe pipe, bool state)
1132 {
1133         u32 val;
1134         bool cur_state;
1135
1136         val = I915_READ(DPLL(pipe));
1137         cur_state = !!(val & DPLL_VCO_ENABLE);
1138         I915_STATE_WARN(cur_state != state,
1139              "PLL state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142
1143 /* XXX: the dsi pll is shared between MIPI DSI ports */
1144 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1145 {
1146         u32 val;
1147         bool cur_state;
1148
1149         vlv_cck_get(dev_priv);
1150         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1151         vlv_cck_put(dev_priv);
1152
1153         cur_state = val & DSI_PLL_VCO_EN;
1154         I915_STATE_WARN(cur_state != state,
1155              "DSI PLL state assertion failure (expected %s, current %s)\n",
1156                         onoff(state), onoff(cur_state));
1157 }
1158
1159 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1160                           enum pipe pipe, bool state)
1161 {
1162         bool cur_state;
1163         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1164                                                                       pipe);
1165
1166         if (HAS_DDI(dev_priv)) {
1167                 /* DDI does not have a specific FDI_TX register */
1168                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1169                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1170         } else {
1171                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1172                 cur_state = !!(val & FDI_TX_ENABLE);
1173         }
1174         I915_STATE_WARN(cur_state != state,
1175              "FDI TX state assertion failure (expected %s, current %s)\n",
1176                         onoff(state), onoff(cur_state));
1177 }
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180
1181 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182                           enum pipe pipe, bool state)
1183 {
1184         u32 val;
1185         bool cur_state;
1186
1187         val = I915_READ(FDI_RX_CTL(pipe));
1188         cur_state = !!(val & FDI_RX_ENABLE);
1189         I915_STATE_WARN(cur_state != state,
1190              "FDI RX state assertion failure (expected %s, current %s)\n",
1191                         onoff(state), onoff(cur_state));
1192 }
1193 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1194 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1195
1196 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1197                                       enum pipe pipe)
1198 {
1199         u32 val;
1200
1201         /* ILK FDI PLL is always enabled */
1202         if (IS_GEN(dev_priv, 5))
1203                 return;
1204
1205         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1206         if (HAS_DDI(dev_priv))
1207                 return;
1208
1209         val = I915_READ(FDI_TX_CTL(pipe));
1210         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1211 }
1212
1213 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1214                        enum pipe pipe, bool state)
1215 {
1216         u32 val;
1217         bool cur_state;
1218
1219         val = I915_READ(FDI_RX_CTL(pipe));
1220         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1221         I915_STATE_WARN(cur_state != state,
1222              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1223                         onoff(state), onoff(cur_state));
1224 }
1225
1226 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1227 {
1228         i915_reg_t pp_reg;
1229         u32 val;
1230         enum pipe panel_pipe = INVALID_PIPE;
1231         bool locked = true;
1232
1233         if (WARN_ON(HAS_DDI(dev_priv)))
1234                 return;
1235
1236         if (HAS_PCH_SPLIT(dev_priv)) {
1237                 u32 port_sel;
1238
1239                 pp_reg = PP_CONTROL(0);
1240                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1241
1242                 switch (port_sel) {
1243                 case PANEL_PORT_SELECT_LVDS:
1244                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1245                         break;
1246                 case PANEL_PORT_SELECT_DPA:
1247                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1248                         break;
1249                 case PANEL_PORT_SELECT_DPC:
1250                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1251                         break;
1252                 case PANEL_PORT_SELECT_DPD:
1253                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1254                         break;
1255                 default:
1256                         MISSING_CASE(port_sel);
1257                         break;
1258                 }
1259         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1260                 /* presumably write lock depends on pipe, not port select */
1261                 pp_reg = PP_CONTROL(pipe);
1262                 panel_pipe = pipe;
1263         } else {
1264                 u32 port_sel;
1265
1266                 pp_reg = PP_CONTROL(0);
1267                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1268
1269                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1270                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1271         }
1272
1273         val = I915_READ(pp_reg);
1274         if (!(val & PANEL_POWER_ON) ||
1275             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1276                 locked = false;
1277
1278         I915_STATE_WARN(panel_pipe == pipe && locked,
1279              "panel assertion failure, pipe %c regs locked\n",
1280              pipe_name(pipe));
1281 }
1282
1283 void assert_pipe(struct drm_i915_private *dev_priv,
1284                  enum pipe pipe, bool state)
1285 {
1286         bool cur_state;
1287         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1288                                                                       pipe);
1289         enum intel_display_power_domain power_domain;
1290         intel_wakeref_t wakeref;
1291
1292         /* we keep both pipes enabled on 830 */
1293         if (IS_I830(dev_priv))
1294                 state = true;
1295
1296         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1297         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1298         if (wakeref) {
1299                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1300                 cur_state = !!(val & PIPECONF_ENABLE);
1301
1302                 intel_display_power_put(dev_priv, power_domain, wakeref);
1303         } else {
1304                 cur_state = false;
1305         }
1306
1307         I915_STATE_WARN(cur_state != state,
1308              "pipe %c assertion failure (expected %s, current %s)\n",
1309                         pipe_name(pipe), onoff(state), onoff(cur_state));
1310 }
1311
1312 static void assert_plane(struct intel_plane *plane, bool state)
1313 {
1314         enum pipe pipe;
1315         bool cur_state;
1316
1317         cur_state = plane->get_hw_state(plane, &pipe);
1318
1319         I915_STATE_WARN(cur_state != state,
1320                         "%s assertion failure (expected %s, current %s)\n",
1321                         plane->base.name, onoff(state), onoff(cur_state));
1322 }
1323
1324 #define assert_plane_enabled(p) assert_plane(p, true)
1325 #define assert_plane_disabled(p) assert_plane(p, false)
1326
1327 static void assert_planes_disabled(struct intel_crtc *crtc)
1328 {
1329         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1330         struct intel_plane *plane;
1331
1332         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1333                 assert_plane_disabled(plane);
1334 }
1335
1336 static void assert_vblank_disabled(struct drm_crtc *crtc)
1337 {
1338         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1339                 drm_crtc_vblank_put(crtc);
1340 }
1341
1342 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1343                                     enum pipe pipe)
1344 {
1345         u32 val;
1346         bool enabled;
1347
1348         val = I915_READ(PCH_TRANSCONF(pipe));
1349         enabled = !!(val & TRANS_ENABLE);
1350         I915_STATE_WARN(enabled,
1351              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1352              pipe_name(pipe));
1353 }
1354
1355 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1356                                    enum pipe pipe, enum port port,
1357                                    i915_reg_t dp_reg)
1358 {
1359         enum pipe port_pipe;
1360         bool state;
1361
1362         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1363
1364         I915_STATE_WARN(state && port_pipe == pipe,
1365                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1366                         port_name(port), pipe_name(pipe));
1367
1368         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369                         "IBX PCH DP %c still using transcoder B\n",
1370                         port_name(port));
1371 }
1372
1373 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1374                                      enum pipe pipe, enum port port,
1375                                      i915_reg_t hdmi_reg)
1376 {
1377         enum pipe port_pipe;
1378         bool state;
1379
1380         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1381
1382         I915_STATE_WARN(state && port_pipe == pipe,
1383                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1384                         port_name(port), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1387                         "IBX PCH HDMI %c still using transcoder B\n",
1388                         port_name(port));
1389 }
1390
1391 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1392                                       enum pipe pipe)
1393 {
1394         enum pipe port_pipe;
1395
1396         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1397         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1398         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1399
1400         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1401                         port_pipe == pipe,
1402                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1403                         pipe_name(pipe));
1404
1405         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1406                         port_pipe == pipe,
1407                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1408                         pipe_name(pipe));
1409
1410         /* PCH SDVOB multiplex with HDMIB */
1411         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1412         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1413         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1414 }
1415
1416 static void _vlv_enable_pll(struct intel_crtc *crtc,
1417                             const struct intel_crtc_state *pipe_config)
1418 {
1419         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1420         enum pipe pipe = crtc->pipe;
1421
1422         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1423         POSTING_READ(DPLL(pipe));
1424         udelay(150);
1425
1426         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1427                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1428 }
1429
1430 static void vlv_enable_pll(struct intel_crtc *crtc,
1431                            const struct intel_crtc_state *pipe_config)
1432 {
1433         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1434         enum pipe pipe = crtc->pipe;
1435
1436         assert_pipe_disabled(dev_priv, pipe);
1437
1438         /* PLL is protected by panel, make sure we can write it */
1439         assert_panel_unlocked(dev_priv, pipe);
1440
1441         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1442                 _vlv_enable_pll(crtc, pipe_config);
1443
1444         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1445         POSTING_READ(DPLL_MD(pipe));
1446 }
1447
1448
1449 static void _chv_enable_pll(struct intel_crtc *crtc,
1450                             const struct intel_crtc_state *pipe_config)
1451 {
1452         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1453         enum pipe pipe = crtc->pipe;
1454         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1455         u32 tmp;
1456
1457         vlv_dpio_get(dev_priv);
1458
1459         /* Enable back the 10bit clock to display controller */
1460         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1461         tmp |= DPIO_DCLKP_EN;
1462         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1463
1464         vlv_dpio_put(dev_priv);
1465
1466         /*
1467          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1468          */
1469         udelay(1);
1470
1471         /* Enable PLL */
1472         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1473
1474         /* Check PLL is locked */
1475         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1476                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1477 }
1478
1479 static void chv_enable_pll(struct intel_crtc *crtc,
1480                            const struct intel_crtc_state *pipe_config)
1481 {
1482         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1483         enum pipe pipe = crtc->pipe;
1484
1485         assert_pipe_disabled(dev_priv, pipe);
1486
1487         /* PLL is protected by panel, make sure we can write it */
1488         assert_panel_unlocked(dev_priv, pipe);
1489
1490         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1491                 _chv_enable_pll(crtc, pipe_config);
1492
1493         if (pipe != PIPE_A) {
1494                 /*
1495                  * WaPixelRepeatModeFixForC0:chv
1496                  *
1497                  * DPLLCMD is AWOL. Use chicken bits to propagate
1498                  * the value from DPLLBMD to either pipe B or C.
1499                  */
1500                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1501                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1502                 I915_WRITE(CBR4_VLV, 0);
1503                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1504
1505                 /*
1506                  * DPLLB VGA mode also seems to cause problems.
1507                  * We should always have it disabled.
1508                  */
1509                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1510         } else {
1511                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1512                 POSTING_READ(DPLL_MD(pipe));
1513         }
1514 }
1515
1516 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1517 {
1518         if (IS_I830(dev_priv))
1519                 return false;
1520
1521         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1522 }
1523
1524 static void i9xx_enable_pll(struct intel_crtc *crtc,
1525                             const struct intel_crtc_state *crtc_state)
1526 {
1527         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1528         i915_reg_t reg = DPLL(crtc->pipe);
1529         u32 dpll = crtc_state->dpll_hw_state.dpll;
1530         int i;
1531
1532         assert_pipe_disabled(dev_priv, crtc->pipe);
1533
1534         /* PLL is protected by panel, make sure we can write it */
1535         if (i9xx_has_pps(dev_priv))
1536                 assert_panel_unlocked(dev_priv, crtc->pipe);
1537
1538         /*
1539          * Apparently we need to have VGA mode enabled prior to changing
1540          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1541          * dividers, even though the register value does change.
1542          */
1543         I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1544         I915_WRITE(reg, dpll);
1545
1546         /* Wait for the clocks to stabilize. */
1547         POSTING_READ(reg);
1548         udelay(150);
1549
1550         if (INTEL_GEN(dev_priv) >= 4) {
1551                 I915_WRITE(DPLL_MD(crtc->pipe),
1552                            crtc_state->dpll_hw_state.dpll_md);
1553         } else {
1554                 /* The pixel multiplier can only be updated once the
1555                  * DPLL is enabled and the clocks are stable.
1556                  *
1557                  * So write it again.
1558                  */
1559                 I915_WRITE(reg, dpll);
1560         }
1561
1562         /* We do this three times for luck */
1563         for (i = 0; i < 3; i++) {
1564                 I915_WRITE(reg, dpll);
1565                 POSTING_READ(reg);
1566                 udelay(150); /* wait for warmup */
1567         }
1568 }
1569
1570 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1571 {
1572         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1573         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574         enum pipe pipe = crtc->pipe;
1575
1576         /* Don't disable pipe or pipe PLLs if needed */
1577         if (IS_I830(dev_priv))
1578                 return;
1579
1580         /* Make sure the pipe isn't still relying on us */
1581         assert_pipe_disabled(dev_priv, pipe);
1582
1583         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1584         POSTING_READ(DPLL(pipe));
1585 }
1586
1587 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1588 {
1589         u32 val;
1590
1591         /* Make sure the pipe isn't still relying on us */
1592         assert_pipe_disabled(dev_priv, pipe);
1593
1594         val = DPLL_INTEGRATED_REF_CLK_VLV |
1595                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1596         if (pipe != PIPE_A)
1597                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1598
1599         I915_WRITE(DPLL(pipe), val);
1600         POSTING_READ(DPLL(pipe));
1601 }
1602
1603 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1604 {
1605         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1606         u32 val;
1607
1608         /* Make sure the pipe isn't still relying on us */
1609         assert_pipe_disabled(dev_priv, pipe);
1610
1611         val = DPLL_SSC_REF_CLK_CHV |
1612                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1613         if (pipe != PIPE_A)
1614                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1615
1616         I915_WRITE(DPLL(pipe), val);
1617         POSTING_READ(DPLL(pipe));
1618
1619         vlv_dpio_get(dev_priv);
1620
1621         /* Disable 10bit clock to display controller */
1622         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1623         val &= ~DPIO_DCLKP_EN;
1624         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1625
1626         vlv_dpio_put(dev_priv);
1627 }
1628
1629 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1630                          struct intel_digital_port *dport,
1631                          unsigned int expected_mask)
1632 {
1633         u32 port_mask;
1634         i915_reg_t dpll_reg;
1635
1636         switch (dport->base.port) {
1637         case PORT_B:
1638                 port_mask = DPLL_PORTB_READY_MASK;
1639                 dpll_reg = DPLL(0);
1640                 break;
1641         case PORT_C:
1642                 port_mask = DPLL_PORTC_READY_MASK;
1643                 dpll_reg = DPLL(0);
1644                 expected_mask <<= 4;
1645                 break;
1646         case PORT_D:
1647                 port_mask = DPLL_PORTD_READY_MASK;
1648                 dpll_reg = DPIO_PHY_STATUS;
1649                 break;
1650         default:
1651                 BUG();
1652         }
1653
1654         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1655                                        port_mask, expected_mask, 1000))
1656                 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1657                      dport->base.base.base.id, dport->base.base.name,
1658                      I915_READ(dpll_reg) & port_mask, expected_mask);
1659 }
1660
1661 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1662 {
1663         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1665         enum pipe pipe = crtc->pipe;
1666         i915_reg_t reg;
1667         u32 val, pipeconf_val;
1668
1669         /* Make sure PCH DPLL is enabled */
1670         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1671
1672         /* FDI must be feeding us bits for PCH ports */
1673         assert_fdi_tx_enabled(dev_priv, pipe);
1674         assert_fdi_rx_enabled(dev_priv, pipe);
1675
1676         if (HAS_PCH_CPT(dev_priv)) {
1677                 reg = TRANS_CHICKEN2(pipe);
1678                 val = I915_READ(reg);
1679                 /*
1680                  * Workaround: Set the timing override bit
1681                  * before enabling the pch transcoder.
1682                  */
1683                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1684                 /* Configure frame start delay to match the CPU */
1685                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1686                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1687                 I915_WRITE(reg, val);
1688         }
1689
1690         reg = PCH_TRANSCONF(pipe);
1691         val = I915_READ(reg);
1692         pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694         if (HAS_PCH_IBX(dev_priv)) {
1695                 /* Configure frame start delay to match the CPU */
1696                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1697                 val |= TRANS_FRAME_START_DELAY(0);
1698
1699                 /*
1700                  * Make the BPC in transcoder be consistent with
1701                  * that in pipeconf reg. For HDMI we must use 8bpc
1702                  * here for both 8bpc and 12bpc.
1703                  */
1704                 val &= ~PIPECONF_BPC_MASK;
1705                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1706                         val |= PIPECONF_8BPC;
1707                 else
1708                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1709         }
1710
1711         val &= ~TRANS_INTERLACE_MASK;
1712         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1713                 if (HAS_PCH_IBX(dev_priv) &&
1714                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1715                         val |= TRANS_LEGACY_INTERLACED_ILK;
1716                 else
1717                         val |= TRANS_INTERLACED;
1718         } else {
1719                 val |= TRANS_PROGRESSIVE;
1720         }
1721
1722         I915_WRITE(reg, val | TRANS_ENABLE);
1723         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1724                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1725 }
1726
1727 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1728                                       enum transcoder cpu_transcoder)
1729 {
1730         u32 val, pipeconf_val;
1731
1732         /* FDI must be feeding us bits for PCH ports */
1733         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1734         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1735
1736         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1737         /* Workaround: set timing override bit. */
1738         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1739         /* Configure frame start delay to match the CPU */
1740         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1741         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1742         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1743
1744         val = TRANS_ENABLE;
1745         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1746
1747         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1748             PIPECONF_INTERLACED_ILK)
1749                 val |= TRANS_INTERLACED;
1750         else
1751                 val |= TRANS_PROGRESSIVE;
1752
1753         I915_WRITE(LPT_TRANSCONF, val);
1754         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1755                                   TRANS_STATE_ENABLE, 100))
1756                 DRM_ERROR("Failed to enable PCH transcoder\n");
1757 }
1758
1759 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1760                                             enum pipe pipe)
1761 {
1762         i915_reg_t reg;
1763         u32 val;
1764
1765         /* FDI relies on the transcoder */
1766         assert_fdi_tx_disabled(dev_priv, pipe);
1767         assert_fdi_rx_disabled(dev_priv, pipe);
1768
1769         /* Ports must be off as well */
1770         assert_pch_ports_disabled(dev_priv, pipe);
1771
1772         reg = PCH_TRANSCONF(pipe);
1773         val = I915_READ(reg);
1774         val &= ~TRANS_ENABLE;
1775         I915_WRITE(reg, val);
1776         /* wait for PCH transcoder off, transcoder state */
1777         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1778                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1779
1780         if (HAS_PCH_CPT(dev_priv)) {
1781                 /* Workaround: Clear the timing override chicken bit again. */
1782                 reg = TRANS_CHICKEN2(pipe);
1783                 val = I915_READ(reg);
1784                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1785                 I915_WRITE(reg, val);
1786         }
1787 }
1788
1789 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1790 {
1791         u32 val;
1792
1793         val = I915_READ(LPT_TRANSCONF);
1794         val &= ~TRANS_ENABLE;
1795         I915_WRITE(LPT_TRANSCONF, val);
1796         /* wait for PCH transcoder off, transcoder state */
1797         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1798                                     TRANS_STATE_ENABLE, 50))
1799                 DRM_ERROR("Failed to disable PCH transcoder\n");
1800
1801         /* Workaround: clear timing override bit. */
1802         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1803         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1804         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1805 }
1806
1807 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1808 {
1809         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1810
1811         if (HAS_PCH_LPT(dev_priv))
1812                 return PIPE_A;
1813         else
1814                 return crtc->pipe;
1815 }
1816
1817 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1818 {
1819         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1820
1821         /*
1822          * On i965gm the hardware frame counter reads
1823          * zero when the TV encoder is enabled :(
1824          */
1825         if (IS_I965GM(dev_priv) &&
1826             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1827                 return 0;
1828
1829         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1830                 return 0xffffffff; /* full 32 bit counter */
1831         else if (INTEL_GEN(dev_priv) >= 3)
1832                 return 0xffffff; /* only 24 bits of frame count */
1833         else
1834                 return 0; /* Gen2 doesn't have a hardware frame counter */
1835 }
1836
1837 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1838 {
1839         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1840
1841         assert_vblank_disabled(&crtc->base);
1842         drm_crtc_set_max_vblank_count(&crtc->base,
1843                                       intel_crtc_max_vblank_count(crtc_state));
1844         drm_crtc_vblank_on(&crtc->base);
1845 }
1846
1847 static void intel_crtc_vblank_off(struct intel_crtc *crtc)
1848 {
1849         drm_crtc_vblank_off(&crtc->base);
1850         assert_vblank_disabled(&crtc->base);
1851 }
1852
1853 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1854 {
1855         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1856         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1857         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1858         enum pipe pipe = crtc->pipe;
1859         i915_reg_t reg;
1860         u32 val;
1861
1862         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1863
1864         assert_planes_disabled(crtc);
1865
1866         /*
1867          * A pipe without a PLL won't actually be able to drive bits from
1868          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1869          * need the check.
1870          */
1871         if (HAS_GMCH(dev_priv)) {
1872                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1873                         assert_dsi_pll_enabled(dev_priv);
1874                 else
1875                         assert_pll_enabled(dev_priv, pipe);
1876         } else {
1877                 if (new_crtc_state->has_pch_encoder) {
1878                         /* if driving the PCH, we need FDI enabled */
1879                         assert_fdi_rx_pll_enabled(dev_priv,
1880                                                   intel_crtc_pch_transcoder(crtc));
1881                         assert_fdi_tx_pll_enabled(dev_priv,
1882                                                   (enum pipe) cpu_transcoder);
1883                 }
1884                 /* FIXME: assert CPU port conditions for SNB+ */
1885         }
1886
1887         trace_intel_pipe_enable(crtc);
1888
1889         reg = PIPECONF(cpu_transcoder);
1890         val = I915_READ(reg);
1891         if (val & PIPECONF_ENABLE) {
1892                 /* we keep both pipes enabled on 830 */
1893                 WARN_ON(!IS_I830(dev_priv));
1894                 return;
1895         }
1896
1897         I915_WRITE(reg, val | PIPECONF_ENABLE);
1898         POSTING_READ(reg);
1899
1900         /*
1901          * Until the pipe starts PIPEDSL reads will return a stale value,
1902          * which causes an apparent vblank timestamp jump when PIPEDSL
1903          * resets to its proper value. That also messes up the frame count
1904          * when it's derived from the timestamps. So let's wait for the
1905          * pipe to start properly before we call drm_crtc_vblank_on()
1906          */
1907         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1908                 intel_wait_for_pipe_scanline_moving(crtc);
1909 }
1910
1911 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1912 {
1913         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1914         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1915         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1916         enum pipe pipe = crtc->pipe;
1917         i915_reg_t reg;
1918         u32 val;
1919
1920         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1921
1922         /*
1923          * Make sure planes won't keep trying to pump pixels to us,
1924          * or we might hang the display.
1925          */
1926         assert_planes_disabled(crtc);
1927
1928         trace_intel_pipe_disable(crtc);
1929
1930         reg = PIPECONF(cpu_transcoder);
1931         val = I915_READ(reg);
1932         if ((val & PIPECONF_ENABLE) == 0)
1933                 return;
1934
1935         /*
1936          * Double wide has implications for planes
1937          * so best keep it disabled when not needed.
1938          */
1939         if (old_crtc_state->double_wide)
1940                 val &= ~PIPECONF_DOUBLE_WIDE;
1941
1942         /* Don't disable pipe or pipe PLLs if needed */
1943         if (!IS_I830(dev_priv))
1944                 val &= ~PIPECONF_ENABLE;
1945
1946         I915_WRITE(reg, val);
1947         if ((val & PIPECONF_ENABLE) == 0)
1948                 intel_wait_for_pipe_off(old_crtc_state);
1949 }
1950
1951 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1952 {
1953         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1954 }
1955
1956 static unsigned int
1957 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1958 {
1959         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1960         unsigned int cpp = fb->format->cpp[color_plane];
1961
1962         switch (fb->modifier) {
1963         case DRM_FORMAT_MOD_LINEAR:
1964                 return intel_tile_size(dev_priv);
1965         case I915_FORMAT_MOD_X_TILED:
1966                 if (IS_GEN(dev_priv, 2))
1967                         return 128;
1968                 else
1969                         return 512;
1970         case I915_FORMAT_MOD_Y_TILED_CCS:
1971                 if (color_plane == 1)
1972                         return 128;
1973                 /* fall through */
1974         case I915_FORMAT_MOD_Y_TILED:
1975                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1976                         return 128;
1977                 else
1978                         return 512;
1979         case I915_FORMAT_MOD_Yf_TILED_CCS:
1980                 if (color_plane == 1)
1981                         return 128;
1982                 /* fall through */
1983         case I915_FORMAT_MOD_Yf_TILED:
1984                 switch (cpp) {
1985                 case 1:
1986                         return 64;
1987                 case 2:
1988                 case 4:
1989                         return 128;
1990                 case 8:
1991                 case 16:
1992                         return 256;
1993                 default:
1994                         MISSING_CASE(cpp);
1995                         return cpp;
1996                 }
1997                 break;
1998         default:
1999                 MISSING_CASE(fb->modifier);
2000                 return cpp;
2001         }
2002 }
2003
2004 static unsigned int
2005 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2006 {
2007         return intel_tile_size(to_i915(fb->dev)) /
2008                 intel_tile_width_bytes(fb, color_plane);
2009 }
2010
2011 /* Return the tile dimensions in pixel units */
2012 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2013                             unsigned int *tile_width,
2014                             unsigned int *tile_height)
2015 {
2016         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2017         unsigned int cpp = fb->format->cpp[color_plane];
2018
2019         *tile_width = tile_width_bytes / cpp;
2020         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2021 }
2022
2023 unsigned int
2024 intel_fb_align_height(const struct drm_framebuffer *fb,
2025                       int color_plane, unsigned int height)
2026 {
2027         unsigned int tile_height = intel_tile_height(fb, color_plane);
2028
2029         return ALIGN(height, tile_height);
2030 }
2031
2032 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2033 {
2034         unsigned int size = 0;
2035         int i;
2036
2037         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2038                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2039
2040         return size;
2041 }
2042
2043 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2044 {
2045         unsigned int size = 0;
2046         int i;
2047
2048         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2049                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2050
2051         return size;
2052 }
2053
2054 static void
2055 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2056                         const struct drm_framebuffer *fb,
2057                         unsigned int rotation)
2058 {
2059         view->type = I915_GGTT_VIEW_NORMAL;
2060         if (drm_rotation_90_or_270(rotation)) {
2061                 view->type = I915_GGTT_VIEW_ROTATED;
2062                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2063         }
2064 }
2065
2066 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2067 {
2068         if (IS_I830(dev_priv))
2069                 return 16 * 1024;
2070         else if (IS_I85X(dev_priv))
2071                 return 256;
2072         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2073                 return 32;
2074         else
2075                 return 4 * 1024;
2076 }
2077
2078 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2079 {
2080         if (INTEL_GEN(dev_priv) >= 9)
2081                 return 256 * 1024;
2082         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2083                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2084                 return 128 * 1024;
2085         else if (INTEL_GEN(dev_priv) >= 4)
2086                 return 4 * 1024;
2087         else
2088                 return 0;
2089 }
2090
2091 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2092                                          int color_plane)
2093 {
2094         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2095
2096         /* AUX_DIST needs only 4K alignment */
2097         if (color_plane == 1)
2098                 return 4096;
2099
2100         switch (fb->modifier) {
2101         case DRM_FORMAT_MOD_LINEAR:
2102                 return intel_linear_alignment(dev_priv);
2103         case I915_FORMAT_MOD_X_TILED:
2104                 if (INTEL_GEN(dev_priv) >= 9)
2105                         return 256 * 1024;
2106                 return 0;
2107         case I915_FORMAT_MOD_Y_TILED_CCS:
2108         case I915_FORMAT_MOD_Yf_TILED_CCS:
2109         case I915_FORMAT_MOD_Y_TILED:
2110         case I915_FORMAT_MOD_Yf_TILED:
2111                 return 1 * 1024 * 1024;
2112         default:
2113                 MISSING_CASE(fb->modifier);
2114                 return 0;
2115         }
2116 }
2117
2118 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2119 {
2120         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2121         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2122
2123         return INTEL_GEN(dev_priv) < 4 ||
2124                 (plane->has_fbc &&
2125                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2126 }
2127
2128 struct i915_vma *
2129 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2130                            const struct i915_ggtt_view *view,
2131                            bool uses_fence,
2132                            unsigned long *out_flags)
2133 {
2134         struct drm_device *dev = fb->dev;
2135         struct drm_i915_private *dev_priv = to_i915(dev);
2136         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2137         intel_wakeref_t wakeref;
2138         struct i915_vma *vma;
2139         unsigned int pinctl;
2140         u32 alignment;
2141
2142         if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2143                 return ERR_PTR(-EINVAL);
2144
2145         alignment = intel_surf_alignment(fb, 0);
2146
2147         /* Note that the w/a also requires 64 PTE of padding following the
2148          * bo. We currently fill all unused PTE with the shadow page and so
2149          * we should always have valid PTE following the scanout preventing
2150          * the VT-d warning.
2151          */
2152         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2153                 alignment = 256 * 1024;
2154
2155         /*
2156          * Global gtt pte registers are special registers which actually forward
2157          * writes to a chunk of system memory. Which means that there is no risk
2158          * that the register values disappear as soon as we call
2159          * intel_runtime_pm_put(), so it is correct to wrap only the
2160          * pin/unpin/fence and not more.
2161          */
2162         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2163         i915_gem_object_lock(obj);
2164
2165         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2166
2167         pinctl = 0;
2168
2169         /* Valleyview is definitely limited to scanning out the first
2170          * 512MiB. Lets presume this behaviour was inherited from the
2171          * g4x display engine and that all earlier gen are similarly
2172          * limited. Testing suggests that it is a little more
2173          * complicated than this. For example, Cherryview appears quite
2174          * happy to scanout from anywhere within its global aperture.
2175          */
2176         if (HAS_GMCH(dev_priv))
2177                 pinctl |= PIN_MAPPABLE;
2178
2179         vma = i915_gem_object_pin_to_display_plane(obj,
2180                                                    alignment, view, pinctl);
2181         if (IS_ERR(vma))
2182                 goto err;
2183
2184         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2185                 int ret;
2186
2187                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2188                  * fence, whereas 965+ only requires a fence if using
2189                  * framebuffer compression.  For simplicity, we always, when
2190                  * possible, install a fence as the cost is not that onerous.
2191                  *
2192                  * If we fail to fence the tiled scanout, then either the
2193                  * modeset will reject the change (which is highly unlikely as
2194                  * the affected systems, all but one, do not have unmappable
2195                  * space) or we will not be able to enable full powersaving
2196                  * techniques (also likely not to apply due to various limits
2197                  * FBC and the like impose on the size of the buffer, which
2198                  * presumably we violated anyway with this unmappable buffer).
2199                  * Anyway, it is presumably better to stumble onwards with
2200                  * something and try to run the system in a "less than optimal"
2201                  * mode that matches the user configuration.
2202                  */
2203                 ret = i915_vma_pin_fence(vma);
2204                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2205                         i915_gem_object_unpin_from_display_plane(vma);
2206                         vma = ERR_PTR(ret);
2207                         goto err;
2208                 }
2209
2210                 if (ret == 0 && vma->fence)
2211                         *out_flags |= PLANE_HAS_FENCE;
2212         }
2213
2214         i915_vma_get(vma);
2215 err:
2216         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2217
2218         i915_gem_object_unlock(obj);
2219         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2220         return vma;
2221 }
2222
2223 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2224 {
2225         i915_gem_object_lock(vma->obj);
2226         if (flags & PLANE_HAS_FENCE)
2227                 i915_vma_unpin_fence(vma);
2228         i915_gem_object_unpin_from_display_plane(vma);
2229         i915_gem_object_unlock(vma->obj);
2230
2231         i915_vma_put(vma);
2232 }
2233
2234 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2235                           unsigned int rotation)
2236 {
2237         if (drm_rotation_90_or_270(rotation))
2238                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2239         else
2240                 return fb->pitches[color_plane];
2241 }
2242
2243 /*
2244  * Convert the x/y offsets into a linear offset.
2245  * Only valid with 0/180 degree rotation, which is fine since linear
2246  * offset is only used with linear buffers on pre-hsw and tiled buffers
2247  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2248  */
2249 u32 intel_fb_xy_to_linear(int x, int y,
2250                           const struct intel_plane_state *state,
2251                           int color_plane)
2252 {
2253         const struct drm_framebuffer *fb = state->hw.fb;
2254         unsigned int cpp = fb->format->cpp[color_plane];
2255         unsigned int pitch = state->color_plane[color_plane].stride;
2256
2257         return y * pitch + x * cpp;
2258 }
2259
2260 /*
2261  * Add the x/y offsets derived from fb->offsets[] to the user
2262  * specified plane src x/y offsets. The resulting x/y offsets
2263  * specify the start of scanout from the beginning of the gtt mapping.
2264  */
2265 void intel_add_fb_offsets(int *x, int *y,
2266                           const struct intel_plane_state *state,
2267                           int color_plane)
2268
2269 {
2270         *x += state->color_plane[color_plane].x;
2271         *y += state->color_plane[color_plane].y;
2272 }
2273
2274 static u32 intel_adjust_tile_offset(int *x, int *y,
2275                                     unsigned int tile_width,
2276                                     unsigned int tile_height,
2277                                     unsigned int tile_size,
2278                                     unsigned int pitch_tiles,
2279                                     u32 old_offset,
2280                                     u32 new_offset)
2281 {
2282         unsigned int pitch_pixels = pitch_tiles * tile_width;
2283         unsigned int tiles;
2284
2285         WARN_ON(old_offset & (tile_size - 1));
2286         WARN_ON(new_offset & (tile_size - 1));
2287         WARN_ON(new_offset > old_offset);
2288
2289         tiles = (old_offset - new_offset) / tile_size;
2290
2291         *y += tiles / pitch_tiles * tile_height;
2292         *x += tiles % pitch_tiles * tile_width;
2293
2294         /* minimize x in case it got needlessly big */
2295         *y += *x / pitch_pixels * tile_height;
2296         *x %= pitch_pixels;
2297
2298         return new_offset;
2299 }
2300
2301 static bool is_surface_linear(u64 modifier, int color_plane)
2302 {
2303         return modifier == DRM_FORMAT_MOD_LINEAR;
2304 }
2305
2306 static u32 intel_adjust_aligned_offset(int *x, int *y,
2307                                        const struct drm_framebuffer *fb,
2308                                        int color_plane,
2309                                        unsigned int rotation,
2310                                        unsigned int pitch,
2311                                        u32 old_offset, u32 new_offset)
2312 {
2313         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2314         unsigned int cpp = fb->format->cpp[color_plane];
2315
2316         WARN_ON(new_offset > old_offset);
2317
2318         if (!is_surface_linear(fb->modifier, color_plane)) {
2319                 unsigned int tile_size, tile_width, tile_height;
2320                 unsigned int pitch_tiles;
2321
2322                 tile_size = intel_tile_size(dev_priv);
2323                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2324
2325                 if (drm_rotation_90_or_270(rotation)) {
2326                         pitch_tiles = pitch / tile_height;
2327                         swap(tile_width, tile_height);
2328                 } else {
2329                         pitch_tiles = pitch / (tile_width * cpp);
2330                 }
2331
2332                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2333                                          tile_size, pitch_tiles,
2334                                          old_offset, new_offset);
2335         } else {
2336                 old_offset += *y * pitch + *x * cpp;
2337
2338                 *y = (old_offset - new_offset) / pitch;
2339                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2340         }
2341
2342         return new_offset;
2343 }
2344
2345 /*
2346  * Adjust the tile offset by moving the difference into
2347  * the x/y offsets.
2348  */
2349 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2350                                              const struct intel_plane_state *state,
2351                                              int color_plane,
2352                                              u32 old_offset, u32 new_offset)
2353 {
2354         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2355                                            state->hw.rotation,
2356                                            state->color_plane[color_plane].stride,
2357                                            old_offset, new_offset);
2358 }
2359
2360 /*
2361  * Computes the aligned offset to the base tile and adjusts
2362  * x, y. bytes per pixel is assumed to be a power-of-two.
2363  *
2364  * In the 90/270 rotated case, x and y are assumed
2365  * to be already rotated to match the rotated GTT view, and
2366  * pitch is the tile_height aligned framebuffer height.
2367  *
2368  * This function is used when computing the derived information
2369  * under intel_framebuffer, so using any of that information
2370  * here is not allowed. Anything under drm_framebuffer can be
2371  * used. This is why the user has to pass in the pitch since it
2372  * is specified in the rotated orientation.
2373  */
2374 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2375                                         int *x, int *y,
2376                                         const struct drm_framebuffer *fb,
2377                                         int color_plane,
2378                                         unsigned int pitch,
2379                                         unsigned int rotation,
2380                                         u32 alignment)
2381 {
2382         unsigned int cpp = fb->format->cpp[color_plane];
2383         u32 offset, offset_aligned;
2384
2385         if (alignment)
2386                 alignment--;
2387
2388         if (!is_surface_linear(fb->modifier, color_plane)) {
2389                 unsigned int tile_size, tile_width, tile_height;
2390                 unsigned int tile_rows, tiles, pitch_tiles;
2391
2392                 tile_size = intel_tile_size(dev_priv);
2393                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2394
2395                 if (drm_rotation_90_or_270(rotation)) {
2396                         pitch_tiles = pitch / tile_height;
2397                         swap(tile_width, tile_height);
2398                 } else {
2399                         pitch_tiles = pitch / (tile_width * cpp);
2400                 }
2401
2402                 tile_rows = *y / tile_height;
2403                 *y %= tile_height;
2404
2405                 tiles = *x / tile_width;
2406                 *x %= tile_width;
2407
2408                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2409                 offset_aligned = offset & ~alignment;
2410
2411                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2412                                          tile_size, pitch_tiles,
2413                                          offset, offset_aligned);
2414         } else {
2415                 offset = *y * pitch + *x * cpp;
2416                 offset_aligned = offset & ~alignment;
2417
2418                 *y = (offset & alignment) / pitch;
2419                 *x = ((offset & alignment) - *y * pitch) / cpp;
2420         }
2421
2422         return offset_aligned;
2423 }
2424
2425 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2426                                               const struct intel_plane_state *state,
2427                                               int color_plane)
2428 {
2429         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2430         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2431         const struct drm_framebuffer *fb = state->hw.fb;
2432         unsigned int rotation = state->hw.rotation;
2433         int pitch = state->color_plane[color_plane].stride;
2434         u32 alignment;
2435
2436         if (intel_plane->id == PLANE_CURSOR)
2437                 alignment = intel_cursor_alignment(dev_priv);
2438         else
2439                 alignment = intel_surf_alignment(fb, color_plane);
2440
2441         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2442                                             pitch, rotation, alignment);
2443 }
2444
2445 /* Convert the fb->offset[] into x/y offsets */
2446 static int intel_fb_offset_to_xy(int *x, int *y,
2447                                  const struct drm_framebuffer *fb,
2448                                  int color_plane)
2449 {
2450         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2451         unsigned int height;
2452
2453         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2454             fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2455                 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2456                               fb->offsets[color_plane], color_plane);
2457                 return -EINVAL;
2458         }
2459
2460         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2461         height = ALIGN(height, intel_tile_height(fb, color_plane));
2462
2463         /* Catch potential overflows early */
2464         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2465                             fb->offsets[color_plane])) {
2466                 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2467                               fb->offsets[color_plane], fb->pitches[color_plane],
2468                               color_plane);
2469                 return -ERANGE;
2470         }
2471
2472         *x = 0;
2473         *y = 0;
2474
2475         intel_adjust_aligned_offset(x, y,
2476                                     fb, color_plane, DRM_MODE_ROTATE_0,
2477                                     fb->pitches[color_plane],
2478                                     fb->offsets[color_plane], 0);
2479
2480         return 0;
2481 }
2482
2483 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2484 {
2485         switch (fb_modifier) {
2486         case I915_FORMAT_MOD_X_TILED:
2487                 return I915_TILING_X;
2488         case I915_FORMAT_MOD_Y_TILED:
2489         case I915_FORMAT_MOD_Y_TILED_CCS:
2490                 return I915_TILING_Y;
2491         default:
2492                 return I915_TILING_NONE;
2493         }
2494 }
2495
2496 /*
2497  * From the Sky Lake PRM:
2498  * "The Color Control Surface (CCS) contains the compression status of
2499  *  the cache-line pairs. The compression state of the cache-line pair
2500  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2501  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2502  *  cache-line-pairs. CCS is always Y tiled."
2503  *
2504  * Since cache line pairs refers to horizontally adjacent cache lines,
2505  * each cache line in the CCS corresponds to an area of 32x16 cache
2506  * lines on the main surface. Since each pixel is 4 bytes, this gives
2507  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2508  * main surface.
2509  */
2510 static const struct drm_format_info ccs_formats[] = {
2511         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2512           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2513         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2514           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2515         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2516           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2517         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2518           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2519 };
2520
2521 static const struct drm_format_info *
2522 lookup_format_info(const struct drm_format_info formats[],
2523                    int num_formats, u32 format)
2524 {
2525         int i;
2526
2527         for (i = 0; i < num_formats; i++) {
2528                 if (formats[i].format == format)
2529                         return &formats[i];
2530         }
2531
2532         return NULL;
2533 }
2534
2535 static const struct drm_format_info *
2536 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2537 {
2538         switch (cmd->modifier[0]) {
2539         case I915_FORMAT_MOD_Y_TILED_CCS:
2540         case I915_FORMAT_MOD_Yf_TILED_CCS:
2541                 return lookup_format_info(ccs_formats,
2542                                           ARRAY_SIZE(ccs_formats),
2543                                           cmd->pixel_format);
2544         default:
2545                 return NULL;
2546         }
2547 }
2548
2549 bool is_ccs_modifier(u64 modifier)
2550 {
2551         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2552                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2553 }
2554
2555 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2556                               u32 pixel_format, u64 modifier)
2557 {
2558         struct intel_crtc *crtc;
2559         struct intel_plane *plane;
2560
2561         /*
2562          * We assume the primary plane for pipe A has
2563          * the highest stride limits of them all.
2564          */
2565         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2566         if (!crtc)
2567                 return 0;
2568
2569         plane = to_intel_plane(crtc->base.primary);
2570
2571         return plane->max_stride(plane, pixel_format, modifier,
2572                                  DRM_MODE_ROTATE_0);
2573 }
2574
2575 static
2576 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2577                         u32 pixel_format, u64 modifier)
2578 {
2579         /*
2580          * Arbitrary limit for gen4+ chosen to match the
2581          * render engine max stride.
2582          *
2583          * The new CCS hash mode makes remapping impossible
2584          */
2585         if (!is_ccs_modifier(modifier)) {
2586                 if (INTEL_GEN(dev_priv) >= 7)
2587                         return 256*1024;
2588                 else if (INTEL_GEN(dev_priv) >= 4)
2589                         return 128*1024;
2590         }
2591
2592         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2593 }
2594
2595 static u32
2596 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2597 {
2598         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2599
2600         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2601                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2602                                                            fb->format->format,
2603                                                            fb->modifier);
2604
2605                 /*
2606                  * To make remapping with linear generally feasible
2607                  * we need the stride to be page aligned.
2608                  */
2609                 if (fb->pitches[color_plane] > max_stride)
2610                         return intel_tile_size(dev_priv);
2611                 else
2612                         return 64;
2613         } else {
2614                 return intel_tile_width_bytes(fb, color_plane);
2615         }
2616 }
2617
2618 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2619 {
2620         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2621         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2622         const struct drm_framebuffer *fb = plane_state->hw.fb;
2623         int i;
2624
2625         /* We don't want to deal with remapping with cursors */
2626         if (plane->id == PLANE_CURSOR)
2627                 return false;
2628
2629         /*
2630          * The display engine limits already match/exceed the
2631          * render engine limits, so not much point in remapping.
2632          * Would also need to deal with the fence POT alignment
2633          * and gen2 2KiB GTT tile size.
2634          */
2635         if (INTEL_GEN(dev_priv) < 4)
2636                 return false;
2637
2638         /*
2639          * The new CCS hash mode isn't compatible with remapping as
2640          * the virtual address of the pages affects the compressed data.
2641          */
2642         if (is_ccs_modifier(fb->modifier))
2643                 return false;
2644
2645         /* Linear needs a page aligned stride for remapping */
2646         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2647                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2648
2649                 for (i = 0; i < fb->format->num_planes; i++) {
2650                         if (fb->pitches[i] & alignment)
2651                                 return false;
2652                 }
2653         }
2654
2655         return true;
2656 }
2657
2658 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2659 {
2660         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2661         const struct drm_framebuffer *fb = plane_state->hw.fb;
2662         unsigned int rotation = plane_state->hw.rotation;
2663         u32 stride, max_stride;
2664
2665         /*
2666          * No remapping for invisible planes since we don't have
2667          * an actual source viewport to remap.
2668          */
2669         if (!plane_state->uapi.visible)
2670                 return false;
2671
2672         if (!intel_plane_can_remap(plane_state))
2673                 return false;
2674
2675         /*
2676          * FIXME: aux plane limits on gen9+ are
2677          * unclear in Bspec, for now no checking.
2678          */
2679         stride = intel_fb_pitch(fb, 0, rotation);
2680         max_stride = plane->max_stride(plane, fb->format->format,
2681                                        fb->modifier, rotation);
2682
2683         return stride > max_stride;
2684 }
2685
2686 static int
2687 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2688                    struct drm_framebuffer *fb)
2689 {
2690         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2691         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2692         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2693         u32 gtt_offset_rotated = 0;
2694         unsigned int max_size = 0;
2695         int i, num_planes = fb->format->num_planes;
2696         unsigned int tile_size = intel_tile_size(dev_priv);
2697
2698         for (i = 0; i < num_planes; i++) {
2699                 unsigned int width, height;
2700                 unsigned int cpp, size;
2701                 u32 offset;
2702                 int x, y;
2703                 int ret;
2704
2705                 cpp = fb->format->cpp[i];
2706                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2707                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2708
2709                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2710                 if (ret) {
2711                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2712                                       i, fb->offsets[i]);
2713                         return ret;
2714                 }
2715
2716                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2717                         int hsub = fb->format->hsub;
2718                         int vsub = fb->format->vsub;
2719                         int tile_width, tile_height;
2720                         int main_x, main_y;
2721                         int ccs_x, ccs_y;
2722
2723                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2724                         tile_width *= hsub;
2725                         tile_height *= vsub;
2726
2727                         ccs_x = (x * hsub) % tile_width;
2728                         ccs_y = (y * vsub) % tile_height;
2729                         main_x = intel_fb->normal[0].x % tile_width;
2730                         main_y = intel_fb->normal[0].y % tile_height;
2731
2732                         /*
2733                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2734                          * x/y offsets must match between CCS and the main surface.
2735                          */
2736                         if (main_x != ccs_x || main_y != ccs_y) {
2737                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2738                                               main_x, main_y,
2739                                               ccs_x, ccs_y,
2740                                               intel_fb->normal[0].x,
2741                                               intel_fb->normal[0].y,
2742                                               x, y);
2743                                 return -EINVAL;
2744                         }
2745                 }
2746
2747                 /*
2748                  * The fence (if used) is aligned to the start of the object
2749                  * so having the framebuffer wrap around across the edge of the
2750                  * fenced region doesn't really work. We have no API to configure
2751                  * the fence start offset within the object (nor could we probably
2752                  * on gen2/3). So it's just easier if we just require that the
2753                  * fb layout agrees with the fence layout. We already check that the
2754                  * fb stride matches the fence stride elsewhere.
2755                  */
2756                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2757                     (x + width) * cpp > fb->pitches[i]) {
2758                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2759                                       i, fb->offsets[i]);
2760                         return -EINVAL;
2761                 }
2762
2763                 /*
2764                  * First pixel of the framebuffer from
2765                  * the start of the normal gtt mapping.
2766                  */
2767                 intel_fb->normal[i].x = x;
2768                 intel_fb->normal[i].y = y;
2769
2770                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2771                                                       fb->pitches[i],
2772                                                       DRM_MODE_ROTATE_0,
2773                                                       tile_size);
2774                 offset /= tile_size;
2775
2776                 if (!is_surface_linear(fb->modifier, i)) {
2777                         unsigned int tile_width, tile_height;
2778                         unsigned int pitch_tiles;
2779                         struct drm_rect r;
2780
2781                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2782
2783                         rot_info->plane[i].offset = offset;
2784                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2785                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2786                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2787
2788                         intel_fb->rotated[i].pitch =
2789                                 rot_info->plane[i].height * tile_height;
2790
2791                         /* how many tiles does this plane need */
2792                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2793                         /*
2794                          * If the plane isn't horizontally tile aligned,
2795                          * we need one more tile.
2796                          */
2797                         if (x != 0)
2798                                 size++;
2799
2800                         /* rotate the x/y offsets to match the GTT view */
2801                         drm_rect_init(&r, x, y, width, height);
2802                         drm_rect_rotate(&r,
2803                                         rot_info->plane[i].width * tile_width,
2804                                         rot_info->plane[i].height * tile_height,
2805                                         DRM_MODE_ROTATE_270);
2806                         x = r.x1;
2807                         y = r.y1;
2808
2809                         /* rotate the tile dimensions to match the GTT view */
2810                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2811                         swap(tile_width, tile_height);
2812
2813                         /*
2814                          * We only keep the x/y offsets, so push all of the
2815                          * gtt offset into the x/y offsets.
2816                          */
2817                         intel_adjust_tile_offset(&x, &y,
2818                                                  tile_width, tile_height,
2819                                                  tile_size, pitch_tiles,
2820                                                  gtt_offset_rotated * tile_size, 0);
2821
2822                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2823
2824                         /*
2825                          * First pixel of the framebuffer from
2826                          * the start of the rotated gtt mapping.
2827                          */
2828                         intel_fb->rotated[i].x = x;
2829                         intel_fb->rotated[i].y = y;
2830                 } else {
2831                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2832                                             x * cpp, tile_size);
2833                 }
2834
2835                 /* how many tiles in total needed in the bo */
2836                 max_size = max(max_size, offset + size);
2837         }
2838
2839         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2840                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2841                               mul_u32_u32(max_size, tile_size), obj->base.size);
2842                 return -EINVAL;
2843         }
2844
2845         return 0;
2846 }
2847
2848 static void
2849 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2850 {
2851         struct drm_i915_private *dev_priv =
2852                 to_i915(plane_state->uapi.plane->dev);
2853         struct drm_framebuffer *fb = plane_state->hw.fb;
2854         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2855         struct intel_rotation_info *info = &plane_state->view.rotated;
2856         unsigned int rotation = plane_state->hw.rotation;
2857         int i, num_planes = fb->format->num_planes;
2858         unsigned int tile_size = intel_tile_size(dev_priv);
2859         unsigned int src_x, src_y;
2860         unsigned int src_w, src_h;
2861         u32 gtt_offset = 0;
2862
2863         memset(&plane_state->view, 0, sizeof(plane_state->view));
2864         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2865                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2866
2867         src_x = plane_state->uapi.src.x1 >> 16;
2868         src_y = plane_state->uapi.src.y1 >> 16;
2869         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2870         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2871
2872         WARN_ON(is_ccs_modifier(fb->modifier));
2873
2874         /* Make src coordinates relative to the viewport */
2875         drm_rect_translate(&plane_state->uapi.src,
2876                            -(src_x << 16), -(src_y << 16));
2877
2878         /* Rotate src coordinates to match rotated GTT view */
2879         if (drm_rotation_90_or_270(rotation))
2880                 drm_rect_rotate(&plane_state->uapi.src,
2881                                 src_w << 16, src_h << 16,
2882                                 DRM_MODE_ROTATE_270);
2883
2884         for (i = 0; i < num_planes; i++) {
2885                 unsigned int hsub = i ? fb->format->hsub : 1;
2886                 unsigned int vsub = i ? fb->format->vsub : 1;
2887                 unsigned int cpp = fb->format->cpp[i];
2888                 unsigned int tile_width, tile_height;
2889                 unsigned int width, height;
2890                 unsigned int pitch_tiles;
2891                 unsigned int x, y;
2892                 u32 offset;
2893
2894                 intel_tile_dims(fb, i, &tile_width, &tile_height);
2895
2896                 x = src_x / hsub;
2897                 y = src_y / vsub;
2898                 width = src_w / hsub;
2899                 height = src_h / vsub;
2900
2901                 /*
2902                  * First pixel of the src viewport from the
2903                  * start of the normal gtt mapping.
2904                  */
2905                 x += intel_fb->normal[i].x;
2906                 y += intel_fb->normal[i].y;
2907
2908                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2909                                                       fb, i, fb->pitches[i],
2910                                                       DRM_MODE_ROTATE_0, tile_size);
2911                 offset /= tile_size;
2912
2913                 info->plane[i].offset = offset;
2914                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2915                                                      tile_width * cpp);
2916                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2917                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2918
2919                 if (drm_rotation_90_or_270(rotation)) {
2920                         struct drm_rect r;
2921
2922                         /* rotate the x/y offsets to match the GTT view */
2923                         drm_rect_init(&r, x, y, width, height);
2924                         drm_rect_rotate(&r,
2925                                         info->plane[i].width * tile_width,
2926                                         info->plane[i].height * tile_height,
2927                                         DRM_MODE_ROTATE_270);
2928                         x = r.x1;
2929                         y = r.y1;
2930
2931                         pitch_tiles = info->plane[i].height;
2932                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2933
2934                         /* rotate the tile dimensions to match the GTT view */
2935                         swap(tile_width, tile_height);
2936                 } else {
2937                         pitch_tiles = info->plane[i].width;
2938                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2939                 }
2940
2941                 /*
2942                  * We only keep the x/y offsets, so push all of the
2943                  * gtt offset into the x/y offsets.
2944                  */
2945                 intel_adjust_tile_offset(&x, &y,
2946                                          tile_width, tile_height,
2947                                          tile_size, pitch_tiles,
2948                                          gtt_offset * tile_size, 0);
2949
2950                 gtt_offset += info->plane[i].width * info->plane[i].height;
2951
2952                 plane_state->color_plane[i].offset = 0;
2953                 plane_state->color_plane[i].x = x;
2954                 plane_state->color_plane[i].y = y;
2955         }
2956 }
2957
2958 static int
2959 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2960 {
2961         const struct intel_framebuffer *fb =
2962                 to_intel_framebuffer(plane_state->hw.fb);
2963         unsigned int rotation = plane_state->hw.rotation;
2964         int i, num_planes;
2965
2966         if (!fb)
2967                 return 0;
2968
2969         num_planes = fb->base.format->num_planes;
2970
2971         if (intel_plane_needs_remap(plane_state)) {
2972                 intel_plane_remap_gtt(plane_state);
2973
2974                 /*
2975                  * Sometimes even remapping can't overcome
2976                  * the stride limitations :( Can happen with
2977                  * big plane sizes and suitably misaligned
2978                  * offsets.
2979                  */
2980                 return intel_plane_check_stride(plane_state);
2981         }
2982
2983         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2984
2985         for (i = 0; i < num_planes; i++) {
2986                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2987                 plane_state->color_plane[i].offset = 0;
2988
2989                 if (drm_rotation_90_or_270(rotation)) {
2990                         plane_state->color_plane[i].x = fb->rotated[i].x;
2991                         plane_state->color_plane[i].y = fb->rotated[i].y;
2992                 } else {
2993                         plane_state->color_plane[i].x = fb->normal[i].x;
2994                         plane_state->color_plane[i].y = fb->normal[i].y;
2995                 }
2996         }
2997
2998         /* Rotate src coordinates to match rotated GTT view */
2999         if (drm_rotation_90_or_270(rotation))
3000                 drm_rect_rotate(&plane_state->uapi.src,
3001                                 fb->base.width << 16, fb->base.height << 16,
3002                                 DRM_MODE_ROTATE_270);
3003
3004         return intel_plane_check_stride(plane_state);
3005 }
3006
3007 static int i9xx_format_to_fourcc(int format)
3008 {
3009         switch (format) {
3010         case DISPPLANE_8BPP:
3011                 return DRM_FORMAT_C8;
3012         case DISPPLANE_BGRA555:
3013                 return DRM_FORMAT_ARGB1555;
3014         case DISPPLANE_BGRX555:
3015                 return DRM_FORMAT_XRGB1555;
3016         case DISPPLANE_BGRX565:
3017                 return DRM_FORMAT_RGB565;
3018         default:
3019         case DISPPLANE_BGRX888:
3020                 return DRM_FORMAT_XRGB8888;
3021         case DISPPLANE_RGBX888:
3022                 return DRM_FORMAT_XBGR8888;
3023         case DISPPLANE_BGRA888:
3024                 return DRM_FORMAT_ARGB8888;
3025         case DISPPLANE_RGBA888:
3026                 return DRM_FORMAT_ABGR8888;
3027         case DISPPLANE_BGRX101010:
3028                 return DRM_FORMAT_XRGB2101010;
3029         case DISPPLANE_RGBX101010:
3030                 return DRM_FORMAT_XBGR2101010;
3031         case DISPPLANE_BGRA101010:
3032                 return DRM_FORMAT_ARGB2101010;
3033         case DISPPLANE_RGBA101010:
3034                 return DRM_FORMAT_ABGR2101010;
3035         case DISPPLANE_RGBX161616:
3036                 return DRM_FORMAT_XBGR16161616F;
3037         }
3038 }
3039
3040 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3041 {
3042         switch (format) {
3043         case PLANE_CTL_FORMAT_RGB_565:
3044                 return DRM_FORMAT_RGB565;
3045         case PLANE_CTL_FORMAT_NV12:
3046                 return DRM_FORMAT_NV12;
3047         case PLANE_CTL_FORMAT_P010:
3048                 return DRM_FORMAT_P010;
3049         case PLANE_CTL_FORMAT_P012:
3050                 return DRM_FORMAT_P012;
3051         case PLANE_CTL_FORMAT_P016:
3052                 return DRM_FORMAT_P016;
3053         case PLANE_CTL_FORMAT_Y210:
3054                 return DRM_FORMAT_Y210;
3055         case PLANE_CTL_FORMAT_Y212:
3056                 return DRM_FORMAT_Y212;
3057         case PLANE_CTL_FORMAT_Y216:
3058                 return DRM_FORMAT_Y216;
3059         case PLANE_CTL_FORMAT_Y410:
3060                 return DRM_FORMAT_XVYU2101010;
3061         case PLANE_CTL_FORMAT_Y412:
3062                 return DRM_FORMAT_XVYU12_16161616;
3063         case PLANE_CTL_FORMAT_Y416:
3064                 return DRM_FORMAT_XVYU16161616;
3065         default:
3066         case PLANE_CTL_FORMAT_XRGB_8888:
3067                 if (rgb_order) {
3068                         if (alpha)
3069                                 return DRM_FORMAT_ABGR8888;
3070                         else
3071                                 return DRM_FORMAT_XBGR8888;
3072                 } else {
3073                         if (alpha)
3074                                 return DRM_FORMAT_ARGB8888;
3075                         else
3076                                 return DRM_FORMAT_XRGB8888;
3077                 }
3078         case PLANE_CTL_FORMAT_XRGB_2101010:
3079                 if (rgb_order) {
3080                         if (alpha)
3081                                 return DRM_FORMAT_ABGR2101010;
3082                         else
3083                                 return DRM_FORMAT_XBGR2101010;
3084                 } else {
3085                         if (alpha)
3086                                 return DRM_FORMAT_ARGB2101010;
3087                         else
3088                                 return DRM_FORMAT_XRGB2101010;
3089                 }
3090         case PLANE_CTL_FORMAT_XRGB_16161616F:
3091                 if (rgb_order) {
3092                         if (alpha)
3093                                 return DRM_FORMAT_ABGR16161616F;
3094                         else
3095                                 return DRM_FORMAT_XBGR16161616F;
3096                 } else {
3097                         if (alpha)
3098                                 return DRM_FORMAT_ARGB16161616F;
3099                         else
3100                                 return DRM_FORMAT_XRGB16161616F;
3101                 }
3102         }
3103 }
3104
3105 static bool
3106 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3107                               struct intel_initial_plane_config *plane_config)
3108 {
3109         struct drm_device *dev = crtc->base.dev;
3110         struct drm_i915_private *dev_priv = to_i915(dev);
3111         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3112         struct drm_framebuffer *fb = &plane_config->fb->base;
3113         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3114         u32 size_aligned = round_up(plane_config->base + plane_config->size,
3115                                     PAGE_SIZE);
3116         struct drm_i915_gem_object *obj;
3117         bool ret = false;
3118
3119         size_aligned -= base_aligned;
3120
3121         if (plane_config->size == 0)
3122                 return false;
3123
3124         /* If the FB is too big, just don't use it since fbdev is not very
3125          * important and we should probably use that space with FBC or other
3126          * features. */
3127         if (size_aligned * 2 > dev_priv->stolen_usable_size)
3128                 return false;
3129
3130         switch (fb->modifier) {
3131         case DRM_FORMAT_MOD_LINEAR:
3132         case I915_FORMAT_MOD_X_TILED:
3133         case I915_FORMAT_MOD_Y_TILED:
3134                 break;
3135         default:
3136                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3137                                  fb->modifier);
3138                 return false;
3139         }
3140
3141         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3142                                                              base_aligned,
3143                                                              base_aligned,
3144                                                              size_aligned);
3145         if (IS_ERR(obj))
3146                 return false;
3147
3148         switch (plane_config->tiling) {
3149         case I915_TILING_NONE:
3150                 break;
3151         case I915_TILING_X:
3152         case I915_TILING_Y:
3153                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3154                 break;
3155         default:
3156                 MISSING_CASE(plane_config->tiling);
3157                 goto out;
3158         }
3159
3160         mode_cmd.pixel_format = fb->format->format;
3161         mode_cmd.width = fb->width;
3162         mode_cmd.height = fb->height;
3163         mode_cmd.pitches[0] = fb->pitches[0];
3164         mode_cmd.modifier[0] = fb->modifier;
3165         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3166
3167         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3168                 DRM_DEBUG_KMS("intel fb init failed\n");
3169                 goto out;
3170         }
3171
3172
3173         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3174         ret = true;
3175 out:
3176         i915_gem_object_put(obj);
3177         return ret;
3178 }
3179
3180 static void
3181 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3182                         struct intel_plane_state *plane_state,
3183                         bool visible)
3184 {
3185         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3186
3187         plane_state->uapi.visible = visible;
3188
3189         if (visible)
3190                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3191         else
3192                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3193 }
3194
3195 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3196 {
3197         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3198         struct drm_plane *plane;
3199
3200         /*
3201          * Active_planes aliases if multiple "primary" or cursor planes
3202          * have been used on the same (or wrong) pipe. plane_mask uses
3203          * unique ids, hence we can use that to reconstruct active_planes.
3204          */
3205         crtc_state->active_planes = 0;
3206
3207         drm_for_each_plane_mask(plane, &dev_priv->drm,
3208                                 crtc_state->uapi.plane_mask)
3209                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3210 }
3211
3212 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3213                                          struct intel_plane *plane)
3214 {
3215         struct intel_crtc_state *crtc_state =
3216                 to_intel_crtc_state(crtc->base.state);
3217         struct intel_plane_state *plane_state =
3218                 to_intel_plane_state(plane->base.state);
3219
3220         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3221                       plane->base.base.id, plane->base.name,
3222                       crtc->base.base.id, crtc->base.name);
3223
3224         intel_set_plane_visible(crtc_state, plane_state, false);
3225         fixup_active_planes(crtc_state);
3226         crtc_state->data_rate[plane->id] = 0;
3227         crtc_state->min_cdclk[plane->id] = 0;
3228
3229         if (plane->id == PLANE_PRIMARY)
3230                 intel_pre_disable_primary_noatomic(&crtc->base);
3231
3232         intel_disable_plane(plane, crtc_state);
3233 }
3234
3235 static struct intel_frontbuffer *
3236 to_intel_frontbuffer(struct drm_framebuffer *fb)
3237 {
3238         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3239 }
3240
3241 static void
3242 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3243                              struct intel_initial_plane_config *plane_config)
3244 {
3245         struct drm_device *dev = intel_crtc->base.dev;
3246         struct drm_i915_private *dev_priv = to_i915(dev);
3247         struct drm_crtc *c;
3248         struct drm_plane *primary = intel_crtc->base.primary;
3249         struct drm_plane_state *plane_state = primary->state;
3250         struct intel_plane *intel_plane = to_intel_plane(primary);
3251         struct intel_plane_state *intel_state =
3252                 to_intel_plane_state(plane_state);
3253         struct drm_framebuffer *fb;
3254
3255         if (!plane_config->fb)
3256                 return;
3257
3258         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3259                 fb = &plane_config->fb->base;
3260                 goto valid_fb;
3261         }
3262
3263         kfree(plane_config->fb);
3264
3265         /*
3266          * Failed to alloc the obj, check to see if we should share
3267          * an fb with another CRTC instead
3268          */
3269         for_each_crtc(dev, c) {
3270                 struct intel_plane_state *state;
3271
3272                 if (c == &intel_crtc->base)
3273                         continue;
3274
3275                 if (!to_intel_crtc(c)->active)
3276                         continue;
3277
3278                 state = to_intel_plane_state(c->primary->state);
3279                 if (!state->vma)
3280                         continue;
3281
3282                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3283                         fb = state->hw.fb;
3284                         drm_framebuffer_get(fb);
3285                         goto valid_fb;
3286                 }
3287         }
3288
3289         /*
3290          * We've failed to reconstruct the BIOS FB.  Current display state
3291          * indicates that the primary plane is visible, but has a NULL FB,
3292          * which will lead to problems later if we don't fix it up.  The
3293          * simplest solution is to just disable the primary plane now and
3294          * pretend the BIOS never had it enabled.
3295          */
3296         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3297
3298         return;
3299
3300 valid_fb:
3301         intel_state->hw.rotation = plane_config->rotation;
3302         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3303                                 intel_state->hw.rotation);
3304         intel_state->color_plane[0].stride =
3305                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3306
3307         intel_state->vma =
3308                 intel_pin_and_fence_fb_obj(fb,
3309                                            &intel_state->view,
3310                                            intel_plane_uses_fence(intel_state),
3311                                            &intel_state->flags);
3312         if (IS_ERR(intel_state->vma)) {
3313                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3314                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
3315
3316                 intel_state->vma = NULL;
3317                 drm_framebuffer_put(fb);
3318                 return;
3319         }
3320
3321         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3322
3323         plane_state->src_x = 0;
3324         plane_state->src_y = 0;
3325         plane_state->src_w = fb->width << 16;
3326         plane_state->src_h = fb->height << 16;
3327
3328         plane_state->crtc_x = 0;
3329         plane_state->crtc_y = 0;
3330         plane_state->crtc_w = fb->width;
3331         plane_state->crtc_h = fb->height;
3332
3333         intel_state->uapi.src = drm_plane_state_src(plane_state);
3334         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3335
3336         if (plane_config->tiling)
3337                 dev_priv->preserve_bios_swizzle = true;
3338
3339         plane_state->fb = fb;
3340         plane_state->crtc = &intel_crtc->base;
3341         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3342
3343         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3344                   &to_intel_frontbuffer(fb)->bits);
3345 }
3346
3347 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3348                                int color_plane,
3349                                unsigned int rotation)
3350 {
3351         int cpp = fb->format->cpp[color_plane];
3352
3353         switch (fb->modifier) {
3354         case DRM_FORMAT_MOD_LINEAR:
3355         case I915_FORMAT_MOD_X_TILED:
3356                 /*
3357                  * Validated limit is 4k, but has 5k should
3358                  * work apart from the following features:
3359                  * - Ytile (already limited to 4k)
3360                  * - FP16 (already limited to 4k)
3361                  * - render compression (already limited to 4k)
3362                  * - KVMR sprite and cursor (don't care)
3363                  * - horizontal panning (TODO verify this)
3364                  * - pipe and plane scaling (TODO verify this)
3365                  */
3366                 if (cpp == 8)
3367                         return 4096;
3368                 else
3369                         return 5120;
3370         case I915_FORMAT_MOD_Y_TILED_CCS:
3371         case I915_FORMAT_MOD_Yf_TILED_CCS:
3372                 /* FIXME AUX plane? */
3373         case I915_FORMAT_MOD_Y_TILED:
3374         case I915_FORMAT_MOD_Yf_TILED:
3375                 if (cpp == 8)
3376                         return 2048;
3377                 else
3378                         return 4096;
3379         default:
3380                 MISSING_CASE(fb->modifier);
3381                 return 2048;
3382         }
3383 }
3384
3385 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3386                                int color_plane,
3387                                unsigned int rotation)
3388 {
3389         int cpp = fb->format->cpp[color_plane];
3390
3391         switch (fb->modifier) {
3392         case DRM_FORMAT_MOD_LINEAR:
3393         case I915_FORMAT_MOD_X_TILED:
3394                 if (cpp == 8)
3395                         return 4096;
3396                 else
3397                         return 5120;
3398         case I915_FORMAT_MOD_Y_TILED_CCS:
3399         case I915_FORMAT_MOD_Yf_TILED_CCS:
3400                 /* FIXME AUX plane? */
3401         case I915_FORMAT_MOD_Y_TILED:
3402         case I915_FORMAT_MOD_Yf_TILED:
3403                 if (cpp == 8)
3404                         return 2048;
3405                 else
3406                         return 5120;
3407         default:
3408                 MISSING_CASE(fb->modifier);
3409                 return 2048;
3410         }
3411 }
3412
3413 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3414                                int color_plane,
3415                                unsigned int rotation)
3416 {
3417         return 5120;
3418 }
3419
3420 static int skl_max_plane_height(void)
3421 {
3422         return 4096;
3423 }
3424
3425 static int icl_max_plane_height(void)
3426 {
3427         return 4320;
3428 }
3429
3430 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3431                                            int main_x, int main_y, u32 main_offset)
3432 {
3433         const struct drm_framebuffer *fb = plane_state->hw.fb;
3434         int hsub = fb->format->hsub;
3435         int vsub = fb->format->vsub;
3436         int aux_x = plane_state->color_plane[1].x;
3437         int aux_y = plane_state->color_plane[1].y;
3438         u32 aux_offset = plane_state->color_plane[1].offset;
3439         u32 alignment = intel_surf_alignment(fb, 1);
3440
3441         while (aux_offset >= main_offset && aux_y <= main_y) {
3442                 int x, y;
3443
3444                 if (aux_x == main_x && aux_y == main_y)
3445                         break;
3446
3447                 if (aux_offset == 0)
3448                         break;
3449
3450                 x = aux_x / hsub;
3451                 y = aux_y / vsub;
3452                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3453                                                                aux_offset, aux_offset - alignment);
3454                 aux_x = x * hsub + aux_x % hsub;
3455                 aux_y = y * vsub + aux_y % vsub;
3456         }
3457
3458         if (aux_x != main_x || aux_y != main_y)
3459                 return false;
3460
3461         plane_state->color_plane[1].offset = aux_offset;
3462         plane_state->color_plane[1].x = aux_x;
3463         plane_state->color_plane[1].y = aux_y;
3464
3465         return true;
3466 }
3467
3468 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3469 {
3470         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3471         const struct drm_framebuffer *fb = plane_state->hw.fb;
3472         unsigned int rotation = plane_state->hw.rotation;
3473         int x = plane_state->uapi.src.x1 >> 16;
3474         int y = plane_state->uapi.src.y1 >> 16;
3475         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3476         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3477         int max_width;
3478         int max_height;
3479         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3480
3481         if (INTEL_GEN(dev_priv) >= 11)
3482                 max_width = icl_max_plane_width(fb, 0, rotation);
3483         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3484                 max_width = glk_max_plane_width(fb, 0, rotation);
3485         else
3486                 max_width = skl_max_plane_width(fb, 0, rotation);
3487
3488         if (INTEL_GEN(dev_priv) >= 11)
3489                 max_height = icl_max_plane_height();
3490         else
3491                 max_height = skl_max_plane_height();
3492
3493         if (w > max_width || h > max_height) {
3494                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3495                               w, h, max_width, max_height);
3496                 return -EINVAL;
3497         }
3498
3499         intel_add_fb_offsets(&x, &y, plane_state, 0);
3500         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3501         alignment = intel_surf_alignment(fb, 0);
3502
3503         /*
3504          * AUX surface offset is specified as the distance from the
3505          * main surface offset, and it must be non-negative. Make
3506          * sure that is what we will get.
3507          */
3508         if (offset > aux_offset)
3509                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3510                                                            offset, aux_offset & ~(alignment - 1));
3511
3512         /*
3513          * When using an X-tiled surface, the plane blows up
3514          * if the x offset + width exceed the stride.
3515          *
3516          * TODO: linear and Y-tiled seem fine, Yf untested,
3517          */
3518         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3519                 int cpp = fb->format->cpp[0];
3520
3521                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3522                         if (offset == 0) {
3523                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3524                                 return -EINVAL;
3525                         }
3526
3527                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3528                                                                    offset, offset - alignment);
3529                 }
3530         }
3531
3532         /*
3533          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3534          * they match with the main surface x/y offsets.
3535          */
3536         if (is_ccs_modifier(fb->modifier)) {
3537                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3538                         if (offset == 0)
3539                                 break;
3540
3541                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3542                                                                    offset, offset - alignment);
3543                 }
3544
3545                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3546                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3547                         return -EINVAL;
3548                 }
3549         }
3550
3551         plane_state->color_plane[0].offset = offset;
3552         plane_state->color_plane[0].x = x;
3553         plane_state->color_plane[0].y = y;
3554
3555         /*
3556          * Put the final coordinates back so that the src
3557          * coordinate checks will see the right values.
3558          */
3559         drm_rect_translate_to(&plane_state->uapi.src,
3560                               x << 16, y << 16);
3561
3562         return 0;
3563 }
3564
3565 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3566 {
3567         const struct drm_framebuffer *fb = plane_state->hw.fb;
3568         unsigned int rotation = plane_state->hw.rotation;
3569         int max_width = skl_max_plane_width(fb, 1, rotation);
3570         int max_height = 4096;
3571         int x = plane_state->uapi.src.x1 >> 17;
3572         int y = plane_state->uapi.src.y1 >> 17;
3573         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3574         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3575         u32 offset;
3576
3577         intel_add_fb_offsets(&x, &y, plane_state, 1);
3578         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3579
3580         /* FIXME not quite sure how/if these apply to the chroma plane */
3581         if (w > max_width || h > max_height) {
3582                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3583                               w, h, max_width, max_height);
3584                 return -EINVAL;
3585         }
3586
3587         plane_state->color_plane[1].offset = offset;
3588         plane_state->color_plane[1].x = x;
3589         plane_state->color_plane[1].y = y;
3590
3591         return 0;
3592 }
3593
3594 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3595 {
3596         const struct drm_framebuffer *fb = plane_state->hw.fb;
3597         int src_x = plane_state->uapi.src.x1 >> 16;
3598         int src_y = plane_state->uapi.src.y1 >> 16;
3599         int hsub = fb->format->hsub;
3600         int vsub = fb->format->vsub;
3601         int x = src_x / hsub;
3602         int y = src_y / vsub;
3603         u32 offset;
3604
3605         intel_add_fb_offsets(&x, &y, plane_state, 1);
3606         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3607
3608         plane_state->color_plane[1].offset = offset;
3609         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3610         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3611
3612         return 0;
3613 }
3614
3615 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3616 {
3617         const struct drm_framebuffer *fb = plane_state->hw.fb;
3618         int ret;
3619
3620         ret = intel_plane_compute_gtt(plane_state);
3621         if (ret)
3622                 return ret;
3623
3624         if (!plane_state->uapi.visible)
3625                 return 0;
3626
3627         /*
3628          * Handle the AUX surface first since
3629          * the main surface setup depends on it.
3630          */
3631         if (drm_format_info_is_yuv_semiplanar(fb->format)) {
3632                 ret = skl_check_nv12_aux_surface(plane_state);
3633                 if (ret)
3634                         return ret;
3635         } else if (is_ccs_modifier(fb->modifier)) {
3636                 ret = skl_check_ccs_aux_surface(plane_state);
3637                 if (ret)
3638                         return ret;
3639         } else {
3640                 plane_state->color_plane[1].offset = ~0xfff;
3641                 plane_state->color_plane[1].x = 0;
3642                 plane_state->color_plane[1].y = 0;
3643         }
3644
3645         ret = skl_check_main_surface(plane_state);
3646         if (ret)
3647                 return ret;
3648
3649         return 0;
3650 }
3651
3652 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
3653                              const struct intel_plane_state *plane_state,
3654                              unsigned int *num, unsigned int *den)
3655 {
3656         const struct drm_framebuffer *fb = plane_state->hw.fb;
3657         unsigned int cpp = fb->format->cpp[0];
3658
3659         /*
3660          * g4x bspec says 64bpp pixel rate can't exceed 80%
3661          * of cdclk when the sprite plane is enabled on the
3662          * same pipe. ilk/snb bspec says 64bpp pixel rate is
3663          * never allowed to exceed 80% of cdclk. Let's just go
3664          * with the ilk/snb limit always.
3665          */
3666         if (cpp == 8) {
3667                 *num = 10;
3668                 *den = 8;
3669         } else {
3670                 *num = 1;
3671                 *den = 1;
3672         }
3673 }
3674
3675 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
3676                                 const struct intel_plane_state *plane_state)
3677 {
3678         unsigned int pixel_rate;
3679         unsigned int num, den;
3680
3681         /*
3682          * Note that crtc_state->pixel_rate accounts for both
3683          * horizontal and vertical panel fitter downscaling factors.
3684          * Pre-HSW bspec tells us to only consider the horizontal
3685          * downscaling factor here. We ignore that and just consider
3686          * both for simplicity.
3687          */
3688         pixel_rate = crtc_state->pixel_rate;
3689
3690         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
3691
3692         /* two pixels per clock with double wide pipe */
3693         if (crtc_state->double_wide)
3694                 den *= 2;
3695
3696         return DIV_ROUND_UP(pixel_rate * num, den);
3697 }
3698
3699 unsigned int
3700 i9xx_plane_max_stride(struct intel_plane *plane,
3701                       u32 pixel_format, u64 modifier,
3702                       unsigned int rotation)
3703 {
3704         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3705
3706         if (!HAS_GMCH(dev_priv)) {
3707                 return 32*1024;
3708         } else if (INTEL_GEN(dev_priv) >= 4) {
3709                 if (modifier == I915_FORMAT_MOD_X_TILED)
3710                         return 16*1024;
3711                 else
3712                         return 32*1024;
3713         } else if (INTEL_GEN(dev_priv) >= 3) {
3714                 if (modifier == I915_FORMAT_MOD_X_TILED)
3715                         return 8*1024;
3716                 else
3717                         return 16*1024;
3718         } else {
3719                 if (plane->i9xx_plane == PLANE_C)
3720                         return 4*1024;
3721                 else
3722                         return 8*1024;
3723         }
3724 }
3725
3726 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3727 {
3728         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3729         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3730         u32 dspcntr = 0;
3731
3732         if (crtc_state->gamma_enable)
3733                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3734
3735         if (crtc_state->csc_enable)
3736                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3737
3738         if (INTEL_GEN(dev_priv) < 5)
3739                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3740
3741         return dspcntr;
3742 }
3743
3744 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3745                           const struct intel_plane_state *plane_state)
3746 {
3747         struct drm_i915_private *dev_priv =
3748                 to_i915(plane_state->uapi.plane->dev);
3749         const struct drm_framebuffer *fb = plane_state->hw.fb;
3750         unsigned int rotation = plane_state->hw.rotation;
3751         u32 dspcntr;
3752
3753         dspcntr = DISPLAY_PLANE_ENABLE;
3754
3755         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3756             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3757                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3758
3759         switch (fb->format->format) {
3760         case DRM_FORMAT_C8:
3761                 dspcntr |= DISPPLANE_8BPP;
3762                 break;
3763         case DRM_FORMAT_XRGB1555:
3764                 dspcntr |= DISPPLANE_BGRX555;
3765                 break;
3766         case DRM_FORMAT_ARGB1555:
3767                 dspcntr |= DISPPLANE_BGRA555;
3768                 break;
3769         case DRM_FORMAT_RGB565:
3770                 dspcntr |= DISPPLANE_BGRX565;
3771                 break;
3772         case DRM_FORMAT_XRGB8888:
3773                 dspcntr |= DISPPLANE_BGRX888;
3774                 break;
3775         case DRM_FORMAT_XBGR8888:
3776                 dspcntr |= DISPPLANE_RGBX888;
3777                 break;
3778         case DRM_FORMAT_ARGB8888:
3779                 dspcntr |= DISPPLANE_BGRA888;
3780                 break;
3781         case DRM_FORMAT_ABGR8888:
3782                 dspcntr |= DISPPLANE_RGBA888;
3783                 break;
3784         case DRM_FORMAT_XRGB2101010:
3785                 dspcntr |= DISPPLANE_BGRX101010;
3786                 break;
3787         case DRM_FORMAT_XBGR2101010:
3788                 dspcntr |= DISPPLANE_RGBX101010;
3789                 break;
3790         case DRM_FORMAT_ARGB2101010:
3791                 dspcntr |= DISPPLANE_BGRA101010;
3792                 break;
3793         case DRM_FORMAT_ABGR2101010:
3794                 dspcntr |= DISPPLANE_RGBA101010;
3795                 break;
3796         case DRM_FORMAT_XBGR16161616F:
3797                 dspcntr |= DISPPLANE_RGBX161616;
3798                 break;
3799         default:
3800                 MISSING_CASE(fb->format->format);
3801                 return 0;
3802         }
3803
3804         if (INTEL_GEN(dev_priv) >= 4 &&
3805             fb->modifier == I915_FORMAT_MOD_X_TILED)
3806                 dspcntr |= DISPPLANE_TILED;
3807
3808         if (rotation & DRM_MODE_ROTATE_180)
3809                 dspcntr |= DISPPLANE_ROTATE_180;
3810
3811         if (rotation & DRM_MODE_REFLECT_X)
3812                 dspcntr |= DISPPLANE_MIRROR;
3813
3814         return dspcntr;
3815 }
3816
3817 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3818 {
3819         struct drm_i915_private *dev_priv =
3820                 to_i915(plane_state->uapi.plane->dev);
3821         const struct drm_framebuffer *fb = plane_state->hw.fb;
3822         int src_x, src_y, src_w;
3823         u32 offset;
3824         int ret;
3825
3826         ret = intel_plane_compute_gtt(plane_state);
3827         if (ret)
3828                 return ret;
3829
3830         if (!plane_state->uapi.visible)
3831                 return 0;
3832
3833         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3834         src_x = plane_state->uapi.src.x1 >> 16;
3835         src_y = plane_state->uapi.src.y1 >> 16;
3836
3837         /* Undocumented hardware limit on i965/g4x/vlv/chv */
3838         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
3839                 return -EINVAL;
3840
3841         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3842
3843         if (INTEL_GEN(dev_priv) >= 4)
3844                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3845                                                             plane_state, 0);
3846         else
3847                 offset = 0;
3848
3849         /*
3850          * Put the final coordinates back so that the src
3851          * coordinate checks will see the right values.
3852          */
3853         drm_rect_translate_to(&plane_state->uapi.src,
3854                               src_x << 16, src_y << 16);
3855
3856         /* HSW/BDW do this automagically in hardware */
3857         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3858                 unsigned int rotation = plane_state->hw.rotation;
3859                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3860                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3861
3862                 if (rotation & DRM_MODE_ROTATE_180) {
3863                         src_x += src_w - 1;
3864                         src_y += src_h - 1;
3865                 } else if (rotation & DRM_MODE_REFLECT_X) {
3866                         src_x += src_w - 1;
3867                 }
3868         }
3869
3870         plane_state->color_plane[0].offset = offset;
3871         plane_state->color_plane[0].x = src_x;
3872         plane_state->color_plane[0].y = src_y;
3873
3874         return 0;
3875 }
3876
3877 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3878 {
3879         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3880         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3881
3882         if (IS_CHERRYVIEW(dev_priv))
3883                 return i9xx_plane == PLANE_B;
3884         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3885                 return false;
3886         else if (IS_GEN(dev_priv, 4))
3887                 return i9xx_plane == PLANE_C;
3888         else
3889                 return i9xx_plane == PLANE_B ||
3890                         i9xx_plane == PLANE_C;
3891 }
3892
3893 static int
3894 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3895                  struct intel_plane_state *plane_state)
3896 {
3897         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3898         int ret;
3899
3900         ret = chv_plane_check_rotation(plane_state);
3901         if (ret)
3902                 return ret;
3903
3904         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
3905                                                   &crtc_state->uapi,
3906                                                   DRM_PLANE_HELPER_NO_SCALING,
3907                                                   DRM_PLANE_HELPER_NO_SCALING,
3908                                                   i9xx_plane_has_windowing(plane),
3909                                                   true);
3910         if (ret)
3911                 return ret;
3912
3913         ret = i9xx_check_plane_surface(plane_state);
3914         if (ret)
3915                 return ret;
3916
3917         if (!plane_state->uapi.visible)
3918                 return 0;
3919
3920         ret = intel_plane_check_src_coordinates(plane_state);
3921         if (ret)
3922                 return ret;
3923
3924         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3925
3926         return 0;
3927 }
3928
3929 static void i9xx_update_plane(struct intel_plane *plane,
3930                               const struct intel_crtc_state *crtc_state,
3931                               const struct intel_plane_state *plane_state)
3932 {
3933         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3934         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3935         u32 linear_offset;
3936         int x = plane_state->color_plane[0].x;
3937         int y = plane_state->color_plane[0].y;
3938         int crtc_x = plane_state->uapi.dst.x1;
3939         int crtc_y = plane_state->uapi.dst.y1;
3940         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
3941         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
3942         unsigned long irqflags;
3943         u32 dspaddr_offset;
3944         u32 dspcntr;
3945
3946         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3947
3948         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3949
3950         if (INTEL_GEN(dev_priv) >= 4)
3951                 dspaddr_offset = plane_state->color_plane[0].offset;
3952         else
3953                 dspaddr_offset = linear_offset;
3954
3955         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3956
3957         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3958
3959         if (INTEL_GEN(dev_priv) < 4) {
3960                 /*
3961                  * PLANE_A doesn't actually have a full window
3962                  * generator but let's assume we still need to
3963                  * program whatever is there.
3964                  */
3965                 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3966                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3967                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3968         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3969                 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3970                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3971                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3972                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3973         }
3974
3975         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3976                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3977         } else if (INTEL_GEN(dev_priv) >= 4) {
3978                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3979                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3980         }
3981
3982         /*
3983          * The control register self-arms if the plane was previously
3984          * disabled. Try to make the plane enable atomic by writing
3985          * the control register just before the surface register.
3986          */
3987         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3988         if (INTEL_GEN(dev_priv) >= 4)
3989                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3990                               intel_plane_ggtt_offset(plane_state) +
3991                               dspaddr_offset);
3992         else
3993                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3994                               intel_plane_ggtt_offset(plane_state) +
3995                               dspaddr_offset);
3996
3997         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3998 }
3999
4000 static void i9xx_disable_plane(struct intel_plane *plane,
4001                                const struct intel_crtc_state *crtc_state)
4002 {
4003         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4004         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4005         unsigned long irqflags;
4006         u32 dspcntr;
4007
4008         /*
4009          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4010          * enable on ilk+ affect the pipe bottom color as
4011          * well, so we must configure them even if the plane
4012          * is disabled.
4013          *
4014          * On pre-g4x there is no way to gamma correct the
4015          * pipe bottom color but we'll keep on doing this
4016          * anyway so that the crtc state readout works correctly.
4017          */
4018         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4019
4020         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4021
4022         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
4023         if (INTEL_GEN(dev_priv) >= 4)
4024                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
4025         else
4026                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
4027
4028         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4029 }
4030
4031 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4032                                     enum pipe *pipe)
4033 {
4034         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4035         enum intel_display_power_domain power_domain;
4036         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4037         intel_wakeref_t wakeref;
4038         bool ret;
4039         u32 val;
4040
4041         /*
4042          * Not 100% correct for planes that can move between pipes,
4043          * but that's only the case for gen2-4 which don't have any
4044          * display power wells.
4045          */
4046         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4047         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4048         if (!wakeref)
4049                 return false;
4050
4051         val = I915_READ(DSPCNTR(i9xx_plane));
4052
4053         ret = val & DISPLAY_PLANE_ENABLE;
4054
4055         if (INTEL_GEN(dev_priv) >= 5)
4056                 *pipe = plane->pipe;
4057         else
4058                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4059                         DISPPLANE_SEL_PIPE_SHIFT;
4060
4061         intel_display_power_put(dev_priv, power_domain, wakeref);
4062
4063         return ret;
4064 }
4065
4066 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4067 {
4068         struct drm_device *dev = intel_crtc->base.dev;
4069         struct drm_i915_private *dev_priv = to_i915(dev);
4070
4071         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4072         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4073         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4074 }
4075
4076 /*
4077  * This function detaches (aka. unbinds) unused scalers in hardware
4078  */
4079 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4080 {
4081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4082         const struct intel_crtc_scaler_state *scaler_state =
4083                 &crtc_state->scaler_state;
4084         int i;
4085
4086         /* loop through and disable scalers that aren't in use */
4087         for (i = 0; i < intel_crtc->num_scalers; i++) {
4088                 if (!scaler_state->scalers[i].in_use)
4089                         skl_detach_scaler(intel_crtc, i);
4090         }
4091 }
4092
4093 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4094                                           int color_plane, unsigned int rotation)
4095 {
4096         /*
4097          * The stride is either expressed as a multiple of 64 bytes chunks for
4098          * linear buffers or in number of tiles for tiled buffers.
4099          */
4100         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
4101                 return 64;
4102         else if (drm_rotation_90_or_270(rotation))
4103                 return intel_tile_height(fb, color_plane);
4104         else
4105                 return intel_tile_width_bytes(fb, color_plane);
4106 }
4107
4108 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4109                      int color_plane)
4110 {
4111         const struct drm_framebuffer *fb = plane_state->hw.fb;
4112         unsigned int rotation = plane_state->hw.rotation;
4113         u32 stride = plane_state->color_plane[color_plane].stride;
4114
4115         if (color_plane >= fb->format->num_planes)
4116                 return 0;
4117
4118         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4119 }
4120
4121 static u32 skl_plane_ctl_format(u32 pixel_format)
4122 {
4123         switch (pixel_format) {
4124         case DRM_FORMAT_C8:
4125                 return PLANE_CTL_FORMAT_INDEXED;
4126         case DRM_FORMAT_RGB565:
4127                 return PLANE_CTL_FORMAT_RGB_565;
4128         case DRM_FORMAT_XBGR8888:
4129         case DRM_FORMAT_ABGR8888:
4130                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4131         case DRM_FORMAT_XRGB8888:
4132         case DRM_FORMAT_ARGB8888:
4133                 return PLANE_CTL_FORMAT_XRGB_8888;
4134         case DRM_FORMAT_XBGR2101010:
4135         case DRM_FORMAT_ABGR2101010:
4136                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4137         case DRM_FORMAT_XRGB2101010:
4138         case DRM_FORMAT_ARGB2101010:
4139                 return PLANE_CTL_FORMAT_XRGB_2101010;
4140         case DRM_FORMAT_XBGR16161616F:
4141         case DRM_FORMAT_ABGR16161616F:
4142                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4143         case DRM_FORMAT_XRGB16161616F:
4144         case DRM_FORMAT_ARGB16161616F:
4145                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4146         case DRM_FORMAT_YUYV:
4147                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4148         case DRM_FORMAT_YVYU:
4149                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4150         case DRM_FORMAT_UYVY:
4151                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4152         case DRM_FORMAT_VYUY:
4153                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4154         case DRM_FORMAT_NV12:
4155                 return PLANE_CTL_FORMAT_NV12;
4156         case DRM_FORMAT_P010:
4157                 return PLANE_CTL_FORMAT_P010;
4158         case DRM_FORMAT_P012:
4159                 return PLANE_CTL_FORMAT_P012;
4160         case DRM_FORMAT_P016:
4161                 return PLANE_CTL_FORMAT_P016;
4162         case DRM_FORMAT_Y210:
4163                 return PLANE_CTL_FORMAT_Y210;
4164         case DRM_FORMAT_Y212:
4165                 return PLANE_CTL_FORMAT_Y212;
4166         case DRM_FORMAT_Y216:
4167                 return PLANE_CTL_FORMAT_Y216;
4168         case DRM_FORMAT_XVYU2101010:
4169                 return PLANE_CTL_FORMAT_Y410;
4170         case DRM_FORMAT_XVYU12_16161616:
4171                 return PLANE_CTL_FORMAT_Y412;
4172         case DRM_FORMAT_XVYU16161616:
4173                 return PLANE_CTL_FORMAT_Y416;
4174         default:
4175                 MISSING_CASE(pixel_format);
4176         }
4177
4178         return 0;
4179 }
4180
4181 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4182 {
4183         if (!plane_state->hw.fb->format->has_alpha)
4184                 return PLANE_CTL_ALPHA_DISABLE;
4185
4186         switch (plane_state->hw.pixel_blend_mode) {
4187         case DRM_MODE_BLEND_PIXEL_NONE:
4188                 return PLANE_CTL_ALPHA_DISABLE;
4189         case DRM_MODE_BLEND_PREMULTI:
4190                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4191         case DRM_MODE_BLEND_COVERAGE:
4192                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4193         default:
4194                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4195                 return PLANE_CTL_ALPHA_DISABLE;
4196         }
4197 }
4198
4199 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4200 {
4201         if (!plane_state->hw.fb->format->has_alpha)
4202                 return PLANE_COLOR_ALPHA_DISABLE;
4203
4204         switch (plane_state->hw.pixel_blend_mode) {
4205         case DRM_MODE_BLEND_PIXEL_NONE:
4206                 return PLANE_COLOR_ALPHA_DISABLE;
4207         case DRM_MODE_BLEND_PREMULTI:
4208                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4209         case DRM_MODE_BLEND_COVERAGE:
4210                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4211         default:
4212                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4213                 return PLANE_COLOR_ALPHA_DISABLE;
4214         }
4215 }
4216
4217 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4218 {
4219         switch (fb_modifier) {
4220         case DRM_FORMAT_MOD_LINEAR:
4221                 break;
4222         case I915_FORMAT_MOD_X_TILED:
4223                 return PLANE_CTL_TILED_X;
4224         case I915_FORMAT_MOD_Y_TILED:
4225                 return PLANE_CTL_TILED_Y;
4226         case I915_FORMAT_MOD_Y_TILED_CCS:
4227                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4228         case I915_FORMAT_MOD_Yf_TILED:
4229                 return PLANE_CTL_TILED_YF;
4230         case I915_FORMAT_MOD_Yf_TILED_CCS:
4231                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4232         default:
4233                 MISSING_CASE(fb_modifier);
4234         }
4235
4236         return 0;
4237 }
4238
4239 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4240 {
4241         switch (rotate) {
4242         case DRM_MODE_ROTATE_0:
4243                 break;
4244         /*
4245          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4246          * while i915 HW rotation is clockwise, thats why this swapping.
4247          */
4248         case DRM_MODE_ROTATE_90:
4249                 return PLANE_CTL_ROTATE_270;
4250         case DRM_MODE_ROTATE_180:
4251                 return PLANE_CTL_ROTATE_180;
4252         case DRM_MODE_ROTATE_270:
4253                 return PLANE_CTL_ROTATE_90;
4254         default:
4255                 MISSING_CASE(rotate);
4256         }
4257
4258         return 0;
4259 }
4260
4261 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4262 {
4263         switch (reflect) {
4264         case 0:
4265                 break;
4266         case DRM_MODE_REFLECT_X:
4267                 return PLANE_CTL_FLIP_HORIZONTAL;
4268         case DRM_MODE_REFLECT_Y:
4269         default:
4270                 MISSING_CASE(reflect);
4271         }
4272
4273         return 0;
4274 }
4275
4276 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4277 {
4278         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4279         u32 plane_ctl = 0;
4280
4281         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4282                 return plane_ctl;
4283
4284         if (crtc_state->gamma_enable)
4285                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4286
4287         if (crtc_state->csc_enable)
4288                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4289
4290         return plane_ctl;
4291 }
4292
4293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4294                   const struct intel_plane_state *plane_state)
4295 {
4296         struct drm_i915_private *dev_priv =
4297                 to_i915(plane_state->uapi.plane->dev);
4298         const struct drm_framebuffer *fb = plane_state->hw.fb;
4299         unsigned int rotation = plane_state->hw.rotation;
4300         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4301         u32 plane_ctl;
4302
4303         plane_ctl = PLANE_CTL_ENABLE;
4304
4305         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4306                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4307                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4308
4309                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4310                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4311
4312                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4313                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4314         }
4315
4316         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4317         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4318         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4319
4320         if (INTEL_GEN(dev_priv) >= 10)
4321                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4322                                                 DRM_MODE_REFLECT_MASK);
4323
4324         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4325                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4326         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4327                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4328
4329         return plane_ctl;
4330 }
4331
4332 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4333 {
4334         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4335         u32 plane_color_ctl = 0;
4336
4337         if (INTEL_GEN(dev_priv) >= 11)
4338                 return plane_color_ctl;
4339
4340         if (crtc_state->gamma_enable)
4341                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4342
4343         if (crtc_state->csc_enable)
4344                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4345
4346         return plane_color_ctl;
4347 }
4348
4349 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4350                         const struct intel_plane_state *plane_state)
4351 {
4352         struct drm_i915_private *dev_priv =
4353                 to_i915(plane_state->uapi.plane->dev);
4354         const struct drm_framebuffer *fb = plane_state->hw.fb;
4355         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4356         u32 plane_color_ctl = 0;
4357
4358         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4359         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4360
4361         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4362                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4363                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4364                 else
4365                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4366
4367                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4368                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4369         } else if (fb->format->is_yuv) {
4370                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4371         }
4372
4373         return plane_color_ctl;
4374 }
4375
4376 static int
4377 __intel_display_resume(struct drm_device *dev,
4378                        struct drm_atomic_state *state,
4379                        struct drm_modeset_acquire_ctx *ctx)
4380 {
4381         struct drm_crtc_state *crtc_state;
4382         struct drm_crtc *crtc;
4383         int i, ret;
4384
4385         intel_modeset_setup_hw_state(dev, ctx);
4386         intel_vga_redisable(to_i915(dev));
4387
4388         if (!state)
4389                 return 0;
4390
4391         /*
4392          * We've duplicated the state, pointers to the old state are invalid.
4393          *
4394          * Don't attempt to use the old state until we commit the duplicated state.
4395          */
4396         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4397                 /*
4398                  * Force recalculation even if we restore
4399                  * current state. With fast modeset this may not result
4400                  * in a modeset when the state is compatible.
4401                  */
4402                 crtc_state->mode_changed = true;
4403         }
4404
4405         /* ignore any reset values/BIOS leftovers in the WM registers */
4406         if (!HAS_GMCH(to_i915(dev)))
4407                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4408
4409         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4410
4411         WARN_ON(ret == -EDEADLK);
4412         return ret;
4413 }
4414
4415 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4416 {
4417         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4418                 intel_has_gpu_reset(&dev_priv->gt));
4419 }
4420
4421 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4422 {
4423         struct drm_device *dev = &dev_priv->drm;
4424         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4425         struct drm_atomic_state *state;
4426         int ret;
4427
4428         /* reset doesn't touch the display */
4429         if (!i915_modparams.force_reset_modeset_test &&
4430             !gpu_reset_clobbers_display(dev_priv))
4431                 return;
4432
4433         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4434         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4435         smp_mb__after_atomic();
4436         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4437
4438         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4439                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4440                 intel_gt_set_wedged(&dev_priv->gt);
4441         }
4442
4443         /*
4444          * Need mode_config.mutex so that we don't
4445          * trample ongoing ->detect() and whatnot.
4446          */
4447         mutex_lock(&dev->mode_config.mutex);
4448         drm_modeset_acquire_init(ctx, 0);
4449         while (1) {
4450                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4451                 if (ret != -EDEADLK)
4452                         break;
4453
4454                 drm_modeset_backoff(ctx);
4455         }
4456         /*
4457          * Disabling the crtcs gracefully seems nicer. Also the
4458          * g33 docs say we should at least disable all the planes.
4459          */
4460         state = drm_atomic_helper_duplicate_state(dev, ctx);
4461         if (IS_ERR(state)) {
4462                 ret = PTR_ERR(state);
4463                 DRM_ERROR("Duplicating state failed with %i\n", ret);
4464                 return;
4465         }
4466
4467         ret = drm_atomic_helper_disable_all(dev, ctx);
4468         if (ret) {
4469                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4470                 drm_atomic_state_put(state);
4471                 return;
4472         }
4473
4474         dev_priv->modeset_restore_state = state;
4475         state->acquire_ctx = ctx;
4476 }
4477
4478 void intel_finish_reset(struct drm_i915_private *dev_priv)
4479 {
4480         struct drm_device *dev = &dev_priv->drm;
4481         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4482         struct drm_atomic_state *state;
4483         int ret;
4484
4485         /* reset doesn't touch the display */
4486         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4487                 return;
4488
4489         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4490         if (!state)
4491                 goto unlock;
4492
4493         /* reset doesn't touch the display */
4494         if (!gpu_reset_clobbers_display(dev_priv)) {
4495                 /* for testing only restore the display */
4496                 ret = __intel_display_resume(dev, state, ctx);
4497                 if (ret)
4498                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4499         } else {
4500                 /*
4501                  * The display has been reset as well,
4502                  * so need a full re-initialization.
4503                  */
4504                 intel_pps_unlock_regs_wa(dev_priv);
4505                 intel_modeset_init_hw(dev_priv);
4506                 intel_init_clock_gating(dev_priv);
4507
4508                 spin_lock_irq(&dev_priv->irq_lock);
4509                 if (dev_priv->display.hpd_irq_setup)
4510                         dev_priv->display.hpd_irq_setup(dev_priv);
4511                 spin_unlock_irq(&dev_priv->irq_lock);
4512
4513                 ret = __intel_display_resume(dev, state, ctx);
4514                 if (ret)
4515                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4516
4517                 intel_hpd_init(dev_priv);
4518         }
4519
4520         drm_atomic_state_put(state);
4521 unlock:
4522         drm_modeset_drop_locks(ctx);
4523         drm_modeset_acquire_fini(ctx);
4524         mutex_unlock(&dev->mode_config.mutex);
4525
4526         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4527 }
4528
4529 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4530 {
4531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4532         enum pipe pipe = crtc->pipe;
4533         u32 tmp;
4534
4535         tmp = I915_READ(PIPE_CHICKEN(pipe));
4536
4537         /*
4538          * Display WA #1153: icl
4539          * enable hardware to bypass the alpha math
4540          * and rounding for per-pixel values 00 and 0xff
4541          */
4542         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4543         /*
4544          * Display WA # 1605353570: icl
4545          * Set the pixel rounding bit to 1 for allowing
4546          * passthrough of Frame buffer pixels unmodified
4547          * across pipe
4548          */
4549         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4550         I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4551 }
4552
4553 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
4554 {
4555         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4556         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4557         u32 trans_ddi_func_ctl2_val;
4558         u8 master_select;
4559
4560         /*
4561          * Configure the master select and enable Transcoder Port Sync for
4562          * Slave CRTCs transcoder.
4563          */
4564         if (crtc_state->master_transcoder == INVALID_TRANSCODER)
4565                 return;
4566
4567         if (crtc_state->master_transcoder == TRANSCODER_EDP)
4568                 master_select = 0;
4569         else
4570                 master_select = crtc_state->master_transcoder + 1;
4571
4572         /* Set the master select bits for Tranascoder Port Sync */
4573         trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
4574                                    PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
4575                 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
4576         /* Enable Transcoder Port Sync */
4577         trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
4578
4579         I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
4580                    trans_ddi_func_ctl2_val);
4581 }
4582
4583 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
4584 {
4585         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4586         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4587         i915_reg_t reg;
4588         u32 trans_ddi_func_ctl2_val;
4589
4590         if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
4591                 return;
4592
4593         DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
4594                       transcoder_name(old_crtc_state->cpu_transcoder));
4595
4596         reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
4597         trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
4598                                     PORT_SYNC_MODE_MASTER_SELECT_MASK);
4599         I915_WRITE(reg, trans_ddi_func_ctl2_val);
4600 }
4601
4602 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4603 {
4604         struct drm_device *dev = crtc->base.dev;
4605         struct drm_i915_private *dev_priv = to_i915(dev);
4606         enum pipe pipe = crtc->pipe;
4607         i915_reg_t reg;
4608         u32 temp;
4609
4610         /* enable normal train */
4611         reg = FDI_TX_CTL(pipe);
4612         temp = I915_READ(reg);
4613         if (IS_IVYBRIDGE(dev_priv)) {
4614                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4615                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4616         } else {
4617                 temp &= ~FDI_LINK_TRAIN_NONE;
4618                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4619         }
4620         I915_WRITE(reg, temp);
4621
4622         reg = FDI_RX_CTL(pipe);
4623         temp = I915_READ(reg);
4624         if (HAS_PCH_CPT(dev_priv)) {
4625                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4626                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4627         } else {
4628                 temp &= ~FDI_LINK_TRAIN_NONE;
4629                 temp |= FDI_LINK_TRAIN_NONE;
4630         }
4631         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4632
4633         /* wait one idle pattern time */
4634         POSTING_READ(reg);
4635         udelay(1000);
4636
4637         /* IVB wants error correction enabled */
4638         if (IS_IVYBRIDGE(dev_priv))
4639                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4640                            FDI_FE_ERRC_ENABLE);
4641 }
4642
4643 /* The FDI link training functions for ILK/Ibexpeak. */
4644 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4645                                     const struct intel_crtc_state *crtc_state)
4646 {
4647         struct drm_device *dev = crtc->base.dev;
4648         struct drm_i915_private *dev_priv = to_i915(dev);
4649         enum pipe pipe = crtc->pipe;
4650         i915_reg_t reg;
4651         u32 temp, tries;
4652
4653         /* FDI needs bits from pipe first */
4654         assert_pipe_enabled(dev_priv, pipe);
4655
4656         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4657            for train result */
4658         reg = FDI_RX_IMR(pipe);
4659         temp = I915_READ(reg);
4660         temp &= ~FDI_RX_SYMBOL_LOCK;
4661         temp &= ~FDI_RX_BIT_LOCK;
4662         I915_WRITE(reg, temp);
4663         I915_READ(reg);
4664         udelay(150);
4665
4666         /* enable CPU FDI TX and PCH FDI RX */
4667         reg = FDI_TX_CTL(pipe);
4668         temp = I915_READ(reg);
4669         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4670         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4671         temp &= ~FDI_LINK_TRAIN_NONE;
4672         temp |= FDI_LINK_TRAIN_PATTERN_1;
4673         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4674
4675         reg = FDI_RX_CTL(pipe);
4676         temp = I915_READ(reg);
4677         temp &= ~FDI_LINK_TRAIN_NONE;
4678         temp |= FDI_LINK_TRAIN_PATTERN_1;
4679         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4680
4681         POSTING_READ(reg);
4682         udelay(150);
4683
4684         /* Ironlake workaround, enable clock pointer after FDI enable*/
4685         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4686         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4687                    FDI_RX_PHASE_SYNC_POINTER_EN);
4688
4689         reg = FDI_RX_IIR(pipe);
4690         for (tries = 0; tries < 5; tries++) {
4691                 temp = I915_READ(reg);
4692                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4693
4694                 if ((temp & FDI_RX_BIT_LOCK)) {
4695                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4696                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4697                         break;
4698                 }
4699         }
4700         if (tries == 5)
4701                 DRM_ERROR("FDI train 1 fail!\n");
4702
4703         /* Train 2 */
4704         reg = FDI_TX_CTL(pipe);
4705         temp = I915_READ(reg);
4706         temp &= ~FDI_LINK_TRAIN_NONE;
4707         temp |= FDI_LINK_TRAIN_PATTERN_2;
4708         I915_WRITE(reg, temp);
4709
4710         reg = FDI_RX_CTL(pipe);
4711         temp = I915_READ(reg);
4712         temp &= ~FDI_LINK_TRAIN_NONE;
4713         temp |= FDI_LINK_TRAIN_PATTERN_2;
4714         I915_WRITE(reg, temp);
4715
4716         POSTING_READ(reg);
4717         udelay(150);
4718
4719         reg = FDI_RX_IIR(pipe);
4720         for (tries = 0; tries < 5; tries++) {
4721                 temp = I915_READ(reg);
4722                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4723
4724                 if (temp & FDI_RX_SYMBOL_LOCK) {
4725                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4726                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4727                         break;
4728                 }
4729         }
4730         if (tries == 5)
4731                 DRM_ERROR("FDI train 2 fail!\n");
4732
4733         DRM_DEBUG_KMS("FDI train done\n");
4734
4735 }
4736
4737 static const int snb_b_fdi_train_param[] = {
4738         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4739         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4740         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4741         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4742 };
4743
4744 /* The FDI link training functions for SNB/Cougarpoint. */
4745 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4746                                 const struct intel_crtc_state *crtc_state)
4747 {
4748         struct drm_device *dev = crtc->base.dev;
4749         struct drm_i915_private *dev_priv = to_i915(dev);
4750         enum pipe pipe = crtc->pipe;
4751         i915_reg_t reg;
4752         u32 temp, i, retry;
4753
4754         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4755            for train result */
4756         reg = FDI_RX_IMR(pipe);
4757         temp = I915_READ(reg);
4758         temp &= ~FDI_RX_SYMBOL_LOCK;
4759         temp &= ~FDI_RX_BIT_LOCK;
4760         I915_WRITE(reg, temp);
4761
4762         POSTING_READ(reg);
4763         udelay(150);
4764
4765         /* enable CPU FDI TX and PCH FDI RX */
4766         reg = FDI_TX_CTL(pipe);
4767         temp = I915_READ(reg);
4768         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4769         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4770         temp &= ~FDI_LINK_TRAIN_NONE;
4771         temp |= FDI_LINK_TRAIN_PATTERN_1;
4772         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4773         /* SNB-B */
4774         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4775         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4776
4777         I915_WRITE(FDI_RX_MISC(pipe),
4778                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4779
4780         reg = FDI_RX_CTL(pipe);
4781         temp = I915_READ(reg);
4782         if (HAS_PCH_CPT(dev_priv)) {
4783                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4784                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4785         } else {
4786                 temp &= ~FDI_LINK_TRAIN_NONE;
4787                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4788         }
4789         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4790
4791         POSTING_READ(reg);
4792         udelay(150);
4793
4794         for (i = 0; i < 4; i++) {
4795                 reg = FDI_TX_CTL(pipe);
4796                 temp = I915_READ(reg);
4797                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4798                 temp |= snb_b_fdi_train_param[i];
4799                 I915_WRITE(reg, temp);
4800
4801                 POSTING_READ(reg);
4802                 udelay(500);
4803
4804                 for (retry = 0; retry < 5; retry++) {
4805                         reg = FDI_RX_IIR(pipe);
4806                         temp = I915_READ(reg);
4807                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4808                         if (temp & FDI_RX_BIT_LOCK) {
4809                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4810                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4811                                 break;
4812                         }
4813                         udelay(50);
4814                 }
4815                 if (retry < 5)
4816                         break;
4817         }
4818         if (i == 4)
4819                 DRM_ERROR("FDI train 1 fail!\n");
4820
4821         /* Train 2 */
4822         reg = FDI_TX_CTL(pipe);
4823         temp = I915_READ(reg);
4824         temp &= ~FDI_LINK_TRAIN_NONE;
4825         temp |= FDI_LINK_TRAIN_PATTERN_2;
4826         if (IS_GEN(dev_priv, 6)) {
4827                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4828                 /* SNB-B */
4829                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4830         }
4831         I915_WRITE(reg, temp);
4832
4833         reg = FDI_RX_CTL(pipe);
4834         temp = I915_READ(reg);
4835         if (HAS_PCH_CPT(dev_priv)) {
4836                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4837                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4838         } else {
4839                 temp &= ~FDI_LINK_TRAIN_NONE;
4840                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4841         }
4842         I915_WRITE(reg, temp);
4843
4844         POSTING_READ(reg);
4845         udelay(150);
4846
4847         for (i = 0; i < 4; i++) {
4848                 reg = FDI_TX_CTL(pipe);
4849                 temp = I915_READ(reg);
4850                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4851                 temp |= snb_b_fdi_train_param[i];
4852                 I915_WRITE(reg, temp);
4853
4854                 POSTING_READ(reg);
4855                 udelay(500);
4856
4857                 for (retry = 0; retry < 5; retry++) {
4858                         reg = FDI_RX_IIR(pipe);
4859                         temp = I915_READ(reg);
4860                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4861                         if (temp & FDI_RX_SYMBOL_LOCK) {
4862                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4863                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4864                                 break;
4865                         }
4866                         udelay(50);
4867                 }
4868                 if (retry < 5)
4869                         break;
4870         }
4871         if (i == 4)
4872                 DRM_ERROR("FDI train 2 fail!\n");
4873
4874         DRM_DEBUG_KMS("FDI train done.\n");
4875 }
4876
4877 /* Manual link training for Ivy Bridge A0 parts */
4878 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4879                                       const struct intel_crtc_state *crtc_state)
4880 {
4881         struct drm_device *dev = crtc->base.dev;
4882         struct drm_i915_private *dev_priv = to_i915(dev);
4883         enum pipe pipe = crtc->pipe;
4884         i915_reg_t reg;
4885         u32 temp, i, j;
4886
4887         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4888            for train result */
4889         reg = FDI_RX_IMR(pipe);
4890         temp = I915_READ(reg);
4891         temp &= ~FDI_RX_SYMBOL_LOCK;
4892         temp &= ~FDI_RX_BIT_LOCK;
4893         I915_WRITE(reg, temp);
4894
4895         POSTING_READ(reg);
4896         udelay(150);
4897
4898         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4899                       I915_READ(FDI_RX_IIR(pipe)));
4900
4901         /* Try each vswing and preemphasis setting twice before moving on */
4902         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4903                 /* disable first in case we need to retry */
4904                 reg = FDI_TX_CTL(pipe);
4905                 temp = I915_READ(reg);
4906                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4907                 temp &= ~FDI_TX_ENABLE;
4908                 I915_WRITE(reg, temp);
4909
4910                 reg = FDI_RX_CTL(pipe);
4911                 temp = I915_READ(reg);
4912                 temp &= ~FDI_LINK_TRAIN_AUTO;
4913                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4914                 temp &= ~FDI_RX_ENABLE;
4915                 I915_WRITE(reg, temp);
4916
4917                 /* enable CPU FDI TX and PCH FDI RX */
4918                 reg = FDI_TX_CTL(pipe);
4919                 temp = I915_READ(reg);
4920                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4921                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4922                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4923                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4924                 temp |= snb_b_fdi_train_param[j/2];
4925                 temp |= FDI_COMPOSITE_SYNC;
4926                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4927
4928                 I915_WRITE(FDI_RX_MISC(pipe),
4929                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4930
4931                 reg = FDI_RX_CTL(pipe);
4932                 temp = I915_READ(reg);
4933                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4934                 temp |= FDI_COMPOSITE_SYNC;
4935                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4936
4937                 POSTING_READ(reg);
4938                 udelay(1); /* should be 0.5us */
4939
4940                 for (i = 0; i < 4; i++) {
4941                         reg = FDI_RX_IIR(pipe);
4942                         temp = I915_READ(reg);
4943                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4944
4945                         if (temp & FDI_RX_BIT_LOCK ||
4946                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4947                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4948                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4949                                               i);
4950                                 break;
4951                         }
4952                         udelay(1); /* should be 0.5us */
4953                 }
4954                 if (i == 4) {
4955                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4956                         continue;
4957                 }
4958
4959                 /* Train 2 */
4960                 reg = FDI_TX_CTL(pipe);
4961                 temp = I915_READ(reg);
4962                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4963                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4964                 I915_WRITE(reg, temp);
4965
4966                 reg = FDI_RX_CTL(pipe);
4967                 temp = I915_READ(reg);
4968                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4969                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4970                 I915_WRITE(reg, temp);
4971
4972                 POSTING_READ(reg);
4973                 udelay(2); /* should be 1.5us */
4974
4975                 for (i = 0; i < 4; i++) {
4976                         reg = FDI_RX_IIR(pipe);
4977                         temp = I915_READ(reg);
4978                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4979
4980                         if (temp & FDI_RX_SYMBOL_LOCK ||
4981                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4982                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4983                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4984                                               i);
4985                                 goto train_done;
4986                         }
4987                         udelay(2); /* should be 1.5us */
4988                 }
4989                 if (i == 4)
4990                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4991         }
4992
4993 train_done:
4994         DRM_DEBUG_KMS("FDI train done.\n");
4995 }
4996
4997 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4998 {
4999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5000         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5001         enum pipe pipe = intel_crtc->pipe;
5002         i915_reg_t reg;
5003         u32 temp;
5004
5005         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5006         reg = FDI_RX_CTL(pipe);
5007         temp = I915_READ(reg);
5008         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5009         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5010         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5011         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
5012
5013         POSTING_READ(reg);
5014         udelay(200);
5015
5016         /* Switch from Rawclk to PCDclk */
5017         temp = I915_READ(reg);
5018         I915_WRITE(reg, temp | FDI_PCDCLK);
5019
5020         POSTING_READ(reg);
5021         udelay(200);
5022
5023         /* Enable CPU FDI TX PLL, always on for Ironlake */
5024         reg = FDI_TX_CTL(pipe);
5025         temp = I915_READ(reg);
5026         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5027                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5028
5029                 POSTING_READ(reg);
5030                 udelay(100);
5031         }
5032 }
5033
5034 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
5035 {
5036         struct drm_device *dev = intel_crtc->base.dev;
5037         struct drm_i915_private *dev_priv = to_i915(dev);
5038         enum pipe pipe = intel_crtc->pipe;
5039         i915_reg_t reg;
5040         u32 temp;
5041
5042         /* Switch from PCDclk to Rawclk */
5043         reg = FDI_RX_CTL(pipe);
5044         temp = I915_READ(reg);
5045         I915_WRITE(reg, temp & ~FDI_PCDCLK);
5046
5047         /* Disable CPU FDI TX PLL */
5048         reg = FDI_TX_CTL(pipe);
5049         temp = I915_READ(reg);
5050         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
5051
5052         POSTING_READ(reg);
5053         udelay(100);
5054
5055         reg = FDI_RX_CTL(pipe);
5056         temp = I915_READ(reg);
5057         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
5058
5059         /* Wait for the clocks to turn off. */
5060         POSTING_READ(reg);
5061         udelay(100);
5062 }
5063
5064 static void ironlake_fdi_disable(struct intel_crtc *crtc)
5065 {
5066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5067         enum pipe pipe = crtc->pipe;
5068         i915_reg_t reg;
5069         u32 temp;
5070
5071         /* disable CPU FDI tx and PCH FDI rx */
5072         reg = FDI_TX_CTL(pipe);
5073         temp = I915_READ(reg);
5074         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
5075         POSTING_READ(reg);
5076
5077         reg = FDI_RX_CTL(pipe);
5078         temp = I915_READ(reg);
5079         temp &= ~(0x7 << 16);
5080         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5081         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
5082
5083         POSTING_READ(reg);
5084         udelay(100);
5085
5086         /* Ironlake workaround, disable clock pointer after downing FDI */
5087         if (HAS_PCH_IBX(dev_priv))
5088                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
5089
5090         /* still set train pattern 1 */
5091         reg = FDI_TX_CTL(pipe);
5092         temp = I915_READ(reg);
5093         temp &= ~FDI_LINK_TRAIN_NONE;
5094         temp |= FDI_LINK_TRAIN_PATTERN_1;
5095         I915_WRITE(reg, temp);
5096
5097         reg = FDI_RX_CTL(pipe);
5098         temp = I915_READ(reg);
5099         if (HAS_PCH_CPT(dev_priv)) {
5100                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5101                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5102         } else {
5103                 temp &= ~FDI_LINK_TRAIN_NONE;
5104                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5105         }
5106         /* BPC in FDI rx is consistent with that in PIPECONF */
5107         temp &= ~(0x07 << 16);
5108         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5109         I915_WRITE(reg, temp);
5110
5111         POSTING_READ(reg);
5112         udelay(100);
5113 }
5114
5115 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5116 {
5117         struct drm_crtc *crtc;
5118         bool cleanup_done;
5119
5120         drm_for_each_crtc(crtc, &dev_priv->drm) {
5121                 struct drm_crtc_commit *commit;
5122                 spin_lock(&crtc->commit_lock);
5123                 commit = list_first_entry_or_null(&crtc->commit_list,
5124                                                   struct drm_crtc_commit, commit_entry);
5125                 cleanup_done = commit ?
5126                         try_wait_for_completion(&commit->cleanup_done) : true;
5127                 spin_unlock(&crtc->commit_lock);
5128
5129                 if (cleanup_done)
5130                         continue;
5131
5132                 drm_crtc_wait_one_vblank(crtc);
5133
5134                 return true;
5135         }
5136
5137         return false;
5138 }
5139
5140 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5141 {
5142         u32 temp;
5143
5144         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
5145
5146         mutex_lock(&dev_priv->sb_lock);
5147
5148         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5149         temp |= SBI_SSCCTL_DISABLE;
5150         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5151
5152         mutex_unlock(&dev_priv->sb_lock);
5153 }
5154
5155 /* Program iCLKIP clock to the desired frequency */
5156 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5157 {
5158         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5159         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5160         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5161         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5162         u32 temp;
5163
5164         lpt_disable_iclkip(dev_priv);
5165
5166         /* The iCLK virtual clock root frequency is in MHz,
5167          * but the adjusted_mode->crtc_clock in in KHz. To get the
5168          * divisors, it is necessary to divide one by another, so we
5169          * convert the virtual clock precision to KHz here for higher
5170          * precision.
5171          */
5172         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5173                 u32 iclk_virtual_root_freq = 172800 * 1000;
5174                 u32 iclk_pi_range = 64;
5175                 u32 desired_divisor;
5176
5177                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5178                                                     clock << auxdiv);
5179                 divsel = (desired_divisor / iclk_pi_range) - 2;
5180                 phaseinc = desired_divisor % iclk_pi_range;
5181
5182                 /*
5183                  * Near 20MHz is a corner case which is
5184                  * out of range for the 7-bit divisor
5185                  */
5186                 if (divsel <= 0x7f)
5187                         break;
5188         }
5189
5190         /* This should not happen with any sane values */
5191         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5192                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5193         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5194                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5195
5196         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5197                         clock,
5198                         auxdiv,
5199                         divsel,
5200                         phasedir,
5201                         phaseinc);
5202
5203         mutex_lock(&dev_priv->sb_lock);
5204
5205         /* Program SSCDIVINTPHASE6 */
5206         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5207         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5208         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5209         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5210         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5211         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5212         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5213         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5214
5215         /* Program SSCAUXDIV */
5216         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5217         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5218         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5219         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5220
5221         /* Enable modulator and associated divider */
5222         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5223         temp &= ~SBI_SSCCTL_DISABLE;
5224         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5225
5226         mutex_unlock(&dev_priv->sb_lock);
5227
5228         /* Wait for initialization time */
5229         udelay(24);
5230
5231         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5232 }
5233
5234 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5235 {
5236         u32 divsel, phaseinc, auxdiv;
5237         u32 iclk_virtual_root_freq = 172800 * 1000;
5238         u32 iclk_pi_range = 64;
5239         u32 desired_divisor;
5240         u32 temp;
5241
5242         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5243                 return 0;
5244
5245         mutex_lock(&dev_priv->sb_lock);
5246
5247         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5248         if (temp & SBI_SSCCTL_DISABLE) {
5249                 mutex_unlock(&dev_priv->sb_lock);
5250                 return 0;
5251         }
5252
5253         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5254         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5255                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5256         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5257                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5258
5259         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5260         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5261                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5262
5263         mutex_unlock(&dev_priv->sb_lock);
5264
5265         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5266
5267         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5268                                  desired_divisor << auxdiv);
5269 }
5270
5271 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5272                                                 enum pipe pch_transcoder)
5273 {
5274         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5275         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5276         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5277
5278         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5279                    I915_READ(HTOTAL(cpu_transcoder)));
5280         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5281                    I915_READ(HBLANK(cpu_transcoder)));
5282         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5283                    I915_READ(HSYNC(cpu_transcoder)));
5284
5285         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5286                    I915_READ(VTOTAL(cpu_transcoder)));
5287         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5288                    I915_READ(VBLANK(cpu_transcoder)));
5289         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5290                    I915_READ(VSYNC(cpu_transcoder)));
5291         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5292                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
5293 }
5294
5295 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5296 {
5297         u32 temp;
5298
5299         temp = I915_READ(SOUTH_CHICKEN1);
5300         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5301                 return;
5302
5303         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5304         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5305
5306         temp &= ~FDI_BC_BIFURCATION_SELECT;
5307         if (enable)
5308                 temp |= FDI_BC_BIFURCATION_SELECT;
5309
5310         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5311         I915_WRITE(SOUTH_CHICKEN1, temp);
5312         POSTING_READ(SOUTH_CHICKEN1);
5313 }
5314
5315 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5316 {
5317         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5318         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5319
5320         switch (crtc->pipe) {
5321         case PIPE_A:
5322                 break;
5323         case PIPE_B:
5324                 if (crtc_state->fdi_lanes > 2)
5325                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5326                 else
5327                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5328
5329                 break;
5330         case PIPE_C:
5331                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5332
5333                 break;
5334         default:
5335                 BUG();
5336         }
5337 }
5338
5339 /*
5340  * Finds the encoder associated with the given CRTC. This can only be
5341  * used when we know that the CRTC isn't feeding multiple encoders!
5342  */
5343 static struct intel_encoder *
5344 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5345                            const struct intel_crtc_state *crtc_state)
5346 {
5347         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5348         const struct drm_connector_state *connector_state;
5349         const struct drm_connector *connector;
5350         struct intel_encoder *encoder = NULL;
5351         int num_encoders = 0;
5352         int i;
5353
5354         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5355                 if (connector_state->crtc != &crtc->base)
5356                         continue;
5357
5358                 encoder = to_intel_encoder(connector_state->best_encoder);
5359                 num_encoders++;
5360         }
5361
5362         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5363              num_encoders, pipe_name(crtc->pipe));
5364
5365         return encoder;
5366 }
5367
5368 /*
5369  * Enable PCH resources required for PCH ports:
5370  *   - PCH PLLs
5371  *   - FDI training & RX/TX
5372  *   - update transcoder timings
5373  *   - DP transcoding bits
5374  *   - transcoder
5375  */
5376 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5377                                 const struct intel_crtc_state *crtc_state)
5378 {
5379         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5380         struct drm_device *dev = crtc->base.dev;
5381         struct drm_i915_private *dev_priv = to_i915(dev);
5382         enum pipe pipe = crtc->pipe;
5383         u32 temp;
5384
5385         assert_pch_transcoder_disabled(dev_priv, pipe);
5386
5387         if (IS_IVYBRIDGE(dev_priv))
5388                 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5389
5390         /* Write the TU size bits before fdi link training, so that error
5391          * detection works. */
5392         I915_WRITE(FDI_RX_TUSIZE1(pipe),
5393                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5394
5395         /* For PCH output, training FDI link */
5396         dev_priv->display.fdi_link_train(crtc, crtc_state);
5397
5398         /* We need to program the right clock selection before writing the pixel
5399          * mutliplier into the DPLL. */
5400         if (HAS_PCH_CPT(dev_priv)) {
5401                 u32 sel;
5402
5403                 temp = I915_READ(PCH_DPLL_SEL);
5404                 temp |= TRANS_DPLL_ENABLE(pipe);
5405                 sel = TRANS_DPLLB_SEL(pipe);
5406                 if (crtc_state->shared_dpll ==
5407                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5408                         temp |= sel;
5409                 else
5410                         temp &= ~sel;
5411                 I915_WRITE(PCH_DPLL_SEL, temp);
5412         }
5413
5414         /* XXX: pch pll's can be enabled any time before we enable the PCH
5415          * transcoder, and we actually should do this to not upset any PCH
5416          * transcoder that already use the clock when we share it.
5417          *
5418          * Note that enable_shared_dpll tries to do the right thing, but
5419          * get_shared_dpll unconditionally resets the pll - we need that to have
5420          * the right LVDS enable sequence. */
5421         intel_enable_shared_dpll(crtc_state);
5422
5423         /* set transcoder timing, panel must allow it */
5424         assert_panel_unlocked(dev_priv, pipe);
5425         ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5426
5427         intel_fdi_normal_train(crtc);
5428
5429         /* For PCH DP, enable TRANS_DP_CTL */
5430         if (HAS_PCH_CPT(dev_priv) &&
5431             intel_crtc_has_dp_encoder(crtc_state)) {
5432                 const struct drm_display_mode *adjusted_mode =
5433                         &crtc_state->hw.adjusted_mode;
5434                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5435                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5436                 enum port port;
5437
5438                 temp = I915_READ(reg);
5439                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5440                           TRANS_DP_SYNC_MASK |
5441                           TRANS_DP_BPC_MASK);
5442                 temp |= TRANS_DP_OUTPUT_ENABLE;
5443                 temp |= bpc << 9; /* same format but at 11:9 */
5444
5445                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5446                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5447                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5448                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5449
5450                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5451                 WARN_ON(port < PORT_B || port > PORT_D);
5452                 temp |= TRANS_DP_PORT_SEL(port);
5453
5454                 I915_WRITE(reg, temp);
5455         }
5456
5457         ironlake_enable_pch_transcoder(crtc_state);
5458 }
5459
5460 static void lpt_pch_enable(const struct intel_atomic_state *state,
5461                            const struct intel_crtc_state *crtc_state)
5462 {
5463         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5465         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5466
5467         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5468
5469         lpt_program_iclkip(crtc_state);
5470
5471         /* Set transcoder timing. */
5472         ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5473
5474         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5475 }
5476
5477 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5478                                enum pipe pipe)
5479 {
5480         i915_reg_t dslreg = PIPEDSL(pipe);
5481         u32 temp;
5482
5483         temp = I915_READ(dslreg);
5484         udelay(500);
5485         if (wait_for(I915_READ(dslreg) != temp, 5)) {
5486                 if (wait_for(I915_READ(dslreg) != temp, 5))
5487                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5488         }
5489 }
5490
5491 /*
5492  * The hardware phase 0.0 refers to the center of the pixel.
5493  * We want to start from the top/left edge which is phase
5494  * -0.5. That matches how the hardware calculates the scaling
5495  * factors (from top-left of the first pixel to bottom-right
5496  * of the last pixel, as opposed to the pixel centers).
5497  *
5498  * For 4:2:0 subsampled chroma planes we obviously have to
5499  * adjust that so that the chroma sample position lands in
5500  * the right spot.
5501  *
5502  * Note that for packed YCbCr 4:2:2 formats there is no way to
5503  * control chroma siting. The hardware simply replicates the
5504  * chroma samples for both of the luma samples, and thus we don't
5505  * actually get the expected MPEG2 chroma siting convention :(
5506  * The same behaviour is observed on pre-SKL platforms as well.
5507  *
5508  * Theory behind the formula (note that we ignore sub-pixel
5509  * source coordinates):
5510  * s = source sample position
5511  * d = destination sample position
5512  *
5513  * Downscaling 4:1:
5514  * -0.5
5515  * | 0.0
5516  * | |     1.5 (initial phase)
5517  * | |     |
5518  * v v     v
5519  * | s | s | s | s |
5520  * |       d       |
5521  *
5522  * Upscaling 1:4:
5523  * -0.5
5524  * | -0.375 (initial phase)
5525  * | |     0.0
5526  * | |     |
5527  * v v     v
5528  * |       s       |
5529  * | d | d | d | d |
5530  */
5531 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5532 {
5533         int phase = -0x8000;
5534         u16 trip = 0;
5535
5536         if (chroma_cosited)
5537                 phase += (sub - 1) * 0x8000 / sub;
5538
5539         phase += scale / (2 * sub);
5540
5541         /*
5542          * Hardware initial phase limited to [-0.5:1.5].
5543          * Since the max hardware scale factor is 3.0, we
5544          * should never actually excdeed 1.0 here.
5545          */
5546         WARN_ON(phase < -0x8000 || phase > 0x18000);
5547
5548         if (phase < 0)
5549                 phase = 0x10000 + phase;
5550         else
5551                 trip = PS_PHASE_TRIP;
5552
5553         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5554 }
5555
5556 #define SKL_MIN_SRC_W 8
5557 #define SKL_MAX_SRC_W 4096
5558 #define SKL_MIN_SRC_H 8
5559 #define SKL_MAX_SRC_H 4096
5560 #define SKL_MIN_DST_W 8
5561 #define SKL_MAX_DST_W 4096
5562 #define SKL_MIN_DST_H 8
5563 #define SKL_MAX_DST_H 4096
5564 #define ICL_MAX_SRC_W 5120
5565 #define ICL_MAX_SRC_H 4096
5566 #define ICL_MAX_DST_W 5120
5567 #define ICL_MAX_DST_H 4096
5568 #define SKL_MIN_YUV_420_SRC_W 16
5569 #define SKL_MIN_YUV_420_SRC_H 16
5570
5571 static int
5572 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5573                   unsigned int scaler_user, int *scaler_id,
5574                   int src_w, int src_h, int dst_w, int dst_h,
5575                   const struct drm_format_info *format, bool need_scaler)
5576 {
5577         struct intel_crtc_scaler_state *scaler_state =
5578                 &crtc_state->scaler_state;
5579         struct intel_crtc *intel_crtc =
5580                 to_intel_crtc(crtc_state->uapi.crtc);
5581         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5582         const struct drm_display_mode *adjusted_mode =
5583                 &crtc_state->hw.adjusted_mode;
5584
5585         /*
5586          * Src coordinates are already rotated by 270 degrees for
5587          * the 90/270 degree plane rotation cases (to match the
5588          * GTT mapping), hence no need to account for rotation here.
5589          */
5590         if (src_w != dst_w || src_h != dst_h)
5591                 need_scaler = true;
5592
5593         /*
5594          * Scaling/fitting not supported in IF-ID mode in GEN9+
5595          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5596          * Once NV12 is enabled, handle it here while allocating scaler
5597          * for NV12.
5598          */
5599         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
5600             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5601                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5602                 return -EINVAL;
5603         }
5604
5605         /*
5606          * if plane is being disabled or scaler is no more required or force detach
5607          *  - free scaler binded to this plane/crtc
5608          *  - in order to do this, update crtc->scaler_usage
5609          *
5610          * Here scaler state in crtc_state is set free so that
5611          * scaler can be assigned to other user. Actual register
5612          * update to free the scaler is done in plane/panel-fit programming.
5613          * For this purpose crtc/plane_state->scaler_id isn't reset here.
5614          */
5615         if (force_detach || !need_scaler) {
5616                 if (*scaler_id >= 0) {
5617                         scaler_state->scaler_users &= ~(1 << scaler_user);
5618                         scaler_state->scalers[*scaler_id].in_use = 0;
5619
5620                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5621                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5622                                 intel_crtc->pipe, scaler_user, *scaler_id,
5623                                 scaler_state->scaler_users);
5624                         *scaler_id = -1;
5625                 }
5626                 return 0;
5627         }
5628
5629         if (format && drm_format_info_is_yuv_semiplanar(format) &&
5630             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5631                 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5632                 return -EINVAL;
5633         }
5634
5635         /* range checks */
5636         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5637             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5638             (INTEL_GEN(dev_priv) >= 11 &&
5639              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5640               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5641             (INTEL_GEN(dev_priv) < 11 &&
5642              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5643               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5644                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5645                         "size is out of scaler range\n",
5646                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5647                 return -EINVAL;
5648         }
5649
5650         /* mark this plane as a scaler user in crtc_state */
5651         scaler_state->scaler_users |= (1 << scaler_user);
5652         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5653                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5654                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5655                 scaler_state->scaler_users);
5656
5657         return 0;
5658 }
5659
5660 /**
5661  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5662  *
5663  * @state: crtc's scaler state
5664  *
5665  * Return
5666  *     0 - scaler_usage updated successfully
5667  *    error - requested scaling cannot be supported or other error condition
5668  */
5669 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5670 {
5671         const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
5672         bool need_scaler = false;
5673
5674         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5675                 need_scaler = true;
5676
5677         return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
5678                                  &state->scaler_state.scaler_id,
5679                                  state->pipe_src_w, state->pipe_src_h,
5680                                  adjusted_mode->crtc_hdisplay,
5681                                  adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5682 }
5683
5684 /**
5685  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5686  * @crtc_state: crtc's scaler state
5687  * @plane_state: atomic plane state to update
5688  *
5689  * Return
5690  *     0 - scaler_usage updated successfully
5691  *    error - requested scaling cannot be supported or other error condition
5692  */
5693 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5694                                    struct intel_plane_state *plane_state)
5695 {
5696         struct intel_plane *intel_plane =
5697                 to_intel_plane(plane_state->uapi.plane);
5698         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5699         struct drm_framebuffer *fb = plane_state->hw.fb;
5700         int ret;
5701         bool force_detach = !fb || !plane_state->uapi.visible;
5702         bool need_scaler = false;
5703
5704         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5705         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5706             fb && drm_format_info_is_yuv_semiplanar(fb->format))
5707                 need_scaler = true;
5708
5709         ret = skl_update_scaler(crtc_state, force_detach,
5710                                 drm_plane_index(&intel_plane->base),
5711                                 &plane_state->scaler_id,
5712                                 drm_rect_width(&plane_state->uapi.src) >> 16,
5713                                 drm_rect_height(&plane_state->uapi.src) >> 16,
5714                                 drm_rect_width(&plane_state->uapi.dst),
5715                                 drm_rect_height(&plane_state->uapi.dst),
5716                                 fb ? fb->format : NULL, need_scaler);
5717
5718         if (ret || plane_state->scaler_id < 0)
5719                 return ret;
5720
5721         /* check colorkey */
5722         if (plane_state->ckey.flags) {
5723                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5724                               intel_plane->base.base.id,
5725                               intel_plane->base.name);
5726                 return -EINVAL;
5727         }
5728
5729         /* Check src format */
5730         switch (fb->format->format) {
5731         case DRM_FORMAT_RGB565:
5732         case DRM_FORMAT_XBGR8888:
5733         case DRM_FORMAT_XRGB8888:
5734         case DRM_FORMAT_ABGR8888:
5735         case DRM_FORMAT_ARGB8888:
5736         case DRM_FORMAT_XRGB2101010:
5737         case DRM_FORMAT_XBGR2101010:
5738         case DRM_FORMAT_ARGB2101010:
5739         case DRM_FORMAT_ABGR2101010:
5740         case DRM_FORMAT_YUYV:
5741         case DRM_FORMAT_YVYU:
5742         case DRM_FORMAT_UYVY:
5743         case DRM_FORMAT_VYUY:
5744         case DRM_FORMAT_NV12:
5745         case DRM_FORMAT_P010:
5746         case DRM_FORMAT_P012:
5747         case DRM_FORMAT_P016:
5748         case DRM_FORMAT_Y210:
5749         case DRM_FORMAT_Y212:
5750         case DRM_FORMAT_Y216:
5751         case DRM_FORMAT_XVYU2101010:
5752         case DRM_FORMAT_XVYU12_16161616:
5753         case DRM_FORMAT_XVYU16161616:
5754                 break;
5755         case DRM_FORMAT_XBGR16161616F:
5756         case DRM_FORMAT_ABGR16161616F:
5757         case DRM_FORMAT_XRGB16161616F:
5758         case DRM_FORMAT_ARGB16161616F:
5759                 if (INTEL_GEN(dev_priv) >= 11)
5760                         break;
5761                 /* fall through */
5762         default:
5763                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5764                               intel_plane->base.base.id, intel_plane->base.name,
5765                               fb->base.id, fb->format->format);
5766                 return -EINVAL;
5767         }
5768
5769         return 0;
5770 }
5771
5772 static void skylake_scaler_disable(struct intel_crtc *crtc)
5773 {
5774         int i;
5775
5776         for (i = 0; i < crtc->num_scalers; i++)
5777                 skl_detach_scaler(crtc, i);
5778 }
5779
5780 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5781 {
5782         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5783         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5784         enum pipe pipe = crtc->pipe;
5785         const struct intel_crtc_scaler_state *scaler_state =
5786                 &crtc_state->scaler_state;
5787
5788         if (crtc_state->pch_pfit.enabled) {
5789                 u16 uv_rgb_hphase, uv_rgb_vphase;
5790                 int pfit_w, pfit_h, hscale, vscale;
5791                 int id;
5792
5793                 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5794                         return;
5795
5796                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5797                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5798
5799                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5800                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5801
5802                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5803                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5804
5805                 id = scaler_state->scaler_id;
5806                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5807                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5808                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5809                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5810                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5811                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5812                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5813                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5814         }
5815 }
5816
5817 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5818 {
5819         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5820         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5821         enum pipe pipe = crtc->pipe;
5822
5823         if (crtc_state->pch_pfit.enabled) {
5824                 /* Force use of hard-coded filter coefficients
5825                  * as some pre-programmed values are broken,
5826                  * e.g. x201.
5827                  */
5828                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5829                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5830                                                  PF_PIPE_SEL_IVB(pipe));
5831                 else
5832                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5833                 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5834                 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5835         }
5836 }
5837
5838 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5839 {
5840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5841         struct drm_device *dev = crtc->base.dev;
5842         struct drm_i915_private *dev_priv = to_i915(dev);
5843
5844         if (!crtc_state->ips_enabled)
5845                 return;
5846
5847         /*
5848          * We can only enable IPS after we enable a plane and wait for a vblank
5849          * This function is called from post_plane_update, which is run after
5850          * a vblank wait.
5851          */
5852         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5853
5854         if (IS_BROADWELL(dev_priv)) {
5855                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5856                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5857                 /* Quoting Art Runyan: "its not safe to expect any particular
5858                  * value in IPS_CTL bit 31 after enabling IPS through the
5859                  * mailbox." Moreover, the mailbox may return a bogus state,
5860                  * so we need to just enable it and continue on.
5861                  */
5862         } else {
5863                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5864                 /* The bit only becomes 1 in the next vblank, so this wait here
5865                  * is essentially intel_wait_for_vblank. If we don't have this
5866                  * and don't wait for vblanks until the end of crtc_enable, then
5867                  * the HW state readout code will complain that the expected
5868                  * IPS_CTL value is not the one we read. */
5869                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5870                         DRM_ERROR("Timed out waiting for IPS enable\n");
5871         }
5872 }
5873
5874 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5875 {
5876         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5877         struct drm_device *dev = crtc->base.dev;
5878         struct drm_i915_private *dev_priv = to_i915(dev);
5879
5880         if (!crtc_state->ips_enabled)
5881                 return;
5882
5883         if (IS_BROADWELL(dev_priv)) {
5884                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5885                 /*
5886                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5887                  * 42ms timeout value leads to occasional timeouts so use 100ms
5888                  * instead.
5889                  */
5890                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5891                         DRM_ERROR("Timed out waiting for IPS disable\n");
5892         } else {
5893                 I915_WRITE(IPS_CTL, 0);
5894                 POSTING_READ(IPS_CTL);
5895         }
5896
5897         /* We need to wait for a vblank before we can disable the plane. */
5898         intel_wait_for_vblank(dev_priv, crtc->pipe);
5899 }
5900
5901 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5902 {
5903         if (intel_crtc->overlay)
5904                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5905
5906         /* Let userspace switch the overlay on again. In most cases userspace
5907          * has to recompute where to put it anyway.
5908          */
5909 }
5910
5911 /**
5912  * intel_post_enable_primary - Perform operations after enabling primary plane
5913  * @crtc: the CRTC whose primary plane was just enabled
5914  * @new_crtc_state: the enabling state
5915  *
5916  * Performs potentially sleeping operations that must be done after the primary
5917  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5918  * called due to an explicit primary plane update, or due to an implicit
5919  * re-enable that is caused when a sprite plane is updated to no longer
5920  * completely hide the primary plane.
5921  */
5922 static void
5923 intel_post_enable_primary(struct drm_crtc *crtc,
5924                           const struct intel_crtc_state *new_crtc_state)
5925 {
5926         struct drm_device *dev = crtc->dev;
5927         struct drm_i915_private *dev_priv = to_i915(dev);
5928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5929         enum pipe pipe = intel_crtc->pipe;
5930
5931         /*
5932          * Gen2 reports pipe underruns whenever all planes are disabled.
5933          * So don't enable underrun reporting before at least some planes
5934          * are enabled.
5935          * FIXME: Need to fix the logic to work when we turn off all planes
5936          * but leave the pipe running.
5937          */
5938         if (IS_GEN(dev_priv, 2))
5939                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5940
5941         /* Underruns don't always raise interrupts, so check manually. */
5942         intel_check_cpu_fifo_underruns(dev_priv);
5943         intel_check_pch_fifo_underruns(dev_priv);
5944 }
5945
5946 /* FIXME get rid of this and use pre_plane_update */
5947 static void
5948 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5949 {
5950         struct drm_device *dev = crtc->dev;
5951         struct drm_i915_private *dev_priv = to_i915(dev);
5952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5953         enum pipe pipe = intel_crtc->pipe;
5954
5955         /*
5956          * Gen2 reports pipe underruns whenever all planes are disabled.
5957          * So disable underrun reporting before all the planes get disabled.
5958          */
5959         if (IS_GEN(dev_priv, 2))
5960                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5961
5962         hsw_disable_ips(to_intel_crtc_state(crtc->state));
5963
5964         /*
5965          * Vblank time updates from the shadow to live plane control register
5966          * are blocked if the memory self-refresh mode is active at that
5967          * moment. So to make sure the plane gets truly disabled, disable
5968          * first the self-refresh mode. The self-refresh enable bit in turn
5969          * will be checked/applied by the HW only at the next frame start
5970          * event which is after the vblank start event, so we need to have a
5971          * wait-for-vblank between disabling the plane and the pipe.
5972          */
5973         if (HAS_GMCH(dev_priv) &&
5974             intel_set_memory_cxsr(dev_priv, false))
5975                 intel_wait_for_vblank(dev_priv, pipe);
5976 }
5977
5978 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5979                                        const struct intel_crtc_state *new_crtc_state)
5980 {
5981         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5982         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5983
5984         if (!old_crtc_state->ips_enabled)
5985                 return false;
5986
5987         if (needs_modeset(new_crtc_state))
5988                 return true;
5989
5990         /*
5991          * Workaround : Do not read or write the pipe palette/gamma data while
5992          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5993          *
5994          * Disable IPS before we program the LUT.
5995          */
5996         if (IS_HASWELL(dev_priv) &&
5997             (new_crtc_state->uapi.color_mgmt_changed ||
5998              new_crtc_state->update_pipe) &&
5999             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6000                 return true;
6001
6002         return !new_crtc_state->ips_enabled;
6003 }
6004
6005 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6006                                        const struct intel_crtc_state *new_crtc_state)
6007 {
6008         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6009         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6010
6011         if (!new_crtc_state->ips_enabled)
6012                 return false;
6013
6014         if (needs_modeset(new_crtc_state))
6015                 return true;
6016
6017         /*
6018          * Workaround : Do not read or write the pipe palette/gamma data while
6019          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6020          *
6021          * Re-enable IPS after the LUT has been programmed.
6022          */
6023         if (IS_HASWELL(dev_priv) &&
6024             (new_crtc_state->uapi.color_mgmt_changed ||
6025              new_crtc_state->update_pipe) &&
6026             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6027                 return true;
6028
6029         /*
6030          * We can't read out IPS on broadwell, assume the worst and
6031          * forcibly enable IPS on the first fastset.
6032          */
6033         if (new_crtc_state->update_pipe &&
6034             old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
6035                 return true;
6036
6037         return !old_crtc_state->ips_enabled;
6038 }
6039
6040 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
6041                           const struct intel_crtc_state *crtc_state)
6042 {
6043         if (!crtc_state->nv12_planes)
6044                 return false;
6045
6046         /* WA Display #0827: Gen9:all */
6047         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6048                 return true;
6049
6050         return false;
6051 }
6052
6053 static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
6054                                const struct intel_crtc_state *crtc_state)
6055 {
6056         /* Wa_2006604312:icl */
6057         if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
6058                 return true;
6059
6060         return false;
6061 }
6062
6063 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
6064 {
6065         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6066         struct drm_device *dev = crtc->base.dev;
6067         struct drm_i915_private *dev_priv = to_i915(dev);
6068         struct drm_atomic_state *state = old_crtc_state->uapi.state;
6069         struct intel_crtc_state *pipe_config =
6070                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
6071                                                 crtc);
6072         struct drm_plane *primary = crtc->base.primary;
6073         struct drm_plane_state *old_primary_state =
6074                 drm_atomic_get_old_plane_state(state, primary);
6075
6076         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
6077
6078         if (pipe_config->update_wm_post && pipe_config->hw.active)
6079                 intel_update_watermarks(crtc);
6080
6081         if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
6082                 hsw_enable_ips(pipe_config);
6083
6084         if (old_primary_state) {
6085                 struct drm_plane_state *new_primary_state =
6086                         drm_atomic_get_new_plane_state(state, primary);
6087
6088                 intel_fbc_post_update(crtc);
6089
6090                 if (new_primary_state->visible &&
6091                     (needs_modeset(pipe_config) ||
6092                      !old_primary_state->visible))
6093                         intel_post_enable_primary(&crtc->base, pipe_config);
6094         }
6095
6096         if (needs_nv12_wa(dev_priv, old_crtc_state) &&
6097             !needs_nv12_wa(dev_priv, pipe_config))
6098                 skl_wa_827(dev_priv, crtc->pipe, false);
6099
6100         if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
6101             !needs_scalerclk_wa(dev_priv, pipe_config))
6102                 icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
6103 }
6104
6105 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
6106                                    struct intel_crtc_state *pipe_config)
6107 {
6108         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6109         struct drm_device *dev = crtc->base.dev;
6110         struct drm_i915_private *dev_priv = to_i915(dev);
6111         struct drm_atomic_state *state = old_crtc_state->uapi.state;
6112         struct drm_plane *primary = crtc->base.primary;
6113         struct drm_plane_state *old_primary_state =
6114                 drm_atomic_get_old_plane_state(state, primary);
6115         bool modeset = needs_modeset(pipe_config);
6116         struct intel_atomic_state *intel_state =
6117                 to_intel_atomic_state(state);
6118
6119         if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
6120                 hsw_disable_ips(old_crtc_state);
6121
6122         if (old_primary_state) {
6123                 struct intel_plane_state *new_primary_state =
6124                         intel_atomic_get_new_plane_state(intel_state,
6125                                                          to_intel_plane(primary));
6126
6127                 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
6128                 /*
6129                  * Gen2 reports pipe underruns whenever all planes are disabled.
6130                  * So disable underrun reporting before all the planes get disabled.
6131                  */
6132                 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
6133                     (modeset || !new_primary_state->uapi.visible))
6134                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
6135         }
6136
6137         /* Display WA 827 */
6138         if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
6139             needs_nv12_wa(dev_priv, pipe_config))
6140                 skl_wa_827(dev_priv, crtc->pipe, true);
6141
6142         /* Wa_2006604312:icl */
6143         if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
6144             needs_scalerclk_wa(dev_priv, pipe_config))
6145                 icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
6146
6147         /*
6148          * Vblank time updates from the shadow to live plane control register
6149          * are blocked if the memory self-refresh mode is active at that
6150          * moment. So to make sure the plane gets truly disabled, disable
6151          * first the self-refresh mode. The self-refresh enable bit in turn
6152          * will be checked/applied by the HW only at the next frame start
6153          * event which is after the vblank start event, so we need to have a
6154          * wait-for-vblank between disabling the plane and the pipe.
6155          */
6156         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6157             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6158                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6159
6160         /*
6161          * IVB workaround: must disable low power watermarks for at least
6162          * one frame before enabling scaling.  LP watermarks can be re-enabled
6163          * when scaling is disabled.
6164          *
6165          * WaCxSRDisabledForSpriteScaling:ivb
6166          */
6167         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
6168             old_crtc_state->hw.active)
6169                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6170
6171         /*
6172          * If we're doing a modeset, we're done.  No need to do any pre-vblank
6173          * watermark programming here.
6174          */
6175         if (needs_modeset(pipe_config))
6176                 return;
6177
6178         /*
6179          * For platforms that support atomic watermarks, program the
6180          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6181          * will be the intermediate values that are safe for both pre- and
6182          * post- vblank; when vblank happens, the 'active' values will be set
6183          * to the final 'target' values and we'll do this again to get the
6184          * optimal watermarks.  For gen9+ platforms, the values we program here
6185          * will be the final target values which will get automatically latched
6186          * at vblank time; no further programming will be necessary.
6187          *
6188          * If a platform hasn't been transitioned to atomic watermarks yet,
6189          * we'll continue to update watermarks the old way, if flags tell
6190          * us to.
6191          */
6192         if (dev_priv->display.initial_watermarks)
6193                 dev_priv->display.initial_watermarks(intel_state, crtc);
6194         else if (pipe_config->update_wm_pre)
6195                 intel_update_watermarks(crtc);
6196 }
6197
6198 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6199                                       struct intel_crtc *crtc)
6200 {
6201         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6202         const struct intel_crtc_state *new_crtc_state =
6203                 intel_atomic_get_new_crtc_state(state, crtc);
6204         unsigned int update_mask = new_crtc_state->update_planes;
6205         const struct intel_plane_state *old_plane_state;
6206         struct intel_plane *plane;
6207         unsigned fb_bits = 0;
6208         int i;
6209
6210         intel_crtc_dpms_overlay_disable(crtc);
6211
6212         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6213                 if (crtc->pipe != plane->pipe ||
6214                     !(update_mask & BIT(plane->id)))
6215                         continue;
6216
6217                 intel_disable_plane(plane, new_crtc_state);
6218
6219                 if (old_plane_state->uapi.visible)
6220                         fb_bits |= plane->frontbuffer_bit;
6221         }
6222
6223         intel_frontbuffer_flip(dev_priv, fb_bits);
6224 }
6225
6226 /*
6227  * intel_connector_primary_encoder - get the primary encoder for a connector
6228  * @connector: connector for which to return the encoder
6229  *
6230  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6231  * all connectors to their encoder, except for DP-MST connectors which have
6232  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6233  * pointed to by as many DP-MST connectors as there are pipes.
6234  */
6235 static struct intel_encoder *
6236 intel_connector_primary_encoder(struct intel_connector *connector)
6237 {
6238         struct intel_encoder *encoder;
6239
6240         if (connector->mst_port)
6241                 return &dp_to_dig_port(connector->mst_port)->base;
6242
6243         encoder = intel_attached_encoder(&connector->base);
6244         WARN_ON(!encoder);
6245
6246         return encoder;
6247 }
6248
6249 static bool
6250 intel_connector_needs_modeset(struct intel_atomic_state *state,
6251                               const struct drm_connector_state *old_conn_state,
6252                               const struct drm_connector_state *new_conn_state)
6253 {
6254         struct intel_crtc *old_crtc = old_conn_state->crtc ?
6255                                       to_intel_crtc(old_conn_state->crtc) : NULL;
6256         struct intel_crtc *new_crtc = new_conn_state->crtc ?
6257                                       to_intel_crtc(new_conn_state->crtc) : NULL;
6258
6259         return new_crtc != old_crtc ||
6260                (new_crtc &&
6261                 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6262 }
6263
6264 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6265 {
6266         struct drm_connector_state *old_conn_state;
6267         struct drm_connector_state *new_conn_state;
6268         struct drm_connector *conn;
6269         int i;
6270
6271         for_each_oldnew_connector_in_state(&state->base, conn,
6272                                            old_conn_state, new_conn_state, i) {
6273                 struct intel_encoder *encoder;
6274                 struct intel_crtc *crtc;
6275
6276                 if (!intel_connector_needs_modeset(state,
6277                                                    old_conn_state,
6278                                                    new_conn_state))
6279                         continue;
6280
6281                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6282                 if (!encoder->update_prepare)
6283                         continue;
6284
6285                 crtc = new_conn_state->crtc ?
6286                         to_intel_crtc(new_conn_state->crtc) : NULL;
6287                 encoder->update_prepare(state, encoder, crtc);
6288         }
6289 }
6290
6291 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6292 {
6293         struct drm_connector_state *old_conn_state;
6294         struct drm_connector_state *new_conn_state;
6295         struct drm_connector *conn;
6296         int i;
6297
6298         for_each_oldnew_connector_in_state(&state->base, conn,
6299                                            old_conn_state, new_conn_state, i) {
6300                 struct intel_encoder *encoder;
6301                 struct intel_crtc *crtc;
6302
6303                 if (!intel_connector_needs_modeset(state,
6304                                                    old_conn_state,
6305                                                    new_conn_state))
6306                         continue;
6307
6308                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6309                 if (!encoder->update_complete)
6310                         continue;
6311
6312                 crtc = new_conn_state->crtc ?
6313                         to_intel_crtc(new_conn_state->crtc) : NULL;
6314                 encoder->update_complete(state, encoder, crtc);
6315         }
6316 }
6317
6318 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6319                                           struct intel_crtc *crtc)
6320 {
6321         const struct intel_crtc_state *crtc_state =
6322                 intel_atomic_get_new_crtc_state(state, crtc);
6323         const struct drm_connector_state *conn_state;
6324         struct drm_connector *conn;
6325         int i;
6326
6327         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6328                 struct intel_encoder *encoder =
6329                         to_intel_encoder(conn_state->best_encoder);
6330
6331                 if (conn_state->crtc != &crtc->base)
6332                         continue;
6333
6334                 if (encoder->pre_pll_enable)
6335                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6336         }
6337 }
6338
6339 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6340                                       struct intel_crtc *crtc)
6341 {
6342         const struct intel_crtc_state *crtc_state =
6343                 intel_atomic_get_new_crtc_state(state, crtc);
6344         const struct drm_connector_state *conn_state;
6345         struct drm_connector *conn;
6346         int i;
6347
6348         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6349                 struct intel_encoder *encoder =
6350                         to_intel_encoder(conn_state->best_encoder);
6351
6352                 if (conn_state->crtc != &crtc->base)
6353                         continue;
6354
6355                 if (encoder->pre_enable)
6356                         encoder->pre_enable(encoder, crtc_state, conn_state);
6357         }
6358 }
6359
6360 static void intel_encoders_enable(struct intel_atomic_state *state,
6361                                   struct intel_crtc *crtc)
6362 {
6363         const struct intel_crtc_state *crtc_state =
6364                 intel_atomic_get_new_crtc_state(state, crtc);
6365         const struct drm_connector_state *conn_state;
6366         struct drm_connector *conn;
6367         int i;
6368
6369         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6370                 struct intel_encoder *encoder =
6371                         to_intel_encoder(conn_state->best_encoder);
6372
6373                 if (conn_state->crtc != &crtc->base)
6374                         continue;
6375
6376                 if (encoder->enable)
6377                         encoder->enable(encoder, crtc_state, conn_state);
6378                 intel_opregion_notify_encoder(encoder, true);
6379         }
6380 }
6381
6382 static void intel_encoders_disable(struct intel_atomic_state *state,
6383                                    struct intel_crtc *crtc)
6384 {
6385         const struct intel_crtc_state *old_crtc_state =
6386                 intel_atomic_get_old_crtc_state(state, crtc);
6387         const struct drm_connector_state *old_conn_state;
6388         struct drm_connector *conn;
6389         int i;
6390
6391         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6392                 struct intel_encoder *encoder =
6393                         to_intel_encoder(old_conn_state->best_encoder);
6394
6395                 if (old_conn_state->crtc != &crtc->base)
6396                         continue;
6397
6398                 intel_opregion_notify_encoder(encoder, false);
6399                 if (encoder->disable)
6400                         encoder->disable(encoder, old_crtc_state, old_conn_state);
6401         }
6402 }
6403
6404 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6405                                         struct intel_crtc *crtc)
6406 {
6407         const struct intel_crtc_state *old_crtc_state =
6408                 intel_atomic_get_old_crtc_state(state, crtc);
6409         const struct drm_connector_state *old_conn_state;
6410         struct drm_connector *conn;
6411         int i;
6412
6413         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6414                 struct intel_encoder *encoder =
6415                         to_intel_encoder(old_conn_state->best_encoder);
6416
6417                 if (old_conn_state->crtc != &crtc->base)
6418                         continue;
6419
6420                 if (encoder->post_disable)
6421                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6422         }
6423 }
6424
6425 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6426                                             struct intel_crtc *crtc)
6427 {
6428         const struct intel_crtc_state *old_crtc_state =
6429                 intel_atomic_get_old_crtc_state(state, crtc);
6430         const struct drm_connector_state *old_conn_state;
6431         struct drm_connector *conn;
6432         int i;
6433
6434         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6435                 struct intel_encoder *encoder =
6436                         to_intel_encoder(old_conn_state->best_encoder);
6437
6438                 if (old_conn_state->crtc != &crtc->base)
6439                         continue;
6440
6441                 if (encoder->post_pll_disable)
6442                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6443         }
6444 }
6445
6446 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6447                                        struct intel_crtc *crtc)
6448 {
6449         const struct intel_crtc_state *crtc_state =
6450                 intel_atomic_get_new_crtc_state(state, crtc);
6451         const struct drm_connector_state *conn_state;
6452         struct drm_connector *conn;
6453         int i;
6454
6455         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6456                 struct intel_encoder *encoder =
6457                         to_intel_encoder(conn_state->best_encoder);
6458
6459                 if (conn_state->crtc != &crtc->base)
6460                         continue;
6461
6462                 if (encoder->update_pipe)
6463                         encoder->update_pipe(encoder, crtc_state, conn_state);
6464         }
6465 }
6466
6467 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6468 {
6469         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6470         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6471
6472         plane->disable_plane(plane, crtc_state);
6473 }
6474
6475 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
6476                                  struct intel_atomic_state *state)
6477 {
6478         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
6479         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6480         enum pipe pipe = crtc->pipe;
6481
6482         if (WARN_ON(crtc->active))
6483                 return;
6484
6485         /*
6486          * Sometimes spurious CPU pipe underruns happen during FDI
6487          * training, at least with VGA+HDMI cloning. Suppress them.
6488          *
6489          * On ILK we get an occasional spurious CPU pipe underruns
6490          * between eDP port A enable and vdd enable. Also PCH port
6491          * enable seems to result in the occasional CPU pipe underrun.
6492          *
6493          * Spurious PCH underruns also occur during PCH enabling.
6494          */
6495         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6496         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6497
6498         if (pipe_config->has_pch_encoder)
6499                 intel_prepare_shared_dpll(pipe_config);
6500
6501         if (intel_crtc_has_dp_encoder(pipe_config))
6502                 intel_dp_set_m_n(pipe_config, M1_N1);
6503
6504         intel_set_pipe_timings(pipe_config);
6505         intel_set_pipe_src_size(pipe_config);
6506
6507         if (pipe_config->has_pch_encoder) {
6508                 intel_cpu_transcoder_set_m_n(pipe_config,
6509                                              &pipe_config->fdi_m_n, NULL);
6510         }
6511
6512         ironlake_set_pipeconf(pipe_config);
6513
6514         crtc->active = true;
6515
6516         intel_encoders_pre_enable(state, crtc);
6517
6518         if (pipe_config->has_pch_encoder) {
6519                 /* Note: FDI PLL enabling _must_ be done before we enable the
6520                  * cpu pipes, hence this is separate from all the other fdi/pch
6521                  * enabling. */
6522                 ironlake_fdi_pll_enable(pipe_config);
6523         } else {
6524                 assert_fdi_tx_disabled(dev_priv, pipe);
6525                 assert_fdi_rx_disabled(dev_priv, pipe);
6526         }
6527
6528         ironlake_pfit_enable(pipe_config);
6529
6530         /*
6531          * On ILK+ LUT must be loaded before the pipe is running but with
6532          * clocks enabled
6533          */
6534         intel_color_load_luts(pipe_config);
6535         intel_color_commit(pipe_config);
6536         /* update DSPCNTR to configure gamma for pipe bottom color */
6537         intel_disable_primary_plane(pipe_config);
6538
6539         if (dev_priv->display.initial_watermarks)
6540                 dev_priv->display.initial_watermarks(state, crtc);
6541         intel_enable_pipe(pipe_config);
6542
6543         if (pipe_config->has_pch_encoder)
6544                 ironlake_pch_enable(state, pipe_config);
6545
6546         intel_crtc_vblank_on(pipe_config);
6547
6548         intel_encoders_enable(state, crtc);
6549
6550         if (HAS_PCH_CPT(dev_priv))
6551                 cpt_verify_modeset(dev_priv, pipe);
6552
6553         /*
6554          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6555          * And a second vblank wait is needed at least on ILK with
6556          * some interlaced HDMI modes. Let's do the double wait always
6557          * in case there are more corner cases we don't know about.
6558          */
6559         if (pipe_config->has_pch_encoder) {
6560                 intel_wait_for_vblank(dev_priv, pipe);
6561                 intel_wait_for_vblank(dev_priv, pipe);
6562         }
6563         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6564         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6565 }
6566
6567 /* IPS only exists on ULT machines and is tied to pipe A. */
6568 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6569 {
6570         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6571 }
6572
6573 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6574                                             enum pipe pipe, bool apply)
6575 {
6576         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6577         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6578
6579         if (apply)
6580                 val |= mask;
6581         else
6582                 val &= ~mask;
6583
6584         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6585 }
6586
6587 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6588 {
6589         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6590         enum pipe pipe = crtc->pipe;
6591         u32 val;
6592
6593         val = MBUS_DBOX_A_CREDIT(2);
6594
6595         if (INTEL_GEN(dev_priv) >= 12) {
6596                 val |= MBUS_DBOX_BW_CREDIT(2);
6597                 val |= MBUS_DBOX_B_CREDIT(12);
6598         } else {
6599                 val |= MBUS_DBOX_BW_CREDIT(1);
6600                 val |= MBUS_DBOX_B_CREDIT(8);
6601         }
6602
6603         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6604 }
6605
6606 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
6607 {
6608         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6610         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
6611         u32 val;
6612
6613         val = I915_READ(reg);
6614         val &= ~HSW_FRAME_START_DELAY_MASK;
6615         val |= HSW_FRAME_START_DELAY(0);
6616         I915_WRITE(reg, val);
6617 }
6618
6619 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
6620                                 struct intel_atomic_state *state)
6621 {
6622         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
6623         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6624         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
6625         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6626         bool psl_clkgate_wa;
6627
6628         if (WARN_ON(crtc->active))
6629                 return;
6630
6631         intel_encoders_pre_pll_enable(state, crtc);
6632
6633         if (pipe_config->shared_dpll)
6634                 intel_enable_shared_dpll(pipe_config);
6635
6636         intel_encoders_pre_enable(state, crtc);
6637
6638         if (intel_crtc_has_dp_encoder(pipe_config))
6639                 intel_dp_set_m_n(pipe_config, M1_N1);
6640
6641         if (!transcoder_is_dsi(cpu_transcoder))
6642                 intel_set_pipe_timings(pipe_config);
6643
6644         if (INTEL_GEN(dev_priv) >= 11)
6645                 icl_enable_trans_port_sync(pipe_config);
6646
6647         intel_set_pipe_src_size(pipe_config);
6648
6649         if (cpu_transcoder != TRANSCODER_EDP &&
6650             !transcoder_is_dsi(cpu_transcoder)) {
6651                 I915_WRITE(PIPE_MULT(cpu_transcoder),
6652                            pipe_config->pixel_multiplier - 1);
6653         }
6654
6655         if (pipe_config->has_pch_encoder) {
6656                 intel_cpu_transcoder_set_m_n(pipe_config,
6657                                              &pipe_config->fdi_m_n, NULL);
6658         }
6659
6660         if (!transcoder_is_dsi(cpu_transcoder)) {
6661                 hsw_set_frame_start_delay(pipe_config);
6662                 haswell_set_pipeconf(pipe_config);
6663         }
6664
6665         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6666                 bdw_set_pipemisc(pipe_config);
6667
6668         crtc->active = true;
6669
6670         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6671         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6672                          pipe_config->pch_pfit.enabled;
6673         if (psl_clkgate_wa)
6674                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6675
6676         if (INTEL_GEN(dev_priv) >= 9)
6677                 skylake_pfit_enable(pipe_config);
6678         else
6679                 ironlake_pfit_enable(pipe_config);
6680
6681         /*
6682          * On ILK+ LUT must be loaded before the pipe is running but with
6683          * clocks enabled
6684          */
6685         intel_color_load_luts(pipe_config);
6686         intel_color_commit(pipe_config);
6687         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6688         if (INTEL_GEN(dev_priv) < 9)
6689                 intel_disable_primary_plane(pipe_config);
6690
6691         if (INTEL_GEN(dev_priv) >= 11)
6692                 icl_set_pipe_chicken(crtc);
6693
6694         if (!transcoder_is_dsi(cpu_transcoder))
6695                 intel_ddi_enable_transcoder_func(pipe_config);
6696
6697         if (dev_priv->display.initial_watermarks)
6698                 dev_priv->display.initial_watermarks(state, crtc);
6699
6700         if (INTEL_GEN(dev_priv) >= 11)
6701                 icl_pipe_mbus_enable(crtc);
6702
6703         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6704         if (!transcoder_is_dsi(cpu_transcoder))
6705                 intel_enable_pipe(pipe_config);
6706
6707         if (pipe_config->has_pch_encoder)
6708                 lpt_pch_enable(state, pipe_config);
6709
6710         intel_crtc_vblank_on(pipe_config);
6711
6712         intel_encoders_enable(state, crtc);
6713
6714         if (psl_clkgate_wa) {
6715                 intel_wait_for_vblank(dev_priv, pipe);
6716                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6717         }
6718
6719         /* If we change the relative order between pipe/planes enabling, we need
6720          * to change the workaround. */
6721         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
6722         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6723                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6724                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6725         }
6726 }
6727
6728 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6729 {
6730         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6731         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6732         enum pipe pipe = crtc->pipe;
6733
6734         /* To avoid upsetting the power well on haswell only disable the pfit if
6735          * it's in use. The hw state code will make sure we get this right. */
6736         if (old_crtc_state->pch_pfit.enabled) {
6737                 I915_WRITE(PF_CTL(pipe), 0);
6738                 I915_WRITE(PF_WIN_POS(pipe), 0);
6739                 I915_WRITE(PF_WIN_SZ(pipe), 0);
6740         }
6741 }
6742
6743 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6744                                   struct intel_atomic_state *state)
6745 {
6746         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6747         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6748         enum pipe pipe = crtc->pipe;
6749
6750         /*
6751          * Sometimes spurious CPU pipe underruns happen when the
6752          * pipe is already disabled, but FDI RX/TX is still enabled.
6753          * Happens at least with VGA+HDMI cloning. Suppress them.
6754          */
6755         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6756         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6757
6758         intel_encoders_disable(state, crtc);
6759
6760         intel_crtc_vblank_off(crtc);
6761
6762         intel_disable_pipe(old_crtc_state);
6763
6764         ironlake_pfit_disable(old_crtc_state);
6765
6766         if (old_crtc_state->has_pch_encoder)
6767                 ironlake_fdi_disable(crtc);
6768
6769         intel_encoders_post_disable(state, crtc);
6770
6771         if (old_crtc_state->has_pch_encoder) {
6772                 ironlake_disable_pch_transcoder(dev_priv, pipe);
6773
6774                 if (HAS_PCH_CPT(dev_priv)) {
6775                         i915_reg_t reg;
6776                         u32 temp;
6777
6778                         /* disable TRANS_DP_CTL */
6779                         reg = TRANS_DP_CTL(pipe);
6780                         temp = I915_READ(reg);
6781                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6782                                   TRANS_DP_PORT_SEL_MASK);
6783                         temp |= TRANS_DP_PORT_SEL_NONE;
6784                         I915_WRITE(reg, temp);
6785
6786                         /* disable DPLL_SEL */
6787                         temp = I915_READ(PCH_DPLL_SEL);
6788                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6789                         I915_WRITE(PCH_DPLL_SEL, temp);
6790                 }
6791
6792                 ironlake_fdi_pll_disable(crtc);
6793         }
6794
6795         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6796         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6797 }
6798
6799 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6800                                  struct intel_atomic_state *state)
6801 {
6802         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6803         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6804         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6805
6806         intel_encoders_disable(state, crtc);
6807
6808         intel_crtc_vblank_off(crtc);
6809
6810         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6811         if (!transcoder_is_dsi(cpu_transcoder))
6812                 intel_disable_pipe(old_crtc_state);
6813
6814         if (INTEL_GEN(dev_priv) >= 11)
6815                 icl_disable_transcoder_port_sync(old_crtc_state);
6816
6817         if (!transcoder_is_dsi(cpu_transcoder))
6818                 intel_ddi_disable_transcoder_func(old_crtc_state);
6819
6820         intel_dsc_disable(old_crtc_state);
6821
6822         if (INTEL_GEN(dev_priv) >= 9)
6823                 skylake_scaler_disable(crtc);
6824         else
6825                 ironlake_pfit_disable(old_crtc_state);
6826
6827         intel_encoders_post_disable(state, crtc);
6828
6829         intel_encoders_post_pll_disable(state, crtc);
6830 }
6831
6832 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6833 {
6834         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6835         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6836
6837         if (!crtc_state->gmch_pfit.control)
6838                 return;
6839
6840         /*
6841          * The panel fitter should only be adjusted whilst the pipe is disabled,
6842          * according to register description and PRM.
6843          */
6844         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6845         assert_pipe_disabled(dev_priv, crtc->pipe);
6846
6847         I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6848         I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6849
6850         /* Border color in case we don't scale up to the full screen. Black by
6851          * default, change to something else for debugging. */
6852         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6853 }
6854
6855 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6856 {
6857         if (phy == PHY_NONE)
6858                 return false;
6859
6860         if (IS_ELKHARTLAKE(dev_priv))
6861                 return phy <= PHY_C;
6862
6863         if (INTEL_GEN(dev_priv) >= 11)
6864                 return phy <= PHY_B;
6865
6866         return false;
6867 }
6868
6869 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6870 {
6871         if (INTEL_GEN(dev_priv) >= 12)
6872                 return phy >= PHY_D && phy <= PHY_I;
6873
6874         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6875                 return phy >= PHY_C && phy <= PHY_F;
6876
6877         return false;
6878 }
6879
6880 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6881 {
6882         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6883                 return PHY_A;
6884
6885         return (enum phy)port;
6886 }
6887
6888 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6889 {
6890         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6891                 return PORT_TC_NONE;
6892
6893         if (INTEL_GEN(dev_priv) >= 12)
6894                 return port - PORT_D;
6895
6896         return port - PORT_C;
6897 }
6898
6899 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6900 {
6901         switch (port) {
6902         case PORT_A:
6903                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6904         case PORT_B:
6905                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6906         case PORT_C:
6907                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6908         case PORT_D:
6909                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6910         case PORT_E:
6911                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6912         case PORT_F:
6913                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6914         case PORT_G:
6915                 return POWER_DOMAIN_PORT_DDI_G_LANES;
6916         default:
6917                 MISSING_CASE(port);
6918                 return POWER_DOMAIN_PORT_OTHER;
6919         }
6920 }
6921
6922 enum intel_display_power_domain
6923 intel_aux_power_domain(struct intel_digital_port *dig_port)
6924 {
6925         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6926         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6927
6928         if (intel_phy_is_tc(dev_priv, phy) &&
6929             dig_port->tc_mode == TC_PORT_TBT_ALT) {
6930                 switch (dig_port->aux_ch) {
6931                 case AUX_CH_C:
6932                         return POWER_DOMAIN_AUX_C_TBT;
6933                 case AUX_CH_D:
6934                         return POWER_DOMAIN_AUX_D_TBT;
6935                 case AUX_CH_E:
6936                         return POWER_DOMAIN_AUX_E_TBT;
6937                 case AUX_CH_F:
6938                         return POWER_DOMAIN_AUX_F_TBT;
6939                 case AUX_CH_G:
6940                         return POWER_DOMAIN_AUX_G_TBT;
6941                 default:
6942                         MISSING_CASE(dig_port->aux_ch);
6943                         return POWER_DOMAIN_AUX_C_TBT;
6944                 }
6945         }
6946
6947         switch (dig_port->aux_ch) {
6948         case AUX_CH_A:
6949                 return POWER_DOMAIN_AUX_A;
6950         case AUX_CH_B:
6951                 return POWER_DOMAIN_AUX_B;
6952         case AUX_CH_C:
6953                 return POWER_DOMAIN_AUX_C;
6954         case AUX_CH_D:
6955                 return POWER_DOMAIN_AUX_D;
6956         case AUX_CH_E:
6957                 return POWER_DOMAIN_AUX_E;
6958         case AUX_CH_F:
6959                 return POWER_DOMAIN_AUX_F;
6960         case AUX_CH_G:
6961                 return POWER_DOMAIN_AUX_G;
6962         default:
6963                 MISSING_CASE(dig_port->aux_ch);
6964                 return POWER_DOMAIN_AUX_A;
6965         }
6966 }
6967
6968 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6969 {
6970         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6971         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6972         struct drm_encoder *encoder;
6973         enum pipe pipe = crtc->pipe;
6974         u64 mask;
6975         enum transcoder transcoder = crtc_state->cpu_transcoder;
6976
6977         if (!crtc_state->hw.active)
6978                 return 0;
6979
6980         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6981         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6982         if (crtc_state->pch_pfit.enabled ||
6983             crtc_state->pch_pfit.force_thru)
6984                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6985
6986         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6987                                   crtc_state->uapi.encoder_mask) {
6988                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6989
6990                 mask |= BIT_ULL(intel_encoder->power_domain);
6991         }
6992
6993         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6994                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6995
6996         if (crtc_state->shared_dpll)
6997                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6998
6999         return mask;
7000 }
7001
7002 static u64
7003 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7004 {
7005         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7006         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7007         enum intel_display_power_domain domain;
7008         u64 domains, new_domains, old_domains;
7009
7010         old_domains = crtc->enabled_power_domains;
7011         crtc->enabled_power_domains = new_domains =
7012                 get_crtc_power_domains(crtc_state);
7013
7014         domains = new_domains & ~old_domains;
7015
7016         for_each_power_domain(domain, domains)
7017                 intel_display_power_get(dev_priv, domain);
7018
7019         return old_domains & ~new_domains;
7020 }
7021
7022 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7023                                       u64 domains)
7024 {
7025         enum intel_display_power_domain domain;
7026
7027         for_each_power_domain(domain, domains)
7028                 intel_display_power_put_unchecked(dev_priv, domain);
7029 }
7030
7031 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
7032                                    struct intel_atomic_state *state)
7033 {
7034         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
7035         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7036         enum pipe pipe = crtc->pipe;
7037
7038         if (WARN_ON(crtc->active))
7039                 return;
7040
7041         if (intel_crtc_has_dp_encoder(pipe_config))
7042                 intel_dp_set_m_n(pipe_config, M1_N1);
7043
7044         intel_set_pipe_timings(pipe_config);
7045         intel_set_pipe_src_size(pipe_config);
7046
7047         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7048                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7049                 I915_WRITE(CHV_CANVAS(pipe), 0);
7050         }
7051
7052         i9xx_set_pipeconf(pipe_config);
7053
7054         crtc->active = true;
7055
7056         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7057
7058         intel_encoders_pre_pll_enable(state, crtc);
7059
7060         if (IS_CHERRYVIEW(dev_priv)) {
7061                 chv_prepare_pll(crtc, pipe_config);
7062                 chv_enable_pll(crtc, pipe_config);
7063         } else {
7064                 vlv_prepare_pll(crtc, pipe_config);
7065                 vlv_enable_pll(crtc, pipe_config);
7066         }
7067
7068         intel_encoders_pre_enable(state, crtc);
7069
7070         i9xx_pfit_enable(pipe_config);
7071
7072         intel_color_load_luts(pipe_config);
7073         intel_color_commit(pipe_config);
7074         /* update DSPCNTR to configure gamma for pipe bottom color */
7075         intel_disable_primary_plane(pipe_config);
7076
7077         dev_priv->display.initial_watermarks(state, crtc);
7078         intel_enable_pipe(pipe_config);
7079
7080         intel_crtc_vblank_on(pipe_config);
7081
7082         intel_encoders_enable(state, crtc);
7083 }
7084
7085 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7086 {
7087         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7088         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7089
7090         I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
7091         I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
7092 }
7093
7094 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
7095                              struct intel_atomic_state *state)
7096 {
7097         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
7098         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7099         enum pipe pipe = crtc->pipe;
7100
7101         if (WARN_ON(crtc->active))
7102                 return;
7103
7104         i9xx_set_pll_dividers(pipe_config);
7105
7106         if (intel_crtc_has_dp_encoder(pipe_config))
7107                 intel_dp_set_m_n(pipe_config, M1_N1);
7108
7109         intel_set_pipe_timings(pipe_config);
7110         intel_set_pipe_src_size(pipe_config);
7111
7112         i9xx_set_pipeconf(pipe_config);
7113
7114         crtc->active = true;
7115
7116         if (!IS_GEN(dev_priv, 2))
7117                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7118
7119         intel_encoders_pre_enable(state, crtc);
7120
7121         i9xx_enable_pll(crtc, pipe_config);
7122
7123         i9xx_pfit_enable(pipe_config);
7124
7125         intel_color_load_luts(pipe_config);
7126         intel_color_commit(pipe_config);
7127         /* update DSPCNTR to configure gamma for pipe bottom color */
7128         intel_disable_primary_plane(pipe_config);
7129
7130         if (dev_priv->display.initial_watermarks)
7131                 dev_priv->display.initial_watermarks(state, crtc);
7132         else
7133                 intel_update_watermarks(crtc);
7134         intel_enable_pipe(pipe_config);
7135
7136         intel_crtc_vblank_on(pipe_config);
7137
7138         intel_encoders_enable(state, crtc);
7139 }
7140
7141 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7142 {
7143         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7144         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7145
7146         if (!old_crtc_state->gmch_pfit.control)
7147                 return;
7148
7149         assert_pipe_disabled(dev_priv, crtc->pipe);
7150
7151         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
7152                       I915_READ(PFIT_CONTROL));
7153         I915_WRITE(PFIT_CONTROL, 0);
7154 }
7155
7156 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
7157                               struct intel_atomic_state *state)
7158 {
7159         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7160         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7161         enum pipe pipe = crtc->pipe;
7162
7163         /*
7164          * On gen2 planes are double buffered but the pipe isn't, so we must
7165          * wait for planes to fully turn off before disabling the pipe.
7166          */
7167         if (IS_GEN(dev_priv, 2))
7168                 intel_wait_for_vblank(dev_priv, pipe);
7169
7170         intel_encoders_disable(state, crtc);
7171
7172         intel_crtc_vblank_off(crtc);
7173
7174         intel_disable_pipe(old_crtc_state);
7175
7176         i9xx_pfit_disable(old_crtc_state);
7177
7178         intel_encoders_post_disable(state, crtc);
7179
7180         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7181                 if (IS_CHERRYVIEW(dev_priv))
7182                         chv_disable_pll(dev_priv, pipe);
7183                 else if (IS_VALLEYVIEW(dev_priv))
7184                         vlv_disable_pll(dev_priv, pipe);
7185                 else
7186                         i9xx_disable_pll(old_crtc_state);
7187         }
7188
7189         intel_encoders_post_pll_disable(state, crtc);
7190
7191         if (!IS_GEN(dev_priv, 2))
7192                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7193
7194         if (!dev_priv->display.initial_watermarks)
7195                 intel_update_watermarks(crtc);
7196
7197         /* clock the pipe down to 640x480@60 to potentially save power */
7198         if (IS_I830(dev_priv))
7199                 i830_enable_pipe(dev_priv, pipe);
7200 }
7201
7202 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
7203                                         struct drm_modeset_acquire_ctx *ctx)
7204 {
7205         struct intel_encoder *encoder;
7206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7207         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7208         struct intel_bw_state *bw_state =
7209                 to_intel_bw_state(dev_priv->bw_obj.state);
7210         struct intel_crtc_state *crtc_state =
7211                 to_intel_crtc_state(crtc->state);
7212         enum intel_display_power_domain domain;
7213         struct intel_plane *plane;
7214         u64 domains;
7215         struct drm_atomic_state *state;
7216         struct intel_crtc_state *temp_crtc_state;
7217         int ret;
7218
7219         if (!intel_crtc->active)
7220                 return;
7221
7222         for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
7223                 const struct intel_plane_state *plane_state =
7224                         to_intel_plane_state(plane->base.state);
7225
7226                 if (plane_state->uapi.visible)
7227                         intel_plane_disable_noatomic(intel_crtc, plane);
7228         }
7229
7230         state = drm_atomic_state_alloc(crtc->dev);
7231         if (!state) {
7232                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7233                               crtc->base.id, crtc->name);
7234                 return;
7235         }
7236
7237         state->acquire_ctx = ctx;
7238
7239         /* Everything's already locked, -EDEADLK can't happen. */
7240         temp_crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
7241         ret = drm_atomic_add_affected_connectors(state, crtc);
7242
7243         WARN_ON(IS_ERR(temp_crtc_state) || ret);
7244
7245         dev_priv->display.crtc_disable(temp_crtc_state, to_intel_atomic_state(state));
7246
7247         drm_atomic_state_put(state);
7248
7249         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7250                       crtc->base.id, crtc->name);
7251
7252         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
7253         crtc->state->active = false;
7254         intel_crtc->active = false;
7255         crtc->enabled = false;
7256         crtc->state->connector_mask = 0;
7257         crtc->state->encoder_mask = 0;
7258         intel_crtc_free_hw_state(crtc_state);
7259         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7260
7261         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
7262                 encoder->base.crtc = NULL;
7263
7264         intel_fbc_disable(intel_crtc);
7265         intel_update_watermarks(intel_crtc);
7266         intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
7267
7268         domains = intel_crtc->enabled_power_domains;
7269         for_each_power_domain(domain, domains)
7270                 intel_display_power_put_unchecked(dev_priv, domain);
7271         intel_crtc->enabled_power_domains = 0;
7272
7273         dev_priv->active_pipes &= ~BIT(intel_crtc->pipe);
7274         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
7275         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
7276
7277         bw_state->data_rate[intel_crtc->pipe] = 0;
7278         bw_state->num_active_planes[intel_crtc->pipe] = 0;
7279 }
7280
7281 /*
7282  * turn all crtc's off, but do not adjust state
7283  * This has to be paired with a call to intel_modeset_setup_hw_state.
7284  */
7285 int intel_display_suspend(struct drm_device *dev)
7286 {
7287         struct drm_i915_private *dev_priv = to_i915(dev);
7288         struct drm_atomic_state *state;
7289         int ret;
7290
7291         state = drm_atomic_helper_suspend(dev);
7292         ret = PTR_ERR_OR_ZERO(state);
7293         if (ret)
7294                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7295         else
7296                 dev_priv->modeset_restore_state = state;
7297         return ret;
7298 }
7299
7300 void intel_encoder_destroy(struct drm_encoder *encoder)
7301 {
7302         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7303
7304         drm_encoder_cleanup(encoder);
7305         kfree(intel_encoder);
7306 }
7307
7308 /* Cross check the actual hw state with our own modeset state tracking (and it's
7309  * internal consistency). */
7310 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7311                                          struct drm_connector_state *conn_state)
7312 {
7313         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7314
7315         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7316                       connector->base.base.id,
7317                       connector->base.name);
7318
7319         if (connector->get_hw_state(connector)) {
7320                 struct intel_encoder *encoder = connector->encoder;
7321
7322                 I915_STATE_WARN(!crtc_state,
7323                          "connector enabled without attached crtc\n");
7324
7325                 if (!crtc_state)
7326                         return;
7327
7328                 I915_STATE_WARN(!crtc_state->hw.active,
7329                                 "connector is active, but attached crtc isn't\n");
7330
7331                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7332                         return;
7333
7334                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7335                         "atomic encoder doesn't match attached encoder\n");
7336
7337                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7338                         "attached encoder crtc differs from connector crtc\n");
7339         } else {
7340                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7341                                 "attached crtc is active, but connector isn't\n");
7342                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7343                         "best encoder set without crtc!\n");
7344         }
7345 }
7346
7347 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7348 {
7349         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7350                 return crtc_state->fdi_lanes;
7351
7352         return 0;
7353 }
7354
7355 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7356                                      struct intel_crtc_state *pipe_config)
7357 {
7358         struct drm_i915_private *dev_priv = to_i915(dev);
7359         struct drm_atomic_state *state = pipe_config->uapi.state;
7360         struct intel_crtc *other_crtc;
7361         struct intel_crtc_state *other_crtc_state;
7362
7363         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7364                       pipe_name(pipe), pipe_config->fdi_lanes);
7365         if (pipe_config->fdi_lanes > 4) {
7366                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7367                               pipe_name(pipe), pipe_config->fdi_lanes);
7368                 return -EINVAL;
7369         }
7370
7371         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7372                 if (pipe_config->fdi_lanes > 2) {
7373                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7374                                       pipe_config->fdi_lanes);
7375                         return -EINVAL;
7376                 } else {
7377                         return 0;
7378                 }
7379         }
7380
7381         if (INTEL_NUM_PIPES(dev_priv) == 2)
7382                 return 0;
7383
7384         /* Ivybridge 3 pipe is really complicated */
7385         switch (pipe) {
7386         case PIPE_A:
7387                 return 0;
7388         case PIPE_B:
7389                 if (pipe_config->fdi_lanes <= 2)
7390                         return 0;
7391
7392                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7393                 other_crtc_state =
7394                         intel_atomic_get_crtc_state(state, other_crtc);
7395                 if (IS_ERR(other_crtc_state))
7396                         return PTR_ERR(other_crtc_state);
7397
7398                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7399                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7400                                       pipe_name(pipe), pipe_config->fdi_lanes);
7401                         return -EINVAL;
7402                 }
7403                 return 0;
7404         case PIPE_C:
7405                 if (pipe_config->fdi_lanes > 2) {
7406                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7407                                       pipe_name(pipe), pipe_config->fdi_lanes);
7408                         return -EINVAL;
7409                 }
7410
7411                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7412                 other_crtc_state =
7413                         intel_atomic_get_crtc_state(state, other_crtc);
7414                 if (IS_ERR(other_crtc_state))
7415                         return PTR_ERR(other_crtc_state);
7416
7417                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7418                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7419                         return -EINVAL;
7420                 }
7421                 return 0;
7422         default:
7423                 BUG();
7424         }
7425 }
7426
7427 #define RETRY 1
7428 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7429                                        struct intel_crtc_state *pipe_config)
7430 {
7431         struct drm_device *dev = intel_crtc->base.dev;
7432         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7433         int lane, link_bw, fdi_dotclock, ret;
7434         bool needs_recompute = false;
7435
7436 retry:
7437         /* FDI is a binary signal running at ~2.7GHz, encoding
7438          * each output octet as 10 bits. The actual frequency
7439          * is stored as a divider into a 100MHz clock, and the
7440          * mode pixel clock is stored in units of 1KHz.
7441          * Hence the bw of each lane in terms of the mode signal
7442          * is:
7443          */
7444         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7445
7446         fdi_dotclock = adjusted_mode->crtc_clock;
7447
7448         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7449                                            pipe_config->pipe_bpp);
7450
7451         pipe_config->fdi_lanes = lane;
7452
7453         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7454                                link_bw, &pipe_config->fdi_m_n, false, false);
7455
7456         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7457         if (ret == -EDEADLK)
7458                 return ret;
7459
7460         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7461                 pipe_config->pipe_bpp -= 2*3;
7462                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7463                               pipe_config->pipe_bpp);
7464                 needs_recompute = true;
7465                 pipe_config->bw_constrained = true;
7466
7467                 goto retry;
7468         }
7469
7470         if (needs_recompute)
7471                 return RETRY;
7472
7473         return ret;
7474 }
7475
7476 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7477 {
7478         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7479         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7480
7481         /* IPS only exists on ULT machines and is tied to pipe A. */
7482         if (!hsw_crtc_supports_ips(crtc))
7483                 return false;
7484
7485         if (!i915_modparams.enable_ips)
7486                 return false;
7487
7488         if (crtc_state->pipe_bpp > 24)
7489                 return false;
7490
7491         /*
7492          * We compare against max which means we must take
7493          * the increased cdclk requirement into account when
7494          * calculating the new cdclk.
7495          *
7496          * Should measure whether using a lower cdclk w/o IPS
7497          */
7498         if (IS_BROADWELL(dev_priv) &&
7499             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7500                 return false;
7501
7502         return true;
7503 }
7504
7505 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7506 {
7507         struct drm_i915_private *dev_priv =
7508                 to_i915(crtc_state->uapi.crtc->dev);
7509         struct intel_atomic_state *intel_state =
7510                 to_intel_atomic_state(crtc_state->uapi.state);
7511
7512         if (!hsw_crtc_state_ips_capable(crtc_state))
7513                 return false;
7514
7515         /*
7516          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7517          * enabled and disabled dynamically based on package C states,
7518          * user space can't make reliable use of the CRCs, so let's just
7519          * completely disable it.
7520          */
7521         if (crtc_state->crc_enabled)
7522                 return false;
7523
7524         /* IPS should be fine as long as at least one plane is enabled. */
7525         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7526                 return false;
7527
7528         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7529         if (IS_BROADWELL(dev_priv) &&
7530             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7531                 return false;
7532
7533         return true;
7534 }
7535
7536 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7537 {
7538         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7539
7540         /* GDG double wide on either pipe, otherwise pipe A only */
7541         return INTEL_GEN(dev_priv) < 4 &&
7542                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7543 }
7544
7545 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7546 {
7547         u32 pixel_rate;
7548
7549         pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7550
7551         /*
7552          * We only use IF-ID interlacing. If we ever use
7553          * PF-ID we'll need to adjust the pixel_rate here.
7554          */
7555
7556         if (pipe_config->pch_pfit.enabled) {
7557                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7558                 u32 pfit_size = pipe_config->pch_pfit.size;
7559
7560                 pipe_w = pipe_config->pipe_src_w;
7561                 pipe_h = pipe_config->pipe_src_h;
7562
7563                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7564                 pfit_h = pfit_size & 0xFFFF;
7565                 if (pipe_w < pfit_w)
7566                         pipe_w = pfit_w;
7567                 if (pipe_h < pfit_h)
7568                         pipe_h = pfit_h;
7569
7570                 if (WARN_ON(!pfit_w || !pfit_h))
7571                         return pixel_rate;
7572
7573                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7574                                      pfit_w * pfit_h);
7575         }
7576
7577         return pixel_rate;
7578 }
7579
7580 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7581 {
7582         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7583
7584         if (HAS_GMCH(dev_priv))
7585                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7586                 crtc_state->pixel_rate =
7587                         crtc_state->hw.adjusted_mode.crtc_clock;
7588         else
7589                 crtc_state->pixel_rate =
7590                         ilk_pipe_pixel_rate(crtc_state);
7591 }
7592
7593 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7594                                      struct intel_crtc_state *pipe_config)
7595 {
7596         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7597         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7598         int clock_limit = dev_priv->max_dotclk_freq;
7599
7600         if (INTEL_GEN(dev_priv) < 4) {
7601                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7602
7603                 /*
7604                  * Enable double wide mode when the dot clock
7605                  * is > 90% of the (display) core speed.
7606                  */
7607                 if (intel_crtc_supports_double_wide(crtc) &&
7608                     adjusted_mode->crtc_clock > clock_limit) {
7609                         clock_limit = dev_priv->max_dotclk_freq;
7610                         pipe_config->double_wide = true;
7611                 }
7612         }
7613
7614         if (adjusted_mode->crtc_clock > clock_limit) {
7615                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7616                               adjusted_mode->crtc_clock, clock_limit,
7617                               yesno(pipe_config->double_wide));
7618                 return -EINVAL;
7619         }
7620
7621         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7622              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7623              pipe_config->hw.ctm) {
7624                 /*
7625                  * There is only one pipe CSC unit per pipe, and we need that
7626                  * for output conversion from RGB->YCBCR. So if CTM is already
7627                  * applied we can't support YCBCR420 output.
7628                  */
7629                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7630                 return -EINVAL;
7631         }
7632
7633         /*
7634          * Pipe horizontal size must be even in:
7635          * - DVO ganged mode
7636          * - LVDS dual channel mode
7637          * - Double wide pipe
7638          */
7639         if (pipe_config->pipe_src_w & 1) {
7640                 if (pipe_config->double_wide) {
7641                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7642                         return -EINVAL;
7643                 }
7644
7645                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7646                     intel_is_dual_link_lvds(dev_priv)) {
7647                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7648                         return -EINVAL;
7649                 }
7650         }
7651
7652         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7653          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7654          */
7655         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7656                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7657                 return -EINVAL;
7658
7659         intel_crtc_compute_pixel_rate(pipe_config);
7660
7661         if (pipe_config->has_pch_encoder)
7662                 return ironlake_fdi_compute_config(crtc, pipe_config);
7663
7664         return 0;
7665 }
7666
7667 static void
7668 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7669 {
7670         while (*num > DATA_LINK_M_N_MASK ||
7671                *den > DATA_LINK_M_N_MASK) {
7672                 *num >>= 1;
7673                 *den >>= 1;
7674         }
7675 }
7676
7677 static void compute_m_n(unsigned int m, unsigned int n,
7678                         u32 *ret_m, u32 *ret_n,
7679                         bool constant_n)
7680 {
7681         /*
7682          * Several DP dongles in particular seem to be fussy about
7683          * too large link M/N values. Give N value as 0x8000 that
7684          * should be acceptable by specific devices. 0x8000 is the
7685          * specified fixed N value for asynchronous clock mode,
7686          * which the devices expect also in synchronous clock mode.
7687          */
7688         if (constant_n)
7689                 *ret_n = 0x8000;
7690         else
7691                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7692
7693         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7694         intel_reduce_m_n_ratio(ret_m, ret_n);
7695 }
7696
7697 void
7698 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7699                        int pixel_clock, int link_clock,
7700                        struct intel_link_m_n *m_n,
7701                        bool constant_n, bool fec_enable)
7702 {
7703         u32 data_clock = bits_per_pixel * pixel_clock;
7704
7705         if (fec_enable)
7706                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
7707
7708         m_n->tu = 64;
7709         compute_m_n(data_clock,
7710                     link_clock * nlanes * 8,
7711                     &m_n->gmch_m, &m_n->gmch_n,
7712                     constant_n);
7713
7714         compute_m_n(pixel_clock, link_clock,
7715                     &m_n->link_m, &m_n->link_n,
7716                     constant_n);
7717 }
7718
7719 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
7720 {
7721         /*
7722          * There may be no VBT; and if the BIOS enabled SSC we can
7723          * just keep using it to avoid unnecessary flicker.  Whereas if the
7724          * BIOS isn't using it, don't assume it will work even if the VBT
7725          * indicates as much.
7726          */
7727         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7728                 bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) &
7729                         DREF_SSC1_ENABLE;
7730
7731                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
7732                         DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n",
7733                                       enableddisabled(bios_lvds_use_ssc),
7734                                       enableddisabled(dev_priv->vbt.lvds_use_ssc));
7735                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
7736                 }
7737         }
7738 }
7739
7740 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7741 {
7742         if (i915_modparams.panel_use_ssc >= 0)
7743                 return i915_modparams.panel_use_ssc != 0;
7744         return dev_priv->vbt.lvds_use_ssc
7745                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7746 }
7747
7748 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7749 {
7750         return (1 << dpll->n) << 16 | dpll->m2;
7751 }
7752
7753 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7754 {
7755         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7756 }
7757
7758 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7759                                      struct intel_crtc_state *crtc_state,
7760                                      struct dpll *reduced_clock)
7761 {
7762         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7763         u32 fp, fp2 = 0;
7764
7765         if (IS_PINEVIEW(dev_priv)) {
7766                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7767                 if (reduced_clock)
7768                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7769         } else {
7770                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7771                 if (reduced_clock)
7772                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7773         }
7774
7775         crtc_state->dpll_hw_state.fp0 = fp;
7776
7777         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7778             reduced_clock) {
7779                 crtc_state->dpll_hw_state.fp1 = fp2;
7780         } else {
7781                 crtc_state->dpll_hw_state.fp1 = fp;
7782         }
7783 }
7784
7785 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7786                 pipe)
7787 {
7788         u32 reg_val;
7789
7790         /*
7791          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7792          * and set it to a reasonable value instead.
7793          */
7794         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7795         reg_val &= 0xffffff00;
7796         reg_val |= 0x00000030;
7797         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7798
7799         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7800         reg_val &= 0x00ffffff;
7801         reg_val |= 0x8c000000;
7802         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7803
7804         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7805         reg_val &= 0xffffff00;
7806         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7807
7808         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7809         reg_val &= 0x00ffffff;
7810         reg_val |= 0xb0000000;
7811         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7812 }
7813
7814 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7815                                          const struct intel_link_m_n *m_n)
7816 {
7817         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7818         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7819         enum pipe pipe = crtc->pipe;
7820
7821         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7822         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7823         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7824         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7825 }
7826
7827 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7828                                  enum transcoder transcoder)
7829 {
7830         if (IS_HASWELL(dev_priv))
7831                 return transcoder == TRANSCODER_EDP;
7832
7833         /*
7834          * Strictly speaking some registers are available before
7835          * gen7, but we only support DRRS on gen7+
7836          */
7837         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7838 }
7839
7840 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7841                                          const struct intel_link_m_n *m_n,
7842                                          const struct intel_link_m_n *m2_n2)
7843 {
7844         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7845         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7846         enum pipe pipe = crtc->pipe;
7847         enum transcoder transcoder = crtc_state->cpu_transcoder;
7848
7849         if (INTEL_GEN(dev_priv) >= 5) {
7850                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7851                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7852                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7853                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7854                 /*
7855                  *  M2_N2 registers are set only if DRRS is supported
7856                  * (to make sure the registers are not unnecessarily accessed).
7857                  */
7858                 if (m2_n2 && crtc_state->has_drrs &&
7859                     transcoder_has_m2_n2(dev_priv, transcoder)) {
7860                         I915_WRITE(PIPE_DATA_M2(transcoder),
7861                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7862                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7863                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7864                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7865                 }
7866         } else {
7867                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7868                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7869                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7870                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7871         }
7872 }
7873
7874 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7875 {
7876         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7877
7878         if (m_n == M1_N1) {
7879                 dp_m_n = &crtc_state->dp_m_n;
7880                 dp_m2_n2 = &crtc_state->dp_m2_n2;
7881         } else if (m_n == M2_N2) {
7882
7883                 /*
7884                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7885                  * needs to be programmed into M1_N1.
7886                  */
7887                 dp_m_n = &crtc_state->dp_m2_n2;
7888         } else {
7889                 DRM_ERROR("Unsupported divider value\n");
7890                 return;
7891         }
7892
7893         if (crtc_state->has_pch_encoder)
7894                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7895         else
7896                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7897 }
7898
7899 static void vlv_compute_dpll(struct intel_crtc *crtc,
7900                              struct intel_crtc_state *pipe_config)
7901 {
7902         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7903                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7904         if (crtc->pipe != PIPE_A)
7905                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7906
7907         /* DPLL not used with DSI, but still need the rest set up */
7908         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7909                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7910                         DPLL_EXT_BUFFER_ENABLE_VLV;
7911
7912         pipe_config->dpll_hw_state.dpll_md =
7913                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7914 }
7915
7916 static void chv_compute_dpll(struct intel_crtc *crtc,
7917                              struct intel_crtc_state *pipe_config)
7918 {
7919         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7920                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7921         if (crtc->pipe != PIPE_A)
7922                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7923
7924         /* DPLL not used with DSI, but still need the rest set up */
7925         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7926                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7927
7928         pipe_config->dpll_hw_state.dpll_md =
7929                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7930 }
7931
7932 static void vlv_prepare_pll(struct intel_crtc *crtc,
7933                             const struct intel_crtc_state *pipe_config)
7934 {
7935         struct drm_device *dev = crtc->base.dev;
7936         struct drm_i915_private *dev_priv = to_i915(dev);
7937         enum pipe pipe = crtc->pipe;
7938         u32 mdiv;
7939         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7940         u32 coreclk, reg_val;
7941
7942         /* Enable Refclk */
7943         I915_WRITE(DPLL(pipe),
7944                    pipe_config->dpll_hw_state.dpll &
7945                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7946
7947         /* No need to actually set up the DPLL with DSI */
7948         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7949                 return;
7950
7951         vlv_dpio_get(dev_priv);
7952
7953         bestn = pipe_config->dpll.n;
7954         bestm1 = pipe_config->dpll.m1;
7955         bestm2 = pipe_config->dpll.m2;
7956         bestp1 = pipe_config->dpll.p1;
7957         bestp2 = pipe_config->dpll.p2;
7958
7959         /* See eDP HDMI DPIO driver vbios notes doc */
7960
7961         /* PLL B needs special handling */
7962         if (pipe == PIPE_B)
7963                 vlv_pllb_recal_opamp(dev_priv, pipe);
7964
7965         /* Set up Tx target for periodic Rcomp update */
7966         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7967
7968         /* Disable target IRef on PLL */
7969         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7970         reg_val &= 0x00ffffff;
7971         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7972
7973         /* Disable fast lock */
7974         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7975
7976         /* Set idtafcrecal before PLL is enabled */
7977         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7978         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7979         mdiv |= ((bestn << DPIO_N_SHIFT));
7980         mdiv |= (1 << DPIO_K_SHIFT);
7981
7982         /*
7983          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7984          * but we don't support that).
7985          * Note: don't use the DAC post divider as it seems unstable.
7986          */
7987         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7988         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7989
7990         mdiv |= DPIO_ENABLE_CALIBRATION;
7991         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7992
7993         /* Set HBR and RBR LPF coefficients */
7994         if (pipe_config->port_clock == 162000 ||
7995             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7996             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7997                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7998                                  0x009f0003);
7999         else
8000                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8001                                  0x00d0000f);
8002
8003         if (intel_crtc_has_dp_encoder(pipe_config)) {
8004                 /* Use SSC source */
8005                 if (pipe == PIPE_A)
8006                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8007                                          0x0df40000);
8008                 else
8009                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8010                                          0x0df70000);
8011         } else { /* HDMI or VGA */
8012                 /* Use bend source */
8013                 if (pipe == PIPE_A)
8014                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8015                                          0x0df70000);
8016                 else
8017                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8018                                          0x0df40000);
8019         }
8020
8021         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8022         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8023         if (intel_crtc_has_dp_encoder(pipe_config))
8024                 coreclk |= 0x01000000;
8025         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8026
8027         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8028
8029         vlv_dpio_put(dev_priv);
8030 }
8031
8032 static void chv_prepare_pll(struct intel_crtc *crtc,
8033                             const struct intel_crtc_state *pipe_config)
8034 {
8035         struct drm_device *dev = crtc->base.dev;
8036         struct drm_i915_private *dev_priv = to_i915(dev);
8037         enum pipe pipe = crtc->pipe;
8038         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8039         u32 loopfilter, tribuf_calcntr;
8040         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8041         u32 dpio_val;
8042         int vco;
8043
8044         /* Enable Refclk and SSC */
8045         I915_WRITE(DPLL(pipe),
8046                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8047
8048         /* No need to actually set up the DPLL with DSI */
8049         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8050                 return;
8051
8052         bestn = pipe_config->dpll.n;
8053         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8054         bestm1 = pipe_config->dpll.m1;
8055         bestm2 = pipe_config->dpll.m2 >> 22;
8056         bestp1 = pipe_config->dpll.p1;
8057         bestp2 = pipe_config->dpll.p2;
8058         vco = pipe_config->dpll.vco;
8059         dpio_val = 0;
8060         loopfilter = 0;
8061
8062         vlv_dpio_get(dev_priv);
8063
8064         /* p1 and p2 divider */
8065         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8066                         5 << DPIO_CHV_S1_DIV_SHIFT |
8067                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8068                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8069                         1 << DPIO_CHV_K_DIV_SHIFT);
8070
8071         /* Feedback post-divider - m2 */
8072         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8073
8074         /* Feedback refclk divider - n and m1 */
8075         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8076                         DPIO_CHV_M1_DIV_BY_2 |
8077                         1 << DPIO_CHV_N_DIV_SHIFT);
8078
8079         /* M2 fraction division */
8080         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8081
8082         /* M2 fraction division enable */
8083         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8084         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8085         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8086         if (bestm2_frac)
8087                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8088         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8089
8090         /* Program digital lock detect threshold */
8091         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8092         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8093                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8094         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8095         if (!bestm2_frac)
8096                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8097         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8098
8099         /* Loop filter */
8100         if (vco == 5400000) {
8101                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8102                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8103                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8104                 tribuf_calcntr = 0x9;
8105         } else if (vco <= 6200000) {
8106                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8107                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8108                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8109                 tribuf_calcntr = 0x9;
8110         } else if (vco <= 6480000) {
8111                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8112                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8113                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8114                 tribuf_calcntr = 0x8;
8115         } else {
8116                 /* Not supported. Apply the same limits as in the max case */
8117                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8118                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8119                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8120                 tribuf_calcntr = 0;
8121         }
8122         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8123
8124         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8125         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8126         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8127         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8128
8129         /* AFC Recal */
8130         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8131                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8132                         DPIO_AFC_RECAL);
8133
8134         vlv_dpio_put(dev_priv);
8135 }
8136
8137 /**
8138  * vlv_force_pll_on - forcibly enable just the PLL
8139  * @dev_priv: i915 private structure
8140  * @pipe: pipe PLL to enable
8141  * @dpll: PLL configuration
8142  *
8143  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8144  * in cases where we need the PLL enabled even when @pipe is not going to
8145  * be enabled.
8146  */
8147 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8148                      const struct dpll *dpll)
8149 {
8150         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8151         struct intel_crtc_state *pipe_config;
8152
8153         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8154         if (!pipe_config)
8155                 return -ENOMEM;
8156
8157         pipe_config->uapi.crtc = &crtc->base;
8158         pipe_config->pixel_multiplier = 1;
8159         pipe_config->dpll = *dpll;
8160
8161         if (IS_CHERRYVIEW(dev_priv)) {
8162                 chv_compute_dpll(crtc, pipe_config);
8163                 chv_prepare_pll(crtc, pipe_config);
8164                 chv_enable_pll(crtc, pipe_config);
8165         } else {
8166                 vlv_compute_dpll(crtc, pipe_config);
8167                 vlv_prepare_pll(crtc, pipe_config);
8168                 vlv_enable_pll(crtc, pipe_config);
8169         }
8170
8171         kfree(pipe_config);
8172
8173         return 0;
8174 }
8175
8176 /**
8177  * vlv_force_pll_off - forcibly disable just the PLL
8178  * @dev_priv: i915 private structure
8179  * @pipe: pipe PLL to disable
8180  *
8181  * Disable the PLL for @pipe. To be used in cases where we need
8182  * the PLL enabled even when @pipe is not going to be enabled.
8183  */
8184 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8185 {
8186         if (IS_CHERRYVIEW(dev_priv))
8187                 chv_disable_pll(dev_priv, pipe);
8188         else
8189                 vlv_disable_pll(dev_priv, pipe);
8190 }
8191
8192 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8193                               struct intel_crtc_state *crtc_state,
8194                               struct dpll *reduced_clock)
8195 {
8196         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8197         u32 dpll;
8198         struct dpll *clock = &crtc_state->dpll;
8199
8200         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8201
8202         dpll = DPLL_VGA_MODE_DIS;
8203
8204         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8205                 dpll |= DPLLB_MODE_LVDS;
8206         else
8207                 dpll |= DPLLB_MODE_DAC_SERIAL;
8208
8209         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8210             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8211                 dpll |= (crtc_state->pixel_multiplier - 1)
8212                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8213         }
8214
8215         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8216             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8217                 dpll |= DPLL_SDVO_HIGH_SPEED;
8218
8219         if (intel_crtc_has_dp_encoder(crtc_state))
8220                 dpll |= DPLL_SDVO_HIGH_SPEED;
8221
8222         /* compute bitmask from p1 value */
8223         if (IS_PINEVIEW(dev_priv))
8224                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8225         else {
8226                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8227                 if (IS_G4X(dev_priv) && reduced_clock)
8228                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8229         }
8230         switch (clock->p2) {
8231         case 5:
8232                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8233                 break;
8234         case 7:
8235                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8236                 break;
8237         case 10:
8238                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8239                 break;
8240         case 14:
8241                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8242                 break;
8243         }
8244         if (INTEL_GEN(dev_priv) >= 4)
8245                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8246
8247         if (crtc_state->sdvo_tv_clock)
8248                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8249         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8250                  intel_panel_use_ssc(dev_priv))
8251                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8252         else
8253                 dpll |= PLL_REF_INPUT_DREFCLK;
8254
8255         dpll |= DPLL_VCO_ENABLE;
8256         crtc_state->dpll_hw_state.dpll = dpll;
8257
8258         if (INTEL_GEN(dev_priv) >= 4) {
8259                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8260                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8261                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8262         }
8263 }
8264
8265 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8266                               struct intel_crtc_state *crtc_state,
8267                               struct dpll *reduced_clock)
8268 {
8269         struct drm_device *dev = crtc->base.dev;
8270         struct drm_i915_private *dev_priv = to_i915(dev);
8271         u32 dpll;
8272         struct dpll *clock = &crtc_state->dpll;
8273
8274         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8275
8276         dpll = DPLL_VGA_MODE_DIS;
8277
8278         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8279                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8280         } else {
8281                 if (clock->p1 == 2)
8282                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8283                 else
8284                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8285                 if (clock->p2 == 4)
8286                         dpll |= PLL_P2_DIVIDE_BY_4;
8287         }
8288
8289         /*
8290          * Bspec:
8291          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8292          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8293          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8294          *  Enable) must be set to “1” in both the DPLL A Control Register
8295          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8296          *
8297          * For simplicity We simply keep both bits always enabled in
8298          * both DPLLS. The spec says we should disable the DVO 2X clock
8299          * when not needed, but this seems to work fine in practice.
8300          */
8301         if (IS_I830(dev_priv) ||
8302             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8303                 dpll |= DPLL_DVO_2X_MODE;
8304
8305         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8306             intel_panel_use_ssc(dev_priv))
8307                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8308         else
8309                 dpll |= PLL_REF_INPUT_DREFCLK;
8310
8311         dpll |= DPLL_VCO_ENABLE;
8312         crtc_state->dpll_hw_state.dpll = dpll;
8313 }
8314
8315 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8316 {
8317         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8318         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8319         enum pipe pipe = crtc->pipe;
8320         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8321         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8322         u32 crtc_vtotal, crtc_vblank_end;
8323         int vsyncshift = 0;
8324
8325         /* We need to be careful not to changed the adjusted mode, for otherwise
8326          * the hw state checker will get angry at the mismatch. */
8327         crtc_vtotal = adjusted_mode->crtc_vtotal;
8328         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8329
8330         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8331                 /* the chip adds 2 halflines automatically */
8332                 crtc_vtotal -= 1;
8333                 crtc_vblank_end -= 1;
8334
8335                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8336                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8337                 else
8338                         vsyncshift = adjusted_mode->crtc_hsync_start -
8339                                 adjusted_mode->crtc_htotal / 2;
8340                 if (vsyncshift < 0)
8341                         vsyncshift += adjusted_mode->crtc_htotal;
8342         }
8343
8344         if (INTEL_GEN(dev_priv) > 3)
8345                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8346
8347         I915_WRITE(HTOTAL(cpu_transcoder),
8348                    (adjusted_mode->crtc_hdisplay - 1) |
8349                    ((adjusted_mode->crtc_htotal - 1) << 16));
8350         I915_WRITE(HBLANK(cpu_transcoder),
8351                    (adjusted_mode->crtc_hblank_start - 1) |
8352                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8353         I915_WRITE(HSYNC(cpu_transcoder),
8354                    (adjusted_mode->crtc_hsync_start - 1) |
8355                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8356
8357         I915_WRITE(VTOTAL(cpu_transcoder),
8358                    (adjusted_mode->crtc_vdisplay - 1) |
8359                    ((crtc_vtotal - 1) << 16));
8360         I915_WRITE(VBLANK(cpu_transcoder),
8361                    (adjusted_mode->crtc_vblank_start - 1) |
8362                    ((crtc_vblank_end - 1) << 16));
8363         I915_WRITE(VSYNC(cpu_transcoder),
8364                    (adjusted_mode->crtc_vsync_start - 1) |
8365                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8366
8367         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8368          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8369          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8370          * bits. */
8371         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8372             (pipe == PIPE_B || pipe == PIPE_C))
8373                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8374
8375 }
8376
8377 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8378 {
8379         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8380         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8381         enum pipe pipe = crtc->pipe;
8382
8383         /* pipesrc controls the size that is scaled from, which should
8384          * always be the user's requested size.
8385          */
8386         I915_WRITE(PIPESRC(pipe),
8387                    ((crtc_state->pipe_src_w - 1) << 16) |
8388                    (crtc_state->pipe_src_h - 1));
8389 }
8390
8391 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8392 {
8393         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8394         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8395
8396         if (IS_GEN(dev_priv, 2))
8397                 return false;
8398
8399         if (INTEL_GEN(dev_priv) >= 9 ||
8400             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8401                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8402         else
8403                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8404 }
8405
8406 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8407                                    struct intel_crtc_state *pipe_config)
8408 {
8409         struct drm_device *dev = crtc->base.dev;
8410         struct drm_i915_private *dev_priv = to_i915(dev);
8411         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8412         u32 tmp;
8413
8414         tmp = I915_READ(HTOTAL(cpu_transcoder));
8415         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8416         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8417
8418         if (!transcoder_is_dsi(cpu_transcoder)) {
8419                 tmp = I915_READ(HBLANK(cpu_transcoder));
8420                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8421                                                         (tmp & 0xffff) + 1;
8422                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8423                                                 ((tmp >> 16) & 0xffff) + 1;
8424         }
8425         tmp = I915_READ(HSYNC(cpu_transcoder));
8426         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8427         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8428
8429         tmp = I915_READ(VTOTAL(cpu_transcoder));
8430         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8431         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8432
8433         if (!transcoder_is_dsi(cpu_transcoder)) {
8434                 tmp = I915_READ(VBLANK(cpu_transcoder));
8435                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8436                                                         (tmp & 0xffff) + 1;
8437                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8438                                                 ((tmp >> 16) & 0xffff) + 1;
8439         }
8440         tmp = I915_READ(VSYNC(cpu_transcoder));
8441         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8442         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8443
8444         if (intel_pipe_is_interlaced(pipe_config)) {
8445                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8446                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8447                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8448         }
8449 }
8450
8451 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8452                                     struct intel_crtc_state *pipe_config)
8453 {
8454         struct drm_device *dev = crtc->base.dev;
8455         struct drm_i915_private *dev_priv = to_i915(dev);
8456         u32 tmp;
8457
8458         tmp = I915_READ(PIPESRC(crtc->pipe));
8459         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8460         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8461
8462         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8463         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8464 }
8465
8466 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8467                                  struct intel_crtc_state *pipe_config)
8468 {
8469         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8470         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8471         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8472         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8473
8474         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8475         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8476         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8477         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8478
8479         mode->flags = pipe_config->hw.adjusted_mode.flags;
8480         mode->type = DRM_MODE_TYPE_DRIVER;
8481
8482         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8483
8484         mode->hsync = drm_mode_hsync(mode);
8485         mode->vrefresh = drm_mode_vrefresh(mode);
8486         drm_mode_set_name(mode);
8487 }
8488
8489 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8490 {
8491         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8492         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8493         u32 pipeconf;
8494
8495         pipeconf = 0;
8496
8497         /* we keep both pipes enabled on 830 */
8498         if (IS_I830(dev_priv))
8499                 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8500
8501         if (crtc_state->double_wide)
8502                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8503
8504         /* only g4x and later have fancy bpc/dither controls */
8505         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8506             IS_CHERRYVIEW(dev_priv)) {
8507                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8508                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8509                         pipeconf |= PIPECONF_DITHER_EN |
8510                                     PIPECONF_DITHER_TYPE_SP;
8511
8512                 switch (crtc_state->pipe_bpp) {
8513                 case 18:
8514                         pipeconf |= PIPECONF_6BPC;
8515                         break;
8516                 case 24:
8517                         pipeconf |= PIPECONF_8BPC;
8518                         break;
8519                 case 30:
8520                         pipeconf |= PIPECONF_10BPC;
8521                         break;
8522                 default:
8523                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8524                         BUG();
8525                 }
8526         }
8527
8528         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8529                 if (INTEL_GEN(dev_priv) < 4 ||
8530                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8531                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8532                 else
8533                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8534         } else {
8535                 pipeconf |= PIPECONF_PROGRESSIVE;
8536         }
8537
8538         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8539              crtc_state->limited_color_range)
8540                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8541
8542         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8543
8544         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8545
8546         I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8547         POSTING_READ(PIPECONF(crtc->pipe));
8548 }
8549
8550 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8551                                    struct intel_crtc_state *crtc_state)
8552 {
8553         struct drm_device *dev = crtc->base.dev;
8554         struct drm_i915_private *dev_priv = to_i915(dev);
8555         const struct intel_limit *limit;
8556         int refclk = 48000;
8557
8558         memset(&crtc_state->dpll_hw_state, 0,
8559                sizeof(crtc_state->dpll_hw_state));
8560
8561         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8562                 if (intel_panel_use_ssc(dev_priv)) {
8563                         refclk = dev_priv->vbt.lvds_ssc_freq;
8564                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8565                 }
8566
8567                 limit = &intel_limits_i8xx_lvds;
8568         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8569                 limit = &intel_limits_i8xx_dvo;
8570         } else {
8571                 limit = &intel_limits_i8xx_dac;
8572         }
8573
8574         if (!crtc_state->clock_set &&
8575             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8576                                  refclk, NULL, &crtc_state->dpll)) {
8577                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8578                 return -EINVAL;
8579         }
8580
8581         i8xx_compute_dpll(crtc, crtc_state, NULL);
8582
8583         return 0;
8584 }
8585
8586 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8587                                   struct intel_crtc_state *crtc_state)
8588 {
8589         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8590         const struct intel_limit *limit;
8591         int refclk = 96000;
8592
8593         memset(&crtc_state->dpll_hw_state, 0,
8594                sizeof(crtc_state->dpll_hw_state));
8595
8596         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8597                 if (intel_panel_use_ssc(dev_priv)) {
8598                         refclk = dev_priv->vbt.lvds_ssc_freq;
8599                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8600                 }
8601
8602                 if (intel_is_dual_link_lvds(dev_priv))
8603                         limit = &intel_limits_g4x_dual_channel_lvds;
8604                 else
8605                         limit = &intel_limits_g4x_single_channel_lvds;
8606         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8607                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8608                 limit = &intel_limits_g4x_hdmi;
8609         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8610                 limit = &intel_limits_g4x_sdvo;
8611         } else {
8612                 /* The option is for other outputs */
8613                 limit = &intel_limits_i9xx_sdvo;
8614         }
8615
8616         if (!crtc_state->clock_set &&
8617             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8618                                 refclk, NULL, &crtc_state->dpll)) {
8619                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8620                 return -EINVAL;
8621         }
8622
8623         i9xx_compute_dpll(crtc, crtc_state, NULL);
8624
8625         return 0;
8626 }
8627
8628 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8629                                   struct intel_crtc_state *crtc_state)
8630 {
8631         struct drm_device *dev = crtc->base.dev;
8632         struct drm_i915_private *dev_priv = to_i915(dev);
8633         const struct intel_limit *limit;
8634         int refclk = 96000;
8635
8636         memset(&crtc_state->dpll_hw_state, 0,
8637                sizeof(crtc_state->dpll_hw_state));
8638
8639         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8640                 if (intel_panel_use_ssc(dev_priv)) {
8641                         refclk = dev_priv->vbt.lvds_ssc_freq;
8642                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8643                 }
8644
8645                 limit = &intel_limits_pineview_lvds;
8646         } else {
8647                 limit = &intel_limits_pineview_sdvo;
8648         }
8649
8650         if (!crtc_state->clock_set &&
8651             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8652                                 refclk, NULL, &crtc_state->dpll)) {
8653                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8654                 return -EINVAL;
8655         }
8656
8657         i9xx_compute_dpll(crtc, crtc_state, NULL);
8658
8659         return 0;
8660 }
8661
8662 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8663                                    struct intel_crtc_state *crtc_state)
8664 {
8665         struct drm_device *dev = crtc->base.dev;
8666         struct drm_i915_private *dev_priv = to_i915(dev);
8667         const struct intel_limit *limit;
8668         int refclk = 96000;
8669
8670         memset(&crtc_state->dpll_hw_state, 0,
8671                sizeof(crtc_state->dpll_hw_state));
8672
8673         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8674                 if (intel_panel_use_ssc(dev_priv)) {
8675                         refclk = dev_priv->vbt.lvds_ssc_freq;
8676                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8677                 }
8678
8679                 limit = &intel_limits_i9xx_lvds;
8680         } else {
8681                 limit = &intel_limits_i9xx_sdvo;
8682         }
8683
8684         if (!crtc_state->clock_set &&
8685             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8686                                  refclk, NULL, &crtc_state->dpll)) {
8687                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8688                 return -EINVAL;
8689         }
8690
8691         i9xx_compute_dpll(crtc, crtc_state, NULL);
8692
8693         return 0;
8694 }
8695
8696 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8697                                   struct intel_crtc_state *crtc_state)
8698 {
8699         int refclk = 100000;
8700         const struct intel_limit *limit = &intel_limits_chv;
8701
8702         memset(&crtc_state->dpll_hw_state, 0,
8703                sizeof(crtc_state->dpll_hw_state));
8704
8705         if (!crtc_state->clock_set &&
8706             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8707                                 refclk, NULL, &crtc_state->dpll)) {
8708                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8709                 return -EINVAL;
8710         }
8711
8712         chv_compute_dpll(crtc, crtc_state);
8713
8714         return 0;
8715 }
8716
8717 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8718                                   struct intel_crtc_state *crtc_state)
8719 {
8720         int refclk = 100000;
8721         const struct intel_limit *limit = &intel_limits_vlv;
8722
8723         memset(&crtc_state->dpll_hw_state, 0,
8724                sizeof(crtc_state->dpll_hw_state));
8725
8726         if (!crtc_state->clock_set &&
8727             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8728                                 refclk, NULL, &crtc_state->dpll)) {
8729                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8730                 return -EINVAL;
8731         }
8732
8733         vlv_compute_dpll(crtc, crtc_state);
8734
8735         return 0;
8736 }
8737
8738 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8739 {
8740         if (IS_I830(dev_priv))
8741                 return false;
8742
8743         return INTEL_GEN(dev_priv) >= 4 ||
8744                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8745 }
8746
8747 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8748                                  struct intel_crtc_state *pipe_config)
8749 {
8750         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8751         u32 tmp;
8752
8753         if (!i9xx_has_pfit(dev_priv))
8754                 return;
8755
8756         tmp = I915_READ(PFIT_CONTROL);
8757         if (!(tmp & PFIT_ENABLE))
8758                 return;
8759
8760         /* Check whether the pfit is attached to our pipe. */
8761         if (INTEL_GEN(dev_priv) < 4) {
8762                 if (crtc->pipe != PIPE_B)
8763                         return;
8764         } else {
8765                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8766                         return;
8767         }
8768
8769         pipe_config->gmch_pfit.control = tmp;
8770         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8771 }
8772
8773 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8774                                struct intel_crtc_state *pipe_config)
8775 {
8776         struct drm_device *dev = crtc->base.dev;
8777         struct drm_i915_private *dev_priv = to_i915(dev);
8778         enum pipe pipe = crtc->pipe;
8779         struct dpll clock;
8780         u32 mdiv;
8781         int refclk = 100000;
8782
8783         /* In case of DSI, DPLL will not be used */
8784         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8785                 return;
8786
8787         vlv_dpio_get(dev_priv);
8788         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8789         vlv_dpio_put(dev_priv);
8790
8791         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8792         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8793         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8794         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8795         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8796
8797         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8798 }
8799
8800 static void
8801 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8802                               struct intel_initial_plane_config *plane_config)
8803 {
8804         struct drm_device *dev = crtc->base.dev;
8805         struct drm_i915_private *dev_priv = to_i915(dev);
8806         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8807         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8808         enum pipe pipe;
8809         u32 val, base, offset;
8810         int fourcc, pixel_format;
8811         unsigned int aligned_height;
8812         struct drm_framebuffer *fb;
8813         struct intel_framebuffer *intel_fb;
8814
8815         if (!plane->get_hw_state(plane, &pipe))
8816                 return;
8817
8818         WARN_ON(pipe != crtc->pipe);
8819
8820         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8821         if (!intel_fb) {
8822                 DRM_DEBUG_KMS("failed to alloc fb\n");
8823                 return;
8824         }
8825
8826         fb = &intel_fb->base;
8827
8828         fb->dev = dev;
8829
8830         val = I915_READ(DSPCNTR(i9xx_plane));
8831
8832         if (INTEL_GEN(dev_priv) >= 4) {
8833                 if (val & DISPPLANE_TILED) {
8834                         plane_config->tiling = I915_TILING_X;
8835                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8836                 }
8837
8838                 if (val & DISPPLANE_ROTATE_180)
8839                         plane_config->rotation = DRM_MODE_ROTATE_180;
8840         }
8841
8842         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8843             val & DISPPLANE_MIRROR)
8844                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8845
8846         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8847         fourcc = i9xx_format_to_fourcc(pixel_format);
8848         fb->format = drm_format_info(fourcc);
8849
8850         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8851                 offset = I915_READ(DSPOFFSET(i9xx_plane));
8852                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8853         } else if (INTEL_GEN(dev_priv) >= 4) {
8854                 if (plane_config->tiling)
8855                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
8856                 else
8857                         offset = I915_READ(DSPLINOFF(i9xx_plane));
8858                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8859         } else {
8860                 base = I915_READ(DSPADDR(i9xx_plane));
8861         }
8862         plane_config->base = base;
8863
8864         val = I915_READ(PIPESRC(pipe));
8865         fb->width = ((val >> 16) & 0xfff) + 1;
8866         fb->height = ((val >> 0) & 0xfff) + 1;
8867
8868         val = I915_READ(DSPSTRIDE(i9xx_plane));
8869         fb->pitches[0] = val & 0xffffffc0;
8870
8871         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8872
8873         plane_config->size = fb->pitches[0] * aligned_height;
8874
8875         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8876                       crtc->base.name, plane->base.name, fb->width, fb->height,
8877                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8878                       plane_config->size);
8879
8880         plane_config->fb = intel_fb;
8881 }
8882
8883 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8884                                struct intel_crtc_state *pipe_config)
8885 {
8886         struct drm_device *dev = crtc->base.dev;
8887         struct drm_i915_private *dev_priv = to_i915(dev);
8888         enum pipe pipe = crtc->pipe;
8889         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8890         struct dpll clock;
8891         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8892         int refclk = 100000;
8893
8894         /* In case of DSI, DPLL will not be used */
8895         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8896                 return;
8897
8898         vlv_dpio_get(dev_priv);
8899         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8900         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8901         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8902         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8903         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8904         vlv_dpio_put(dev_priv);
8905
8906         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8907         clock.m2 = (pll_dw0 & 0xff) << 22;
8908         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8909                 clock.m2 |= pll_dw2 & 0x3fffff;
8910         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8911         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8912         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8913
8914         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8915 }
8916
8917 static enum intel_output_format
8918 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
8919 {
8920         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8921         u32 tmp;
8922
8923         tmp = I915_READ(PIPEMISC(crtc->pipe));
8924
8925         if (tmp & PIPEMISC_YUV420_ENABLE) {
8926                 /* We support 4:2:0 in full blend mode only */
8927                 WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
8928
8929                 return INTEL_OUTPUT_FORMAT_YCBCR420;
8930         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8931                 return INTEL_OUTPUT_FORMAT_YCBCR444;
8932         } else {
8933                 return INTEL_OUTPUT_FORMAT_RGB;
8934         }
8935 }
8936
8937 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8938 {
8939         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8940         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8941         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8942         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8943         u32 tmp;
8944
8945         tmp = I915_READ(DSPCNTR(i9xx_plane));
8946
8947         if (tmp & DISPPLANE_GAMMA_ENABLE)
8948                 crtc_state->gamma_enable = true;
8949
8950         if (!HAS_GMCH(dev_priv) &&
8951             tmp & DISPPLANE_PIPE_CSC_ENABLE)
8952                 crtc_state->csc_enable = true;
8953 }
8954
8955 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8956                                  struct intel_crtc_state *pipe_config)
8957 {
8958         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8959         enum intel_display_power_domain power_domain;
8960         intel_wakeref_t wakeref;
8961         u32 tmp;
8962         bool ret;
8963
8964         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8965         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8966         if (!wakeref)
8967                 return false;
8968
8969         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8970         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8971         pipe_config->shared_dpll = NULL;
8972         pipe_config->master_transcoder = INVALID_TRANSCODER;
8973
8974         ret = false;
8975
8976         tmp = I915_READ(PIPECONF(crtc->pipe));
8977         if (!(tmp & PIPECONF_ENABLE))
8978                 goto out;
8979
8980         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8981             IS_CHERRYVIEW(dev_priv)) {
8982                 switch (tmp & PIPECONF_BPC_MASK) {
8983                 case PIPECONF_6BPC:
8984                         pipe_config->pipe_bpp = 18;
8985                         break;
8986                 case PIPECONF_8BPC:
8987                         pipe_config->pipe_bpp = 24;
8988                         break;
8989                 case PIPECONF_10BPC:
8990                         pipe_config->pipe_bpp = 30;
8991                         break;
8992                 default:
8993                         break;
8994                 }
8995         }
8996
8997         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8998             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8999                 pipe_config->limited_color_range = true;
9000
9001         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9002                 PIPECONF_GAMMA_MODE_SHIFT;
9003
9004         if (IS_CHERRYVIEW(dev_priv))
9005                 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
9006
9007         i9xx_get_pipe_color_config(pipe_config);
9008         intel_color_get_config(pipe_config);
9009
9010         if (INTEL_GEN(dev_priv) < 4)
9011                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9012
9013         intel_get_pipe_timings(crtc, pipe_config);
9014         intel_get_pipe_src_size(crtc, pipe_config);
9015
9016         i9xx_get_pfit_config(crtc, pipe_config);
9017
9018         if (INTEL_GEN(dev_priv) >= 4) {
9019                 /* No way to read it out on pipes B and C */
9020                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9021                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
9022                 else
9023                         tmp = I915_READ(DPLL_MD(crtc->pipe));
9024                 pipe_config->pixel_multiplier =
9025                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9026                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9027                 pipe_config->dpll_hw_state.dpll_md = tmp;
9028         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9029                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9030                 tmp = I915_READ(DPLL(crtc->pipe));
9031                 pipe_config->pixel_multiplier =
9032                         ((tmp & SDVO_MULTIPLIER_MASK)
9033                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9034         } else {
9035                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9036                  * port and will be fixed up in the encoder->get_config
9037                  * function. */
9038                 pipe_config->pixel_multiplier = 1;
9039         }
9040         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
9041         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9042                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
9043                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
9044         } else {
9045                 /* Mask out read-only status bits. */
9046                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9047                                                      DPLL_PORTC_READY_MASK |
9048                                                      DPLL_PORTB_READY_MASK);
9049         }
9050
9051         if (IS_CHERRYVIEW(dev_priv))
9052                 chv_crtc_clock_get(crtc, pipe_config);
9053         else if (IS_VALLEYVIEW(dev_priv))
9054                 vlv_crtc_clock_get(crtc, pipe_config);
9055         else
9056                 i9xx_crtc_clock_get(crtc, pipe_config);
9057
9058         /*
9059          * Normally the dotclock is filled in by the encoder .get_config()
9060          * but in case the pipe is enabled w/o any ports we need a sane
9061          * default.
9062          */
9063         pipe_config->hw.adjusted_mode.crtc_clock =
9064                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9065
9066         ret = true;
9067
9068 out:
9069         intel_display_power_put(dev_priv, power_domain, wakeref);
9070
9071         return ret;
9072 }
9073
9074 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
9075 {
9076         struct intel_encoder *encoder;
9077         int i;
9078         u32 val, final;
9079         bool has_lvds = false;
9080         bool has_cpu_edp = false;
9081         bool has_panel = false;
9082         bool has_ck505 = false;
9083         bool can_ssc = false;
9084         bool using_ssc_source = false;
9085
9086         /* We need to take the global config into account */
9087         for_each_intel_encoder(&dev_priv->drm, encoder) {
9088                 switch (encoder->type) {
9089                 case INTEL_OUTPUT_LVDS:
9090                         has_panel = true;
9091                         has_lvds = true;
9092                         break;
9093                 case INTEL_OUTPUT_EDP:
9094                         has_panel = true;
9095                         if (encoder->port == PORT_A)
9096                                 has_cpu_edp = true;
9097                         break;
9098                 default:
9099                         break;
9100                 }
9101         }
9102
9103         if (HAS_PCH_IBX(dev_priv)) {
9104                 has_ck505 = dev_priv->vbt.display_clock_mode;
9105                 can_ssc = has_ck505;
9106         } else {
9107                 has_ck505 = false;
9108                 can_ssc = true;
9109         }
9110
9111         /* Check if any DPLLs are using the SSC source */
9112         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9113                 u32 temp = I915_READ(PCH_DPLL(i));
9114
9115                 if (!(temp & DPLL_VCO_ENABLE))
9116                         continue;
9117
9118                 if ((temp & PLL_REF_INPUT_MASK) ==
9119                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9120                         using_ssc_source = true;
9121                         break;
9122                 }
9123         }
9124
9125         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9126                       has_panel, has_lvds, has_ck505, using_ssc_source);
9127
9128         /* Ironlake: try to setup display ref clock before DPLL
9129          * enabling. This is only under driver's control after
9130          * PCH B stepping, previous chipset stepping should be
9131          * ignoring this setting.
9132          */
9133         val = I915_READ(PCH_DREF_CONTROL);
9134
9135         /* As we must carefully and slowly disable/enable each source in turn,
9136          * compute the final state we want first and check if we need to
9137          * make any changes at all.
9138          */
9139         final = val;
9140         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9141         if (has_ck505)
9142                 final |= DREF_NONSPREAD_CK505_ENABLE;
9143         else
9144                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9145
9146         final &= ~DREF_SSC_SOURCE_MASK;
9147         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9148         final &= ~DREF_SSC1_ENABLE;
9149
9150         if (has_panel) {
9151                 final |= DREF_SSC_SOURCE_ENABLE;
9152
9153                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9154                         final |= DREF_SSC1_ENABLE;
9155
9156                 if (has_cpu_edp) {
9157                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9158                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9159                         else
9160                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9161                 } else
9162                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9163         } else if (using_ssc_source) {
9164                 final |= DREF_SSC_SOURCE_ENABLE;
9165                 final |= DREF_SSC1_ENABLE;
9166         }
9167
9168         if (final == val)
9169                 return;
9170
9171         /* Always enable nonspread source */
9172         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9173
9174         if (has_ck505)
9175                 val |= DREF_NONSPREAD_CK505_ENABLE;
9176         else
9177                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9178
9179         if (has_panel) {
9180                 val &= ~DREF_SSC_SOURCE_MASK;
9181                 val |= DREF_SSC_SOURCE_ENABLE;
9182
9183                 /* SSC must be turned on before enabling the CPU output  */
9184                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9185                         DRM_DEBUG_KMS("Using SSC on panel\n");
9186                         val |= DREF_SSC1_ENABLE;
9187                 } else
9188                         val &= ~DREF_SSC1_ENABLE;
9189
9190                 /* Get SSC going before enabling the outputs */
9191                 I915_WRITE(PCH_DREF_CONTROL, val);
9192                 POSTING_READ(PCH_DREF_CONTROL);
9193                 udelay(200);
9194
9195                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9196
9197                 /* Enable CPU source on CPU attached eDP */
9198                 if (has_cpu_edp) {
9199                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9200                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9201                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9202                         } else
9203                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9204                 } else
9205                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9206
9207                 I915_WRITE(PCH_DREF_CONTROL, val);
9208                 POSTING_READ(PCH_DREF_CONTROL);
9209                 udelay(200);
9210         } else {
9211                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9212
9213                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9214
9215                 /* Turn off CPU output */
9216                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9217
9218                 I915_WRITE(PCH_DREF_CONTROL, val);
9219                 POSTING_READ(PCH_DREF_CONTROL);
9220                 udelay(200);
9221
9222                 if (!using_ssc_source) {
9223                         DRM_DEBUG_KMS("Disabling SSC source\n");
9224
9225                         /* Turn off the SSC source */
9226                         val &= ~DREF_SSC_SOURCE_MASK;
9227                         val |= DREF_SSC_SOURCE_DISABLE;
9228
9229                         /* Turn off SSC1 */
9230                         val &= ~DREF_SSC1_ENABLE;
9231
9232                         I915_WRITE(PCH_DREF_CONTROL, val);
9233                         POSTING_READ(PCH_DREF_CONTROL);
9234                         udelay(200);
9235                 }
9236         }
9237
9238         BUG_ON(val != final);
9239 }
9240
9241 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9242 {
9243         u32 tmp;
9244
9245         tmp = I915_READ(SOUTH_CHICKEN2);
9246         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9247         I915_WRITE(SOUTH_CHICKEN2, tmp);
9248
9249         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9250                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9251                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9252
9253         tmp = I915_READ(SOUTH_CHICKEN2);
9254         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9255         I915_WRITE(SOUTH_CHICKEN2, tmp);
9256
9257         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9258                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9259                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9260 }
9261
9262 /* WaMPhyProgramming:hsw */
9263 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9264 {
9265         u32 tmp;
9266
9267         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9268         tmp &= ~(0xFF << 24);
9269         tmp |= (0x12 << 24);
9270         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9271
9272         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9273         tmp |= (1 << 11);
9274         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9275
9276         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9277         tmp |= (1 << 11);
9278         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9279
9280         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9281         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9282         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9283
9284         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9285         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9286         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9287
9288         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9289         tmp &= ~(7 << 13);
9290         tmp |= (5 << 13);
9291         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9292
9293         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9294         tmp &= ~(7 << 13);
9295         tmp |= (5 << 13);
9296         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9297
9298         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9299         tmp &= ~0xFF;
9300         tmp |= 0x1C;
9301         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9302
9303         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9304         tmp &= ~0xFF;
9305         tmp |= 0x1C;
9306         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9307
9308         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9309         tmp &= ~(0xFF << 16);
9310         tmp |= (0x1C << 16);
9311         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9312
9313         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9314         tmp &= ~(0xFF << 16);
9315         tmp |= (0x1C << 16);
9316         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9317
9318         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9319         tmp |= (1 << 27);
9320         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9321
9322         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9323         tmp |= (1 << 27);
9324         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9325
9326         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9327         tmp &= ~(0xF << 28);
9328         tmp |= (4 << 28);
9329         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9330
9331         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9332         tmp &= ~(0xF << 28);
9333         tmp |= (4 << 28);
9334         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9335 }
9336
9337 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9338  * Programming" based on the parameters passed:
9339  * - Sequence to enable CLKOUT_DP
9340  * - Sequence to enable CLKOUT_DP without spread
9341  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9342  */
9343 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9344                                  bool with_spread, bool with_fdi)
9345 {
9346         u32 reg, tmp;
9347
9348         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9349                 with_spread = true;
9350         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9351             with_fdi, "LP PCH doesn't have FDI\n"))
9352                 with_fdi = false;
9353
9354         mutex_lock(&dev_priv->sb_lock);
9355
9356         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9357         tmp &= ~SBI_SSCCTL_DISABLE;
9358         tmp |= SBI_SSCCTL_PATHALT;
9359         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9360
9361         udelay(24);
9362
9363         if (with_spread) {
9364                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9365                 tmp &= ~SBI_SSCCTL_PATHALT;
9366                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9367
9368                 if (with_fdi) {
9369                         lpt_reset_fdi_mphy(dev_priv);
9370                         lpt_program_fdi_mphy(dev_priv);
9371                 }
9372         }
9373
9374         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9375         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9376         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9377         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9378
9379         mutex_unlock(&dev_priv->sb_lock);
9380 }
9381
9382 /* Sequence to disable CLKOUT_DP */
9383 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9384 {
9385         u32 reg, tmp;
9386
9387         mutex_lock(&dev_priv->sb_lock);
9388
9389         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9390         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9391         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9392         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9393
9394         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9395         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9396                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9397                         tmp |= SBI_SSCCTL_PATHALT;
9398                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9399                         udelay(32);
9400                 }
9401                 tmp |= SBI_SSCCTL_DISABLE;
9402                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9403         }
9404
9405         mutex_unlock(&dev_priv->sb_lock);
9406 }
9407
9408 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9409
9410 static const u16 sscdivintphase[] = {
9411         [BEND_IDX( 50)] = 0x3B23,
9412         [BEND_IDX( 45)] = 0x3B23,
9413         [BEND_IDX( 40)] = 0x3C23,
9414         [BEND_IDX( 35)] = 0x3C23,
9415         [BEND_IDX( 30)] = 0x3D23,
9416         [BEND_IDX( 25)] = 0x3D23,
9417         [BEND_IDX( 20)] = 0x3E23,
9418         [BEND_IDX( 15)] = 0x3E23,
9419         [BEND_IDX( 10)] = 0x3F23,
9420         [BEND_IDX(  5)] = 0x3F23,
9421         [BEND_IDX(  0)] = 0x0025,
9422         [BEND_IDX( -5)] = 0x0025,
9423         [BEND_IDX(-10)] = 0x0125,
9424         [BEND_IDX(-15)] = 0x0125,
9425         [BEND_IDX(-20)] = 0x0225,
9426         [BEND_IDX(-25)] = 0x0225,
9427         [BEND_IDX(-30)] = 0x0325,
9428         [BEND_IDX(-35)] = 0x0325,
9429         [BEND_IDX(-40)] = 0x0425,
9430         [BEND_IDX(-45)] = 0x0425,
9431         [BEND_IDX(-50)] = 0x0525,
9432 };
9433
9434 /*
9435  * Bend CLKOUT_DP
9436  * steps -50 to 50 inclusive, in steps of 5
9437  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9438  * change in clock period = -(steps / 10) * 5.787 ps
9439  */
9440 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9441 {
9442         u32 tmp;
9443         int idx = BEND_IDX(steps);
9444
9445         if (WARN_ON(steps % 5 != 0))
9446                 return;
9447
9448         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9449                 return;
9450
9451         mutex_lock(&dev_priv->sb_lock);
9452
9453         if (steps % 10 != 0)
9454                 tmp = 0xAAAAAAAB;
9455         else
9456                 tmp = 0x00000000;
9457         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9458
9459         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9460         tmp &= 0xffff0000;
9461         tmp |= sscdivintphase[idx];
9462         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9463
9464         mutex_unlock(&dev_priv->sb_lock);
9465 }
9466
9467 #undef BEND_IDX
9468
9469 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9470 {
9471         u32 fuse_strap = I915_READ(FUSE_STRAP);
9472         u32 ctl = I915_READ(SPLL_CTL);
9473
9474         if ((ctl & SPLL_PLL_ENABLE) == 0)
9475                 return false;
9476
9477         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9478             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9479                 return true;
9480
9481         if (IS_BROADWELL(dev_priv) &&
9482             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9483                 return true;
9484
9485         return false;
9486 }
9487
9488 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9489                                enum intel_dpll_id id)
9490 {
9491         u32 fuse_strap = I915_READ(FUSE_STRAP);
9492         u32 ctl = I915_READ(WRPLL_CTL(id));
9493
9494         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9495                 return false;
9496
9497         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9498                 return true;
9499
9500         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9501             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9502             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9503                 return true;
9504
9505         return false;
9506 }
9507
9508 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9509 {
9510         struct intel_encoder *encoder;
9511         bool has_fdi = false;
9512
9513         for_each_intel_encoder(&dev_priv->drm, encoder) {
9514                 switch (encoder->type) {
9515                 case INTEL_OUTPUT_ANALOG:
9516                         has_fdi = true;
9517                         break;
9518                 default:
9519                         break;
9520                 }
9521         }
9522
9523         /*
9524          * The BIOS may have decided to use the PCH SSC
9525          * reference so we must not disable it until the
9526          * relevant PLLs have stopped relying on it. We'll
9527          * just leave the PCH SSC reference enabled in case
9528          * any active PLL is using it. It will get disabled
9529          * after runtime suspend if we don't have FDI.
9530          *
9531          * TODO: Move the whole reference clock handling
9532          * to the modeset sequence proper so that we can
9533          * actually enable/disable/reconfigure these things
9534          * safely. To do that we need to introduce a real
9535          * clock hierarchy. That would also allow us to do
9536          * clock bending finally.
9537          */
9538         dev_priv->pch_ssc_use = 0;
9539
9540         if (spll_uses_pch_ssc(dev_priv)) {
9541                 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9542                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9543         }
9544
9545         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9546                 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9547                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9548         }
9549
9550         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9551                 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9552                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9553         }
9554
9555         if (dev_priv->pch_ssc_use)
9556                 return;
9557
9558         if (has_fdi) {
9559                 lpt_bend_clkout_dp(dev_priv, 0);
9560                 lpt_enable_clkout_dp(dev_priv, true, true);
9561         } else {
9562                 lpt_disable_clkout_dp(dev_priv);
9563         }
9564 }
9565
9566 /*
9567  * Initialize reference clocks when the driver loads
9568  */
9569 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9570 {
9571         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9572                 ironlake_init_pch_refclk(dev_priv);
9573         else if (HAS_PCH_LPT(dev_priv))
9574                 lpt_init_pch_refclk(dev_priv);
9575 }
9576
9577 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9578 {
9579         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9580         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9581         enum pipe pipe = crtc->pipe;
9582         u32 val;
9583
9584         val = 0;
9585
9586         switch (crtc_state->pipe_bpp) {
9587         case 18:
9588                 val |= PIPECONF_6BPC;
9589                 break;
9590         case 24:
9591                 val |= PIPECONF_8BPC;
9592                 break;
9593         case 30:
9594                 val |= PIPECONF_10BPC;
9595                 break;
9596         case 36:
9597                 val |= PIPECONF_12BPC;
9598                 break;
9599         default:
9600                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9601                 BUG();
9602         }
9603
9604         if (crtc_state->dither)
9605                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9606
9607         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9608                 val |= PIPECONF_INTERLACED_ILK;
9609         else
9610                 val |= PIPECONF_PROGRESSIVE;
9611
9612         /*
9613          * This would end up with an odd purple hue over
9614          * the entire display. Make sure we don't do it.
9615          */
9616         WARN_ON(crtc_state->limited_color_range &&
9617                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
9618
9619         if (crtc_state->limited_color_range)
9620                 val |= PIPECONF_COLOR_RANGE_SELECT;
9621
9622         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9623                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
9624
9625         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9626
9627         val |= PIPECONF_FRAME_START_DELAY(0);
9628
9629         I915_WRITE(PIPECONF(pipe), val);
9630         POSTING_READ(PIPECONF(pipe));
9631 }
9632
9633 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9634 {
9635         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9636         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9637         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9638         u32 val = 0;
9639
9640         if (IS_HASWELL(dev_priv) && crtc_state->dither)
9641                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9642
9643         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9644                 val |= PIPECONF_INTERLACED_ILK;
9645         else
9646                 val |= PIPECONF_PROGRESSIVE;
9647
9648         if (IS_HASWELL(dev_priv) &&
9649             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9650                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
9651
9652         I915_WRITE(PIPECONF(cpu_transcoder), val);
9653         POSTING_READ(PIPECONF(cpu_transcoder));
9654 }
9655
9656 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9657 {
9658         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9659         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9660         u32 val = 0;
9661
9662         switch (crtc_state->pipe_bpp) {
9663         case 18:
9664                 val |= PIPEMISC_DITHER_6_BPC;
9665                 break;
9666         case 24:
9667                 val |= PIPEMISC_DITHER_8_BPC;
9668                 break;
9669         case 30:
9670                 val |= PIPEMISC_DITHER_10_BPC;
9671                 break;
9672         case 36:
9673                 val |= PIPEMISC_DITHER_12_BPC;
9674                 break;
9675         default:
9676                 MISSING_CASE(crtc_state->pipe_bpp);
9677                 break;
9678         }
9679
9680         if (crtc_state->dither)
9681                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9682
9683         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9684             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9685                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9686
9687         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9688                 val |= PIPEMISC_YUV420_ENABLE |
9689                         PIPEMISC_YUV420_MODE_FULL_BLEND;
9690
9691         if (INTEL_GEN(dev_priv) >= 11 &&
9692             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9693                                            BIT(PLANE_CURSOR))) == 0)
9694                 val |= PIPEMISC_HDR_MODE_PRECISION;
9695
9696         I915_WRITE(PIPEMISC(crtc->pipe), val);
9697 }
9698
9699 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9700 {
9701         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9702         u32 tmp;
9703
9704         tmp = I915_READ(PIPEMISC(crtc->pipe));
9705
9706         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9707         case PIPEMISC_DITHER_6_BPC:
9708                 return 18;
9709         case PIPEMISC_DITHER_8_BPC:
9710                 return 24;
9711         case PIPEMISC_DITHER_10_BPC:
9712                 return 30;
9713         case PIPEMISC_DITHER_12_BPC:
9714                 return 36;
9715         default:
9716                 MISSING_CASE(tmp);
9717                 return 0;
9718         }
9719 }
9720
9721 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9722 {
9723         /*
9724          * Account for spread spectrum to avoid
9725          * oversubscribing the link. Max center spread
9726          * is 2.5%; use 5% for safety's sake.
9727          */
9728         u32 bps = target_clock * bpp * 21 / 20;
9729         return DIV_ROUND_UP(bps, link_bw * 8);
9730 }
9731
9732 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9733 {
9734         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9735 }
9736
9737 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9738                                   struct intel_crtc_state *crtc_state,
9739                                   struct dpll *reduced_clock)
9740 {
9741         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9742         u32 dpll, fp, fp2;
9743         int factor;
9744
9745         /* Enable autotuning of the PLL clock (if permissible) */
9746         factor = 21;
9747         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9748                 if ((intel_panel_use_ssc(dev_priv) &&
9749                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9750                     (HAS_PCH_IBX(dev_priv) &&
9751                      intel_is_dual_link_lvds(dev_priv)))
9752                         factor = 25;
9753         } else if (crtc_state->sdvo_tv_clock) {
9754                 factor = 20;
9755         }
9756
9757         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9758
9759         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9760                 fp |= FP_CB_TUNE;
9761
9762         if (reduced_clock) {
9763                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9764
9765                 if (reduced_clock->m < factor * reduced_clock->n)
9766                         fp2 |= FP_CB_TUNE;
9767         } else {
9768                 fp2 = fp;
9769         }
9770
9771         dpll = 0;
9772
9773         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9774                 dpll |= DPLLB_MODE_LVDS;
9775         else
9776                 dpll |= DPLLB_MODE_DAC_SERIAL;
9777
9778         dpll |= (crtc_state->pixel_multiplier - 1)
9779                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9780
9781         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9782             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9783                 dpll |= DPLL_SDVO_HIGH_SPEED;
9784
9785         if (intel_crtc_has_dp_encoder(crtc_state))
9786                 dpll |= DPLL_SDVO_HIGH_SPEED;
9787
9788         /*
9789          * The high speed IO clock is only really required for
9790          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9791          * possible to share the DPLL between CRT and HDMI. Enabling
9792          * the clock needlessly does no real harm, except use up a
9793          * bit of power potentially.
9794          *
9795          * We'll limit this to IVB with 3 pipes, since it has only two
9796          * DPLLs and so DPLL sharing is the only way to get three pipes
9797          * driving PCH ports at the same time. On SNB we could do this,
9798          * and potentially avoid enabling the second DPLL, but it's not
9799          * clear if it''s a win or loss power wise. No point in doing
9800          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9801          */
9802         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
9803             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9804                 dpll |= DPLL_SDVO_HIGH_SPEED;
9805
9806         /* compute bitmask from p1 value */
9807         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9808         /* also FPA1 */
9809         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9810
9811         switch (crtc_state->dpll.p2) {
9812         case 5:
9813                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9814                 break;
9815         case 7:
9816                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9817                 break;
9818         case 10:
9819                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9820                 break;
9821         case 14:
9822                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9823                 break;
9824         }
9825
9826         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9827             intel_panel_use_ssc(dev_priv))
9828                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9829         else
9830                 dpll |= PLL_REF_INPUT_DREFCLK;
9831
9832         dpll |= DPLL_VCO_ENABLE;
9833
9834         crtc_state->dpll_hw_state.dpll = dpll;
9835         crtc_state->dpll_hw_state.fp0 = fp;
9836         crtc_state->dpll_hw_state.fp1 = fp2;
9837 }
9838
9839 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9840                                        struct intel_crtc_state *crtc_state)
9841 {
9842         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9843         struct intel_atomic_state *state =
9844                 to_intel_atomic_state(crtc_state->uapi.state);
9845         const struct intel_limit *limit;
9846         int refclk = 120000;
9847
9848         memset(&crtc_state->dpll_hw_state, 0,
9849                sizeof(crtc_state->dpll_hw_state));
9850
9851         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9852         if (!crtc_state->has_pch_encoder)
9853                 return 0;
9854
9855         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9856                 if (intel_panel_use_ssc(dev_priv)) {
9857                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9858                                       dev_priv->vbt.lvds_ssc_freq);
9859                         refclk = dev_priv->vbt.lvds_ssc_freq;
9860                 }
9861
9862                 if (intel_is_dual_link_lvds(dev_priv)) {
9863                         if (refclk == 100000)
9864                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9865                         else
9866                                 limit = &intel_limits_ironlake_dual_lvds;
9867                 } else {
9868                         if (refclk == 100000)
9869                                 limit = &intel_limits_ironlake_single_lvds_100m;
9870                         else
9871                                 limit = &intel_limits_ironlake_single_lvds;
9872                 }
9873         } else {
9874                 limit = &intel_limits_ironlake_dac;
9875         }
9876
9877         if (!crtc_state->clock_set &&
9878             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9879                                 refclk, NULL, &crtc_state->dpll)) {
9880                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9881                 return -EINVAL;
9882         }
9883
9884         ironlake_compute_dpll(crtc, crtc_state, NULL);
9885
9886         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9887                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9888                               pipe_name(crtc->pipe));
9889                 return -EINVAL;
9890         }
9891
9892         return 0;
9893 }
9894
9895 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9896                                          struct intel_link_m_n *m_n)
9897 {
9898         struct drm_device *dev = crtc->base.dev;
9899         struct drm_i915_private *dev_priv = to_i915(dev);
9900         enum pipe pipe = crtc->pipe;
9901
9902         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9903         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9904         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9905                 & ~TU_SIZE_MASK;
9906         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9907         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9908                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9909 }
9910
9911 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9912                                          enum transcoder transcoder,
9913                                          struct intel_link_m_n *m_n,
9914                                          struct intel_link_m_n *m2_n2)
9915 {
9916         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9917         enum pipe pipe = crtc->pipe;
9918
9919         if (INTEL_GEN(dev_priv) >= 5) {
9920                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9921                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9922                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9923                         & ~TU_SIZE_MASK;
9924                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9925                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9926                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9927
9928                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9929                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9930                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9931                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9932                                         & ~TU_SIZE_MASK;
9933                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9934                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9935                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9936                 }
9937         } else {
9938                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9939                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9940                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9941                         & ~TU_SIZE_MASK;
9942                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9943                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9944                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9945         }
9946 }
9947
9948 void intel_dp_get_m_n(struct intel_crtc *crtc,
9949                       struct intel_crtc_state *pipe_config)
9950 {
9951         if (pipe_config->has_pch_encoder)
9952                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9953         else
9954                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9955                                              &pipe_config->dp_m_n,
9956                                              &pipe_config->dp_m2_n2);
9957 }
9958
9959 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9960                                         struct intel_crtc_state *pipe_config)
9961 {
9962         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9963                                      &pipe_config->fdi_m_n, NULL);
9964 }
9965
9966 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9967                                     struct intel_crtc_state *pipe_config)
9968 {
9969         struct drm_device *dev = crtc->base.dev;
9970         struct drm_i915_private *dev_priv = to_i915(dev);
9971         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9972         u32 ps_ctrl = 0;
9973         int id = -1;
9974         int i;
9975
9976         /* find scaler attached to this pipe */
9977         for (i = 0; i < crtc->num_scalers; i++) {
9978                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9979                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9980                         id = i;
9981                         pipe_config->pch_pfit.enabled = true;
9982                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9983                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9984                         scaler_state->scalers[i].in_use = true;
9985                         break;
9986                 }
9987         }
9988
9989         scaler_state->scaler_id = id;
9990         if (id >= 0) {
9991                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9992         } else {
9993                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9994         }
9995 }
9996
9997 static void
9998 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9999                                  struct intel_initial_plane_config *plane_config)
10000 {
10001         struct drm_device *dev = crtc->base.dev;
10002         struct drm_i915_private *dev_priv = to_i915(dev);
10003         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10004         enum plane_id plane_id = plane->id;
10005         enum pipe pipe;
10006         u32 val, base, offset, stride_mult, tiling, alpha;
10007         int fourcc, pixel_format;
10008         unsigned int aligned_height;
10009         struct drm_framebuffer *fb;
10010         struct intel_framebuffer *intel_fb;
10011
10012         if (!plane->get_hw_state(plane, &pipe))
10013                 return;
10014
10015         WARN_ON(pipe != crtc->pipe);
10016
10017         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10018         if (!intel_fb) {
10019                 DRM_DEBUG_KMS("failed to alloc fb\n");
10020                 return;
10021         }
10022
10023         fb = &intel_fb->base;
10024
10025         fb->dev = dev;
10026
10027         val = I915_READ(PLANE_CTL(pipe, plane_id));
10028
10029         if (INTEL_GEN(dev_priv) >= 11)
10030                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10031         else
10032                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10033
10034         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10035                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
10036                 alpha &= PLANE_COLOR_ALPHA_MASK;
10037         } else {
10038                 alpha = val & PLANE_CTL_ALPHA_MASK;
10039         }
10040
10041         fourcc = skl_format_to_fourcc(pixel_format,
10042                                       val & PLANE_CTL_ORDER_RGBX, alpha);
10043         fb->format = drm_format_info(fourcc);
10044
10045         tiling = val & PLANE_CTL_TILED_MASK;
10046         switch (tiling) {
10047         case PLANE_CTL_TILED_LINEAR:
10048                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10049                 break;
10050         case PLANE_CTL_TILED_X:
10051                 plane_config->tiling = I915_TILING_X;
10052                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10053                 break;
10054         case PLANE_CTL_TILED_Y:
10055                 plane_config->tiling = I915_TILING_Y;
10056                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10057                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
10058                 else
10059                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10060                 break;
10061         case PLANE_CTL_TILED_YF:
10062                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10063                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10064                 else
10065                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10066                 break;
10067         default:
10068                 MISSING_CASE(tiling);
10069                 goto error;
10070         }
10071
10072         /*
10073          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10074          * while i915 HW rotation is clockwise, thats why this swapping.
10075          */
10076         switch (val & PLANE_CTL_ROTATE_MASK) {
10077         case PLANE_CTL_ROTATE_0:
10078                 plane_config->rotation = DRM_MODE_ROTATE_0;
10079                 break;
10080         case PLANE_CTL_ROTATE_90:
10081                 plane_config->rotation = DRM_MODE_ROTATE_270;
10082                 break;
10083         case PLANE_CTL_ROTATE_180:
10084                 plane_config->rotation = DRM_MODE_ROTATE_180;
10085                 break;
10086         case PLANE_CTL_ROTATE_270:
10087                 plane_config->rotation = DRM_MODE_ROTATE_90;
10088                 break;
10089         }
10090
10091         if (INTEL_GEN(dev_priv) >= 10 &&
10092             val & PLANE_CTL_FLIP_HORIZONTAL)
10093                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10094
10095         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10096         plane_config->base = base;
10097
10098         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
10099
10100         val = I915_READ(PLANE_SIZE(pipe, plane_id));
10101         fb->height = ((val >> 16) & 0xffff) + 1;
10102         fb->width = ((val >> 0) & 0xffff) + 1;
10103
10104         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
10105         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10106         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10107
10108         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10109
10110         plane_config->size = fb->pitches[0] * aligned_height;
10111
10112         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10113                       crtc->base.name, plane->base.name, fb->width, fb->height,
10114                       fb->format->cpp[0] * 8, base, fb->pitches[0],
10115                       plane_config->size);
10116
10117         plane_config->fb = intel_fb;
10118         return;
10119
10120 error:
10121         kfree(intel_fb);
10122 }
10123
10124 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
10125                                      struct intel_crtc_state *pipe_config)
10126 {
10127         struct drm_device *dev = crtc->base.dev;
10128         struct drm_i915_private *dev_priv = to_i915(dev);
10129         u32 tmp;
10130
10131         tmp = I915_READ(PF_CTL(crtc->pipe));
10132
10133         if (tmp & PF_ENABLE) {
10134                 pipe_config->pch_pfit.enabled = true;
10135                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
10136                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
10137
10138                 /* We currently do not free assignements of panel fitters on
10139                  * ivb/hsw (since we don't use the higher upscaling modes which
10140                  * differentiates them) so just WARN about this case for now. */
10141                 if (IS_GEN(dev_priv, 7)) {
10142                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
10143                                 PF_PIPE_SEL_IVB(crtc->pipe));
10144                 }
10145         }
10146 }
10147
10148 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
10149                                      struct intel_crtc_state *pipe_config)
10150 {
10151         struct drm_device *dev = crtc->base.dev;
10152         struct drm_i915_private *dev_priv = to_i915(dev);
10153         enum intel_display_power_domain power_domain;
10154         intel_wakeref_t wakeref;
10155         u32 tmp;
10156         bool ret;
10157
10158         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10159         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10160         if (!wakeref)
10161                 return false;
10162
10163         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10164         pipe_config->shared_dpll = NULL;
10165         pipe_config->master_transcoder = INVALID_TRANSCODER;
10166
10167         ret = false;
10168         tmp = I915_READ(PIPECONF(crtc->pipe));
10169         if (!(tmp & PIPECONF_ENABLE))
10170                 goto out;
10171
10172         switch (tmp & PIPECONF_BPC_MASK) {
10173         case PIPECONF_6BPC:
10174                 pipe_config->pipe_bpp = 18;
10175                 break;
10176         case PIPECONF_8BPC:
10177                 pipe_config->pipe_bpp = 24;
10178                 break;
10179         case PIPECONF_10BPC:
10180                 pipe_config->pipe_bpp = 30;
10181                 break;
10182         case PIPECONF_12BPC:
10183                 pipe_config->pipe_bpp = 36;
10184                 break;
10185         default:
10186                 break;
10187         }
10188
10189         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10190                 pipe_config->limited_color_range = true;
10191
10192         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10193         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10194         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10195                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10196                 break;
10197         default:
10198                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10199                 break;
10200         }
10201
10202         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10203                 PIPECONF_GAMMA_MODE_SHIFT;
10204
10205         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10206
10207         i9xx_get_pipe_color_config(pipe_config);
10208         intel_color_get_config(pipe_config);
10209
10210         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10211                 struct intel_shared_dpll *pll;
10212                 enum intel_dpll_id pll_id;
10213
10214                 pipe_config->has_pch_encoder = true;
10215
10216                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
10217                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10218                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10219
10220                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10221
10222                 if (HAS_PCH_IBX(dev_priv)) {
10223                         /*
10224                          * The pipe->pch transcoder and pch transcoder->pll
10225                          * mapping is fixed.
10226                          */
10227                         pll_id = (enum intel_dpll_id) crtc->pipe;
10228                 } else {
10229                         tmp = I915_READ(PCH_DPLL_SEL);
10230                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10231                                 pll_id = DPLL_ID_PCH_PLL_B;
10232                         else
10233                                 pll_id= DPLL_ID_PCH_PLL_A;
10234                 }
10235
10236                 pipe_config->shared_dpll =
10237                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10238                 pll = pipe_config->shared_dpll;
10239
10240                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10241                                                 &pipe_config->dpll_hw_state));
10242
10243                 tmp = pipe_config->dpll_hw_state.dpll;
10244                 pipe_config->pixel_multiplier =
10245                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10246                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10247
10248                 ironlake_pch_clock_get(crtc, pipe_config);
10249         } else {
10250                 pipe_config->pixel_multiplier = 1;
10251         }
10252
10253         intel_get_pipe_timings(crtc, pipe_config);
10254         intel_get_pipe_src_size(crtc, pipe_config);
10255
10256         ironlake_get_pfit_config(crtc, pipe_config);
10257
10258         ret = true;
10259
10260 out:
10261         intel_display_power_put(dev_priv, power_domain, wakeref);
10262
10263         return ret;
10264 }
10265 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10266                                       struct intel_crtc_state *crtc_state)
10267 {
10268         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10269         struct intel_atomic_state *state =
10270                 to_intel_atomic_state(crtc_state->uapi.state);
10271
10272         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10273             INTEL_GEN(dev_priv) >= 11) {
10274                 struct intel_encoder *encoder =
10275                         intel_get_crtc_new_encoder(state, crtc_state);
10276
10277                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10278                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10279                                       pipe_name(crtc->pipe));
10280                         return -EINVAL;
10281                 }
10282         }
10283
10284         return 0;
10285 }
10286
10287 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10288                                    enum port port,
10289                                    struct intel_crtc_state *pipe_config)
10290 {
10291         enum intel_dpll_id id;
10292         u32 temp;
10293
10294         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10295         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10296
10297         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10298                 return;
10299
10300         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10301 }
10302
10303 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10304                                 enum port port,
10305                                 struct intel_crtc_state *pipe_config)
10306 {
10307         enum phy phy = intel_port_to_phy(dev_priv, port);
10308         enum icl_port_dpll_id port_dpll_id;
10309         enum intel_dpll_id id;
10310         u32 temp;
10311
10312         if (intel_phy_is_combo(dev_priv, phy)) {
10313                 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10314                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10315                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10316                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10317         } else if (intel_phy_is_tc(dev_priv, phy)) {
10318                 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10319
10320                 if (clk_sel == DDI_CLK_SEL_MG) {
10321                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10322                                                                     port));
10323                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10324                 } else {
10325                         WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10326                         id = DPLL_ID_ICL_TBTPLL;
10327                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10328                 }
10329         } else {
10330                 WARN(1, "Invalid port %x\n", port);
10331                 return;
10332         }
10333
10334         pipe_config->icl_port_dplls[port_dpll_id].pll =
10335                 intel_get_shared_dpll_by_id(dev_priv, id);
10336
10337         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10338 }
10339
10340 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10341                                 enum port port,
10342                                 struct intel_crtc_state *pipe_config)
10343 {
10344         enum intel_dpll_id id;
10345
10346         switch (port) {
10347         case PORT_A:
10348                 id = DPLL_ID_SKL_DPLL0;
10349                 break;
10350         case PORT_B:
10351                 id = DPLL_ID_SKL_DPLL1;
10352                 break;
10353         case PORT_C:
10354                 id = DPLL_ID_SKL_DPLL2;
10355                 break;
10356         default:
10357                 DRM_ERROR("Incorrect port type\n");
10358                 return;
10359         }
10360
10361         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10362 }
10363
10364 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10365                                 enum port port,
10366                                 struct intel_crtc_state *pipe_config)
10367 {
10368         enum intel_dpll_id id;
10369         u32 temp;
10370
10371         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10372         id = temp >> (port * 3 + 1);
10373
10374         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10375                 return;
10376
10377         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10378 }
10379
10380 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10381                                 enum port port,
10382                                 struct intel_crtc_state *pipe_config)
10383 {
10384         enum intel_dpll_id id;
10385         u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10386
10387         switch (ddi_pll_sel) {
10388         case PORT_CLK_SEL_WRPLL1:
10389                 id = DPLL_ID_WRPLL1;
10390                 break;
10391         case PORT_CLK_SEL_WRPLL2:
10392                 id = DPLL_ID_WRPLL2;
10393                 break;
10394         case PORT_CLK_SEL_SPLL:
10395                 id = DPLL_ID_SPLL;
10396                 break;
10397         case PORT_CLK_SEL_LCPLL_810:
10398                 id = DPLL_ID_LCPLL_810;
10399                 break;
10400         case PORT_CLK_SEL_LCPLL_1350:
10401                 id = DPLL_ID_LCPLL_1350;
10402                 break;
10403         case PORT_CLK_SEL_LCPLL_2700:
10404                 id = DPLL_ID_LCPLL_2700;
10405                 break;
10406         default:
10407                 MISSING_CASE(ddi_pll_sel);
10408                 /* fall through */
10409         case PORT_CLK_SEL_NONE:
10410                 return;
10411         }
10412
10413         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10414 }
10415
10416 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10417                                      struct intel_crtc_state *pipe_config,
10418                                      u64 *power_domain_mask,
10419                                      intel_wakeref_t *wakerefs)
10420 {
10421         struct drm_device *dev = crtc->base.dev;
10422         struct drm_i915_private *dev_priv = to_i915(dev);
10423         enum intel_display_power_domain power_domain;
10424         unsigned long panel_transcoder_mask = 0;
10425         unsigned long enabled_panel_transcoders = 0;
10426         enum transcoder panel_transcoder;
10427         intel_wakeref_t wf;
10428         u32 tmp;
10429
10430         if (INTEL_GEN(dev_priv) >= 11)
10431                 panel_transcoder_mask |=
10432                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10433
10434         if (HAS_TRANSCODER_EDP(dev_priv))
10435                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10436
10437         /*
10438          * The pipe->transcoder mapping is fixed with the exception of the eDP
10439          * and DSI transcoders handled below.
10440          */
10441         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10442
10443         /*
10444          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10445          * consistency and less surprising code; it's in always on power).
10446          */
10447         for_each_set_bit(panel_transcoder,
10448                          &panel_transcoder_mask,
10449                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10450                 bool force_thru = false;
10451                 enum pipe trans_pipe;
10452
10453                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10454                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10455                         continue;
10456
10457                 /*
10458                  * Log all enabled ones, only use the first one.
10459                  *
10460                  * FIXME: This won't work for two separate DSI displays.
10461                  */
10462                 enabled_panel_transcoders |= BIT(panel_transcoder);
10463                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10464                         continue;
10465
10466                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10467                 default:
10468                         WARN(1, "unknown pipe linked to transcoder %s\n",
10469                              transcoder_name(panel_transcoder));
10470                         /* fall through */
10471                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10472                         force_thru = true;
10473                         /* fall through */
10474                 case TRANS_DDI_EDP_INPUT_A_ON:
10475                         trans_pipe = PIPE_A;
10476                         break;
10477                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10478                         trans_pipe = PIPE_B;
10479                         break;
10480                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10481                         trans_pipe = PIPE_C;
10482                         break;
10483                 }
10484
10485                 if (trans_pipe == crtc->pipe) {
10486                         pipe_config->cpu_transcoder = panel_transcoder;
10487                         pipe_config->pch_pfit.force_thru = force_thru;
10488                 }
10489         }
10490
10491         /*
10492          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10493          */
10494         WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10495                 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10496
10497         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10498         WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10499
10500         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10501         if (!wf)
10502                 return false;
10503
10504         wakerefs[power_domain] = wf;
10505         *power_domain_mask |= BIT_ULL(power_domain);
10506
10507         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10508
10509         return tmp & PIPECONF_ENABLE;
10510 }
10511
10512 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10513                                          struct intel_crtc_state *pipe_config,
10514                                          u64 *power_domain_mask,
10515                                          intel_wakeref_t *wakerefs)
10516 {
10517         struct drm_device *dev = crtc->base.dev;
10518         struct drm_i915_private *dev_priv = to_i915(dev);
10519         enum intel_display_power_domain power_domain;
10520         enum transcoder cpu_transcoder;
10521         intel_wakeref_t wf;
10522         enum port port;
10523         u32 tmp;
10524
10525         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10526                 if (port == PORT_A)
10527                         cpu_transcoder = TRANSCODER_DSI_A;
10528                 else
10529                         cpu_transcoder = TRANSCODER_DSI_C;
10530
10531                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10532                 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10533
10534                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10535                 if (!wf)
10536                         continue;
10537
10538                 wakerefs[power_domain] = wf;
10539                 *power_domain_mask |= BIT_ULL(power_domain);
10540
10541                 /*
10542                  * The PLL needs to be enabled with a valid divider
10543                  * configuration, otherwise accessing DSI registers will hang
10544                  * the machine. See BSpec North Display Engine
10545                  * registers/MIPI[BXT]. We can break out here early, since we
10546                  * need the same DSI PLL to be enabled for both DSI ports.
10547                  */
10548                 if (!bxt_dsi_pll_is_enabled(dev_priv))
10549                         break;
10550
10551                 /* XXX: this works for video mode only */
10552                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10553                 if (!(tmp & DPI_ENABLE))
10554                         continue;
10555
10556                 tmp = I915_READ(MIPI_CTRL(port));
10557                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10558                         continue;
10559
10560                 pipe_config->cpu_transcoder = cpu_transcoder;
10561                 break;
10562         }
10563
10564         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10565 }
10566
10567 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10568                                        struct intel_crtc_state *pipe_config)
10569 {
10570         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10571         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
10572         struct intel_shared_dpll *pll;
10573         enum port port;
10574         u32 tmp;
10575
10576         if (transcoder_is_dsi(cpu_transcoder)) {
10577                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
10578                                                 PORT_A : PORT_B;
10579         } else {
10580                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
10581                 if (INTEL_GEN(dev_priv) >= 12)
10582                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10583                 else
10584                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10585         }
10586
10587         if (INTEL_GEN(dev_priv) >= 11)
10588                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10589         else if (IS_CANNONLAKE(dev_priv))
10590                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10591         else if (IS_GEN9_BC(dev_priv))
10592                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10593         else if (IS_GEN9_LP(dev_priv))
10594                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10595         else
10596                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10597
10598         pll = pipe_config->shared_dpll;
10599         if (pll) {
10600                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10601                                                 &pipe_config->dpll_hw_state));
10602         }
10603
10604         /*
10605          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10606          * DDI E. So just check whether this pipe is wired to DDI E and whether
10607          * the PCH transcoder is on.
10608          */
10609         if (INTEL_GEN(dev_priv) < 9 &&
10610             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10611                 pipe_config->has_pch_encoder = true;
10612
10613                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10614                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10615                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10616
10617                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10618         }
10619 }
10620
10621 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
10622                                                  enum transcoder cpu_transcoder)
10623 {
10624         u32 trans_port_sync, master_select;
10625
10626         trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
10627
10628         if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
10629                 return INVALID_TRANSCODER;
10630
10631         master_select = trans_port_sync &
10632                         PORT_SYNC_MODE_MASTER_SELECT_MASK;
10633         if (master_select == 0)
10634                 return TRANSCODER_EDP;
10635         else
10636                 return master_select - 1;
10637 }
10638
10639 static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
10640 {
10641         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
10642         u32 transcoders;
10643         enum transcoder cpu_transcoder;
10644
10645         crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
10646                                                                   crtc_state->cpu_transcoder);
10647
10648         transcoders = BIT(TRANSCODER_A) |
10649                 BIT(TRANSCODER_B) |
10650                 BIT(TRANSCODER_C) |
10651                 BIT(TRANSCODER_D);
10652         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
10653                 enum intel_display_power_domain power_domain;
10654                 intel_wakeref_t trans_wakeref;
10655
10656                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10657                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
10658                                                                    power_domain);
10659
10660                 if (!trans_wakeref)
10661                         continue;
10662
10663                 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
10664                     crtc_state->cpu_transcoder)
10665                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
10666
10667                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
10668         }
10669
10670         WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
10671                 crtc_state->sync_mode_slaves_mask);
10672 }
10673
10674 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10675                                     struct intel_crtc_state *pipe_config)
10676 {
10677         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10678         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10679         enum intel_display_power_domain power_domain;
10680         u64 power_domain_mask;
10681         bool active;
10682
10683         intel_crtc_init_scalers(crtc, pipe_config);
10684
10685         pipe_config->master_transcoder = INVALID_TRANSCODER;
10686
10687         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10688         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10689         if (!wf)
10690                 return false;
10691
10692         wakerefs[power_domain] = wf;
10693         power_domain_mask = BIT_ULL(power_domain);
10694
10695         pipe_config->shared_dpll = NULL;
10696
10697         active = hsw_get_transcoder_state(crtc, pipe_config,
10698                                           &power_domain_mask, wakerefs);
10699
10700         if (IS_GEN9_LP(dev_priv) &&
10701             bxt_get_dsi_transcoder_state(crtc, pipe_config,
10702                                          &power_domain_mask, wakerefs)) {
10703                 WARN_ON(active);
10704                 active = true;
10705         }
10706
10707         if (!active)
10708                 goto out;
10709
10710         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10711             INTEL_GEN(dev_priv) >= 11) {
10712                 haswell_get_ddi_port_state(crtc, pipe_config);
10713                 intel_get_pipe_timings(crtc, pipe_config);
10714         }
10715
10716         intel_get_pipe_src_size(crtc, pipe_config);
10717
10718         if (IS_HASWELL(dev_priv)) {
10719                 u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10720
10721                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
10722                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10723                 else
10724                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10725         } else {
10726                 pipe_config->output_format =
10727                         bdw_get_pipemisc_output_format(crtc);
10728
10729                 /*
10730                  * Currently there is no interface defined to
10731                  * check user preference between RGB/YCBCR444
10732                  * or YCBCR420. So the only possible case for
10733                  * YCBCR444 usage is driving YCBCR420 output
10734                  * with LSPCON, when pipe is configured for
10735                  * YCBCR444 output and LSPCON takes care of
10736                  * downsampling it.
10737                  */
10738                 pipe_config->lspcon_downsampling =
10739                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
10740         }
10741
10742         pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10743
10744         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10745
10746         if (INTEL_GEN(dev_priv) >= 9) {
10747                 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10748
10749                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10750                         pipe_config->gamma_enable = true;
10751
10752                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10753                         pipe_config->csc_enable = true;
10754         } else {
10755                 i9xx_get_pipe_color_config(pipe_config);
10756         }
10757
10758         intel_color_get_config(pipe_config);
10759
10760         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10761         WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10762
10763         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10764         if (wf) {
10765                 wakerefs[power_domain] = wf;
10766                 power_domain_mask |= BIT_ULL(power_domain);
10767
10768                 if (INTEL_GEN(dev_priv) >= 9)
10769                         skylake_get_pfit_config(crtc, pipe_config);
10770                 else
10771                         ironlake_get_pfit_config(crtc, pipe_config);
10772         }
10773
10774         if (hsw_crtc_supports_ips(crtc)) {
10775                 if (IS_HASWELL(dev_priv))
10776                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10777                 else {
10778                         /*
10779                          * We cannot readout IPS state on broadwell, set to
10780                          * true so we can set it to a defined state on first
10781                          * commit.
10782                          */
10783                         pipe_config->ips_enabled = true;
10784                 }
10785         }
10786
10787         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10788             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10789                 pipe_config->pixel_multiplier =
10790                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10791         } else {
10792                 pipe_config->pixel_multiplier = 1;
10793         }
10794
10795         if (INTEL_GEN(dev_priv) >= 11 &&
10796             !transcoder_is_dsi(pipe_config->cpu_transcoder))
10797                 icelake_get_trans_port_sync_config(pipe_config);
10798
10799 out:
10800         for_each_power_domain(power_domain, power_domain_mask)
10801                 intel_display_power_put(dev_priv,
10802                                         power_domain, wakerefs[power_domain]);
10803
10804         return active;
10805 }
10806
10807 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10808 {
10809         struct drm_i915_private *dev_priv =
10810                 to_i915(plane_state->uapi.plane->dev);
10811         const struct drm_framebuffer *fb = plane_state->hw.fb;
10812         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10813         u32 base;
10814
10815         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10816                 base = obj->phys_handle->busaddr;
10817         else
10818                 base = intel_plane_ggtt_offset(plane_state);
10819
10820         return base + plane_state->color_plane[0].offset;
10821 }
10822
10823 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10824 {
10825         int x = plane_state->uapi.dst.x1;
10826         int y = plane_state->uapi.dst.y1;
10827         u32 pos = 0;
10828
10829         if (x < 0) {
10830                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10831                 x = -x;
10832         }
10833         pos |= x << CURSOR_X_SHIFT;
10834
10835         if (y < 0) {
10836                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10837                 y = -y;
10838         }
10839         pos |= y << CURSOR_Y_SHIFT;
10840
10841         return pos;
10842 }
10843
10844 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10845 {
10846         const struct drm_mode_config *config =
10847                 &plane_state->uapi.plane->dev->mode_config;
10848         int width = drm_rect_width(&plane_state->uapi.dst);
10849         int height = drm_rect_height(&plane_state->uapi.dst);
10850
10851         return width > 0 && width <= config->cursor_width &&
10852                 height > 0 && height <= config->cursor_height;
10853 }
10854
10855 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10856 {
10857         struct drm_i915_private *dev_priv =
10858                 to_i915(plane_state->uapi.plane->dev);
10859         unsigned int rotation = plane_state->hw.rotation;
10860         int src_x, src_y;
10861         u32 offset;
10862         int ret;
10863
10864         ret = intel_plane_compute_gtt(plane_state);
10865         if (ret)
10866                 return ret;
10867
10868         if (!plane_state->uapi.visible)
10869                 return 0;
10870
10871         src_x = plane_state->uapi.src.x1 >> 16;
10872         src_y = plane_state->uapi.src.y1 >> 16;
10873
10874         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10875         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10876                                                     plane_state, 0);
10877
10878         if (src_x != 0 || src_y != 0) {
10879                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10880                 return -EINVAL;
10881         }
10882
10883         /*
10884          * Put the final coordinates back so that the src
10885          * coordinate checks will see the right values.
10886          */
10887         drm_rect_translate_to(&plane_state->uapi.src,
10888                               src_x << 16, src_y << 16);
10889
10890         /* ILK+ do this automagically in hardware */
10891         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
10892                 const struct drm_framebuffer *fb = plane_state->hw.fb;
10893                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
10894                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
10895
10896                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
10897         }
10898
10899         plane_state->color_plane[0].offset = offset;
10900         plane_state->color_plane[0].x = src_x;
10901         plane_state->color_plane[0].y = src_y;
10902
10903         return 0;
10904 }
10905
10906 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10907                               struct intel_plane_state *plane_state)
10908 {
10909         const struct drm_framebuffer *fb = plane_state->hw.fb;
10910         int ret;
10911
10912         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10913                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10914                 return -EINVAL;
10915         }
10916
10917         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
10918                                                   &crtc_state->uapi,
10919                                                   DRM_PLANE_HELPER_NO_SCALING,
10920                                                   DRM_PLANE_HELPER_NO_SCALING,
10921                                                   true, true);
10922         if (ret)
10923                 return ret;
10924
10925         /* Use the unclipped src/dst rectangles, which we program to hw */
10926         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
10927         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
10928
10929         ret = intel_cursor_check_surface(plane_state);
10930         if (ret)
10931                 return ret;
10932
10933         if (!plane_state->uapi.visible)
10934                 return 0;
10935
10936         ret = intel_plane_check_src_coordinates(plane_state);
10937         if (ret)
10938                 return ret;
10939
10940         return 0;
10941 }
10942
10943 static unsigned int
10944 i845_cursor_max_stride(struct intel_plane *plane,
10945                        u32 pixel_format, u64 modifier,
10946                        unsigned int rotation)
10947 {
10948         return 2048;
10949 }
10950
10951 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10952 {
10953         u32 cntl = 0;
10954
10955         if (crtc_state->gamma_enable)
10956                 cntl |= CURSOR_GAMMA_ENABLE;
10957
10958         return cntl;
10959 }
10960
10961 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10962                            const struct intel_plane_state *plane_state)
10963 {
10964         return CURSOR_ENABLE |
10965                 CURSOR_FORMAT_ARGB |
10966                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10967 }
10968
10969 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10970 {
10971         int width = drm_rect_width(&plane_state->uapi.dst);
10972
10973         /*
10974          * 845g/865g are only limited by the width of their cursors,
10975          * the height is arbitrary up to the precision of the register.
10976          */
10977         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10978 }
10979
10980 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10981                              struct intel_plane_state *plane_state)
10982 {
10983         const struct drm_framebuffer *fb = plane_state->hw.fb;
10984         int ret;
10985
10986         ret = intel_check_cursor(crtc_state, plane_state);
10987         if (ret)
10988                 return ret;
10989
10990         /* if we want to turn off the cursor ignore width and height */
10991         if (!fb)
10992                 return 0;
10993
10994         /* Check for which cursor types we support */
10995         if (!i845_cursor_size_ok(plane_state)) {
10996                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10997                           drm_rect_width(&plane_state->uapi.dst),
10998                           drm_rect_height(&plane_state->uapi.dst));
10999                 return -EINVAL;
11000         }
11001
11002         WARN_ON(plane_state->uapi.visible &&
11003                 plane_state->color_plane[0].stride != fb->pitches[0]);
11004
11005         switch (fb->pitches[0]) {
11006         case 256:
11007         case 512:
11008         case 1024:
11009         case 2048:
11010                 break;
11011         default:
11012                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
11013                               fb->pitches[0]);
11014                 return -EINVAL;
11015         }
11016
11017         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11018
11019         return 0;
11020 }
11021
11022 static void i845_update_cursor(struct intel_plane *plane,
11023                                const struct intel_crtc_state *crtc_state,
11024                                const struct intel_plane_state *plane_state)
11025 {
11026         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11027         u32 cntl = 0, base = 0, pos = 0, size = 0;
11028         unsigned long irqflags;
11029
11030         if (plane_state && plane_state->uapi.visible) {
11031                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11032                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11033
11034                 cntl = plane_state->ctl |
11035                         i845_cursor_ctl_crtc(crtc_state);
11036
11037                 size = (height << 12) | width;
11038
11039                 base = intel_cursor_base(plane_state);
11040                 pos = intel_cursor_position(plane_state);
11041         }
11042
11043         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11044
11045         /* On these chipsets we can only modify the base/size/stride
11046          * whilst the cursor is disabled.
11047          */
11048         if (plane->cursor.base != base ||
11049             plane->cursor.size != size ||
11050             plane->cursor.cntl != cntl) {
11051                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
11052                 I915_WRITE_FW(CURBASE(PIPE_A), base);
11053                 I915_WRITE_FW(CURSIZE, size);
11054                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11055                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
11056
11057                 plane->cursor.base = base;
11058                 plane->cursor.size = size;
11059                 plane->cursor.cntl = cntl;
11060         } else {
11061                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11062         }
11063
11064         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11065 }
11066
11067 static void i845_disable_cursor(struct intel_plane *plane,
11068                                 const struct intel_crtc_state *crtc_state)
11069 {
11070         i845_update_cursor(plane, crtc_state, NULL);
11071 }
11072
11073 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11074                                      enum pipe *pipe)
11075 {
11076         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11077         enum intel_display_power_domain power_domain;
11078         intel_wakeref_t wakeref;
11079         bool ret;
11080
11081         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11082         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11083         if (!wakeref)
11084                 return false;
11085
11086         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11087
11088         *pipe = PIPE_A;
11089
11090         intel_display_power_put(dev_priv, power_domain, wakeref);
11091
11092         return ret;
11093 }
11094
11095 static unsigned int
11096 i9xx_cursor_max_stride(struct intel_plane *plane,
11097                        u32 pixel_format, u64 modifier,
11098                        unsigned int rotation)
11099 {
11100         return plane->base.dev->mode_config.cursor_width * 4;
11101 }
11102
11103 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11104 {
11105         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11106         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11107         u32 cntl = 0;
11108
11109         if (INTEL_GEN(dev_priv) >= 11)
11110                 return cntl;
11111
11112         if (crtc_state->gamma_enable)
11113                 cntl = MCURSOR_GAMMA_ENABLE;
11114
11115         if (crtc_state->csc_enable)
11116                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11117
11118         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11119                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11120
11121         return cntl;
11122 }
11123
11124 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11125                            const struct intel_plane_state *plane_state)
11126 {
11127         struct drm_i915_private *dev_priv =
11128                 to_i915(plane_state->uapi.plane->dev);
11129         u32 cntl = 0;
11130
11131         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11132                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11133
11134         switch (drm_rect_width(&plane_state->uapi.dst)) {
11135         case 64:
11136                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11137                 break;
11138         case 128:
11139                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11140                 break;
11141         case 256:
11142                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11143                 break;
11144         default:
11145                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11146                 return 0;
11147         }
11148
11149         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11150                 cntl |= MCURSOR_ROTATE_180;
11151
11152         return cntl;
11153 }
11154
11155 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11156 {
11157         struct drm_i915_private *dev_priv =
11158                 to_i915(plane_state->uapi.plane->dev);
11159         int width = drm_rect_width(&plane_state->uapi.dst);
11160         int height = drm_rect_height(&plane_state->uapi.dst);
11161
11162         if (!intel_cursor_size_ok(plane_state))
11163                 return false;
11164
11165         /* Cursor width is limited to a few power-of-two sizes */
11166         switch (width) {
11167         case 256:
11168         case 128:
11169         case 64:
11170                 break;
11171         default:
11172                 return false;
11173         }
11174
11175         /*
11176          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11177          * height from 8 lines up to the cursor width, when the
11178          * cursor is not rotated. Everything else requires square
11179          * cursors.
11180          */
11181         if (HAS_CUR_FBC(dev_priv) &&
11182             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11183                 if (height < 8 || height > width)
11184                         return false;
11185         } else {
11186                 if (height != width)
11187                         return false;
11188         }
11189
11190         return true;
11191 }
11192
11193 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11194                              struct intel_plane_state *plane_state)
11195 {
11196         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11197         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11198         const struct drm_framebuffer *fb = plane_state->hw.fb;
11199         enum pipe pipe = plane->pipe;
11200         int ret;
11201
11202         ret = intel_check_cursor(crtc_state, plane_state);
11203         if (ret)
11204                 return ret;
11205
11206         /* if we want to turn off the cursor ignore width and height */
11207         if (!fb)
11208                 return 0;
11209
11210         /* Check for which cursor types we support */
11211         if (!i9xx_cursor_size_ok(plane_state)) {
11212                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11213                           drm_rect_width(&plane_state->uapi.dst),
11214                           drm_rect_height(&plane_state->uapi.dst));
11215                 return -EINVAL;
11216         }
11217
11218         WARN_ON(plane_state->uapi.visible &&
11219                 plane_state->color_plane[0].stride != fb->pitches[0]);
11220
11221         if (fb->pitches[0] !=
11222             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11223                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
11224                               fb->pitches[0],
11225                               drm_rect_width(&plane_state->uapi.dst));
11226                 return -EINVAL;
11227         }
11228
11229         /*
11230          * There's something wrong with the cursor on CHV pipe C.
11231          * If it straddles the left edge of the screen then
11232          * moving it away from the edge or disabling it often
11233          * results in a pipe underrun, and often that can lead to
11234          * dead pipe (constant underrun reported, and it scans
11235          * out just a solid color). To recover from that, the
11236          * display power well must be turned off and on again.
11237          * Refuse the put the cursor into that compromised position.
11238          */
11239         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11240             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11241                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11242                 return -EINVAL;
11243         }
11244
11245         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11246
11247         return 0;
11248 }
11249
11250 static void i9xx_update_cursor(struct intel_plane *plane,
11251                                const struct intel_crtc_state *crtc_state,
11252                                const struct intel_plane_state *plane_state)
11253 {
11254         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11255         enum pipe pipe = plane->pipe;
11256         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11257         unsigned long irqflags;
11258
11259         if (plane_state && plane_state->uapi.visible) {
11260                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11261                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11262
11263                 cntl = plane_state->ctl |
11264                         i9xx_cursor_ctl_crtc(crtc_state);
11265
11266                 if (width != height)
11267                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11268
11269                 base = intel_cursor_base(plane_state);
11270                 pos = intel_cursor_position(plane_state);
11271         }
11272
11273         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11274
11275         /*
11276          * On some platforms writing CURCNTR first will also
11277          * cause CURPOS to be armed by the CURBASE write.
11278          * Without the CURCNTR write the CURPOS write would
11279          * arm itself. Thus we always update CURCNTR before
11280          * CURPOS.
11281          *
11282          * On other platforms CURPOS always requires the
11283          * CURBASE write to arm the update. Additonally
11284          * a write to any of the cursor register will cancel
11285          * an already armed cursor update. Thus leaving out
11286          * the CURBASE write after CURPOS could lead to a
11287          * cursor that doesn't appear to move, or even change
11288          * shape. Thus we always write CURBASE.
11289          *
11290          * The other registers are armed by by the CURBASE write
11291          * except when the plane is getting enabled at which time
11292          * the CURCNTR write arms the update.
11293          */
11294
11295         if (INTEL_GEN(dev_priv) >= 9)
11296                 skl_write_cursor_wm(plane, crtc_state);
11297
11298         if (plane->cursor.base != base ||
11299             plane->cursor.size != fbc_ctl ||
11300             plane->cursor.cntl != cntl) {
11301                 if (HAS_CUR_FBC(dev_priv))
11302                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
11303                 I915_WRITE_FW(CURCNTR(pipe), cntl);
11304                 I915_WRITE_FW(CURPOS(pipe), pos);
11305                 I915_WRITE_FW(CURBASE(pipe), base);
11306
11307                 plane->cursor.base = base;
11308                 plane->cursor.size = fbc_ctl;
11309                 plane->cursor.cntl = cntl;
11310         } else {
11311                 I915_WRITE_FW(CURPOS(pipe), pos);
11312                 I915_WRITE_FW(CURBASE(pipe), base);
11313         }
11314
11315         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11316 }
11317
11318 static void i9xx_disable_cursor(struct intel_plane *plane,
11319                                 const struct intel_crtc_state *crtc_state)
11320 {
11321         i9xx_update_cursor(plane, crtc_state, NULL);
11322 }
11323
11324 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11325                                      enum pipe *pipe)
11326 {
11327         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11328         enum intel_display_power_domain power_domain;
11329         intel_wakeref_t wakeref;
11330         bool ret;
11331         u32 val;
11332
11333         /*
11334          * Not 100% correct for planes that can move between pipes,
11335          * but that's only the case for gen2-3 which don't have any
11336          * display power wells.
11337          */
11338         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11339         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11340         if (!wakeref)
11341                 return false;
11342
11343         val = I915_READ(CURCNTR(plane->pipe));
11344
11345         ret = val & MCURSOR_MODE;
11346
11347         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11348                 *pipe = plane->pipe;
11349         else
11350                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11351                         MCURSOR_PIPE_SELECT_SHIFT;
11352
11353         intel_display_power_put(dev_priv, power_domain, wakeref);
11354
11355         return ret;
11356 }
11357
11358 /* VESA 640x480x72Hz mode to set on the pipe */
11359 static const struct drm_display_mode load_detect_mode = {
11360         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11361                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11362 };
11363
11364 struct drm_framebuffer *
11365 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11366                          struct drm_mode_fb_cmd2 *mode_cmd)
11367 {
11368         struct intel_framebuffer *intel_fb;
11369         int ret;
11370
11371         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11372         if (!intel_fb)
11373                 return ERR_PTR(-ENOMEM);
11374
11375         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11376         if (ret)
11377                 goto err;
11378
11379         return &intel_fb->base;
11380
11381 err:
11382         kfree(intel_fb);
11383         return ERR_PTR(ret);
11384 }
11385
11386 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11387                                         struct drm_crtc *crtc)
11388 {
11389         struct drm_plane *plane;
11390         struct drm_plane_state *plane_state;
11391         int ret, i;
11392
11393         ret = drm_atomic_add_affected_planes(state, crtc);
11394         if (ret)
11395                 return ret;
11396
11397         for_each_new_plane_in_state(state, plane, plane_state, i) {
11398                 if (plane_state->crtc != crtc)
11399                         continue;
11400
11401                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11402                 if (ret)
11403                         return ret;
11404
11405                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11406         }
11407
11408         return 0;
11409 }
11410
11411 int intel_get_load_detect_pipe(struct drm_connector *connector,
11412                                struct intel_load_detect_pipe *old,
11413                                struct drm_modeset_acquire_ctx *ctx)
11414 {
11415         struct intel_crtc *intel_crtc;
11416         struct intel_encoder *intel_encoder =
11417                 intel_attached_encoder(connector);
11418         struct drm_crtc *possible_crtc;
11419         struct drm_encoder *encoder = &intel_encoder->base;
11420         struct drm_crtc *crtc = NULL;
11421         struct drm_device *dev = encoder->dev;
11422         struct drm_i915_private *dev_priv = to_i915(dev);
11423         struct drm_mode_config *config = &dev->mode_config;
11424         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11425         struct drm_connector_state *connector_state;
11426         struct intel_crtc_state *crtc_state;
11427         int ret, i = -1;
11428
11429         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11430                       connector->base.id, connector->name,
11431                       encoder->base.id, encoder->name);
11432
11433         old->restore_state = NULL;
11434
11435         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11436
11437         /*
11438          * Algorithm gets a little messy:
11439          *
11440          *   - if the connector already has an assigned crtc, use it (but make
11441          *     sure it's on first)
11442          *
11443          *   - try to find the first unused crtc that can drive this connector,
11444          *     and use that if we find one
11445          */
11446
11447         /* See if we already have a CRTC for this connector */
11448         if (connector->state->crtc) {
11449                 crtc = connector->state->crtc;
11450
11451                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11452                 if (ret)
11453                         goto fail;
11454
11455                 /* Make sure the crtc and connector are running */
11456                 goto found;
11457         }
11458
11459         /* Find an unused one (if possible) */
11460         for_each_crtc(dev, possible_crtc) {
11461                 i++;
11462                 if (!(encoder->possible_crtcs & (1 << i)))
11463                         continue;
11464
11465                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11466                 if (ret)
11467                         goto fail;
11468
11469                 if (possible_crtc->state->enable) {
11470                         drm_modeset_unlock(&possible_crtc->mutex);
11471                         continue;
11472                 }
11473
11474                 crtc = possible_crtc;
11475                 break;
11476         }
11477
11478         /*
11479          * If we didn't find an unused CRTC, don't use any.
11480          */
11481         if (!crtc) {
11482                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11483                 ret = -ENODEV;
11484                 goto fail;
11485         }
11486
11487 found:
11488         intel_crtc = to_intel_crtc(crtc);
11489
11490         state = drm_atomic_state_alloc(dev);
11491         restore_state = drm_atomic_state_alloc(dev);
11492         if (!state || !restore_state) {
11493                 ret = -ENOMEM;
11494                 goto fail;
11495         }
11496
11497         state->acquire_ctx = ctx;
11498         restore_state->acquire_ctx = ctx;
11499
11500         connector_state = drm_atomic_get_connector_state(state, connector);
11501         if (IS_ERR(connector_state)) {
11502                 ret = PTR_ERR(connector_state);
11503                 goto fail;
11504         }
11505
11506         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11507         if (ret)
11508                 goto fail;
11509
11510         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11511         if (IS_ERR(crtc_state)) {
11512                 ret = PTR_ERR(crtc_state);
11513                 goto fail;
11514         }
11515
11516         crtc_state->uapi.active = true;
11517
11518         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11519                                            &load_detect_mode);
11520         if (ret)
11521                 goto fail;
11522
11523         ret = intel_modeset_disable_planes(state, crtc);
11524         if (ret)
11525                 goto fail;
11526
11527         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11528         if (!ret)
11529                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11530         if (!ret)
11531                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11532         if (ret) {
11533                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11534                 goto fail;
11535         }
11536
11537         ret = drm_atomic_commit(state);
11538         if (ret) {
11539                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11540                 goto fail;
11541         }
11542
11543         old->restore_state = restore_state;
11544         drm_atomic_state_put(state);
11545
11546         /* let the connector get through one full cycle before testing */
11547         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11548         return true;
11549
11550 fail:
11551         if (state) {
11552                 drm_atomic_state_put(state);
11553                 state = NULL;
11554         }
11555         if (restore_state) {
11556                 drm_atomic_state_put(restore_state);
11557                 restore_state = NULL;
11558         }
11559
11560         if (ret == -EDEADLK)
11561                 return ret;
11562
11563         return false;
11564 }
11565
11566 void intel_release_load_detect_pipe(struct drm_connector *connector,
11567                                     struct intel_load_detect_pipe *old,
11568                                     struct drm_modeset_acquire_ctx *ctx)
11569 {
11570         struct intel_encoder *intel_encoder =
11571                 intel_attached_encoder(connector);
11572         struct drm_encoder *encoder = &intel_encoder->base;
11573         struct drm_atomic_state *state = old->restore_state;
11574         int ret;
11575
11576         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11577                       connector->base.id, connector->name,
11578                       encoder->base.id, encoder->name);
11579
11580         if (!state)
11581                 return;
11582
11583         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11584         if (ret)
11585                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11586         drm_atomic_state_put(state);
11587 }
11588
11589 static int i9xx_pll_refclk(struct drm_device *dev,
11590                            const struct intel_crtc_state *pipe_config)
11591 {
11592         struct drm_i915_private *dev_priv = to_i915(dev);
11593         u32 dpll = pipe_config->dpll_hw_state.dpll;
11594
11595         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11596                 return dev_priv->vbt.lvds_ssc_freq;
11597         else if (HAS_PCH_SPLIT(dev_priv))
11598                 return 120000;
11599         else if (!IS_GEN(dev_priv, 2))
11600                 return 96000;
11601         else
11602                 return 48000;
11603 }
11604
11605 /* Returns the clock of the currently programmed mode of the given pipe. */
11606 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11607                                 struct intel_crtc_state *pipe_config)
11608 {
11609         struct drm_device *dev = crtc->base.dev;
11610         struct drm_i915_private *dev_priv = to_i915(dev);
11611         enum pipe pipe = crtc->pipe;
11612         u32 dpll = pipe_config->dpll_hw_state.dpll;
11613         u32 fp;
11614         struct dpll clock;
11615         int port_clock;
11616         int refclk = i9xx_pll_refclk(dev, pipe_config);
11617
11618         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11619                 fp = pipe_config->dpll_hw_state.fp0;
11620         else
11621                 fp = pipe_config->dpll_hw_state.fp1;
11622
11623         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11624         if (IS_PINEVIEW(dev_priv)) {
11625                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11626                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11627         } else {
11628                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11629                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11630         }
11631
11632         if (!IS_GEN(dev_priv, 2)) {
11633                 if (IS_PINEVIEW(dev_priv))
11634                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11635                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11636                 else
11637                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11638                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11639
11640                 switch (dpll & DPLL_MODE_MASK) {
11641                 case DPLLB_MODE_DAC_SERIAL:
11642                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11643                                 5 : 10;
11644                         break;
11645                 case DPLLB_MODE_LVDS:
11646                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11647                                 7 : 14;
11648                         break;
11649                 default:
11650                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11651                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11652                         return;
11653                 }
11654
11655                 if (IS_PINEVIEW(dev_priv))
11656                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11657                 else
11658                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11659         } else {
11660                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11661                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11662
11663                 if (is_lvds) {
11664                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11665                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11666
11667                         if (lvds & LVDS_CLKB_POWER_UP)
11668                                 clock.p2 = 7;
11669                         else
11670                                 clock.p2 = 14;
11671                 } else {
11672                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11673                                 clock.p1 = 2;
11674                         else {
11675                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11676                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11677                         }
11678                         if (dpll & PLL_P2_DIVIDE_BY_4)
11679                                 clock.p2 = 4;
11680                         else
11681                                 clock.p2 = 2;
11682                 }
11683
11684                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11685         }
11686
11687         /*
11688          * This value includes pixel_multiplier. We will use
11689          * port_clock to compute adjusted_mode.crtc_clock in the
11690          * encoder's get_config() function.
11691          */
11692         pipe_config->port_clock = port_clock;
11693 }
11694
11695 int intel_dotclock_calculate(int link_freq,
11696                              const struct intel_link_m_n *m_n)
11697 {
11698         /*
11699          * The calculation for the data clock is:
11700          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11701          * But we want to avoid losing precison if possible, so:
11702          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11703          *
11704          * and the link clock is simpler:
11705          * link_clock = (m * link_clock) / n
11706          */
11707
11708         if (!m_n->link_n)
11709                 return 0;
11710
11711         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11712 }
11713
11714 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11715                                    struct intel_crtc_state *pipe_config)
11716 {
11717         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11718
11719         /* read out port_clock from the DPLL */
11720         i9xx_crtc_clock_get(crtc, pipe_config);
11721
11722         /*
11723          * In case there is an active pipe without active ports,
11724          * we may need some idea for the dotclock anyway.
11725          * Calculate one based on the FDI configuration.
11726          */
11727         pipe_config->hw.adjusted_mode.crtc_clock =
11728                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11729                                          &pipe_config->fdi_m_n);
11730 }
11731
11732 /* Returns the currently programmed mode of the given encoder. */
11733 struct drm_display_mode *
11734 intel_encoder_current_mode(struct intel_encoder *encoder)
11735 {
11736         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11737         struct intel_crtc_state *crtc_state;
11738         struct drm_display_mode *mode;
11739         struct intel_crtc *crtc;
11740         enum pipe pipe;
11741
11742         if (!encoder->get_hw_state(encoder, &pipe))
11743                 return NULL;
11744
11745         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11746
11747         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11748         if (!mode)
11749                 return NULL;
11750
11751         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11752         if (!crtc_state) {
11753                 kfree(mode);
11754                 return NULL;
11755         }
11756
11757         crtc_state->uapi.crtc = &crtc->base;
11758
11759         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11760                 kfree(crtc_state);
11761                 kfree(mode);
11762                 return NULL;
11763         }
11764
11765         encoder->get_config(encoder, crtc_state);
11766
11767         intel_mode_from_pipe_config(mode, crtc_state);
11768
11769         kfree(crtc_state);
11770
11771         return mode;
11772 }
11773
11774 static void intel_crtc_destroy(struct drm_crtc *crtc)
11775 {
11776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11777
11778         drm_crtc_cleanup(crtc);
11779         kfree(intel_crtc);
11780 }
11781
11782 /**
11783  * intel_wm_need_update - Check whether watermarks need updating
11784  * @cur: current plane state
11785  * @new: new plane state
11786  *
11787  * Check current plane state versus the new one to determine whether
11788  * watermarks need to be recalculated.
11789  *
11790  * Returns true or false.
11791  */
11792 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11793                                  struct intel_plane_state *new)
11794 {
11795         /* Update watermarks on tiling or size changes. */
11796         if (new->uapi.visible != cur->uapi.visible)
11797                 return true;
11798
11799         if (!cur->hw.fb || !new->hw.fb)
11800                 return false;
11801
11802         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
11803             cur->hw.rotation != new->hw.rotation ||
11804             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
11805             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
11806             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
11807             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
11808                 return true;
11809
11810         return false;
11811 }
11812
11813 static bool needs_scaling(const struct intel_plane_state *state)
11814 {
11815         int src_w = drm_rect_width(&state->uapi.src) >> 16;
11816         int src_h = drm_rect_height(&state->uapi.src) >> 16;
11817         int dst_w = drm_rect_width(&state->uapi.dst);
11818         int dst_h = drm_rect_height(&state->uapi.dst);
11819
11820         return (src_w != dst_w || src_h != dst_h);
11821 }
11822
11823 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11824                                     struct intel_crtc_state *crtc_state,
11825                                     const struct intel_plane_state *old_plane_state,
11826                                     struct intel_plane_state *plane_state)
11827 {
11828         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11829         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11830         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11831         bool mode_changed = needs_modeset(crtc_state);
11832         bool was_crtc_enabled = old_crtc_state->hw.active;
11833         bool is_crtc_enabled = crtc_state->hw.active;
11834         bool turn_off, turn_on, visible, was_visible;
11835         int ret;
11836
11837         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11838                 ret = skl_update_scaler_plane(crtc_state, plane_state);
11839                 if (ret)
11840                         return ret;
11841         }
11842
11843         was_visible = old_plane_state->uapi.visible;
11844         visible = plane_state->uapi.visible;
11845
11846         if (!was_crtc_enabled && WARN_ON(was_visible))
11847                 was_visible = false;
11848
11849         /*
11850          * Visibility is calculated as if the crtc was on, but
11851          * after scaler setup everything depends on it being off
11852          * when the crtc isn't active.
11853          *
11854          * FIXME this is wrong for watermarks. Watermarks should also
11855          * be computed as if the pipe would be active. Perhaps move
11856          * per-plane wm computation to the .check_plane() hook, and
11857          * only combine the results from all planes in the current place?
11858          */
11859         if (!is_crtc_enabled) {
11860                 plane_state->uapi.visible = visible = false;
11861                 crtc_state->active_planes &= ~BIT(plane->id);
11862                 crtc_state->data_rate[plane->id] = 0;
11863                 crtc_state->min_cdclk[plane->id] = 0;
11864         }
11865
11866         if (!was_visible && !visible)
11867                 return 0;
11868
11869         turn_off = was_visible && (!visible || mode_changed);
11870         turn_on = visible && (!was_visible || mode_changed);
11871
11872         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11873                          crtc->base.base.id, crtc->base.name,
11874                          plane->base.base.id, plane->base.name,
11875                          was_visible, visible,
11876                          turn_off, turn_on, mode_changed);
11877
11878         if (turn_on) {
11879                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11880                         crtc_state->update_wm_pre = true;
11881
11882                 /* must disable cxsr around plane enable/disable */
11883                 if (plane->id != PLANE_CURSOR)
11884                         crtc_state->disable_cxsr = true;
11885         } else if (turn_off) {
11886                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11887                         crtc_state->update_wm_post = true;
11888
11889                 /* must disable cxsr around plane enable/disable */
11890                 if (plane->id != PLANE_CURSOR)
11891                         crtc_state->disable_cxsr = true;
11892         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11893                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11894                         /* FIXME bollocks */
11895                         crtc_state->update_wm_pre = true;
11896                         crtc_state->update_wm_post = true;
11897                 }
11898         }
11899
11900         if (visible || was_visible)
11901                 crtc_state->fb_bits |= plane->frontbuffer_bit;
11902
11903         /*
11904          * ILK/SNB DVSACNTR/Sprite Enable
11905          * IVB SPR_CTL/Sprite Enable
11906          * "When in Self Refresh Big FIFO mode, a write to enable the
11907          *  plane will be internally buffered and delayed while Big FIFO
11908          *  mode is exiting."
11909          *
11910          * Which means that enabling the sprite can take an extra frame
11911          * when we start in big FIFO mode (LP1+). Thus we need to drop
11912          * down to LP0 and wait for vblank in order to make sure the
11913          * sprite gets enabled on the next vblank after the register write.
11914          * Doing otherwise would risk enabling the sprite one frame after
11915          * we've already signalled flip completion. We can resume LP1+
11916          * once the sprite has been enabled.
11917          *
11918          *
11919          * WaCxSRDisabledForSpriteScaling:ivb
11920          * IVB SPR_SCALE/Scaling Enable
11921          * "Low Power watermarks must be disabled for at least one
11922          *  frame before enabling sprite scaling, and kept disabled
11923          *  until sprite scaling is disabled."
11924          *
11925          * ILK/SNB DVSASCALE/Scaling Enable
11926          * "When in Self Refresh Big FIFO mode, scaling enable will be
11927          *  masked off while Big FIFO mode is exiting."
11928          *
11929          * Despite the w/a only being listed for IVB we assume that
11930          * the ILK/SNB note has similar ramifications, hence we apply
11931          * the w/a on all three platforms.
11932          *
11933          * With experimental results seems this is needed also for primary
11934          * plane, not only sprite plane.
11935          */
11936         if (plane->id != PLANE_CURSOR &&
11937             (IS_GEN_RANGE(dev_priv, 5, 6) ||
11938              IS_IVYBRIDGE(dev_priv)) &&
11939             (turn_on || (!needs_scaling(old_plane_state) &&
11940                          needs_scaling(plane_state))))
11941                 crtc_state->disable_lp_wm = true;
11942
11943         return 0;
11944 }
11945
11946 static bool encoders_cloneable(const struct intel_encoder *a,
11947                                const struct intel_encoder *b)
11948 {
11949         /* masks could be asymmetric, so check both ways */
11950         return a == b || (a->cloneable & (1 << b->type) &&
11951                           b->cloneable & (1 << a->type));
11952 }
11953
11954 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11955                                          struct intel_crtc *crtc,
11956                                          struct intel_encoder *encoder)
11957 {
11958         struct intel_encoder *source_encoder;
11959         struct drm_connector *connector;
11960         struct drm_connector_state *connector_state;
11961         int i;
11962
11963         for_each_new_connector_in_state(state, connector, connector_state, i) {
11964                 if (connector_state->crtc != &crtc->base)
11965                         continue;
11966
11967                 source_encoder =
11968                         to_intel_encoder(connector_state->best_encoder);
11969                 if (!encoders_cloneable(encoder, source_encoder))
11970                         return false;
11971         }
11972
11973         return true;
11974 }
11975
11976 static int icl_add_linked_planes(struct intel_atomic_state *state)
11977 {
11978         struct intel_plane *plane, *linked;
11979         struct intel_plane_state *plane_state, *linked_plane_state;
11980         int i;
11981
11982         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11983                 linked = plane_state->planar_linked_plane;
11984
11985                 if (!linked)
11986                         continue;
11987
11988                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11989                 if (IS_ERR(linked_plane_state))
11990                         return PTR_ERR(linked_plane_state);
11991
11992                 WARN_ON(linked_plane_state->planar_linked_plane != plane);
11993                 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
11994         }
11995
11996         return 0;
11997 }
11998
11999 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12000 {
12001         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12002         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12003         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12004         struct intel_plane *plane, *linked;
12005         struct intel_plane_state *plane_state;
12006         int i;
12007
12008         if (INTEL_GEN(dev_priv) < 11)
12009                 return 0;
12010
12011         /*
12012          * Destroy all old plane links and make the slave plane invisible
12013          * in the crtc_state->active_planes mask.
12014          */
12015         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12016                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12017                         continue;
12018
12019                 plane_state->planar_linked_plane = NULL;
12020                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12021                         crtc_state->active_planes &= ~BIT(plane->id);
12022                         crtc_state->update_planes |= BIT(plane->id);
12023                 }
12024
12025                 plane_state->planar_slave = false;
12026         }
12027
12028         if (!crtc_state->nv12_planes)
12029                 return 0;
12030
12031         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12032                 struct intel_plane_state *linked_state = NULL;
12033
12034                 if (plane->pipe != crtc->pipe ||
12035                     !(crtc_state->nv12_planes & BIT(plane->id)))
12036                         continue;
12037
12038                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12039                         if (!icl_is_nv12_y_plane(linked->id))
12040                                 continue;
12041
12042                         if (crtc_state->active_planes & BIT(linked->id))
12043                                 continue;
12044
12045                         linked_state = intel_atomic_get_plane_state(state, linked);
12046                         if (IS_ERR(linked_state))
12047                                 return PTR_ERR(linked_state);
12048
12049                         break;
12050                 }
12051
12052                 if (!linked_state) {
12053                         DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
12054                                       hweight8(crtc_state->nv12_planes));
12055
12056                         return -EINVAL;
12057                 }
12058
12059                 plane_state->planar_linked_plane = linked;
12060
12061                 linked_state->planar_slave = true;
12062                 linked_state->planar_linked_plane = plane;
12063                 crtc_state->active_planes |= BIT(linked->id);
12064                 crtc_state->update_planes |= BIT(linked->id);
12065                 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
12066
12067                 /* Copy parameters to slave plane */
12068                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12069                 linked_state->color_ctl = plane_state->color_ctl;
12070                 linked_state->color_plane[0] = plane_state->color_plane[0];
12071
12072                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12073                 linked_state->uapi.src = plane_state->uapi.src;
12074                 linked_state->uapi.dst = plane_state->uapi.dst;
12075
12076                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12077                         if (linked->id == PLANE_SPRITE5)
12078                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12079                         else if (linked->id == PLANE_SPRITE4)
12080                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12081                         else
12082                                 MISSING_CASE(linked->id);
12083                 }
12084         }
12085
12086         return 0;
12087 }
12088
12089 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12090 {
12091         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12092         struct intel_atomic_state *state =
12093                 to_intel_atomic_state(new_crtc_state->uapi.state);
12094         const struct intel_crtc_state *old_crtc_state =
12095                 intel_atomic_get_old_crtc_state(state, crtc);
12096
12097         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12098 }
12099
12100 static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
12101 {
12102         struct drm_crtc *crtc = crtc_state->uapi.crtc;
12103         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12104         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12105         struct drm_connector *master_connector, *connector;
12106         struct drm_connector_state *connector_state;
12107         struct drm_connector_list_iter conn_iter;
12108         struct drm_crtc *master_crtc = NULL;
12109         struct drm_crtc_state *master_crtc_state;
12110         struct intel_crtc_state *master_pipe_config;
12111         int i, tile_group_id;
12112
12113         if (INTEL_GEN(dev_priv) < 11)
12114                 return 0;
12115
12116         /*
12117          * In case of tiled displays there could be one or more slaves but there is
12118          * only one master. Lets make the CRTC used by the connector corresponding
12119          * to the last horizonal and last vertical tile a master/genlock CRTC.
12120          * All the other CRTCs corresponding to other tiles of the same Tile group
12121          * are the slave CRTCs and hold a pointer to their genlock CRTC.
12122          */
12123         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
12124                 if (connector_state->crtc != crtc)
12125                         continue;
12126                 if (!connector->has_tile)
12127                         continue;
12128                 if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
12129                     crtc_state->hw.mode.vdisplay != connector->tile_v_size)
12130                         return 0;
12131                 if (connector->tile_h_loc == connector->num_h_tile - 1 &&
12132                     connector->tile_v_loc == connector->num_v_tile - 1)
12133                         continue;
12134                 crtc_state->sync_mode_slaves_mask = 0;
12135                 tile_group_id = connector->tile_group->id;
12136                 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
12137                 drm_for_each_connector_iter(master_connector, &conn_iter) {
12138                         struct drm_connector_state *master_conn_state = NULL;
12139
12140                         if (!master_connector->has_tile)
12141                                 continue;
12142                         if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
12143                             master_connector->tile_v_loc != master_connector->num_v_tile - 1)
12144                                 continue;
12145                         if (master_connector->tile_group->id != tile_group_id)
12146                                 continue;
12147
12148                         master_conn_state = drm_atomic_get_connector_state(&state->base,
12149                                                                            master_connector);
12150                         if (IS_ERR(master_conn_state)) {
12151                                 drm_connector_list_iter_end(&conn_iter);
12152                                 return PTR_ERR(master_conn_state);
12153                         }
12154                         if (master_conn_state->crtc) {
12155                                 master_crtc = master_conn_state->crtc;
12156                                 break;
12157                         }
12158                 }
12159                 drm_connector_list_iter_end(&conn_iter);
12160
12161                 if (!master_crtc) {
12162                         DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
12163                                       connector_state->crtc->base.id);
12164                         return -EINVAL;
12165                 }
12166
12167                 master_crtc_state = drm_atomic_get_crtc_state(&state->base,
12168                                                               master_crtc);
12169                 if (IS_ERR(master_crtc_state))
12170                         return PTR_ERR(master_crtc_state);
12171
12172                 master_pipe_config = to_intel_crtc_state(master_crtc_state);
12173                 crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
12174                 master_pipe_config->sync_mode_slaves_mask |=
12175                         BIT(crtc_state->cpu_transcoder);
12176                 DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
12177                               transcoder_name(crtc_state->master_transcoder),
12178                               crtc_state->uapi.crtc->base.id,
12179                               master_pipe_config->sync_mode_slaves_mask);
12180         }
12181
12182         return 0;
12183 }
12184
12185 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12186                                    struct intel_crtc *crtc)
12187 {
12188         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12189         struct intel_crtc_state *crtc_state =
12190                 intel_atomic_get_new_crtc_state(state, crtc);
12191         bool mode_changed = needs_modeset(crtc_state);
12192         int ret;
12193
12194         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12195             mode_changed && !crtc_state->hw.active)
12196                 crtc_state->update_wm_post = true;
12197
12198         if (mode_changed && crtc_state->hw.enable &&
12199             dev_priv->display.crtc_compute_clock &&
12200             !WARN_ON(crtc_state->shared_dpll)) {
12201                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12202                 if (ret)
12203                         return ret;
12204         }
12205
12206         /*
12207          * May need to update pipe gamma enable bits
12208          * when C8 planes are getting enabled/disabled.
12209          */
12210         if (c8_planes_changed(crtc_state))
12211                 crtc_state->uapi.color_mgmt_changed = true;
12212
12213         if (mode_changed || crtc_state->update_pipe ||
12214             crtc_state->uapi.color_mgmt_changed) {
12215                 ret = intel_color_check(crtc_state);
12216                 if (ret)
12217                         return ret;
12218         }
12219
12220         ret = 0;
12221         if (dev_priv->display.compute_pipe_wm) {
12222                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12223                 if (ret) {
12224                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12225                         return ret;
12226                 }
12227         }
12228
12229         if (dev_priv->display.compute_intermediate_wm) {
12230                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12231                         return 0;
12232
12233                 /*
12234                  * Calculate 'intermediate' watermarks that satisfy both the
12235                  * old state and the new state.  We can program these
12236                  * immediately.
12237                  */
12238                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12239                 if (ret) {
12240                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12241                         return ret;
12242                 }
12243         }
12244
12245         if (INTEL_GEN(dev_priv) >= 9) {
12246                 if (mode_changed || crtc_state->update_pipe)
12247                         ret = skl_update_scaler_crtc(crtc_state);
12248                 if (!ret)
12249                         ret = intel_atomic_setup_scalers(dev_priv, crtc,
12250                                                          crtc_state);
12251         }
12252
12253         if (HAS_IPS(dev_priv))
12254                 crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
12255
12256         return ret;
12257 }
12258
12259 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12260 {
12261         struct intel_connector *connector;
12262         struct drm_connector_list_iter conn_iter;
12263
12264         drm_connector_list_iter_begin(dev, &conn_iter);
12265         for_each_intel_connector_iter(connector, &conn_iter) {
12266                 if (connector->base.state->crtc)
12267                         drm_connector_put(&connector->base);
12268
12269                 if (connector->base.encoder) {
12270                         connector->base.state->best_encoder =
12271                                 connector->base.encoder;
12272                         connector->base.state->crtc =
12273                                 connector->base.encoder->crtc;
12274
12275                         drm_connector_get(&connector->base);
12276                 } else {
12277                         connector->base.state->best_encoder = NULL;
12278                         connector->base.state->crtc = NULL;
12279                 }
12280         }
12281         drm_connector_list_iter_end(&conn_iter);
12282 }
12283
12284 static int
12285 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12286                       struct intel_crtc_state *pipe_config)
12287 {
12288         struct drm_connector *connector = conn_state->connector;
12289         const struct drm_display_info *info = &connector->display_info;
12290         int bpp;
12291
12292         switch (conn_state->max_bpc) {
12293         case 6 ... 7:
12294                 bpp = 6 * 3;
12295                 break;
12296         case 8 ... 9:
12297                 bpp = 8 * 3;
12298                 break;
12299         case 10 ... 11:
12300                 bpp = 10 * 3;
12301                 break;
12302         case 12:
12303                 bpp = 12 * 3;
12304                 break;
12305         default:
12306                 return -EINVAL;
12307         }
12308
12309         if (bpp < pipe_config->pipe_bpp) {
12310                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12311                               "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12312                               connector->base.id, connector->name,
12313                               bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
12314                               pipe_config->pipe_bpp);
12315
12316                 pipe_config->pipe_bpp = bpp;
12317         }
12318
12319         return 0;
12320 }
12321
12322 static int
12323 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12324                           struct intel_crtc_state *pipe_config)
12325 {
12326         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12327         struct drm_atomic_state *state = pipe_config->uapi.state;
12328         struct drm_connector *connector;
12329         struct drm_connector_state *connector_state;
12330         int bpp, i;
12331
12332         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12333             IS_CHERRYVIEW(dev_priv)))
12334                 bpp = 10*3;
12335         else if (INTEL_GEN(dev_priv) >= 5)
12336                 bpp = 12*3;
12337         else
12338                 bpp = 8*3;
12339
12340         pipe_config->pipe_bpp = bpp;
12341
12342         /* Clamp display bpp to connector max bpp */
12343         for_each_new_connector_in_state(state, connector, connector_state, i) {
12344                 int ret;
12345
12346                 if (connector_state->crtc != &crtc->base)
12347                         continue;
12348
12349                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12350                 if (ret)
12351                         return ret;
12352         }
12353
12354         return 0;
12355 }
12356
12357 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12358 {
12359         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12360                       "type: 0x%x flags: 0x%x\n",
12361                       mode->crtc_clock,
12362                       mode->crtc_hdisplay, mode->crtc_hsync_start,
12363                       mode->crtc_hsync_end, mode->crtc_htotal,
12364                       mode->crtc_vdisplay, mode->crtc_vsync_start,
12365                       mode->crtc_vsync_end, mode->crtc_vtotal,
12366                       mode->type, mode->flags);
12367 }
12368
12369 static inline void
12370 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12371                       const char *id, unsigned int lane_count,
12372                       const struct intel_link_m_n *m_n)
12373 {
12374         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12375                       id, lane_count,
12376                       m_n->gmch_m, m_n->gmch_n,
12377                       m_n->link_m, m_n->link_n, m_n->tu);
12378 }
12379
12380 static void
12381 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12382                      const union hdmi_infoframe *frame)
12383 {
12384         if ((drm_debug & DRM_UT_KMS) == 0)
12385                 return;
12386
12387         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12388 }
12389
12390 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12391
12392 static const char * const output_type_str[] = {
12393         OUTPUT_TYPE(UNUSED),
12394         OUTPUT_TYPE(ANALOG),
12395         OUTPUT_TYPE(DVO),
12396         OUTPUT_TYPE(SDVO),
12397         OUTPUT_TYPE(LVDS),
12398         OUTPUT_TYPE(TVOUT),
12399         OUTPUT_TYPE(HDMI),
12400         OUTPUT_TYPE(DP),
12401         OUTPUT_TYPE(EDP),
12402         OUTPUT_TYPE(DSI),
12403         OUTPUT_TYPE(DDI),
12404         OUTPUT_TYPE(DP_MST),
12405 };
12406
12407 #undef OUTPUT_TYPE
12408
12409 static void snprintf_output_types(char *buf, size_t len,
12410                                   unsigned int output_types)
12411 {
12412         char *str = buf;
12413         int i;
12414
12415         str[0] = '\0';
12416
12417         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12418                 int r;
12419
12420                 if ((output_types & BIT(i)) == 0)
12421                         continue;
12422
12423                 r = snprintf(str, len, "%s%s",
12424                              str != buf ? "," : "", output_type_str[i]);
12425                 if (r >= len)
12426                         break;
12427                 str += r;
12428                 len -= r;
12429
12430                 output_types &= ~BIT(i);
12431         }
12432
12433         WARN_ON_ONCE(output_types != 0);
12434 }
12435
12436 static const char * const output_format_str[] = {
12437         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12438         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12439         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12440         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12441 };
12442
12443 static const char *output_formats(enum intel_output_format format)
12444 {
12445         if (format >= ARRAY_SIZE(output_format_str))
12446                 format = INTEL_OUTPUT_FORMAT_INVALID;
12447         return output_format_str[format];
12448 }
12449
12450 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12451 {
12452         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12453         const struct drm_framebuffer *fb = plane_state->hw.fb;
12454         struct drm_format_name_buf format_name;
12455
12456         if (!fb) {
12457                 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12458                               plane->base.base.id, plane->base.name,
12459                               yesno(plane_state->uapi.visible));
12460                 return;
12461         }
12462
12463         DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12464                       plane->base.base.id, plane->base.name,
12465                       fb->base.id, fb->width, fb->height,
12466                       drm_get_format_name(fb->format->format, &format_name),
12467                       yesno(plane_state->uapi.visible));
12468         DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12469                       plane_state->hw.rotation, plane_state->scaler_id);
12470         if (plane_state->uapi.visible)
12471                 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12472                               DRM_RECT_FP_ARG(&plane_state->uapi.src),
12473                               DRM_RECT_ARG(&plane_state->uapi.dst));
12474 }
12475
12476 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12477                                    struct intel_atomic_state *state,
12478                                    const char *context)
12479 {
12480         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12481         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12482         const struct intel_plane_state *plane_state;
12483         struct intel_plane *plane;
12484         char buf[64];
12485         int i;
12486
12487         DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12488                       crtc->base.base.id, crtc->base.name,
12489                       yesno(pipe_config->hw.enable), context);
12490
12491         if (!pipe_config->hw.enable)
12492                 goto dump_planes;
12493
12494         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12495         DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12496                       yesno(pipe_config->hw.active),
12497                       buf, pipe_config->output_types,
12498                       output_formats(pipe_config->output_format));
12499
12500         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12501                       transcoder_name(pipe_config->cpu_transcoder),
12502                       pipe_config->pipe_bpp, pipe_config->dither);
12503
12504         if (pipe_config->has_pch_encoder)
12505                 intel_dump_m_n_config(pipe_config, "fdi",
12506                                       pipe_config->fdi_lanes,
12507                                       &pipe_config->fdi_m_n);
12508
12509         if (intel_crtc_has_dp_encoder(pipe_config)) {
12510                 intel_dump_m_n_config(pipe_config, "dp m_n",
12511                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12512                 if (pipe_config->has_drrs)
12513                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12514                                               pipe_config->lane_count,
12515                                               &pipe_config->dp_m2_n2);
12516         }
12517
12518         DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12519                       pipe_config->has_audio, pipe_config->has_infoframe,
12520                       pipe_config->infoframes.enable);
12521
12522         if (pipe_config->infoframes.enable &
12523             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12524                 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12525         if (pipe_config->infoframes.enable &
12526             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12527                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12528         if (pipe_config->infoframes.enable &
12529             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12530                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12531         if (pipe_config->infoframes.enable &
12532             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12533                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12534
12535         DRM_DEBUG_KMS("requested mode:\n");
12536         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
12537         DRM_DEBUG_KMS("adjusted mode:\n");
12538         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
12539         intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
12540         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12541                       pipe_config->port_clock,
12542                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12543                       pipe_config->pixel_rate);
12544
12545         if (INTEL_GEN(dev_priv) >= 9)
12546                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12547                               crtc->num_scalers,
12548                               pipe_config->scaler_state.scaler_users,
12549                               pipe_config->scaler_state.scaler_id);
12550
12551         if (HAS_GMCH(dev_priv))
12552                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12553                               pipe_config->gmch_pfit.control,
12554                               pipe_config->gmch_pfit.pgm_ratios,
12555                               pipe_config->gmch_pfit.lvds_border_bits);
12556         else
12557                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12558                               pipe_config->pch_pfit.pos,
12559                               pipe_config->pch_pfit.size,
12560                               enableddisabled(pipe_config->pch_pfit.enabled),
12561                               yesno(pipe_config->pch_pfit.force_thru));
12562
12563         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12564                       pipe_config->ips_enabled, pipe_config->double_wide);
12565
12566         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12567
12568         if (IS_CHERRYVIEW(dev_priv))
12569                 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12570                               pipe_config->cgm_mode, pipe_config->gamma_mode,
12571                               pipe_config->gamma_enable, pipe_config->csc_enable);
12572         else
12573                 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12574                               pipe_config->csc_mode, pipe_config->gamma_mode,
12575                               pipe_config->gamma_enable, pipe_config->csc_enable);
12576
12577 dump_planes:
12578         if (!state)
12579                 return;
12580
12581         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12582                 if (plane->pipe == crtc->pipe)
12583                         intel_dump_plane_state(plane_state);
12584         }
12585 }
12586
12587 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12588 {
12589         struct drm_device *dev = state->base.dev;
12590         struct drm_connector *connector;
12591         struct drm_connector_list_iter conn_iter;
12592         unsigned int used_ports = 0;
12593         unsigned int used_mst_ports = 0;
12594         bool ret = true;
12595
12596         /*
12597          * We're going to peek into connector->state,
12598          * hence connection_mutex must be held.
12599          */
12600         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
12601
12602         /*
12603          * Walk the connector list instead of the encoder
12604          * list to detect the problem on ddi platforms
12605          * where there's just one encoder per digital port.
12606          */
12607         drm_connector_list_iter_begin(dev, &conn_iter);
12608         drm_for_each_connector_iter(connector, &conn_iter) {
12609                 struct drm_connector_state *connector_state;
12610                 struct intel_encoder *encoder;
12611
12612                 connector_state =
12613                         drm_atomic_get_new_connector_state(&state->base,
12614                                                            connector);
12615                 if (!connector_state)
12616                         connector_state = connector->state;
12617
12618                 if (!connector_state->best_encoder)
12619                         continue;
12620
12621                 encoder = to_intel_encoder(connector_state->best_encoder);
12622
12623                 WARN_ON(!connector_state->crtc);
12624
12625                 switch (encoder->type) {
12626                         unsigned int port_mask;
12627                 case INTEL_OUTPUT_DDI:
12628                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12629                                 break;
12630                         /* else, fall through */
12631                 case INTEL_OUTPUT_DP:
12632                 case INTEL_OUTPUT_HDMI:
12633                 case INTEL_OUTPUT_EDP:
12634                         port_mask = 1 << encoder->port;
12635
12636                         /* the same port mustn't appear more than once */
12637                         if (used_ports & port_mask)
12638                                 ret = false;
12639
12640                         used_ports |= port_mask;
12641                         break;
12642                 case INTEL_OUTPUT_DP_MST:
12643                         used_mst_ports |=
12644                                 1 << encoder->port;
12645                         break;
12646                 default:
12647                         break;
12648                 }
12649         }
12650         drm_connector_list_iter_end(&conn_iter);
12651
12652         /* can't mix MST and SST/HDMI on the same port */
12653         if (used_ports & used_mst_ports)
12654                 return false;
12655
12656         return ret;
12657 }
12658
12659 static void
12660 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
12661 {
12662         intel_crtc_copy_color_blobs(crtc_state);
12663 }
12664
12665 static void
12666 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
12667 {
12668         crtc_state->hw.enable = crtc_state->uapi.enable;
12669         crtc_state->hw.active = crtc_state->uapi.active;
12670         crtc_state->hw.mode = crtc_state->uapi.mode;
12671         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
12672         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
12673 }
12674
12675 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
12676 {
12677         crtc_state->uapi.enable = crtc_state->hw.enable;
12678         crtc_state->uapi.active = crtc_state->hw.active;
12679         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
12680
12681         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
12682
12683         /* copy color blobs to uapi */
12684         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
12685                                   crtc_state->hw.degamma_lut);
12686         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
12687                                   crtc_state->hw.gamma_lut);
12688         drm_property_replace_blob(&crtc_state->uapi.ctm,
12689                                   crtc_state->hw.ctm);
12690 }
12691
12692 static int
12693 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
12694 {
12695         struct drm_i915_private *dev_priv =
12696                 to_i915(crtc_state->uapi.crtc->dev);
12697         struct intel_crtc_state *saved_state;
12698
12699         saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12700         if (!saved_state)
12701                 return -ENOMEM;
12702
12703         /* free the old crtc_state->hw members */
12704         intel_crtc_free_hw_state(crtc_state);
12705
12706         /* FIXME: before the switch to atomic started, a new pipe_config was
12707          * kzalloc'd. Code that depends on any field being zero should be
12708          * fixed, so that the crtc_state can be safely duplicated. For now,
12709          * only fields that are know to not cause problems are preserved. */
12710
12711         saved_state->uapi = crtc_state->uapi;
12712         saved_state->scaler_state = crtc_state->scaler_state;
12713         saved_state->shared_dpll = crtc_state->shared_dpll;
12714         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12715         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12716                sizeof(saved_state->icl_port_dplls));
12717         saved_state->crc_enabled = crtc_state->crc_enabled;
12718         if (IS_G4X(dev_priv) ||
12719             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12720                 saved_state->wm = crtc_state->wm;
12721         /*
12722          * Save the slave bitmask which gets filled for master crtc state during
12723          * slave atomic check call.
12724          */
12725         if (is_trans_port_sync_master(crtc_state))
12726                 saved_state->sync_mode_slaves_mask =
12727                         crtc_state->sync_mode_slaves_mask;
12728
12729         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
12730         kfree(saved_state);
12731
12732         intel_crtc_copy_uapi_to_hw_state(crtc_state);
12733
12734         return 0;
12735 }
12736
12737 static int
12738 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12739 {
12740         struct drm_crtc *crtc = pipe_config->uapi.crtc;
12741         struct drm_atomic_state *state = pipe_config->uapi.state;
12742         struct intel_encoder *encoder;
12743         struct drm_connector *connector;
12744         struct drm_connector_state *connector_state;
12745         int base_bpp, ret;
12746         int i;
12747         bool retry = true;
12748
12749         pipe_config->cpu_transcoder =
12750                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12751
12752         /*
12753          * Sanitize sync polarity flags based on requested ones. If neither
12754          * positive or negative polarity is requested, treat this as meaning
12755          * negative polarity.
12756          */
12757         if (!(pipe_config->hw.adjusted_mode.flags &
12758               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12759                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12760
12761         if (!(pipe_config->hw.adjusted_mode.flags &
12762               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12763                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12764
12765         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12766                                         pipe_config);
12767         if (ret)
12768                 return ret;
12769
12770         base_bpp = pipe_config->pipe_bpp;
12771
12772         /*
12773          * Determine the real pipe dimensions. Note that stereo modes can
12774          * increase the actual pipe size due to the frame doubling and
12775          * insertion of additional space for blanks between the frame. This
12776          * is stored in the crtc timings. We use the requested mode to do this
12777          * computation to clearly distinguish it from the adjusted mode, which
12778          * can be changed by the connectors in the below retry loop.
12779          */
12780         drm_mode_get_hv_timing(&pipe_config->hw.mode,
12781                                &pipe_config->pipe_src_w,
12782                                &pipe_config->pipe_src_h);
12783
12784         for_each_new_connector_in_state(state, connector, connector_state, i) {
12785                 if (connector_state->crtc != crtc)
12786                         continue;
12787
12788                 encoder = to_intel_encoder(connector_state->best_encoder);
12789
12790                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12791                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12792                         return -EINVAL;
12793                 }
12794
12795                 /*
12796                  * Determine output_types before calling the .compute_config()
12797                  * hooks so that the hooks can use this information safely.
12798                  */
12799                 if (encoder->compute_output_type)
12800                         pipe_config->output_types |=
12801                                 BIT(encoder->compute_output_type(encoder, pipe_config,
12802                                                                  connector_state));
12803                 else
12804                         pipe_config->output_types |= BIT(encoder->type);
12805         }
12806
12807 encoder_retry:
12808         /* Ensure the port clock defaults are reset when retrying. */
12809         pipe_config->port_clock = 0;
12810         pipe_config->pixel_multiplier = 1;
12811
12812         /* Fill in default crtc timings, allow encoders to overwrite them. */
12813         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
12814                               CRTC_STEREO_DOUBLE);
12815
12816         /* Set the crtc_state defaults for trans_port_sync */
12817         pipe_config->master_transcoder = INVALID_TRANSCODER;
12818         ret = icl_add_sync_mode_crtcs(pipe_config);
12819         if (ret) {
12820                 DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
12821                               ret);
12822                 return ret;
12823         }
12824
12825         /* Pass our mode to the connectors and the CRTC to give them a chance to
12826          * adjust it according to limitations or connector properties, and also
12827          * a chance to reject the mode entirely.
12828          */
12829         for_each_new_connector_in_state(state, connector, connector_state, i) {
12830                 if (connector_state->crtc != crtc)
12831                         continue;
12832
12833                 encoder = to_intel_encoder(connector_state->best_encoder);
12834                 ret = encoder->compute_config(encoder, pipe_config,
12835                                               connector_state);
12836                 if (ret < 0) {
12837                         if (ret != -EDEADLK)
12838                                 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12839                                               ret);
12840                         return ret;
12841                 }
12842         }
12843
12844         /* Set default port clock if not overwritten by the encoder. Needs to be
12845          * done afterwards in case the encoder adjusts the mode. */
12846         if (!pipe_config->port_clock)
12847                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
12848                         * pipe_config->pixel_multiplier;
12849
12850         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12851         if (ret == -EDEADLK)
12852                 return ret;
12853         if (ret < 0) {
12854                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12855                 return ret;
12856         }
12857
12858         if (ret == RETRY) {
12859                 if (WARN(!retry, "loop in pipe configuration computation\n"))
12860                         return -EINVAL;
12861
12862                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12863                 retry = false;
12864                 goto encoder_retry;
12865         }
12866
12867         /* Dithering seems to not pass-through bits correctly when it should, so
12868          * only enable it on 6bpc panels and when its not a compliance
12869          * test requesting 6bpc video pattern.
12870          */
12871         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12872                 !pipe_config->dither_force_disable;
12873         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12874                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12875
12876         /*
12877          * Make drm_calc_timestamping_constants in
12878          * drm_atomic_helper_update_legacy_modeset_state() happy
12879          */
12880         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
12881
12882         return 0;
12883 }
12884
12885 bool intel_fuzzy_clock_check(int clock1, int clock2)
12886 {
12887         int diff;
12888
12889         if (clock1 == clock2)
12890                 return true;
12891
12892         if (!clock1 || !clock2)
12893                 return false;
12894
12895         diff = abs(clock1 - clock2);
12896
12897         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12898                 return true;
12899
12900         return false;
12901 }
12902
12903 static bool
12904 intel_compare_m_n(unsigned int m, unsigned int n,
12905                   unsigned int m2, unsigned int n2,
12906                   bool exact)
12907 {
12908         if (m == m2 && n == n2)
12909                 return true;
12910
12911         if (exact || !m || !n || !m2 || !n2)
12912                 return false;
12913
12914         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12915
12916         if (n > n2) {
12917                 while (n > n2) {
12918                         m2 <<= 1;
12919                         n2 <<= 1;
12920                 }
12921         } else if (n < n2) {
12922                 while (n < n2) {
12923                         m <<= 1;
12924                         n <<= 1;
12925                 }
12926         }
12927
12928         if (n != n2)
12929                 return false;
12930
12931         return intel_fuzzy_clock_check(m, m2);
12932 }
12933
12934 static bool
12935 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12936                        const struct intel_link_m_n *m2_n2,
12937                        bool exact)
12938 {
12939         return m_n->tu == m2_n2->tu &&
12940                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12941                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12942                 intel_compare_m_n(m_n->link_m, m_n->link_n,
12943                                   m2_n2->link_m, m2_n2->link_n, exact);
12944 }
12945
12946 static bool
12947 intel_compare_infoframe(const union hdmi_infoframe *a,
12948                         const union hdmi_infoframe *b)
12949 {
12950         return memcmp(a, b, sizeof(*a)) == 0;
12951 }
12952
12953 static void
12954 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12955                                bool fastset, const char *name,
12956                                const union hdmi_infoframe *a,
12957                                const union hdmi_infoframe *b)
12958 {
12959         if (fastset) {
12960                 if ((drm_debug & DRM_UT_KMS) == 0)
12961                         return;
12962
12963                 DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name);
12964                 DRM_DEBUG_KMS("expected:\n");
12965                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12966                 DRM_DEBUG_KMS("found:\n");
12967                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12968         } else {
12969                 DRM_ERROR("mismatch in %s infoframe\n", name);
12970                 DRM_ERROR("expected:\n");
12971                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12972                 DRM_ERROR("found:\n");
12973                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12974         }
12975 }
12976
12977 static void __printf(4, 5)
12978 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
12979                      const char *name, const char *format, ...)
12980 {
12981         struct va_format vaf;
12982         va_list args;
12983
12984         va_start(args, format);
12985         vaf.fmt = format;
12986         vaf.va = &args;
12987
12988         if (fastset)
12989                 DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
12990                               crtc->base.base.id, crtc->base.name, name, &vaf);
12991         else
12992                 DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
12993                           crtc->base.base.id, crtc->base.name, name, &vaf);
12994
12995         va_end(args);
12996 }
12997
12998 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12999 {
13000         if (i915_modparams.fastboot != -1)
13001                 return i915_modparams.fastboot;
13002
13003         /* Enable fastboot by default on Skylake and newer */
13004         if (INTEL_GEN(dev_priv) >= 9)
13005                 return true;
13006
13007         /* Enable fastboot by default on VLV and CHV */
13008         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13009                 return true;
13010
13011         /* Disabled by default on all others */
13012         return false;
13013 }
13014
13015 static bool
13016 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13017                           const struct intel_crtc_state *pipe_config,
13018                           bool fastset)
13019 {
13020         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13021         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13022         bool ret = true;
13023         u32 bp_gamma = 0;
13024         bool fixup_inherited = fastset &&
13025                 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
13026                 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
13027
13028         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13029                 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
13030                 ret = false;
13031         }
13032
13033 #define PIPE_CONF_CHECK_X(name) do { \
13034         if (current_config->name != pipe_config->name) { \
13035                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13036                                      "(expected 0x%08x, found 0x%08x)", \
13037                                      current_config->name, \
13038                                      pipe_config->name); \
13039                 ret = false; \
13040         } \
13041 } while (0)
13042
13043 #define PIPE_CONF_CHECK_I(name) do { \
13044         if (current_config->name != pipe_config->name) { \
13045                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13046                                      "(expected %i, found %i)", \
13047                                      current_config->name, \
13048                                      pipe_config->name); \
13049                 ret = false; \
13050         } \
13051 } while (0)
13052
13053 #define PIPE_CONF_CHECK_BOOL(name) do { \
13054         if (current_config->name != pipe_config->name) { \
13055                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13056                                      "(expected %s, found %s)", \
13057                                      yesno(current_config->name), \
13058                                      yesno(pipe_config->name)); \
13059                 ret = false; \
13060         } \
13061 } while (0)
13062
13063 /*
13064  * Checks state where we only read out the enabling, but not the entire
13065  * state itself (like full infoframes or ELD for audio). These states
13066  * require a full modeset on bootup to fix up.
13067  */
13068 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13069         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13070                 PIPE_CONF_CHECK_BOOL(name); \
13071         } else { \
13072                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13073                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13074                                      yesno(current_config->name), \
13075                                      yesno(pipe_config->name)); \
13076                 ret = false; \
13077         } \
13078 } while (0)
13079
13080 #define PIPE_CONF_CHECK_P(name) do { \
13081         if (current_config->name != pipe_config->name) { \
13082                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13083                                      "(expected %p, found %p)", \
13084                                      current_config->name, \
13085                                      pipe_config->name); \
13086                 ret = false; \
13087         } \
13088 } while (0)
13089
13090 #define PIPE_CONF_CHECK_M_N(name) do { \
13091         if (!intel_compare_link_m_n(&current_config->name, \
13092                                     &pipe_config->name,\
13093                                     !fastset)) { \
13094                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13095                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13096                                      "found tu %i, gmch %i/%i link %i/%i)", \
13097                                      current_config->name.tu, \
13098                                      current_config->name.gmch_m, \
13099                                      current_config->name.gmch_n, \
13100                                      current_config->name.link_m, \
13101                                      current_config->name.link_n, \
13102                                      pipe_config->name.tu, \
13103                                      pipe_config->name.gmch_m, \
13104                                      pipe_config->name.gmch_n, \
13105                                      pipe_config->name.link_m, \
13106                                      pipe_config->name.link_n); \
13107                 ret = false; \
13108         } \
13109 } while (0)
13110
13111 /* This is required for BDW+ where there is only one set of registers for
13112  * switching between high and low RR.
13113  * This macro can be used whenever a comparison has to be made between one
13114  * hw state and multiple sw state variables.
13115  */
13116 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13117         if (!intel_compare_link_m_n(&current_config->name, \
13118                                     &pipe_config->name, !fastset) && \
13119             !intel_compare_link_m_n(&current_config->alt_name, \
13120                                     &pipe_config->name, !fastset)) { \
13121                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13122                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13123                                      "or tu %i gmch %i/%i link %i/%i, " \
13124                                      "found tu %i, gmch %i/%i link %i/%i)", \
13125                                      current_config->name.tu, \
13126                                      current_config->name.gmch_m, \
13127                                      current_config->name.gmch_n, \
13128                                      current_config->name.link_m, \
13129                                      current_config->name.link_n, \
13130                                      current_config->alt_name.tu, \
13131                                      current_config->alt_name.gmch_m, \
13132                                      current_config->alt_name.gmch_n, \
13133                                      current_config->alt_name.link_m, \
13134                                      current_config->alt_name.link_n, \
13135                                      pipe_config->name.tu, \
13136                                      pipe_config->name.gmch_m, \
13137                                      pipe_config->name.gmch_n, \
13138                                      pipe_config->name.link_m, \
13139                                      pipe_config->name.link_n); \
13140                 ret = false; \
13141         } \
13142 } while (0)
13143
13144 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13145         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13146                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13147                                      "(%x) (expected %i, found %i)", \
13148                                      (mask), \
13149                                      current_config->name & (mask), \
13150                                      pipe_config->name & (mask)); \
13151                 ret = false; \
13152         } \
13153 } while (0)
13154
13155 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13156         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13157                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13158                                      "(expected %i, found %i)", \
13159                                      current_config->name, \
13160                                      pipe_config->name); \
13161                 ret = false; \
13162         } \
13163 } while (0)
13164
13165 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13166         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13167                                      &pipe_config->infoframes.name)) { \
13168                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13169                                                &current_config->infoframes.name, \
13170                                                &pipe_config->infoframes.name); \
13171                 ret = false; \
13172         } \
13173 } while (0)
13174
13175 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13176         if (current_config->name1 != pipe_config->name1) { \
13177                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13178                                 "(expected %i, found %i, won't compare lut values)", \
13179                                 current_config->name1, \
13180                                 pipe_config->name1); \
13181                 ret = false;\
13182         } else { \
13183                 if (!intel_color_lut_equal(current_config->name2, \
13184                                         pipe_config->name2, pipe_config->name1, \
13185                                         bit_precision)) { \
13186                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13187                                         "hw_state doesn't match sw_state"); \
13188                         ret = false; \
13189                 } \
13190         } \
13191 } while (0)
13192
13193 #define PIPE_CONF_QUIRK(quirk) \
13194         ((current_config->quirks | pipe_config->quirks) & (quirk))
13195
13196         PIPE_CONF_CHECK_I(cpu_transcoder);
13197
13198         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13199         PIPE_CONF_CHECK_I(fdi_lanes);
13200         PIPE_CONF_CHECK_M_N(fdi_m_n);
13201
13202         PIPE_CONF_CHECK_I(lane_count);
13203         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13204
13205         if (INTEL_GEN(dev_priv) < 8) {
13206                 PIPE_CONF_CHECK_M_N(dp_m_n);
13207
13208                 if (current_config->has_drrs)
13209                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13210         } else
13211                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13212
13213         PIPE_CONF_CHECK_X(output_types);
13214
13215         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13216         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13217         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13218         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13219         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13220         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13221
13222         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13223         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13224         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13225         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13226         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13227         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13228
13229         PIPE_CONF_CHECK_I(pixel_multiplier);
13230         PIPE_CONF_CHECK_I(output_format);
13231         PIPE_CONF_CHECK_I(dc3co_exitline);
13232         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13233         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13234             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13235                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13236
13237         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13238         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13239         PIPE_CONF_CHECK_BOOL(has_infoframe);
13240         PIPE_CONF_CHECK_BOOL(fec_enable);
13241
13242         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13243
13244         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13245                               DRM_MODE_FLAG_INTERLACE);
13246
13247         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13248                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13249                                       DRM_MODE_FLAG_PHSYNC);
13250                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13251                                       DRM_MODE_FLAG_NHSYNC);
13252                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13253                                       DRM_MODE_FLAG_PVSYNC);
13254                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13255                                       DRM_MODE_FLAG_NVSYNC);
13256         }
13257
13258         PIPE_CONF_CHECK_X(gmch_pfit.control);
13259         /* pfit ratios are autocomputed by the hw on gen4+ */
13260         if (INTEL_GEN(dev_priv) < 4)
13261                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13262         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13263
13264         /*
13265          * Changing the EDP transcoder input mux
13266          * (A_ONOFF vs. A_ON) requires a full modeset.
13267          */
13268         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13269
13270         if (!fastset) {
13271                 PIPE_CONF_CHECK_I(pipe_src_w);
13272                 PIPE_CONF_CHECK_I(pipe_src_h);
13273
13274                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13275                 if (current_config->pch_pfit.enabled) {
13276                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13277                         PIPE_CONF_CHECK_X(pch_pfit.size);
13278                 }
13279
13280                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13281                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13282
13283                 PIPE_CONF_CHECK_X(gamma_mode);
13284                 if (IS_CHERRYVIEW(dev_priv))
13285                         PIPE_CONF_CHECK_X(cgm_mode);
13286                 else
13287                         PIPE_CONF_CHECK_X(csc_mode);
13288                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13289                 PIPE_CONF_CHECK_BOOL(csc_enable);
13290
13291                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13292                 if (bp_gamma)
13293                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13294
13295         }
13296
13297         PIPE_CONF_CHECK_BOOL(double_wide);
13298
13299         PIPE_CONF_CHECK_P(shared_dpll);
13300         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13301         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13302         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13303         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13304         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13305         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13306         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13307         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13308         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13309         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13310         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13311         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13312         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13313         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13314         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13315         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13316         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13317         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13318         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13319         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13320         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13321         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13322         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13323         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13324         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13325         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13326         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13327         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13328         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13329         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13330         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13331
13332         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13333         PIPE_CONF_CHECK_X(dsi_pll.div);
13334
13335         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13336                 PIPE_CONF_CHECK_I(pipe_bpp);
13337
13338         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13339         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13340
13341         PIPE_CONF_CHECK_I(min_voltage_level);
13342
13343         PIPE_CONF_CHECK_X(infoframes.enable);
13344         PIPE_CONF_CHECK_X(infoframes.gcp);
13345         PIPE_CONF_CHECK_INFOFRAME(avi);
13346         PIPE_CONF_CHECK_INFOFRAME(spd);
13347         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13348         PIPE_CONF_CHECK_INFOFRAME(drm);
13349
13350         PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
13351         PIPE_CONF_CHECK_I(master_transcoder);
13352
13353 #undef PIPE_CONF_CHECK_X
13354 #undef PIPE_CONF_CHECK_I
13355 #undef PIPE_CONF_CHECK_BOOL
13356 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13357 #undef PIPE_CONF_CHECK_P
13358 #undef PIPE_CONF_CHECK_FLAGS
13359 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13360 #undef PIPE_CONF_CHECK_COLOR_LUT
13361 #undef PIPE_CONF_QUIRK
13362
13363         return ret;
13364 }
13365
13366 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13367                                            const struct intel_crtc_state *pipe_config)
13368 {
13369         if (pipe_config->has_pch_encoder) {
13370                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13371                                                             &pipe_config->fdi_m_n);
13372                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13373
13374                 /*
13375                  * FDI already provided one idea for the dotclock.
13376                  * Yell if the encoder disagrees.
13377                  */
13378                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13379                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13380                      fdi_dotclock, dotclock);
13381         }
13382 }
13383
13384 static void verify_wm_state(struct intel_crtc *crtc,
13385                             struct intel_crtc_state *new_crtc_state)
13386 {
13387         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13388         struct skl_hw_state {
13389                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13390                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13391                 struct skl_ddb_allocation ddb;
13392                 struct skl_pipe_wm wm;
13393         } *hw;
13394         struct skl_ddb_allocation *sw_ddb;
13395         struct skl_pipe_wm *sw_wm;
13396         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13397         const enum pipe pipe = crtc->pipe;
13398         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13399
13400         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13401                 return;
13402
13403         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13404         if (!hw)
13405                 return;
13406
13407         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13408         sw_wm = &new_crtc_state->wm.skl.optimal;
13409
13410         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13411
13412         skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13413         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13414
13415         if (INTEL_GEN(dev_priv) >= 11 &&
13416             hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13417                 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
13418                           sw_ddb->enabled_slices,
13419                           hw->ddb.enabled_slices);
13420
13421         /* planes */
13422         for_each_universal_plane(dev_priv, pipe, plane) {
13423                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13424
13425                 hw_plane_wm = &hw->wm.planes[plane];
13426                 sw_plane_wm = &sw_wm->planes[plane];
13427
13428                 /* Watermarks */
13429                 for (level = 0; level <= max_level; level++) {
13430                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13431                                                 &sw_plane_wm->wm[level]))
13432                                 continue;
13433
13434                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13435                                   pipe_name(pipe), plane + 1, level,
13436                                   sw_plane_wm->wm[level].plane_en,
13437                                   sw_plane_wm->wm[level].plane_res_b,
13438                                   sw_plane_wm->wm[level].plane_res_l,
13439                                   hw_plane_wm->wm[level].plane_en,
13440                                   hw_plane_wm->wm[level].plane_res_b,
13441                                   hw_plane_wm->wm[level].plane_res_l);
13442                 }
13443
13444                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13445                                          &sw_plane_wm->trans_wm)) {
13446                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13447                                   pipe_name(pipe), plane + 1,
13448                                   sw_plane_wm->trans_wm.plane_en,
13449                                   sw_plane_wm->trans_wm.plane_res_b,
13450                                   sw_plane_wm->trans_wm.plane_res_l,
13451                                   hw_plane_wm->trans_wm.plane_en,
13452                                   hw_plane_wm->trans_wm.plane_res_b,
13453                                   hw_plane_wm->trans_wm.plane_res_l);
13454                 }
13455
13456                 /* DDB */
13457                 hw_ddb_entry = &hw->ddb_y[plane];
13458                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13459
13460                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13461                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13462                                   pipe_name(pipe), plane + 1,
13463                                   sw_ddb_entry->start, sw_ddb_entry->end,
13464                                   hw_ddb_entry->start, hw_ddb_entry->end);
13465                 }
13466         }
13467
13468         /*
13469          * cursor
13470          * If the cursor plane isn't active, we may not have updated it's ddb
13471          * allocation. In that case since the ddb allocation will be updated
13472          * once the plane becomes visible, we can skip this check
13473          */
13474         if (1) {
13475                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13476
13477                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13478                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13479
13480                 /* Watermarks */
13481                 for (level = 0; level <= max_level; level++) {
13482                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13483                                                 &sw_plane_wm->wm[level]))
13484                                 continue;
13485
13486                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13487                                   pipe_name(pipe), level,
13488                                   sw_plane_wm->wm[level].plane_en,
13489                                   sw_plane_wm->wm[level].plane_res_b,
13490                                   sw_plane_wm->wm[level].plane_res_l,
13491                                   hw_plane_wm->wm[level].plane_en,
13492                                   hw_plane_wm->wm[level].plane_res_b,
13493                                   hw_plane_wm->wm[level].plane_res_l);
13494                 }
13495
13496                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13497                                          &sw_plane_wm->trans_wm)) {
13498                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13499                                   pipe_name(pipe),
13500                                   sw_plane_wm->trans_wm.plane_en,
13501                                   sw_plane_wm->trans_wm.plane_res_b,
13502                                   sw_plane_wm->trans_wm.plane_res_l,
13503                                   hw_plane_wm->trans_wm.plane_en,
13504                                   hw_plane_wm->trans_wm.plane_res_b,
13505                                   hw_plane_wm->trans_wm.plane_res_l);
13506                 }
13507
13508                 /* DDB */
13509                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13510                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13511
13512                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13513                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13514                                   pipe_name(pipe),
13515                                   sw_ddb_entry->start, sw_ddb_entry->end,
13516                                   hw_ddb_entry->start, hw_ddb_entry->end);
13517                 }
13518         }
13519
13520         kfree(hw);
13521 }
13522
13523 static void
13524 verify_connector_state(struct intel_atomic_state *state,
13525                        struct intel_crtc *crtc)
13526 {
13527         struct drm_connector *connector;
13528         struct drm_connector_state *new_conn_state;
13529         int i;
13530
13531         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13532                 struct drm_encoder *encoder = connector->encoder;
13533                 struct intel_crtc_state *crtc_state = NULL;
13534
13535                 if (new_conn_state->crtc != &crtc->base)
13536                         continue;
13537
13538                 if (crtc)
13539                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13540
13541                 intel_connector_verify_state(crtc_state, new_conn_state);
13542
13543                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13544                      "connector's atomic encoder doesn't match legacy encoder\n");
13545         }
13546 }
13547
13548 static void
13549 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13550 {
13551         struct intel_encoder *encoder;
13552         struct drm_connector *connector;
13553         struct drm_connector_state *old_conn_state, *new_conn_state;
13554         int i;
13555
13556         for_each_intel_encoder(&dev_priv->drm, encoder) {
13557                 bool enabled = false, found = false;
13558                 enum pipe pipe;
13559
13560                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13561                               encoder->base.base.id,
13562                               encoder->base.name);
13563
13564                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13565                                                    new_conn_state, i) {
13566                         if (old_conn_state->best_encoder == &encoder->base)
13567                                 found = true;
13568
13569                         if (new_conn_state->best_encoder != &encoder->base)
13570                                 continue;
13571                         found = enabled = true;
13572
13573                         I915_STATE_WARN(new_conn_state->crtc !=
13574                                         encoder->base.crtc,
13575                              "connector's crtc doesn't match encoder crtc\n");
13576                 }
13577
13578                 if (!found)
13579                         continue;
13580
13581                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13582                      "encoder's enabled state mismatch "
13583                      "(expected %i, found %i)\n",
13584                      !!encoder->base.crtc, enabled);
13585
13586                 if (!encoder->base.crtc) {
13587                         bool active;
13588
13589                         active = encoder->get_hw_state(encoder, &pipe);
13590                         I915_STATE_WARN(active,
13591                              "encoder detached but still enabled on pipe %c.\n",
13592                              pipe_name(pipe));
13593                 }
13594         }
13595 }
13596
13597 static void
13598 verify_crtc_state(struct intel_crtc *crtc,
13599                   struct intel_crtc_state *old_crtc_state,
13600                   struct intel_crtc_state *new_crtc_state)
13601 {
13602         struct drm_device *dev = crtc->base.dev;
13603         struct drm_i915_private *dev_priv = to_i915(dev);
13604         struct intel_encoder *encoder;
13605         struct intel_crtc_state *pipe_config;
13606         struct drm_atomic_state *state;
13607         bool active;
13608
13609         state = old_crtc_state->uapi.state;
13610         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
13611         intel_crtc_free_hw_state(old_crtc_state);
13612
13613         pipe_config = old_crtc_state;
13614         memset(pipe_config, 0, sizeof(*pipe_config));
13615         pipe_config->uapi.crtc = &crtc->base;
13616         pipe_config->uapi.state = state;
13617
13618         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13619
13620         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13621
13622         /* we keep both pipes enabled on 830 */
13623         if (IS_I830(dev_priv))
13624                 active = new_crtc_state->hw.active;
13625
13626         I915_STATE_WARN(new_crtc_state->hw.active != active,
13627                         "crtc active state doesn't match with hw state "
13628                         "(expected %i, found %i)\n",
13629                         new_crtc_state->hw.active, active);
13630
13631         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
13632                         "transitional active state does not match atomic hw state "
13633                         "(expected %i, found %i)\n",
13634                         new_crtc_state->hw.active, crtc->active);
13635
13636         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13637                 enum pipe pipe;
13638
13639                 active = encoder->get_hw_state(encoder, &pipe);
13640                 I915_STATE_WARN(active != new_crtc_state->hw.active,
13641                                 "[ENCODER:%i] active %i with crtc active %i\n",
13642                                 encoder->base.base.id, active,
13643                                 new_crtc_state->hw.active);
13644
13645                 I915_STATE_WARN(active && crtc->pipe != pipe,
13646                                 "Encoder connected to wrong pipe %c\n",
13647                                 pipe_name(pipe));
13648
13649                 if (active)
13650                         encoder->get_config(encoder, pipe_config);
13651         }
13652
13653         intel_crtc_compute_pixel_rate(pipe_config);
13654
13655         if (!new_crtc_state->hw.active)
13656                 return;
13657
13658         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13659
13660         if (!intel_pipe_config_compare(new_crtc_state,
13661                                        pipe_config, false)) {
13662                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13663                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13664                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13665         }
13666 }
13667
13668 static void
13669 intel_verify_planes(struct intel_atomic_state *state)
13670 {
13671         struct intel_plane *plane;
13672         const struct intel_plane_state *plane_state;
13673         int i;
13674
13675         for_each_new_intel_plane_in_state(state, plane,
13676                                           plane_state, i)
13677                 assert_plane(plane, plane_state->planar_slave ||
13678                              plane_state->uapi.visible);
13679 }
13680
13681 static void
13682 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13683                          struct intel_shared_dpll *pll,
13684                          struct intel_crtc *crtc,
13685                          struct intel_crtc_state *new_crtc_state)
13686 {
13687         struct intel_dpll_hw_state dpll_hw_state;
13688         unsigned int crtc_mask;
13689         bool active;
13690
13691         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13692
13693         DRM_DEBUG_KMS("%s\n", pll->info->name);
13694
13695         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13696
13697         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13698                 I915_STATE_WARN(!pll->on && pll->active_mask,
13699                      "pll in active use but not on in sw tracking\n");
13700                 I915_STATE_WARN(pll->on && !pll->active_mask,
13701                      "pll is on but not used by any active crtc\n");
13702                 I915_STATE_WARN(pll->on != active,
13703                      "pll on state mismatch (expected %i, found %i)\n",
13704                      pll->on, active);
13705         }
13706
13707         if (!crtc) {
13708                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13709                                 "more active pll users than references: %x vs %x\n",
13710                                 pll->active_mask, pll->state.crtc_mask);
13711
13712                 return;
13713         }
13714
13715         crtc_mask = drm_crtc_mask(&crtc->base);
13716
13717         if (new_crtc_state->hw.active)
13718                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13719                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13720                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13721         else
13722                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13723                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13724                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13725
13726         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13727                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13728                         crtc_mask, pll->state.crtc_mask);
13729
13730         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13731                                           &dpll_hw_state,
13732                                           sizeof(dpll_hw_state)),
13733                         "pll hw state mismatch\n");
13734 }
13735
13736 static void
13737 verify_shared_dpll_state(struct intel_crtc *crtc,
13738                          struct intel_crtc_state *old_crtc_state,
13739                          struct intel_crtc_state *new_crtc_state)
13740 {
13741         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13742
13743         if (new_crtc_state->shared_dpll)
13744                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13745
13746         if (old_crtc_state->shared_dpll &&
13747             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13748                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13749                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13750
13751                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13752                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13753                                 pipe_name(drm_crtc_index(&crtc->base)));
13754                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13755                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13756                                 pipe_name(drm_crtc_index(&crtc->base)));
13757         }
13758 }
13759
13760 static void
13761 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13762                           struct intel_atomic_state *state,
13763                           struct intel_crtc_state *old_crtc_state,
13764                           struct intel_crtc_state *new_crtc_state)
13765 {
13766         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13767                 return;
13768
13769         verify_wm_state(crtc, new_crtc_state);
13770         verify_connector_state(state, crtc);
13771         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13772         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13773 }
13774
13775 static void
13776 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13777 {
13778         int i;
13779
13780         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13781                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13782 }
13783
13784 static void
13785 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13786                               struct intel_atomic_state *state)
13787 {
13788         verify_encoder_state(dev_priv, state);
13789         verify_connector_state(state, NULL);
13790         verify_disabled_dpll_state(dev_priv);
13791 }
13792
13793 static void
13794 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
13795 {
13796         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13797         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13798         const struct drm_display_mode *adjusted_mode =
13799                 &crtc_state->hw.adjusted_mode;
13800
13801         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
13802
13803         /*
13804          * The scanline counter increments at the leading edge of hsync.
13805          *
13806          * On most platforms it starts counting from vtotal-1 on the
13807          * first active line. That means the scanline counter value is
13808          * always one less than what we would expect. Ie. just after
13809          * start of vblank, which also occurs at start of hsync (on the
13810          * last active line), the scanline counter will read vblank_start-1.
13811          *
13812          * On gen2 the scanline counter starts counting from 1 instead
13813          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13814          * to keep the value positive), instead of adding one.
13815          *
13816          * On HSW+ the behaviour of the scanline counter depends on the output
13817          * type. For DP ports it behaves like most other platforms, but on HDMI
13818          * there's an extra 1 line difference. So we need to add two instead of
13819          * one to the value.
13820          *
13821          * On VLV/CHV DSI the scanline counter would appear to increment
13822          * approx. 1/3 of a scanline before start of vblank. Unfortunately
13823          * that means we can't tell whether we're in vblank or not while
13824          * we're on that particular line. We must still set scanline_offset
13825          * to 1 so that the vblank timestamps come out correct when we query
13826          * the scanline counter from within the vblank interrupt handler.
13827          * However if queried just before the start of vblank we'll get an
13828          * answer that's slightly in the future.
13829          */
13830         if (IS_GEN(dev_priv, 2)) {
13831                 int vtotal;
13832
13833                 vtotal = adjusted_mode->crtc_vtotal;
13834                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13835                         vtotal /= 2;
13836
13837                 crtc->scanline_offset = vtotal - 1;
13838         } else if (HAS_DDI(dev_priv) &&
13839                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13840                 crtc->scanline_offset = 2;
13841         } else {
13842                 crtc->scanline_offset = 1;
13843         }
13844 }
13845
13846 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13847 {
13848         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13849         struct intel_crtc_state *new_crtc_state;
13850         struct intel_crtc *crtc;
13851         int i;
13852
13853         if (!dev_priv->display.crtc_compute_clock)
13854                 return;
13855
13856         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13857                 if (!needs_modeset(new_crtc_state))
13858                         continue;
13859
13860                 intel_release_shared_dplls(state, crtc);
13861         }
13862 }
13863
13864 /*
13865  * This implements the workaround described in the "notes" section of the mode
13866  * set sequence documentation. When going from no pipes or single pipe to
13867  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13868  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13869  */
13870 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13871 {
13872         struct intel_crtc_state *crtc_state;
13873         struct intel_crtc *crtc;
13874         struct intel_crtc_state *first_crtc_state = NULL;
13875         struct intel_crtc_state *other_crtc_state = NULL;
13876         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13877         int i;
13878
13879         /* look at all crtc's that are going to be enabled in during modeset */
13880         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13881                 if (!crtc_state->hw.active ||
13882                     !needs_modeset(crtc_state))
13883                         continue;
13884
13885                 if (first_crtc_state) {
13886                         other_crtc_state = crtc_state;
13887                         break;
13888                 } else {
13889                         first_crtc_state = crtc_state;
13890                         first_pipe = crtc->pipe;
13891                 }
13892         }
13893
13894         /* No workaround needed? */
13895         if (!first_crtc_state)
13896                 return 0;
13897
13898         /* w/a possibly needed, check how many crtc's are already enabled. */
13899         for_each_intel_crtc(state->base.dev, crtc) {
13900                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13901                 if (IS_ERR(crtc_state))
13902                         return PTR_ERR(crtc_state);
13903
13904                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13905
13906                 if (!crtc_state->hw.active ||
13907                     needs_modeset(crtc_state))
13908                         continue;
13909
13910                 /* 2 or more enabled crtcs means no need for w/a */
13911                 if (enabled_pipe != INVALID_PIPE)
13912                         return 0;
13913
13914                 enabled_pipe = crtc->pipe;
13915         }
13916
13917         if (enabled_pipe != INVALID_PIPE)
13918                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13919         else if (other_crtc_state)
13920                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13921
13922         return 0;
13923 }
13924
13925 static int intel_modeset_checks(struct intel_atomic_state *state)
13926 {
13927         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13928         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13929         struct intel_crtc *crtc;
13930         int ret, i;
13931
13932         /* keep the current setting */
13933         if (!state->cdclk.force_min_cdclk_changed)
13934                 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13935
13936         state->modeset = true;
13937         state->active_pipes = dev_priv->active_pipes;
13938         state->cdclk.logical = dev_priv->cdclk.logical;
13939         state->cdclk.actual = dev_priv->cdclk.actual;
13940
13941         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13942                                             new_crtc_state, i) {
13943                 if (new_crtc_state->hw.active)
13944                         state->active_pipes |= BIT(crtc->pipe);
13945                 else
13946                         state->active_pipes &= ~BIT(crtc->pipe);
13947
13948                 if (old_crtc_state->hw.active != new_crtc_state->hw.active)
13949                         state->active_pipe_changes |= BIT(crtc->pipe);
13950         }
13951
13952         if (state->active_pipe_changes) {
13953                 ret = intel_atomic_lock_global_state(state);
13954                 if (ret)
13955                         return ret;
13956         }
13957
13958         ret = intel_modeset_calc_cdclk(state);
13959         if (ret)
13960                 return ret;
13961
13962         intel_modeset_clear_plls(state);
13963
13964         if (IS_HASWELL(dev_priv))
13965                 return haswell_mode_set_planes_workaround(state);
13966
13967         return 0;
13968 }
13969
13970 /*
13971  * Handle calculation of various watermark data at the end of the atomic check
13972  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13973  * handlers to ensure that all derived state has been updated.
13974  */
13975 static int calc_watermark_data(struct intel_atomic_state *state)
13976 {
13977         struct drm_device *dev = state->base.dev;
13978         struct drm_i915_private *dev_priv = to_i915(dev);
13979
13980         /* Is there platform-specific watermark information to calculate? */
13981         if (dev_priv->display.compute_global_watermarks)
13982                 return dev_priv->display.compute_global_watermarks(state);
13983
13984         return 0;
13985 }
13986
13987 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13988                                      struct intel_crtc_state *new_crtc_state)
13989 {
13990         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
13991                 return;
13992
13993         new_crtc_state->uapi.mode_changed = false;
13994         new_crtc_state->update_pipe = true;
13995
13996         /*
13997          * If we're not doing the full modeset we want to
13998          * keep the current M/N values as they may be
13999          * sufficiently different to the computed values
14000          * to cause problems.
14001          *
14002          * FIXME: should really copy more fuzzy state here
14003          */
14004         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14005         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14006         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14007         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14008 }
14009
14010 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14011                                           struct intel_crtc *crtc,
14012                                           u8 plane_ids_mask)
14013 {
14014         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14015         struct intel_plane *plane;
14016
14017         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14018                 struct intel_plane_state *plane_state;
14019
14020                 if ((plane_ids_mask & BIT(plane->id)) == 0)
14021                         continue;
14022
14023                 plane_state = intel_atomic_get_plane_state(state, plane);
14024                 if (IS_ERR(plane_state))
14025                         return PTR_ERR(plane_state);
14026         }
14027
14028         return 0;
14029 }
14030
14031 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14032 {
14033         /* See {hsw,vlv,ivb}_plane_ratio() */
14034         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14035                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14036                 IS_IVYBRIDGE(dev_priv);
14037 }
14038
14039 static int intel_atomic_check_planes(struct intel_atomic_state *state,
14040                                      bool *need_modeset)
14041 {
14042         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14043         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14044         struct intel_plane_state *plane_state;
14045         struct intel_plane *plane;
14046         struct intel_crtc *crtc;
14047         int i, ret;
14048
14049         ret = icl_add_linked_planes(state);
14050         if (ret)
14051                 return ret;
14052
14053         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14054                 ret = intel_plane_atomic_check(state, plane);
14055                 if (ret) {
14056                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
14057                                          plane->base.base.id, plane->base.name);
14058                         return ret;
14059                 }
14060         }
14061
14062         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14063                                             new_crtc_state, i) {
14064                 u8 old_active_planes, new_active_planes;
14065
14066                 ret = icl_check_nv12_planes(new_crtc_state);
14067                 if (ret)
14068                         return ret;
14069
14070                 /*
14071                  * On some platforms the number of active planes affects
14072                  * the planes' minimum cdclk calculation. Add such planes
14073                  * to the state before we compute the minimum cdclk.
14074                  */
14075                 if (!active_planes_affects_min_cdclk(dev_priv))
14076                         continue;
14077
14078                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14079                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14080
14081                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
14082                         continue;
14083
14084                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14085                 if (ret)
14086                         return ret;
14087         }
14088
14089         /*
14090          * active_planes bitmask has been updated, and potentially
14091          * affected planes are part of the state. We can now
14092          * compute the minimum cdclk for each plane.
14093          */
14094         for_each_new_intel_plane_in_state(state, plane, plane_state, i)
14095                 *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
14096
14097         return 0;
14098 }
14099
14100 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14101 {
14102         struct intel_crtc_state *crtc_state;
14103         struct intel_crtc *crtc;
14104         int i;
14105
14106         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14107                 int ret = intel_crtc_atomic_check(state, crtc);
14108                 if (ret) {
14109                         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
14110                                          crtc->base.base.id, crtc->base.name);
14111                         return ret;
14112                 }
14113         }
14114
14115         return 0;
14116 }
14117
14118 /**
14119  * intel_atomic_check - validate state object
14120  * @dev: drm device
14121  * @_state: state to validate
14122  */
14123 static int intel_atomic_check(struct drm_device *dev,
14124                               struct drm_atomic_state *_state)
14125 {
14126         struct drm_i915_private *dev_priv = to_i915(dev);
14127         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14128         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14129         struct intel_crtc *crtc;
14130         int ret, i;
14131         bool any_ms = false;
14132
14133         /* Catch I915_MODE_FLAG_INHERITED */
14134         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14135                                             new_crtc_state, i) {
14136                 if (new_crtc_state->hw.mode.private_flags !=
14137                     old_crtc_state->hw.mode.private_flags)
14138                         new_crtc_state->uapi.mode_changed = true;
14139         }
14140
14141         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14142         if (ret)
14143                 goto fail;
14144
14145         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14146                                             new_crtc_state, i) {
14147                 if (!needs_modeset(new_crtc_state)) {
14148                         /* Light copy */
14149                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14150
14151                         continue;
14152                 }
14153
14154                 if (!new_crtc_state->uapi.enable) {
14155                         intel_crtc_copy_uapi_to_hw_state(new_crtc_state);
14156
14157                         any_ms = true;
14158                         continue;
14159                 }
14160
14161                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14162                 if (ret)
14163                         goto fail;
14164
14165                 ret = intel_modeset_pipe_config(new_crtc_state);
14166                 if (ret)
14167                         goto fail;
14168
14169                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14170
14171                 if (needs_modeset(new_crtc_state))
14172                         any_ms = true;
14173         }
14174
14175         if (any_ms && !check_digital_port_conflicts(state)) {
14176                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14177                 ret = EINVAL;
14178                 goto fail;
14179         }
14180
14181         ret = drm_dp_mst_atomic_check(&state->base);
14182         if (ret)
14183                 goto fail;
14184
14185         any_ms |= state->cdclk.force_min_cdclk_changed;
14186
14187         ret = intel_atomic_check_planes(state, &any_ms);
14188         if (ret)
14189                 goto fail;
14190
14191         if (any_ms) {
14192                 ret = intel_modeset_checks(state);
14193                 if (ret)
14194                         goto fail;
14195         } else {
14196                 state->cdclk.logical = dev_priv->cdclk.logical;
14197         }
14198
14199         ret = intel_atomic_check_crtcs(state);
14200         if (ret)
14201                 goto fail;
14202
14203         intel_fbc_choose_crtc(dev_priv, state);
14204         ret = calc_watermark_data(state);
14205         if (ret)
14206                 goto fail;
14207
14208         ret = intel_bw_atomic_check(state);
14209         if (ret)
14210                 goto fail;
14211
14212         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14213                                             new_crtc_state, i) {
14214                 if (!needs_modeset(new_crtc_state) &&
14215                     !new_crtc_state->update_pipe)
14216                         continue;
14217
14218                 intel_dump_pipe_config(new_crtc_state, state,
14219                                        needs_modeset(new_crtc_state) ?
14220                                        "[modeset]" : "[fastset]");
14221         }
14222
14223         return 0;
14224
14225  fail:
14226         if (ret == -EDEADLK)
14227                 return ret;
14228
14229         /*
14230          * FIXME would probably be nice to know which crtc specifically
14231          * caused the failure, in cases where we can pinpoint it.
14232          */
14233         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14234                                             new_crtc_state, i)
14235                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14236
14237         return ret;
14238 }
14239
14240 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14241 {
14242         return drm_atomic_helper_prepare_planes(state->base.dev,
14243                                                 &state->base);
14244 }
14245
14246 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14247 {
14248         struct drm_device *dev = crtc->base.dev;
14249         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14250
14251         if (!vblank->max_vblank_count)
14252                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14253
14254         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14255 }
14256
14257 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14258                                   struct intel_crtc_state *crtc_state)
14259 {
14260         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14261
14262         if (!IS_GEN(dev_priv, 2))
14263                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14264
14265         if (crtc_state->has_pch_encoder) {
14266                 enum pipe pch_transcoder =
14267                         intel_crtc_pch_transcoder(crtc);
14268
14269                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14270         }
14271 }
14272
14273 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14274                                const struct intel_crtc_state *new_crtc_state)
14275 {
14276         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14277         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14278
14279         /*
14280          * Update pipe size and adjust fitter if needed: the reason for this is
14281          * that in compute_mode_changes we check the native mode (not the pfit
14282          * mode) to see if we can flip rather than do a full mode set. In the
14283          * fastboot case, we'll flip, but if we don't update the pipesrc and
14284          * pfit state, we'll end up with a big fb scanned out into the wrong
14285          * sized surface.
14286          */
14287         intel_set_pipe_src_size(new_crtc_state);
14288
14289         /* on skylake this is done by detaching scalers */
14290         if (INTEL_GEN(dev_priv) >= 9) {
14291                 skl_detach_scalers(new_crtc_state);
14292
14293                 if (new_crtc_state->pch_pfit.enabled)
14294                         skylake_pfit_enable(new_crtc_state);
14295         } else if (HAS_PCH_SPLIT(dev_priv)) {
14296                 if (new_crtc_state->pch_pfit.enabled)
14297                         ironlake_pfit_enable(new_crtc_state);
14298                 else if (old_crtc_state->pch_pfit.enabled)
14299                         ironlake_pfit_disable(old_crtc_state);
14300         }
14301
14302         if (INTEL_GEN(dev_priv) >= 11)
14303                 icl_set_pipe_chicken(crtc);
14304 }
14305
14306 static void commit_pipe_config(struct intel_atomic_state *state,
14307                                struct intel_crtc_state *old_crtc_state,
14308                                struct intel_crtc_state *new_crtc_state)
14309 {
14310         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14311         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14312         bool modeset = needs_modeset(new_crtc_state);
14313
14314         /*
14315          * During modesets pipe configuration was programmed as the
14316          * CRTC was enabled.
14317          */
14318         if (!modeset) {
14319                 if (new_crtc_state->uapi.color_mgmt_changed ||
14320                     new_crtc_state->update_pipe)
14321                         intel_color_commit(new_crtc_state);
14322
14323                 if (INTEL_GEN(dev_priv) >= 9)
14324                         skl_detach_scalers(new_crtc_state);
14325
14326                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14327                         bdw_set_pipemisc(new_crtc_state);
14328
14329                 if (new_crtc_state->update_pipe)
14330                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
14331         }
14332
14333         if (dev_priv->display.atomic_update_watermarks)
14334                 dev_priv->display.atomic_update_watermarks(state, crtc);
14335 }
14336
14337 static void intel_update_crtc(struct intel_crtc *crtc,
14338                               struct intel_atomic_state *state,
14339                               struct intel_crtc_state *old_crtc_state,
14340                               struct intel_crtc_state *new_crtc_state)
14341 {
14342         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14343         bool modeset = needs_modeset(new_crtc_state);
14344         struct intel_plane_state *new_plane_state =
14345                 intel_atomic_get_new_plane_state(state,
14346                                                  to_intel_plane(crtc->base.primary));
14347
14348         if (modeset) {
14349                 intel_crtc_update_active_timings(new_crtc_state);
14350
14351                 dev_priv->display.crtc_enable(new_crtc_state, state);
14352
14353                 /* vblanks work again, re-enable pipe CRC. */
14354                 intel_crtc_enable_pipe_crc(crtc);
14355         } else {
14356                 if (new_crtc_state->preload_luts &&
14357                     (new_crtc_state->uapi.color_mgmt_changed ||
14358                      new_crtc_state->update_pipe))
14359                         intel_color_load_luts(new_crtc_state);
14360
14361                 intel_pre_plane_update(old_crtc_state, new_crtc_state);
14362
14363                 if (new_crtc_state->update_pipe)
14364                         intel_encoders_update_pipe(state, crtc);
14365         }
14366
14367         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14368                 intel_fbc_disable(crtc);
14369         else if (new_plane_state)
14370                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14371
14372         /* Perform vblank evasion around commit operation */
14373         intel_pipe_update_start(new_crtc_state);
14374
14375         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14376
14377         if (INTEL_GEN(dev_priv) >= 9)
14378                 skl_update_planes_on_crtc(state, crtc);
14379         else
14380                 i9xx_update_planes_on_crtc(state, crtc);
14381
14382         intel_pipe_update_end(new_crtc_state);
14383
14384         /*
14385          * We usually enable FIFO underrun interrupts as part of the
14386          * CRTC enable sequence during modesets.  But when we inherit a
14387          * valid pipe configuration from the BIOS we need to take care
14388          * of enabling them on the CRTC's first fastset.
14389          */
14390         if (new_crtc_state->update_pipe && !modeset &&
14391             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14392                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14393 }
14394
14395 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
14396 {
14397         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
14398         enum transcoder slave_transcoder;
14399
14400         WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
14401
14402         slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
14403         return intel_get_crtc_for_pipe(dev_priv,
14404                                        (enum pipe)slave_transcoder);
14405 }
14406
14407 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
14408                                           struct intel_crtc_state *old_crtc_state,
14409                                           struct intel_crtc_state *new_crtc_state,
14410                                           struct intel_crtc *crtc)
14411 {
14412         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14413
14414         intel_crtc_disable_planes(state, crtc);
14415
14416         /*
14417          * We need to disable pipe CRC before disabling the pipe,
14418          * or we race against vblank off.
14419          */
14420         intel_crtc_disable_pipe_crc(crtc);
14421
14422         dev_priv->display.crtc_disable(old_crtc_state, state);
14423         crtc->active = false;
14424         intel_fbc_disable(crtc);
14425         intel_disable_shared_dpll(old_crtc_state);
14426
14427         /*
14428          * Underruns don't always raise interrupts,
14429          * so check manually.
14430          */
14431         intel_check_cpu_fifo_underruns(dev_priv);
14432         intel_check_pch_fifo_underruns(dev_priv);
14433
14434         /* FIXME unify this for all platforms */
14435         if (!new_crtc_state->hw.active &&
14436             !HAS_GMCH(dev_priv) &&
14437             dev_priv->display.initial_watermarks)
14438                 dev_priv->display.initial_watermarks(state, crtc);
14439 }
14440
14441 static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
14442                                                    struct intel_crtc *crtc,
14443                                                    struct intel_crtc_state *old_crtc_state,
14444                                                    struct intel_crtc_state *new_crtc_state)
14445 {
14446         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14447         struct intel_crtc_state *new_slave_crtc_state =
14448                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14449         struct intel_crtc_state *old_slave_crtc_state =
14450                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14451
14452         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14453                 !old_slave_crtc_state);
14454
14455         /* Disable Slave first */
14456         intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
14457         if (old_slave_crtc_state->hw.active)
14458                 intel_old_crtc_state_disables(state,
14459                                               old_slave_crtc_state,
14460                                               new_slave_crtc_state,
14461                                               slave_crtc);
14462
14463         /* Disable Master */
14464         intel_pre_plane_update(old_crtc_state, new_crtc_state);
14465         if (old_crtc_state->hw.active)
14466                 intel_old_crtc_state_disables(state,
14467                                               old_crtc_state,
14468                                               new_crtc_state,
14469                                               crtc);
14470 }
14471
14472 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
14473 {
14474         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14475         struct intel_crtc *crtc;
14476         int i;
14477
14478         /*
14479          * Disable CRTC/pipes in reverse order because some features(MST in
14480          * TGL+) requires master and slave relationship between pipes, so it
14481          * should always pick the lowest pipe as master as it will be enabled
14482          * first and disable in the reverse order so the master will be the
14483          * last one to be disabled.
14484          */
14485         for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
14486                                                     new_crtc_state, i) {
14487                 if (!needs_modeset(new_crtc_state))
14488                         continue;
14489
14490                 /* In case of Transcoder port Sync master slave CRTCs can be
14491                  * assigned in any order and we need to make sure that
14492                  * slave CRTCs are disabled first and then master CRTC since
14493                  * Slave vblanks are masked till Master Vblanks.
14494                  */
14495                 if (is_trans_port_sync_mode(new_crtc_state)) {
14496                         if (is_trans_port_sync_master(new_crtc_state))
14497                                 intel_trans_port_sync_modeset_disables(state,
14498                                                                        crtc,
14499                                                                        old_crtc_state,
14500                                                                        new_crtc_state);
14501                         else
14502                                 continue;
14503                 } else {
14504                         intel_pre_plane_update(old_crtc_state, new_crtc_state);
14505
14506                         if (old_crtc_state->hw.active)
14507                                 intel_old_crtc_state_disables(state,
14508                                                               old_crtc_state,
14509                                                               new_crtc_state,
14510                                                               crtc);
14511                 }
14512         }
14513 }
14514
14515 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
14516 {
14517         struct intel_crtc *crtc;
14518         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14519         int i;
14520
14521         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14522                 if (!new_crtc_state->hw.active)
14523                         continue;
14524
14525                 intel_update_crtc(crtc, state, old_crtc_state,
14526                                   new_crtc_state);
14527         }
14528 }
14529
14530 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
14531                                               struct intel_atomic_state *state,
14532                                               struct intel_crtc_state *new_crtc_state)
14533 {
14534         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14535
14536         intel_crtc_update_active_timings(new_crtc_state);
14537         dev_priv->display.crtc_enable(new_crtc_state, state);
14538         intel_crtc_enable_pipe_crc(crtc);
14539 }
14540
14541 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
14542                                        struct intel_atomic_state *state)
14543 {
14544         struct drm_connector *uninitialized_var(conn);
14545         struct drm_connector_state *conn_state;
14546         struct intel_dp *intel_dp;
14547         int i;
14548
14549         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
14550                 if (conn_state->crtc == &crtc->base)
14551                         break;
14552         }
14553         intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
14554         intel_dp_stop_link_train(intel_dp);
14555 }
14556
14557 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
14558                                            struct intel_atomic_state *state)
14559 {
14560         struct intel_crtc_state *new_crtc_state =
14561                 intel_atomic_get_new_crtc_state(state, crtc);
14562         struct intel_crtc_state *old_crtc_state =
14563                 intel_atomic_get_old_crtc_state(state, crtc);
14564         struct intel_plane_state *new_plane_state =
14565                 intel_atomic_get_new_plane_state(state,
14566                                                  to_intel_plane(crtc->base.primary));
14567         bool modeset = needs_modeset(new_crtc_state);
14568
14569         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14570                 intel_fbc_disable(crtc);
14571         else if (new_plane_state)
14572                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14573
14574         /* Perform vblank evasion around commit operation */
14575         intel_pipe_update_start(new_crtc_state);
14576         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14577         skl_update_planes_on_crtc(state, crtc);
14578         intel_pipe_update_end(new_crtc_state);
14579
14580         /*
14581          * We usually enable FIFO underrun interrupts as part of the
14582          * CRTC enable sequence during modesets.  But when we inherit a
14583          * valid pipe configuration from the BIOS we need to take care
14584          * of enabling them on the CRTC's first fastset.
14585          */
14586         if (new_crtc_state->update_pipe && !modeset &&
14587             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14588                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14589 }
14590
14591 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
14592                                                struct intel_atomic_state *state,
14593                                                struct intel_crtc_state *old_crtc_state,
14594                                                struct intel_crtc_state *new_crtc_state)
14595 {
14596         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14597         struct intel_crtc_state *new_slave_crtc_state =
14598                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14599         struct intel_crtc_state *old_slave_crtc_state =
14600                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14601
14602         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14603                 !old_slave_crtc_state);
14604
14605         DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
14606                       crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
14607                       slave_crtc->base.name);
14608
14609         /* Enable seq for slave with with DP_TP_CTL left Idle until the
14610          * master is ready
14611          */
14612         intel_crtc_enable_trans_port_sync(slave_crtc,
14613                                           state,
14614                                           new_slave_crtc_state);
14615
14616         /* Enable seq for master with with DP_TP_CTL left Idle */
14617         intel_crtc_enable_trans_port_sync(crtc,
14618                                           state,
14619                                           new_crtc_state);
14620
14621         /* Set Slave's DP_TP_CTL to Normal */
14622         intel_set_dp_tp_ctl_normal(slave_crtc,
14623                                    state);
14624
14625         /* Set Master's DP_TP_CTL To Normal */
14626         usleep_range(200, 400);
14627         intel_set_dp_tp_ctl_normal(crtc,
14628                                    state);
14629
14630         /* Now do the post crtc enable for all master and slaves */
14631         intel_post_crtc_enable_updates(slave_crtc,
14632                                        state);
14633         intel_post_crtc_enable_updates(crtc,
14634                                        state);
14635 }
14636
14637 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
14638 {
14639         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14640         struct intel_crtc *crtc;
14641         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14642         unsigned int updated = 0;
14643         bool progress;
14644         int i;
14645         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
14646         u8 required_slices = state->wm_results.ddb.enabled_slices;
14647         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
14648
14649         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
14650                 /* ignore allocations for crtc's that have been turned off. */
14651                 if (new_crtc_state->hw.active)
14652                         entries[i] = old_crtc_state->wm.skl.ddb;
14653
14654         /* If 2nd DBuf slice required, enable it here */
14655         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
14656                 icl_dbuf_slices_update(dev_priv, required_slices);
14657
14658         /*
14659          * Whenever the number of active pipes changes, we need to make sure we
14660          * update the pipes in the right order so that their ddb allocations
14661          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14662          * cause pipe underruns and other bad stuff.
14663          */
14664         do {
14665                 progress = false;
14666
14667                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14668                         enum pipe pipe = crtc->pipe;
14669                         bool vbl_wait = false;
14670                         bool modeset = needs_modeset(new_crtc_state);
14671
14672                         if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
14673                                 continue;
14674
14675                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
14676                                                         entries,
14677                                                         INTEL_NUM_PIPES(dev_priv), i))
14678                                 continue;
14679
14680                         updated |= BIT(pipe);
14681                         entries[i] = new_crtc_state->wm.skl.ddb;
14682
14683                         /*
14684                          * If this is an already active pipe, it's DDB changed,
14685                          * and this isn't the last pipe that needs updating
14686                          * then we need to wait for a vblank to pass for the
14687                          * new ddb allocation to take effect.
14688                          */
14689                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
14690                                                  &old_crtc_state->wm.skl.ddb) &&
14691                             !modeset &&
14692                             state->wm_results.dirty_pipes != updated)
14693                                 vbl_wait = true;
14694
14695                         if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
14696                                 if (is_trans_port_sync_master(new_crtc_state))
14697                                         intel_update_trans_port_sync_crtcs(crtc,
14698                                                                            state,
14699                                                                            old_crtc_state,
14700                                                                            new_crtc_state);
14701                                 else
14702                                         continue;
14703                         } else {
14704                                 intel_update_crtc(crtc, state, old_crtc_state,
14705                                                   new_crtc_state);
14706                         }
14707
14708                         if (vbl_wait)
14709                                 intel_wait_for_vblank(dev_priv, pipe);
14710
14711                         progress = true;
14712                 }
14713         } while (progress);
14714
14715         /* If 2nd DBuf slice is no more required disable it */
14716         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
14717                 icl_dbuf_slices_update(dev_priv, required_slices);
14718 }
14719
14720 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14721 {
14722         struct intel_atomic_state *state, *next;
14723         struct llist_node *freed;
14724
14725         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14726         llist_for_each_entry_safe(state, next, freed, freed)
14727                 drm_atomic_state_put(&state->base);
14728 }
14729
14730 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14731 {
14732         struct drm_i915_private *dev_priv =
14733                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14734
14735         intel_atomic_helper_free_state(dev_priv);
14736 }
14737
14738 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
14739 {
14740         struct wait_queue_entry wait_fence, wait_reset;
14741         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
14742
14743         init_wait_entry(&wait_fence, 0);
14744         init_wait_entry(&wait_reset, 0);
14745         for (;;) {
14746                 prepare_to_wait(&intel_state->commit_ready.wait,
14747                                 &wait_fence, TASK_UNINTERRUPTIBLE);
14748                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14749                                               I915_RESET_MODESET),
14750                                 &wait_reset, TASK_UNINTERRUPTIBLE);
14751
14752
14753                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
14754                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
14755                         break;
14756
14757                 schedule();
14758         }
14759         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
14760         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14761                                   I915_RESET_MODESET),
14762                     &wait_reset);
14763 }
14764
14765 static void intel_atomic_cleanup_work(struct work_struct *work)
14766 {
14767         struct drm_atomic_state *state =
14768                 container_of(work, struct drm_atomic_state, commit_work);
14769         struct drm_i915_private *i915 = to_i915(state->dev);
14770
14771         drm_atomic_helper_cleanup_planes(&i915->drm, state);
14772         drm_atomic_helper_commit_cleanup_done(state);
14773         drm_atomic_state_put(state);
14774
14775         intel_atomic_helper_free_state(i915);
14776 }
14777
14778 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
14779 {
14780         struct drm_device *dev = state->base.dev;
14781         struct drm_i915_private *dev_priv = to_i915(dev);
14782         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14783         struct intel_crtc *crtc;
14784         u64 put_domains[I915_MAX_PIPES] = {};
14785         intel_wakeref_t wakeref = 0;
14786         int i;
14787
14788         intel_atomic_commit_fence_wait(state);
14789
14790         drm_atomic_helper_wait_for_dependencies(&state->base);
14791
14792         if (state->modeset)
14793                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14794
14795         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14796                                             new_crtc_state, i) {
14797                 if (needs_modeset(new_crtc_state) ||
14798                     new_crtc_state->update_pipe) {
14799
14800                         put_domains[crtc->pipe] =
14801                                 modeset_get_crtc_power_domains(new_crtc_state);
14802                 }
14803         }
14804
14805         intel_commit_modeset_disables(state);
14806
14807         /* FIXME: Eventually get rid of our crtc->config pointer */
14808         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14809                 crtc->config = new_crtc_state;
14810
14811         if (state->modeset) {
14812                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14813
14814                 intel_set_cdclk_pre_plane_update(dev_priv,
14815                                                  &state->cdclk.actual,
14816                                                  &dev_priv->cdclk.actual,
14817                                                  state->cdclk.pipe);
14818
14819                 /*
14820                  * SKL workaround: bspec recommends we disable the SAGV when we
14821                  * have more then one pipe enabled
14822                  */
14823                 if (!intel_can_enable_sagv(state))
14824                         intel_disable_sagv(dev_priv);
14825
14826                 intel_modeset_verify_disabled(dev_priv, state);
14827         }
14828
14829         /* Complete the events for pipes that have now been disabled */
14830         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14831                 bool modeset = needs_modeset(new_crtc_state);
14832
14833                 /* Complete events for now disable pipes here. */
14834                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
14835                         spin_lock_irq(&dev->event_lock);
14836                         drm_crtc_send_vblank_event(&crtc->base,
14837                                                    new_crtc_state->uapi.event);
14838                         spin_unlock_irq(&dev->event_lock);
14839
14840                         new_crtc_state->uapi.event = NULL;
14841                 }
14842         }
14843
14844         if (state->modeset)
14845                 intel_encoders_update_prepare(state);
14846
14847         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14848         dev_priv->display.commit_modeset_enables(state);
14849
14850         if (state->modeset) {
14851                 intel_encoders_update_complete(state);
14852
14853                 intel_set_cdclk_post_plane_update(dev_priv,
14854                                                   &state->cdclk.actual,
14855                                                   &dev_priv->cdclk.actual,
14856                                                   state->cdclk.pipe);
14857         }
14858
14859         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14860          * already, but still need the state for the delayed optimization. To
14861          * fix this:
14862          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14863          * - schedule that vblank worker _before_ calling hw_done
14864          * - at the start of commit_tail, cancel it _synchrously
14865          * - switch over to the vblank wait helper in the core after that since
14866          *   we don't need out special handling any more.
14867          */
14868         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14869
14870         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14871                 if (new_crtc_state->hw.active &&
14872                     !needs_modeset(new_crtc_state) &&
14873                     !new_crtc_state->preload_luts &&
14874                     (new_crtc_state->uapi.color_mgmt_changed ||
14875                      new_crtc_state->update_pipe))
14876                         intel_color_load_luts(new_crtc_state);
14877         }
14878
14879         /*
14880          * Now that the vblank has passed, we can go ahead and program the
14881          * optimal watermarks on platforms that need two-step watermark
14882          * programming.
14883          *
14884          * TODO: Move this (and other cleanup) to an async worker eventually.
14885          */
14886         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14887                 if (dev_priv->display.optimize_watermarks)
14888                         dev_priv->display.optimize_watermarks(state, crtc);
14889         }
14890
14891         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14892                 intel_post_plane_update(old_crtc_state);
14893
14894                 if (put_domains[i])
14895                         modeset_put_power_domains(dev_priv, put_domains[i]);
14896
14897                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14898         }
14899
14900         if (state->modeset)
14901                 intel_verify_planes(state);
14902
14903         if (state->modeset && intel_can_enable_sagv(state))
14904                 intel_enable_sagv(dev_priv);
14905
14906         drm_atomic_helper_commit_hw_done(&state->base);
14907
14908         if (state->modeset) {
14909                 /* As one of the primary mmio accessors, KMS has a high
14910                  * likelihood of triggering bugs in unclaimed access. After we
14911                  * finish modesetting, see if an error has been flagged, and if
14912                  * so enable debugging for the next modeset - and hope we catch
14913                  * the culprit.
14914                  */
14915                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14916                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14917         }
14918         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14919
14920         /*
14921          * Defer the cleanup of the old state to a separate worker to not
14922          * impede the current task (userspace for blocking modesets) that
14923          * are executed inline. For out-of-line asynchronous modesets/flips,
14924          * deferring to a new worker seems overkill, but we would place a
14925          * schedule point (cond_resched()) here anyway to keep latencies
14926          * down.
14927          */
14928         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14929         queue_work(system_highpri_wq, &state->base.commit_work);
14930 }
14931
14932 static void intel_atomic_commit_work(struct work_struct *work)
14933 {
14934         struct intel_atomic_state *state =
14935                 container_of(work, struct intel_atomic_state, base.commit_work);
14936
14937         intel_atomic_commit_tail(state);
14938 }
14939
14940 static int __i915_sw_fence_call
14941 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14942                           enum i915_sw_fence_notify notify)
14943 {
14944         struct intel_atomic_state *state =
14945                 container_of(fence, struct intel_atomic_state, commit_ready);
14946
14947         switch (notify) {
14948         case FENCE_COMPLETE:
14949                 /* we do blocking waits in the worker, nothing to do here */
14950                 break;
14951         case FENCE_FREE:
14952                 {
14953                         struct intel_atomic_helper *helper =
14954                                 &to_i915(state->base.dev)->atomic_helper;
14955
14956                         if (llist_add(&state->freed, &helper->free_list))
14957                                 schedule_work(&helper->free_work);
14958                         break;
14959                 }
14960         }
14961
14962         return NOTIFY_DONE;
14963 }
14964
14965 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14966 {
14967         struct intel_plane_state *old_plane_state, *new_plane_state;
14968         struct intel_plane *plane;
14969         int i;
14970
14971         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14972                                              new_plane_state, i)
14973                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
14974                                         to_intel_frontbuffer(new_plane_state->hw.fb),
14975                                         plane->frontbuffer_bit);
14976 }
14977
14978 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
14979 {
14980         struct intel_crtc *crtc;
14981
14982         for_each_intel_crtc(&dev_priv->drm, crtc)
14983                 drm_modeset_lock_assert_held(&crtc->base.mutex);
14984 }
14985
14986 static int intel_atomic_commit(struct drm_device *dev,
14987                                struct drm_atomic_state *_state,
14988                                bool nonblock)
14989 {
14990         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14991         struct drm_i915_private *dev_priv = to_i915(dev);
14992         int ret = 0;
14993
14994         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
14995
14996         drm_atomic_state_get(&state->base);
14997         i915_sw_fence_init(&state->commit_ready,
14998                            intel_atomic_commit_ready);
14999
15000         /*
15001          * The intel_legacy_cursor_update() fast path takes care
15002          * of avoiding the vblank waits for simple cursor
15003          * movement and flips. For cursor on/off and size changes,
15004          * we want to perform the vblank waits so that watermark
15005          * updates happen during the correct frames. Gen9+ have
15006          * double buffered watermarks and so shouldn't need this.
15007          *
15008          * Unset state->legacy_cursor_update before the call to
15009          * drm_atomic_helper_setup_commit() because otherwise
15010          * drm_atomic_helper_wait_for_flip_done() is a noop and
15011          * we get FIFO underruns because we didn't wait
15012          * for vblank.
15013          *
15014          * FIXME doing watermarks and fb cleanup from a vblank worker
15015          * (assuming we had any) would solve these problems.
15016          */
15017         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15018                 struct intel_crtc_state *new_crtc_state;
15019                 struct intel_crtc *crtc;
15020                 int i;
15021
15022                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15023                         if (new_crtc_state->wm.need_postvbl_update ||
15024                             new_crtc_state->update_wm_post)
15025                                 state->base.legacy_cursor_update = false;
15026         }
15027
15028         ret = intel_atomic_prepare_commit(state);
15029         if (ret) {
15030                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
15031                 i915_sw_fence_commit(&state->commit_ready);
15032                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15033                 return ret;
15034         }
15035
15036         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15037         if (!ret)
15038                 ret = drm_atomic_helper_swap_state(&state->base, true);
15039
15040         if (ret) {
15041                 i915_sw_fence_commit(&state->commit_ready);
15042
15043                 drm_atomic_helper_cleanup_planes(dev, &state->base);
15044                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15045                 return ret;
15046         }
15047         dev_priv->wm.distrust_bios_wm = false;
15048         intel_shared_dpll_swap_state(state);
15049         intel_atomic_track_fbs(state);
15050
15051         if (state->global_state_changed) {
15052                 assert_global_state_locked(dev_priv);
15053
15054                 memcpy(dev_priv->min_cdclk, state->min_cdclk,
15055                        sizeof(state->min_cdclk));
15056                 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
15057                        sizeof(state->min_voltage_level));
15058                 dev_priv->active_pipes = state->active_pipes;
15059                 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
15060
15061                 intel_cdclk_swap_state(state);
15062         }
15063
15064         drm_atomic_state_get(&state->base);
15065         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15066
15067         i915_sw_fence_commit(&state->commit_ready);
15068         if (nonblock && state->modeset) {
15069                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15070         } else if (nonblock) {
15071                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15072         } else {
15073                 if (state->modeset)
15074                         flush_workqueue(dev_priv->modeset_wq);
15075                 intel_atomic_commit_tail(state);
15076         }
15077
15078         return 0;
15079 }
15080
15081 struct wait_rps_boost {
15082         struct wait_queue_entry wait;
15083
15084         struct drm_crtc *crtc;
15085         struct i915_request *request;
15086 };
15087
15088 static int do_rps_boost(struct wait_queue_entry *_wait,
15089                         unsigned mode, int sync, void *key)
15090 {
15091         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15092         struct i915_request *rq = wait->request;
15093
15094         /*
15095          * If we missed the vblank, but the request is already running it
15096          * is reasonable to assume that it will complete before the next
15097          * vblank without our intervention, so leave RPS alone.
15098          */
15099         if (!i915_request_started(rq))
15100                 intel_rps_boost(rq);
15101         i915_request_put(rq);
15102
15103         drm_crtc_vblank_put(wait->crtc);
15104
15105         list_del(&wait->wait.entry);
15106         kfree(wait);
15107         return 1;
15108 }
15109
15110 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15111                                        struct dma_fence *fence)
15112 {
15113         struct wait_rps_boost *wait;
15114
15115         if (!dma_fence_is_i915(fence))
15116                 return;
15117
15118         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15119                 return;
15120
15121         if (drm_crtc_vblank_get(crtc))
15122                 return;
15123
15124         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15125         if (!wait) {
15126                 drm_crtc_vblank_put(crtc);
15127                 return;
15128         }
15129
15130         wait->request = to_request(dma_fence_get(fence));
15131         wait->crtc = crtc;
15132
15133         wait->wait.func = do_rps_boost;
15134         wait->wait.flags = 0;
15135
15136         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15137 }
15138
15139 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15140 {
15141         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15142         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15143         struct drm_framebuffer *fb = plane_state->hw.fb;
15144         struct i915_vma *vma;
15145
15146         if (plane->id == PLANE_CURSOR &&
15147             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15148                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15149                 const int align = intel_cursor_alignment(dev_priv);
15150                 int err;
15151
15152                 err = i915_gem_object_attach_phys(obj, align);
15153                 if (err)
15154                         return err;
15155         }
15156
15157         vma = intel_pin_and_fence_fb_obj(fb,
15158                                          &plane_state->view,
15159                                          intel_plane_uses_fence(plane_state),
15160                                          &plane_state->flags);
15161         if (IS_ERR(vma))
15162                 return PTR_ERR(vma);
15163
15164         plane_state->vma = vma;
15165
15166         return 0;
15167 }
15168
15169 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15170 {
15171         struct i915_vma *vma;
15172
15173         vma = fetch_and_zero(&old_plane_state->vma);
15174         if (vma)
15175                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15176 }
15177
15178 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15179 {
15180         struct i915_sched_attr attr = {
15181                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15182         };
15183
15184         i915_gem_object_wait_priority(obj, 0, &attr);
15185 }
15186
15187 /**
15188  * intel_prepare_plane_fb - Prepare fb for usage on plane
15189  * @plane: drm plane to prepare for
15190  * @_new_plane_state: the plane state being prepared
15191  *
15192  * Prepares a framebuffer for usage on a display plane.  Generally this
15193  * involves pinning the underlying object and updating the frontbuffer tracking
15194  * bits.  Some older platforms need special physical address handling for
15195  * cursor planes.
15196  *
15197  * Returns 0 on success, negative error code on failure.
15198  */
15199 int
15200 intel_prepare_plane_fb(struct drm_plane *plane,
15201                        struct drm_plane_state *_new_plane_state)
15202 {
15203         struct intel_plane_state *new_plane_state =
15204                 to_intel_plane_state(_new_plane_state);
15205         struct intel_atomic_state *intel_state =
15206                 to_intel_atomic_state(new_plane_state->uapi.state);
15207         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15208         struct drm_framebuffer *fb = new_plane_state->hw.fb;
15209         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15210         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
15211         int ret;
15212
15213         if (old_obj) {
15214                 struct intel_crtc_state *crtc_state =
15215                         intel_atomic_get_new_crtc_state(intel_state,
15216                                                         to_intel_crtc(plane->state->crtc));
15217
15218                 /* Big Hammer, we also need to ensure that any pending
15219                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15220                  * current scanout is retired before unpinning the old
15221                  * framebuffer. Note that we rely on userspace rendering
15222                  * into the buffer attached to the pipe they are waiting
15223                  * on. If not, userspace generates a GPU hang with IPEHR
15224                  * point to the MI_WAIT_FOR_EVENT.
15225                  *
15226                  * This should only fail upon a hung GPU, in which case we
15227                  * can safely continue.
15228                  */
15229                 if (needs_modeset(crtc_state)) {
15230                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15231                                                               old_obj->base.resv, NULL,
15232                                                               false, 0,
15233                                                               GFP_KERNEL);
15234                         if (ret < 0)
15235                                 return ret;
15236                 }
15237         }
15238
15239         if (new_plane_state->uapi.fence) { /* explicit fencing */
15240                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
15241                                                     new_plane_state->uapi.fence,
15242                                                     I915_FENCE_TIMEOUT,
15243                                                     GFP_KERNEL);
15244                 if (ret < 0)
15245                         return ret;
15246         }
15247
15248         if (!obj)
15249                 return 0;
15250
15251         ret = i915_gem_object_pin_pages(obj);
15252         if (ret)
15253                 return ret;
15254
15255         ret = intel_plane_pin_fb(new_plane_state);
15256
15257         i915_gem_object_unpin_pages(obj);
15258         if (ret)
15259                 return ret;
15260
15261         fb_obj_bump_render_priority(obj);
15262         intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
15263
15264         if (!new_plane_state->uapi.fence) { /* implicit fencing */
15265                 struct dma_fence *fence;
15266
15267                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15268                                                       obj->base.resv, NULL,
15269                                                       false, I915_FENCE_TIMEOUT,
15270                                                       GFP_KERNEL);
15271                 if (ret < 0)
15272                         return ret;
15273
15274                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15275                 if (fence) {
15276                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15277                                                    fence);
15278                         dma_fence_put(fence);
15279                 }
15280         } else {
15281                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15282                                            new_plane_state->uapi.fence);
15283         }
15284
15285         /*
15286          * We declare pageflips to be interactive and so merit a small bias
15287          * towards upclocking to deliver the frame on time. By only changing
15288          * the RPS thresholds to sample more regularly and aim for higher
15289          * clocks we can hopefully deliver low power workloads (like kodi)
15290          * that are not quite steady state without resorting to forcing
15291          * maximum clocks following a vblank miss (see do_rps_boost()).
15292          */
15293         if (!intel_state->rps_interactive) {
15294                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15295                 intel_state->rps_interactive = true;
15296         }
15297
15298         return 0;
15299 }
15300
15301 /**
15302  * intel_cleanup_plane_fb - Cleans up an fb after plane use
15303  * @plane: drm plane to clean up for
15304  * @_old_plane_state: the state from the previous modeset
15305  *
15306  * Cleans up a framebuffer that has just been removed from a plane.
15307  */
15308 void
15309 intel_cleanup_plane_fb(struct drm_plane *plane,
15310                        struct drm_plane_state *_old_plane_state)
15311 {
15312         struct intel_plane_state *old_plane_state =
15313                 to_intel_plane_state(_old_plane_state);
15314         struct intel_atomic_state *intel_state =
15315                 to_intel_atomic_state(old_plane_state->uapi.state);
15316         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15317
15318         if (intel_state->rps_interactive) {
15319                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15320                 intel_state->rps_interactive = false;
15321         }
15322
15323         /* Should only be called after a successful intel_prepare_plane_fb()! */
15324         intel_plane_unpin_fb(old_plane_state);
15325 }
15326
15327 /**
15328  * intel_plane_destroy - destroy a plane
15329  * @plane: plane to destroy
15330  *
15331  * Common destruction function for all types of planes (primary, cursor,
15332  * sprite).
15333  */
15334 void intel_plane_destroy(struct drm_plane *plane)
15335 {
15336         drm_plane_cleanup(plane);
15337         kfree(to_intel_plane(plane));
15338 }
15339
15340 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15341                                             u32 format, u64 modifier)
15342 {
15343         switch (modifier) {
15344         case DRM_FORMAT_MOD_LINEAR:
15345         case I915_FORMAT_MOD_X_TILED:
15346                 break;
15347         default:
15348                 return false;
15349         }
15350
15351         switch (format) {
15352         case DRM_FORMAT_C8:
15353         case DRM_FORMAT_RGB565:
15354         case DRM_FORMAT_XRGB1555:
15355         case DRM_FORMAT_XRGB8888:
15356                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15357                         modifier == I915_FORMAT_MOD_X_TILED;
15358         default:
15359                 return false;
15360         }
15361 }
15362
15363 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15364                                             u32 format, u64 modifier)
15365 {
15366         switch (modifier) {
15367         case DRM_FORMAT_MOD_LINEAR:
15368         case I915_FORMAT_MOD_X_TILED:
15369                 break;
15370         default:
15371                 return false;
15372         }
15373
15374         switch (format) {
15375         case DRM_FORMAT_C8:
15376         case DRM_FORMAT_RGB565:
15377         case DRM_FORMAT_XRGB8888:
15378         case DRM_FORMAT_XBGR8888:
15379         case DRM_FORMAT_ARGB8888:
15380         case DRM_FORMAT_ABGR8888:
15381         case DRM_FORMAT_XRGB2101010:
15382         case DRM_FORMAT_XBGR2101010:
15383         case DRM_FORMAT_ARGB2101010:
15384         case DRM_FORMAT_ABGR2101010:
15385         case DRM_FORMAT_XBGR16161616F:
15386                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15387                         modifier == I915_FORMAT_MOD_X_TILED;
15388         default:
15389                 return false;
15390         }
15391 }
15392
15393 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15394                                               u32 format, u64 modifier)
15395 {
15396         return modifier == DRM_FORMAT_MOD_LINEAR &&
15397                 format == DRM_FORMAT_ARGB8888;
15398 }
15399
15400 static const struct drm_plane_funcs i965_plane_funcs = {
15401         .update_plane = drm_atomic_helper_update_plane,
15402         .disable_plane = drm_atomic_helper_disable_plane,
15403         .destroy = intel_plane_destroy,
15404         .atomic_duplicate_state = intel_plane_duplicate_state,
15405         .atomic_destroy_state = intel_plane_destroy_state,
15406         .format_mod_supported = i965_plane_format_mod_supported,
15407 };
15408
15409 static const struct drm_plane_funcs i8xx_plane_funcs = {
15410         .update_plane = drm_atomic_helper_update_plane,
15411         .disable_plane = drm_atomic_helper_disable_plane,
15412         .destroy = intel_plane_destroy,
15413         .atomic_duplicate_state = intel_plane_duplicate_state,
15414         .atomic_destroy_state = intel_plane_destroy_state,
15415         .format_mod_supported = i8xx_plane_format_mod_supported,
15416 };
15417
15418 static int
15419 intel_legacy_cursor_update(struct drm_plane *_plane,
15420                            struct drm_crtc *_crtc,
15421                            struct drm_framebuffer *fb,
15422                            int crtc_x, int crtc_y,
15423                            unsigned int crtc_w, unsigned int crtc_h,
15424                            u32 src_x, u32 src_y,
15425                            u32 src_w, u32 src_h,
15426                            struct drm_modeset_acquire_ctx *ctx)
15427 {
15428         struct intel_plane *plane = to_intel_plane(_plane);
15429         struct intel_crtc *crtc = to_intel_crtc(_crtc);
15430         struct intel_plane_state *old_plane_state =
15431                 to_intel_plane_state(plane->base.state);
15432         struct intel_plane_state *new_plane_state;
15433         struct intel_crtc_state *crtc_state =
15434                 to_intel_crtc_state(crtc->base.state);
15435         struct intel_crtc_state *new_crtc_state;
15436         int ret;
15437
15438         /*
15439          * When crtc is inactive or there is a modeset pending,
15440          * wait for it to complete in the slowpath
15441          */
15442         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
15443             crtc_state->update_pipe)
15444                 goto slow;
15445
15446         /*
15447          * Don't do an async update if there is an outstanding commit modifying
15448          * the plane.  This prevents our async update's changes from getting
15449          * overridden by a previous synchronous update's state.
15450          */
15451         if (old_plane_state->uapi.commit &&
15452             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
15453                 goto slow;
15454
15455         /*
15456          * If any parameters change that may affect watermarks,
15457          * take the slowpath. Only changing fb or position should be
15458          * in the fastpath.
15459          */
15460         if (old_plane_state->uapi.crtc != &crtc->base ||
15461             old_plane_state->uapi.src_w != src_w ||
15462             old_plane_state->uapi.src_h != src_h ||
15463             old_plane_state->uapi.crtc_w != crtc_w ||
15464             old_plane_state->uapi.crtc_h != crtc_h ||
15465             !old_plane_state->uapi.fb != !fb)
15466                 goto slow;
15467
15468         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
15469         if (!new_plane_state)
15470                 return -ENOMEM;
15471
15472         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
15473         if (!new_crtc_state) {
15474                 ret = -ENOMEM;
15475                 goto out_free;
15476         }
15477
15478         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
15479
15480         new_plane_state->uapi.src_x = src_x;
15481         new_plane_state->uapi.src_y = src_y;
15482         new_plane_state->uapi.src_w = src_w;
15483         new_plane_state->uapi.src_h = src_h;
15484         new_plane_state->uapi.crtc_x = crtc_x;
15485         new_plane_state->uapi.crtc_y = crtc_y;
15486         new_plane_state->uapi.crtc_w = crtc_w;
15487         new_plane_state->uapi.crtc_h = crtc_h;
15488
15489         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
15490                                                   old_plane_state, new_plane_state);
15491         if (ret)
15492                 goto out_free;
15493
15494         ret = intel_plane_pin_fb(new_plane_state);
15495         if (ret)
15496                 goto out_free;
15497
15498         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
15499                                 ORIGIN_FLIP);
15500         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15501                                 to_intel_frontbuffer(new_plane_state->hw.fb),
15502                                 plane->frontbuffer_bit);
15503
15504         /* Swap plane state */
15505         plane->base.state = &new_plane_state->uapi;
15506
15507         /*
15508          * We cannot swap crtc_state as it may be in use by an atomic commit or
15509          * page flip that's running simultaneously. If we swap crtc_state and
15510          * destroy the old state, we will cause a use-after-free there.
15511          *
15512          * Only update active_planes, which is needed for our internal
15513          * bookkeeping. Either value will do the right thing when updating
15514          * planes atomically. If the cursor was part of the atomic update then
15515          * we would have taken the slowpath.
15516          */
15517         crtc_state->active_planes = new_crtc_state->active_planes;
15518
15519         if (new_plane_state->uapi.visible)
15520                 intel_update_plane(plane, crtc_state, new_plane_state);
15521         else
15522                 intel_disable_plane(plane, crtc_state);
15523
15524         intel_plane_unpin_fb(old_plane_state);
15525
15526 out_free:
15527         if (new_crtc_state)
15528                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
15529         if (ret)
15530                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
15531         else
15532                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
15533         return ret;
15534
15535 slow:
15536         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
15537                                               crtc_x, crtc_y, crtc_w, crtc_h,
15538                                               src_x, src_y, src_w, src_h, ctx);
15539 }
15540
15541 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15542         .update_plane = intel_legacy_cursor_update,
15543         .disable_plane = drm_atomic_helper_disable_plane,
15544         .destroy = intel_plane_destroy,
15545         .atomic_duplicate_state = intel_plane_duplicate_state,
15546         .atomic_destroy_state = intel_plane_destroy_state,
15547         .format_mod_supported = intel_cursor_format_mod_supported,
15548 };
15549
15550 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
15551                                enum i9xx_plane_id i9xx_plane)
15552 {
15553         if (!HAS_FBC(dev_priv))
15554                 return false;
15555
15556         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15557                 return i9xx_plane == PLANE_A; /* tied to pipe A */
15558         else if (IS_IVYBRIDGE(dev_priv))
15559                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
15560                         i9xx_plane == PLANE_C;
15561         else if (INTEL_GEN(dev_priv) >= 4)
15562                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
15563         else
15564                 return i9xx_plane == PLANE_A;
15565 }
15566
15567 static struct intel_plane *
15568 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15569 {
15570         struct intel_plane *plane;
15571         const struct drm_plane_funcs *plane_funcs;
15572         unsigned int supported_rotations;
15573         unsigned int possible_crtcs;
15574         const u32 *formats;
15575         int num_formats;
15576         int ret, zpos;
15577
15578         if (INTEL_GEN(dev_priv) >= 9)
15579                 return skl_universal_plane_create(dev_priv, pipe,
15580                                                   PLANE_PRIMARY);
15581
15582         plane = intel_plane_alloc();
15583         if (IS_ERR(plane))
15584                 return plane;
15585
15586         plane->pipe = pipe;
15587         /*
15588          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15589          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15590          */
15591         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15592                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
15593         else
15594                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
15595         plane->id = PLANE_PRIMARY;
15596         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
15597
15598         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
15599         if (plane->has_fbc) {
15600                 struct intel_fbc *fbc = &dev_priv->fbc;
15601
15602                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
15603         }
15604
15605         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15606                 formats = vlv_primary_formats;
15607                 num_formats = ARRAY_SIZE(vlv_primary_formats);
15608         } else if (INTEL_GEN(dev_priv) >= 4) {
15609                 /*
15610                  * WaFP16GammaEnabling:ivb
15611                  * "Workaround : When using the 64-bit format, the plane
15612                  *  output on each color channel has one quarter amplitude.
15613                  *  It can be brought up to full amplitude by using pipe
15614                  *  gamma correction or pipe color space conversion to
15615                  *  multiply the plane output by four."
15616                  *
15617                  * There is no dedicated plane gamma for the primary plane,
15618                  * and using the pipe gamma/csc could conflict with other
15619                  * planes, so we choose not to expose fp16 on IVB primary
15620                  * planes. HSW primary planes no longer have this problem.
15621                  */
15622                 if (IS_IVYBRIDGE(dev_priv)) {
15623                         formats = ivb_primary_formats;
15624                         num_formats = ARRAY_SIZE(ivb_primary_formats);
15625                 } else {
15626                         formats = i965_primary_formats;
15627                         num_formats = ARRAY_SIZE(i965_primary_formats);
15628                 }
15629         } else {
15630                 formats = i8xx_primary_formats;
15631                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15632         }
15633
15634         if (INTEL_GEN(dev_priv) >= 4)
15635                 plane_funcs = &i965_plane_funcs;
15636         else
15637                 plane_funcs = &i8xx_plane_funcs;
15638
15639         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15640                 plane->min_cdclk = vlv_plane_min_cdclk;
15641         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15642                 plane->min_cdclk = hsw_plane_min_cdclk;
15643         else if (IS_IVYBRIDGE(dev_priv))
15644                 plane->min_cdclk = ivb_plane_min_cdclk;
15645         else
15646                 plane->min_cdclk = i9xx_plane_min_cdclk;
15647
15648         plane->max_stride = i9xx_plane_max_stride;
15649         plane->update_plane = i9xx_update_plane;
15650         plane->disable_plane = i9xx_disable_plane;
15651         plane->get_hw_state = i9xx_plane_get_hw_state;
15652         plane->check_plane = i9xx_plane_check;
15653
15654         possible_crtcs = BIT(pipe);
15655
15656         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15657                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15658                                                possible_crtcs, plane_funcs,
15659                                                formats, num_formats,
15660                                                i9xx_format_modifiers,
15661                                                DRM_PLANE_TYPE_PRIMARY,
15662                                                "primary %c", pipe_name(pipe));
15663         else
15664                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15665                                                possible_crtcs, plane_funcs,
15666                                                formats, num_formats,
15667                                                i9xx_format_modifiers,
15668                                                DRM_PLANE_TYPE_PRIMARY,
15669                                                "plane %c",
15670                                                plane_name(plane->i9xx_plane));
15671         if (ret)
15672                 goto fail;
15673
15674         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15675                 supported_rotations =
15676                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
15677                         DRM_MODE_REFLECT_X;
15678         } else if (INTEL_GEN(dev_priv) >= 4) {
15679                 supported_rotations =
15680                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
15681         } else {
15682                 supported_rotations = DRM_MODE_ROTATE_0;
15683         }
15684
15685         if (INTEL_GEN(dev_priv) >= 4)
15686                 drm_plane_create_rotation_property(&plane->base,
15687                                                    DRM_MODE_ROTATE_0,
15688                                                    supported_rotations);
15689
15690         zpos = 0;
15691         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
15692
15693         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
15694
15695         return plane;
15696
15697 fail:
15698         intel_plane_free(plane);
15699
15700         return ERR_PTR(ret);
15701 }
15702
15703 static struct intel_plane *
15704 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
15705                           enum pipe pipe)
15706 {
15707         unsigned int possible_crtcs;
15708         struct intel_plane *cursor;
15709         int ret, zpos;
15710
15711         cursor = intel_plane_alloc();
15712         if (IS_ERR(cursor))
15713                 return cursor;
15714
15715         cursor->pipe = pipe;
15716         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15717         cursor->id = PLANE_CURSOR;
15718         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15719
15720         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15721                 cursor->max_stride = i845_cursor_max_stride;
15722                 cursor->update_plane = i845_update_cursor;
15723                 cursor->disable_plane = i845_disable_cursor;
15724                 cursor->get_hw_state = i845_cursor_get_hw_state;
15725                 cursor->check_plane = i845_check_cursor;
15726         } else {
15727                 cursor->max_stride = i9xx_cursor_max_stride;
15728                 cursor->update_plane = i9xx_update_cursor;
15729                 cursor->disable_plane = i9xx_disable_cursor;
15730                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15731                 cursor->check_plane = i9xx_check_cursor;
15732         }
15733
15734         cursor->cursor.base = ~0;
15735         cursor->cursor.cntl = ~0;
15736
15737         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15738                 cursor->cursor.size = ~0;
15739
15740         possible_crtcs = BIT(pipe);
15741
15742         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15743                                        possible_crtcs, &intel_cursor_plane_funcs,
15744                                        intel_cursor_formats,
15745                                        ARRAY_SIZE(intel_cursor_formats),
15746                                        cursor_format_modifiers,
15747                                        DRM_PLANE_TYPE_CURSOR,
15748                                        "cursor %c", pipe_name(pipe));
15749         if (ret)
15750                 goto fail;
15751
15752         if (INTEL_GEN(dev_priv) >= 4)
15753                 drm_plane_create_rotation_property(&cursor->base,
15754                                                    DRM_MODE_ROTATE_0,
15755                                                    DRM_MODE_ROTATE_0 |
15756                                                    DRM_MODE_ROTATE_180);
15757
15758         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15759         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15760
15761         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15762
15763         return cursor;
15764
15765 fail:
15766         intel_plane_free(cursor);
15767
15768         return ERR_PTR(ret);
15769 }
15770
15771 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15772                                     struct intel_crtc_state *crtc_state)
15773 {
15774         struct intel_crtc_scaler_state *scaler_state =
15775                 &crtc_state->scaler_state;
15776         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15777         int i;
15778
15779         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
15780         if (!crtc->num_scalers)
15781                 return;
15782
15783         for (i = 0; i < crtc->num_scalers; i++) {
15784                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15785
15786                 scaler->in_use = 0;
15787                 scaler->mode = 0;
15788         }
15789
15790         scaler_state->scaler_id = -1;
15791 }
15792
15793 #define INTEL_CRTC_FUNCS \
15794         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15795         .set_config = drm_atomic_helper_set_config, \
15796         .destroy = intel_crtc_destroy, \
15797         .page_flip = drm_atomic_helper_page_flip, \
15798         .atomic_duplicate_state = intel_crtc_duplicate_state, \
15799         .atomic_destroy_state = intel_crtc_destroy_state, \
15800         .set_crc_source = intel_crtc_set_crc_source, \
15801         .verify_crc_source = intel_crtc_verify_crc_source, \
15802         .get_crc_sources = intel_crtc_get_crc_sources
15803
15804 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15805         INTEL_CRTC_FUNCS,
15806
15807         .get_vblank_counter = g4x_get_vblank_counter,
15808         .enable_vblank = bdw_enable_vblank,
15809         .disable_vblank = bdw_disable_vblank,
15810 };
15811
15812 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15813         INTEL_CRTC_FUNCS,
15814
15815         .get_vblank_counter = g4x_get_vblank_counter,
15816         .enable_vblank = ilk_enable_vblank,
15817         .disable_vblank = ilk_disable_vblank,
15818 };
15819
15820 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15821         INTEL_CRTC_FUNCS,
15822
15823         .get_vblank_counter = g4x_get_vblank_counter,
15824         .enable_vblank = i965_enable_vblank,
15825         .disable_vblank = i965_disable_vblank,
15826 };
15827
15828 static const struct drm_crtc_funcs i965_crtc_funcs = {
15829         INTEL_CRTC_FUNCS,
15830
15831         .get_vblank_counter = i915_get_vblank_counter,
15832         .enable_vblank = i965_enable_vblank,
15833         .disable_vblank = i965_disable_vblank,
15834 };
15835
15836 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
15837         INTEL_CRTC_FUNCS,
15838
15839         .get_vblank_counter = i915_get_vblank_counter,
15840         .enable_vblank = i915gm_enable_vblank,
15841         .disable_vblank = i915gm_disable_vblank,
15842 };
15843
15844 static const struct drm_crtc_funcs i915_crtc_funcs = {
15845         INTEL_CRTC_FUNCS,
15846
15847         .get_vblank_counter = i915_get_vblank_counter,
15848         .enable_vblank = i8xx_enable_vblank,
15849         .disable_vblank = i8xx_disable_vblank,
15850 };
15851
15852 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15853         INTEL_CRTC_FUNCS,
15854
15855         /* no hw vblank counter */
15856         .enable_vblank = i8xx_enable_vblank,
15857         .disable_vblank = i8xx_disable_vblank,
15858 };
15859
15860 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15861 {
15862         const struct drm_crtc_funcs *funcs;
15863         struct intel_crtc *intel_crtc;
15864         struct intel_crtc_state *crtc_state = NULL;
15865         struct intel_plane *primary = NULL;
15866         struct intel_plane *cursor = NULL;
15867         int sprite, ret;
15868
15869         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15870         if (!intel_crtc)
15871                 return -ENOMEM;
15872
15873         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15874         if (!crtc_state) {
15875                 ret = -ENOMEM;
15876                 goto fail;
15877         }
15878         __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
15879         intel_crtc->config = crtc_state;
15880
15881         primary = intel_primary_plane_create(dev_priv, pipe);
15882         if (IS_ERR(primary)) {
15883                 ret = PTR_ERR(primary);
15884                 goto fail;
15885         }
15886         intel_crtc->plane_ids_mask |= BIT(primary->id);
15887
15888         for_each_sprite(dev_priv, pipe, sprite) {
15889                 struct intel_plane *plane;
15890
15891                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15892                 if (IS_ERR(plane)) {
15893                         ret = PTR_ERR(plane);
15894                         goto fail;
15895                 }
15896                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15897         }
15898
15899         cursor = intel_cursor_plane_create(dev_priv, pipe);
15900         if (IS_ERR(cursor)) {
15901                 ret = PTR_ERR(cursor);
15902                 goto fail;
15903         }
15904         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15905
15906         if (HAS_GMCH(dev_priv)) {
15907                 if (IS_CHERRYVIEW(dev_priv) ||
15908                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15909                         funcs = &g4x_crtc_funcs;
15910                 else if (IS_GEN(dev_priv, 4))
15911                         funcs = &i965_crtc_funcs;
15912                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
15913                         funcs = &i915gm_crtc_funcs;
15914                 else if (IS_GEN(dev_priv, 3))
15915                         funcs = &i915_crtc_funcs;
15916                 else
15917                         funcs = &i8xx_crtc_funcs;
15918         } else {
15919                 if (INTEL_GEN(dev_priv) >= 8)
15920                         funcs = &bdw_crtc_funcs;
15921                 else
15922                         funcs = &ilk_crtc_funcs;
15923         }
15924
15925         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15926                                         &primary->base, &cursor->base,
15927                                         funcs, "pipe %c", pipe_name(pipe));
15928         if (ret)
15929                 goto fail;
15930
15931         intel_crtc->pipe = pipe;
15932
15933         /* initialize shared scalers */
15934         intel_crtc_init_scalers(intel_crtc, crtc_state);
15935
15936         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15937                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15938         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
15939
15940         if (INTEL_GEN(dev_priv) < 9) {
15941                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15942
15943                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15944                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15945                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
15946         }
15947
15948         intel_color_init(intel_crtc);
15949
15950         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15951
15952         return 0;
15953
15954 fail:
15955         /*
15956          * drm_mode_config_cleanup() will free up any
15957          * crtcs/planes already initialized.
15958          */
15959         kfree(crtc_state);
15960         kfree(intel_crtc);
15961
15962         return ret;
15963 }
15964
15965 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15966                                       struct drm_file *file)
15967 {
15968         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15969         struct drm_crtc *drmmode_crtc;
15970         struct intel_crtc *crtc;
15971
15972         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15973         if (!drmmode_crtc)
15974                 return -ENOENT;
15975
15976         crtc = to_intel_crtc(drmmode_crtc);
15977         pipe_from_crtc_id->pipe = crtc->pipe;
15978
15979         return 0;
15980 }
15981
15982 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
15983 {
15984         struct drm_device *dev = encoder->base.dev;
15985         struct intel_encoder *source_encoder;
15986         u32 possible_clones = 0;
15987
15988         for_each_intel_encoder(dev, source_encoder) {
15989                 if (encoders_cloneable(encoder, source_encoder))
15990                         possible_clones |= drm_encoder_mask(&source_encoder->base);
15991         }
15992
15993         return possible_clones;
15994 }
15995
15996 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
15997 {
15998         struct drm_device *dev = encoder->base.dev;
15999         struct intel_crtc *crtc;
16000         u32 possible_crtcs = 0;
16001
16002         for_each_intel_crtc(dev, crtc) {
16003                 if (encoder->pipe_mask & BIT(crtc->pipe))
16004                         possible_crtcs |= drm_crtc_mask(&crtc->base);
16005         }
16006
16007         return possible_crtcs;
16008 }
16009
16010 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16011 {
16012         if (!IS_MOBILE(dev_priv))
16013                 return false;
16014
16015         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
16016                 return false;
16017
16018         if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
16019                 return false;
16020
16021         return true;
16022 }
16023
16024 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16025 {
16026         if (INTEL_GEN(dev_priv) >= 9)
16027                 return false;
16028
16029         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16030                 return false;
16031
16032         if (HAS_PCH_LPT_H(dev_priv) &&
16033             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16034                 return false;
16035
16036         /* DDI E can't be used if DDI A requires 4 lanes */
16037         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16038                 return false;
16039
16040         if (!dev_priv->vbt.int_crt_support)
16041                 return false;
16042
16043         return true;
16044 }
16045
16046 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16047 {
16048         int pps_num;
16049         int pps_idx;
16050
16051         if (HAS_DDI(dev_priv))
16052                 return;
16053         /*
16054          * This w/a is needed at least on CPT/PPT, but to be sure apply it
16055          * everywhere where registers can be write protected.
16056          */
16057         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16058                 pps_num = 2;
16059         else
16060                 pps_num = 1;
16061
16062         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16063                 u32 val = I915_READ(PP_CONTROL(pps_idx));
16064
16065                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16066                 I915_WRITE(PP_CONTROL(pps_idx), val);
16067         }
16068 }
16069
16070 static void intel_pps_init(struct drm_i915_private *dev_priv)
16071 {
16072         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16073                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16074         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16075                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16076         else
16077                 dev_priv->pps_mmio_base = PPS_BASE;
16078
16079         intel_pps_unlock_regs_wa(dev_priv);
16080 }
16081
16082 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16083 {
16084         struct intel_encoder *encoder;
16085         bool dpd_is_edp = false;
16086
16087         intel_pps_init(dev_priv);
16088
16089         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16090                 return;
16091
16092         if (INTEL_GEN(dev_priv) >= 12) {
16093                 intel_ddi_init(dev_priv, PORT_A);
16094                 intel_ddi_init(dev_priv, PORT_B);
16095                 intel_ddi_init(dev_priv, PORT_D);
16096                 intel_ddi_init(dev_priv, PORT_E);
16097                 intel_ddi_init(dev_priv, PORT_F);
16098                 intel_ddi_init(dev_priv, PORT_G);
16099                 intel_ddi_init(dev_priv, PORT_H);
16100                 intel_ddi_init(dev_priv, PORT_I);
16101                 icl_dsi_init(dev_priv);
16102         } else if (IS_ELKHARTLAKE(dev_priv)) {
16103                 intel_ddi_init(dev_priv, PORT_A);
16104                 intel_ddi_init(dev_priv, PORT_B);
16105                 intel_ddi_init(dev_priv, PORT_C);
16106                 intel_ddi_init(dev_priv, PORT_D);
16107                 icl_dsi_init(dev_priv);
16108         } else if (IS_GEN(dev_priv, 11)) {
16109                 intel_ddi_init(dev_priv, PORT_A);
16110                 intel_ddi_init(dev_priv, PORT_B);
16111                 intel_ddi_init(dev_priv, PORT_C);
16112                 intel_ddi_init(dev_priv, PORT_D);
16113                 intel_ddi_init(dev_priv, PORT_E);
16114                 /*
16115                  * On some ICL SKUs port F is not present. No strap bits for
16116                  * this, so rely on VBT.
16117                  * Work around broken VBTs on SKUs known to have no port F.
16118                  */
16119                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16120                     intel_bios_is_port_present(dev_priv, PORT_F))
16121                         intel_ddi_init(dev_priv, PORT_F);
16122
16123                 icl_dsi_init(dev_priv);
16124         } else if (IS_GEN9_LP(dev_priv)) {
16125                 /*
16126                  * FIXME: Broxton doesn't support port detection via the
16127                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16128                  * detect the ports.
16129                  */
16130                 intel_ddi_init(dev_priv, PORT_A);
16131                 intel_ddi_init(dev_priv, PORT_B);
16132                 intel_ddi_init(dev_priv, PORT_C);
16133
16134                 vlv_dsi_init(dev_priv);
16135         } else if (HAS_DDI(dev_priv)) {
16136                 int found;
16137
16138                 if (intel_ddi_crt_present(dev_priv))
16139                         intel_crt_init(dev_priv);
16140
16141                 /*
16142                  * Haswell uses DDI functions to detect digital outputs.
16143                  * On SKL pre-D0 the strap isn't connected, so we assume
16144                  * it's there.
16145                  */
16146                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16147                 /* WaIgnoreDDIAStrap: skl */
16148                 if (found || IS_GEN9_BC(dev_priv))
16149                         intel_ddi_init(dev_priv, PORT_A);
16150
16151                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16152                  * register */
16153                 found = I915_READ(SFUSE_STRAP);
16154
16155                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16156                         intel_ddi_init(dev_priv, PORT_B);
16157                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16158                         intel_ddi_init(dev_priv, PORT_C);
16159                 if (found & SFUSE_STRAP_DDID_DETECTED)
16160                         intel_ddi_init(dev_priv, PORT_D);
16161                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16162                         intel_ddi_init(dev_priv, PORT_F);
16163                 /*
16164                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16165                  */
16166                 if (IS_GEN9_BC(dev_priv) &&
16167                     intel_bios_is_port_present(dev_priv, PORT_E))
16168                         intel_ddi_init(dev_priv, PORT_E);
16169
16170         } else if (HAS_PCH_SPLIT(dev_priv)) {
16171                 int found;
16172
16173                 /*
16174                  * intel_edp_init_connector() depends on this completing first,
16175                  * to prevent the registration of both eDP and LVDS and the
16176                  * incorrect sharing of the PPS.
16177                  */
16178                 intel_lvds_init(dev_priv);
16179                 intel_crt_init(dev_priv);
16180
16181                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16182
16183                 if (ilk_has_edp_a(dev_priv))
16184                         intel_dp_init(dev_priv, DP_A, PORT_A);
16185
16186                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
16187                         /* PCH SDVOB multiplex with HDMIB */
16188                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16189                         if (!found)
16190                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16191                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
16192                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16193                 }
16194
16195                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
16196                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16197
16198                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
16199                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16200
16201                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
16202                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16203
16204                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
16205                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16206         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16207                 bool has_edp, has_port;
16208
16209                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16210                         intel_crt_init(dev_priv);
16211
16212                 /*
16213                  * The DP_DETECTED bit is the latched state of the DDC
16214                  * SDA pin at boot. However since eDP doesn't require DDC
16215                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16216                  * eDP ports may have been muxed to an alternate function.
16217                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16218                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16219                  * detect eDP ports.
16220                  *
16221                  * Sadly the straps seem to be missing sometimes even for HDMI
16222                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16223                  * and VBT for the presence of the port. Additionally we can't
16224                  * trust the port type the VBT declares as we've seen at least
16225                  * HDMI ports that the VBT claim are DP or eDP.
16226                  */
16227                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16228                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16229                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
16230                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16231                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16232                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16233
16234                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16235                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16236                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
16237                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16238                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16239                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16240
16241                 if (IS_CHERRYVIEW(dev_priv)) {
16242                         /*
16243                          * eDP not supported on port D,
16244                          * so no need to worry about it
16245                          */
16246                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16247                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
16248                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16249                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
16250                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16251                 }
16252
16253                 vlv_dsi_init(dev_priv);
16254         } else if (IS_PINEVIEW(dev_priv)) {
16255                 intel_lvds_init(dev_priv);
16256                 intel_crt_init(dev_priv);
16257         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16258                 bool found = false;
16259
16260                 if (IS_MOBILE(dev_priv))
16261                         intel_lvds_init(dev_priv);
16262
16263                 intel_crt_init(dev_priv);
16264
16265                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16266                         DRM_DEBUG_KMS("probing SDVOB\n");
16267                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16268                         if (!found && IS_G4X(dev_priv)) {
16269                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
16270                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16271                         }
16272
16273                         if (!found && IS_G4X(dev_priv))
16274                                 intel_dp_init(dev_priv, DP_B, PORT_B);
16275                 }
16276
16277                 /* Before G4X SDVOC doesn't have its own detect register */
16278
16279                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16280                         DRM_DEBUG_KMS("probing SDVOC\n");
16281                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16282                 }
16283
16284                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
16285
16286                         if (IS_G4X(dev_priv)) {
16287                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
16288                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16289                         }
16290                         if (IS_G4X(dev_priv))
16291                                 intel_dp_init(dev_priv, DP_C, PORT_C);
16292                 }
16293
16294                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
16295                         intel_dp_init(dev_priv, DP_D, PORT_D);
16296
16297                 if (SUPPORTS_TV(dev_priv))
16298                         intel_tv_init(dev_priv);
16299         } else if (IS_GEN(dev_priv, 2)) {
16300                 if (IS_I85X(dev_priv))
16301                         intel_lvds_init(dev_priv);
16302
16303                 intel_crt_init(dev_priv);
16304                 intel_dvo_init(dev_priv);
16305         }
16306
16307         intel_psr_init(dev_priv);
16308
16309         for_each_intel_encoder(&dev_priv->drm, encoder) {
16310                 encoder->base.possible_crtcs =
16311                         intel_encoder_possible_crtcs(encoder);
16312                 encoder->base.possible_clones =
16313                         intel_encoder_possible_clones(encoder);
16314         }
16315
16316         intel_init_pch_refclk(dev_priv);
16317
16318         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16319 }
16320
16321 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16322 {
16323         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16324
16325         drm_framebuffer_cleanup(fb);
16326         intel_frontbuffer_put(intel_fb->frontbuffer);
16327
16328         kfree(intel_fb);
16329 }
16330
16331 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16332                                                 struct drm_file *file,
16333                                                 unsigned int *handle)
16334 {
16335         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16336
16337         if (obj->userptr.mm) {
16338                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
16339                 return -EINVAL;
16340         }
16341
16342         return drm_gem_handle_create(file, &obj->base, handle);
16343 }
16344
16345 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16346                                         struct drm_file *file,
16347                                         unsigned flags, unsigned color,
16348                                         struct drm_clip_rect *clips,
16349                                         unsigned num_clips)
16350 {
16351         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16352
16353         i915_gem_object_flush_if_display(obj);
16354         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16355
16356         return 0;
16357 }
16358
16359 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16360         .destroy = intel_user_framebuffer_destroy,
16361         .create_handle = intel_user_framebuffer_create_handle,
16362         .dirty = intel_user_framebuffer_dirty,
16363 };
16364
16365 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16366                                   struct drm_i915_gem_object *obj,
16367                                   struct drm_mode_fb_cmd2 *mode_cmd)
16368 {
16369         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16370         struct drm_framebuffer *fb = &intel_fb->base;
16371         u32 max_stride;
16372         unsigned int tiling, stride;
16373         int ret = -EINVAL;
16374         int i;
16375
16376         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16377         if (!intel_fb->frontbuffer)
16378                 return -ENOMEM;
16379
16380         i915_gem_object_lock(obj);
16381         tiling = i915_gem_object_get_tiling(obj);
16382         stride = i915_gem_object_get_stride(obj);
16383         i915_gem_object_unlock(obj);
16384
16385         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16386                 /*
16387                  * If there's a fence, enforce that
16388                  * the fb modifier and tiling mode match.
16389                  */
16390                 if (tiling != I915_TILING_NONE &&
16391                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16392                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
16393                         goto err;
16394                 }
16395         } else {
16396                 if (tiling == I915_TILING_X) {
16397                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16398                 } else if (tiling == I915_TILING_Y) {
16399                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
16400                         goto err;
16401                 }
16402         }
16403
16404         if (!drm_any_plane_has_format(&dev_priv->drm,
16405                                       mode_cmd->pixel_format,
16406                                       mode_cmd->modifier[0])) {
16407                 struct drm_format_name_buf format_name;
16408
16409                 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
16410                               drm_get_format_name(mode_cmd->pixel_format,
16411                                                   &format_name),
16412                               mode_cmd->modifier[0]);
16413                 goto err;
16414         }
16415
16416         /*
16417          * gen2/3 display engine uses the fence if present,
16418          * so the tiling mode must match the fb modifier exactly.
16419          */
16420         if (INTEL_GEN(dev_priv) < 4 &&
16421             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16422                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
16423                 goto err;
16424         }
16425
16426         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
16427                                          mode_cmd->modifier[0]);
16428         if (mode_cmd->pitches[0] > max_stride) {
16429                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
16430                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
16431                               "tiled" : "linear",
16432                               mode_cmd->pitches[0], max_stride);
16433                 goto err;
16434         }
16435
16436         /*
16437          * If there's a fence, enforce that
16438          * the fb pitch and fence stride match.
16439          */
16440         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
16441                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
16442                               mode_cmd->pitches[0], stride);
16443                 goto err;
16444         }
16445
16446         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16447         if (mode_cmd->offsets[0] != 0)
16448                 goto err;
16449
16450         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
16451
16452         for (i = 0; i < fb->format->num_planes; i++) {
16453                 u32 stride_alignment;
16454
16455                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
16456                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
16457                         goto err;
16458                 }
16459
16460                 stride_alignment = intel_fb_stride_alignment(fb, i);
16461
16462                 /*
16463                  * Display WA #0531: skl,bxt,kbl,glk
16464                  *
16465                  * Render decompression and plane width > 3840
16466                  * combined with horizontal panning requires the
16467                  * plane stride to be a multiple of 4. We'll just
16468                  * require the entire fb to accommodate that to avoid
16469                  * potential runtime errors at plane configuration time.
16470                  */
16471                 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
16472                     is_ccs_modifier(fb->modifier))
16473                         stride_alignment *= 4;
16474
16475                 if (fb->pitches[i] & (stride_alignment - 1)) {
16476                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
16477                                       i, fb->pitches[i], stride_alignment);
16478                         goto err;
16479                 }
16480
16481                 fb->obj[i] = &obj->base;
16482         }
16483
16484         ret = intel_fill_fb_info(dev_priv, fb);
16485         if (ret)
16486                 goto err;
16487
16488         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
16489         if (ret) {
16490                 DRM_ERROR("framebuffer init failed %d\n", ret);
16491                 goto err;
16492         }
16493
16494         return 0;
16495
16496 err:
16497         intel_frontbuffer_put(intel_fb->frontbuffer);
16498         return ret;
16499 }
16500
16501 static struct drm_framebuffer *
16502 intel_user_framebuffer_create(struct drm_device *dev,
16503                               struct drm_file *filp,
16504                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16505 {
16506         struct drm_framebuffer *fb;
16507         struct drm_i915_gem_object *obj;
16508         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16509
16510         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16511         if (!obj)
16512                 return ERR_PTR(-ENOENT);
16513
16514         fb = intel_framebuffer_create(obj, &mode_cmd);
16515         i915_gem_object_put(obj);
16516
16517         return fb;
16518 }
16519
16520 static void intel_atomic_state_free(struct drm_atomic_state *state)
16521 {
16522         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16523
16524         drm_atomic_state_default_release(state);
16525
16526         i915_sw_fence_fini(&intel_state->commit_ready);
16527
16528         kfree(state);
16529 }
16530
16531 static enum drm_mode_status
16532 intel_mode_valid(struct drm_device *dev,
16533                  const struct drm_display_mode *mode)
16534 {
16535         struct drm_i915_private *dev_priv = to_i915(dev);
16536         int hdisplay_max, htotal_max;
16537         int vdisplay_max, vtotal_max;
16538
16539         /*
16540          * Can't reject DBLSCAN here because Xorg ddxen can add piles
16541          * of DBLSCAN modes to the output's mode list when they detect
16542          * the scaling mode property on the connector. And they don't
16543          * ask the kernel to validate those modes in any way until
16544          * modeset time at which point the client gets a protocol error.
16545          * So in order to not upset those clients we silently ignore the
16546          * DBLSCAN flag on such connectors. For other connectors we will
16547          * reject modes with the DBLSCAN flag in encoder->compute_config().
16548          * And we always reject DBLSCAN modes in connector->mode_valid()
16549          * as we never want such modes on the connector's mode list.
16550          */
16551
16552         if (mode->vscan > 1)
16553                 return MODE_NO_VSCAN;
16554
16555         if (mode->flags & DRM_MODE_FLAG_HSKEW)
16556                 return MODE_H_ILLEGAL;
16557
16558         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
16559                            DRM_MODE_FLAG_NCSYNC |
16560                            DRM_MODE_FLAG_PCSYNC))
16561                 return MODE_HSYNC;
16562
16563         if (mode->flags & (DRM_MODE_FLAG_BCAST |
16564                            DRM_MODE_FLAG_PIXMUX |
16565                            DRM_MODE_FLAG_CLKDIV2))
16566                 return MODE_BAD;
16567
16568         /* Transcoder timing limits */
16569         if (INTEL_GEN(dev_priv) >= 11) {
16570                 hdisplay_max = 16384;
16571                 vdisplay_max = 8192;
16572                 htotal_max = 16384;
16573                 vtotal_max = 8192;
16574         } else if (INTEL_GEN(dev_priv) >= 9 ||
16575                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
16576                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
16577                 vdisplay_max = 4096;
16578                 htotal_max = 8192;
16579                 vtotal_max = 8192;
16580         } else if (INTEL_GEN(dev_priv) >= 3) {
16581                 hdisplay_max = 4096;
16582                 vdisplay_max = 4096;
16583                 htotal_max = 8192;
16584                 vtotal_max = 8192;
16585         } else {
16586                 hdisplay_max = 2048;
16587                 vdisplay_max = 2048;
16588                 htotal_max = 4096;
16589                 vtotal_max = 4096;
16590         }
16591
16592         if (mode->hdisplay > hdisplay_max ||
16593             mode->hsync_start > htotal_max ||
16594             mode->hsync_end > htotal_max ||
16595             mode->htotal > htotal_max)
16596                 return MODE_H_ILLEGAL;
16597
16598         if (mode->vdisplay > vdisplay_max ||
16599             mode->vsync_start > vtotal_max ||
16600             mode->vsync_end > vtotal_max ||
16601             mode->vtotal > vtotal_max)
16602                 return MODE_V_ILLEGAL;
16603
16604         if (INTEL_GEN(dev_priv) >= 5) {
16605                 if (mode->hdisplay < 64 ||
16606                     mode->htotal - mode->hdisplay < 32)
16607                         return MODE_H_ILLEGAL;
16608
16609                 if (mode->vtotal - mode->vdisplay < 5)
16610                         return MODE_V_ILLEGAL;
16611         } else {
16612                 if (mode->htotal - mode->hdisplay < 32)
16613                         return MODE_H_ILLEGAL;
16614
16615                 if (mode->vtotal - mode->vdisplay < 3)
16616                         return MODE_V_ILLEGAL;
16617         }
16618
16619         return MODE_OK;
16620 }
16621
16622 enum drm_mode_status
16623 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
16624                                 const struct drm_display_mode *mode)
16625 {
16626         int plane_width_max, plane_height_max;
16627
16628         /*
16629          * intel_mode_valid() should be
16630          * sufficient on older platforms.
16631          */
16632         if (INTEL_GEN(dev_priv) < 9)
16633                 return MODE_OK;
16634
16635         /*
16636          * Most people will probably want a fullscreen
16637          * plane so let's not advertize modes that are
16638          * too big for that.
16639          */
16640         if (INTEL_GEN(dev_priv) >= 11) {
16641                 plane_width_max = 5120;
16642                 plane_height_max = 4320;
16643         } else {
16644                 plane_width_max = 5120;
16645                 plane_height_max = 4096;
16646         }
16647
16648         if (mode->hdisplay > plane_width_max)
16649                 return MODE_H_ILLEGAL;
16650
16651         if (mode->vdisplay > plane_height_max)
16652                 return MODE_V_ILLEGAL;
16653
16654         return MODE_OK;
16655 }
16656
16657 static const struct drm_mode_config_funcs intel_mode_funcs = {
16658         .fb_create = intel_user_framebuffer_create,
16659         .get_format_info = intel_get_format_info,
16660         .output_poll_changed = intel_fbdev_output_poll_changed,
16661         .mode_valid = intel_mode_valid,
16662         .atomic_check = intel_atomic_check,
16663         .atomic_commit = intel_atomic_commit,
16664         .atomic_state_alloc = intel_atomic_state_alloc,
16665         .atomic_state_clear = intel_atomic_state_clear,
16666         .atomic_state_free = intel_atomic_state_free,
16667 };
16668
16669 /**
16670  * intel_init_display_hooks - initialize the display modesetting hooks
16671  * @dev_priv: device private
16672  */
16673 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16674 {
16675         intel_init_cdclk_hooks(dev_priv);
16676
16677         if (INTEL_GEN(dev_priv) >= 9) {
16678                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16679                 dev_priv->display.get_initial_plane_config =
16680                         skylake_get_initial_plane_config;
16681                 dev_priv->display.crtc_compute_clock =
16682                         haswell_crtc_compute_clock;
16683                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16684                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16685         } else if (HAS_DDI(dev_priv)) {
16686                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16687                 dev_priv->display.get_initial_plane_config =
16688                         i9xx_get_initial_plane_config;
16689                 dev_priv->display.crtc_compute_clock =
16690                         haswell_crtc_compute_clock;
16691                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16692                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16693         } else if (HAS_PCH_SPLIT(dev_priv)) {
16694                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16695                 dev_priv->display.get_initial_plane_config =
16696                         i9xx_get_initial_plane_config;
16697                 dev_priv->display.crtc_compute_clock =
16698                         ironlake_crtc_compute_clock;
16699                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16700                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16701         } else if (IS_CHERRYVIEW(dev_priv)) {
16702                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16703                 dev_priv->display.get_initial_plane_config =
16704                         i9xx_get_initial_plane_config;
16705                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16706                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16707                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16708         } else if (IS_VALLEYVIEW(dev_priv)) {
16709                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16710                 dev_priv->display.get_initial_plane_config =
16711                         i9xx_get_initial_plane_config;
16712                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16713                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16714                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16715         } else if (IS_G4X(dev_priv)) {
16716                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16717                 dev_priv->display.get_initial_plane_config =
16718                         i9xx_get_initial_plane_config;
16719                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16720                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16721                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16722         } else if (IS_PINEVIEW(dev_priv)) {
16723                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16724                 dev_priv->display.get_initial_plane_config =
16725                         i9xx_get_initial_plane_config;
16726                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16727                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16728                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16729         } else if (!IS_GEN(dev_priv, 2)) {
16730                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16731                 dev_priv->display.get_initial_plane_config =
16732                         i9xx_get_initial_plane_config;
16733                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16734                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16735                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16736         } else {
16737                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16738                 dev_priv->display.get_initial_plane_config =
16739                         i9xx_get_initial_plane_config;
16740                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16741                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16742                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16743         }
16744
16745         if (IS_GEN(dev_priv, 5)) {
16746                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16747         } else if (IS_GEN(dev_priv, 6)) {
16748                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16749         } else if (IS_IVYBRIDGE(dev_priv)) {
16750                 /* FIXME: detect B0+ stepping and use auto training */
16751                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16752         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16753                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16754         }
16755
16756         if (INTEL_GEN(dev_priv) >= 9)
16757                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
16758         else
16759                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
16760
16761 }
16762
16763 void intel_modeset_init_hw(struct drm_i915_private *i915)
16764 {
16765         intel_update_cdclk(i915);
16766         intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
16767         i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
16768 }
16769
16770 /*
16771  * Calculate what we think the watermarks should be for the state we've read
16772  * out of the hardware and then immediately program those watermarks so that
16773  * we ensure the hardware settings match our internal state.
16774  *
16775  * We can calculate what we think WM's should be by creating a duplicate of the
16776  * current state (which was constructed during hardware readout) and running it
16777  * through the atomic check code to calculate new watermark values in the
16778  * state object.
16779  */
16780 static void sanitize_watermarks(struct drm_device *dev)
16781 {
16782         struct drm_i915_private *dev_priv = to_i915(dev);
16783         struct drm_atomic_state *state;
16784         struct intel_atomic_state *intel_state;
16785         struct intel_crtc *crtc;
16786         struct intel_crtc_state *crtc_state;
16787         struct drm_modeset_acquire_ctx ctx;
16788         int ret;
16789         int i;
16790
16791         /* Only supported on platforms that use atomic watermark design */
16792         if (!dev_priv->display.optimize_watermarks)
16793                 return;
16794
16795         /*
16796          * We need to hold connection_mutex before calling duplicate_state so
16797          * that the connector loop is protected.
16798          */
16799         drm_modeset_acquire_init(&ctx, 0);
16800 retry:
16801         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16802         if (ret == -EDEADLK) {
16803                 drm_modeset_backoff(&ctx);
16804                 goto retry;
16805         } else if (WARN_ON(ret)) {
16806                 goto fail;
16807         }
16808
16809         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16810         if (WARN_ON(IS_ERR(state)))
16811                 goto fail;
16812
16813         intel_state = to_intel_atomic_state(state);
16814
16815         /*
16816          * Hardware readout is the only time we don't want to calculate
16817          * intermediate watermarks (since we don't trust the current
16818          * watermarks).
16819          */
16820         if (!HAS_GMCH(dev_priv))
16821                 intel_state->skip_intermediate_wm = true;
16822
16823         ret = intel_atomic_check(dev, state);
16824         if (ret) {
16825                 /*
16826                  * If we fail here, it means that the hardware appears to be
16827                  * programmed in a way that shouldn't be possible, given our
16828                  * understanding of watermark requirements.  This might mean a
16829                  * mistake in the hardware readout code or a mistake in the
16830                  * watermark calculations for a given platform.  Raise a WARN
16831                  * so that this is noticeable.
16832                  *
16833                  * If this actually happens, we'll have to just leave the
16834                  * BIOS-programmed watermarks untouched and hope for the best.
16835                  */
16836                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16837                 goto put_state;
16838         }
16839
16840         /* Write calculated watermark values back */
16841         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16842                 crtc_state->wm.need_postvbl_update = true;
16843                 dev_priv->display.optimize_watermarks(intel_state, crtc);
16844
16845                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16846         }
16847
16848 put_state:
16849         drm_atomic_state_put(state);
16850 fail:
16851         drm_modeset_drop_locks(&ctx);
16852         drm_modeset_acquire_fini(&ctx);
16853 }
16854
16855 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16856 {
16857         if (IS_GEN(dev_priv, 5)) {
16858                 u32 fdi_pll_clk =
16859                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16860
16861                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16862         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16863                 dev_priv->fdi_pll_freq = 270000;
16864         } else {
16865                 return;
16866         }
16867
16868         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16869 }
16870
16871 static int intel_initial_commit(struct drm_device *dev)
16872 {
16873         struct drm_atomic_state *state = NULL;
16874         struct drm_modeset_acquire_ctx ctx;
16875         struct intel_crtc *crtc;
16876         int ret = 0;
16877
16878         state = drm_atomic_state_alloc(dev);
16879         if (!state)
16880                 return -ENOMEM;
16881
16882         drm_modeset_acquire_init(&ctx, 0);
16883
16884 retry:
16885         state->acquire_ctx = &ctx;
16886
16887         for_each_intel_crtc(dev, crtc) {
16888                 struct intel_crtc_state *crtc_state =
16889                         intel_atomic_get_crtc_state(state, crtc);
16890
16891                 if (IS_ERR(crtc_state)) {
16892                         ret = PTR_ERR(crtc_state);
16893                         goto out;
16894                 }
16895
16896                 if (crtc_state->hw.active) {
16897                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
16898                         if (ret)
16899                                 goto out;
16900
16901                         /*
16902                          * FIXME hack to force a LUT update to avoid the
16903                          * plane update forcing the pipe gamma on without
16904                          * having a proper LUT loaded. Remove once we
16905                          * have readout for pipe gamma enable.
16906                          */
16907                         crtc_state->uapi.color_mgmt_changed = true;
16908                 }
16909         }
16910
16911         ret = drm_atomic_commit(state);
16912
16913 out:
16914         if (ret == -EDEADLK) {
16915                 drm_atomic_state_clear(state);
16916                 drm_modeset_backoff(&ctx);
16917                 goto retry;
16918         }
16919
16920         drm_atomic_state_put(state);
16921
16922         drm_modeset_drop_locks(&ctx);
16923         drm_modeset_acquire_fini(&ctx);
16924
16925         return ret;
16926 }
16927
16928 static void intel_mode_config_init(struct drm_i915_private *i915)
16929 {
16930         struct drm_mode_config *mode_config = &i915->drm.mode_config;
16931
16932         drm_mode_config_init(&i915->drm);
16933
16934         mode_config->min_width = 0;
16935         mode_config->min_height = 0;
16936
16937         mode_config->preferred_depth = 24;
16938         mode_config->prefer_shadow = 1;
16939
16940         mode_config->allow_fb_modifiers = true;
16941
16942         mode_config->funcs = &intel_mode_funcs;
16943
16944         /*
16945          * Maximum framebuffer dimensions, chosen to match
16946          * the maximum render engine surface size on gen4+.
16947          */
16948         if (INTEL_GEN(i915) >= 7) {
16949                 mode_config->max_width = 16384;
16950                 mode_config->max_height = 16384;
16951         } else if (INTEL_GEN(i915) >= 4) {
16952                 mode_config->max_width = 8192;
16953                 mode_config->max_height = 8192;
16954         } else if (IS_GEN(i915, 3)) {
16955                 mode_config->max_width = 4096;
16956                 mode_config->max_height = 4096;
16957         } else {
16958                 mode_config->max_width = 2048;
16959                 mode_config->max_height = 2048;
16960         }
16961
16962         if (IS_I845G(i915) || IS_I865G(i915)) {
16963                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
16964                 mode_config->cursor_height = 1023;
16965         } else if (IS_GEN(i915, 2)) {
16966                 mode_config->cursor_width = 64;
16967                 mode_config->cursor_height = 64;
16968         } else {
16969                 mode_config->cursor_width = 256;
16970                 mode_config->cursor_height = 256;
16971         }
16972 }
16973
16974 int intel_modeset_init(struct drm_i915_private *i915)
16975 {
16976         struct drm_device *dev = &i915->drm;
16977         enum pipe pipe;
16978         struct intel_crtc *crtc;
16979         int ret;
16980
16981         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16982         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16983                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16984
16985         intel_mode_config_init(i915);
16986
16987         ret = intel_bw_init(i915);
16988         if (ret)
16989                 return ret;
16990
16991         init_llist_head(&i915->atomic_helper.free_list);
16992         INIT_WORK(&i915->atomic_helper.free_work,
16993                   intel_atomic_helper_free_state_worker);
16994
16995         intel_init_quirks(i915);
16996
16997         intel_fbc_init(i915);
16998
16999         intel_init_pm(i915);
17000
17001         intel_panel_sanitize_ssc(i915);
17002
17003         intel_gmbus_setup(i915);
17004
17005         DRM_DEBUG_KMS("%d display pipe%s available.\n",
17006                       INTEL_NUM_PIPES(i915),
17007                       INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17008
17009         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
17010                 for_each_pipe(i915, pipe) {
17011                         ret = intel_crtc_init(i915, pipe);
17012                         if (ret) {
17013                                 drm_mode_config_cleanup(dev);
17014                                 return ret;
17015                         }
17016                 }
17017         }
17018
17019         intel_shared_dpll_init(dev);
17020         intel_update_fdi_pll_freq(i915);
17021
17022         intel_update_czclk(i915);
17023         intel_modeset_init_hw(i915);
17024
17025         intel_hdcp_component_init(i915);
17026
17027         if (i915->max_cdclk_freq == 0)
17028                 intel_update_max_cdclk(i915);
17029
17030         /* Just disable it once at startup */
17031         intel_vga_disable(i915);
17032         intel_setup_outputs(i915);
17033
17034         drm_modeset_lock_all(dev);
17035         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17036         drm_modeset_unlock_all(dev);
17037
17038         for_each_intel_crtc(dev, crtc) {
17039                 struct intel_initial_plane_config plane_config = {};
17040
17041                 if (!crtc->active)
17042                         continue;
17043
17044                 /*
17045                  * Note that reserving the BIOS fb up front prevents us
17046                  * from stuffing other stolen allocations like the ring
17047                  * on top.  This prevents some ugliness at boot time, and
17048                  * can even allow for smooth boot transitions if the BIOS
17049                  * fb is large enough for the active pipe configuration.
17050                  */
17051                 i915->display.get_initial_plane_config(crtc, &plane_config);
17052
17053                 /*
17054                  * If the fb is shared between multiple heads, we'll
17055                  * just get the first one.
17056                  */
17057                 intel_find_initial_plane_obj(crtc, &plane_config);
17058         }
17059
17060         /*
17061          * Make sure hardware watermarks really match the state we read out.
17062          * Note that we need to do this after reconstructing the BIOS fb's
17063          * since the watermark calculation done here will use pstate->fb.
17064          */
17065         if (!HAS_GMCH(i915))
17066                 sanitize_watermarks(dev);
17067
17068         /*
17069          * Force all active planes to recompute their states. So that on
17070          * mode_setcrtc after probe, all the intel_plane_state variables
17071          * are already calculated and there is no assert_plane warnings
17072          * during bootup.
17073          */
17074         ret = intel_initial_commit(dev);
17075         if (ret)
17076                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
17077
17078         return 0;
17079 }
17080
17081 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17082 {
17083         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17084         /* 640x480@60Hz, ~25175 kHz */
17085         struct dpll clock = {
17086                 .m1 = 18,
17087                 .m2 = 7,
17088                 .p1 = 13,
17089                 .p2 = 4,
17090                 .n = 2,
17091         };
17092         u32 dpll, fp;
17093         int i;
17094
17095         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
17096
17097         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17098                       pipe_name(pipe), clock.vco, clock.dot);
17099
17100         fp = i9xx_dpll_compute_fp(&clock);
17101         dpll = DPLL_DVO_2X_MODE |
17102                 DPLL_VGA_MODE_DIS |
17103                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17104                 PLL_P2_DIVIDE_BY_4 |
17105                 PLL_REF_INPUT_DREFCLK |
17106                 DPLL_VCO_ENABLE;
17107
17108         I915_WRITE(FP0(pipe), fp);
17109         I915_WRITE(FP1(pipe), fp);
17110
17111         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17112         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17113         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17114         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17115         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17116         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17117         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17118
17119         /*
17120          * Apparently we need to have VGA mode enabled prior to changing
17121          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17122          * dividers, even though the register value does change.
17123          */
17124         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17125         I915_WRITE(DPLL(pipe), dpll);
17126
17127         /* Wait for the clocks to stabilize. */
17128         POSTING_READ(DPLL(pipe));
17129         udelay(150);
17130
17131         /* The pixel multiplier can only be updated once the
17132          * DPLL is enabled and the clocks are stable.
17133          *
17134          * So write it again.
17135          */
17136         I915_WRITE(DPLL(pipe), dpll);
17137
17138         /* We do this three times for luck */
17139         for (i = 0; i < 3 ; i++) {
17140                 I915_WRITE(DPLL(pipe), dpll);
17141                 POSTING_READ(DPLL(pipe));
17142                 udelay(150); /* wait for warmup */
17143         }
17144
17145         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17146         POSTING_READ(PIPECONF(pipe));
17147
17148         intel_wait_for_pipe_scanline_moving(crtc);
17149 }
17150
17151 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17152 {
17153         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17154
17155         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
17156                       pipe_name(pipe));
17157
17158         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
17159         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
17160         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
17161         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
17162         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
17163
17164         I915_WRITE(PIPECONF(pipe), 0);
17165         POSTING_READ(PIPECONF(pipe));
17166
17167         intel_wait_for_pipe_scanline_stopped(crtc);
17168
17169         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
17170         POSTING_READ(DPLL(pipe));
17171 }
17172
17173 static void
17174 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17175 {
17176         struct intel_crtc *crtc;
17177
17178         if (INTEL_GEN(dev_priv) >= 4)
17179                 return;
17180
17181         for_each_intel_crtc(&dev_priv->drm, crtc) {
17182                 struct intel_plane *plane =
17183                         to_intel_plane(crtc->base.primary);
17184                 struct intel_crtc *plane_crtc;
17185                 enum pipe pipe;
17186
17187                 if (!plane->get_hw_state(plane, &pipe))
17188                         continue;
17189
17190                 if (pipe == crtc->pipe)
17191                         continue;
17192
17193                 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17194                               plane->base.base.id, plane->base.name);
17195
17196                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17197                 intel_plane_disable_noatomic(plane_crtc, plane);
17198         }
17199 }
17200
17201 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17202 {
17203         struct drm_device *dev = crtc->base.dev;
17204         struct intel_encoder *encoder;
17205
17206         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17207                 return true;
17208
17209         return false;
17210 }
17211
17212 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17213 {
17214         struct drm_device *dev = encoder->base.dev;
17215         struct intel_connector *connector;
17216
17217         for_each_connector_on_encoder(dev, &encoder->base, connector)
17218                 return connector;
17219
17220         return NULL;
17221 }
17222
17223 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17224                               enum pipe pch_transcoder)
17225 {
17226         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17227                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17228 }
17229
17230 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
17231 {
17232         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
17233         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
17234         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17235
17236         if (INTEL_GEN(dev_priv) >= 9 ||
17237             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17238                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
17239                 u32 val;
17240
17241                 if (transcoder_is_dsi(cpu_transcoder))
17242                         return;
17243
17244                 val = I915_READ(reg);
17245                 val &= ~HSW_FRAME_START_DELAY_MASK;
17246                 val |= HSW_FRAME_START_DELAY(0);
17247                 I915_WRITE(reg, val);
17248         } else {
17249                 i915_reg_t reg = PIPECONF(cpu_transcoder);
17250                 u32 val;
17251
17252                 val = I915_READ(reg);
17253                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
17254                 val |= PIPECONF_FRAME_START_DELAY(0);
17255                 I915_WRITE(reg, val);
17256         }
17257
17258         if (!crtc_state->has_pch_encoder)
17259                 return;
17260
17261         if (HAS_PCH_IBX(dev_priv)) {
17262                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
17263                 u32 val;
17264
17265                 val = I915_READ(reg);
17266                 val &= ~TRANS_FRAME_START_DELAY_MASK;
17267                 val |= TRANS_FRAME_START_DELAY(0);
17268                 I915_WRITE(reg, val);
17269         } else {
17270                 i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
17271                 u32 val;
17272
17273                 val = I915_READ(reg);
17274                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
17275                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
17276                 I915_WRITE(reg, val);
17277         }
17278 }
17279
17280 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17281                                 struct drm_modeset_acquire_ctx *ctx)
17282 {
17283         struct drm_device *dev = crtc->base.dev;
17284         struct drm_i915_private *dev_priv = to_i915(dev);
17285         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17286
17287         if (crtc_state->hw.active) {
17288                 struct intel_plane *plane;
17289
17290                 /* Clear any frame start delays used for debugging left by the BIOS */
17291                 intel_sanitize_frame_start_delay(crtc_state);
17292
17293                 /* Disable everything but the primary plane */
17294                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17295                         const struct intel_plane_state *plane_state =
17296                                 to_intel_plane_state(plane->base.state);
17297
17298                         if (plane_state->uapi.visible &&
17299                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17300                                 intel_plane_disable_noatomic(crtc, plane);
17301                 }
17302
17303                 /*
17304                  * Disable any background color set by the BIOS, but enable the
17305                  * gamma and CSC to match how we program our planes.
17306                  */
17307                 if (INTEL_GEN(dev_priv) >= 9)
17308                         I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
17309                                    SKL_BOTTOM_COLOR_GAMMA_ENABLE |
17310                                    SKL_BOTTOM_COLOR_CSC_ENABLE);
17311         }
17312
17313         /* Adjust the state of the output pipe according to whether we
17314          * have active connectors/encoders. */
17315         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
17316                 intel_crtc_disable_noatomic(&crtc->base, ctx);
17317
17318         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
17319                 /*
17320                  * We start out with underrun reporting disabled to avoid races.
17321                  * For correct bookkeeping mark this on active crtcs.
17322                  *
17323                  * Also on gmch platforms we dont have any hardware bits to
17324                  * disable the underrun reporting. Which means we need to start
17325                  * out with underrun reporting disabled also on inactive pipes,
17326                  * since otherwise we'll complain about the garbage we read when
17327                  * e.g. coming up after runtime pm.
17328                  *
17329                  * No protection against concurrent access is required - at
17330                  * worst a fifo underrun happens which also sets this to false.
17331                  */
17332                 crtc->cpu_fifo_underrun_disabled = true;
17333                 /*
17334                  * We track the PCH trancoder underrun reporting state
17335                  * within the crtc. With crtc for pipe A housing the underrun
17336                  * reporting state for PCH transcoder A, crtc for pipe B housing
17337                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
17338                  * and marking underrun reporting as disabled for the non-existing
17339                  * PCH transcoders B and C would prevent enabling the south
17340                  * error interrupt (see cpt_can_enable_serr_int()).
17341                  */
17342                 if (has_pch_trancoder(dev_priv, crtc->pipe))
17343                         crtc->pch_fifo_underrun_disabled = true;
17344         }
17345 }
17346
17347 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
17348 {
17349         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
17350
17351         /*
17352          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
17353          * the hardware when a high res displays plugged in. DPLL P
17354          * divider is zero, and the pipe timings are bonkers. We'll
17355          * try to disable everything in that case.
17356          *
17357          * FIXME would be nice to be able to sanitize this state
17358          * without several WARNs, but for now let's take the easy
17359          * road.
17360          */
17361         return IS_GEN(dev_priv, 6) &&
17362                 crtc_state->hw.active &&
17363                 crtc_state->shared_dpll &&
17364                 crtc_state->port_clock == 0;
17365 }
17366
17367 static void intel_sanitize_encoder(struct intel_encoder *encoder)
17368 {
17369         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
17370         struct intel_connector *connector;
17371         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
17372         struct intel_crtc_state *crtc_state = crtc ?
17373                 to_intel_crtc_state(crtc->base.state) : NULL;
17374
17375         /* We need to check both for a crtc link (meaning that the
17376          * encoder is active and trying to read from a pipe) and the
17377          * pipe itself being active. */
17378         bool has_active_crtc = crtc_state &&
17379                 crtc_state->hw.active;
17380
17381         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
17382                 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
17383                               pipe_name(crtc->pipe));
17384                 has_active_crtc = false;
17385         }
17386
17387         connector = intel_encoder_find_connector(encoder);
17388         if (connector && !has_active_crtc) {
17389                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
17390                               encoder->base.base.id,
17391                               encoder->base.name);
17392
17393                 /* Connector is active, but has no active pipe. This is
17394                  * fallout from our resume register restoring. Disable
17395                  * the encoder manually again. */
17396                 if (crtc_state) {
17397                         struct drm_encoder *best_encoder;
17398
17399                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
17400                                       encoder->base.base.id,
17401                                       encoder->base.name);
17402
17403                         /* avoid oopsing in case the hooks consult best_encoder */
17404                         best_encoder = connector->base.state->best_encoder;
17405                         connector->base.state->best_encoder = &encoder->base;
17406
17407                         if (encoder->disable)
17408                                 encoder->disable(encoder, crtc_state,
17409                                                  connector->base.state);
17410                         if (encoder->post_disable)
17411                                 encoder->post_disable(encoder, crtc_state,
17412                                                       connector->base.state);
17413
17414                         connector->base.state->best_encoder = best_encoder;
17415                 }
17416                 encoder->base.crtc = NULL;
17417
17418                 /* Inconsistent output/port/pipe state happens presumably due to
17419                  * a bug in one of the get_hw_state functions. Or someplace else
17420                  * in our code, like the register restore mess on resume. Clamp
17421                  * things to off as a safer default. */
17422
17423                 connector->base.dpms = DRM_MODE_DPMS_OFF;
17424                 connector->base.encoder = NULL;
17425         }
17426
17427         /* notify opregion of the sanitized encoder state */
17428         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
17429
17430         if (INTEL_GEN(dev_priv) >= 11)
17431                 icl_sanitize_encoder_pll_mapping(encoder);
17432 }
17433
17434 /* FIXME read out full plane state for all planes */
17435 static void readout_plane_state(struct drm_i915_private *dev_priv)
17436 {
17437         struct intel_plane *plane;
17438         struct intel_crtc *crtc;
17439
17440         for_each_intel_plane(&dev_priv->drm, plane) {
17441                 struct intel_plane_state *plane_state =
17442                         to_intel_plane_state(plane->base.state);
17443                 struct intel_crtc_state *crtc_state;
17444                 enum pipe pipe = PIPE_A;
17445                 bool visible;
17446
17447                 visible = plane->get_hw_state(plane, &pipe);
17448
17449                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17450                 crtc_state = to_intel_crtc_state(crtc->base.state);
17451
17452                 intel_set_plane_visible(crtc_state, plane_state, visible);
17453
17454                 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
17455                               plane->base.base.id, plane->base.name,
17456                               enableddisabled(visible), pipe_name(pipe));
17457         }
17458
17459         for_each_intel_crtc(&dev_priv->drm, crtc) {
17460                 struct intel_crtc_state *crtc_state =
17461                         to_intel_crtc_state(crtc->base.state);
17462
17463                 fixup_active_planes(crtc_state);
17464         }
17465 }
17466
17467 static void intel_modeset_readout_hw_state(struct drm_device *dev)
17468 {
17469         struct drm_i915_private *dev_priv = to_i915(dev);
17470         enum pipe pipe;
17471         struct intel_crtc *crtc;
17472         struct intel_encoder *encoder;
17473         struct intel_connector *connector;
17474         struct drm_connector_list_iter conn_iter;
17475         int i;
17476
17477         dev_priv->active_pipes = 0;
17478
17479         for_each_intel_crtc(dev, crtc) {
17480                 struct intel_crtc_state *crtc_state =
17481                         to_intel_crtc_state(crtc->base.state);
17482
17483                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
17484                 intel_crtc_free_hw_state(crtc_state);
17485                 memset(crtc_state, 0, sizeof(*crtc_state));
17486                 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
17487
17488                 crtc_state->hw.active = crtc_state->hw.enable =
17489                         dev_priv->display.get_pipe_config(crtc, crtc_state);
17490
17491                 crtc->base.enabled = crtc_state->hw.enable;
17492                 crtc->active = crtc_state->hw.active;
17493
17494                 if (crtc_state->hw.active)
17495                         dev_priv->active_pipes |= BIT(crtc->pipe);
17496
17497                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17498                               crtc->base.base.id, crtc->base.name,
17499                               enableddisabled(crtc_state->hw.active));
17500         }
17501
17502         readout_plane_state(dev_priv);
17503
17504         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17505                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17506
17507                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
17508                                                         &pll->state.hw_state);
17509
17510                 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
17511                     pll->info->id == DPLL_ID_EHL_DPLL4) {
17512                         pll->wakeref = intel_display_power_get(dev_priv,
17513                                                                POWER_DOMAIN_DPLL_DC_OFF);
17514                 }
17515
17516                 pll->state.crtc_mask = 0;
17517                 for_each_intel_crtc(dev, crtc) {
17518                         struct intel_crtc_state *crtc_state =
17519                                 to_intel_crtc_state(crtc->base.state);
17520
17521                         if (crtc_state->hw.active &&
17522                             crtc_state->shared_dpll == pll)
17523                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17524                 }
17525                 pll->active_mask = pll->state.crtc_mask;
17526
17527                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17528                               pll->info->name, pll->state.crtc_mask, pll->on);
17529         }
17530
17531         for_each_intel_encoder(dev, encoder) {
17532                 pipe = 0;
17533
17534                 if (encoder->get_hw_state(encoder, &pipe)) {
17535                         struct intel_crtc_state *crtc_state;
17536
17537                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17538                         crtc_state = to_intel_crtc_state(crtc->base.state);
17539
17540                         encoder->base.crtc = &crtc->base;
17541                         encoder->get_config(encoder, crtc_state);
17542                 } else {
17543                         encoder->base.crtc = NULL;
17544                 }
17545
17546                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17547                               encoder->base.base.id, encoder->base.name,
17548                               enableddisabled(encoder->base.crtc),
17549                               pipe_name(pipe));
17550         }
17551
17552         drm_connector_list_iter_begin(dev, &conn_iter);
17553         for_each_intel_connector_iter(connector, &conn_iter) {
17554                 if (connector->get_hw_state(connector)) {
17555                         struct intel_crtc_state *crtc_state;
17556                         struct intel_crtc *crtc;
17557
17558                         connector->base.dpms = DRM_MODE_DPMS_ON;
17559
17560                         encoder = connector->encoder;
17561                         connector->base.encoder = &encoder->base;
17562
17563                         crtc = to_intel_crtc(encoder->base.crtc);
17564                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
17565
17566                         if (crtc_state && crtc_state->hw.active) {
17567                                 /*
17568                                  * This has to be done during hardware readout
17569                                  * because anything calling .crtc_disable may
17570                                  * rely on the connector_mask being accurate.
17571                                  */
17572                                 crtc_state->uapi.connector_mask |=
17573                                         drm_connector_mask(&connector->base);
17574                                 crtc_state->uapi.encoder_mask |=
17575                                         drm_encoder_mask(&encoder->base);
17576                         }
17577                 } else {
17578                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17579                         connector->base.encoder = NULL;
17580                 }
17581                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17582                               connector->base.base.id, connector->base.name,
17583                               enableddisabled(connector->base.encoder));
17584         }
17585         drm_connector_list_iter_end(&conn_iter);
17586
17587         for_each_intel_crtc(dev, crtc) {
17588                 struct intel_bw_state *bw_state =
17589                         to_intel_bw_state(dev_priv->bw_obj.state);
17590                 struct intel_crtc_state *crtc_state =
17591                         to_intel_crtc_state(crtc->base.state);
17592                 struct intel_plane *plane;
17593                 int min_cdclk = 0;
17594
17595                 if (crtc_state->hw.active) {
17596                         struct drm_display_mode *mode = &crtc_state->hw.mode;
17597
17598                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
17599                                                     crtc_state);
17600
17601                         *mode = crtc_state->hw.adjusted_mode;
17602                         mode->hdisplay = crtc_state->pipe_src_w;
17603                         mode->vdisplay = crtc_state->pipe_src_h;
17604
17605                         /*
17606                          * The initial mode needs to be set in order to keep
17607                          * the atomic core happy. It wants a valid mode if the
17608                          * crtc's enabled, so we do the above call.
17609                          *
17610                          * But we don't set all the derived state fully, hence
17611                          * set a flag to indicate that a full recalculation is
17612                          * needed on the next commit.
17613                          */
17614                         mode->private_flags = I915_MODE_FLAG_INHERITED;
17615
17616                         intel_crtc_compute_pixel_rate(crtc_state);
17617
17618                         intel_crtc_update_active_timings(crtc_state);
17619
17620                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
17621                 }
17622
17623                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
17624                         const struct intel_plane_state *plane_state =
17625                                 to_intel_plane_state(plane->base.state);
17626
17627                         /*
17628                          * FIXME don't have the fb yet, so can't
17629                          * use intel_plane_data_rate() :(
17630                          */
17631                         if (plane_state->uapi.visible)
17632                                 crtc_state->data_rate[plane->id] =
17633                                         4 * crtc_state->pixel_rate;
17634                         /*
17635                          * FIXME don't have the fb yet, so can't
17636                          * use plane->min_cdclk() :(
17637                          */
17638                         if (plane_state->uapi.visible && plane->min_cdclk) {
17639                                 if (crtc_state->double_wide ||
17640                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
17641                                         crtc_state->min_cdclk[plane->id] =
17642                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
17643                                 else
17644                                         crtc_state->min_cdclk[plane->id] =
17645                                                 crtc_state->pixel_rate;
17646                         }
17647                         DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n",
17648                                       plane->base.base.id, plane->base.name,
17649                                       crtc_state->min_cdclk[plane->id]);
17650                 }
17651
17652                 if (crtc_state->hw.active) {
17653                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
17654                         if (WARN_ON(min_cdclk < 0))
17655                                 min_cdclk = 0;
17656                 }
17657
17658                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
17659                 dev_priv->min_voltage_level[crtc->pipe] =
17660                         crtc_state->min_voltage_level;
17661
17662                 intel_bw_crtc_update(bw_state, crtc_state);
17663
17664                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17665         }
17666 }
17667
17668 static void
17669 get_encoder_power_domains(struct drm_i915_private *dev_priv)
17670 {
17671         struct intel_encoder *encoder;
17672
17673         for_each_intel_encoder(&dev_priv->drm, encoder) {
17674                 struct intel_crtc_state *crtc_state;
17675
17676                 if (!encoder->get_power_domains)
17677                         continue;
17678
17679                 /*
17680                  * MST-primary and inactive encoders don't have a crtc state
17681                  * and neither of these require any power domain references.
17682                  */
17683                 if (!encoder->base.crtc)
17684                         continue;
17685
17686                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
17687                 encoder->get_power_domains(encoder, crtc_state);
17688         }
17689 }
17690
17691 static void intel_early_display_was(struct drm_i915_private *dev_priv)
17692 {
17693         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
17694         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
17695                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
17696                            DARBF_GATING_DIS);
17697
17698         if (IS_HASWELL(dev_priv)) {
17699                 /*
17700                  * WaRsPkgCStateDisplayPMReq:hsw
17701                  * System hang if this isn't done before disabling all planes!
17702                  */
17703                 I915_WRITE(CHICKEN_PAR1_1,
17704                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
17705         }
17706 }
17707
17708 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
17709                                        enum port port, i915_reg_t hdmi_reg)
17710 {
17711         u32 val = I915_READ(hdmi_reg);
17712
17713         if (val & SDVO_ENABLE ||
17714             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
17715                 return;
17716
17717         DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
17718                       port_name(port));
17719
17720         val &= ~SDVO_PIPE_SEL_MASK;
17721         val |= SDVO_PIPE_SEL(PIPE_A);
17722
17723         I915_WRITE(hdmi_reg, val);
17724 }
17725
17726 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
17727                                      enum port port, i915_reg_t dp_reg)
17728 {
17729         u32 val = I915_READ(dp_reg);
17730
17731         if (val & DP_PORT_EN ||
17732             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
17733                 return;
17734
17735         DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
17736                       port_name(port));
17737
17738         val &= ~DP_PIPE_SEL_MASK;
17739         val |= DP_PIPE_SEL(PIPE_A);
17740
17741         I915_WRITE(dp_reg, val);
17742 }
17743
17744 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
17745 {
17746         /*
17747          * The BIOS may select transcoder B on some of the PCH
17748          * ports even it doesn't enable the port. This would trip
17749          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
17750          * Sanitize the transcoder select bits to prevent that. We
17751          * assume that the BIOS never actually enabled the port,
17752          * because if it did we'd actually have to toggle the port
17753          * on and back off to make the transcoder A select stick
17754          * (see. intel_dp_link_down(), intel_disable_hdmi(),
17755          * intel_disable_sdvo()).
17756          */
17757         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
17758         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
17759         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
17760
17761         /* PCH SDVOB multiplex with HDMIB */
17762         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
17763         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
17764         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
17765 }
17766
17767 /* Scan out the current hw modeset state,
17768  * and sanitizes it to the current state
17769  */
17770 static void
17771 intel_modeset_setup_hw_state(struct drm_device *dev,
17772                              struct drm_modeset_acquire_ctx *ctx)
17773 {
17774         struct drm_i915_private *dev_priv = to_i915(dev);
17775         struct intel_encoder *encoder;
17776         struct intel_crtc *crtc;
17777         intel_wakeref_t wakeref;
17778         int i;
17779
17780         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17781
17782         intel_early_display_was(dev_priv);
17783         intel_modeset_readout_hw_state(dev);
17784
17785         /* HW state is read out, now we need to sanitize this mess. */
17786
17787         /* Sanitize the TypeC port mode upfront, encoders depend on this */
17788         for_each_intel_encoder(dev, encoder) {
17789                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17790
17791                 /* We need to sanitize only the MST primary port. */
17792                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17793                     intel_phy_is_tc(dev_priv, phy))
17794                         intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17795         }
17796
17797         get_encoder_power_domains(dev_priv);
17798
17799         if (HAS_PCH_IBX(dev_priv))
17800                 ibx_sanitize_pch_ports(dev_priv);
17801
17802         /*
17803          * intel_sanitize_plane_mapping() may need to do vblank
17804          * waits, so we need vblank interrupts restored beforehand.
17805          */
17806         for_each_intel_crtc(&dev_priv->drm, crtc) {
17807                 struct intel_crtc_state *crtc_state =
17808                         to_intel_crtc_state(crtc->base.state);
17809
17810                 drm_crtc_vblank_reset(&crtc->base);
17811
17812                 if (crtc_state->hw.active)
17813                         intel_crtc_vblank_on(crtc_state);
17814         }
17815
17816         intel_sanitize_plane_mapping(dev_priv);
17817
17818         for_each_intel_encoder(dev, encoder)
17819                 intel_sanitize_encoder(encoder);
17820
17821         for_each_intel_crtc(&dev_priv->drm, crtc) {
17822                 struct intel_crtc_state *crtc_state =
17823                         crtc_state = to_intel_crtc_state(crtc->base.state);
17824
17825                 intel_sanitize_crtc(crtc, ctx);
17826                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17827         }
17828
17829         intel_modeset_update_connector_atomic_state(dev);
17830
17831         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17832                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17833
17834                 if (!pll->on || pll->active_mask)
17835                         continue;
17836
17837                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17838                               pll->info->name);
17839
17840                 pll->info->funcs->disable(dev_priv, pll);
17841                 pll->on = false;
17842         }
17843
17844         if (IS_G4X(dev_priv)) {
17845                 g4x_wm_get_hw_state(dev_priv);
17846                 g4x_wm_sanitize(dev_priv);
17847         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17848                 vlv_wm_get_hw_state(dev_priv);
17849                 vlv_wm_sanitize(dev_priv);
17850         } else if (INTEL_GEN(dev_priv) >= 9) {
17851                 skl_wm_get_hw_state(dev_priv);
17852         } else if (HAS_PCH_SPLIT(dev_priv)) {
17853                 ilk_wm_get_hw_state(dev_priv);
17854         }
17855
17856         for_each_intel_crtc(dev, crtc) {
17857                 struct intel_crtc_state *crtc_state =
17858                         to_intel_crtc_state(crtc->base.state);
17859                 u64 put_domains;
17860
17861                 put_domains = modeset_get_crtc_power_domains(crtc_state);
17862                 if (WARN_ON(put_domains))
17863                         modeset_put_power_domains(dev_priv, put_domains);
17864         }
17865
17866         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17867
17868         intel_fbc_init_pipe_state(dev_priv);
17869 }
17870
17871 void intel_display_resume(struct drm_device *dev)
17872 {
17873         struct drm_i915_private *dev_priv = to_i915(dev);
17874         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17875         struct drm_modeset_acquire_ctx ctx;
17876         int ret;
17877
17878         dev_priv->modeset_restore_state = NULL;
17879         if (state)
17880                 state->acquire_ctx = &ctx;
17881
17882         drm_modeset_acquire_init(&ctx, 0);
17883
17884         while (1) {
17885                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17886                 if (ret != -EDEADLK)
17887                         break;
17888
17889                 drm_modeset_backoff(&ctx);
17890         }
17891
17892         if (!ret)
17893                 ret = __intel_display_resume(dev, state, &ctx);
17894
17895         intel_enable_ipc(dev_priv);
17896         drm_modeset_drop_locks(&ctx);
17897         drm_modeset_acquire_fini(&ctx);
17898
17899         if (ret)
17900                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17901         if (state)
17902                 drm_atomic_state_put(state);
17903 }
17904
17905 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
17906 {
17907         struct intel_connector *connector;
17908         struct drm_connector_list_iter conn_iter;
17909
17910         /* Kill all the work that may have been queued by hpd. */
17911         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
17912         for_each_intel_connector_iter(connector, &conn_iter) {
17913                 if (connector->modeset_retry_work.func)
17914                         cancel_work_sync(&connector->modeset_retry_work);
17915                 if (connector->hdcp.shim) {
17916                         cancel_delayed_work_sync(&connector->hdcp.check_work);
17917                         cancel_work_sync(&connector->hdcp.prop_work);
17918                 }
17919         }
17920         drm_connector_list_iter_end(&conn_iter);
17921 }
17922
17923 void intel_modeset_driver_remove(struct drm_i915_private *i915)
17924 {
17925         flush_workqueue(i915->flip_wq);
17926         flush_workqueue(i915->modeset_wq);
17927
17928         flush_work(&i915->atomic_helper.free_work);
17929         WARN_ON(!llist_empty(&i915->atomic_helper.free_list));
17930
17931         /*
17932          * Interrupts and polling as the first thing to avoid creating havoc.
17933          * Too much stuff here (turning of connectors, ...) would
17934          * experience fancy races otherwise.
17935          */
17936         intel_irq_uninstall(i915);
17937
17938         /*
17939          * Due to the hpd irq storm handling the hotplug work can re-arm the
17940          * poll handlers. Hence disable polling after hpd handling is shut down.
17941          */
17942         intel_hpd_poll_fini(i915);
17943
17944         /* poll work can call into fbdev, hence clean that up afterwards */
17945         intel_fbdev_fini(i915);
17946
17947         intel_unregister_dsm_handler();
17948
17949         intel_fbc_global_disable(i915);
17950
17951         /* flush any delayed tasks or pending work */
17952         flush_scheduled_work();
17953
17954         intel_hdcp_component_fini(i915);
17955
17956         drm_mode_config_cleanup(&i915->drm);
17957
17958         intel_overlay_cleanup(i915);
17959
17960         intel_gmbus_teardown(i915);
17961
17962         destroy_workqueue(i915->flip_wq);
17963         destroy_workqueue(i915->modeset_wq);
17964
17965         intel_fbc_cleanup_cfb(i915);
17966 }
17967
17968 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17969
17970 struct intel_display_error_state {
17971
17972         u32 power_well_driver;
17973
17974         struct intel_cursor_error_state {
17975                 u32 control;
17976                 u32 position;
17977                 u32 base;
17978                 u32 size;
17979         } cursor[I915_MAX_PIPES];
17980
17981         struct intel_pipe_error_state {
17982                 bool power_domain_on;
17983                 u32 source;
17984                 u32 stat;
17985         } pipe[I915_MAX_PIPES];
17986
17987         struct intel_plane_error_state {
17988                 u32 control;
17989                 u32 stride;
17990                 u32 size;
17991                 u32 pos;
17992                 u32 addr;
17993                 u32 surface;
17994                 u32 tile_offset;
17995         } plane[I915_MAX_PIPES];
17996
17997         struct intel_transcoder_error_state {
17998                 bool available;
17999                 bool power_domain_on;
18000                 enum transcoder cpu_transcoder;
18001
18002                 u32 conf;
18003
18004                 u32 htotal;
18005                 u32 hblank;
18006                 u32 hsync;
18007                 u32 vtotal;
18008                 u32 vblank;
18009                 u32 vsync;
18010         } transcoder[5];
18011 };
18012
18013 struct intel_display_error_state *
18014 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
18015 {
18016         struct intel_display_error_state *error;
18017         int transcoders[] = {
18018                 TRANSCODER_A,
18019                 TRANSCODER_B,
18020                 TRANSCODER_C,
18021                 TRANSCODER_D,
18022                 TRANSCODER_EDP,
18023         };
18024         int i;
18025
18026         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
18027
18028         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
18029                 return NULL;
18030
18031         error = kzalloc(sizeof(*error), GFP_ATOMIC);
18032         if (error == NULL)
18033                 return NULL;
18034
18035         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18036                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
18037
18038         for_each_pipe(dev_priv, i) {
18039                 error->pipe[i].power_domain_on =
18040                         __intel_display_power_is_enabled(dev_priv,
18041                                                          POWER_DOMAIN_PIPE(i));
18042                 if (!error->pipe[i].power_domain_on)
18043                         continue;
18044
18045                 error->cursor[i].control = I915_READ(CURCNTR(i));
18046                 error->cursor[i].position = I915_READ(CURPOS(i));
18047                 error->cursor[i].base = I915_READ(CURBASE(i));
18048
18049                 error->plane[i].control = I915_READ(DSPCNTR(i));
18050                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
18051                 if (INTEL_GEN(dev_priv) <= 3) {
18052                         error->plane[i].size = I915_READ(DSPSIZE(i));
18053                         error->plane[i].pos = I915_READ(DSPPOS(i));
18054                 }
18055                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18056                         error->plane[i].addr = I915_READ(DSPADDR(i));
18057                 if (INTEL_GEN(dev_priv) >= 4) {
18058                         error->plane[i].surface = I915_READ(DSPSURF(i));
18059                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
18060                 }
18061
18062                 error->pipe[i].source = I915_READ(PIPESRC(i));
18063
18064                 if (HAS_GMCH(dev_priv))
18065                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
18066         }
18067
18068         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18069                 enum transcoder cpu_transcoder = transcoders[i];
18070
18071                 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
18072                         continue;
18073
18074                 error->transcoder[i].available = true;
18075                 error->transcoder[i].power_domain_on =
18076                         __intel_display_power_is_enabled(dev_priv,
18077                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18078                 if (!error->transcoder[i].power_domain_on)
18079                         continue;
18080
18081                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18082
18083                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
18084                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
18085                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
18086                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
18087                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
18088                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
18089                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
18090         }
18091
18092         return error;
18093 }
18094
18095 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18096
18097 void
18098 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18099                                 struct intel_display_error_state *error)
18100 {
18101         struct drm_i915_private *dev_priv = m->i915;
18102         int i;
18103
18104         if (!error)
18105                 return;
18106
18107         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18108         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18109                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18110                            error->power_well_driver);
18111         for_each_pipe(dev_priv, i) {
18112                 err_printf(m, "Pipe [%d]:\n", i);
18113                 err_printf(m, "  Power: %s\n",
18114                            onoff(error->pipe[i].power_domain_on));
18115                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
18116                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
18117
18118                 err_printf(m, "Plane [%d]:\n", i);
18119                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
18120                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
18121                 if (INTEL_GEN(dev_priv) <= 3) {
18122                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
18123                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
18124                 }
18125                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18126                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
18127                 if (INTEL_GEN(dev_priv) >= 4) {
18128                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
18129                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
18130                 }
18131
18132                 err_printf(m, "Cursor [%d]:\n", i);
18133                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
18134                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
18135                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
18136         }
18137
18138         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18139                 if (!error->transcoder[i].available)
18140                         continue;
18141
18142                 err_printf(m, "CPU transcoder: %s\n",
18143                            transcoder_name(error->transcoder[i].cpu_transcoder));
18144                 err_printf(m, "  Power: %s\n",
18145                            onoff(error->transcoder[i].power_domain_on));
18146                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
18147                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
18148                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
18149                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
18150                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
18151                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
18152                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
18153         }
18154 }
18155
18156 #endif