drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <drm/i915_drm.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_RGB565,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 /* Primary plane formats for vlv/chv */
 116 static const u32 vlv_primary_formats[] = {
 117         DRM_FORMAT_C8,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_XRGB8888,
 120         DRM_FORMAT_XBGR8888,
 121         DRM_FORMAT_ARGB8888,
 122         DRM_FORMAT_ABGR8888,
 123         DRM_FORMAT_XRGB2101010,
 124         DRM_FORMAT_XBGR2101010,
 125         DRM_FORMAT_ARGB2101010,
 126         DRM_FORMAT_ABGR2101010,
 127         DRM_FORMAT_XBGR16161616F,
 128 };
 129
 130 static const u64 i9xx_format_modifiers[] = {
 131         I915_FORMAT_MOD_X_TILED,
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 /* Cursor formats */
 137 static const u32 intel_cursor_formats[] = {
 138         DRM_FORMAT_ARGB8888,
 139 };
 140
 141 static const u64 cursor_format_modifiers[] = {
 142         DRM_FORMAT_MOD_LINEAR,
 143         DRM_FORMAT_MOD_INVALID
 144 };
 145
 146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 147                                 struct intel_crtc_state *pipe_config);
 148 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 149                                    struct intel_crtc_state *pipe_config);
 150
 151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 152                                   struct drm_i915_gem_object *obj,
 153                                   struct drm_mode_fb_cmd2 *mode_cmd);
 154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 157                                          const struct intel_link_m_n *m_n,
 158                                          const struct intel_link_m_n *m2_n2);
 159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 160 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 161 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
 162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 163 static void vlv_prepare_pll(struct intel_crtc *crtc,
 164                             const struct intel_crtc_state *pipe_config);
 165 static void chv_prepare_pll(struct intel_crtc *crtc,
 166                             const struct intel_crtc_state *pipe_config);
 167 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 168                                     struct intel_crtc_state *crtc_state);
 169 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
 170 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 171 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 173                                          struct drm_modeset_acquire_ctx *ctx);
 174 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 175
 176 struct intel_limit {
 177         struct {
 178                 int min, max;
 179         } dot, vco, n, m, m1, m2, p, p1;
 180
 181         struct {
 182                 int dot_limit;
 183                 int p2_slow, p2_fast;
 184         } p2;
 185 };
 186
 187 /* returns HPLL frequency in kHz */
 188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 189 {
 190         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 191
 192         /* Obtain SKU information */
 193         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 194                 CCK_FUSE_HPLL_FREQ_MASK;
 195
 196         return vco_freq[hpll_freq] * 1000;
 197 }
 198
 199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 200                       const char *name, u32 reg, int ref_freq)
 201 {
 202         u32 val;
 203         int divider;
 204
 205         val = vlv_cck_read(dev_priv, reg);
 206         divider = val & CCK_FREQUENCY_VALUES;
 207
 208         WARN((val & CCK_FREQUENCY_STATUS) !=
 209              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 210              "%s change in progress\n", name);
 211
 212         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 213 }
 214
 215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 216                            const char *name, u32 reg)
 217 {
 218         int hpll;
 219
 220         vlv_cck_get(dev_priv);
 221
 222         if (dev_priv->hpll_freq == 0)
 223                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 224
 225         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 226
 227         vlv_cck_put(dev_priv);
 228
 229         return hpll;
 230 }
 231
 232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 233 {
 234         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 235                 return;
 236
 237         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 238                                                       CCK_CZ_CLOCK_CONTROL);
 239
 240         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 241 }
 242
 243 static inline u32 /* units of 100MHz */
 244 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 245                     const struct intel_crtc_state *pipe_config)
 246 {
 247         if (HAS_DDI(dev_priv))
 248                 return pipe_config->port_clock; /* SPLL */
 249         else
 250                 return dev_priv->fdi_pll_freq;
 251 }
 252
 253 static const struct intel_limit intel_limits_i8xx_dac = {
 254         .dot = { .min = 25000, .max = 350000 },
 255         .vco = { .min = 908000, .max = 1512000 },
 256         .n = { .min = 2, .max = 16 },
 257         .m = { .min = 96, .max = 140 },
 258         .m1 = { .min = 18, .max = 26 },
 259         .m2 = { .min = 6, .max = 16 },
 260         .p = { .min = 4, .max = 128 },
 261         .p1 = { .min = 2, .max = 33 },
 262         .p2 = { .dot_limit = 165000,
 263                 .p2_slow = 4, .p2_fast = 2 },
 264 };
 265
 266 static const struct intel_limit intel_limits_i8xx_dvo = {
 267         .dot = { .min = 25000, .max = 350000 },
 268         .vco = { .min = 908000, .max = 1512000 },
 269         .n = { .min = 2, .max = 16 },
 270         .m = { .min = 96, .max = 140 },
 271         .m1 = { .min = 18, .max = 26 },
 272         .m2 = { .min = 6, .max = 16 },
 273         .p = { .min = 4, .max = 128 },
 274         .p1 = { .min = 2, .max = 33 },
 275         .p2 = { .dot_limit = 165000,
 276                 .p2_slow = 4, .p2_fast = 4 },
 277 };
 278
 279 static const struct intel_limit intel_limits_i8xx_lvds = {
 280         .dot = { .min = 25000, .max = 350000 },
 281         .vco = { .min = 908000, .max = 1512000 },
 282         .n = { .min = 2, .max = 16 },
 283         .m = { .min = 96, .max = 140 },
 284         .m1 = { .min = 18, .max = 26 },
 285         .m2 = { .min = 6, .max = 16 },
 286         .p = { .min = 4, .max = 128 },
 287         .p1 = { .min = 1, .max = 6 },
 288         .p2 = { .dot_limit = 165000,
 289                 .p2_slow = 14, .p2_fast = 7 },
 290 };
 291
 292 static const struct intel_limit intel_limits_i9xx_sdvo = {
 293         .dot = { .min = 20000, .max = 400000 },
 294         .vco = { .min = 1400000, .max = 2800000 },
 295         .n = { .min = 1, .max = 6 },
 296         .m = { .min = 70, .max = 120 },
 297         .m1 = { .min = 8, .max = 18 },
 298         .m2 = { .min = 3, .max = 7 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 200000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303 };
 304
 305 static const struct intel_limit intel_limits_i9xx_lvds = {
 306         .dot = { .min = 20000, .max = 400000 },
 307         .vco = { .min = 1400000, .max = 2800000 },
 308         .n = { .min = 1, .max = 6 },
 309         .m = { .min = 70, .max = 120 },
 310         .m1 = { .min = 8, .max = 18 },
 311         .m2 = { .min = 3, .max = 7 },
 312         .p = { .min = 7, .max = 98 },
 313         .p1 = { .min = 1, .max = 8 },
 314         .p2 = { .dot_limit = 112000,
 315                 .p2_slow = 14, .p2_fast = 7 },
 316 };
 317
 318
 319 static const struct intel_limit intel_limits_g4x_sdvo = {
 320         .dot = { .min = 25000, .max = 270000 },
 321         .vco = { .min = 1750000, .max = 3500000},
 322         .n = { .min = 1, .max = 4 },
 323         .m = { .min = 104, .max = 138 },
 324         .m1 = { .min = 17, .max = 23 },
 325         .m2 = { .min = 5, .max = 11 },
 326         .p = { .min = 10, .max = 30 },
 327         .p1 = { .min = 1, .max = 3},
 328         .p2 = { .dot_limit = 270000,
 329                 .p2_slow = 10,
 330                 .p2_fast = 10
 331         },
 332 };
 333
 334 static const struct intel_limit intel_limits_g4x_hdmi = {
 335         .dot = { .min = 22000, .max = 400000 },
 336         .vco = { .min = 1750000, .max = 3500000},
 337         .n = { .min = 1, .max = 4 },
 338         .m = { .min = 104, .max = 138 },
 339         .m1 = { .min = 16, .max = 23 },
 340         .m2 = { .min = 5, .max = 11 },
 341         .p = { .min = 5, .max = 80 },
 342         .p1 = { .min = 1, .max = 8},
 343         .p2 = { .dot_limit = 165000,
 344                 .p2_slow = 10, .p2_fast = 5 },
 345 };
 346
 347 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 348         .dot = { .min = 20000, .max = 115000 },
 349         .vco = { .min = 1750000, .max = 3500000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 104, .max = 138 },
 352         .m1 = { .min = 17, .max = 23 },
 353         .m2 = { .min = 5, .max = 11 },
 354         .p = { .min = 28, .max = 112 },
 355         .p1 = { .min = 2, .max = 8 },
 356         .p2 = { .dot_limit = 0,
 357                 .p2_slow = 14, .p2_fast = 14
 358         },
 359 };
 360
 361 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 362         .dot = { .min = 80000, .max = 224000 },
 363         .vco = { .min = 1750000, .max = 3500000 },
 364         .n = { .min = 1, .max = 3 },
 365         .m = { .min = 104, .max = 138 },
 366         .m1 = { .min = 17, .max = 23 },
 367         .m2 = { .min = 5, .max = 11 },
 368         .p = { .min = 14, .max = 42 },
 369         .p1 = { .min = 2, .max = 6 },
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 7, .p2_fast = 7
 372         },
 373 };
 374
 375 static const struct intel_limit intel_limits_pineview_sdvo = {
 376         .dot = { .min = 20000, .max = 400000},
 377         .vco = { .min = 1700000, .max = 3500000 },
 378         /* Pineview's Ncounter is a ring counter */
 379         .n = { .min = 3, .max = 6 },
 380         .m = { .min = 2, .max = 256 },
 381         /* Pineview only has one combined m divider, which we treat as m2. */
 382         .m1 = { .min = 0, .max = 0 },
 383         .m2 = { .min = 0, .max = 254 },
 384         .p = { .min = 5, .max = 80 },
 385         .p1 = { .min = 1, .max = 8 },
 386         .p2 = { .dot_limit = 200000,
 387                 .p2_slow = 10, .p2_fast = 5 },
 388 };
 389
 390 static const struct intel_limit intel_limits_pineview_lvds = {
 391         .dot = { .min = 20000, .max = 400000 },
 392         .vco = { .min = 1700000, .max = 3500000 },
 393         .n = { .min = 3, .max = 6 },
 394         .m = { .min = 2, .max = 256 },
 395         .m1 = { .min = 0, .max = 0 },
 396         .m2 = { .min = 0, .max = 254 },
 397         .p = { .min = 7, .max = 112 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 112000,
 400                 .p2_slow = 14, .p2_fast = 14 },
 401 };
 402
 403 /* Ironlake / Sandybridge
 404  *
 405  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 406  * the range value for them is (actual_value - 2).
 407  */
 408 static const struct intel_limit intel_limits_ironlake_dac = {
 409         .dot = { .min = 25000, .max = 350000 },
 410         .vco = { .min = 1760000, .max = 3510000 },
 411         .n = { .min = 1, .max = 5 },
 412         .m = { .min = 79, .max = 127 },
 413         .m1 = { .min = 12, .max = 22 },
 414         .m2 = { .min = 5, .max = 9 },
 415         .p = { .min = 5, .max = 80 },
 416         .p1 = { .min = 1, .max = 8 },
 417         .p2 = { .dot_limit = 225000,
 418                 .p2_slow = 10, .p2_fast = 5 },
 419 };
 420
 421 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 422         .dot = { .min = 25000, .max = 350000 },
 423         .vco = { .min = 1760000, .max = 3510000 },
 424         .n = { .min = 1, .max = 3 },
 425         .m = { .min = 79, .max = 118 },
 426         .m1 = { .min = 12, .max = 22 },
 427         .m2 = { .min = 5, .max = 9 },
 428         .p = { .min = 28, .max = 112 },
 429         .p1 = { .min = 2, .max = 8 },
 430         .p2 = { .dot_limit = 225000,
 431                 .p2_slow = 14, .p2_fast = 14 },
 432 };
 433
 434 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 435         .dot = { .min = 25000, .max = 350000 },
 436         .vco = { .min = 1760000, .max = 3510000 },
 437         .n = { .min = 1, .max = 3 },
 438         .m = { .min = 79, .max = 127 },
 439         .m1 = { .min = 12, .max = 22 },
 440         .m2 = { .min = 5, .max = 9 },
 441         .p = { .min = 14, .max = 56 },
 442         .p1 = { .min = 2, .max = 8 },
 443         .p2 = { .dot_limit = 225000,
 444                 .p2_slow = 7, .p2_fast = 7 },
 445 };
 446
 447 /* LVDS 100mhz refclk limits. */
 448 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 449         .dot = { .min = 25000, .max = 350000 },
 450         .vco = { .min = 1760000, .max = 3510000 },
 451         .n = { .min = 1, .max = 2 },
 452         .m = { .min = 79, .max = 126 },
 453         .m1 = { .min = 12, .max = 22 },
 454         .m2 = { .min = 5, .max = 9 },
 455         .p = { .min = 28, .max = 112 },
 456         .p1 = { .min = 2, .max = 8 },
 457         .p2 = { .dot_limit = 225000,
 458                 .p2_slow = 14, .p2_fast = 14 },
 459 };
 460
 461 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 462         .dot = { .min = 25000, .max = 350000 },
 463         .vco = { .min = 1760000, .max = 3510000 },
 464         .n = { .min = 1, .max = 3 },
 465         .m = { .min = 79, .max = 126 },
 466         .m1 = { .min = 12, .max = 22 },
 467         .m2 = { .min = 5, .max = 9 },
 468         .p = { .min = 14, .max = 42 },
 469         .p1 = { .min = 2, .max = 6 },
 470         .p2 = { .dot_limit = 225000,
 471                 .p2_slow = 7, .p2_fast = 7 },
 472 };
 473
 474 static const struct intel_limit intel_limits_vlv = {
 475          /*
 476           * These are the data rate limits (measured in fast clocks)
 477           * since those are the strictest limits we have. The fast
 478           * clock and actual rate limits are more relaxed, so checking
 479           * them would make no difference.
 480           */
 481         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 482         .vco = { .min = 4000000, .max = 6000000 },
 483         .n = { .min = 1, .max = 7 },
 484         .m1 = { .min = 2, .max = 3 },
 485         .m2 = { .min = 11, .max = 156 },
 486         .p1 = { .min = 2, .max = 3 },
 487         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 488 };
 489
 490 static const struct intel_limit intel_limits_chv = {
 491         /*
 492          * These are the data rate limits (measured in fast clocks)
 493          * since those are the strictest limits we have.  The fast
 494          * clock and actual rate limits are more relaxed, so checking
 495          * them would make no difference.
 496          */
 497         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 498         .vco = { .min = 4800000, .max = 6480000 },
 499         .n = { .min = 1, .max = 1 },
 500         .m1 = { .min = 2, .max = 2 },
 501         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 502         .p1 = { .min = 2, .max = 4 },
 503         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 504 };
 505
 506 static const struct intel_limit intel_limits_bxt = {
 507         /* FIXME: find real dot limits */
 508         .dot = { .min = 0, .max = INT_MAX },
 509         .vco = { .min = 4800000, .max = 6700000 },
 510         .n = { .min = 1, .max = 1 },
 511         .m1 = { .min = 2, .max = 2 },
 512         /* FIXME: find real m2 limits */
 513         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 514         .p1 = { .min = 2, .max = 4 },
 515         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 516 };
 517
 518 /* WA Display #0827: Gen9:all */
 519 static void
 520 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 521 {
 522         if (enable)
 523                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 524                            I915_READ(CLKGATE_DIS_PSL(pipe)) |
 525                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 526         else
 527                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 528                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 529                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 530 }
 531
 532 /* Wa_2006604312:icl */
 533 static void
 534 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 535                        bool enable)
 536 {
 537         if (enable)
 538                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 539                            I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 540         else
 541                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 542                            I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 543 }
 544
 545 static bool
 546 needs_modeset(const struct intel_crtc_state *state)
 547 {
 548         return drm_atomic_crtc_needs_modeset(&state->uapi);
 549 }
 550
 551 bool
 552 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 553 {
 554         return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
 555                 crtc_state->sync_mode_slaves_mask);
 556 }
 557
 558 static bool
 559 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 560 {
 561         return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
 562                 crtc_state->sync_mode_slaves_mask);
 563 }
 564
 565 /*
 566  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 567  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 568  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 569  * The helpers' return value is the rate of the clock that is fed to the
 570  * display engine's pipe which can be the above fast dot clock rate or a
 571  * divided-down version of it.
 572  */
 573 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 574 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 575 {
 576         clock->m = clock->m2 + 2;
 577         clock->p = clock->p1 * clock->p2;
 578         if (WARN_ON(clock->n == 0 || clock->p == 0))
 579                 return 0;
 580         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 581         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 582
 583         return clock->dot;
 584 }
 585
 586 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 587 {
 588         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 589 }
 590
 591 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 592 {
 593         clock->m = i9xx_dpll_compute_m(clock);
 594         clock->p = clock->p1 * clock->p2;
 595         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 596                 return 0;
 597         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 598         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 599
 600         return clock->dot;
 601 }
 602
 603 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 604 {
 605         clock->m = clock->m1 * clock->m2;
 606         clock->p = clock->p1 * clock->p2;
 607         if (WARN_ON(clock->n == 0 || clock->p == 0))
 608                 return 0;
 609         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 610         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 611
 612         return clock->dot / 5;
 613 }
 614
 615 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 616 {
 617         clock->m = clock->m1 * clock->m2;
 618         clock->p = clock->p1 * clock->p2;
 619         if (WARN_ON(clock->n == 0 || clock->p == 0))
 620                 return 0;
 621         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 622                                            clock->n << 22);
 623         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 624
 625         return clock->dot / 5;
 626 }
 627
 628 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 629
 630 /*
 631  * Returns whether the given set of divisors are valid for a given refclk with
 632  * the given connectors.
 633  */
 634 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 635                                const struct intel_limit *limit,
 636                                const struct dpll *clock)
 637 {
 638         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 639                 INTELPllInvalid("n out of range\n");
 640         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 641                 INTELPllInvalid("p1 out of range\n");
 642         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 643                 INTELPllInvalid("m2 out of range\n");
 644         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 645                 INTELPllInvalid("m1 out of range\n");
 646
 647         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 648             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 649                 if (clock->m1 <= clock->m2)
 650                         INTELPllInvalid("m1 <= m2\n");
 651
 652         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 653             !IS_GEN9_LP(dev_priv)) {
 654                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 655                         INTELPllInvalid("p out of range\n");
 656                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 657                         INTELPllInvalid("m out of range\n");
 658         }
 659
 660         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 661                 INTELPllInvalid("vco out of range\n");
 662         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 663          * connector, etc., rather than just a single range.
 664          */
 665         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 666                 INTELPllInvalid("dot out of range\n");
 667
 668         return true;
 669 }
 670
 671 static int
 672 i9xx_select_p2_div(const struct intel_limit *limit,
 673                    const struct intel_crtc_state *crtc_state,
 674                    int target)
 675 {
 676         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 677
 678         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 679                 /*
 680                  * For LVDS just rely on its current settings for dual-channel.
 681                  * We haven't figured out how to reliably set up different
 682                  * single/dual channel state, if we even can.
 683                  */
 684                 if (intel_is_dual_link_lvds(dev_priv))
 685                         return limit->p2.p2_fast;
 686                 else
 687                         return limit->p2.p2_slow;
 688         } else {
 689                 if (target < limit->p2.dot_limit)
 690                         return limit->p2.p2_slow;
 691                 else
 692                         return limit->p2.p2_fast;
 693         }
 694 }
 695
 696 /*
 697  * Returns a set of divisors for the desired target clock with the given
 698  * refclk, or FALSE.  The returned values represent the clock equation:
 699  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 700  *
 701  * Target and reference clocks are specified in kHz.
 702  *
 703  * If match_clock is provided, then best_clock P divider must match the P
 704  * divider from @match_clock used for LVDS downclocking.
 705  */
 706 static bool
 707 i9xx_find_best_dpll(const struct intel_limit *limit,
 708                     struct intel_crtc_state *crtc_state,
 709                     int target, int refclk, struct dpll *match_clock,
 710                     struct dpll *best_clock)
 711 {
 712         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 713         struct dpll clock;
 714         int err = target;
 715
 716         memset(best_clock, 0, sizeof(*best_clock));
 717
 718         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 719
 720         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 721              clock.m1++) {
 722                 for (clock.m2 = limit->m2.min;
 723                      clock.m2 <= limit->m2.max; clock.m2++) {
 724                         if (clock.m2 >= clock.m1)
 725                                 break;
 726                         for (clock.n = limit->n.min;
 727                              clock.n <= limit->n.max; clock.n++) {
 728                                 for (clock.p1 = limit->p1.min;
 729                                         clock.p1 <= limit->p1.max; clock.p1++) {
 730                                         int this_err;
 731
 732                                         i9xx_calc_dpll_params(refclk, &clock);
 733                                         if (!intel_PLL_is_valid(to_i915(dev),
 734                                                                 limit,
 735                                                                 &clock))
 736                                                 continue;
 737                                         if (match_clock &&
 738                                             clock.p != match_clock->p)
 739                                                 continue;
 740
 741                                         this_err = abs(clock.dot - target);
 742                                         if (this_err < err) {
 743                                                 *best_clock = clock;
 744                                                 err = this_err;
 745                                         }
 746                                 }
 747                         }
 748                 }
 749         }
 750
 751         return (err != target);
 752 }
 753
 754 /*
 755  * Returns a set of divisors for the desired target clock with the given
 756  * refclk, or FALSE.  The returned values represent the clock equation:
 757  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 758  *
 759  * Target and reference clocks are specified in kHz.
 760  *
 761  * If match_clock is provided, then best_clock P divider must match the P
 762  * divider from @match_clock used for LVDS downclocking.
 763  */
 764 static bool
 765 pnv_find_best_dpll(const struct intel_limit *limit,
 766                    struct intel_crtc_state *crtc_state,
 767                    int target, int refclk, struct dpll *match_clock,
 768                    struct dpll *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 771         struct dpll clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         for (clock.n = limit->n.min;
 783                              clock.n <= limit->n.max; clock.n++) {
 784                                 for (clock.p1 = limit->p1.min;
 785                                         clock.p1 <= limit->p1.max; clock.p1++) {
 786                                         int this_err;
 787
 788                                         pnv_calc_dpll_params(refclk, &clock);
 789                                         if (!intel_PLL_is_valid(to_i915(dev),
 790                                                                 limit,
 791                                                                 &clock))
 792                                                 continue;
 793                                         if (match_clock &&
 794                                             clock.p != match_clock->p)
 795                                                 continue;
 796
 797                                         this_err = abs(clock.dot - target);
 798                                         if (this_err < err) {
 799                                                 *best_clock = clock;
 800                                                 err = this_err;
 801                                         }
 802                                 }
 803                         }
 804                 }
 805         }
 806
 807         return (err != target);
 808 }
 809
 810 /*
 811  * Returns a set of divisors for the desired target clock with the given
 812  * refclk, or FALSE.  The returned values represent the clock equation:
 813  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 814  *
 815  * Target and reference clocks are specified in kHz.
 816  *
 817  * If match_clock is provided, then best_clock P divider must match the P
 818  * divider from @match_clock used for LVDS downclocking.
 819  */
 820 static bool
 821 g4x_find_best_dpll(const struct intel_limit *limit,
 822                    struct intel_crtc_state *crtc_state,
 823                    int target, int refclk, struct dpll *match_clock,
 824                    struct dpll *best_clock)
 825 {
 826         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 827         struct dpll clock;
 828         int max_n;
 829         bool found = false;
 830         /* approximately equals target * 0.00585 */
 831         int err_most = (target >> 8) + (target >> 9);
 832
 833         memset(best_clock, 0, sizeof(*best_clock));
 834
 835         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 836
 837         max_n = limit->n.max;
 838         /* based on hardware requirement, prefer smaller n to precision */
 839         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 840                 /* based on hardware requirement, prefere larger m1,m2 */
 841                 for (clock.m1 = limit->m1.max;
 842                      clock.m1 >= limit->m1.min; clock.m1--) {
 843                         for (clock.m2 = limit->m2.max;
 844                              clock.m2 >= limit->m2.min; clock.m2--) {
 845                                 for (clock.p1 = limit->p1.max;
 846                                      clock.p1 >= limit->p1.min; clock.p1--) {
 847                                         int this_err;
 848
 849                                         i9xx_calc_dpll_params(refclk, &clock);
 850                                         if (!intel_PLL_is_valid(to_i915(dev),
 851                                                                 limit,
 852                                                                 &clock))
 853                                                 continue;
 854
 855                                         this_err = abs(clock.dot - target);
 856                                         if (this_err < err_most) {
 857                                                 *best_clock = clock;
 858                                                 err_most = this_err;
 859                                                 max_n = clock.n;
 860                                                 found = true;
 861                                         }
 862                                 }
 863                         }
 864                 }
 865         }
 866         return found;
 867 }
 868
 869 /*
 870  * Check if the calculated PLL configuration is more optimal compared to the
 871  * best configuration and error found so far. Return the calculated error.
 872  */
 873 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 874                                const struct dpll *calculated_clock,
 875                                const struct dpll *best_clock,
 876                                unsigned int best_error_ppm,
 877                                unsigned int *error_ppm)
 878 {
 879         /*
 880          * For CHV ignore the error and consider only the P value.
 881          * Prefer a bigger P value based on HW requirements.
 882          */
 883         if (IS_CHERRYVIEW(to_i915(dev))) {
 884                 *error_ppm = 0;
 885
 886                 return calculated_clock->p > best_clock->p;
 887         }
 888
 889         if (WARN_ON_ONCE(!target_freq))
 890                 return false;
 891
 892         *error_ppm = div_u64(1000000ULL *
 893                                 abs(target_freq - calculated_clock->dot),
 894                              target_freq);
 895         /*
 896          * Prefer a better P value over a better (smaller) error if the error
 897          * is small. Ensure this preference for future configurations too by
 898          * setting the error to 0.
 899          */
 900         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 901                 *error_ppm = 0;
 902
 903                 return true;
 904         }
 905
 906         return *error_ppm + 10 < best_error_ppm;
 907 }
 908
 909 /*
 910  * Returns a set of divisors for the desired target clock with the given
 911  * refclk, or FALSE.  The returned values represent the clock equation:
 912  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 913  */
 914 static bool
 915 vlv_find_best_dpll(const struct intel_limit *limit,
 916                    struct intel_crtc_state *crtc_state,
 917                    int target, int refclk, struct dpll *match_clock,
 918                    struct dpll *best_clock)
 919 {
 920         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 921         struct drm_device *dev = crtc->base.dev;
 922         struct dpll clock;
 923         unsigned int bestppm = 1000000;
 924         /* min update 19.2 MHz */
 925         int max_n = min(limit->n.max, refclk / 19200);
 926         bool found = false;
 927
 928         target *= 5; /* fast clock */
 929
 930         memset(best_clock, 0, sizeof(*best_clock));
 931
 932         /* based on hardware requirement, prefer smaller n to precision */
 933         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 934                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 935                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 936                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 937                                 clock.p = clock.p1 * clock.p2;
 938                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 939                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 940                                         unsigned int ppm;
 941
 942                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 943                                                                      refclk * clock.m1);
 944
 945                                         vlv_calc_dpll_params(refclk, &clock);
 946
 947                                         if (!intel_PLL_is_valid(to_i915(dev),
 948                                                                 limit,
 949                                                                 &clock))
 950                                                 continue;
 951
 952                                         if (!vlv_PLL_is_optimal(dev, target,
 953                                                                 &clock,
 954                                                                 best_clock,
 955                                                                 bestppm, &ppm))
 956                                                 continue;
 957
 958                                         *best_clock = clock;
 959                                         bestppm = ppm;
 960                                         found = true;
 961                                 }
 962                         }
 963                 }
 964         }
 965
 966         return found;
 967 }
 968
 969 /*
 970  * Returns a set of divisors for the desired target clock with the given
 971  * refclk, or FALSE.  The returned values represent the clock equation:
 972  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 973  */
 974 static bool
 975 chv_find_best_dpll(const struct intel_limit *limit,
 976                    struct intel_crtc_state *crtc_state,
 977                    int target, int refclk, struct dpll *match_clock,
 978                    struct dpll *best_clock)
 979 {
 980         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 981         struct drm_device *dev = crtc->base.dev;
 982         unsigned int best_error_ppm;
 983         struct dpll clock;
 984         u64 m2;
 985         int found = false;
 986
 987         memset(best_clock, 0, sizeof(*best_clock));
 988         best_error_ppm = 1000000;
 989
 990         /*
 991          * Based on hardware doc, the n always set to 1, and m1 always
 992          * set to 2.  If requires to support 200Mhz refclk, we need to
 993          * revisit this because n may not 1 anymore.
 994          */
 995         clock.n = 1, clock.m1 = 2;
 996         target *= 5;    /* fast clock */
 997
 998         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 999                 for (clock.p2 = limit->p2.p2_fast;
1000                                 clock.p2 >= limit->p2.p2_slow;
1001                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1002                         unsigned int error_ppm;
1003
1004                         clock.p = clock.p1 * clock.p2;
1005
1006                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1007                                                    refclk * clock.m1);
1008
1009                         if (m2 > INT_MAX/clock.m1)
1010                                 continue;
1011
1012                         clock.m2 = m2;
1013
1014                         chv_calc_dpll_params(refclk, &clock);
1015
1016                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1017                                 continue;
1018
1019                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1020                                                 best_error_ppm, &error_ppm))
1021                                 continue;
1022
1023                         *best_clock = clock;
1024                         best_error_ppm = error_ppm;
1025                         found = true;
1026                 }
1027         }
1028
1029         return found;
1030 }
1031
1032 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1033                         struct dpll *best_clock)
1034 {
1035         int refclk = 100000;
1036         const struct intel_limit *limit = &intel_limits_bxt;
1037
1038         return chv_find_best_dpll(limit, crtc_state,
1039                                   crtc_state->port_clock, refclk,
1040                                   NULL, best_clock);
1041 }
1042
1043 bool intel_crtc_active(struct intel_crtc *crtc)
1044 {
1045         /* Be paranoid as we can arrive here with only partial
1046          * state retrieved from the hardware during setup.
1047          *
1048          * We can ditch the adjusted_mode.crtc_clock check as soon
1049          * as Haswell has gained clock readout/fastboot support.
1050          *
1051          * We can ditch the crtc->primary->state->fb check as soon as we can
1052          * properly reconstruct framebuffers.
1053          *
1054          * FIXME: The intel_crtc->active here should be switched to
1055          * crtc->state->active once we have proper CRTC states wired up
1056          * for atomic.
1057          */
1058         return crtc->active && crtc->base.primary->state->fb &&
1059                 crtc->config->hw.adjusted_mode.crtc_clock;
1060 }
1061
1062 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1063                                              enum pipe pipe)
1064 {
1065         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1066
1067         return crtc->config->cpu_transcoder;
1068 }
1069
1070 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1071                                     enum pipe pipe)
1072 {
1073         i915_reg_t reg = PIPEDSL(pipe);
1074         u32 line1, line2;
1075         u32 line_mask;
1076
1077         if (IS_GEN(dev_priv, 2))
1078                 line_mask = DSL_LINEMASK_GEN2;
1079         else
1080                 line_mask = DSL_LINEMASK_GEN3;
1081
1082         line1 = I915_READ(reg) & line_mask;
1083         msleep(5);
1084         line2 = I915_READ(reg) & line_mask;
1085
1086         return line1 != line2;
1087 }
1088
1089 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1090 {
1091         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092         enum pipe pipe = crtc->pipe;
1093
1094         /* Wait for the display line to settle/start moving */
1095         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1096                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1097                           pipe_name(pipe), onoff(state));
1098 }
1099
1100 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1101 {
1102         wait_for_pipe_scanline_moving(crtc, false);
1103 }
1104
1105 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1106 {
1107         wait_for_pipe_scanline_moving(crtc, true);
1108 }
1109
1110 static void
1111 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1112 {
1113         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1114         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1115
1116         if (INTEL_GEN(dev_priv) >= 4) {
1117                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1118                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1119
1120                 /* Wait for the Pipe State to go off */
1121                 if (intel_de_wait_for_clear(dev_priv, reg,
1122                                             I965_PIPECONF_ACTIVE, 100))
1123                         WARN(1, "pipe_off wait timed out\n");
1124         } else {
1125                 intel_wait_for_pipe_scanline_stopped(crtc);
1126         }
1127 }
1128
1129 /* Only for pre-ILK configs */
1130 void assert_pll(struct drm_i915_private *dev_priv,
1131                 enum pipe pipe, bool state)
1132 {
1133         u32 val;
1134         bool cur_state;
1135
1136         val = I915_READ(DPLL(pipe));
1137         cur_state = !!(val & DPLL_VCO_ENABLE);
1138         I915_STATE_WARN(cur_state != state,
1139              "PLL state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142
1143 /* XXX: the dsi pll is shared between MIPI DSI ports */
1144 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1145 {
1146         u32 val;
1147         bool cur_state;
1148
1149         vlv_cck_get(dev_priv);
1150         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1151         vlv_cck_put(dev_priv);
1152
1153         cur_state = val & DSI_PLL_VCO_EN;
1154         I915_STATE_WARN(cur_state != state,
1155              "DSI PLL state assertion failure (expected %s, current %s)\n",
1156                         onoff(state), onoff(cur_state));
1157 }
1158
1159 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1160                           enum pipe pipe, bool state)
1161 {
1162         bool cur_state;
1163         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1164                                                                       pipe);
1165
1166         if (HAS_DDI(dev_priv)) {
1167                 /* DDI does not have a specific FDI_TX register */
1168                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1169                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1170         } else {
1171                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1172                 cur_state = !!(val & FDI_TX_ENABLE);
1173         }
1174         I915_STATE_WARN(cur_state != state,
1175              "FDI TX state assertion failure (expected %s, current %s)\n",
1176                         onoff(state), onoff(cur_state));
1177 }
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180
1181 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182                           enum pipe pipe, bool state)
1183 {
1184         u32 val;
1185         bool cur_state;
1186
1187         val = I915_READ(FDI_RX_CTL(pipe));
1188         cur_state = !!(val & FDI_RX_ENABLE);
1189         I915_STATE_WARN(cur_state != state,
1190              "FDI RX state assertion failure (expected %s, current %s)\n",
1191                         onoff(state), onoff(cur_state));
1192 }
1193 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1194 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1195
1196 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1197                                       enum pipe pipe)
1198 {
1199         u32 val;
1200
1201         /* ILK FDI PLL is always enabled */
1202         if (IS_GEN(dev_priv, 5))
1203                 return;
1204
1205         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1206         if (HAS_DDI(dev_priv))
1207                 return;
1208
1209         val = I915_READ(FDI_TX_CTL(pipe));
1210         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1211 }
1212
1213 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1214                        enum pipe pipe, bool state)
1215 {
1216         u32 val;
1217         bool cur_state;
1218
1219         val = I915_READ(FDI_RX_CTL(pipe));
1220         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1221         I915_STATE_WARN(cur_state != state,
1222              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1223                         onoff(state), onoff(cur_state));
1224 }
1225
1226 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1227 {
1228         i915_reg_t pp_reg;
1229         u32 val;
1230         enum pipe panel_pipe = INVALID_PIPE;
1231         bool locked = true;
1232
1233         if (WARN_ON(HAS_DDI(dev_priv)))
1234                 return;
1235
1236         if (HAS_PCH_SPLIT(dev_priv)) {
1237                 u32 port_sel;
1238
1239                 pp_reg = PP_CONTROL(0);
1240                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1241
1242                 switch (port_sel) {
1243                 case PANEL_PORT_SELECT_LVDS:
1244                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1245                         break;
1246                 case PANEL_PORT_SELECT_DPA:
1247                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1248                         break;
1249                 case PANEL_PORT_SELECT_DPC:
1250                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1251                         break;
1252                 case PANEL_PORT_SELECT_DPD:
1253                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1254                         break;
1255                 default:
1256                         MISSING_CASE(port_sel);
1257                         break;
1258                 }
1259         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1260                 /* presumably write lock depends on pipe, not port select */
1261                 pp_reg = PP_CONTROL(pipe);
1262                 panel_pipe = pipe;
1263         } else {
1264                 u32 port_sel;
1265
1266                 pp_reg = PP_CONTROL(0);
1267                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1268
1269                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1270                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1271         }
1272
1273         val = I915_READ(pp_reg);
1274         if (!(val & PANEL_POWER_ON) ||
1275             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1276                 locked = false;
1277
1278         I915_STATE_WARN(panel_pipe == pipe && locked,
1279              "panel assertion failure, pipe %c regs locked\n",
1280              pipe_name(pipe));
1281 }
1282
1283 void assert_pipe(struct drm_i915_private *dev_priv,
1284                  enum pipe pipe, bool state)
1285 {
1286         bool cur_state;
1287         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1288                                                                       pipe);
1289         enum intel_display_power_domain power_domain;
1290         intel_wakeref_t wakeref;
1291
1292         /* we keep both pipes enabled on 830 */
1293         if (IS_I830(dev_priv))
1294                 state = true;
1295
1296         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1297         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1298         if (wakeref) {
1299                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1300                 cur_state = !!(val & PIPECONF_ENABLE);
1301
1302                 intel_display_power_put(dev_priv, power_domain, wakeref);
1303         } else {
1304                 cur_state = false;
1305         }
1306
1307         I915_STATE_WARN(cur_state != state,
1308              "pipe %c assertion failure (expected %s, current %s)\n",
1309                         pipe_name(pipe), onoff(state), onoff(cur_state));
1310 }
1311
1312 static void assert_plane(struct intel_plane *plane, bool state)
1313 {
1314         enum pipe pipe;
1315         bool cur_state;
1316
1317         cur_state = plane->get_hw_state(plane, &pipe);
1318
1319         I915_STATE_WARN(cur_state != state,
1320                         "%s assertion failure (expected %s, current %s)\n",
1321                         plane->base.name, onoff(state), onoff(cur_state));
1322 }
1323
1324 #define assert_plane_enabled(p) assert_plane(p, true)
1325 #define assert_plane_disabled(p) assert_plane(p, false)
1326
1327 static void assert_planes_disabled(struct intel_crtc *crtc)
1328 {
1329         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1330         struct intel_plane *plane;
1331
1332         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1333                 assert_plane_disabled(plane);
1334 }
1335
1336 static void assert_vblank_disabled(struct drm_crtc *crtc)
1337 {
1338         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1339                 drm_crtc_vblank_put(crtc);
1340 }
1341
1342 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1343                                     enum pipe pipe)
1344 {
1345         u32 val;
1346         bool enabled;
1347
1348         val = I915_READ(PCH_TRANSCONF(pipe));
1349         enabled = !!(val & TRANS_ENABLE);
1350         I915_STATE_WARN(enabled,
1351              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1352              pipe_name(pipe));
1353 }
1354
1355 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1356                                    enum pipe pipe, enum port port,
1357                                    i915_reg_t dp_reg)
1358 {
1359         enum pipe port_pipe;
1360         bool state;
1361
1362         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1363
1364         I915_STATE_WARN(state && port_pipe == pipe,
1365                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1366                         port_name(port), pipe_name(pipe));
1367
1368         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369                         "IBX PCH DP %c still using transcoder B\n",
1370                         port_name(port));
1371 }
1372
1373 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1374                                      enum pipe pipe, enum port port,
1375                                      i915_reg_t hdmi_reg)
1376 {
1377         enum pipe port_pipe;
1378         bool state;
1379
1380         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1381
1382         I915_STATE_WARN(state && port_pipe == pipe,
1383                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1384                         port_name(port), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1387                         "IBX PCH HDMI %c still using transcoder B\n",
1388                         port_name(port));
1389 }
1390
1391 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1392                                       enum pipe pipe)
1393 {
1394         enum pipe port_pipe;
1395
1396         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1397         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1398         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1399
1400         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1401                         port_pipe == pipe,
1402                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1403                         pipe_name(pipe));
1404
1405         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1406                         port_pipe == pipe,
1407                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1408                         pipe_name(pipe));
1409
1410         /* PCH SDVOB multiplex with HDMIB */
1411         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1412         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1413         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1414 }
1415
1416 static void _vlv_enable_pll(struct intel_crtc *crtc,
1417                             const struct intel_crtc_state *pipe_config)
1418 {
1419         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1420         enum pipe pipe = crtc->pipe;
1421
1422         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1423         POSTING_READ(DPLL(pipe));
1424         udelay(150);
1425
1426         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1427                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1428 }
1429
1430 static void vlv_enable_pll(struct intel_crtc *crtc,
1431                            const struct intel_crtc_state *pipe_config)
1432 {
1433         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1434         enum pipe pipe = crtc->pipe;
1435
1436         assert_pipe_disabled(dev_priv, pipe);
1437
1438         /* PLL is protected by panel, make sure we can write it */
1439         assert_panel_unlocked(dev_priv, pipe);
1440
1441         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1442                 _vlv_enable_pll(crtc, pipe_config);
1443
1444         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1445         POSTING_READ(DPLL_MD(pipe));
1446 }
1447
1448
1449 static void _chv_enable_pll(struct intel_crtc *crtc,
1450                             const struct intel_crtc_state *pipe_config)
1451 {
1452         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1453         enum pipe pipe = crtc->pipe;
1454         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1455         u32 tmp;
1456
1457         vlv_dpio_get(dev_priv);
1458
1459         /* Enable back the 10bit clock to display controller */
1460         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1461         tmp |= DPIO_DCLKP_EN;
1462         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1463
1464         vlv_dpio_put(dev_priv);
1465
1466         /*
1467          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1468          */
1469         udelay(1);
1470
1471         /* Enable PLL */
1472         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1473
1474         /* Check PLL is locked */
1475         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1476                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1477 }
1478
1479 static void chv_enable_pll(struct intel_crtc *crtc,
1480                            const struct intel_crtc_state *pipe_config)
1481 {
1482         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1483         enum pipe pipe = crtc->pipe;
1484
1485         assert_pipe_disabled(dev_priv, pipe);
1486
1487         /* PLL is protected by panel, make sure we can write it */
1488         assert_panel_unlocked(dev_priv, pipe);
1489
1490         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1491                 _chv_enable_pll(crtc, pipe_config);
1492
1493         if (pipe != PIPE_A) {
1494                 /*
1495                  * WaPixelRepeatModeFixForC0:chv
1496                  *
1497                  * DPLLCMD is AWOL. Use chicken bits to propagate
1498                  * the value from DPLLBMD to either pipe B or C.
1499                  */
1500                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1501                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1502                 I915_WRITE(CBR4_VLV, 0);
1503                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1504
1505                 /*
1506                  * DPLLB VGA mode also seems to cause problems.
1507                  * We should always have it disabled.
1508                  */
1509                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1510         } else {
1511                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1512                 POSTING_READ(DPLL_MD(pipe));
1513         }
1514 }
1515
1516 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1517 {
1518         if (IS_I830(dev_priv))
1519                 return false;
1520
1521         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1522 }
1523
1524 static void i9xx_enable_pll(struct intel_crtc *crtc,
1525                             const struct intel_crtc_state *crtc_state)
1526 {
1527         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1528         i915_reg_t reg = DPLL(crtc->pipe);
1529         u32 dpll = crtc_state->dpll_hw_state.dpll;
1530         int i;
1531
1532         assert_pipe_disabled(dev_priv, crtc->pipe);
1533
1534         /* PLL is protected by panel, make sure we can write it */
1535         if (i9xx_has_pps(dev_priv))
1536                 assert_panel_unlocked(dev_priv, crtc->pipe);
1537
1538         /*
1539          * Apparently we need to have VGA mode enabled prior to changing
1540          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1541          * dividers, even though the register value does change.
1542          */
1543         I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1544         I915_WRITE(reg, dpll);
1545
1546         /* Wait for the clocks to stabilize. */
1547         POSTING_READ(reg);
1548         udelay(150);
1549
1550         if (INTEL_GEN(dev_priv) >= 4) {
1551                 I915_WRITE(DPLL_MD(crtc->pipe),
1552                            crtc_state->dpll_hw_state.dpll_md);
1553         } else {
1554                 /* The pixel multiplier can only be updated once the
1555                  * DPLL is enabled and the clocks are stable.
1556                  *
1557                  * So write it again.
1558                  */
1559                 I915_WRITE(reg, dpll);
1560         }
1561
1562         /* We do this three times for luck */
1563         for (i = 0; i < 3; i++) {
1564                 I915_WRITE(reg, dpll);
1565                 POSTING_READ(reg);
1566                 udelay(150); /* wait for warmup */
1567         }
1568 }
1569
1570 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1571 {
1572         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1573         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574         enum pipe pipe = crtc->pipe;
1575
1576         /* Don't disable pipe or pipe PLLs if needed */
1577         if (IS_I830(dev_priv))
1578                 return;
1579
1580         /* Make sure the pipe isn't still relying on us */
1581         assert_pipe_disabled(dev_priv, pipe);
1582
1583         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1584         POSTING_READ(DPLL(pipe));
1585 }
1586
1587 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1588 {
1589         u32 val;
1590
1591         /* Make sure the pipe isn't still relying on us */
1592         assert_pipe_disabled(dev_priv, pipe);
1593
1594         val = DPLL_INTEGRATED_REF_CLK_VLV |
1595                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1596         if (pipe != PIPE_A)
1597                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1598
1599         I915_WRITE(DPLL(pipe), val);
1600         POSTING_READ(DPLL(pipe));
1601 }
1602
1603 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1604 {
1605         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1606         u32 val;
1607
1608         /* Make sure the pipe isn't still relying on us */
1609         assert_pipe_disabled(dev_priv, pipe);
1610
1611         val = DPLL_SSC_REF_CLK_CHV |
1612                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1613         if (pipe != PIPE_A)
1614                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1615
1616         I915_WRITE(DPLL(pipe), val);
1617         POSTING_READ(DPLL(pipe));
1618
1619         vlv_dpio_get(dev_priv);
1620
1621         /* Disable 10bit clock to display controller */
1622         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1623         val &= ~DPIO_DCLKP_EN;
1624         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1625
1626         vlv_dpio_put(dev_priv);
1627 }
1628
1629 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1630                          struct intel_digital_port *dport,
1631                          unsigned int expected_mask)
1632 {
1633         u32 port_mask;
1634         i915_reg_t dpll_reg;
1635
1636         switch (dport->base.port) {
1637         case PORT_B:
1638                 port_mask = DPLL_PORTB_READY_MASK;
1639                 dpll_reg = DPLL(0);
1640                 break;
1641         case PORT_C:
1642                 port_mask = DPLL_PORTC_READY_MASK;
1643                 dpll_reg = DPLL(0);
1644                 expected_mask <<= 4;
1645                 break;
1646         case PORT_D:
1647                 port_mask = DPLL_PORTD_READY_MASK;
1648                 dpll_reg = DPIO_PHY_STATUS;
1649                 break;
1650         default:
1651                 BUG();
1652         }
1653
1654         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1655                                        port_mask, expected_mask, 1000))
1656                 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1657                      dport->base.base.base.id, dport->base.base.name,
1658                      I915_READ(dpll_reg) & port_mask, expected_mask);
1659 }
1660
1661 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1662 {
1663         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1665         enum pipe pipe = crtc->pipe;
1666         i915_reg_t reg;
1667         u32 val, pipeconf_val;
1668
1669         /* Make sure PCH DPLL is enabled */
1670         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1671
1672         /* FDI must be feeding us bits for PCH ports */
1673         assert_fdi_tx_enabled(dev_priv, pipe);
1674         assert_fdi_rx_enabled(dev_priv, pipe);
1675
1676         if (HAS_PCH_CPT(dev_priv)) {
1677                 reg = TRANS_CHICKEN2(pipe);
1678                 val = I915_READ(reg);
1679                 /*
1680                  * Workaround: Set the timing override bit
1681                  * before enabling the pch transcoder.
1682                  */
1683                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1684                 /* Configure frame start delay to match the CPU */
1685                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1686                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1687                 I915_WRITE(reg, val);
1688         }
1689
1690         reg = PCH_TRANSCONF(pipe);
1691         val = I915_READ(reg);
1692         pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694         if (HAS_PCH_IBX(dev_priv)) {
1695                 /* Configure frame start delay to match the CPU */
1696                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1697                 val |= TRANS_FRAME_START_DELAY(0);
1698
1699                 /*
1700                  * Make the BPC in transcoder be consistent with
1701                  * that in pipeconf reg. For HDMI we must use 8bpc
1702                  * here for both 8bpc and 12bpc.
1703                  */
1704                 val &= ~PIPECONF_BPC_MASK;
1705                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1706                         val |= PIPECONF_8BPC;
1707                 else
1708                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1709         }
1710
1711         val &= ~TRANS_INTERLACE_MASK;
1712         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1713                 if (HAS_PCH_IBX(dev_priv) &&
1714                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1715                         val |= TRANS_LEGACY_INTERLACED_ILK;
1716                 else
1717                         val |= TRANS_INTERLACED;
1718         } else {
1719                 val |= TRANS_PROGRESSIVE;
1720         }
1721
1722         I915_WRITE(reg, val | TRANS_ENABLE);
1723         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1724                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1725 }
1726
1727 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1728                                       enum transcoder cpu_transcoder)
1729 {
1730         u32 val, pipeconf_val;
1731
1732         /* FDI must be feeding us bits for PCH ports */
1733         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1734         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1735
1736         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1737         /* Workaround: set timing override bit. */
1738         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1739         /* Configure frame start delay to match the CPU */
1740         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1741         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1742         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1743
1744         val = TRANS_ENABLE;
1745         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1746
1747         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1748             PIPECONF_INTERLACED_ILK)
1749                 val |= TRANS_INTERLACED;
1750         else
1751                 val |= TRANS_PROGRESSIVE;
1752
1753         I915_WRITE(LPT_TRANSCONF, val);
1754         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1755                                   TRANS_STATE_ENABLE, 100))
1756                 DRM_ERROR("Failed to enable PCH transcoder\n");
1757 }
1758
1759 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1760                                             enum pipe pipe)
1761 {
1762         i915_reg_t reg;
1763         u32 val;
1764
1765         /* FDI relies on the transcoder */
1766         assert_fdi_tx_disabled(dev_priv, pipe);
1767         assert_fdi_rx_disabled(dev_priv, pipe);
1768
1769         /* Ports must be off as well */
1770         assert_pch_ports_disabled(dev_priv, pipe);
1771
1772         reg = PCH_TRANSCONF(pipe);
1773         val = I915_READ(reg);
1774         val &= ~TRANS_ENABLE;
1775         I915_WRITE(reg, val);
1776         /* wait for PCH transcoder off, transcoder state */
1777         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1778                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1779
1780         if (HAS_PCH_CPT(dev_priv)) {
1781                 /* Workaround: Clear the timing override chicken bit again. */
1782                 reg = TRANS_CHICKEN2(pipe);
1783                 val = I915_READ(reg);
1784                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1785                 I915_WRITE(reg, val);
1786         }
1787 }
1788
1789 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1790 {
1791         u32 val;
1792
1793         val = I915_READ(LPT_TRANSCONF);
1794         val &= ~TRANS_ENABLE;
1795         I915_WRITE(LPT_TRANSCONF, val);
1796         /* wait for PCH transcoder off, transcoder state */
1797         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1798                                     TRANS_STATE_ENABLE, 50))
1799                 DRM_ERROR("Failed to disable PCH transcoder\n");
1800
1801         /* Workaround: clear timing override bit. */
1802         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1803         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1804         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1805 }
1806
1807 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1808 {
1809         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1810
1811         if (HAS_PCH_LPT(dev_priv))
1812                 return PIPE_A;
1813         else
1814                 return crtc->pipe;
1815 }
1816
1817 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1818 {
1819         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1820
1821         /*
1822          * On i965gm the hardware frame counter reads
1823          * zero when the TV encoder is enabled :(
1824          */
1825         if (IS_I965GM(dev_priv) &&
1826             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1827                 return 0;
1828
1829         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1830                 return 0xffffffff; /* full 32 bit counter */
1831         else if (INTEL_GEN(dev_priv) >= 3)
1832                 return 0xffffff; /* only 24 bits of frame count */
1833         else
1834                 return 0; /* Gen2 doesn't have a hardware frame counter */
1835 }
1836
1837 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1838 {
1839         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1840
1841         assert_vblank_disabled(&crtc->base);
1842         drm_crtc_set_max_vblank_count(&crtc->base,
1843                                       intel_crtc_max_vblank_count(crtc_state));
1844         drm_crtc_vblank_on(&crtc->base);
1845 }
1846
1847 static void intel_crtc_vblank_off(struct intel_crtc *crtc)
1848 {
1849         drm_crtc_vblank_off(&crtc->base);
1850         assert_vblank_disabled(&crtc->base);
1851 }
1852
1853 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1854 {
1855         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1856         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1857         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1858         enum pipe pipe = crtc->pipe;
1859         i915_reg_t reg;
1860         u32 val;
1861
1862         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1863
1864         assert_planes_disabled(crtc);
1865
1866         /*
1867          * A pipe without a PLL won't actually be able to drive bits from
1868          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1869          * need the check.
1870          */
1871         if (HAS_GMCH(dev_priv)) {
1872                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1873                         assert_dsi_pll_enabled(dev_priv);
1874                 else
1875                         assert_pll_enabled(dev_priv, pipe);
1876         } else {
1877                 if (new_crtc_state->has_pch_encoder) {
1878                         /* if driving the PCH, we need FDI enabled */
1879                         assert_fdi_rx_pll_enabled(dev_priv,
1880                                                   intel_crtc_pch_transcoder(crtc));
1881                         assert_fdi_tx_pll_enabled(dev_priv,
1882                                                   (enum pipe) cpu_transcoder);
1883                 }
1884                 /* FIXME: assert CPU port conditions for SNB+ */
1885         }
1886
1887         trace_intel_pipe_enable(crtc);
1888
1889         reg = PIPECONF(cpu_transcoder);
1890         val = I915_READ(reg);
1891         if (val & PIPECONF_ENABLE) {
1892                 /* we keep both pipes enabled on 830 */
1893                 WARN_ON(!IS_I830(dev_priv));
1894                 return;
1895         }
1896
1897         I915_WRITE(reg, val | PIPECONF_ENABLE);
1898         POSTING_READ(reg);
1899
1900         /*
1901          * Until the pipe starts PIPEDSL reads will return a stale value,
1902          * which causes an apparent vblank timestamp jump when PIPEDSL
1903          * resets to its proper value. That also messes up the frame count
1904          * when it's derived from the timestamps. So let's wait for the
1905          * pipe to start properly before we call drm_crtc_vblank_on()
1906          */
1907         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1908                 intel_wait_for_pipe_scanline_moving(crtc);
1909 }
1910
1911 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1912 {
1913         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1914         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1915         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1916         enum pipe pipe = crtc->pipe;
1917         i915_reg_t reg;
1918         u32 val;
1919
1920         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1921
1922         /*
1923          * Make sure planes won't keep trying to pump pixels to us,
1924          * or we might hang the display.
1925          */
1926         assert_planes_disabled(crtc);
1927
1928         trace_intel_pipe_disable(crtc);
1929
1930         reg = PIPECONF(cpu_transcoder);
1931         val = I915_READ(reg);
1932         if ((val & PIPECONF_ENABLE) == 0)
1933                 return;
1934
1935         /*
1936          * Double wide has implications for planes
1937          * so best keep it disabled when not needed.
1938          */
1939         if (old_crtc_state->double_wide)
1940                 val &= ~PIPECONF_DOUBLE_WIDE;
1941
1942         /* Don't disable pipe or pipe PLLs if needed */
1943         if (!IS_I830(dev_priv))
1944                 val &= ~PIPECONF_ENABLE;
1945
1946         I915_WRITE(reg, val);
1947         if ((val & PIPECONF_ENABLE) == 0)
1948                 intel_wait_for_pipe_off(old_crtc_state);
1949 }
1950
1951 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1952 {
1953         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1954 }
1955
1956 static unsigned int
1957 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1958 {
1959         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1960         unsigned int cpp = fb->format->cpp[color_plane];
1961
1962         switch (fb->modifier) {
1963         case DRM_FORMAT_MOD_LINEAR:
1964                 return intel_tile_size(dev_priv);
1965         case I915_FORMAT_MOD_X_TILED:
1966                 if (IS_GEN(dev_priv, 2))
1967                         return 128;
1968                 else
1969                         return 512;
1970         case I915_FORMAT_MOD_Y_TILED_CCS:
1971                 if (color_plane == 1)
1972                         return 128;
1973                 /* fall through */
1974         case I915_FORMAT_MOD_Y_TILED:
1975                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1976                         return 128;
1977                 else
1978                         return 512;
1979         case I915_FORMAT_MOD_Yf_TILED_CCS:
1980                 if (color_plane == 1)
1981                         return 128;
1982                 /* fall through */
1983         case I915_FORMAT_MOD_Yf_TILED:
1984                 switch (cpp) {
1985                 case 1:
1986                         return 64;
1987                 case 2:
1988                 case 4:
1989                         return 128;
1990                 case 8:
1991                 case 16:
1992                         return 256;
1993                 default:
1994                         MISSING_CASE(cpp);
1995                         return cpp;
1996                 }
1997                 break;
1998         default:
1999                 MISSING_CASE(fb->modifier);
2000                 return cpp;
2001         }
2002 }
2003
2004 static unsigned int
2005 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2006 {
2007         return intel_tile_size(to_i915(fb->dev)) /
2008                 intel_tile_width_bytes(fb, color_plane);
2009 }
2010
2011 /* Return the tile dimensions in pixel units */
2012 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2013                             unsigned int *tile_width,
2014                             unsigned int *tile_height)
2015 {
2016         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2017         unsigned int cpp = fb->format->cpp[color_plane];
2018
2019         *tile_width = tile_width_bytes / cpp;
2020         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2021 }
2022
2023 unsigned int
2024 intel_fb_align_height(const struct drm_framebuffer *fb,
2025                       int color_plane, unsigned int height)
2026 {
2027         unsigned int tile_height = intel_tile_height(fb, color_plane);
2028
2029         return ALIGN(height, tile_height);
2030 }
2031
2032 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2033 {
2034         unsigned int size = 0;
2035         int i;
2036
2037         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2038                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2039
2040         return size;
2041 }
2042
2043 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2044 {
2045         unsigned int size = 0;
2046         int i;
2047
2048         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2049                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2050
2051         return size;
2052 }
2053
2054 static void
2055 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2056                         const struct drm_framebuffer *fb,
2057                         unsigned int rotation)
2058 {
2059         view->type = I915_GGTT_VIEW_NORMAL;
2060         if (drm_rotation_90_or_270(rotation)) {
2061                 view->type = I915_GGTT_VIEW_ROTATED;
2062                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2063         }
2064 }
2065
2066 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2067 {
2068         if (IS_I830(dev_priv))
2069                 return 16 * 1024;
2070         else if (IS_I85X(dev_priv))
2071                 return 256;
2072         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2073                 return 32;
2074         else
2075                 return 4 * 1024;
2076 }
2077
2078 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2079 {
2080         if (INTEL_GEN(dev_priv) >= 9)
2081                 return 256 * 1024;
2082         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2083                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2084                 return 128 * 1024;
2085         else if (INTEL_GEN(dev_priv) >= 4)
2086                 return 4 * 1024;
2087         else
2088                 return 0;
2089 }
2090
2091 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2092                                          int color_plane)
2093 {
2094         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2095
2096         /* AUX_DIST needs only 4K alignment */
2097         if (color_plane == 1)
2098                 return 4096;
2099
2100         switch (fb->modifier) {
2101         case DRM_FORMAT_MOD_LINEAR:
2102                 return intel_linear_alignment(dev_priv);
2103         case I915_FORMAT_MOD_X_TILED:
2104                 if (INTEL_GEN(dev_priv) >= 9)
2105                         return 256 * 1024;
2106                 return 0;
2107         case I915_FORMAT_MOD_Y_TILED_CCS:
2108         case I915_FORMAT_MOD_Yf_TILED_CCS:
2109         case I915_FORMAT_MOD_Y_TILED:
2110         case I915_FORMAT_MOD_Yf_TILED:
2111                 return 1 * 1024 * 1024;
2112         default:
2113                 MISSING_CASE(fb->modifier);
2114                 return 0;
2115         }
2116 }
2117
2118 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2119 {
2120         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2121         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2122
2123         return INTEL_GEN(dev_priv) < 4 ||
2124                 (plane->has_fbc &&
2125                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2126 }
2127
2128 struct i915_vma *
2129 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2130                            const struct i915_ggtt_view *view,
2131                            bool uses_fence,
2132                            unsigned long *out_flags)
2133 {
2134         struct drm_device *dev = fb->dev;
2135         struct drm_i915_private *dev_priv = to_i915(dev);
2136         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2137         intel_wakeref_t wakeref;
2138         struct i915_vma *vma;
2139         unsigned int pinctl;
2140         u32 alignment;
2141
2142         if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2143                 return ERR_PTR(-EINVAL);
2144
2145         alignment = intel_surf_alignment(fb, 0);
2146
2147         /* Note that the w/a also requires 64 PTE of padding following the
2148          * bo. We currently fill all unused PTE with the shadow page and so
2149          * we should always have valid PTE following the scanout preventing
2150          * the VT-d warning.
2151          */
2152         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2153                 alignment = 256 * 1024;
2154
2155         /*
2156          * Global gtt pte registers are special registers which actually forward
2157          * writes to a chunk of system memory. Which means that there is no risk
2158          * that the register values disappear as soon as we call
2159          * intel_runtime_pm_put(), so it is correct to wrap only the
2160          * pin/unpin/fence and not more.
2161          */
2162         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2163         i915_gem_object_lock(obj);
2164
2165         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2166
2167         pinctl = 0;
2168
2169         /* Valleyview is definitely limited to scanning out the first
2170          * 512MiB. Lets presume this behaviour was inherited from the
2171          * g4x display engine and that all earlier gen are similarly
2172          * limited. Testing suggests that it is a little more
2173          * complicated than this. For example, Cherryview appears quite
2174          * happy to scanout from anywhere within its global aperture.
2175          */
2176         if (HAS_GMCH(dev_priv))
2177                 pinctl |= PIN_MAPPABLE;
2178
2179         vma = i915_gem_object_pin_to_display_plane(obj,
2180                                                    alignment, view, pinctl);
2181         if (IS_ERR(vma))
2182                 goto err;
2183
2184         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2185                 int ret;
2186
2187                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2188                  * fence, whereas 965+ only requires a fence if using
2189                  * framebuffer compression.  For simplicity, we always, when
2190                  * possible, install a fence as the cost is not that onerous.
2191                  *
2192                  * If we fail to fence the tiled scanout, then either the
2193                  * modeset will reject the change (which is highly unlikely as
2194                  * the affected systems, all but one, do not have unmappable
2195                  * space) or we will not be able to enable full powersaving
2196                  * techniques (also likely not to apply due to various limits
2197                  * FBC and the like impose on the size of the buffer, which
2198                  * presumably we violated anyway with this unmappable buffer).
2199                  * Anyway, it is presumably better to stumble onwards with
2200                  * something and try to run the system in a "less than optimal"
2201                  * mode that matches the user configuration.
2202                  */
2203                 ret = i915_vma_pin_fence(vma);
2204                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2205                         i915_gem_object_unpin_from_display_plane(vma);
2206                         vma = ERR_PTR(ret);
2207                         goto err;
2208                 }
2209
2210                 if (ret == 0 && vma->fence)
2211                         *out_flags |= PLANE_HAS_FENCE;
2212         }
2213
2214         i915_vma_get(vma);
2215 err:
2216         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2217
2218         i915_gem_object_unlock(obj);
2219         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2220         return vma;
2221 }
2222
2223 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2224 {
2225         i915_gem_object_lock(vma->obj);
2226         if (flags & PLANE_HAS_FENCE)
2227                 i915_vma_unpin_fence(vma);
2228         i915_gem_object_unpin_from_display_plane(vma);
2229         i915_gem_object_unlock(vma->obj);
2230
2231         i915_vma_put(vma);
2232 }
2233
2234 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2235                           unsigned int rotation)
2236 {
2237         if (drm_rotation_90_or_270(rotation))
2238                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2239         else
2240                 return fb->pitches[color_plane];
2241 }
2242
2243 /*
2244  * Convert the x/y offsets into a linear offset.
2245  * Only valid with 0/180 degree rotation, which is fine since linear
2246  * offset is only used with linear buffers on pre-hsw and tiled buffers
2247  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2248  */
2249 u32 intel_fb_xy_to_linear(int x, int y,
2250                           const struct intel_plane_state *state,
2251                           int color_plane)
2252 {
2253         const struct drm_framebuffer *fb = state->hw.fb;
2254         unsigned int cpp = fb->format->cpp[color_plane];
2255         unsigned int pitch = state->color_plane[color_plane].stride;
2256
2257         return y * pitch + x * cpp;
2258 }
2259
2260 /*
2261  * Add the x/y offsets derived from fb->offsets[] to the user
2262  * specified plane src x/y offsets. The resulting x/y offsets
2263  * specify the start of scanout from the beginning of the gtt mapping.
2264  */
2265 void intel_add_fb_offsets(int *x, int *y,
2266                           const struct intel_plane_state *state,
2267                           int color_plane)
2268
2269 {
2270         *x += state->color_plane[color_plane].x;
2271         *y += state->color_plane[color_plane].y;
2272 }
2273
2274 static u32 intel_adjust_tile_offset(int *x, int *y,
2275                                     unsigned int tile_width,
2276                                     unsigned int tile_height,
2277                                     unsigned int tile_size,
2278                                     unsigned int pitch_tiles,
2279                                     u32 old_offset,
2280                                     u32 new_offset)
2281 {
2282         unsigned int pitch_pixels = pitch_tiles * tile_width;
2283         unsigned int tiles;
2284
2285         WARN_ON(old_offset & (tile_size - 1));
2286         WARN_ON(new_offset & (tile_size - 1));
2287         WARN_ON(new_offset > old_offset);
2288
2289         tiles = (old_offset - new_offset) / tile_size;
2290
2291         *y += tiles / pitch_tiles * tile_height;
2292         *x += tiles % pitch_tiles * tile_width;
2293
2294         /* minimize x in case it got needlessly big */
2295         *y += *x / pitch_pixels * tile_height;
2296         *x %= pitch_pixels;
2297
2298         return new_offset;
2299 }
2300
2301 static bool is_surface_linear(u64 modifier, int color_plane)
2302 {
2303         return modifier == DRM_FORMAT_MOD_LINEAR;
2304 }
2305
2306 static u32 intel_adjust_aligned_offset(int *x, int *y,
2307                                        const struct drm_framebuffer *fb,
2308                                        int color_plane,
2309                                        unsigned int rotation,
2310                                        unsigned int pitch,
2311                                        u32 old_offset, u32 new_offset)
2312 {
2313         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2314         unsigned int cpp = fb->format->cpp[color_plane];
2315
2316         WARN_ON(new_offset > old_offset);
2317
2318         if (!is_surface_linear(fb->modifier, color_plane)) {
2319                 unsigned int tile_size, tile_width, tile_height;
2320                 unsigned int pitch_tiles;
2321
2322                 tile_size = intel_tile_size(dev_priv);
2323                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2324
2325                 if (drm_rotation_90_or_270(rotation)) {
2326                         pitch_tiles = pitch / tile_height;
2327                         swap(tile_width, tile_height);
2328                 } else {
2329                         pitch_tiles = pitch / (tile_width * cpp);
2330                 }
2331
2332                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2333                                          tile_size, pitch_tiles,
2334                                          old_offset, new_offset);
2335         } else {
2336                 old_offset += *y * pitch + *x * cpp;
2337
2338                 *y = (old_offset - new_offset) / pitch;
2339                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2340         }
2341
2342         return new_offset;
2343 }
2344
2345 /*
2346  * Adjust the tile offset by moving the difference into
2347  * the x/y offsets.
2348  */
2349 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2350                                              const struct intel_plane_state *state,
2351                                              int color_plane,
2352                                              u32 old_offset, u32 new_offset)
2353 {
2354         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2355                                            state->hw.rotation,
2356                                            state->color_plane[color_plane].stride,
2357                                            old_offset, new_offset);
2358 }
2359
2360 /*
2361  * Computes the aligned offset to the base tile and adjusts
2362  * x, y. bytes per pixel is assumed to be a power-of-two.
2363  *
2364  * In the 90/270 rotated case, x and y are assumed
2365  * to be already rotated to match the rotated GTT view, and
2366  * pitch is the tile_height aligned framebuffer height.
2367  *
2368  * This function is used when computing the derived information
2369  * under intel_framebuffer, so using any of that information
2370  * here is not allowed. Anything under drm_framebuffer can be
2371  * used. This is why the user has to pass in the pitch since it
2372  * is specified in the rotated orientation.
2373  */
2374 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2375                                         int *x, int *y,
2376                                         const struct drm_framebuffer *fb,
2377                                         int color_plane,
2378                                         unsigned int pitch,
2379                                         unsigned int rotation,
2380                                         u32 alignment)
2381 {
2382         unsigned int cpp = fb->format->cpp[color_plane];
2383         u32 offset, offset_aligned;
2384
2385         if (alignment)
2386                 alignment--;
2387
2388         if (!is_surface_linear(fb->modifier, color_plane)) {
2389                 unsigned int tile_size, tile_width, tile_height;
2390                 unsigned int tile_rows, tiles, pitch_tiles;
2391
2392                 tile_size = intel_tile_size(dev_priv);
2393                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2394
2395                 if (drm_rotation_90_or_270(rotation)) {
2396                         pitch_tiles = pitch / tile_height;
2397                         swap(tile_width, tile_height);
2398                 } else {
2399                         pitch_tiles = pitch / (tile_width * cpp);
2400                 }
2401
2402                 tile_rows = *y / tile_height;
2403                 *y %= tile_height;
2404
2405                 tiles = *x / tile_width;
2406                 *x %= tile_width;
2407
2408                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2409                 offset_aligned = offset & ~alignment;
2410
2411                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2412                                          tile_size, pitch_tiles,
2413                                          offset, offset_aligned);
2414         } else {
2415                 offset = *y * pitch + *x * cpp;
2416                 offset_aligned = offset & ~alignment;
2417
2418                 *y = (offset & alignment) / pitch;
2419                 *x = ((offset & alignment) - *y * pitch) / cpp;
2420         }
2421
2422         return offset_aligned;
2423 }
2424
2425 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2426                                               const struct intel_plane_state *state,
2427                                               int color_plane)
2428 {
2429         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2430         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2431         const struct drm_framebuffer *fb = state->hw.fb;
2432         unsigned int rotation = state->hw.rotation;
2433         int pitch = state->color_plane[color_plane].stride;
2434         u32 alignment;
2435
2436         if (intel_plane->id == PLANE_CURSOR)
2437                 alignment = intel_cursor_alignment(dev_priv);
2438         else
2439                 alignment = intel_surf_alignment(fb, color_plane);
2440
2441         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2442                                             pitch, rotation, alignment);
2443 }
2444
2445 /* Convert the fb->offset[] into x/y offsets */
2446 static int intel_fb_offset_to_xy(int *x, int *y,
2447                                  const struct drm_framebuffer *fb,
2448                                  int color_plane)
2449 {
2450         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2451         unsigned int height;
2452
2453         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2454             fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2455                 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2456                               fb->offsets[color_plane], color_plane);
2457                 return -EINVAL;
2458         }
2459
2460         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2461         height = ALIGN(height, intel_tile_height(fb, color_plane));
2462
2463         /* Catch potential overflows early */
2464         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2465                             fb->offsets[color_plane])) {
2466                 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2467                               fb->offsets[color_plane], fb->pitches[color_plane],
2468                               color_plane);
2469                 return -ERANGE;
2470         }
2471
2472         *x = 0;
2473         *y = 0;
2474
2475         intel_adjust_aligned_offset(x, y,
2476                                     fb, color_plane, DRM_MODE_ROTATE_0,
2477                                     fb->pitches[color_plane],
2478                                     fb->offsets[color_plane], 0);
2479
2480         return 0;
2481 }
2482
2483 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2484 {
2485         switch (fb_modifier) {
2486         case I915_FORMAT_MOD_X_TILED:
2487                 return I915_TILING_X;
2488         case I915_FORMAT_MOD_Y_TILED:
2489         case I915_FORMAT_MOD_Y_TILED_CCS:
2490                 return I915_TILING_Y;
2491         default:
2492                 return I915_TILING_NONE;
2493         }
2494 }
2495
2496 /*
2497  * From the Sky Lake PRM:
2498  * "The Color Control Surface (CCS) contains the compression status of
2499  *  the cache-line pairs. The compression state of the cache-line pair
2500  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2501  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2502  *  cache-line-pairs. CCS is always Y tiled."
2503  *
2504  * Since cache line pairs refers to horizontally adjacent cache lines,
2505  * each cache line in the CCS corresponds to an area of 32x16 cache
2506  * lines on the main surface. Since each pixel is 4 bytes, this gives
2507  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2508  * main surface.
2509  */
2510 static const struct drm_format_info ccs_formats[] = {
2511         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2512           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2513         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2514           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2515         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2516           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2517         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2518           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2519 };
2520
2521 static const struct drm_format_info *
2522 lookup_format_info(const struct drm_format_info formats[],
2523                    int num_formats, u32 format)
2524 {
2525         int i;
2526
2527         for (i = 0; i < num_formats; i++) {
2528                 if (formats[i].format == format)
2529                         return &formats[i];
2530         }
2531
2532         return NULL;
2533 }
2534
2535 static const struct drm_format_info *
2536 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2537 {
2538         switch (cmd->modifier[0]) {
2539         case I915_FORMAT_MOD_Y_TILED_CCS:
2540         case I915_FORMAT_MOD_Yf_TILED_CCS:
2541                 return lookup_format_info(ccs_formats,
2542                                           ARRAY_SIZE(ccs_formats),
2543                                           cmd->pixel_format);
2544         default:
2545                 return NULL;
2546         }
2547 }
2548
2549 bool is_ccs_modifier(u64 modifier)
2550 {
2551         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2552                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2553 }
2554
2555 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2556                               u32 pixel_format, u64 modifier)
2557 {
2558         struct intel_crtc *crtc;
2559         struct intel_plane *plane;
2560
2561         /*
2562          * We assume the primary plane for pipe A has
2563          * the highest stride limits of them all.
2564          */
2565         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2566         if (!crtc)
2567                 return 0;
2568
2569         plane = to_intel_plane(crtc->base.primary);
2570
2571         return plane->max_stride(plane, pixel_format, modifier,
2572                                  DRM_MODE_ROTATE_0);
2573 }
2574
2575 static
2576 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2577                         u32 pixel_format, u64 modifier)
2578 {
2579         /*
2580          * Arbitrary limit for gen4+ chosen to match the
2581          * render engine max stride.
2582          *
2583          * The new CCS hash mode makes remapping impossible
2584          */
2585         if (!is_ccs_modifier(modifier)) {
2586                 if (INTEL_GEN(dev_priv) >= 7)
2587                         return 256*1024;
2588                 else if (INTEL_GEN(dev_priv) >= 4)
2589                         return 128*1024;
2590         }
2591
2592         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2593 }
2594
2595 static u32
2596 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2597 {
2598         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2599
2600         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2601                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2602                                                            fb->format->format,
2603                                                            fb->modifier);
2604
2605                 /*
2606                  * To make remapping with linear generally feasible
2607                  * we need the stride to be page aligned.
2608                  */
2609                 if (fb->pitches[color_plane] > max_stride)
2610                         return intel_tile_size(dev_priv);
2611                 else
2612                         return 64;
2613         } else {
2614                 return intel_tile_width_bytes(fb, color_plane);
2615         }
2616 }
2617
2618 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2619 {
2620         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2621         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2622         const struct drm_framebuffer *fb = plane_state->hw.fb;
2623         int i;
2624
2625         /* We don't want to deal with remapping with cursors */
2626         if (plane->id == PLANE_CURSOR)
2627                 return false;
2628
2629         /*
2630          * The display engine limits already match/exceed the
2631          * render engine limits, so not much point in remapping.
2632          * Would also need to deal with the fence POT alignment
2633          * and gen2 2KiB GTT tile size.
2634          */
2635         if (INTEL_GEN(dev_priv) < 4)
2636                 return false;
2637
2638         /*
2639          * The new CCS hash mode isn't compatible with remapping as
2640          * the virtual address of the pages affects the compressed data.
2641          */
2642         if (is_ccs_modifier(fb->modifier))
2643                 return false;
2644
2645         /* Linear needs a page aligned stride for remapping */
2646         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2647                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2648
2649                 for (i = 0; i < fb->format->num_planes; i++) {
2650                         if (fb->pitches[i] & alignment)
2651                                 return false;
2652                 }
2653         }
2654
2655         return true;
2656 }
2657
2658 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2659 {
2660         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2661         const struct drm_framebuffer *fb = plane_state->hw.fb;
2662         unsigned int rotation = plane_state->hw.rotation;
2663         u32 stride, max_stride;
2664
2665         /*
2666          * No remapping for invisible planes since we don't have
2667          * an actual source viewport to remap.
2668          */
2669         if (!plane_state->uapi.visible)
2670                 return false;
2671
2672         if (!intel_plane_can_remap(plane_state))
2673                 return false;
2674
2675         /*
2676          * FIXME: aux plane limits on gen9+ are
2677          * unclear in Bspec, for now no checking.
2678          */
2679         stride = intel_fb_pitch(fb, 0, rotation);
2680         max_stride = plane->max_stride(plane, fb->format->format,
2681                                        fb->modifier, rotation);
2682
2683         return stride > max_stride;
2684 }
2685
2686 static int
2687 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2688                    struct drm_framebuffer *fb)
2689 {
2690         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2691         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2692         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2693         u32 gtt_offset_rotated = 0;
2694         unsigned int max_size = 0;
2695         int i, num_planes = fb->format->num_planes;
2696         unsigned int tile_size = intel_tile_size(dev_priv);
2697
2698         for (i = 0; i < num_planes; i++) {
2699                 unsigned int width, height;
2700                 unsigned int cpp, size;
2701                 u32 offset;
2702                 int x, y;
2703                 int ret;
2704
2705                 cpp = fb->format->cpp[i];
2706                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2707                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2708
2709                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2710                 if (ret) {
2711                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2712                                       i, fb->offsets[i]);
2713                         return ret;
2714                 }
2715
2716                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2717                         int hsub = fb->format->hsub;
2718                         int vsub = fb->format->vsub;
2719                         int tile_width, tile_height;
2720                         int main_x, main_y;
2721                         int ccs_x, ccs_y;
2722
2723                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2724                         tile_width *= hsub;
2725                         tile_height *= vsub;
2726
2727                         ccs_x = (x * hsub) % tile_width;
2728                         ccs_y = (y * vsub) % tile_height;
2729                         main_x = intel_fb->normal[0].x % tile_width;
2730                         main_y = intel_fb->normal[0].y % tile_height;
2731
2732                         /*
2733                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2734                          * x/y offsets must match between CCS and the main surface.
2735                          */
2736                         if (main_x != ccs_x || main_y != ccs_y) {
2737                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2738                                               main_x, main_y,
2739                                               ccs_x, ccs_y,
2740                                               intel_fb->normal[0].x,
2741                                               intel_fb->normal[0].y,
2742                                               x, y);
2743                                 return -EINVAL;
2744                         }
2745                 }
2746
2747                 /*
2748                  * The fence (if used) is aligned to the start of the object
2749                  * so having the framebuffer wrap around across the edge of the
2750                  * fenced region doesn't really work. We have no API to configure
2751                  * the fence start offset within the object (nor could we probably
2752                  * on gen2/3). So it's just easier if we just require that the
2753                  * fb layout agrees with the fence layout. We already check that the
2754                  * fb stride matches the fence stride elsewhere.
2755                  */
2756                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2757                     (x + width) * cpp > fb->pitches[i]) {
2758                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2759                                       i, fb->offsets[i]);
2760                         return -EINVAL;
2761                 }
2762
2763                 /*
2764                  * First pixel of the framebuffer from
2765                  * the start of the normal gtt mapping.
2766                  */
2767                 intel_fb->normal[i].x = x;
2768                 intel_fb->normal[i].y = y;
2769
2770                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2771                                                       fb->pitches[i],
2772                                                       DRM_MODE_ROTATE_0,
2773                                                       tile_size);
2774                 offset /= tile_size;
2775
2776                 if (!is_surface_linear(fb->modifier, i)) {
2777                         unsigned int tile_width, tile_height;
2778                         unsigned int pitch_tiles;
2779                         struct drm_rect r;
2780
2781                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2782
2783                         rot_info->plane[i].offset = offset;
2784                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2785                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2786                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2787
2788                         intel_fb->rotated[i].pitch =
2789                                 rot_info->plane[i].height * tile_height;
2790
2791                         /* how many tiles does this plane need */
2792                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2793                         /*
2794                          * If the plane isn't horizontally tile aligned,
2795                          * we need one more tile.
2796                          */
2797                         if (x != 0)
2798                                 size++;
2799
2800                         /* rotate the x/y offsets to match the GTT view */
2801                         drm_rect_init(&r, x, y, width, height);
2802                         drm_rect_rotate(&r,
2803                                         rot_info->plane[i].width * tile_width,
2804                                         rot_info->plane[i].height * tile_height,
2805                                         DRM_MODE_ROTATE_270);
2806                         x = r.x1;
2807                         y = r.y1;
2808
2809                         /* rotate the tile dimensions to match the GTT view */
2810                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2811                         swap(tile_width, tile_height);
2812
2813                         /*
2814                          * We only keep the x/y offsets, so push all of the
2815                          * gtt offset into the x/y offsets.
2816                          */
2817                         intel_adjust_tile_offset(&x, &y,
2818                                                  tile_width, tile_height,
2819                                                  tile_size, pitch_tiles,
2820                                                  gtt_offset_rotated * tile_size, 0);
2821
2822                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2823
2824                         /*
2825                          * First pixel of the framebuffer from
2826                          * the start of the rotated gtt mapping.
2827                          */
2828                         intel_fb->rotated[i].x = x;
2829                         intel_fb->rotated[i].y = y;
2830                 } else {
2831                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2832                                             x * cpp, tile_size);
2833                 }
2834
2835                 /* how many tiles in total needed in the bo */
2836                 max_size = max(max_size, offset + size);
2837         }
2838
2839         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2840                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2841                               mul_u32_u32(max_size, tile_size), obj->base.size);
2842                 return -EINVAL;
2843         }
2844
2845         return 0;
2846 }
2847
2848 static void
2849 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2850 {
2851         struct drm_i915_private *dev_priv =
2852                 to_i915(plane_state->uapi.plane->dev);
2853         struct drm_framebuffer *fb = plane_state->hw.fb;
2854         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2855         struct intel_rotation_info *info = &plane_state->view.rotated;
2856         unsigned int rotation = plane_state->hw.rotation;
2857         int i, num_planes = fb->format->num_planes;
2858         unsigned int tile_size = intel_tile_size(dev_priv);
2859         unsigned int src_x, src_y;
2860         unsigned int src_w, src_h;
2861         u32 gtt_offset = 0;
2862
2863         memset(&plane_state->view, 0, sizeof(plane_state->view));
2864         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2865                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2866
2867         src_x = plane_state->uapi.src.x1 >> 16;
2868         src_y = plane_state->uapi.src.y1 >> 16;
2869         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2870         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2871
2872         WARN_ON(is_ccs_modifier(fb->modifier));
2873
2874         /* Make src coordinates relative to the viewport */
2875         drm_rect_translate(&plane_state->uapi.src,
2876                            -(src_x << 16), -(src_y << 16));
2877
2878         /* Rotate src coordinates to match rotated GTT view */
2879         if (drm_rotation_90_or_270(rotation))
2880                 drm_rect_rotate(&plane_state->uapi.src,
2881                                 src_w << 16, src_h << 16,
2882                                 DRM_MODE_ROTATE_270);
2883
2884         for (i = 0; i < num_planes; i++) {
2885                 unsigned int hsub = i ? fb->format->hsub : 1;
2886                 unsigned int vsub = i ? fb->format->vsub : 1;
2887                 unsigned int cpp = fb->format->cpp[i];
2888                 unsigned int tile_width, tile_height;
2889                 unsigned int width, height;
2890                 unsigned int pitch_tiles;
2891                 unsigned int x, y;
2892                 u32 offset;
2893
2894                 intel_tile_dims(fb, i, &tile_width, &tile_height);
2895
2896                 x = src_x / hsub;
2897                 y = src_y / vsub;
2898                 width = src_w / hsub;
2899                 height = src_h / vsub;
2900
2901                 /*
2902                  * First pixel of the src viewport from the
2903                  * start of the normal gtt mapping.
2904                  */
2905                 x += intel_fb->normal[i].x;
2906                 y += intel_fb->normal[i].y;
2907
2908                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2909                                                       fb, i, fb->pitches[i],
2910                                                       DRM_MODE_ROTATE_0, tile_size);
2911                 offset /= tile_size;
2912
2913                 info->plane[i].offset = offset;
2914                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2915                                                      tile_width * cpp);
2916                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2917                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2918
2919                 if (drm_rotation_90_or_270(rotation)) {
2920                         struct drm_rect r;
2921
2922                         /* rotate the x/y offsets to match the GTT view */
2923                         drm_rect_init(&r, x, y, width, height);
2924                         drm_rect_rotate(&r,
2925                                         info->plane[i].width * tile_width,
2926                                         info->plane[i].height * tile_height,
2927                                         DRM_MODE_ROTATE_270);
2928                         x = r.x1;
2929                         y = r.y1;
2930
2931                         pitch_tiles = info->plane[i].height;
2932                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2933
2934                         /* rotate the tile dimensions to match the GTT view */
2935                         swap(tile_width, tile_height);
2936                 } else {
2937                         pitch_tiles = info->plane[i].width;
2938                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2939                 }
2940
2941                 /*
2942                  * We only keep the x/y offsets, so push all of the
2943                  * gtt offset into the x/y offsets.
2944                  */
2945                 intel_adjust_tile_offset(&x, &y,
2946                                          tile_width, tile_height,
2947                                          tile_size, pitch_tiles,
2948                                          gtt_offset * tile_size, 0);
2949
2950                 gtt_offset += info->plane[i].width * info->plane[i].height;
2951
2952                 plane_state->color_plane[i].offset = 0;
2953                 plane_state->color_plane[i].x = x;
2954                 plane_state->color_plane[i].y = y;
2955         }
2956 }
2957
2958 static int
2959 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2960 {
2961         const struct intel_framebuffer *fb =
2962                 to_intel_framebuffer(plane_state->hw.fb);
2963         unsigned int rotation = plane_state->hw.rotation;
2964         int i, num_planes;
2965
2966         if (!fb)
2967                 return 0;
2968
2969         num_planes = fb->base.format->num_planes;
2970
2971         if (intel_plane_needs_remap(plane_state)) {
2972                 intel_plane_remap_gtt(plane_state);
2973
2974                 /*
2975                  * Sometimes even remapping can't overcome
2976                  * the stride limitations :( Can happen with
2977                  * big plane sizes and suitably misaligned
2978                  * offsets.
2979                  */
2980                 return intel_plane_check_stride(plane_state);
2981         }
2982
2983         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2984
2985         for (i = 0; i < num_planes; i++) {
2986                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2987                 plane_state->color_plane[i].offset = 0;
2988
2989                 if (drm_rotation_90_or_270(rotation)) {
2990                         plane_state->color_plane[i].x = fb->rotated[i].x;
2991                         plane_state->color_plane[i].y = fb->rotated[i].y;
2992                 } else {
2993                         plane_state->color_plane[i].x = fb->normal[i].x;
2994                         plane_state->color_plane[i].y = fb->normal[i].y;
2995                 }
2996         }
2997
2998         /* Rotate src coordinates to match rotated GTT view */
2999         if (drm_rotation_90_or_270(rotation))
3000                 drm_rect_rotate(&plane_state->uapi.src,
3001                                 fb->base.width << 16, fb->base.height << 16,
3002                                 DRM_MODE_ROTATE_270);
3003
3004         return intel_plane_check_stride(plane_state);
3005 }
3006
3007 static int i9xx_format_to_fourcc(int format)
3008 {
3009         switch (format) {
3010         case DISPPLANE_8BPP:
3011                 return DRM_FORMAT_C8;
3012         case DISPPLANE_BGRA555:
3013                 return DRM_FORMAT_ARGB1555;
3014         case DISPPLANE_BGRX555:
3015                 return DRM_FORMAT_XRGB1555;
3016         case DISPPLANE_BGRX565:
3017                 return DRM_FORMAT_RGB565;
3018         default:
3019         case DISPPLANE_BGRX888:
3020                 return DRM_FORMAT_XRGB8888;
3021         case DISPPLANE_RGBX888:
3022                 return DRM_FORMAT_XBGR8888;
3023         case DISPPLANE_BGRA888:
3024                 return DRM_FORMAT_ARGB8888;
3025         case DISPPLANE_RGBA888:
3026                 return DRM_FORMAT_ABGR8888;
3027         case DISPPLANE_BGRX101010:
3028                 return DRM_FORMAT_XRGB2101010;
3029         case DISPPLANE_RGBX101010:
3030                 return DRM_FORMAT_XBGR2101010;
3031         case DISPPLANE_BGRA101010:
3032                 return DRM_FORMAT_ARGB2101010;
3033         case DISPPLANE_RGBA101010:
3034                 return DRM_FORMAT_ABGR2101010;
3035         case DISPPLANE_RGBX161616:
3036                 return DRM_FORMAT_XBGR16161616F;
3037         }
3038 }
3039
3040 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3041 {
3042         switch (format) {
3043         case PLANE_CTL_FORMAT_RGB_565:
3044                 return DRM_FORMAT_RGB565;
3045         case PLANE_CTL_FORMAT_NV12:
3046                 return DRM_FORMAT_NV12;
3047         case PLANE_CTL_FORMAT_P010:
3048                 return DRM_FORMAT_P010;
3049         case PLANE_CTL_FORMAT_P012:
3050                 return DRM_FORMAT_P012;
3051         case PLANE_CTL_FORMAT_P016:
3052                 return DRM_FORMAT_P016;
3053         case PLANE_CTL_FORMAT_Y210:
3054                 return DRM_FORMAT_Y210;
3055         case PLANE_CTL_FORMAT_Y212:
3056                 return DRM_FORMAT_Y212;
3057         case PLANE_CTL_FORMAT_Y216:
3058                 return DRM_FORMAT_Y216;
3059         case PLANE_CTL_FORMAT_Y410:
3060                 return DRM_FORMAT_XVYU2101010;
3061         case PLANE_CTL_FORMAT_Y412:
3062                 return DRM_FORMAT_XVYU12_16161616;
3063         case PLANE_CTL_FORMAT_Y416:
3064                 return DRM_FORMAT_XVYU16161616;
3065         default:
3066         case PLANE_CTL_FORMAT_XRGB_8888:
3067                 if (rgb_order) {
3068                         if (alpha)
3069                                 return DRM_FORMAT_ABGR8888;
3070                         else
3071                                 return DRM_FORMAT_XBGR8888;
3072                 } else {
3073                         if (alpha)
3074                                 return DRM_FORMAT_ARGB8888;
3075                         else
3076                                 return DRM_FORMAT_XRGB8888;
3077                 }
3078         case PLANE_CTL_FORMAT_XRGB_2101010:
3079                 if (rgb_order) {
3080                         if (alpha)
3081                                 return DRM_FORMAT_ABGR2101010;
3082                         else
3083                                 return DRM_FORMAT_XBGR2101010;
3084                 } else {
3085                         if (alpha)
3086                                 return DRM_FORMAT_ARGB2101010;
3087                         else
3088                                 return DRM_FORMAT_XRGB2101010;
3089                 }
3090         case PLANE_CTL_FORMAT_XRGB_16161616F:
3091                 if (rgb_order) {
3092                         if (alpha)
3093                                 return DRM_FORMAT_ABGR16161616F;
3094                         else
3095                                 return DRM_FORMAT_XBGR16161616F;
3096                 } else {
3097                         if (alpha)
3098                                 return DRM_FORMAT_ARGB16161616F;
3099                         else
3100                                 return DRM_FORMAT_XRGB16161616F;
3101                 }
3102         }
3103 }
3104
3105 static bool
3106 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3107                               struct intel_initial_plane_config *plane_config)
3108 {
3109         struct drm_device *dev = crtc->base.dev;
3110         struct drm_i915_private *dev_priv = to_i915(dev);
3111         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3112         struct drm_framebuffer *fb = &plane_config->fb->base;
3113         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3114         u32 size_aligned = round_up(plane_config->base + plane_config->size,
3115                                     PAGE_SIZE);
3116         struct drm_i915_gem_object *obj;
3117         bool ret = false;
3118
3119         size_aligned -= base_aligned;
3120
3121         if (plane_config->size == 0)
3122                 return false;
3123
3124         /* If the FB is too big, just don't use it since fbdev is not very
3125          * important and we should probably use that space with FBC or other
3126          * features. */
3127         if (size_aligned * 2 > dev_priv->stolen_usable_size)
3128                 return false;
3129
3130         switch (fb->modifier) {
3131         case DRM_FORMAT_MOD_LINEAR:
3132         case I915_FORMAT_MOD_X_TILED:
3133         case I915_FORMAT_MOD_Y_TILED:
3134                 break;
3135         default:
3136                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3137                                  fb->modifier);
3138                 return false;
3139         }
3140
3141         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3142                                                              base_aligned,
3143                                                              base_aligned,
3144                                                              size_aligned);
3145         if (IS_ERR(obj))
3146                 return false;
3147
3148         switch (plane_config->tiling) {
3149         case I915_TILING_NONE:
3150                 break;
3151         case I915_TILING_X:
3152         case I915_TILING_Y:
3153                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3154                 break;
3155         default:
3156                 MISSING_CASE(plane_config->tiling);
3157                 goto out;
3158         }
3159
3160         mode_cmd.pixel_format = fb->format->format;
3161         mode_cmd.width = fb->width;
3162         mode_cmd.height = fb->height;
3163         mode_cmd.pitches[0] = fb->pitches[0];
3164         mode_cmd.modifier[0] = fb->modifier;
3165         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3166
3167         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3168                 DRM_DEBUG_KMS("intel fb init failed\n");
3169                 goto out;
3170         }
3171
3172
3173         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3174         ret = true;
3175 out:
3176         i915_gem_object_put(obj);
3177         return ret;
3178 }
3179
3180 static void
3181 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3182                         struct intel_plane_state *plane_state,
3183                         bool visible)
3184 {
3185         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3186
3187         plane_state->uapi.visible = visible;
3188
3189         if (visible)
3190                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3191         else
3192                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3193 }
3194
3195 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3196 {
3197         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3198         struct drm_plane *plane;
3199
3200         /*
3201          * Active_planes aliases if multiple "primary" or cursor planes
3202          * have been used on the same (or wrong) pipe. plane_mask uses
3203          * unique ids, hence we can use that to reconstruct active_planes.
3204          */
3205         crtc_state->active_planes = 0;
3206
3207         drm_for_each_plane_mask(plane, &dev_priv->drm,
3208                                 crtc_state->uapi.plane_mask)
3209                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3210 }
3211
3212 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3213                                          struct intel_plane *plane)
3214 {
3215         struct intel_crtc_state *crtc_state =
3216                 to_intel_crtc_state(crtc->base.state);
3217         struct intel_plane_state *plane_state =
3218                 to_intel_plane_state(plane->base.state);
3219
3220         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3221                       plane->base.base.id, plane->base.name,
3222                       crtc->base.base.id, crtc->base.name);
3223
3224         intel_set_plane_visible(crtc_state, plane_state, false);
3225         fixup_active_planes(crtc_state);
3226         crtc_state->data_rate[plane->id] = 0;
3227         crtc_state->min_cdclk[plane->id] = 0;
3228
3229         if (plane->id == PLANE_PRIMARY)
3230                 intel_pre_disable_primary_noatomic(&crtc->base);
3231
3232         intel_disable_plane(plane, crtc_state);
3233 }
3234
3235 static struct intel_frontbuffer *
3236 to_intel_frontbuffer(struct drm_framebuffer *fb)
3237 {
3238         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3239 }
3240
3241 static void
3242 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3243                              struct intel_initial_plane_config *plane_config)
3244 {
3245         struct drm_device *dev = intel_crtc->base.dev;
3246         struct drm_i915_private *dev_priv = to_i915(dev);
3247         struct drm_crtc *c;
3248         struct drm_plane *primary = intel_crtc->base.primary;
3249         struct drm_plane_state *plane_state = primary->state;
3250         struct intel_plane *intel_plane = to_intel_plane(primary);
3251         struct intel_plane_state *intel_state =
3252                 to_intel_plane_state(plane_state);
3253         struct drm_framebuffer *fb;
3254
3255         if (!plane_config->fb)
3256                 return;
3257
3258         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3259                 fb = &plane_config->fb->base;
3260                 goto valid_fb;
3261         }
3262
3263         kfree(plane_config->fb);
3264
3265         /*
3266          * Failed to alloc the obj, check to see if we should share
3267          * an fb with another CRTC instead
3268          */
3269         for_each_crtc(dev, c) {
3270                 struct intel_plane_state *state;
3271
3272                 if (c == &intel_crtc->base)
3273                         continue;
3274
3275                 if (!to_intel_crtc(c)->active)
3276                         continue;
3277
3278                 state = to_intel_plane_state(c->primary->state);
3279                 if (!state->vma)
3280                         continue;
3281
3282                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3283                         fb = state->hw.fb;
3284                         drm_framebuffer_get(fb);
3285                         goto valid_fb;
3286                 }
3287         }
3288
3289         /*
3290          * We've failed to reconstruct the BIOS FB.  Current display state
3291          * indicates that the primary plane is visible, but has a NULL FB,
3292          * which will lead to problems later if we don't fix it up.  The
3293          * simplest solution is to just disable the primary plane now and
3294          * pretend the BIOS never had it enabled.
3295          */
3296         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3297
3298         return;
3299
3300 valid_fb:
3301         intel_state->hw.rotation = plane_config->rotation;
3302         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3303                                 intel_state->hw.rotation);
3304         intel_state->color_plane[0].stride =
3305                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3306
3307         intel_state->vma =
3308                 intel_pin_and_fence_fb_obj(fb,
3309                                            &intel_state->view,
3310                                            intel_plane_uses_fence(intel_state),
3311                                            &intel_state->flags);
3312         if (IS_ERR(intel_state->vma)) {
3313                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3314                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
3315
3316                 intel_state->vma = NULL;
3317                 drm_framebuffer_put(fb);
3318                 return;
3319         }
3320
3321         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3322
3323         plane_state->src_x = 0;
3324         plane_state->src_y = 0;
3325         plane_state->src_w = fb->width << 16;
3326         plane_state->src_h = fb->height << 16;
3327
3328         plane_state->crtc_x = 0;
3329         plane_state->crtc_y = 0;
3330         plane_state->crtc_w = fb->width;
3331         plane_state->crtc_h = fb->height;
3332
3333         intel_state->uapi.src = drm_plane_state_src(plane_state);
3334         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3335
3336         if (plane_config->tiling)
3337                 dev_priv->preserve_bios_swizzle = true;
3338
3339         plane_state->fb = fb;
3340         plane_state->crtc = &intel_crtc->base;
3341         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3342
3343         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3344                   &to_intel_frontbuffer(fb)->bits);
3345 }
3346
3347 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3348                                int color_plane,
3349                                unsigned int rotation)
3350 {
3351         int cpp = fb->format->cpp[color_plane];
3352
3353         switch (fb->modifier) {
3354         case DRM_FORMAT_MOD_LINEAR:
3355         case I915_FORMAT_MOD_X_TILED:
3356                 /*
3357                  * Validated limit is 4k, but has 5k should
3358                  * work apart from the following features:
3359                  * - Ytile (already limited to 4k)
3360                  * - FP16 (already limited to 4k)
3361                  * - render compression (already limited to 4k)
3362                  * - KVMR sprite and cursor (don't care)
3363                  * - horizontal panning (TODO verify this)
3364                  * - pipe and plane scaling (TODO verify this)
3365                  */
3366                 if (cpp == 8)
3367                         return 4096;
3368                 else
3369                         return 5120;
3370         case I915_FORMAT_MOD_Y_TILED_CCS:
3371         case I915_FORMAT_MOD_Yf_TILED_CCS:
3372                 /* FIXME AUX plane? */
3373         case I915_FORMAT_MOD_Y_TILED:
3374         case I915_FORMAT_MOD_Yf_TILED:
3375                 if (cpp == 8)
3376                         return 2048;
3377                 else
3378                         return 4096;
3379         default:
3380                 MISSING_CASE(fb->modifier);
3381                 return 2048;
3382         }
3383 }
3384
3385 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3386                                int color_plane,
3387                                unsigned int rotation)
3388 {
3389         int cpp = fb->format->cpp[color_plane];
3390
3391         switch (fb->modifier) {
3392         case DRM_FORMAT_MOD_LINEAR:
3393         case I915_FORMAT_MOD_X_TILED:
3394                 if (cpp == 8)
3395                         return 4096;
3396                 else
3397                         return 5120;
3398         case I915_FORMAT_MOD_Y_TILED_CCS:
3399         case I915_FORMAT_MOD_Yf_TILED_CCS:
3400                 /* FIXME AUX plane? */
3401         case I915_FORMAT_MOD_Y_TILED:
3402         case I915_FORMAT_MOD_Yf_TILED:
3403                 if (cpp == 8)
3404                         return 2048;
3405                 else
3406                         return 5120;
3407         default:
3408                 MISSING_CASE(fb->modifier);
3409                 return 2048;
3410         }
3411 }
3412
3413 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3414                                int color_plane,
3415                                unsigned int rotation)
3416 {
3417         return 5120;
3418 }
3419
3420 static int skl_max_plane_height(void)
3421 {
3422         return 4096;
3423 }
3424
3425 static int icl_max_plane_height(void)
3426 {
3427         return 4320;
3428 }
3429
3430 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3431                                            int main_x, int main_y, u32 main_offset)
3432 {
3433         const struct drm_framebuffer *fb = plane_state->hw.fb;
3434         int hsub = fb->format->hsub;
3435         int vsub = fb->format->vsub;
3436         int aux_x = plane_state->color_plane[1].x;
3437         int aux_y = plane_state->color_plane[1].y;
3438         u32 aux_offset = plane_state->color_plane[1].offset;
3439         u32 alignment = intel_surf_alignment(fb, 1);
3440
3441         while (aux_offset >= main_offset && aux_y <= main_y) {
3442                 int x, y;
3443
3444                 if (aux_x == main_x && aux_y == main_y)
3445                         break;
3446
3447                 if (aux_offset == 0)
3448                         break;
3449
3450                 x = aux_x / hsub;
3451                 y = aux_y / vsub;
3452                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3453                                                                aux_offset, aux_offset - alignment);
3454                 aux_x = x * hsub + aux_x % hsub;
3455                 aux_y = y * vsub + aux_y % vsub;
3456         }
3457
3458         if (aux_x != main_x || aux_y != main_y)
3459                 return false;
3460
3461         plane_state->color_plane[1].offset = aux_offset;
3462         plane_state->color_plane[1].x = aux_x;
3463         plane_state->color_plane[1].y = aux_y;
3464
3465         return true;
3466 }
3467
3468 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3469 {
3470         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3471         const struct drm_framebuffer *fb = plane_state->hw.fb;
3472         unsigned int rotation = plane_state->hw.rotation;
3473         int x = plane_state->uapi.src.x1 >> 16;
3474         int y = plane_state->uapi.src.y1 >> 16;
3475         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3476         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3477         int max_width;
3478         int max_height;
3479         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3480
3481         if (INTEL_GEN(dev_priv) >= 11)
3482                 max_width = icl_max_plane_width(fb, 0, rotation);
3483         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3484                 max_width = glk_max_plane_width(fb, 0, rotation);
3485         else
3486                 max_width = skl_max_plane_width(fb, 0, rotation);
3487
3488         if (INTEL_GEN(dev_priv) >= 11)
3489                 max_height = icl_max_plane_height();
3490         else
3491                 max_height = skl_max_plane_height();
3492
3493         if (w > max_width || h > max_height) {
3494                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3495                               w, h, max_width, max_height);
3496                 return -EINVAL;
3497         }
3498
3499         intel_add_fb_offsets(&x, &y, plane_state, 0);
3500         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3501         alignment = intel_surf_alignment(fb, 0);
3502
3503         /*
3504          * AUX surface offset is specified as the distance from the
3505          * main surface offset, and it must be non-negative. Make
3506          * sure that is what we will get.
3507          */
3508         if (offset > aux_offset)
3509                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3510                                                            offset, aux_offset & ~(alignment - 1));
3511
3512         /*
3513          * When using an X-tiled surface, the plane blows up
3514          * if the x offset + width exceed the stride.
3515          *
3516          * TODO: linear and Y-tiled seem fine, Yf untested,
3517          */
3518         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3519                 int cpp = fb->format->cpp[0];
3520
3521                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3522                         if (offset == 0) {
3523                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3524                                 return -EINVAL;
3525                         }
3526
3527                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3528                                                                    offset, offset - alignment);
3529                 }
3530         }
3531
3532         /*
3533          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3534          * they match with the main surface x/y offsets.
3535          */
3536         if (is_ccs_modifier(fb->modifier)) {
3537                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3538                         if (offset == 0)
3539                                 break;
3540
3541                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3542                                                                    offset, offset - alignment);
3543                 }
3544
3545                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3546                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3547                         return -EINVAL;
3548                 }
3549         }
3550
3551         plane_state->color_plane[0].offset = offset;
3552         plane_state->color_plane[0].x = x;
3553         plane_state->color_plane[0].y = y;
3554
3555         /*
3556          * Put the final coordinates back so that the src
3557          * coordinate checks will see the right values.
3558          */
3559         drm_rect_translate_to(&plane_state->uapi.src,
3560                               x << 16, y << 16);
3561
3562         return 0;
3563 }
3564
3565 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3566 {
3567         const struct drm_framebuffer *fb = plane_state->hw.fb;
3568         unsigned int rotation = plane_state->hw.rotation;
3569         int max_width = skl_max_plane_width(fb, 1, rotation);
3570         int max_height = 4096;
3571         int x = plane_state->uapi.src.x1 >> 17;
3572         int y = plane_state->uapi.src.y1 >> 17;
3573         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3574         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3575         u32 offset;
3576
3577         intel_add_fb_offsets(&x, &y, plane_state, 1);
3578         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3579
3580         /* FIXME not quite sure how/if these apply to the chroma plane */
3581         if (w > max_width || h > max_height) {
3582                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3583                               w, h, max_width, max_height);
3584                 return -EINVAL;
3585         }
3586
3587         plane_state->color_plane[1].offset = offset;
3588         plane_state->color_plane[1].x = x;
3589         plane_state->color_plane[1].y = y;
3590
3591         return 0;
3592 }
3593
3594 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3595 {
3596         const struct drm_framebuffer *fb = plane_state->hw.fb;
3597         int src_x = plane_state->uapi.src.x1 >> 16;
3598         int src_y = plane_state->uapi.src.y1 >> 16;
3599         int hsub = fb->format->hsub;
3600         int vsub = fb->format->vsub;
3601         int x = src_x / hsub;
3602         int y = src_y / vsub;
3603         u32 offset;
3604
3605         intel_add_fb_offsets(&x, &y, plane_state, 1);
3606         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3607
3608         plane_state->color_plane[1].offset = offset;
3609         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3610         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3611
3612         return 0;
3613 }
3614
3615 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3616 {
3617         const struct drm_framebuffer *fb = plane_state->hw.fb;
3618         int ret;
3619
3620         ret = intel_plane_compute_gtt(plane_state);
3621         if (ret)
3622                 return ret;
3623
3624         if (!plane_state->uapi.visible)
3625                 return 0;
3626
3627         /*
3628          * Handle the AUX surface first since
3629          * the main surface setup depends on it.
3630          */
3631         if (drm_format_info_is_yuv_semiplanar(fb->format)) {
3632                 ret = skl_check_nv12_aux_surface(plane_state);
3633                 if (ret)
3634                         return ret;
3635         } else if (is_ccs_modifier(fb->modifier)) {
3636                 ret = skl_check_ccs_aux_surface(plane_state);
3637                 if (ret)
3638                         return ret;
3639         } else {
3640                 plane_state->color_plane[1].offset = ~0xfff;
3641                 plane_state->color_plane[1].x = 0;
3642                 plane_state->color_plane[1].y = 0;
3643         }
3644
3645         ret = skl_check_main_surface(plane_state);
3646         if (ret)
3647                 return ret;
3648
3649         return 0;
3650 }
3651
3652 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
3653                              const struct intel_plane_state *plane_state,
3654                              unsigned int *num, unsigned int *den)
3655 {
3656         const struct drm_framebuffer *fb = plane_state->hw.fb;
3657         unsigned int cpp = fb->format->cpp[0];
3658
3659         /*
3660          * g4x bspec says 64bpp pixel rate can't exceed 80%
3661          * of cdclk when the sprite plane is enabled on the
3662          * same pipe. ilk/snb bspec says 64bpp pixel rate is
3663          * never allowed to exceed 80% of cdclk. Let's just go
3664          * with the ilk/snb limit always.
3665          */
3666         if (cpp == 8) {
3667                 *num = 10;
3668                 *den = 8;
3669         } else {
3670                 *num = 1;
3671                 *den = 1;
3672         }
3673 }
3674
3675 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
3676                                 const struct intel_plane_state *plane_state)
3677 {
3678         unsigned int pixel_rate;
3679         unsigned int num, den;
3680
3681         /*
3682          * Note that crtc_state->pixel_rate accounts for both
3683          * horizontal and vertical panel fitter downscaling factors.
3684          * Pre-HSW bspec tells us to only consider the horizontal
3685          * downscaling factor here. We ignore that and just consider
3686          * both for simplicity.
3687          */
3688         pixel_rate = crtc_state->pixel_rate;
3689
3690         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
3691
3692         /* two pixels per clock with double wide pipe */
3693         if (crtc_state->double_wide)
3694                 den *= 2;
3695
3696         return DIV_ROUND_UP(pixel_rate * num, den);
3697 }
3698
3699 unsigned int
3700 i9xx_plane_max_stride(struct intel_plane *plane,
3701                       u32 pixel_format, u64 modifier,
3702                       unsigned int rotation)
3703 {
3704         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3705
3706         if (!HAS_GMCH(dev_priv)) {
3707                 return 32*1024;
3708         } else if (INTEL_GEN(dev_priv) >= 4) {
3709                 if (modifier == I915_FORMAT_MOD_X_TILED)
3710                         return 16*1024;
3711                 else
3712                         return 32*1024;
3713         } else if (INTEL_GEN(dev_priv) >= 3) {
3714                 if (modifier == I915_FORMAT_MOD_X_TILED)
3715                         return 8*1024;
3716                 else
3717                         return 16*1024;
3718         } else {
3719                 if (plane->i9xx_plane == PLANE_C)
3720                         return 4*1024;
3721                 else
3722                         return 8*1024;
3723         }
3724 }
3725
3726 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3727 {
3728         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3729         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3730         u32 dspcntr = 0;
3731
3732         if (crtc_state->gamma_enable)
3733                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3734
3735         if (crtc_state->csc_enable)
3736                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3737
3738         if (INTEL_GEN(dev_priv) < 5)
3739                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3740
3741         return dspcntr;
3742 }
3743
3744 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3745                           const struct intel_plane_state *plane_state)
3746 {
3747         struct drm_i915_private *dev_priv =
3748                 to_i915(plane_state->uapi.plane->dev);
3749         const struct drm_framebuffer *fb = plane_state->hw.fb;
3750         unsigned int rotation = plane_state->hw.rotation;
3751         u32 dspcntr;
3752
3753         dspcntr = DISPLAY_PLANE_ENABLE;
3754
3755         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3756             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3757                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3758
3759         switch (fb->format->format) {
3760         case DRM_FORMAT_C8:
3761                 dspcntr |= DISPPLANE_8BPP;
3762                 break;
3763         case DRM_FORMAT_XRGB1555:
3764                 dspcntr |= DISPPLANE_BGRX555;
3765                 break;
3766         case DRM_FORMAT_ARGB1555:
3767                 dspcntr |= DISPPLANE_BGRA555;
3768                 break;
3769         case DRM_FORMAT_RGB565:
3770                 dspcntr |= DISPPLANE_BGRX565;
3771                 break;
3772         case DRM_FORMAT_XRGB8888:
3773                 dspcntr |= DISPPLANE_BGRX888;
3774                 break;
3775         case DRM_FORMAT_XBGR8888:
3776                 dspcntr |= DISPPLANE_RGBX888;
3777                 break;
3778         case DRM_FORMAT_ARGB8888:
3779                 dspcntr |= DISPPLANE_BGRA888;
3780                 break;
3781         case DRM_FORMAT_ABGR8888:
3782                 dspcntr |= DISPPLANE_RGBA888;
3783                 break;
3784         case DRM_FORMAT_XRGB2101010:
3785                 dspcntr |= DISPPLANE_BGRX101010;
3786                 break;
3787         case DRM_FORMAT_XBGR2101010:
3788                 dspcntr |= DISPPLANE_RGBX101010;
3789                 break;
3790         case DRM_FORMAT_ARGB2101010:
3791                 dspcntr |= DISPPLANE_BGRA101010;
3792                 break;
3793         case DRM_FORMAT_ABGR2101010:
3794                 dspcntr |= DISPPLANE_RGBA101010;
3795                 break;
3796         case DRM_FORMAT_XBGR16161616F:
3797                 dspcntr |= DISPPLANE_RGBX161616;
3798                 break;
3799         default:
3800                 MISSING_CASE(fb->format->format);
3801                 return 0;
3802         }
3803
3804         if (INTEL_GEN(dev_priv) >= 4 &&
3805             fb->modifier == I915_FORMAT_MOD_X_TILED)
3806                 dspcntr |= DISPPLANE_TILED;
3807
3808         if (rotation & DRM_MODE_ROTATE_180)
3809                 dspcntr |= DISPPLANE_ROTATE_180;
3810
3811         if (rotation & DRM_MODE_REFLECT_X)
3812                 dspcntr |= DISPPLANE_MIRROR;
3813
3814         return dspcntr;
3815 }
3816
3817 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3818 {
3819         struct drm_i915_private *dev_priv =
3820                 to_i915(plane_state->uapi.plane->dev);
3821         const struct drm_framebuffer *fb = plane_state->hw.fb;
3822         int src_x, src_y, src_w;
3823         u32 offset;
3824         int ret;
3825
3826         ret = intel_plane_compute_gtt(plane_state);
3827         if (ret)
3828                 return ret;
3829
3830         if (!plane_state->uapi.visible)
3831                 return 0;
3832
3833         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3834         src_x = plane_state->uapi.src.x1 >> 16;
3835         src_y = plane_state->uapi.src.y1 >> 16;
3836
3837         /* Undocumented hardware limit on i965/g4x/vlv/chv */
3838         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
3839                 return -EINVAL;
3840
3841         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3842
3843         if (INTEL_GEN(dev_priv) >= 4)
3844                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3845                                                             plane_state, 0);
3846         else
3847                 offset = 0;
3848
3849         /*
3850          * Put the final coordinates back so that the src
3851          * coordinate checks will see the right values.
3852          */
3853         drm_rect_translate_to(&plane_state->uapi.src,
3854                               src_x << 16, src_y << 16);
3855
3856         /* HSW/BDW do this automagically in hardware */
3857         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3858                 unsigned int rotation = plane_state->hw.rotation;
3859                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3860                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3861
3862                 if (rotation & DRM_MODE_ROTATE_180) {
3863                         src_x += src_w - 1;
3864                         src_y += src_h - 1;
3865                 } else if (rotation & DRM_MODE_REFLECT_X) {
3866                         src_x += src_w - 1;
3867                 }
3868         }
3869
3870         plane_state->color_plane[0].offset = offset;
3871         plane_state->color_plane[0].x = src_x;
3872         plane_state->color_plane[0].y = src_y;
3873
3874         return 0;
3875 }
3876
3877 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3878 {
3879         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3880         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3881
3882         if (IS_CHERRYVIEW(dev_priv))
3883                 return i9xx_plane == PLANE_B;
3884         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3885                 return false;
3886         else if (IS_GEN(dev_priv, 4))
3887                 return i9xx_plane == PLANE_C;
3888         else
3889                 return i9xx_plane == PLANE_B ||
3890                         i9xx_plane == PLANE_C;
3891 }
3892
3893 static int
3894 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3895                  struct intel_plane_state *plane_state)
3896 {
3897         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3898         int ret;
3899
3900         ret = chv_plane_check_rotation(plane_state);
3901         if (ret)
3902                 return ret;
3903
3904         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
3905                                                   &crtc_state->uapi,
3906                                                   DRM_PLANE_HELPER_NO_SCALING,
3907                                                   DRM_PLANE_HELPER_NO_SCALING,
3908                                                   i9xx_plane_has_windowing(plane),
3909                                                   true);
3910         if (ret)
3911                 return ret;
3912
3913         ret = i9xx_check_plane_surface(plane_state);
3914         if (ret)
3915                 return ret;
3916
3917         if (!plane_state->uapi.visible)
3918                 return 0;
3919
3920         ret = intel_plane_check_src_coordinates(plane_state);
3921         if (ret)
3922                 return ret;
3923
3924         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3925
3926         return 0;
3927 }
3928
3929 static void i9xx_update_plane(struct intel_plane *plane,
3930                               const struct intel_crtc_state *crtc_state,
3931                               const struct intel_plane_state *plane_state)
3932 {
3933         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3934         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3935         u32 linear_offset;
3936         int x = plane_state->color_plane[0].x;
3937         int y = plane_state->color_plane[0].y;
3938         int crtc_x = plane_state->uapi.dst.x1;
3939         int crtc_y = plane_state->uapi.dst.y1;
3940         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
3941         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
3942         unsigned long irqflags;
3943         u32 dspaddr_offset;
3944         u32 dspcntr;
3945
3946         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3947
3948         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3949
3950         if (INTEL_GEN(dev_priv) >= 4)
3951                 dspaddr_offset = plane_state->color_plane[0].offset;
3952         else
3953                 dspaddr_offset = linear_offset;
3954
3955         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3956
3957         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3958
3959         if (INTEL_GEN(dev_priv) < 4) {
3960                 /*
3961                  * PLANE_A doesn't actually have a full window
3962                  * generator but let's assume we still need to
3963                  * program whatever is there.
3964                  */
3965                 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3966                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3967                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3968         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3969                 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3970                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3971                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3972                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3973         }
3974
3975         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3976                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3977         } else if (INTEL_GEN(dev_priv) >= 4) {
3978                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3979                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3980         }
3981
3982         /*
3983          * The control register self-arms if the plane was previously
3984          * disabled. Try to make the plane enable atomic by writing
3985          * the control register just before the surface register.
3986          */
3987         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3988         if (INTEL_GEN(dev_priv) >= 4)
3989                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3990                               intel_plane_ggtt_offset(plane_state) +
3991                               dspaddr_offset);
3992         else
3993                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3994                               intel_plane_ggtt_offset(plane_state) +
3995                               dspaddr_offset);
3996
3997         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3998 }
3999
4000 static void i9xx_disable_plane(struct intel_plane *plane,
4001                                const struct intel_crtc_state *crtc_state)
4002 {
4003         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4004         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4005         unsigned long irqflags;
4006         u32 dspcntr;
4007
4008         /*
4009          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4010          * enable on ilk+ affect the pipe bottom color as
4011          * well, so we must configure them even if the plane
4012          * is disabled.
4013          *
4014          * On pre-g4x there is no way to gamma correct the
4015          * pipe bottom color but we'll keep on doing this
4016          * anyway so that the crtc state readout works correctly.
4017          */
4018         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4019
4020         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4021
4022         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
4023         if (INTEL_GEN(dev_priv) >= 4)
4024                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
4025         else
4026                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
4027
4028         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4029 }
4030
4031 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4032                                     enum pipe *pipe)
4033 {
4034         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4035         enum intel_display_power_domain power_domain;
4036         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4037         intel_wakeref_t wakeref;
4038         bool ret;
4039         u32 val;
4040
4041         /*
4042          * Not 100% correct for planes that can move between pipes,
4043          * but that's only the case for gen2-4 which don't have any
4044          * display power wells.
4045          */
4046         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4047         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4048         if (!wakeref)
4049                 return false;
4050
4051         val = I915_READ(DSPCNTR(i9xx_plane));
4052
4053         ret = val & DISPLAY_PLANE_ENABLE;
4054
4055         if (INTEL_GEN(dev_priv) >= 5)
4056                 *pipe = plane->pipe;
4057         else
4058                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4059                         DISPPLANE_SEL_PIPE_SHIFT;
4060
4061         intel_display_power_put(dev_priv, power_domain, wakeref);
4062
4063         return ret;
4064 }
4065
4066 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4067 {
4068         struct drm_device *dev = intel_crtc->base.dev;
4069         struct drm_i915_private *dev_priv = to_i915(dev);
4070
4071         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4072         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4073         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4074 }
4075
4076 /*
4077  * This function detaches (aka. unbinds) unused scalers in hardware
4078  */
4079 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4080 {
4081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4082         const struct intel_crtc_scaler_state *scaler_state =
4083                 &crtc_state->scaler_state;
4084         int i;
4085
4086         /* loop through and disable scalers that aren't in use */
4087         for (i = 0; i < intel_crtc->num_scalers; i++) {
4088                 if (!scaler_state->scalers[i].in_use)
4089                         skl_detach_scaler(intel_crtc, i);
4090         }
4091 }
4092
4093 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4094                                           int color_plane, unsigned int rotation)
4095 {
4096         /*
4097          * The stride is either expressed as a multiple of 64 bytes chunks for
4098          * linear buffers or in number of tiles for tiled buffers.
4099          */
4100         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
4101                 return 64;
4102         else if (drm_rotation_90_or_270(rotation))
4103                 return intel_tile_height(fb, color_plane);
4104         else
4105                 return intel_tile_width_bytes(fb, color_plane);
4106 }
4107
4108 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4109                      int color_plane)
4110 {
4111         const struct drm_framebuffer *fb = plane_state->hw.fb;
4112         unsigned int rotation = plane_state->hw.rotation;
4113         u32 stride = plane_state->color_plane[color_plane].stride;
4114
4115         if (color_plane >= fb->format->num_planes)
4116                 return 0;
4117
4118         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4119 }
4120
4121 static u32 skl_plane_ctl_format(u32 pixel_format)
4122 {
4123         switch (pixel_format) {
4124         case DRM_FORMAT_C8:
4125                 return PLANE_CTL_FORMAT_INDEXED;
4126         case DRM_FORMAT_RGB565:
4127                 return PLANE_CTL_FORMAT_RGB_565;
4128         case DRM_FORMAT_XBGR8888:
4129         case DRM_FORMAT_ABGR8888:
4130                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4131         case DRM_FORMAT_XRGB8888:
4132         case DRM_FORMAT_ARGB8888:
4133                 return PLANE_CTL_FORMAT_XRGB_8888;
4134         case DRM_FORMAT_XBGR2101010:
4135         case DRM_FORMAT_ABGR2101010:
4136                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4137         case DRM_FORMAT_XRGB2101010:
4138         case DRM_FORMAT_ARGB2101010:
4139                 return PLANE_CTL_FORMAT_XRGB_2101010;
4140         case DRM_FORMAT_XBGR16161616F:
4141         case DRM_FORMAT_ABGR16161616F:
4142                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4143         case DRM_FORMAT_XRGB16161616F:
4144         case DRM_FORMAT_ARGB16161616F:
4145                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4146         case DRM_FORMAT_YUYV:
4147                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4148         case DRM_FORMAT_YVYU:
4149                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4150         case DRM_FORMAT_UYVY:
4151                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4152         case DRM_FORMAT_VYUY:
4153                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4154         case DRM_FORMAT_NV12:
4155                 return PLANE_CTL_FORMAT_NV12;
4156         case DRM_FORMAT_P010:
4157                 return PLANE_CTL_FORMAT_P010;
4158         case DRM_FORMAT_P012:
4159                 return PLANE_CTL_FORMAT_P012;
4160         case DRM_FORMAT_P016:
4161                 return PLANE_CTL_FORMAT_P016;
4162         case DRM_FORMAT_Y210:
4163                 return PLANE_CTL_FORMAT_Y210;
4164         case DRM_FORMAT_Y212:
4165                 return PLANE_CTL_FORMAT_Y212;
4166         case DRM_FORMAT_Y216:
4167                 return PLANE_CTL_FORMAT_Y216;
4168         case DRM_FORMAT_XVYU2101010:
4169                 return PLANE_CTL_FORMAT_Y410;
4170         case DRM_FORMAT_XVYU12_16161616:
4171                 return PLANE_CTL_FORMAT_Y412;
4172         case DRM_FORMAT_XVYU16161616:
4173                 return PLANE_CTL_FORMAT_Y416;
4174         default:
4175                 MISSING_CASE(pixel_format);
4176         }
4177
4178         return 0;
4179 }
4180
4181 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4182 {
4183         if (!plane_state->hw.fb->format->has_alpha)
4184                 return PLANE_CTL_ALPHA_DISABLE;
4185
4186         switch (plane_state->hw.pixel_blend_mode) {
4187         case DRM_MODE_BLEND_PIXEL_NONE:
4188                 return PLANE_CTL_ALPHA_DISABLE;
4189         case DRM_MODE_BLEND_PREMULTI:
4190                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4191         case DRM_MODE_BLEND_COVERAGE:
4192                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4193         default:
4194                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4195                 return PLANE_CTL_ALPHA_DISABLE;
4196         }
4197 }
4198
4199 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4200 {
4201         if (!plane_state->hw.fb->format->has_alpha)
4202                 return PLANE_COLOR_ALPHA_DISABLE;
4203
4204         switch (plane_state->hw.pixel_blend_mode) {
4205         case DRM_MODE_BLEND_PIXEL_NONE:
4206                 return PLANE_COLOR_ALPHA_DISABLE;
4207         case DRM_MODE_BLEND_PREMULTI:
4208                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4209         case DRM_MODE_BLEND_COVERAGE:
4210                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4211         default:
4212                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4213                 return PLANE_COLOR_ALPHA_DISABLE;
4214         }
4215 }
4216
4217 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4218 {
4219         switch (fb_modifier) {
4220         case DRM_FORMAT_MOD_LINEAR:
4221                 break;
4222         case I915_FORMAT_MOD_X_TILED:
4223                 return PLANE_CTL_TILED_X;
4224         case I915_FORMAT_MOD_Y_TILED:
4225                 return PLANE_CTL_TILED_Y;
4226         case I915_FORMAT_MOD_Y_TILED_CCS:
4227                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4228         case I915_FORMAT_MOD_Yf_TILED:
4229                 return PLANE_CTL_TILED_YF;
4230         case I915_FORMAT_MOD_Yf_TILED_CCS:
4231                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4232         default:
4233                 MISSING_CASE(fb_modifier);
4234         }
4235
4236         return 0;
4237 }
4238
4239 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4240 {
4241         switch (rotate) {
4242         case DRM_MODE_ROTATE_0:
4243                 break;
4244         /*
4245          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4246          * while i915 HW rotation is clockwise, thats why this swapping.
4247          */
4248         case DRM_MODE_ROTATE_90:
4249                 return PLANE_CTL_ROTATE_270;
4250         case DRM_MODE_ROTATE_180:
4251                 return PLANE_CTL_ROTATE_180;
4252         case DRM_MODE_ROTATE_270:
4253                 return PLANE_CTL_ROTATE_90;
4254         default:
4255                 MISSING_CASE(rotate);
4256         }
4257
4258         return 0;
4259 }
4260
4261 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4262 {
4263         switch (reflect) {
4264         case 0:
4265                 break;
4266         case DRM_MODE_REFLECT_X:
4267                 return PLANE_CTL_FLIP_HORIZONTAL;
4268         case DRM_MODE_REFLECT_Y:
4269         default:
4270                 MISSING_CASE(reflect);
4271         }
4272
4273         return 0;
4274 }
4275
4276 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4277 {
4278         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4279         u32 plane_ctl = 0;
4280
4281         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4282                 return plane_ctl;
4283
4284         if (crtc_state->gamma_enable)
4285                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4286
4287         if (crtc_state->csc_enable)
4288                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4289
4290         return plane_ctl;
4291 }
4292
4293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4294                   const struct intel_plane_state *plane_state)
4295 {
4296         struct drm_i915_private *dev_priv =
4297                 to_i915(plane_state->uapi.plane->dev);
4298         const struct drm_framebuffer *fb = plane_state->hw.fb;
4299         unsigned int rotation = plane_state->hw.rotation;
4300         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4301         u32 plane_ctl;
4302
4303         plane_ctl = PLANE_CTL_ENABLE;
4304
4305         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4306                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4307                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4308
4309                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4310                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4311
4312                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4313                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4314         }
4315
4316         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4317         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4318         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4319
4320         if (INTEL_GEN(dev_priv) >= 10)
4321                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4322                                                 DRM_MODE_REFLECT_MASK);
4323
4324         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4325                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4326         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4327                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4328
4329         return plane_ctl;
4330 }
4331
4332 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4333 {
4334         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4335         u32 plane_color_ctl = 0;
4336
4337         if (INTEL_GEN(dev_priv) >= 11)
4338                 return plane_color_ctl;
4339
4340         if (crtc_state->gamma_enable)
4341                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4342
4343         if (crtc_state->csc_enable)
4344                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4345
4346         return plane_color_ctl;
4347 }
4348
4349 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4350                         const struct intel_plane_state *plane_state)
4351 {
4352         struct drm_i915_private *dev_priv =
4353                 to_i915(plane_state->uapi.plane->dev);
4354         const struct drm_framebuffer *fb = plane_state->hw.fb;
4355         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4356         u32 plane_color_ctl = 0;
4357
4358         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4359         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4360
4361         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4362                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4363                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4364                 else
4365                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4366
4367                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4368                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4369         } else if (fb->format->is_yuv) {
4370                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4371         }
4372
4373         return plane_color_ctl;
4374 }
4375
4376 static int
4377 __intel_display_resume(struct drm_device *dev,
4378                        struct drm_atomic_state *state,
4379                        struct drm_modeset_acquire_ctx *ctx)
4380 {
4381         struct drm_crtc_state *crtc_state;
4382         struct drm_crtc *crtc;
4383         int i, ret;
4384
4385         intel_modeset_setup_hw_state(dev, ctx);
4386         intel_vga_redisable(to_i915(dev));
4387
4388         if (!state)
4389                 return 0;
4390
4391         /*
4392          * We've duplicated the state, pointers to the old state are invalid.
4393          *
4394          * Don't attempt to use the old state until we commit the duplicated state.
4395          */
4396         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4397                 /*
4398                  * Force recalculation even if we restore
4399                  * current state. With fast modeset this may not result
4400                  * in a modeset when the state is compatible.
4401                  */
4402                 crtc_state->mode_changed = true;
4403         }
4404
4405         /* ignore any reset values/BIOS leftovers in the WM registers */
4406         if (!HAS_GMCH(to_i915(dev)))
4407                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4408
4409         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4410
4411         WARN_ON(ret == -EDEADLK);
4412         return ret;
4413 }
4414
4415 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4416 {
4417         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4418                 intel_has_gpu_reset(&dev_priv->gt));
4419 }
4420
4421 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4422 {
4423         struct drm_device *dev = &dev_priv->drm;
4424         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4425         struct drm_atomic_state *state;
4426         int ret;
4427
4428         /* reset doesn't touch the display */
4429         if (!i915_modparams.force_reset_modeset_test &&
4430             !gpu_reset_clobbers_display(dev_priv))
4431                 return;
4432
4433         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4434         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4435         smp_mb__after_atomic();
4436         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4437
4438         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4439                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4440                 intel_gt_set_wedged(&dev_priv->gt);
4441         }
4442
4443         /*
4444          * Need mode_config.mutex so that we don't
4445          * trample ongoing ->detect() and whatnot.
4446          */
4447         mutex_lock(&dev->mode_config.mutex);
4448         drm_modeset_acquire_init(ctx, 0);
4449         while (1) {
4450                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4451                 if (ret != -EDEADLK)
4452                         break;
4453
4454                 drm_modeset_backoff(ctx);
4455         }
4456         /*
4457          * Disabling the crtcs gracefully seems nicer. Also the
4458          * g33 docs say we should at least disable all the planes.
4459          */
4460         state = drm_atomic_helper_duplicate_state(dev, ctx);
4461         if (IS_ERR(state)) {
4462                 ret = PTR_ERR(state);
4463                 DRM_ERROR("Duplicating state failed with %i\n", ret);
4464                 return;
4465         }
4466
4467         ret = drm_atomic_helper_disable_all(dev, ctx);
4468         if (ret) {
4469                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4470                 drm_atomic_state_put(state);
4471                 return;
4472         }
4473
4474         dev_priv->modeset_restore_state = state;
4475         state->acquire_ctx = ctx;
4476 }
4477
4478 void intel_finish_reset(struct drm_i915_private *dev_priv)
4479 {
4480         struct drm_device *dev = &dev_priv->drm;
4481         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4482         struct drm_atomic_state *state;
4483         int ret;
4484
4485         /* reset doesn't touch the display */
4486         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4487                 return;
4488
4489         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4490         if (!state)
4491                 goto unlock;
4492
4493         /* reset doesn't touch the display */
4494         if (!gpu_reset_clobbers_display(dev_priv)) {
4495                 /* for testing only restore the display */
4496                 ret = __intel_display_resume(dev, state, ctx);
4497                 if (ret)
4498                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4499         } else {
4500                 /*
4501                  * The display has been reset as well,
4502                  * so need a full re-initialization.
4503                  */
4504                 intel_pps_unlock_regs_wa(dev_priv);
4505                 intel_modeset_init_hw(dev_priv);
4506                 intel_init_clock_gating(dev_priv);
4507
4508                 spin_lock_irq(&dev_priv->irq_lock);
4509                 if (dev_priv->display.hpd_irq_setup)
4510                         dev_priv->display.hpd_irq_setup(dev_priv);
4511                 spin_unlock_irq(&dev_priv->irq_lock);
4512
4513                 ret = __intel_display_resume(dev, state, ctx);
4514                 if (ret)
4515                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4516
4517                 intel_hpd_init(dev_priv);
4518         }
4519
4520         drm_atomic_state_put(state);
4521 unlock:
4522         drm_modeset_drop_locks(ctx);
4523         drm_modeset_acquire_fini(ctx);
4524         mutex_unlock(&dev->mode_config.mutex);
4525
4526         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4527 }
4528
4529 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4530 {
4531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4532         enum pipe pipe = crtc->pipe;
4533         u32 tmp;
4534
4535         tmp = I915_READ(PIPE_CHICKEN(pipe));
4536
4537         /*
4538          * Display WA #1153: icl
4539          * enable hardware to bypass the alpha math
4540          * and rounding for per-pixel values 00 and 0xff
4541          */
4542         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4543         /*
4544          * Display WA # 1605353570: icl
4545          * Set the pixel rounding bit to 1 for allowing
4546          * passthrough of Frame buffer pixels unmodified
4547          * across pipe
4548          */
4549         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4550         I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4551 }
4552
4553 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
4554 {
4555         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4556         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4557         u32 trans_ddi_func_ctl2_val;
4558         u8 master_select;
4559
4560         /*
4561          * Configure the master select and enable Transcoder Port Sync for
4562          * Slave CRTCs transcoder.
4563          */
4564         if (crtc_state->master_transcoder == INVALID_TRANSCODER)
4565                 return;
4566
4567         if (crtc_state->master_transcoder == TRANSCODER_EDP)
4568                 master_select = 0;
4569         else
4570                 master_select = crtc_state->master_transcoder + 1;
4571
4572         /* Set the master select bits for Tranascoder Port Sync */
4573         trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
4574                                    PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
4575                 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
4576         /* Enable Transcoder Port Sync */
4577         trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
4578
4579         I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
4580                    trans_ddi_func_ctl2_val);
4581 }
4582
4583 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
4584 {
4585         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4586         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4587         i915_reg_t reg;
4588         u32 trans_ddi_func_ctl2_val;
4589
4590         if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
4591                 return;
4592
4593         DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
4594                       transcoder_name(old_crtc_state->cpu_transcoder));
4595
4596         reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
4597         trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
4598                                     PORT_SYNC_MODE_MASTER_SELECT_MASK);
4599         I915_WRITE(reg, trans_ddi_func_ctl2_val);
4600 }
4601
4602 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4603 {
4604         struct drm_device *dev = crtc->base.dev;
4605         struct drm_i915_private *dev_priv = to_i915(dev);
4606         enum pipe pipe = crtc->pipe;
4607         i915_reg_t reg;
4608         u32 temp;
4609
4610         /* enable normal train */
4611         reg = FDI_TX_CTL(pipe);
4612         temp = I915_READ(reg);
4613         if (IS_IVYBRIDGE(dev_priv)) {
4614                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4615                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4616         } else {
4617                 temp &= ~FDI_LINK_TRAIN_NONE;
4618                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4619         }
4620         I915_WRITE(reg, temp);
4621
4622         reg = FDI_RX_CTL(pipe);
4623         temp = I915_READ(reg);
4624         if (HAS_PCH_CPT(dev_priv)) {
4625                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4626                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4627         } else {
4628                 temp &= ~FDI_LINK_TRAIN_NONE;
4629                 temp |= FDI_LINK_TRAIN_NONE;
4630         }
4631         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4632
4633         /* wait one idle pattern time */
4634         POSTING_READ(reg);
4635         udelay(1000);
4636
4637         /* IVB wants error correction enabled */
4638         if (IS_IVYBRIDGE(dev_priv))
4639                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4640                            FDI_FE_ERRC_ENABLE);
4641 }
4642
4643 /* The FDI link training functions for ILK/Ibexpeak. */
4644 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4645                                     const struct intel_crtc_state *crtc_state)
4646 {
4647         struct drm_device *dev = crtc->base.dev;
4648         struct drm_i915_private *dev_priv = to_i915(dev);
4649         enum pipe pipe = crtc->pipe;
4650         i915_reg_t reg;
4651         u32 temp, tries;
4652
4653         /* FDI needs bits from pipe first */
4654         assert_pipe_enabled(dev_priv, pipe);
4655
4656         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4657            for train result */
4658         reg = FDI_RX_IMR(pipe);
4659         temp = I915_READ(reg);
4660         temp &= ~FDI_RX_SYMBOL_LOCK;
4661         temp &= ~FDI_RX_BIT_LOCK;
4662         I915_WRITE(reg, temp);
4663         I915_READ(reg);
4664         udelay(150);
4665
4666         /* enable CPU FDI TX and PCH FDI RX */
4667         reg = FDI_TX_CTL(pipe);
4668         temp = I915_READ(reg);
4669         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4670         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4671         temp &= ~FDI_LINK_TRAIN_NONE;
4672         temp |= FDI_LINK_TRAIN_PATTERN_1;
4673         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4674
4675         reg = FDI_RX_CTL(pipe);
4676         temp = I915_READ(reg);
4677         temp &= ~FDI_LINK_TRAIN_NONE;
4678         temp |= FDI_LINK_TRAIN_PATTERN_1;
4679         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4680
4681         POSTING_READ(reg);
4682         udelay(150);
4683
4684         /* Ironlake workaround, enable clock pointer after FDI enable*/
4685         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4686         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4687                    FDI_RX_PHASE_SYNC_POINTER_EN);
4688
4689         reg = FDI_RX_IIR(pipe);
4690         for (tries = 0; tries < 5; tries++) {
4691                 temp = I915_READ(reg);
4692                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4693
4694                 if ((temp & FDI_RX_BIT_LOCK)) {
4695                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4696                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4697                         break;
4698                 }
4699         }
4700         if (tries == 5)
4701                 DRM_ERROR("FDI train 1 fail!\n");
4702
4703         /* Train 2 */
4704         reg = FDI_TX_CTL(pipe);
4705         temp = I915_READ(reg);
4706         temp &= ~FDI_LINK_TRAIN_NONE;
4707         temp |= FDI_LINK_TRAIN_PATTERN_2;
4708         I915_WRITE(reg, temp);
4709
4710         reg = FDI_RX_CTL(pipe);
4711         temp = I915_READ(reg);
4712         temp &= ~FDI_LINK_TRAIN_NONE;
4713         temp |= FDI_LINK_TRAIN_PATTERN_2;
4714         I915_WRITE(reg, temp);
4715
4716         POSTING_READ(reg);
4717         udelay(150);
4718
4719         reg = FDI_RX_IIR(pipe);
4720         for (tries = 0; tries < 5; tries++) {
4721                 temp = I915_READ(reg);
4722                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4723
4724                 if (temp & FDI_RX_SYMBOL_LOCK) {
4725                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4726                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4727                         break;
4728                 }
4729         }
4730         if (tries == 5)
4731                 DRM_ERROR("FDI train 2 fail!\n");
4732
4733         DRM_DEBUG_KMS("FDI train done\n");
4734
4735 }
4736
4737 static const int snb_b_fdi_train_param[] = {
4738         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4739         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4740         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4741         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4742 };
4743
4744 /* The FDI link training functions for SNB/Cougarpoint. */
4745 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4746                                 const struct intel_crtc_state *crtc_state)
4747 {
4748         struct drm_device *dev = crtc->base.dev;
4749         struct drm_i915_private *dev_priv = to_i915(dev);
4750         enum pipe pipe = crtc->pipe;
4751         i915_reg_t reg;
4752         u32 temp, i, retry;
4753
4754         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4755            for train result */
4756         reg = FDI_RX_IMR(pipe);
4757         temp = I915_READ(reg);
4758         temp &= ~FDI_RX_SYMBOL_LOCK;
4759         temp &= ~FDI_RX_BIT_LOCK;
4760         I915_WRITE(reg, temp);
4761
4762         POSTING_READ(reg);
4763         udelay(150);
4764
4765         /* enable CPU FDI TX and PCH FDI RX */
4766         reg = FDI_TX_CTL(pipe);
4767         temp = I915_READ(reg);
4768         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4769         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4770         temp &= ~FDI_LINK_TRAIN_NONE;
4771         temp |= FDI_LINK_TRAIN_PATTERN_1;
4772         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4773         /* SNB-B */
4774         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4775         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4776
4777         I915_WRITE(FDI_RX_MISC(pipe),
4778                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4779
4780         reg = FDI_RX_CTL(pipe);
4781         temp = I915_READ(reg);
4782         if (HAS_PCH_CPT(dev_priv)) {
4783                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4784                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4785         } else {
4786                 temp &= ~FDI_LINK_TRAIN_NONE;
4787                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4788         }
4789         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4790
4791         POSTING_READ(reg);
4792         udelay(150);
4793
4794         for (i = 0; i < 4; i++) {
4795                 reg = FDI_TX_CTL(pipe);
4796                 temp = I915_READ(reg);
4797                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4798                 temp |= snb_b_fdi_train_param[i];
4799                 I915_WRITE(reg, temp);
4800
4801                 POSTING_READ(reg);
4802                 udelay(500);
4803
4804                 for (retry = 0; retry < 5; retry++) {
4805                         reg = FDI_RX_IIR(pipe);
4806                         temp = I915_READ(reg);
4807                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4808                         if (temp & FDI_RX_BIT_LOCK) {
4809                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4810                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4811                                 break;
4812                         }
4813                         udelay(50);
4814                 }
4815                 if (retry < 5)
4816                         break;
4817         }
4818         if (i == 4)
4819                 DRM_ERROR("FDI train 1 fail!\n");
4820
4821         /* Train 2 */
4822         reg = FDI_TX_CTL(pipe);
4823         temp = I915_READ(reg);
4824         temp &= ~FDI_LINK_TRAIN_NONE;
4825         temp |= FDI_LINK_TRAIN_PATTERN_2;
4826         if (IS_GEN(dev_priv, 6)) {
4827                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4828                 /* SNB-B */
4829                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4830         }
4831         I915_WRITE(reg, temp);
4832
4833         reg = FDI_RX_CTL(pipe);
4834         temp = I915_READ(reg);
4835         if (HAS_PCH_CPT(dev_priv)) {
4836                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4837                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4838         } else {
4839                 temp &= ~FDI_LINK_TRAIN_NONE;
4840                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4841         }
4842         I915_WRITE(reg, temp);
4843
4844         POSTING_READ(reg);
4845         udelay(150);
4846
4847         for (i = 0; i < 4; i++) {
4848                 reg = FDI_TX_CTL(pipe);
4849                 temp = I915_READ(reg);
4850                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4851                 temp |= snb_b_fdi_train_param[i];
4852                 I915_WRITE(reg, temp);
4853
4854                 POSTING_READ(reg);
4855                 udelay(500);
4856
4857                 for (retry = 0; retry < 5; retry++) {
4858                         reg = FDI_RX_IIR(pipe);
4859                         temp = I915_READ(reg);
4860                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4861                         if (temp & FDI_RX_SYMBOL_LOCK) {
4862                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4863                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4864                                 break;
4865                         }
4866                         udelay(50);
4867                 }
4868                 if (retry < 5)
4869                         break;
4870         }
4871         if (i == 4)
4872                 DRM_ERROR("FDI train 2 fail!\n");
4873
4874         DRM_DEBUG_KMS("FDI train done.\n");
4875 }
4876
4877 /* Manual link training for Ivy Bridge A0 parts */
4878 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4879                                       const struct intel_crtc_state *crtc_state)
4880 {
4881         struct drm_device *dev = crtc->base.dev;
4882         struct drm_i915_private *dev_priv = to_i915(dev);
4883         enum pipe pipe = crtc->pipe;
4884         i915_reg_t reg;
4885         u32 temp, i, j;
4886
4887         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4888            for train result */
4889         reg = FDI_RX_IMR(pipe);
4890         temp = I915_READ(reg);
4891         temp &= ~FDI_RX_SYMBOL_LOCK;
4892         temp &= ~FDI_RX_BIT_LOCK;
4893         I915_WRITE(reg, temp);
4894
4895         POSTING_READ(reg);
4896         udelay(150);
4897
4898         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4899                       I915_READ(FDI_RX_IIR(pipe)));
4900
4901         /* Try each vswing and preemphasis setting twice before moving on */
4902         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4903                 /* disable first in case we need to retry */
4904                 reg = FDI_TX_CTL(pipe);
4905                 temp = I915_READ(reg);
4906                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4907                 temp &= ~FDI_TX_ENABLE;
4908                 I915_WRITE(reg, temp);
4909
4910                 reg = FDI_RX_CTL(pipe);
4911                 temp = I915_READ(reg);
4912                 temp &= ~FDI_LINK_TRAIN_AUTO;
4913                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4914                 temp &= ~FDI_RX_ENABLE;
4915                 I915_WRITE(reg, temp);
4916
4917                 /* enable CPU FDI TX and PCH FDI RX */
4918                 reg = FDI_TX_CTL(pipe);
4919                 temp = I915_READ(reg);
4920                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4921                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4922                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4923                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4924                 temp |= snb_b_fdi_train_param[j/2];
4925                 temp |= FDI_COMPOSITE_SYNC;
4926                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4927
4928                 I915_WRITE(FDI_RX_MISC(pipe),
4929                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4930
4931                 reg = FDI_RX_CTL(pipe);
4932                 temp = I915_READ(reg);
4933                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4934                 temp |= FDI_COMPOSITE_SYNC;
4935                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4936
4937                 POSTING_READ(reg);
4938                 udelay(1); /* should be 0.5us */
4939
4940                 for (i = 0; i < 4; i++) {
4941                         reg = FDI_RX_IIR(pipe);
4942                         temp = I915_READ(reg);
4943                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4944
4945                         if (temp & FDI_RX_BIT_LOCK ||
4946                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4947                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4948                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4949                                               i);
4950                                 break;
4951                         }
4952                         udelay(1); /* should be 0.5us */
4953                 }
4954                 if (i == 4) {
4955                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4956                         continue;
4957                 }
4958
4959                 /* Train 2 */
4960                 reg = FDI_TX_CTL(pipe);
4961                 temp = I915_READ(reg);
4962                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4963                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4964                 I915_WRITE(reg, temp);
4965
4966                 reg = FDI_RX_CTL(pipe);
4967                 temp = I915_READ(reg);
4968                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4969                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4970                 I915_WRITE(reg, temp);
4971
4972                 POSTING_READ(reg);
4973                 udelay(2); /* should be 1.5us */
4974
4975                 for (i = 0; i < 4; i++) {
4976                         reg = FDI_RX_IIR(pipe);
4977                         temp = I915_READ(reg);
4978                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4979
4980                         if (temp & FDI_RX_SYMBOL_LOCK ||
4981                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4982                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4983                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4984                                               i);
4985                                 goto train_done;
4986                         }
4987                         udelay(2); /* should be 1.5us */
4988                 }
4989                 if (i == 4)
4990                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4991         }
4992
4993 train_done:
4994         DRM_DEBUG_KMS("FDI train done.\n");
4995 }
4996
4997 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4998 {
4999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5000         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5001         enum pipe pipe = intel_crtc->pipe;
5002         i915_reg_t reg;
5003         u32 temp;
5004
5005         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5006         reg = FDI_RX_CTL(pipe);
5007         temp = I915_READ(reg);
5008         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5009         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5010         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5011         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
5012
5013         POSTING_READ(reg);
5014         udelay(200);
5015
5016         /* Switch from Rawclk to PCDclk */
5017         temp = I915_READ(reg);
5018         I915_WRITE(reg, temp | FDI_PCDCLK);
5019
5020         POSTING_READ(reg);
5021         udelay(200);
5022
5023         /* Enable CPU FDI TX PLL, always on for Ironlake */
5024         reg = FDI_TX_CTL(pipe);
5025         temp = I915_READ(reg);
5026         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5027                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5028
5029                 POSTING_READ(reg);
5030                 udelay(100);
5031         }
5032 }
5033
5034 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
5035 {
5036         struct drm_device *dev = intel_crtc->base.dev;
5037         struct drm_i915_private *dev_priv = to_i915(dev);
5038         enum pipe pipe = intel_crtc->pipe;
5039         i915_reg_t reg;
5040         u32 temp;
5041
5042         /* Switch from PCDclk to Rawclk */
5043         reg = FDI_RX_CTL(pipe);
5044         temp = I915_READ(reg);
5045         I915_WRITE(reg, temp & ~FDI_PCDCLK);
5046
5047         /* Disable CPU FDI TX PLL */
5048         reg = FDI_TX_CTL(pipe);
5049         temp = I915_READ(reg);
5050         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
5051
5052         POSTING_READ(reg);
5053         udelay(100);
5054
5055         reg = FDI_RX_CTL(pipe);
5056         temp = I915_READ(reg);
5057         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
5058
5059         /* Wait for the clocks to turn off. */
5060         POSTING_READ(reg);
5061         udelay(100);
5062 }
5063
5064 static void ironlake_fdi_disable(struct intel_crtc *crtc)
5065 {
5066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5067         enum pipe pipe = crtc->pipe;
5068         i915_reg_t reg;
5069         u32 temp;
5070
5071         /* disable CPU FDI tx and PCH FDI rx */
5072         reg = FDI_TX_CTL(pipe);
5073         temp = I915_READ(reg);
5074         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
5075         POSTING_READ(reg);
5076
5077         reg = FDI_RX_CTL(pipe);
5078         temp = I915_READ(reg);
5079         temp &= ~(0x7 << 16);
5080         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5081         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
5082
5083         POSTING_READ(reg);
5084         udelay(100);
5085
5086         /* Ironlake workaround, disable clock pointer after downing FDI */
5087         if (HAS_PCH_IBX(dev_priv))
5088                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
5089
5090         /* still set train pattern 1 */
5091         reg = FDI_TX_CTL(pipe);
5092         temp = I915_READ(reg);
5093         temp &= ~FDI_LINK_TRAIN_NONE;
5094         temp |= FDI_LINK_TRAIN_PATTERN_1;
5095         I915_WRITE(reg, temp);
5096
5097         reg = FDI_RX_CTL(pipe);
5098         temp = I915_READ(reg);
5099         if (HAS_PCH_CPT(dev_priv)) {
5100                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5101                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5102         } else {
5103                 temp &= ~FDI_LINK_TRAIN_NONE;
5104                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5105         }
5106         /* BPC in FDI rx is consistent with that in PIPECONF */
5107         temp &= ~(0x07 << 16);
5108         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5109         I915_WRITE(reg, temp);
5110
5111         POSTING_READ(reg);
5112         udelay(100);
5113 }
5114
5115 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5116 {
5117         struct drm_crtc *crtc;
5118         bool cleanup_done;
5119
5120         drm_for_each_crtc(crtc, &dev_priv->drm) {
5121                 struct drm_crtc_commit *commit;
5122                 spin_lock(&crtc->commit_lock);
5123                 commit = list_first_entry_or_null(&crtc->commit_list,
5124                                                   struct drm_crtc_commit, commit_entry);
5125                 cleanup_done = commit ?
5126                         try_wait_for_completion(&commit->cleanup_done) : true;
5127                 spin_unlock(&crtc->commit_lock);
5128
5129                 if (cleanup_done)
5130                         continue;
5131
5132                 drm_crtc_wait_one_vblank(crtc);
5133
5134                 return true;
5135         }
5136
5137         return false;
5138 }
5139
5140 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5141 {
5142         u32 temp;
5143
5144         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
5145
5146         mutex_lock(&dev_priv->sb_lock);
5147
5148         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5149         temp |= SBI_SSCCTL_DISABLE;
5150         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5151
5152         mutex_unlock(&dev_priv->sb_lock);
5153 }
5154
5155 /* Program iCLKIP clock to the desired frequency */
5156 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5157 {
5158         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5159         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5160         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5161         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5162         u32 temp;
5163
5164         lpt_disable_iclkip(dev_priv);
5165
5166         /* The iCLK virtual clock root frequency is in MHz,
5167          * but the adjusted_mode->crtc_clock in in KHz. To get the
5168          * divisors, it is necessary to divide one by another, so we
5169          * convert the virtual clock precision to KHz here for higher
5170          * precision.
5171          */
5172         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5173                 u32 iclk_virtual_root_freq = 172800 * 1000;
5174                 u32 iclk_pi_range = 64;
5175                 u32 desired_divisor;
5176
5177                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5178                                                     clock << auxdiv);
5179                 divsel = (desired_divisor / iclk_pi_range) - 2;
5180                 phaseinc = desired_divisor % iclk_pi_range;
5181
5182                 /*
5183                  * Near 20MHz is a corner case which is
5184                  * out of range for the 7-bit divisor
5185                  */
5186                 if (divsel <= 0x7f)
5187                         break;
5188         }
5189
5190         /* This should not happen with any sane values */
5191         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5192                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5193         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5194                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5195
5196         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5197                         clock,
5198                         auxdiv,
5199                         divsel,
5200                         phasedir,
5201                         phaseinc);
5202
5203         mutex_lock(&dev_priv->sb_lock);
5204
5205         /* Program SSCDIVINTPHASE6 */
5206         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5207         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5208         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5209         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5210         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5211         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5212         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5213         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5214
5215         /* Program SSCAUXDIV */
5216         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5217         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5218         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5219         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5220
5221         /* Enable modulator and associated divider */
5222         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5223         temp &= ~SBI_SSCCTL_DISABLE;
5224         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5225
5226         mutex_unlock(&dev_priv->sb_lock);
5227
5228         /* Wait for initialization time */
5229         udelay(24);
5230
5231         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5232 }
5233
5234 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5235 {
5236         u32 divsel, phaseinc, auxdiv;
5237         u32 iclk_virtual_root_freq = 172800 * 1000;
5238         u32 iclk_pi_range = 64;
5239         u32 desired_divisor;
5240         u32 temp;
5241
5242         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5243                 return 0;
5244
5245         mutex_lock(&dev_priv->sb_lock);
5246
5247         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5248         if (temp & SBI_SSCCTL_DISABLE) {
5249                 mutex_unlock(&dev_priv->sb_lock);
5250                 return 0;
5251         }
5252
5253         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5254         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5255                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5256         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5257                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5258
5259         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5260         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5261                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5262
5263         mutex_unlock(&dev_priv->sb_lock);
5264
5265         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5266
5267         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5268                                  desired_divisor << auxdiv);
5269 }
5270
5271 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5272                                                 enum pipe pch_transcoder)
5273 {
5274         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5275         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5276         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5277
5278         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5279                    I915_READ(HTOTAL(cpu_transcoder)));
5280         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5281                    I915_READ(HBLANK(cpu_transcoder)));
5282         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5283                    I915_READ(HSYNC(cpu_transcoder)));
5284
5285         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5286                    I915_READ(VTOTAL(cpu_transcoder)));
5287         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5288                    I915_READ(VBLANK(cpu_transcoder)));
5289         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5290                    I915_READ(VSYNC(cpu_transcoder)));
5291         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5292                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
5293 }
5294
5295 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5296 {
5297         u32 temp;
5298
5299         temp = I915_READ(SOUTH_CHICKEN1);
5300         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5301                 return;
5302
5303         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5304         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5305
5306         temp &= ~FDI_BC_BIFURCATION_SELECT;
5307         if (enable)
5308                 temp |= FDI_BC_BIFURCATION_SELECT;
5309
5310         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5311         I915_WRITE(SOUTH_CHICKEN1, temp);
5312         POSTING_READ(SOUTH_CHICKEN1);
5313 }
5314
5315 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5316 {
5317         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5318         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5319
5320         switch (crtc->pipe) {
5321         case PIPE_A:
5322                 break;
5323         case PIPE_B:
5324                 if (crtc_state->fdi_lanes > 2)
5325                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5326                 else
5327                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5328
5329                 break;
5330         case PIPE_C:
5331                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5332
5333                 break;
5334         default:
5335                 BUG();
5336         }
5337 }
5338
5339 /*
5340  * Finds the encoder associated with the given CRTC. This can only be
5341  * used when we know that the CRTC isn't feeding multiple encoders!
5342  */
5343 static struct intel_encoder *
5344 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5345                            const struct intel_crtc_state *crtc_state)
5346 {
5347         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5348         const struct drm_connector_state *connector_state;
5349         const struct drm_connector *connector;
5350         struct intel_encoder *encoder = NULL;
5351         int num_encoders = 0;
5352         int i;
5353
5354         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5355                 if (connector_state->crtc != &crtc->base)
5356                         continue;
5357
5358                 encoder = to_intel_encoder(connector_state->best_encoder);
5359                 num_encoders++;
5360         }
5361
5362         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5363              num_encoders, pipe_name(crtc->pipe));
5364
5365         return encoder;
5366 }
5367
5368 /*
5369  * Enable PCH resources required for PCH ports:
5370  *   - PCH PLLs
5371  *   - FDI training & RX/TX
5372  *   - update transcoder timings
5373  *   - DP transcoding bits
5374  *   - transcoder
5375  */
5376 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5377                                 const struct intel_crtc_state *crtc_state)
5378 {
5379         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5380         struct drm_device *dev = crtc->base.dev;
5381         struct drm_i915_private *dev_priv = to_i915(dev);
5382         enum pipe pipe = crtc->pipe;
5383         u32 temp;
5384
5385         assert_pch_transcoder_disabled(dev_priv, pipe);
5386
5387         if (IS_IVYBRIDGE(dev_priv))
5388                 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5389
5390         /* Write the TU size bits before fdi link training, so that error
5391          * detection works. */
5392         I915_WRITE(FDI_RX_TUSIZE1(pipe),
5393                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5394
5395         /* For PCH output, training FDI link */
5396         dev_priv->display.fdi_link_train(crtc, crtc_state);
5397
5398         /* We need to program the right clock selection before writing the pixel
5399          * mutliplier into the DPLL. */
5400         if (HAS_PCH_CPT(dev_priv)) {
5401                 u32 sel;
5402
5403                 temp = I915_READ(PCH_DPLL_SEL);
5404                 temp |= TRANS_DPLL_ENABLE(pipe);
5405                 sel = TRANS_DPLLB_SEL(pipe);
5406                 if (crtc_state->shared_dpll ==
5407                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5408                         temp |= sel;
5409                 else
5410                         temp &= ~sel;
5411                 I915_WRITE(PCH_DPLL_SEL, temp);
5412         }
5413
5414         /* XXX: pch pll's can be enabled any time before we enable the PCH
5415          * transcoder, and we actually should do this to not upset any PCH
5416          * transcoder that already use the clock when we share it.
5417          *
5418          * Note that enable_shared_dpll tries to do the right thing, but
5419          * get_shared_dpll unconditionally resets the pll - we need that to have
5420          * the right LVDS enable sequence. */
5421         intel_enable_shared_dpll(crtc_state);
5422
5423         /* set transcoder timing, panel must allow it */
5424         assert_panel_unlocked(dev_priv, pipe);
5425         ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5426
5427         intel_fdi_normal_train(crtc);
5428
5429         /* For PCH DP, enable TRANS_DP_CTL */
5430         if (HAS_PCH_CPT(dev_priv) &&
5431             intel_crtc_has_dp_encoder(crtc_state)) {
5432                 const struct drm_display_mode *adjusted_mode =
5433                         &crtc_state->hw.adjusted_mode;
5434                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5435                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5436                 enum port port;
5437
5438                 temp = I915_READ(reg);
5439                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5440                           TRANS_DP_SYNC_MASK |
5441                           TRANS_DP_BPC_MASK);
5442                 temp |= TRANS_DP_OUTPUT_ENABLE;
5443                 temp |= bpc << 9; /* same format but at 11:9 */
5444
5445                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5446                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5447                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5448                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5449
5450                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5451                 WARN_ON(port < PORT_B || port > PORT_D);
5452                 temp |= TRANS_DP_PORT_SEL(port);
5453
5454                 I915_WRITE(reg, temp);
5455         }
5456
5457         ironlake_enable_pch_transcoder(crtc_state);
5458 }
5459
5460 static void lpt_pch_enable(const struct intel_atomic_state *state,
5461                            const struct intel_crtc_state *crtc_state)
5462 {
5463         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5465         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5466
5467         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5468
5469         lpt_program_iclkip(crtc_state);
5470
5471         /* Set transcoder timing. */
5472         ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5473
5474         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5475 }
5476
5477 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5478                                enum pipe pipe)
5479 {
5480         i915_reg_t dslreg = PIPEDSL(pipe);
5481         u32 temp;
5482
5483         temp = I915_READ(dslreg);
5484         udelay(500);
5485         if (wait_for(I915_READ(dslreg) != temp, 5)) {
5486                 if (wait_for(I915_READ(dslreg) != temp, 5))
5487                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5488         }
5489 }
5490
5491 /*
5492  * The hardware phase 0.0 refers to the center of the pixel.
5493  * We want to start from the top/left edge which is phase
5494  * -0.5. That matches how the hardware calculates the scaling
5495  * factors (from top-left of the first pixel to bottom-right
5496  * of the last pixel, as opposed to the pixel centers).
5497  *
5498  * For 4:2:0 subsampled chroma planes we obviously have to
5499  * adjust that so that the chroma sample position lands in
5500  * the right spot.
5501  *
5502  * Note that for packed YCbCr 4:2:2 formats there is no way to
5503  * control chroma siting. The hardware simply replicates the
5504  * chroma samples for both of the luma samples, and thus we don't
5505  * actually get the expected MPEG2 chroma siting convention :(
5506  * The same behaviour is observed on pre-SKL platforms as well.
5507  *
5508  * Theory behind the formula (note that we ignore sub-pixel
5509  * source coordinates):
5510  * s = source sample position
5511  * d = destination sample position
5512  *
5513  * Downscaling 4:1:
5514  * -0.5
5515  * | 0.0
5516  * | |     1.5 (initial phase)
5517  * | |     |
5518  * v v     v
5519  * | s | s | s | s |
5520  * |       d       |
5521  *
5522  * Upscaling 1:4:
5523  * -0.5
5524  * | -0.375 (initial phase)
5525  * | |     0.0
5526  * | |     |
5527  * v v     v
5528  * |       s       |
5529  * | d | d | d | d |
5530  */
5531 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5532 {
5533         int phase = -0x8000;
5534         u16 trip = 0;
5535
5536         if (chroma_cosited)
5537                 phase += (sub - 1) * 0x8000 / sub;
5538
5539         phase += scale / (2 * sub);
5540
5541         /*
5542          * Hardware initial phase limited to [-0.5:1.5].
5543          * Since the max hardware scale factor is 3.0, we
5544          * should never actually excdeed 1.0 here.
5545          */
5546         WARN_ON(phase < -0x8000 || phase > 0x18000);
5547
5548         if (phase < 0)
5549                 phase = 0x10000 + phase;
5550         else
5551                 trip = PS_PHASE_TRIP;
5552
5553         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5554 }
5555
5556 #define SKL_MIN_SRC_W 8
5557 #define SKL_MAX_SRC_W 4096
5558 #define SKL_MIN_SRC_H 8
5559 #define SKL_MAX_SRC_H 4096
5560 #define SKL_MIN_DST_W 8
5561 #define SKL_MAX_DST_W 4096
5562 #define SKL_MIN_DST_H 8
5563 #define SKL_MAX_DST_H 4096
5564 #define ICL_MAX_SRC_W 5120
5565 #define ICL_MAX_SRC_H 4096
5566 #define ICL_MAX_DST_W 5120
5567 #define ICL_MAX_DST_H 4096
5568 #define SKL_MIN_YUV_420_SRC_W 16
5569 #define SKL_MIN_YUV_420_SRC_H 16
5570
5571 static int
5572 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5573                   unsigned int scaler_user, int *scaler_id,
5574                   int src_w, int src_h, int dst_w, int dst_h,
5575                   const struct drm_format_info *format, bool need_scaler)
5576 {
5577         struct intel_crtc_scaler_state *scaler_state =
5578                 &crtc_state->scaler_state;
5579         struct intel_crtc *intel_crtc =
5580                 to_intel_crtc(crtc_state->uapi.crtc);
5581         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5582         const struct drm_display_mode *adjusted_mode =
5583                 &crtc_state->hw.adjusted_mode;
5584
5585         /*
5586          * Src coordinates are already rotated by 270 degrees for
5587          * the 90/270 degree plane rotation cases (to match the
5588          * GTT mapping), hence no need to account for rotation here.
5589          */
5590         if (src_w != dst_w || src_h != dst_h)
5591                 need_scaler = true;
5592
5593         /*
5594          * Scaling/fitting not supported in IF-ID mode in GEN9+
5595          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5596          * Once NV12 is enabled, handle it here while allocating scaler
5597          * for NV12.
5598          */
5599         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
5600             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5601                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5602                 return -EINVAL;
5603         }
5604
5605         /*
5606          * if plane is being disabled or scaler is no more required or force detach
5607          *  - free scaler binded to this plane/crtc
5608          *  - in order to do this, update crtc->scaler_usage
5609          *
5610          * Here scaler state in crtc_state is set free so that
5611          * scaler can be assigned to other user. Actual register
5612          * update to free the scaler is done in plane/panel-fit programming.
5613          * For this purpose crtc/plane_state->scaler_id isn't reset here.
5614          */
5615         if (force_detach || !need_scaler) {
5616                 if (*scaler_id >= 0) {
5617                         scaler_state->scaler_users &= ~(1 << scaler_user);
5618                         scaler_state->scalers[*scaler_id].in_use = 0;
5619
5620                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5621                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5622                                 intel_crtc->pipe, scaler_user, *scaler_id,
5623                                 scaler_state->scaler_users);
5624                         *scaler_id = -1;
5625                 }
5626                 return 0;
5627         }
5628
5629         if (format && drm_format_info_is_yuv_semiplanar(format) &&
5630             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5631                 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5632                 return -EINVAL;
5633         }
5634
5635         /* range checks */
5636         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5637             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5638             (INTEL_GEN(dev_priv) >= 11 &&
5639              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5640               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5641             (INTEL_GEN(dev_priv) < 11 &&
5642              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5643               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5644                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5645                         "size is out of scaler range\n",
5646                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5647                 return -EINVAL;
5648         }
5649
5650         /* mark this plane as a scaler user in crtc_state */
5651         scaler_state->scaler_users |= (1 << scaler_user);
5652         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5653                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5654                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5655                 scaler_state->scaler_users);
5656
5657         return 0;
5658 }
5659
5660 /**
5661  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5662  *
5663  * @state: crtc's scaler state
5664  *
5665  * Return
5666  *     0 - scaler_usage updated successfully
5667  *    error - requested scaling cannot be supported or other error condition
5668  */
5669 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5670 {
5671         const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
5672         bool need_scaler = false;
5673
5674         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5675                 need_scaler = true;
5676
5677         return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
5678                                  &state->scaler_state.scaler_id,
5679                                  state->pipe_src_w, state->pipe_src_h,
5680                                  adjusted_mode->crtc_hdisplay,
5681                                  adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5682 }
5683
5684 /**
5685  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5686  * @crtc_state: crtc's scaler state
5687  * @plane_state: atomic plane state to update
5688  *
5689  * Return
5690  *     0 - scaler_usage updated successfully
5691  *    error - requested scaling cannot be supported or other error condition
5692  */
5693 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5694                                    struct intel_plane_state *plane_state)
5695 {
5696         struct intel_plane *intel_plane =
5697                 to_intel_plane(plane_state->uapi.plane);
5698         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5699         struct drm_framebuffer *fb = plane_state->hw.fb;
5700         int ret;
5701         bool force_detach = !fb || !plane_state->uapi.visible;
5702         bool need_scaler = false;
5703
5704         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5705         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5706             fb && drm_format_info_is_yuv_semiplanar(fb->format))
5707                 need_scaler = true;
5708
5709         ret = skl_update_scaler(crtc_state, force_detach,
5710                                 drm_plane_index(&intel_plane->base),
5711                                 &plane_state->scaler_id,
5712                                 drm_rect_width(&plane_state->uapi.src) >> 16,
5713                                 drm_rect_height(&plane_state->uapi.src) >> 16,
5714                                 drm_rect_width(&plane_state->uapi.dst),
5715                                 drm_rect_height(&plane_state->uapi.dst),
5716                                 fb ? fb->format : NULL, need_scaler);
5717
5718         if (ret || plane_state->scaler_id < 0)
5719                 return ret;
5720
5721         /* check colorkey */
5722         if (plane_state->ckey.flags) {
5723                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5724                               intel_plane->base.base.id,
5725                               intel_plane->base.name);
5726                 return -EINVAL;
5727         }
5728
5729         /* Check src format */
5730         switch (fb->format->format) {
5731         case DRM_FORMAT_RGB565:
5732         case DRM_FORMAT_XBGR8888:
5733         case DRM_FORMAT_XRGB8888:
5734         case DRM_FORMAT_ABGR8888:
5735         case DRM_FORMAT_ARGB8888:
5736         case DRM_FORMAT_XRGB2101010:
5737         case DRM_FORMAT_XBGR2101010:
5738         case DRM_FORMAT_ARGB2101010:
5739         case DRM_FORMAT_ABGR2101010:
5740         case DRM_FORMAT_YUYV:
5741         case DRM_FORMAT_YVYU:
5742         case DRM_FORMAT_UYVY:
5743         case DRM_FORMAT_VYUY:
5744         case DRM_FORMAT_NV12:
5745         case DRM_FORMAT_P010:
5746         case DRM_FORMAT_P012:
5747         case DRM_FORMAT_P016:
5748         case DRM_FORMAT_Y210:
5749         case DRM_FORMAT_Y212:
5750         case DRM_FORMAT_Y216:
5751         case DRM_FORMAT_XVYU2101010:
5752         case DRM_FORMAT_XVYU12_16161616:
5753         case DRM_FORMAT_XVYU16161616:
5754                 break;
5755         case DRM_FORMAT_XBGR16161616F:
5756         case DRM_FORMAT_ABGR16161616F:
5757         case DRM_FORMAT_XRGB16161616F:
5758         case DRM_FORMAT_ARGB16161616F:
5759                 if (INTEL_GEN(dev_priv) >= 11)
5760                         break;
5761                 /* fall through */
5762         default:
5763                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5764                               intel_plane->base.base.id, intel_plane->base.name,
5765                               fb->base.id, fb->format->format);
5766                 return -EINVAL;
5767         }
5768
5769         return 0;
5770 }
5771
5772 static void skylake_scaler_disable(struct intel_crtc *crtc)
5773 {
5774         int i;
5775
5776         for (i = 0; i < crtc->num_scalers; i++)
5777                 skl_detach_scaler(crtc, i);
5778 }
5779
5780 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5781 {
5782         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5783         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5784         enum pipe pipe = crtc->pipe;
5785         const struct intel_crtc_scaler_state *scaler_state =
5786                 &crtc_state->scaler_state;
5787
5788         if (crtc_state->pch_pfit.enabled) {
5789                 u16 uv_rgb_hphase, uv_rgb_vphase;
5790                 int pfit_w, pfit_h, hscale, vscale;
5791                 int id;
5792
5793                 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5794                         return;
5795
5796                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5797                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5798
5799                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5800                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5801
5802                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5803                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5804
5805                 id = scaler_state->scaler_id;
5806                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5807                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5808                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5809                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5810                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5811                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5812                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5813                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5814         }
5815 }
5816
5817 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5818 {
5819         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5820         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5821         enum pipe pipe = crtc->pipe;
5822
5823         if (crtc_state->pch_pfit.enabled) {
5824                 /* Force use of hard-coded filter coefficients
5825                  * as some pre-programmed values are broken,
5826                  * e.g. x201.
5827                  */
5828                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5829                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5830                                                  PF_PIPE_SEL_IVB(pipe));
5831                 else
5832                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5833                 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5834                 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5835         }
5836 }
5837
5838 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5839 {
5840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5841         struct drm_device *dev = crtc->base.dev;
5842         struct drm_i915_private *dev_priv = to_i915(dev);
5843
5844         if (!crtc_state->ips_enabled)
5845                 return;
5846
5847         /*
5848          * We can only enable IPS after we enable a plane and wait for a vblank
5849          * This function is called from post_plane_update, which is run after
5850          * a vblank wait.
5851          */
5852         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5853
5854         if (IS_BROADWELL(dev_priv)) {
5855                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5856                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5857                 /* Quoting Art Runyan: "its not safe to expect any particular
5858                  * value in IPS_CTL bit 31 after enabling IPS through the
5859                  * mailbox." Moreover, the mailbox may return a bogus state,
5860                  * so we need to just enable it and continue on.
5861                  */
5862         } else {
5863                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5864                 /* The bit only becomes 1 in the next vblank, so this wait here
5865                  * is essentially intel_wait_for_vblank. If we don't have this
5866                  * and don't wait for vblanks until the end of crtc_enable, then
5867                  * the HW state readout code will complain that the expected
5868                  * IPS_CTL value is not the one we read. */
5869                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5870                         DRM_ERROR("Timed out waiting for IPS enable\n");
5871         }
5872 }
5873
5874 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5875 {
5876         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5877         struct drm_device *dev = crtc->base.dev;
5878         struct drm_i915_private *dev_priv = to_i915(dev);
5879
5880         if (!crtc_state->ips_enabled)
5881                 return;
5882
5883         if (IS_BROADWELL(dev_priv)) {
5884                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5885                 /*
5886                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5887                  * 42ms timeout value leads to occasional timeouts so use 100ms
5888                  * instead.
5889                  */
5890                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5891                         DRM_ERROR("Timed out waiting for IPS disable\n");
5892         } else {
5893                 I915_WRITE(IPS_CTL, 0);
5894                 POSTING_READ(IPS_CTL);
5895         }
5896
5897         /* We need to wait for a vblank before we can disable the plane. */
5898         intel_wait_for_vblank(dev_priv, crtc->pipe);
5899 }
5900
5901 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5902 {
5903         if (intel_crtc->overlay)
5904                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5905
5906         /* Let userspace switch the overlay on again. In most cases userspace
5907          * has to recompute where to put it anyway.
5908          */
5909 }
5910
5911 /**
5912  * intel_post_enable_primary - Perform operations after enabling primary plane
5913  * @crtc: the CRTC whose primary plane was just enabled
5914  * @new_crtc_state: the enabling state
5915  *
5916  * Performs potentially sleeping operations that must be done after the primary
5917  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5918  * called due to an explicit primary plane update, or due to an implicit
5919  * re-enable that is caused when a sprite plane is updated to no longer
5920  * completely hide the primary plane.
5921  */
5922 static void
5923 intel_post_enable_primary(struct drm_crtc *crtc,
5924                           const struct intel_crtc_state *new_crtc_state)
5925 {
5926         struct drm_device *dev = crtc->dev;
5927         struct drm_i915_private *dev_priv = to_i915(dev);
5928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5929         enum pipe pipe = intel_crtc->pipe;
5930
5931         /*
5932          * Gen2 reports pipe underruns whenever all planes are disabled.
5933          * So don't enable underrun reporting before at least some planes
5934          * are enabled.
5935          * FIXME: Need to fix the logic to work when we turn off all planes
5936          * but leave the pipe running.
5937          */
5938         if (IS_GEN(dev_priv, 2))
5939                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5940
5941         /* Underruns don't always raise interrupts, so check manually. */
5942         intel_check_cpu_fifo_underruns(dev_priv);
5943         intel_check_pch_fifo_underruns(dev_priv);
5944 }
5945
5946 /* FIXME get rid of this and use pre_plane_update */
5947 static void
5948 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5949 {
5950         struct drm_device *dev = crtc->dev;
5951         struct drm_i915_private *dev_priv = to_i915(dev);
5952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5953         enum pipe pipe = intel_crtc->pipe;
5954
5955         /*
5956          * Gen2 reports pipe underruns whenever all planes are disabled.
5957          * So disable underrun reporting before all the planes get disabled.
5958          */
5959         if (IS_GEN(dev_priv, 2))
5960                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5961
5962         hsw_disable_ips(to_intel_crtc_state(crtc->state));
5963
5964         /*
5965          * Vblank time updates from the shadow to live plane control register
5966          * are blocked if the memory self-refresh mode is active at that
5967          * moment. So to make sure the plane gets truly disabled, disable
5968          * first the self-refresh mode. The self-refresh enable bit in turn
5969          * will be checked/applied by the HW only at the next frame start
5970          * event which is after the vblank start event, so we need to have a
5971          * wait-for-vblank between disabling the plane and the pipe.
5972          */
5973         if (HAS_GMCH(dev_priv) &&
5974             intel_set_memory_cxsr(dev_priv, false))
5975                 intel_wait_for_vblank(dev_priv, pipe);
5976 }
5977
5978 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5979                                        const struct intel_crtc_state *new_crtc_state)
5980 {
5981         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5982         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5983
5984         if (!old_crtc_state->ips_enabled)
5985                 return false;
5986
5987         if (needs_modeset(new_crtc_state))
5988                 return true;
5989
5990         /*
5991          * Workaround : Do not read or write the pipe palette/gamma data while
5992          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5993          *
5994          * Disable IPS before we program the LUT.
5995          */
5996         if (IS_HASWELL(dev_priv) &&
5997             (new_crtc_state->uapi.color_mgmt_changed ||
5998              new_crtc_state->update_pipe) &&
5999             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6000                 return true;
6001
6002         return !new_crtc_state->ips_enabled;
6003 }
6004
6005 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6006                                        const struct intel_crtc_state *new_crtc_state)
6007 {
6008         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6009         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6010
6011         if (!new_crtc_state->ips_enabled)
6012                 return false;
6013
6014         if (needs_modeset(new_crtc_state))
6015                 return true;
6016
6017         /*
6018          * Workaround : Do not read or write the pipe palette/gamma data while
6019          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6020          *
6021          * Re-enable IPS after the LUT has been programmed.
6022          */
6023         if (IS_HASWELL(dev_priv) &&
6024             (new_crtc_state->uapi.color_mgmt_changed ||
6025              new_crtc_state->update_pipe) &&
6026             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6027                 return true;
6028
6029         /*
6030          * We can't read out IPS on broadwell, assume the worst and
6031          * forcibly enable IPS on the first fastset.
6032          */
6033         if (new_crtc_state->update_pipe &&
6034             old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
6035                 return true;
6036
6037         return !old_crtc_state->ips_enabled;
6038 }
6039
6040 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
6041                           const struct intel_crtc_state *crtc_state)
6042 {
6043         if (!crtc_state->nv12_planes)
6044                 return false;
6045
6046         /* WA Display #0827: Gen9:all */
6047         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6048                 return true;
6049
6050         return false;
6051 }
6052
6053 static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
6054                                const struct intel_crtc_state *crtc_state)
6055 {
6056         /* Wa_2006604312:icl */
6057         if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
6058                 return true;
6059
6060         return false;
6061 }
6062
6063 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
6064 {
6065         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6066         struct drm_device *dev = crtc->base.dev;
6067         struct drm_i915_private *dev_priv = to_i915(dev);
6068         struct drm_atomic_state *state = old_crtc_state->uapi.state;
6069         struct intel_crtc_state *pipe_config =
6070                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
6071                                                 crtc);
6072         struct drm_plane *primary = crtc->base.primary;
6073         struct drm_plane_state *old_primary_state =
6074                 drm_atomic_get_old_plane_state(state, primary);
6075
6076         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
6077
6078         if (pipe_config->update_wm_post && pipe_config->hw.active)
6079                 intel_update_watermarks(crtc);
6080
6081         if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
6082                 hsw_enable_ips(pipe_config);
6083
6084         if (old_primary_state) {
6085                 struct drm_plane_state *new_primary_state =
6086                         drm_atomic_get_new_plane_state(state, primary);
6087
6088                 intel_fbc_post_update(crtc);
6089
6090                 if (new_primary_state->visible &&
6091                     (needs_modeset(pipe_config) ||
6092                      !old_primary_state->visible))
6093                         intel_post_enable_primary(&crtc->base, pipe_config);
6094         }
6095
6096         if (needs_nv12_wa(dev_priv, old_crtc_state) &&
6097             !needs_nv12_wa(dev_priv, pipe_config))
6098                 skl_wa_827(dev_priv, crtc->pipe, false);
6099
6100         if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
6101             !needs_scalerclk_wa(dev_priv, pipe_config))
6102                 icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
6103 }
6104
6105 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
6106                                    struct intel_crtc_state *pipe_config)
6107 {
6108         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6109         struct drm_device *dev = crtc->base.dev;
6110         struct drm_i915_private *dev_priv = to_i915(dev);
6111         struct drm_atomic_state *state = old_crtc_state->uapi.state;
6112         struct drm_plane *primary = crtc->base.primary;
6113         struct drm_plane_state *old_primary_state =
6114                 drm_atomic_get_old_plane_state(state, primary);
6115         bool modeset = needs_modeset(pipe_config);
6116         struct intel_atomic_state *intel_state =
6117                 to_intel_atomic_state(state);
6118
6119         if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
6120                 hsw_disable_ips(old_crtc_state);
6121
6122         if (old_primary_state) {
6123                 struct intel_plane_state *new_primary_state =
6124                         intel_atomic_get_new_plane_state(intel_state,
6125                                                          to_intel_plane(primary));
6126
6127                 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
6128                 /*
6129                  * Gen2 reports pipe underruns whenever all planes are disabled.
6130                  * So disable underrun reporting before all the planes get disabled.
6131                  */
6132                 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
6133                     (modeset || !new_primary_state->uapi.visible))
6134                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
6135         }
6136
6137         /* Display WA 827 */
6138         if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
6139             needs_nv12_wa(dev_priv, pipe_config))
6140                 skl_wa_827(dev_priv, crtc->pipe, true);
6141
6142         /* Wa_2006604312:icl */
6143         if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
6144             needs_scalerclk_wa(dev_priv, pipe_config))
6145                 icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
6146
6147         /*
6148          * Vblank time updates from the shadow to live plane control register
6149          * are blocked if the memory self-refresh mode is active at that
6150          * moment. So to make sure the plane gets truly disabled, disable
6151          * first the self-refresh mode. The self-refresh enable bit in turn
6152          * will be checked/applied by the HW only at the next frame start
6153          * event which is after the vblank start event, so we need to have a
6154          * wait-for-vblank between disabling the plane and the pipe.
6155          */
6156         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6157             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6158                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6159
6160         /*
6161          * IVB workaround: must disable low power watermarks for at least
6162          * one frame before enabling scaling.  LP watermarks can be re-enabled
6163          * when scaling is disabled.
6164          *
6165          * WaCxSRDisabledForSpriteScaling:ivb
6166          */
6167         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
6168             old_crtc_state->hw.active)
6169                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6170
6171         /*
6172          * If we're doing a modeset, we're done.  No need to do any pre-vblank
6173          * watermark programming here.
6174          */
6175         if (needs_modeset(pipe_config))
6176                 return;
6177
6178         /*
6179          * For platforms that support atomic watermarks, program the
6180          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6181          * will be the intermediate values that are safe for both pre- and
6182          * post- vblank; when vblank happens, the 'active' values will be set
6183          * to the final 'target' values and we'll do this again to get the
6184          * optimal watermarks.  For gen9+ platforms, the values we program here
6185          * will be the final target values which will get automatically latched
6186          * at vblank time; no further programming will be necessary.
6187          *
6188          * If a platform hasn't been transitioned to atomic watermarks yet,
6189          * we'll continue to update watermarks the old way, if flags tell
6190          * us to.
6191          */
6192         if (dev_priv->display.initial_watermarks)
6193                 dev_priv->display.initial_watermarks(intel_state, crtc);
6194         else if (pipe_config->update_wm_pre)
6195                 intel_update_watermarks(crtc);
6196 }
6197
6198 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6199                                       struct intel_crtc *crtc)
6200 {
6201         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6202         const struct intel_crtc_state *new_crtc_state =
6203                 intel_atomic_get_new_crtc_state(state, crtc);
6204         unsigned int update_mask = new_crtc_state->update_planes;
6205         const struct intel_plane_state *old_plane_state;
6206         struct intel_plane *plane;
6207         unsigned fb_bits = 0;
6208         int i;
6209
6210         intel_crtc_dpms_overlay_disable(crtc);
6211
6212         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6213                 if (crtc->pipe != plane->pipe ||
6214                     !(update_mask & BIT(plane->id)))
6215                         continue;
6216
6217                 intel_disable_plane(plane, new_crtc_state);
6218
6219                 if (old_plane_state->uapi.visible)
6220                         fb_bits |= plane->frontbuffer_bit;
6221         }
6222
6223         intel_frontbuffer_flip(dev_priv, fb_bits);
6224 }
6225
6226 /*
6227  * intel_connector_primary_encoder - get the primary encoder for a connector
6228  * @connector: connector for which to return the encoder
6229  *
6230  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6231  * all connectors to their encoder, except for DP-MST connectors which have
6232  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6233  * pointed to by as many DP-MST connectors as there are pipes.
6234  */
6235 static struct intel_encoder *
6236 intel_connector_primary_encoder(struct intel_connector *connector)
6237 {
6238         struct intel_encoder *encoder;
6239
6240         if (connector->mst_port)
6241                 return &dp_to_dig_port(connector->mst_port)->base;
6242
6243         encoder = intel_attached_encoder(&connector->base);
6244         WARN_ON(!encoder);
6245
6246         return encoder;
6247 }
6248
6249 static bool
6250 intel_connector_needs_modeset(struct intel_atomic_state *state,
6251                               const struct drm_connector_state *old_conn_state,
6252                               const struct drm_connector_state *new_conn_state)
6253 {
6254         struct intel_crtc *old_crtc = old_conn_state->crtc ?
6255                                       to_intel_crtc(old_conn_state->crtc) : NULL;
6256         struct intel_crtc *new_crtc = new_conn_state->crtc ?
6257                                       to_intel_crtc(new_conn_state->crtc) : NULL;
6258
6259         return new_crtc != old_crtc ||
6260                (new_crtc &&
6261                 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6262 }
6263
6264 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6265 {
6266         struct drm_connector_state *old_conn_state;
6267         struct drm_connector_state *new_conn_state;
6268         struct drm_connector *conn;
6269         int i;
6270
6271         for_each_oldnew_connector_in_state(&state->base, conn,
6272                                            old_conn_state, new_conn_state, i) {
6273                 struct intel_encoder *encoder;
6274                 struct intel_crtc *crtc;
6275
6276                 if (!intel_connector_needs_modeset(state,
6277                                                    old_conn_state,
6278                                                    new_conn_state))
6279                         continue;
6280
6281                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6282                 if (!encoder->update_prepare)
6283                         continue;
6284
6285                 crtc = new_conn_state->crtc ?
6286                         to_intel_crtc(new_conn_state->crtc) : NULL;
6287                 encoder->update_prepare(state, encoder, crtc);
6288         }
6289 }
6290
6291 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6292 {
6293         struct drm_connector_state *old_conn_state;
6294         struct drm_connector_state *new_conn_state;
6295         struct drm_connector *conn;
6296         int i;
6297
6298         for_each_oldnew_connector_in_state(&state->base, conn,
6299                                            old_conn_state, new_conn_state, i) {
6300                 struct intel_encoder *encoder;
6301                 struct intel_crtc *crtc;
6302
6303                 if (!intel_connector_needs_modeset(state,
6304                                                    old_conn_state,
6305                                                    new_conn_state))
6306                         continue;
6307
6308                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6309                 if (!encoder->update_complete)
6310                         continue;
6311
6312                 crtc = new_conn_state->crtc ?
6313                         to_intel_crtc(new_conn_state->crtc) : NULL;
6314                 encoder->update_complete(state, encoder, crtc);
6315         }
6316 }
6317
6318 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6319                                           struct intel_crtc *crtc)
6320 {
6321         const struct intel_crtc_state *crtc_state =
6322                 intel_atomic_get_new_crtc_state(state, crtc);
6323         const struct drm_connector_state *conn_state;
6324         struct drm_connector *conn;
6325         int i;
6326
6327         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6328                 struct intel_encoder *encoder =
6329                         to_intel_encoder(conn_state->best_encoder);
6330
6331                 if (conn_state->crtc != &crtc->base)
6332                         continue;
6333
6334                 if (encoder->pre_pll_enable)
6335                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6336         }
6337 }
6338
6339 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6340                                       struct intel_crtc *crtc)
6341 {
6342         const struct intel_crtc_state *crtc_state =
6343                 intel_atomic_get_new_crtc_state(state, crtc);
6344         const struct drm_connector_state *conn_state;
6345         struct drm_connector *conn;
6346         int i;
6347
6348         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6349                 struct intel_encoder *encoder =
6350                         to_intel_encoder(conn_state->best_encoder);
6351
6352                 if (conn_state->crtc != &crtc->base)
6353                         continue;
6354
6355                 if (encoder->pre_enable)
6356                         encoder->pre_enable(encoder, crtc_state, conn_state);
6357         }
6358 }
6359
6360 static void intel_encoders_enable(struct intel_atomic_state *state,
6361                                   struct intel_crtc *crtc)
6362 {
6363         const struct intel_crtc_state *crtc_state =
6364                 intel_atomic_get_new_crtc_state(state, crtc);
6365         const struct drm_connector_state *conn_state;
6366         struct drm_connector *conn;
6367         int i;
6368
6369         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6370                 struct intel_encoder *encoder =
6371                         to_intel_encoder(conn_state->best_encoder);
6372
6373                 if (conn_state->crtc != &crtc->base)
6374                         continue;
6375
6376                 if (encoder->enable)
6377                         encoder->enable(encoder, crtc_state, conn_state);
6378                 intel_opregion_notify_encoder(encoder, true);
6379         }
6380 }
6381
6382 static void intel_encoders_disable(struct intel_atomic_state *state,
6383                                    struct intel_crtc *crtc)
6384 {
6385         const struct intel_crtc_state *old_crtc_state =
6386                 intel_atomic_get_old_crtc_state(state, crtc);
6387         const struct drm_connector_state *old_conn_state;
6388         struct drm_connector *conn;
6389         int i;
6390
6391         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6392                 struct intel_encoder *encoder =
6393                         to_intel_encoder(old_conn_state->best_encoder);
6394
6395                 if (old_conn_state->crtc != &crtc->base)
6396                         continue;
6397
6398                 intel_opregion_notify_encoder(encoder, false);
6399                 if (encoder->disable)
6400                         encoder->disable(encoder, old_crtc_state, old_conn_state);
6401         }
6402 }
6403
6404 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6405                                         struct intel_crtc *crtc)
6406 {
6407         const struct intel_crtc_state *old_crtc_state =
6408                 intel_atomic_get_old_crtc_state(state, crtc);
6409         const struct drm_connector_state *old_conn_state;
6410         struct drm_connector *conn;
6411         int i;
6412
6413         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6414                 struct intel_encoder *encoder =
6415                         to_intel_encoder(old_conn_state->best_encoder);
6416
6417                 if (old_conn_state->crtc != &crtc->base)
6418                         continue;
6419
6420                 if (encoder->post_disable)
6421                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6422         }
6423 }
6424
6425 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6426                                             struct intel_crtc *crtc)
6427 {
6428         const struct intel_crtc_state *old_crtc_state =
6429                 intel_atomic_get_old_crtc_state(state, crtc);
6430         const struct drm_connector_state *old_conn_state;
6431         struct drm_connector *conn;
6432         int i;
6433
6434         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6435                 struct intel_encoder *encoder =
6436                         to_intel_encoder(old_conn_state->best_encoder);
6437
6438                 if (old_conn_state->crtc != &crtc->base)
6439                         continue;
6440
6441                 if (encoder->post_pll_disable)
6442                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6443         }
6444 }
6445
6446 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6447                                        struct intel_crtc *crtc)
6448 {
6449         const struct intel_crtc_state *crtc_state =
6450                 intel_atomic_get_new_crtc_state(state, crtc);
6451         const struct drm_connector_state *conn_state;
6452         struct drm_connector *conn;
6453         int i;
6454
6455         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6456                 struct intel_encoder *encoder =
6457                         to_intel_encoder(conn_state->best_encoder);
6458
6459                 if (conn_state->crtc != &crtc->base)
6460                         continue;
6461
6462                 if (encoder->update_pipe)
6463                         encoder->update_pipe(encoder, crtc_state, conn_state);
6464         }
6465 }
6466
6467 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6468 {
6469         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6470         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6471
6472         plane->disable_plane(plane, crtc_state);
6473 }
6474
6475 static void ironlake_crtc_enable(struct intel_atomic_state *state,
6476                                  struct intel_crtc *crtc)
6477 {
6478         const struct intel_crtc_state *new_crtc_state =
6479                 intel_atomic_get_new_crtc_state(state, crtc);
6480         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6481         enum pipe pipe = crtc->pipe;
6482
6483         if (WARN_ON(crtc->active))
6484                 return;
6485
6486         /*
6487          * Sometimes spurious CPU pipe underruns happen during FDI
6488          * training, at least with VGA+HDMI cloning. Suppress them.
6489          *
6490          * On ILK we get an occasional spurious CPU pipe underruns
6491          * between eDP port A enable and vdd enable. Also PCH port
6492          * enable seems to result in the occasional CPU pipe underrun.
6493          *
6494          * Spurious PCH underruns also occur during PCH enabling.
6495          */
6496         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6497         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6498
6499         if (new_crtc_state->has_pch_encoder)
6500                 intel_prepare_shared_dpll(new_crtc_state);
6501
6502         if (intel_crtc_has_dp_encoder(new_crtc_state))
6503                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6504
6505         intel_set_pipe_timings(new_crtc_state);
6506         intel_set_pipe_src_size(new_crtc_state);
6507
6508         if (new_crtc_state->has_pch_encoder)
6509                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6510                                              &new_crtc_state->fdi_m_n, NULL);
6511
6512         ironlake_set_pipeconf(new_crtc_state);
6513
6514         crtc->active = true;
6515
6516         intel_encoders_pre_enable(state, crtc);
6517
6518         if (new_crtc_state->has_pch_encoder) {
6519                 /* Note: FDI PLL enabling _must_ be done before we enable the
6520                  * cpu pipes, hence this is separate from all the other fdi/pch
6521                  * enabling. */
6522                 ironlake_fdi_pll_enable(new_crtc_state);
6523         } else {
6524                 assert_fdi_tx_disabled(dev_priv, pipe);
6525                 assert_fdi_rx_disabled(dev_priv, pipe);
6526         }
6527
6528         ironlake_pfit_enable(new_crtc_state);
6529
6530         /*
6531          * On ILK+ LUT must be loaded before the pipe is running but with
6532          * clocks enabled
6533          */
6534         intel_color_load_luts(new_crtc_state);
6535         intel_color_commit(new_crtc_state);
6536         /* update DSPCNTR to configure gamma for pipe bottom color */
6537         intel_disable_primary_plane(new_crtc_state);
6538
6539         if (dev_priv->display.initial_watermarks)
6540                 dev_priv->display.initial_watermarks(state, crtc);
6541         intel_enable_pipe(new_crtc_state);
6542
6543         if (new_crtc_state->has_pch_encoder)
6544                 ironlake_pch_enable(state, new_crtc_state);
6545
6546         intel_crtc_vblank_on(new_crtc_state);
6547
6548         intel_encoders_enable(state, crtc);
6549
6550         if (HAS_PCH_CPT(dev_priv))
6551                 cpt_verify_modeset(dev_priv, pipe);
6552
6553         /*
6554          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6555          * And a second vblank wait is needed at least on ILK with
6556          * some interlaced HDMI modes. Let's do the double wait always
6557          * in case there are more corner cases we don't know about.
6558          */
6559         if (new_crtc_state->has_pch_encoder) {
6560                 intel_wait_for_vblank(dev_priv, pipe);
6561                 intel_wait_for_vblank(dev_priv, pipe);
6562         }
6563         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6564         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6565 }
6566
6567 /* IPS only exists on ULT machines and is tied to pipe A. */
6568 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6569 {
6570         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6571 }
6572
6573 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6574                                             enum pipe pipe, bool apply)
6575 {
6576         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6577         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6578
6579         if (apply)
6580                 val |= mask;
6581         else
6582                 val &= ~mask;
6583
6584         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6585 }
6586
6587 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6588 {
6589         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6590         enum pipe pipe = crtc->pipe;
6591         u32 val;
6592
6593         val = MBUS_DBOX_A_CREDIT(2);
6594
6595         if (INTEL_GEN(dev_priv) >= 12) {
6596                 val |= MBUS_DBOX_BW_CREDIT(2);
6597                 val |= MBUS_DBOX_B_CREDIT(12);
6598         } else {
6599                 val |= MBUS_DBOX_BW_CREDIT(1);
6600                 val |= MBUS_DBOX_B_CREDIT(8);
6601         }
6602
6603         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6604 }
6605
6606 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
6607 {
6608         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6610         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
6611         u32 val;
6612
6613         val = I915_READ(reg);
6614         val &= ~HSW_FRAME_START_DELAY_MASK;
6615         val |= HSW_FRAME_START_DELAY(0);
6616         I915_WRITE(reg, val);
6617 }
6618
6619 static void haswell_crtc_enable(struct intel_atomic_state *state,
6620                                 struct intel_crtc *crtc)
6621 {
6622         const struct intel_crtc_state *new_crtc_state =
6623                 intel_atomic_get_new_crtc_state(state, crtc);
6624         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6625         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
6626         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
6627         bool psl_clkgate_wa;
6628
6629         if (WARN_ON(crtc->active))
6630                 return;
6631
6632         intel_encoders_pre_pll_enable(state, crtc);
6633
6634         if (new_crtc_state->shared_dpll)
6635                 intel_enable_shared_dpll(new_crtc_state);
6636
6637         intel_encoders_pre_enable(state, crtc);
6638
6639         if (intel_crtc_has_dp_encoder(new_crtc_state))
6640                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6641
6642         if (!transcoder_is_dsi(cpu_transcoder))
6643                 intel_set_pipe_timings(new_crtc_state);
6644
6645         if (INTEL_GEN(dev_priv) >= 11)
6646                 icl_enable_trans_port_sync(new_crtc_state);
6647
6648         intel_set_pipe_src_size(new_crtc_state);
6649
6650         if (cpu_transcoder != TRANSCODER_EDP &&
6651             !transcoder_is_dsi(cpu_transcoder))
6652                 I915_WRITE(PIPE_MULT(cpu_transcoder),
6653                            new_crtc_state->pixel_multiplier - 1);
6654
6655         if (new_crtc_state->has_pch_encoder)
6656                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6657                                              &new_crtc_state->fdi_m_n, NULL);
6658
6659         if (!transcoder_is_dsi(cpu_transcoder)) {
6660                 hsw_set_frame_start_delay(new_crtc_state);
6661                 haswell_set_pipeconf(new_crtc_state);
6662         }
6663
6664         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6665                 bdw_set_pipemisc(new_crtc_state);
6666
6667         crtc->active = true;
6668
6669         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6670         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6671                 new_crtc_state->pch_pfit.enabled;
6672         if (psl_clkgate_wa)
6673                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6674
6675         if (INTEL_GEN(dev_priv) >= 9)
6676                 skylake_pfit_enable(new_crtc_state);
6677         else
6678                 ironlake_pfit_enable(new_crtc_state);
6679
6680         /*
6681          * On ILK+ LUT must be loaded before the pipe is running but with
6682          * clocks enabled
6683          */
6684         intel_color_load_luts(new_crtc_state);
6685         intel_color_commit(new_crtc_state);
6686         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6687         if (INTEL_GEN(dev_priv) < 9)
6688                 intel_disable_primary_plane(new_crtc_state);
6689
6690         if (INTEL_GEN(dev_priv) >= 11)
6691                 icl_set_pipe_chicken(crtc);
6692
6693         if (!transcoder_is_dsi(cpu_transcoder))
6694                 intel_ddi_enable_transcoder_func(new_crtc_state);
6695
6696         if (dev_priv->display.initial_watermarks)
6697                 dev_priv->display.initial_watermarks(state, crtc);
6698
6699         if (INTEL_GEN(dev_priv) >= 11)
6700                 icl_pipe_mbus_enable(crtc);
6701
6702         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6703         if (!transcoder_is_dsi(cpu_transcoder))
6704                 intel_enable_pipe(new_crtc_state);
6705
6706         if (new_crtc_state->has_pch_encoder)
6707                 lpt_pch_enable(state, new_crtc_state);
6708
6709         intel_crtc_vblank_on(new_crtc_state);
6710
6711         intel_encoders_enable(state, crtc);
6712
6713         if (psl_clkgate_wa) {
6714                 intel_wait_for_vblank(dev_priv, pipe);
6715                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6716         }
6717
6718         /* If we change the relative order between pipe/planes enabling, we need
6719          * to change the workaround. */
6720         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
6721         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6722                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6723                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6724         }
6725 }
6726
6727 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6728 {
6729         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6730         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6731         enum pipe pipe = crtc->pipe;
6732
6733         /* To avoid upsetting the power well on haswell only disable the pfit if
6734          * it's in use. The hw state code will make sure we get this right. */
6735         if (old_crtc_state->pch_pfit.enabled) {
6736                 I915_WRITE(PF_CTL(pipe), 0);
6737                 I915_WRITE(PF_WIN_POS(pipe), 0);
6738                 I915_WRITE(PF_WIN_SZ(pipe), 0);
6739         }
6740 }
6741
6742 static void ironlake_crtc_disable(struct intel_atomic_state *state,
6743                                   struct intel_crtc *crtc)
6744 {
6745         const struct intel_crtc_state *old_crtc_state =
6746                 intel_atomic_get_old_crtc_state(state, crtc);
6747         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6748         enum pipe pipe = crtc->pipe;
6749
6750         /*
6751          * Sometimes spurious CPU pipe underruns happen when the
6752          * pipe is already disabled, but FDI RX/TX is still enabled.
6753          * Happens at least with VGA+HDMI cloning. Suppress them.
6754          */
6755         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6756         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6757
6758         intel_encoders_disable(state, crtc);
6759
6760         intel_crtc_vblank_off(crtc);
6761
6762         intel_disable_pipe(old_crtc_state);
6763
6764         ironlake_pfit_disable(old_crtc_state);
6765
6766         if (old_crtc_state->has_pch_encoder)
6767                 ironlake_fdi_disable(crtc);
6768
6769         intel_encoders_post_disable(state, crtc);
6770
6771         if (old_crtc_state->has_pch_encoder) {
6772                 ironlake_disable_pch_transcoder(dev_priv, pipe);
6773
6774                 if (HAS_PCH_CPT(dev_priv)) {
6775                         i915_reg_t reg;
6776                         u32 temp;
6777
6778                         /* disable TRANS_DP_CTL */
6779                         reg = TRANS_DP_CTL(pipe);
6780                         temp = I915_READ(reg);
6781                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6782                                   TRANS_DP_PORT_SEL_MASK);
6783                         temp |= TRANS_DP_PORT_SEL_NONE;
6784                         I915_WRITE(reg, temp);
6785
6786                         /* disable DPLL_SEL */
6787                         temp = I915_READ(PCH_DPLL_SEL);
6788                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6789                         I915_WRITE(PCH_DPLL_SEL, temp);
6790                 }
6791
6792                 ironlake_fdi_pll_disable(crtc);
6793         }
6794
6795         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6796         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6797 }
6798
6799 static void haswell_crtc_disable(struct intel_atomic_state *state,
6800                                  struct intel_crtc *crtc)
6801 {
6802         const struct intel_crtc_state *old_crtc_state =
6803                 intel_atomic_get_old_crtc_state(state, crtc);
6804         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6805         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6806
6807         intel_encoders_disable(state, crtc);
6808
6809         intel_crtc_vblank_off(crtc);
6810
6811         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6812         if (!transcoder_is_dsi(cpu_transcoder))
6813                 intel_disable_pipe(old_crtc_state);
6814
6815         if (INTEL_GEN(dev_priv) >= 11)
6816                 icl_disable_transcoder_port_sync(old_crtc_state);
6817
6818         if (!transcoder_is_dsi(cpu_transcoder))
6819                 intel_ddi_disable_transcoder_func(old_crtc_state);
6820
6821         intel_dsc_disable(old_crtc_state);
6822
6823         if (INTEL_GEN(dev_priv) >= 9)
6824                 skylake_scaler_disable(crtc);
6825         else
6826                 ironlake_pfit_disable(old_crtc_state);
6827
6828         intel_encoders_post_disable(state, crtc);
6829
6830         intel_encoders_post_pll_disable(state, crtc);
6831 }
6832
6833 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6834 {
6835         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6836         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6837
6838         if (!crtc_state->gmch_pfit.control)
6839                 return;
6840
6841         /*
6842          * The panel fitter should only be adjusted whilst the pipe is disabled,
6843          * according to register description and PRM.
6844          */
6845         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6846         assert_pipe_disabled(dev_priv, crtc->pipe);
6847
6848         I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6849         I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6850
6851         /* Border color in case we don't scale up to the full screen. Black by
6852          * default, change to something else for debugging. */
6853         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6854 }
6855
6856 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6857 {
6858         if (phy == PHY_NONE)
6859                 return false;
6860
6861         if (IS_ELKHARTLAKE(dev_priv))
6862                 return phy <= PHY_C;
6863
6864         if (INTEL_GEN(dev_priv) >= 11)
6865                 return phy <= PHY_B;
6866
6867         return false;
6868 }
6869
6870 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6871 {
6872         if (INTEL_GEN(dev_priv) >= 12)
6873                 return phy >= PHY_D && phy <= PHY_I;
6874
6875         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6876                 return phy >= PHY_C && phy <= PHY_F;
6877
6878         return false;
6879 }
6880
6881 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6882 {
6883         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6884                 return PHY_A;
6885
6886         return (enum phy)port;
6887 }
6888
6889 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6890 {
6891         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6892                 return PORT_TC_NONE;
6893
6894         if (INTEL_GEN(dev_priv) >= 12)
6895                 return port - PORT_D;
6896
6897         return port - PORT_C;
6898 }
6899
6900 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6901 {
6902         switch (port) {
6903         case PORT_A:
6904                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6905         case PORT_B:
6906                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6907         case PORT_C:
6908                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6909         case PORT_D:
6910                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6911         case PORT_E:
6912                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6913         case PORT_F:
6914                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6915         case PORT_G:
6916                 return POWER_DOMAIN_PORT_DDI_G_LANES;
6917         default:
6918                 MISSING_CASE(port);
6919                 return POWER_DOMAIN_PORT_OTHER;
6920         }
6921 }
6922
6923 enum intel_display_power_domain
6924 intel_aux_power_domain(struct intel_digital_port *dig_port)
6925 {
6926         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6927         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6928
6929         if (intel_phy_is_tc(dev_priv, phy) &&
6930             dig_port->tc_mode == TC_PORT_TBT_ALT) {
6931                 switch (dig_port->aux_ch) {
6932                 case AUX_CH_C:
6933                         return POWER_DOMAIN_AUX_C_TBT;
6934                 case AUX_CH_D:
6935                         return POWER_DOMAIN_AUX_D_TBT;
6936                 case AUX_CH_E:
6937                         return POWER_DOMAIN_AUX_E_TBT;
6938                 case AUX_CH_F:
6939                         return POWER_DOMAIN_AUX_F_TBT;
6940                 case AUX_CH_G:
6941                         return POWER_DOMAIN_AUX_G_TBT;
6942                 default:
6943                         MISSING_CASE(dig_port->aux_ch);
6944                         return POWER_DOMAIN_AUX_C_TBT;
6945                 }
6946         }
6947
6948         switch (dig_port->aux_ch) {
6949         case AUX_CH_A:
6950                 return POWER_DOMAIN_AUX_A;
6951         case AUX_CH_B:
6952                 return POWER_DOMAIN_AUX_B;
6953         case AUX_CH_C:
6954                 return POWER_DOMAIN_AUX_C;
6955         case AUX_CH_D:
6956                 return POWER_DOMAIN_AUX_D;
6957         case AUX_CH_E:
6958                 return POWER_DOMAIN_AUX_E;
6959         case AUX_CH_F:
6960                 return POWER_DOMAIN_AUX_F;
6961         case AUX_CH_G:
6962                 return POWER_DOMAIN_AUX_G;
6963         default:
6964                 MISSING_CASE(dig_port->aux_ch);
6965                 return POWER_DOMAIN_AUX_A;
6966         }
6967 }
6968
6969 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6970 {
6971         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6972         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6973         struct drm_encoder *encoder;
6974         enum pipe pipe = crtc->pipe;
6975         u64 mask;
6976         enum transcoder transcoder = crtc_state->cpu_transcoder;
6977
6978         if (!crtc_state->hw.active)
6979                 return 0;
6980
6981         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6982         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6983         if (crtc_state->pch_pfit.enabled ||
6984             crtc_state->pch_pfit.force_thru)
6985                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6986
6987         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6988                                   crtc_state->uapi.encoder_mask) {
6989                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6990
6991                 mask |= BIT_ULL(intel_encoder->power_domain);
6992         }
6993
6994         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6995                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6996
6997         if (crtc_state->shared_dpll)
6998                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6999
7000         return mask;
7001 }
7002
7003 static u64
7004 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7005 {
7006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7007         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7008         enum intel_display_power_domain domain;
7009         u64 domains, new_domains, old_domains;
7010
7011         old_domains = crtc->enabled_power_domains;
7012         crtc->enabled_power_domains = new_domains =
7013                 get_crtc_power_domains(crtc_state);
7014
7015         domains = new_domains & ~old_domains;
7016
7017         for_each_power_domain(domain, domains)
7018                 intel_display_power_get(dev_priv, domain);
7019
7020         return old_domains & ~new_domains;
7021 }
7022
7023 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7024                                       u64 domains)
7025 {
7026         enum intel_display_power_domain domain;
7027
7028         for_each_power_domain(domain, domains)
7029                 intel_display_power_put_unchecked(dev_priv, domain);
7030 }
7031
7032 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7033                                    struct intel_crtc *crtc)
7034 {
7035         const struct intel_crtc_state *new_crtc_state =
7036                 intel_atomic_get_new_crtc_state(state, crtc);
7037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7038         enum pipe pipe = crtc->pipe;
7039
7040         if (WARN_ON(crtc->active))
7041                 return;
7042
7043         if (intel_crtc_has_dp_encoder(new_crtc_state))
7044                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7045
7046         intel_set_pipe_timings(new_crtc_state);
7047         intel_set_pipe_src_size(new_crtc_state);
7048
7049         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7050                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7051                 I915_WRITE(CHV_CANVAS(pipe), 0);
7052         }
7053
7054         i9xx_set_pipeconf(new_crtc_state);
7055
7056         crtc->active = true;
7057
7058         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7059
7060         intel_encoders_pre_pll_enable(state, crtc);
7061
7062         if (IS_CHERRYVIEW(dev_priv)) {
7063                 chv_prepare_pll(crtc, new_crtc_state);
7064                 chv_enable_pll(crtc, new_crtc_state);
7065         } else {
7066                 vlv_prepare_pll(crtc, new_crtc_state);
7067                 vlv_enable_pll(crtc, new_crtc_state);
7068         }
7069
7070         intel_encoders_pre_enable(state, crtc);
7071
7072         i9xx_pfit_enable(new_crtc_state);
7073
7074         intel_color_load_luts(new_crtc_state);
7075         intel_color_commit(new_crtc_state);
7076         /* update DSPCNTR to configure gamma for pipe bottom color */
7077         intel_disable_primary_plane(new_crtc_state);
7078
7079         dev_priv->display.initial_watermarks(state, crtc);
7080         intel_enable_pipe(new_crtc_state);
7081
7082         intel_crtc_vblank_on(new_crtc_state);
7083
7084         intel_encoders_enable(state, crtc);
7085 }
7086
7087 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7088 {
7089         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7090         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7091
7092         I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
7093         I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
7094 }
7095
7096 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7097                              struct intel_crtc *crtc)
7098 {
7099         const struct intel_crtc_state *new_crtc_state =
7100                 intel_atomic_get_new_crtc_state(state, crtc);
7101         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7102         enum pipe pipe = crtc->pipe;
7103
7104         if (WARN_ON(crtc->active))
7105                 return;
7106
7107         i9xx_set_pll_dividers(new_crtc_state);
7108
7109         if (intel_crtc_has_dp_encoder(new_crtc_state))
7110                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7111
7112         intel_set_pipe_timings(new_crtc_state);
7113         intel_set_pipe_src_size(new_crtc_state);
7114
7115         i9xx_set_pipeconf(new_crtc_state);
7116
7117         crtc->active = true;
7118
7119         if (!IS_GEN(dev_priv, 2))
7120                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7121
7122         intel_encoders_pre_enable(state, crtc);
7123
7124         i9xx_enable_pll(crtc, new_crtc_state);
7125
7126         i9xx_pfit_enable(new_crtc_state);
7127
7128         intel_color_load_luts(new_crtc_state);
7129         intel_color_commit(new_crtc_state);
7130         /* update DSPCNTR to configure gamma for pipe bottom color */
7131         intel_disable_primary_plane(new_crtc_state);
7132
7133         if (dev_priv->display.initial_watermarks)
7134                 dev_priv->display.initial_watermarks(state, crtc);
7135         else
7136                 intel_update_watermarks(crtc);
7137         intel_enable_pipe(new_crtc_state);
7138
7139         intel_crtc_vblank_on(new_crtc_state);
7140
7141         intel_encoders_enable(state, crtc);
7142 }
7143
7144 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7145 {
7146         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7147         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7148
7149         if (!old_crtc_state->gmch_pfit.control)
7150                 return;
7151
7152         assert_pipe_disabled(dev_priv, crtc->pipe);
7153
7154         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
7155                       I915_READ(PFIT_CONTROL));
7156         I915_WRITE(PFIT_CONTROL, 0);
7157 }
7158
7159 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7160                               struct intel_crtc *crtc)
7161 {
7162         struct intel_crtc_state *old_crtc_state =
7163                 intel_atomic_get_old_crtc_state(state, crtc);
7164         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7165         enum pipe pipe = crtc->pipe;
7166
7167         /*
7168          * On gen2 planes are double buffered but the pipe isn't, so we must
7169          * wait for planes to fully turn off before disabling the pipe.
7170          */
7171         if (IS_GEN(dev_priv, 2))
7172                 intel_wait_for_vblank(dev_priv, pipe);
7173
7174         intel_encoders_disable(state, crtc);
7175
7176         intel_crtc_vblank_off(crtc);
7177
7178         intel_disable_pipe(old_crtc_state);
7179
7180         i9xx_pfit_disable(old_crtc_state);
7181
7182         intel_encoders_post_disable(state, crtc);
7183
7184         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7185                 if (IS_CHERRYVIEW(dev_priv))
7186                         chv_disable_pll(dev_priv, pipe);
7187                 else if (IS_VALLEYVIEW(dev_priv))
7188                         vlv_disable_pll(dev_priv, pipe);
7189                 else
7190                         i9xx_disable_pll(old_crtc_state);
7191         }
7192
7193         intel_encoders_post_pll_disable(state, crtc);
7194
7195         if (!IS_GEN(dev_priv, 2))
7196                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7197
7198         if (!dev_priv->display.initial_watermarks)
7199                 intel_update_watermarks(crtc);
7200
7201         /* clock the pipe down to 640x480@60 to potentially save power */
7202         if (IS_I830(dev_priv))
7203                 i830_enable_pipe(dev_priv, pipe);
7204 }
7205
7206 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
7207                                         struct drm_modeset_acquire_ctx *ctx)
7208 {
7209         struct intel_encoder *encoder;
7210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7211         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7212         struct intel_bw_state *bw_state =
7213                 to_intel_bw_state(dev_priv->bw_obj.state);
7214         struct intel_crtc_state *crtc_state =
7215                 to_intel_crtc_state(crtc->state);
7216         enum intel_display_power_domain domain;
7217         struct intel_plane *plane;
7218         u64 domains;
7219         struct drm_atomic_state *state;
7220         struct intel_crtc_state *temp_crtc_state;
7221         int ret;
7222
7223         if (!intel_crtc->active)
7224                 return;
7225
7226         for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
7227                 const struct intel_plane_state *plane_state =
7228                         to_intel_plane_state(plane->base.state);
7229
7230                 if (plane_state->uapi.visible)
7231                         intel_plane_disable_noatomic(intel_crtc, plane);
7232         }
7233
7234         state = drm_atomic_state_alloc(crtc->dev);
7235         if (!state) {
7236                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7237                               crtc->base.id, crtc->name);
7238                 return;
7239         }
7240
7241         state->acquire_ctx = ctx;
7242
7243         /* Everything's already locked, -EDEADLK can't happen. */
7244         temp_crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
7245         ret = drm_atomic_add_affected_connectors(state, crtc);
7246
7247         WARN_ON(IS_ERR(temp_crtc_state) || ret);
7248
7249         dev_priv->display.crtc_disable(to_intel_atomic_state(state),
7250                                        intel_crtc);
7251
7252         drm_atomic_state_put(state);
7253
7254         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7255                       crtc->base.id, crtc->name);
7256
7257         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
7258         crtc->state->active = false;
7259         intel_crtc->active = false;
7260         crtc->enabled = false;
7261         crtc->state->connector_mask = 0;
7262         crtc->state->encoder_mask = 0;
7263         intel_crtc_free_hw_state(crtc_state);
7264         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7265
7266         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
7267                 encoder->base.crtc = NULL;
7268
7269         intel_fbc_disable(intel_crtc);
7270         intel_update_watermarks(intel_crtc);
7271         intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
7272
7273         domains = intel_crtc->enabled_power_domains;
7274         for_each_power_domain(domain, domains)
7275                 intel_display_power_put_unchecked(dev_priv, domain);
7276         intel_crtc->enabled_power_domains = 0;
7277
7278         dev_priv->active_pipes &= ~BIT(intel_crtc->pipe);
7279         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
7280         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
7281
7282         bw_state->data_rate[intel_crtc->pipe] = 0;
7283         bw_state->num_active_planes[intel_crtc->pipe] = 0;
7284 }
7285
7286 /*
7287  * turn all crtc's off, but do not adjust state
7288  * This has to be paired with a call to intel_modeset_setup_hw_state.
7289  */
7290 int intel_display_suspend(struct drm_device *dev)
7291 {
7292         struct drm_i915_private *dev_priv = to_i915(dev);
7293         struct drm_atomic_state *state;
7294         int ret;
7295
7296         state = drm_atomic_helper_suspend(dev);
7297         ret = PTR_ERR_OR_ZERO(state);
7298         if (ret)
7299                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7300         else
7301                 dev_priv->modeset_restore_state = state;
7302         return ret;
7303 }
7304
7305 void intel_encoder_destroy(struct drm_encoder *encoder)
7306 {
7307         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7308
7309         drm_encoder_cleanup(encoder);
7310         kfree(intel_encoder);
7311 }
7312
7313 /* Cross check the actual hw state with our own modeset state tracking (and it's
7314  * internal consistency). */
7315 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7316                                          struct drm_connector_state *conn_state)
7317 {
7318         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7319
7320         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7321                       connector->base.base.id,
7322                       connector->base.name);
7323
7324         if (connector->get_hw_state(connector)) {
7325                 struct intel_encoder *encoder = connector->encoder;
7326
7327                 I915_STATE_WARN(!crtc_state,
7328                          "connector enabled without attached crtc\n");
7329
7330                 if (!crtc_state)
7331                         return;
7332
7333                 I915_STATE_WARN(!crtc_state->hw.active,
7334                                 "connector is active, but attached crtc isn't\n");
7335
7336                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7337                         return;
7338
7339                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7340                         "atomic encoder doesn't match attached encoder\n");
7341
7342                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7343                         "attached encoder crtc differs from connector crtc\n");
7344         } else {
7345                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7346                                 "attached crtc is active, but connector isn't\n");
7347                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7348                         "best encoder set without crtc!\n");
7349         }
7350 }
7351
7352 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7353 {
7354         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7355                 return crtc_state->fdi_lanes;
7356
7357         return 0;
7358 }
7359
7360 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7361                                      struct intel_crtc_state *pipe_config)
7362 {
7363         struct drm_i915_private *dev_priv = to_i915(dev);
7364         struct drm_atomic_state *state = pipe_config->uapi.state;
7365         struct intel_crtc *other_crtc;
7366         struct intel_crtc_state *other_crtc_state;
7367
7368         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7369                       pipe_name(pipe), pipe_config->fdi_lanes);
7370         if (pipe_config->fdi_lanes > 4) {
7371                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7372                               pipe_name(pipe), pipe_config->fdi_lanes);
7373                 return -EINVAL;
7374         }
7375
7376         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7377                 if (pipe_config->fdi_lanes > 2) {
7378                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7379                                       pipe_config->fdi_lanes);
7380                         return -EINVAL;
7381                 } else {
7382                         return 0;
7383                 }
7384         }
7385
7386         if (INTEL_NUM_PIPES(dev_priv) == 2)
7387                 return 0;
7388
7389         /* Ivybridge 3 pipe is really complicated */
7390         switch (pipe) {
7391         case PIPE_A:
7392                 return 0;
7393         case PIPE_B:
7394                 if (pipe_config->fdi_lanes <= 2)
7395                         return 0;
7396
7397                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7398                 other_crtc_state =
7399                         intel_atomic_get_crtc_state(state, other_crtc);
7400                 if (IS_ERR(other_crtc_state))
7401                         return PTR_ERR(other_crtc_state);
7402
7403                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7404                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7405                                       pipe_name(pipe), pipe_config->fdi_lanes);
7406                         return -EINVAL;
7407                 }
7408                 return 0;
7409         case PIPE_C:
7410                 if (pipe_config->fdi_lanes > 2) {
7411                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7412                                       pipe_name(pipe), pipe_config->fdi_lanes);
7413                         return -EINVAL;
7414                 }
7415
7416                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7417                 other_crtc_state =
7418                         intel_atomic_get_crtc_state(state, other_crtc);
7419                 if (IS_ERR(other_crtc_state))
7420                         return PTR_ERR(other_crtc_state);
7421
7422                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7423                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7424                         return -EINVAL;
7425                 }
7426                 return 0;
7427         default:
7428                 BUG();
7429         }
7430 }
7431
7432 #define RETRY 1
7433 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7434                                        struct intel_crtc_state *pipe_config)
7435 {
7436         struct drm_device *dev = intel_crtc->base.dev;
7437         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7438         int lane, link_bw, fdi_dotclock, ret;
7439         bool needs_recompute = false;
7440
7441 retry:
7442         /* FDI is a binary signal running at ~2.7GHz, encoding
7443          * each output octet as 10 bits. The actual frequency
7444          * is stored as a divider into a 100MHz clock, and the
7445          * mode pixel clock is stored in units of 1KHz.
7446          * Hence the bw of each lane in terms of the mode signal
7447          * is:
7448          */
7449         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7450
7451         fdi_dotclock = adjusted_mode->crtc_clock;
7452
7453         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7454                                            pipe_config->pipe_bpp);
7455
7456         pipe_config->fdi_lanes = lane;
7457
7458         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7459                                link_bw, &pipe_config->fdi_m_n, false, false);
7460
7461         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7462         if (ret == -EDEADLK)
7463                 return ret;
7464
7465         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7466                 pipe_config->pipe_bpp -= 2*3;
7467                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7468                               pipe_config->pipe_bpp);
7469                 needs_recompute = true;
7470                 pipe_config->bw_constrained = true;
7471
7472                 goto retry;
7473         }
7474
7475         if (needs_recompute)
7476                 return RETRY;
7477
7478         return ret;
7479 }
7480
7481 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7482 {
7483         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7484         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7485
7486         /* IPS only exists on ULT machines and is tied to pipe A. */
7487         if (!hsw_crtc_supports_ips(crtc))
7488                 return false;
7489
7490         if (!i915_modparams.enable_ips)
7491                 return false;
7492
7493         if (crtc_state->pipe_bpp > 24)
7494                 return false;
7495
7496         /*
7497          * We compare against max which means we must take
7498          * the increased cdclk requirement into account when
7499          * calculating the new cdclk.
7500          *
7501          * Should measure whether using a lower cdclk w/o IPS
7502          */
7503         if (IS_BROADWELL(dev_priv) &&
7504             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7505                 return false;
7506
7507         return true;
7508 }
7509
7510 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7511 {
7512         struct drm_i915_private *dev_priv =
7513                 to_i915(crtc_state->uapi.crtc->dev);
7514         struct intel_atomic_state *intel_state =
7515                 to_intel_atomic_state(crtc_state->uapi.state);
7516
7517         if (!hsw_crtc_state_ips_capable(crtc_state))
7518                 return false;
7519
7520         /*
7521          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7522          * enabled and disabled dynamically based on package C states,
7523          * user space can't make reliable use of the CRCs, so let's just
7524          * completely disable it.
7525          */
7526         if (crtc_state->crc_enabled)
7527                 return false;
7528
7529         /* IPS should be fine as long as at least one plane is enabled. */
7530         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7531                 return false;
7532
7533         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7534         if (IS_BROADWELL(dev_priv) &&
7535             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7536                 return false;
7537
7538         return true;
7539 }
7540
7541 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7542 {
7543         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7544
7545         /* GDG double wide on either pipe, otherwise pipe A only */
7546         return INTEL_GEN(dev_priv) < 4 &&
7547                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7548 }
7549
7550 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7551 {
7552         u32 pixel_rate;
7553
7554         pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7555
7556         /*
7557          * We only use IF-ID interlacing. If we ever use
7558          * PF-ID we'll need to adjust the pixel_rate here.
7559          */
7560
7561         if (pipe_config->pch_pfit.enabled) {
7562                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7563                 u32 pfit_size = pipe_config->pch_pfit.size;
7564
7565                 pipe_w = pipe_config->pipe_src_w;
7566                 pipe_h = pipe_config->pipe_src_h;
7567
7568                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7569                 pfit_h = pfit_size & 0xFFFF;
7570                 if (pipe_w < pfit_w)
7571                         pipe_w = pfit_w;
7572                 if (pipe_h < pfit_h)
7573                         pipe_h = pfit_h;
7574
7575                 if (WARN_ON(!pfit_w || !pfit_h))
7576                         return pixel_rate;
7577
7578                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7579                                      pfit_w * pfit_h);
7580         }
7581
7582         return pixel_rate;
7583 }
7584
7585 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7586 {
7587         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7588
7589         if (HAS_GMCH(dev_priv))
7590                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7591                 crtc_state->pixel_rate =
7592                         crtc_state->hw.adjusted_mode.crtc_clock;
7593         else
7594                 crtc_state->pixel_rate =
7595                         ilk_pipe_pixel_rate(crtc_state);
7596 }
7597
7598 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7599                                      struct intel_crtc_state *pipe_config)
7600 {
7601         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7602         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7603         int clock_limit = dev_priv->max_dotclk_freq;
7604
7605         if (INTEL_GEN(dev_priv) < 4) {
7606                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7607
7608                 /*
7609                  * Enable double wide mode when the dot clock
7610                  * is > 90% of the (display) core speed.
7611                  */
7612                 if (intel_crtc_supports_double_wide(crtc) &&
7613                     adjusted_mode->crtc_clock > clock_limit) {
7614                         clock_limit = dev_priv->max_dotclk_freq;
7615                         pipe_config->double_wide = true;
7616                 }
7617         }
7618
7619         if (adjusted_mode->crtc_clock > clock_limit) {
7620                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7621                               adjusted_mode->crtc_clock, clock_limit,
7622                               yesno(pipe_config->double_wide));
7623                 return -EINVAL;
7624         }
7625
7626         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7627              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7628              pipe_config->hw.ctm) {
7629                 /*
7630                  * There is only one pipe CSC unit per pipe, and we need that
7631                  * for output conversion from RGB->YCBCR. So if CTM is already
7632                  * applied we can't support YCBCR420 output.
7633                  */
7634                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7635                 return -EINVAL;
7636         }
7637
7638         /*
7639          * Pipe horizontal size must be even in:
7640          * - DVO ganged mode
7641          * - LVDS dual channel mode
7642          * - Double wide pipe
7643          */
7644         if (pipe_config->pipe_src_w & 1) {
7645                 if (pipe_config->double_wide) {
7646                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7647                         return -EINVAL;
7648                 }
7649
7650                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7651                     intel_is_dual_link_lvds(dev_priv)) {
7652                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7653                         return -EINVAL;
7654                 }
7655         }
7656
7657         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7658          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7659          */
7660         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7661                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7662                 return -EINVAL;
7663
7664         intel_crtc_compute_pixel_rate(pipe_config);
7665
7666         if (pipe_config->has_pch_encoder)
7667                 return ironlake_fdi_compute_config(crtc, pipe_config);
7668
7669         return 0;
7670 }
7671
7672 static void
7673 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7674 {
7675         while (*num > DATA_LINK_M_N_MASK ||
7676                *den > DATA_LINK_M_N_MASK) {
7677                 *num >>= 1;
7678                 *den >>= 1;
7679         }
7680 }
7681
7682 static void compute_m_n(unsigned int m, unsigned int n,
7683                         u32 *ret_m, u32 *ret_n,
7684                         bool constant_n)
7685 {
7686         /*
7687          * Several DP dongles in particular seem to be fussy about
7688          * too large link M/N values. Give N value as 0x8000 that
7689          * should be acceptable by specific devices. 0x8000 is the
7690          * specified fixed N value for asynchronous clock mode,
7691          * which the devices expect also in synchronous clock mode.
7692          */
7693         if (constant_n)
7694                 *ret_n = 0x8000;
7695         else
7696                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7697
7698         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7699         intel_reduce_m_n_ratio(ret_m, ret_n);
7700 }
7701
7702 void
7703 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7704                        int pixel_clock, int link_clock,
7705                        struct intel_link_m_n *m_n,
7706                        bool constant_n, bool fec_enable)
7707 {
7708         u32 data_clock = bits_per_pixel * pixel_clock;
7709
7710         if (fec_enable)
7711                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
7712
7713         m_n->tu = 64;
7714         compute_m_n(data_clock,
7715                     link_clock * nlanes * 8,
7716                     &m_n->gmch_m, &m_n->gmch_n,
7717                     constant_n);
7718
7719         compute_m_n(pixel_clock, link_clock,
7720                     &m_n->link_m, &m_n->link_n,
7721                     constant_n);
7722 }
7723
7724 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
7725 {
7726         /*
7727          * There may be no VBT; and if the BIOS enabled SSC we can
7728          * just keep using it to avoid unnecessary flicker.  Whereas if the
7729          * BIOS isn't using it, don't assume it will work even if the VBT
7730          * indicates as much.
7731          */
7732         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7733                 bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) &
7734                         DREF_SSC1_ENABLE;
7735
7736                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
7737                         DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n",
7738                                       enableddisabled(bios_lvds_use_ssc),
7739                                       enableddisabled(dev_priv->vbt.lvds_use_ssc));
7740                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
7741                 }
7742         }
7743 }
7744
7745 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7746 {
7747         if (i915_modparams.panel_use_ssc >= 0)
7748                 return i915_modparams.panel_use_ssc != 0;
7749         return dev_priv->vbt.lvds_use_ssc
7750                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7751 }
7752
7753 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7754 {
7755         return (1 << dpll->n) << 16 | dpll->m2;
7756 }
7757
7758 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7759 {
7760         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7761 }
7762
7763 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7764                                      struct intel_crtc_state *crtc_state,
7765                                      struct dpll *reduced_clock)
7766 {
7767         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7768         u32 fp, fp2 = 0;
7769
7770         if (IS_PINEVIEW(dev_priv)) {
7771                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7772                 if (reduced_clock)
7773                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7774         } else {
7775                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7776                 if (reduced_clock)
7777                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7778         }
7779
7780         crtc_state->dpll_hw_state.fp0 = fp;
7781
7782         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7783             reduced_clock) {
7784                 crtc_state->dpll_hw_state.fp1 = fp2;
7785         } else {
7786                 crtc_state->dpll_hw_state.fp1 = fp;
7787         }
7788 }
7789
7790 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7791                 pipe)
7792 {
7793         u32 reg_val;
7794
7795         /*
7796          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7797          * and set it to a reasonable value instead.
7798          */
7799         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7800         reg_val &= 0xffffff00;
7801         reg_val |= 0x00000030;
7802         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7803
7804         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7805         reg_val &= 0x00ffffff;
7806         reg_val |= 0x8c000000;
7807         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7808
7809         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7810         reg_val &= 0xffffff00;
7811         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7812
7813         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7814         reg_val &= 0x00ffffff;
7815         reg_val |= 0xb0000000;
7816         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7817 }
7818
7819 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7820                                          const struct intel_link_m_n *m_n)
7821 {
7822         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7823         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7824         enum pipe pipe = crtc->pipe;
7825
7826         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7827         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7828         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7829         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7830 }
7831
7832 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7833                                  enum transcoder transcoder)
7834 {
7835         if (IS_HASWELL(dev_priv))
7836                 return transcoder == TRANSCODER_EDP;
7837
7838         /*
7839          * Strictly speaking some registers are available before
7840          * gen7, but we only support DRRS on gen7+
7841          */
7842         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7843 }
7844
7845 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7846                                          const struct intel_link_m_n *m_n,
7847                                          const struct intel_link_m_n *m2_n2)
7848 {
7849         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7850         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7851         enum pipe pipe = crtc->pipe;
7852         enum transcoder transcoder = crtc_state->cpu_transcoder;
7853
7854         if (INTEL_GEN(dev_priv) >= 5) {
7855                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7856                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7857                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7858                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7859                 /*
7860                  *  M2_N2 registers are set only if DRRS is supported
7861                  * (to make sure the registers are not unnecessarily accessed).
7862                  */
7863                 if (m2_n2 && crtc_state->has_drrs &&
7864                     transcoder_has_m2_n2(dev_priv, transcoder)) {
7865                         I915_WRITE(PIPE_DATA_M2(transcoder),
7866                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7867                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7868                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7869                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7870                 }
7871         } else {
7872                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7873                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7874                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7875                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7876         }
7877 }
7878
7879 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7880 {
7881         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7882
7883         if (m_n == M1_N1) {
7884                 dp_m_n = &crtc_state->dp_m_n;
7885                 dp_m2_n2 = &crtc_state->dp_m2_n2;
7886         } else if (m_n == M2_N2) {
7887
7888                 /*
7889                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7890                  * needs to be programmed into M1_N1.
7891                  */
7892                 dp_m_n = &crtc_state->dp_m2_n2;
7893         } else {
7894                 DRM_ERROR("Unsupported divider value\n");
7895                 return;
7896         }
7897
7898         if (crtc_state->has_pch_encoder)
7899                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7900         else
7901                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7902 }
7903
7904 static void vlv_compute_dpll(struct intel_crtc *crtc,
7905                              struct intel_crtc_state *pipe_config)
7906 {
7907         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7908                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7909         if (crtc->pipe != PIPE_A)
7910                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7911
7912         /* DPLL not used with DSI, but still need the rest set up */
7913         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7914                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7915                         DPLL_EXT_BUFFER_ENABLE_VLV;
7916
7917         pipe_config->dpll_hw_state.dpll_md =
7918                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7919 }
7920
7921 static void chv_compute_dpll(struct intel_crtc *crtc,
7922                              struct intel_crtc_state *pipe_config)
7923 {
7924         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7925                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7926         if (crtc->pipe != PIPE_A)
7927                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7928
7929         /* DPLL not used with DSI, but still need the rest set up */
7930         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7931                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7932
7933         pipe_config->dpll_hw_state.dpll_md =
7934                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7935 }
7936
7937 static void vlv_prepare_pll(struct intel_crtc *crtc,
7938                             const struct intel_crtc_state *pipe_config)
7939 {
7940         struct drm_device *dev = crtc->base.dev;
7941         struct drm_i915_private *dev_priv = to_i915(dev);
7942         enum pipe pipe = crtc->pipe;
7943         u32 mdiv;
7944         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7945         u32 coreclk, reg_val;
7946
7947         /* Enable Refclk */
7948         I915_WRITE(DPLL(pipe),
7949                    pipe_config->dpll_hw_state.dpll &
7950                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7951
7952         /* No need to actually set up the DPLL with DSI */
7953         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7954                 return;
7955
7956         vlv_dpio_get(dev_priv);
7957
7958         bestn = pipe_config->dpll.n;
7959         bestm1 = pipe_config->dpll.m1;
7960         bestm2 = pipe_config->dpll.m2;
7961         bestp1 = pipe_config->dpll.p1;
7962         bestp2 = pipe_config->dpll.p2;
7963
7964         /* See eDP HDMI DPIO driver vbios notes doc */
7965
7966         /* PLL B needs special handling */
7967         if (pipe == PIPE_B)
7968                 vlv_pllb_recal_opamp(dev_priv, pipe);
7969
7970         /* Set up Tx target for periodic Rcomp update */
7971         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7972
7973         /* Disable target IRef on PLL */
7974         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7975         reg_val &= 0x00ffffff;
7976         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7977
7978         /* Disable fast lock */
7979         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7980
7981         /* Set idtafcrecal before PLL is enabled */
7982         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7983         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7984         mdiv |= ((bestn << DPIO_N_SHIFT));
7985         mdiv |= (1 << DPIO_K_SHIFT);
7986
7987         /*
7988          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7989          * but we don't support that).
7990          * Note: don't use the DAC post divider as it seems unstable.
7991          */
7992         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7993         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7994
7995         mdiv |= DPIO_ENABLE_CALIBRATION;
7996         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7997
7998         /* Set HBR and RBR LPF coefficients */
7999         if (pipe_config->port_clock == 162000 ||
8000             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8001             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8002                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8003                                  0x009f0003);
8004         else
8005                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8006                                  0x00d0000f);
8007
8008         if (intel_crtc_has_dp_encoder(pipe_config)) {
8009                 /* Use SSC source */
8010                 if (pipe == PIPE_A)
8011                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8012                                          0x0df40000);
8013                 else
8014                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8015                                          0x0df70000);
8016         } else { /* HDMI or VGA */
8017                 /* Use bend source */
8018                 if (pipe == PIPE_A)
8019                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8020                                          0x0df70000);
8021                 else
8022                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8023                                          0x0df40000);
8024         }
8025
8026         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8027         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8028         if (intel_crtc_has_dp_encoder(pipe_config))
8029                 coreclk |= 0x01000000;
8030         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8031
8032         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8033
8034         vlv_dpio_put(dev_priv);
8035 }
8036
8037 static void chv_prepare_pll(struct intel_crtc *crtc,
8038                             const struct intel_crtc_state *pipe_config)
8039 {
8040         struct drm_device *dev = crtc->base.dev;
8041         struct drm_i915_private *dev_priv = to_i915(dev);
8042         enum pipe pipe = crtc->pipe;
8043         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8044         u32 loopfilter, tribuf_calcntr;
8045         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8046         u32 dpio_val;
8047         int vco;
8048
8049         /* Enable Refclk and SSC */
8050         I915_WRITE(DPLL(pipe),
8051                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8052
8053         /* No need to actually set up the DPLL with DSI */
8054         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8055                 return;
8056
8057         bestn = pipe_config->dpll.n;
8058         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8059         bestm1 = pipe_config->dpll.m1;
8060         bestm2 = pipe_config->dpll.m2 >> 22;
8061         bestp1 = pipe_config->dpll.p1;
8062         bestp2 = pipe_config->dpll.p2;
8063         vco = pipe_config->dpll.vco;
8064         dpio_val = 0;
8065         loopfilter = 0;
8066
8067         vlv_dpio_get(dev_priv);
8068
8069         /* p1 and p2 divider */
8070         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8071                         5 << DPIO_CHV_S1_DIV_SHIFT |
8072                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8073                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8074                         1 << DPIO_CHV_K_DIV_SHIFT);
8075
8076         /* Feedback post-divider - m2 */
8077         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8078
8079         /* Feedback refclk divider - n and m1 */
8080         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8081                         DPIO_CHV_M1_DIV_BY_2 |
8082                         1 << DPIO_CHV_N_DIV_SHIFT);
8083
8084         /* M2 fraction division */
8085         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8086
8087         /* M2 fraction division enable */
8088         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8089         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8090         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8091         if (bestm2_frac)
8092                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8093         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8094
8095         /* Program digital lock detect threshold */
8096         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8097         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8098                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8099         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8100         if (!bestm2_frac)
8101                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8102         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8103
8104         /* Loop filter */
8105         if (vco == 5400000) {
8106                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8107                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8108                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8109                 tribuf_calcntr = 0x9;
8110         } else if (vco <= 6200000) {
8111                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8112                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8113                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8114                 tribuf_calcntr = 0x9;
8115         } else if (vco <= 6480000) {
8116                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8117                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8118                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8119                 tribuf_calcntr = 0x8;
8120         } else {
8121                 /* Not supported. Apply the same limits as in the max case */
8122                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8123                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8124                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8125                 tribuf_calcntr = 0;
8126         }
8127         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8128
8129         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8130         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8131         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8132         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8133
8134         /* AFC Recal */
8135         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8136                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8137                         DPIO_AFC_RECAL);
8138
8139         vlv_dpio_put(dev_priv);
8140 }
8141
8142 /**
8143  * vlv_force_pll_on - forcibly enable just the PLL
8144  * @dev_priv: i915 private structure
8145  * @pipe: pipe PLL to enable
8146  * @dpll: PLL configuration
8147  *
8148  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8149  * in cases where we need the PLL enabled even when @pipe is not going to
8150  * be enabled.
8151  */
8152 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8153                      const struct dpll *dpll)
8154 {
8155         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8156         struct intel_crtc_state *pipe_config;
8157
8158         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8159         if (!pipe_config)
8160                 return -ENOMEM;
8161
8162         pipe_config->uapi.crtc = &crtc->base;
8163         pipe_config->pixel_multiplier = 1;
8164         pipe_config->dpll = *dpll;
8165
8166         if (IS_CHERRYVIEW(dev_priv)) {
8167                 chv_compute_dpll(crtc, pipe_config);
8168                 chv_prepare_pll(crtc, pipe_config);
8169                 chv_enable_pll(crtc, pipe_config);
8170         } else {
8171                 vlv_compute_dpll(crtc, pipe_config);
8172                 vlv_prepare_pll(crtc, pipe_config);
8173                 vlv_enable_pll(crtc, pipe_config);
8174         }
8175
8176         kfree(pipe_config);
8177
8178         return 0;
8179 }
8180
8181 /**
8182  * vlv_force_pll_off - forcibly disable just the PLL
8183  * @dev_priv: i915 private structure
8184  * @pipe: pipe PLL to disable
8185  *
8186  * Disable the PLL for @pipe. To be used in cases where we need
8187  * the PLL enabled even when @pipe is not going to be enabled.
8188  */
8189 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8190 {
8191         if (IS_CHERRYVIEW(dev_priv))
8192                 chv_disable_pll(dev_priv, pipe);
8193         else
8194                 vlv_disable_pll(dev_priv, pipe);
8195 }
8196
8197 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8198                               struct intel_crtc_state *crtc_state,
8199                               struct dpll *reduced_clock)
8200 {
8201         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8202         u32 dpll;
8203         struct dpll *clock = &crtc_state->dpll;
8204
8205         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8206
8207         dpll = DPLL_VGA_MODE_DIS;
8208
8209         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8210                 dpll |= DPLLB_MODE_LVDS;
8211         else
8212                 dpll |= DPLLB_MODE_DAC_SERIAL;
8213
8214         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8215             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8216                 dpll |= (crtc_state->pixel_multiplier - 1)
8217                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8218         }
8219
8220         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8221             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8222                 dpll |= DPLL_SDVO_HIGH_SPEED;
8223
8224         if (intel_crtc_has_dp_encoder(crtc_state))
8225                 dpll |= DPLL_SDVO_HIGH_SPEED;
8226
8227         /* compute bitmask from p1 value */
8228         if (IS_PINEVIEW(dev_priv))
8229                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8230         else {
8231                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8232                 if (IS_G4X(dev_priv) && reduced_clock)
8233                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8234         }
8235         switch (clock->p2) {
8236         case 5:
8237                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8238                 break;
8239         case 7:
8240                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8241                 break;
8242         case 10:
8243                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8244                 break;
8245         case 14:
8246                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8247                 break;
8248         }
8249         if (INTEL_GEN(dev_priv) >= 4)
8250                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8251
8252         if (crtc_state->sdvo_tv_clock)
8253                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8254         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8255                  intel_panel_use_ssc(dev_priv))
8256                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8257         else
8258                 dpll |= PLL_REF_INPUT_DREFCLK;
8259
8260         dpll |= DPLL_VCO_ENABLE;
8261         crtc_state->dpll_hw_state.dpll = dpll;
8262
8263         if (INTEL_GEN(dev_priv) >= 4) {
8264                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8265                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8266                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8267         }
8268 }
8269
8270 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8271                               struct intel_crtc_state *crtc_state,
8272                               struct dpll *reduced_clock)
8273 {
8274         struct drm_device *dev = crtc->base.dev;
8275         struct drm_i915_private *dev_priv = to_i915(dev);
8276         u32 dpll;
8277         struct dpll *clock = &crtc_state->dpll;
8278
8279         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8280
8281         dpll = DPLL_VGA_MODE_DIS;
8282
8283         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8284                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8285         } else {
8286                 if (clock->p1 == 2)
8287                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8288                 else
8289                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8290                 if (clock->p2 == 4)
8291                         dpll |= PLL_P2_DIVIDE_BY_4;
8292         }
8293
8294         /*
8295          * Bspec:
8296          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8297          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8298          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8299          *  Enable) must be set to “1” in both the DPLL A Control Register
8300          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8301          *
8302          * For simplicity We simply keep both bits always enabled in
8303          * both DPLLS. The spec says we should disable the DVO 2X clock
8304          * when not needed, but this seems to work fine in practice.
8305          */
8306         if (IS_I830(dev_priv) ||
8307             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8308                 dpll |= DPLL_DVO_2X_MODE;
8309
8310         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8311             intel_panel_use_ssc(dev_priv))
8312                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8313         else
8314                 dpll |= PLL_REF_INPUT_DREFCLK;
8315
8316         dpll |= DPLL_VCO_ENABLE;
8317         crtc_state->dpll_hw_state.dpll = dpll;
8318 }
8319
8320 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8321 {
8322         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8323         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8324         enum pipe pipe = crtc->pipe;
8325         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8326         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8327         u32 crtc_vtotal, crtc_vblank_end;
8328         int vsyncshift = 0;
8329
8330         /* We need to be careful not to changed the adjusted mode, for otherwise
8331          * the hw state checker will get angry at the mismatch. */
8332         crtc_vtotal = adjusted_mode->crtc_vtotal;
8333         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8334
8335         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8336                 /* the chip adds 2 halflines automatically */
8337                 crtc_vtotal -= 1;
8338                 crtc_vblank_end -= 1;
8339
8340                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8341                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8342                 else
8343                         vsyncshift = adjusted_mode->crtc_hsync_start -
8344                                 adjusted_mode->crtc_htotal / 2;
8345                 if (vsyncshift < 0)
8346                         vsyncshift += adjusted_mode->crtc_htotal;
8347         }
8348
8349         if (INTEL_GEN(dev_priv) > 3)
8350                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8351
8352         I915_WRITE(HTOTAL(cpu_transcoder),
8353                    (adjusted_mode->crtc_hdisplay - 1) |
8354                    ((adjusted_mode->crtc_htotal - 1) << 16));
8355         I915_WRITE(HBLANK(cpu_transcoder),
8356                    (adjusted_mode->crtc_hblank_start - 1) |
8357                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8358         I915_WRITE(HSYNC(cpu_transcoder),
8359                    (adjusted_mode->crtc_hsync_start - 1) |
8360                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8361
8362         I915_WRITE(VTOTAL(cpu_transcoder),
8363                    (adjusted_mode->crtc_vdisplay - 1) |
8364                    ((crtc_vtotal - 1) << 16));
8365         I915_WRITE(VBLANK(cpu_transcoder),
8366                    (adjusted_mode->crtc_vblank_start - 1) |
8367                    ((crtc_vblank_end - 1) << 16));
8368         I915_WRITE(VSYNC(cpu_transcoder),
8369                    (adjusted_mode->crtc_vsync_start - 1) |
8370                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8371
8372         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8373          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8374          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8375          * bits. */
8376         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8377             (pipe == PIPE_B || pipe == PIPE_C))
8378                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8379
8380 }
8381
8382 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8383 {
8384         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8385         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8386         enum pipe pipe = crtc->pipe;
8387
8388         /* pipesrc controls the size that is scaled from, which should
8389          * always be the user's requested size.
8390          */
8391         I915_WRITE(PIPESRC(pipe),
8392                    ((crtc_state->pipe_src_w - 1) << 16) |
8393                    (crtc_state->pipe_src_h - 1));
8394 }
8395
8396 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8397 {
8398         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8399         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8400
8401         if (IS_GEN(dev_priv, 2))
8402                 return false;
8403
8404         if (INTEL_GEN(dev_priv) >= 9 ||
8405             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8406                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8407         else
8408                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8409 }
8410
8411 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8412                                    struct intel_crtc_state *pipe_config)
8413 {
8414         struct drm_device *dev = crtc->base.dev;
8415         struct drm_i915_private *dev_priv = to_i915(dev);
8416         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8417         u32 tmp;
8418
8419         tmp = I915_READ(HTOTAL(cpu_transcoder));
8420         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8421         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8422
8423         if (!transcoder_is_dsi(cpu_transcoder)) {
8424                 tmp = I915_READ(HBLANK(cpu_transcoder));
8425                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8426                                                         (tmp & 0xffff) + 1;
8427                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8428                                                 ((tmp >> 16) & 0xffff) + 1;
8429         }
8430         tmp = I915_READ(HSYNC(cpu_transcoder));
8431         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8432         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8433
8434         tmp = I915_READ(VTOTAL(cpu_transcoder));
8435         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8436         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8437
8438         if (!transcoder_is_dsi(cpu_transcoder)) {
8439                 tmp = I915_READ(VBLANK(cpu_transcoder));
8440                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8441                                                         (tmp & 0xffff) + 1;
8442                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8443                                                 ((tmp >> 16) & 0xffff) + 1;
8444         }
8445         tmp = I915_READ(VSYNC(cpu_transcoder));
8446         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8447         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8448
8449         if (intel_pipe_is_interlaced(pipe_config)) {
8450                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8451                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8452                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8453         }
8454 }
8455
8456 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8457                                     struct intel_crtc_state *pipe_config)
8458 {
8459         struct drm_device *dev = crtc->base.dev;
8460         struct drm_i915_private *dev_priv = to_i915(dev);
8461         u32 tmp;
8462
8463         tmp = I915_READ(PIPESRC(crtc->pipe));
8464         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8465         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8466
8467         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8468         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8469 }
8470
8471 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8472                                  struct intel_crtc_state *pipe_config)
8473 {
8474         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8475         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8476         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8477         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8478
8479         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8480         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8481         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8482         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8483
8484         mode->flags = pipe_config->hw.adjusted_mode.flags;
8485         mode->type = DRM_MODE_TYPE_DRIVER;
8486
8487         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8488
8489         mode->hsync = drm_mode_hsync(mode);
8490         mode->vrefresh = drm_mode_vrefresh(mode);
8491         drm_mode_set_name(mode);
8492 }
8493
8494 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8495 {
8496         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8497         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8498         u32 pipeconf;
8499
8500         pipeconf = 0;
8501
8502         /* we keep both pipes enabled on 830 */
8503         if (IS_I830(dev_priv))
8504                 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8505
8506         if (crtc_state->double_wide)
8507                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8508
8509         /* only g4x and later have fancy bpc/dither controls */
8510         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8511             IS_CHERRYVIEW(dev_priv)) {
8512                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8513                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8514                         pipeconf |= PIPECONF_DITHER_EN |
8515                                     PIPECONF_DITHER_TYPE_SP;
8516
8517                 switch (crtc_state->pipe_bpp) {
8518                 case 18:
8519                         pipeconf |= PIPECONF_6BPC;
8520                         break;
8521                 case 24:
8522                         pipeconf |= PIPECONF_8BPC;
8523                         break;
8524                 case 30:
8525                         pipeconf |= PIPECONF_10BPC;
8526                         break;
8527                 default:
8528                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8529                         BUG();
8530                 }
8531         }
8532
8533         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8534                 if (INTEL_GEN(dev_priv) < 4 ||
8535                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8536                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8537                 else
8538                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8539         } else {
8540                 pipeconf |= PIPECONF_PROGRESSIVE;
8541         }
8542
8543         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8544              crtc_state->limited_color_range)
8545                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8546
8547         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8548
8549         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8550
8551         I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8552         POSTING_READ(PIPECONF(crtc->pipe));
8553 }
8554
8555 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8556                                    struct intel_crtc_state *crtc_state)
8557 {
8558         struct drm_device *dev = crtc->base.dev;
8559         struct drm_i915_private *dev_priv = to_i915(dev);
8560         const struct intel_limit *limit;
8561         int refclk = 48000;
8562
8563         memset(&crtc_state->dpll_hw_state, 0,
8564                sizeof(crtc_state->dpll_hw_state));
8565
8566         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8567                 if (intel_panel_use_ssc(dev_priv)) {
8568                         refclk = dev_priv->vbt.lvds_ssc_freq;
8569                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8570                 }
8571
8572                 limit = &intel_limits_i8xx_lvds;
8573         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8574                 limit = &intel_limits_i8xx_dvo;
8575         } else {
8576                 limit = &intel_limits_i8xx_dac;
8577         }
8578
8579         if (!crtc_state->clock_set &&
8580             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8581                                  refclk, NULL, &crtc_state->dpll)) {
8582                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8583                 return -EINVAL;
8584         }
8585
8586         i8xx_compute_dpll(crtc, crtc_state, NULL);
8587
8588         return 0;
8589 }
8590
8591 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8592                                   struct intel_crtc_state *crtc_state)
8593 {
8594         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8595         const struct intel_limit *limit;
8596         int refclk = 96000;
8597
8598         memset(&crtc_state->dpll_hw_state, 0,
8599                sizeof(crtc_state->dpll_hw_state));
8600
8601         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8602                 if (intel_panel_use_ssc(dev_priv)) {
8603                         refclk = dev_priv->vbt.lvds_ssc_freq;
8604                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8605                 }
8606
8607                 if (intel_is_dual_link_lvds(dev_priv))
8608                         limit = &intel_limits_g4x_dual_channel_lvds;
8609                 else
8610                         limit = &intel_limits_g4x_single_channel_lvds;
8611         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8612                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8613                 limit = &intel_limits_g4x_hdmi;
8614         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8615                 limit = &intel_limits_g4x_sdvo;
8616         } else {
8617                 /* The option is for other outputs */
8618                 limit = &intel_limits_i9xx_sdvo;
8619         }
8620
8621         if (!crtc_state->clock_set &&
8622             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8623                                 refclk, NULL, &crtc_state->dpll)) {
8624                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8625                 return -EINVAL;
8626         }
8627
8628         i9xx_compute_dpll(crtc, crtc_state, NULL);
8629
8630         return 0;
8631 }
8632
8633 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8634                                   struct intel_crtc_state *crtc_state)
8635 {
8636         struct drm_device *dev = crtc->base.dev;
8637         struct drm_i915_private *dev_priv = to_i915(dev);
8638         const struct intel_limit *limit;
8639         int refclk = 96000;
8640
8641         memset(&crtc_state->dpll_hw_state, 0,
8642                sizeof(crtc_state->dpll_hw_state));
8643
8644         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8645                 if (intel_panel_use_ssc(dev_priv)) {
8646                         refclk = dev_priv->vbt.lvds_ssc_freq;
8647                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8648                 }
8649
8650                 limit = &intel_limits_pineview_lvds;
8651         } else {
8652                 limit = &intel_limits_pineview_sdvo;
8653         }
8654
8655         if (!crtc_state->clock_set &&
8656             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8657                                 refclk, NULL, &crtc_state->dpll)) {
8658                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8659                 return -EINVAL;
8660         }
8661
8662         i9xx_compute_dpll(crtc, crtc_state, NULL);
8663
8664         return 0;
8665 }
8666
8667 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8668                                    struct intel_crtc_state *crtc_state)
8669 {
8670         struct drm_device *dev = crtc->base.dev;
8671         struct drm_i915_private *dev_priv = to_i915(dev);
8672         const struct intel_limit *limit;
8673         int refclk = 96000;
8674
8675         memset(&crtc_state->dpll_hw_state, 0,
8676                sizeof(crtc_state->dpll_hw_state));
8677
8678         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8679                 if (intel_panel_use_ssc(dev_priv)) {
8680                         refclk = dev_priv->vbt.lvds_ssc_freq;
8681                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8682                 }
8683
8684                 limit = &intel_limits_i9xx_lvds;
8685         } else {
8686                 limit = &intel_limits_i9xx_sdvo;
8687         }
8688
8689         if (!crtc_state->clock_set &&
8690             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8691                                  refclk, NULL, &crtc_state->dpll)) {
8692                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8693                 return -EINVAL;
8694         }
8695
8696         i9xx_compute_dpll(crtc, crtc_state, NULL);
8697
8698         return 0;
8699 }
8700
8701 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8702                                   struct intel_crtc_state *crtc_state)
8703 {
8704         int refclk = 100000;
8705         const struct intel_limit *limit = &intel_limits_chv;
8706
8707         memset(&crtc_state->dpll_hw_state, 0,
8708                sizeof(crtc_state->dpll_hw_state));
8709
8710         if (!crtc_state->clock_set &&
8711             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8712                                 refclk, NULL, &crtc_state->dpll)) {
8713                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8714                 return -EINVAL;
8715         }
8716
8717         chv_compute_dpll(crtc, crtc_state);
8718
8719         return 0;
8720 }
8721
8722 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8723                                   struct intel_crtc_state *crtc_state)
8724 {
8725         int refclk = 100000;
8726         const struct intel_limit *limit = &intel_limits_vlv;
8727
8728         memset(&crtc_state->dpll_hw_state, 0,
8729                sizeof(crtc_state->dpll_hw_state));
8730
8731         if (!crtc_state->clock_set &&
8732             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8733                                 refclk, NULL, &crtc_state->dpll)) {
8734                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8735                 return -EINVAL;
8736         }
8737
8738         vlv_compute_dpll(crtc, crtc_state);
8739
8740         return 0;
8741 }
8742
8743 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8744 {
8745         if (IS_I830(dev_priv))
8746                 return false;
8747
8748         return INTEL_GEN(dev_priv) >= 4 ||
8749                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8750 }
8751
8752 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8753                                  struct intel_crtc_state *pipe_config)
8754 {
8755         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8756         u32 tmp;
8757
8758         if (!i9xx_has_pfit(dev_priv))
8759                 return;
8760
8761         tmp = I915_READ(PFIT_CONTROL);
8762         if (!(tmp & PFIT_ENABLE))
8763                 return;
8764
8765         /* Check whether the pfit is attached to our pipe. */
8766         if (INTEL_GEN(dev_priv) < 4) {
8767                 if (crtc->pipe != PIPE_B)
8768                         return;
8769         } else {
8770                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8771                         return;
8772         }
8773
8774         pipe_config->gmch_pfit.control = tmp;
8775         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8776 }
8777
8778 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8779                                struct intel_crtc_state *pipe_config)
8780 {
8781         struct drm_device *dev = crtc->base.dev;
8782         struct drm_i915_private *dev_priv = to_i915(dev);
8783         enum pipe pipe = crtc->pipe;
8784         struct dpll clock;
8785         u32 mdiv;
8786         int refclk = 100000;
8787
8788         /* In case of DSI, DPLL will not be used */
8789         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8790                 return;
8791
8792         vlv_dpio_get(dev_priv);
8793         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8794         vlv_dpio_put(dev_priv);
8795
8796         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8797         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8798         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8799         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8800         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8801
8802         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8803 }
8804
8805 static void
8806 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8807                               struct intel_initial_plane_config *plane_config)
8808 {
8809         struct drm_device *dev = crtc->base.dev;
8810         struct drm_i915_private *dev_priv = to_i915(dev);
8811         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8812         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8813         enum pipe pipe;
8814         u32 val, base, offset;
8815         int fourcc, pixel_format;
8816         unsigned int aligned_height;
8817         struct drm_framebuffer *fb;
8818         struct intel_framebuffer *intel_fb;
8819
8820         if (!plane->get_hw_state(plane, &pipe))
8821                 return;
8822
8823         WARN_ON(pipe != crtc->pipe);
8824
8825         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8826         if (!intel_fb) {
8827                 DRM_DEBUG_KMS("failed to alloc fb\n");
8828                 return;
8829         }
8830
8831         fb = &intel_fb->base;
8832
8833         fb->dev = dev;
8834
8835         val = I915_READ(DSPCNTR(i9xx_plane));
8836
8837         if (INTEL_GEN(dev_priv) >= 4) {
8838                 if (val & DISPPLANE_TILED) {
8839                         plane_config->tiling = I915_TILING_X;
8840                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8841                 }
8842
8843                 if (val & DISPPLANE_ROTATE_180)
8844                         plane_config->rotation = DRM_MODE_ROTATE_180;
8845         }
8846
8847         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8848             val & DISPPLANE_MIRROR)
8849                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8850
8851         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8852         fourcc = i9xx_format_to_fourcc(pixel_format);
8853         fb->format = drm_format_info(fourcc);
8854
8855         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8856                 offset = I915_READ(DSPOFFSET(i9xx_plane));
8857                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8858         } else if (INTEL_GEN(dev_priv) >= 4) {
8859                 if (plane_config->tiling)
8860                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
8861                 else
8862                         offset = I915_READ(DSPLINOFF(i9xx_plane));
8863                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8864         } else {
8865                 base = I915_READ(DSPADDR(i9xx_plane));
8866         }
8867         plane_config->base = base;
8868
8869         val = I915_READ(PIPESRC(pipe));
8870         fb->width = ((val >> 16) & 0xfff) + 1;
8871         fb->height = ((val >> 0) & 0xfff) + 1;
8872
8873         val = I915_READ(DSPSTRIDE(i9xx_plane));
8874         fb->pitches[0] = val & 0xffffffc0;
8875
8876         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8877
8878         plane_config->size = fb->pitches[0] * aligned_height;
8879
8880         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8881                       crtc->base.name, plane->base.name, fb->width, fb->height,
8882                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8883                       plane_config->size);
8884
8885         plane_config->fb = intel_fb;
8886 }
8887
8888 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8889                                struct intel_crtc_state *pipe_config)
8890 {
8891         struct drm_device *dev = crtc->base.dev;
8892         struct drm_i915_private *dev_priv = to_i915(dev);
8893         enum pipe pipe = crtc->pipe;
8894         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8895         struct dpll clock;
8896         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8897         int refclk = 100000;
8898
8899         /* In case of DSI, DPLL will not be used */
8900         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8901                 return;
8902
8903         vlv_dpio_get(dev_priv);
8904         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8905         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8906         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8907         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8908         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8909         vlv_dpio_put(dev_priv);
8910
8911         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8912         clock.m2 = (pll_dw0 & 0xff) << 22;
8913         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8914                 clock.m2 |= pll_dw2 & 0x3fffff;
8915         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8916         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8917         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8918
8919         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8920 }
8921
8922 static enum intel_output_format
8923 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
8924 {
8925         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8926         u32 tmp;
8927
8928         tmp = I915_READ(PIPEMISC(crtc->pipe));
8929
8930         if (tmp & PIPEMISC_YUV420_ENABLE) {
8931                 /* We support 4:2:0 in full blend mode only */
8932                 WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
8933
8934                 return INTEL_OUTPUT_FORMAT_YCBCR420;
8935         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8936                 return INTEL_OUTPUT_FORMAT_YCBCR444;
8937         } else {
8938                 return INTEL_OUTPUT_FORMAT_RGB;
8939         }
8940 }
8941
8942 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8943 {
8944         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8945         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8946         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8947         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8948         u32 tmp;
8949
8950         tmp = I915_READ(DSPCNTR(i9xx_plane));
8951
8952         if (tmp & DISPPLANE_GAMMA_ENABLE)
8953                 crtc_state->gamma_enable = true;
8954
8955         if (!HAS_GMCH(dev_priv) &&
8956             tmp & DISPPLANE_PIPE_CSC_ENABLE)
8957                 crtc_state->csc_enable = true;
8958 }
8959
8960 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8961                                  struct intel_crtc_state *pipe_config)
8962 {
8963         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8964         enum intel_display_power_domain power_domain;
8965         intel_wakeref_t wakeref;
8966         u32 tmp;
8967         bool ret;
8968
8969         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8970         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8971         if (!wakeref)
8972                 return false;
8973
8974         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8975         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8976         pipe_config->shared_dpll = NULL;
8977         pipe_config->master_transcoder = INVALID_TRANSCODER;
8978
8979         ret = false;
8980
8981         tmp = I915_READ(PIPECONF(crtc->pipe));
8982         if (!(tmp & PIPECONF_ENABLE))
8983                 goto out;
8984
8985         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8986             IS_CHERRYVIEW(dev_priv)) {
8987                 switch (tmp & PIPECONF_BPC_MASK) {
8988                 case PIPECONF_6BPC:
8989                         pipe_config->pipe_bpp = 18;
8990                         break;
8991                 case PIPECONF_8BPC:
8992                         pipe_config->pipe_bpp = 24;
8993                         break;
8994                 case PIPECONF_10BPC:
8995                         pipe_config->pipe_bpp = 30;
8996                         break;
8997                 default:
8998                         break;
8999                 }
9000         }
9001
9002         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9003             (tmp & PIPECONF_COLOR_RANGE_SELECT))
9004                 pipe_config->limited_color_range = true;
9005
9006         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9007                 PIPECONF_GAMMA_MODE_SHIFT;
9008
9009         if (IS_CHERRYVIEW(dev_priv))
9010                 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
9011
9012         i9xx_get_pipe_color_config(pipe_config);
9013         intel_color_get_config(pipe_config);
9014
9015         if (INTEL_GEN(dev_priv) < 4)
9016                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9017
9018         intel_get_pipe_timings(crtc, pipe_config);
9019         intel_get_pipe_src_size(crtc, pipe_config);
9020
9021         i9xx_get_pfit_config(crtc, pipe_config);
9022
9023         if (INTEL_GEN(dev_priv) >= 4) {
9024                 /* No way to read it out on pipes B and C */
9025                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9026                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
9027                 else
9028                         tmp = I915_READ(DPLL_MD(crtc->pipe));
9029                 pipe_config->pixel_multiplier =
9030                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9031                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9032                 pipe_config->dpll_hw_state.dpll_md = tmp;
9033         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9034                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9035                 tmp = I915_READ(DPLL(crtc->pipe));
9036                 pipe_config->pixel_multiplier =
9037                         ((tmp & SDVO_MULTIPLIER_MASK)
9038                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9039         } else {
9040                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9041                  * port and will be fixed up in the encoder->get_config
9042                  * function. */
9043                 pipe_config->pixel_multiplier = 1;
9044         }
9045         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
9046         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9047                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
9048                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
9049         } else {
9050                 /* Mask out read-only status bits. */
9051                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9052                                                      DPLL_PORTC_READY_MASK |
9053                                                      DPLL_PORTB_READY_MASK);
9054         }
9055
9056         if (IS_CHERRYVIEW(dev_priv))
9057                 chv_crtc_clock_get(crtc, pipe_config);
9058         else if (IS_VALLEYVIEW(dev_priv))
9059                 vlv_crtc_clock_get(crtc, pipe_config);
9060         else
9061                 i9xx_crtc_clock_get(crtc, pipe_config);
9062
9063         /*
9064          * Normally the dotclock is filled in by the encoder .get_config()
9065          * but in case the pipe is enabled w/o any ports we need a sane
9066          * default.
9067          */
9068         pipe_config->hw.adjusted_mode.crtc_clock =
9069                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9070
9071         ret = true;
9072
9073 out:
9074         intel_display_power_put(dev_priv, power_domain, wakeref);
9075
9076         return ret;
9077 }
9078
9079 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
9080 {
9081         struct intel_encoder *encoder;
9082         int i;
9083         u32 val, final;
9084         bool has_lvds = false;
9085         bool has_cpu_edp = false;
9086         bool has_panel = false;
9087         bool has_ck505 = false;
9088         bool can_ssc = false;
9089         bool using_ssc_source = false;
9090
9091         /* We need to take the global config into account */
9092         for_each_intel_encoder(&dev_priv->drm, encoder) {
9093                 switch (encoder->type) {
9094                 case INTEL_OUTPUT_LVDS:
9095                         has_panel = true;
9096                         has_lvds = true;
9097                         break;
9098                 case INTEL_OUTPUT_EDP:
9099                         has_panel = true;
9100                         if (encoder->port == PORT_A)
9101                                 has_cpu_edp = true;
9102                         break;
9103                 default:
9104                         break;
9105                 }
9106         }
9107
9108         if (HAS_PCH_IBX(dev_priv)) {
9109                 has_ck505 = dev_priv->vbt.display_clock_mode;
9110                 can_ssc = has_ck505;
9111         } else {
9112                 has_ck505 = false;
9113                 can_ssc = true;
9114         }
9115
9116         /* Check if any DPLLs are using the SSC source */
9117         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9118                 u32 temp = I915_READ(PCH_DPLL(i));
9119
9120                 if (!(temp & DPLL_VCO_ENABLE))
9121                         continue;
9122
9123                 if ((temp & PLL_REF_INPUT_MASK) ==
9124                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9125                         using_ssc_source = true;
9126                         break;
9127                 }
9128         }
9129
9130         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9131                       has_panel, has_lvds, has_ck505, using_ssc_source);
9132
9133         /* Ironlake: try to setup display ref clock before DPLL
9134          * enabling. This is only under driver's control after
9135          * PCH B stepping, previous chipset stepping should be
9136          * ignoring this setting.
9137          */
9138         val = I915_READ(PCH_DREF_CONTROL);
9139
9140         /* As we must carefully and slowly disable/enable each source in turn,
9141          * compute the final state we want first and check if we need to
9142          * make any changes at all.
9143          */
9144         final = val;
9145         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9146         if (has_ck505)
9147                 final |= DREF_NONSPREAD_CK505_ENABLE;
9148         else
9149                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9150
9151         final &= ~DREF_SSC_SOURCE_MASK;
9152         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9153         final &= ~DREF_SSC1_ENABLE;
9154
9155         if (has_panel) {
9156                 final |= DREF_SSC_SOURCE_ENABLE;
9157
9158                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9159                         final |= DREF_SSC1_ENABLE;
9160
9161                 if (has_cpu_edp) {
9162                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9163                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9164                         else
9165                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9166                 } else
9167                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9168         } else if (using_ssc_source) {
9169                 final |= DREF_SSC_SOURCE_ENABLE;
9170                 final |= DREF_SSC1_ENABLE;
9171         }
9172
9173         if (final == val)
9174                 return;
9175
9176         /* Always enable nonspread source */
9177         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9178
9179         if (has_ck505)
9180                 val |= DREF_NONSPREAD_CK505_ENABLE;
9181         else
9182                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9183
9184         if (has_panel) {
9185                 val &= ~DREF_SSC_SOURCE_MASK;
9186                 val |= DREF_SSC_SOURCE_ENABLE;
9187
9188                 /* SSC must be turned on before enabling the CPU output  */
9189                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9190                         DRM_DEBUG_KMS("Using SSC on panel\n");
9191                         val |= DREF_SSC1_ENABLE;
9192                 } else
9193                         val &= ~DREF_SSC1_ENABLE;
9194
9195                 /* Get SSC going before enabling the outputs */
9196                 I915_WRITE(PCH_DREF_CONTROL, val);
9197                 POSTING_READ(PCH_DREF_CONTROL);
9198                 udelay(200);
9199
9200                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9201
9202                 /* Enable CPU source on CPU attached eDP */
9203                 if (has_cpu_edp) {
9204                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9205                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9206                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9207                         } else
9208                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9209                 } else
9210                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9211
9212                 I915_WRITE(PCH_DREF_CONTROL, val);
9213                 POSTING_READ(PCH_DREF_CONTROL);
9214                 udelay(200);
9215         } else {
9216                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9217
9218                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9219
9220                 /* Turn off CPU output */
9221                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9222
9223                 I915_WRITE(PCH_DREF_CONTROL, val);
9224                 POSTING_READ(PCH_DREF_CONTROL);
9225                 udelay(200);
9226
9227                 if (!using_ssc_source) {
9228                         DRM_DEBUG_KMS("Disabling SSC source\n");
9229
9230                         /* Turn off the SSC source */
9231                         val &= ~DREF_SSC_SOURCE_MASK;
9232                         val |= DREF_SSC_SOURCE_DISABLE;
9233
9234                         /* Turn off SSC1 */
9235                         val &= ~DREF_SSC1_ENABLE;
9236
9237                         I915_WRITE(PCH_DREF_CONTROL, val);
9238                         POSTING_READ(PCH_DREF_CONTROL);
9239                         udelay(200);
9240                 }
9241         }
9242
9243         BUG_ON(val != final);
9244 }
9245
9246 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9247 {
9248         u32 tmp;
9249
9250         tmp = I915_READ(SOUTH_CHICKEN2);
9251         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9252         I915_WRITE(SOUTH_CHICKEN2, tmp);
9253
9254         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9255                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9256                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9257
9258         tmp = I915_READ(SOUTH_CHICKEN2);
9259         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9260         I915_WRITE(SOUTH_CHICKEN2, tmp);
9261
9262         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9263                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9264                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9265 }
9266
9267 /* WaMPhyProgramming:hsw */
9268 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9269 {
9270         u32 tmp;
9271
9272         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9273         tmp &= ~(0xFF << 24);
9274         tmp |= (0x12 << 24);
9275         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9276
9277         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9278         tmp |= (1 << 11);
9279         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9280
9281         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9282         tmp |= (1 << 11);
9283         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9284
9285         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9286         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9287         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9288
9289         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9290         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9291         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9292
9293         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9294         tmp &= ~(7 << 13);
9295         tmp |= (5 << 13);
9296         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9297
9298         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9299         tmp &= ~(7 << 13);
9300         tmp |= (5 << 13);
9301         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9302
9303         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9304         tmp &= ~0xFF;
9305         tmp |= 0x1C;
9306         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9307
9308         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9309         tmp &= ~0xFF;
9310         tmp |= 0x1C;
9311         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9312
9313         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9314         tmp &= ~(0xFF << 16);
9315         tmp |= (0x1C << 16);
9316         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9317
9318         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9319         tmp &= ~(0xFF << 16);
9320         tmp |= (0x1C << 16);
9321         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9322
9323         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9324         tmp |= (1 << 27);
9325         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9326
9327         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9328         tmp |= (1 << 27);
9329         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9330
9331         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9332         tmp &= ~(0xF << 28);
9333         tmp |= (4 << 28);
9334         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9335
9336         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9337         tmp &= ~(0xF << 28);
9338         tmp |= (4 << 28);
9339         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9340 }
9341
9342 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9343  * Programming" based on the parameters passed:
9344  * - Sequence to enable CLKOUT_DP
9345  * - Sequence to enable CLKOUT_DP without spread
9346  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9347  */
9348 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9349                                  bool with_spread, bool with_fdi)
9350 {
9351         u32 reg, tmp;
9352
9353         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9354                 with_spread = true;
9355         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9356             with_fdi, "LP PCH doesn't have FDI\n"))
9357                 with_fdi = false;
9358
9359         mutex_lock(&dev_priv->sb_lock);
9360
9361         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9362         tmp &= ~SBI_SSCCTL_DISABLE;
9363         tmp |= SBI_SSCCTL_PATHALT;
9364         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9365
9366         udelay(24);
9367
9368         if (with_spread) {
9369                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9370                 tmp &= ~SBI_SSCCTL_PATHALT;
9371                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9372
9373                 if (with_fdi) {
9374                         lpt_reset_fdi_mphy(dev_priv);
9375                         lpt_program_fdi_mphy(dev_priv);
9376                 }
9377         }
9378
9379         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9380         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9381         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9382         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9383
9384         mutex_unlock(&dev_priv->sb_lock);
9385 }
9386
9387 /* Sequence to disable CLKOUT_DP */
9388 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9389 {
9390         u32 reg, tmp;
9391
9392         mutex_lock(&dev_priv->sb_lock);
9393
9394         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9395         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9396         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9397         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9398
9399         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9400         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9401                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9402                         tmp |= SBI_SSCCTL_PATHALT;
9403                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9404                         udelay(32);
9405                 }
9406                 tmp |= SBI_SSCCTL_DISABLE;
9407                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9408         }
9409
9410         mutex_unlock(&dev_priv->sb_lock);
9411 }
9412
9413 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9414
9415 static const u16 sscdivintphase[] = {
9416         [BEND_IDX( 50)] = 0x3B23,
9417         [BEND_IDX( 45)] = 0x3B23,
9418         [BEND_IDX( 40)] = 0x3C23,
9419         [BEND_IDX( 35)] = 0x3C23,
9420         [BEND_IDX( 30)] = 0x3D23,
9421         [BEND_IDX( 25)] = 0x3D23,
9422         [BEND_IDX( 20)] = 0x3E23,
9423         [BEND_IDX( 15)] = 0x3E23,
9424         [BEND_IDX( 10)] = 0x3F23,
9425         [BEND_IDX(  5)] = 0x3F23,
9426         [BEND_IDX(  0)] = 0x0025,
9427         [BEND_IDX( -5)] = 0x0025,
9428         [BEND_IDX(-10)] = 0x0125,
9429         [BEND_IDX(-15)] = 0x0125,
9430         [BEND_IDX(-20)] = 0x0225,
9431         [BEND_IDX(-25)] = 0x0225,
9432         [BEND_IDX(-30)] = 0x0325,
9433         [BEND_IDX(-35)] = 0x0325,
9434         [BEND_IDX(-40)] = 0x0425,
9435         [BEND_IDX(-45)] = 0x0425,
9436         [BEND_IDX(-50)] = 0x0525,
9437 };
9438
9439 /*
9440  * Bend CLKOUT_DP
9441  * steps -50 to 50 inclusive, in steps of 5
9442  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9443  * change in clock period = -(steps / 10) * 5.787 ps
9444  */
9445 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9446 {
9447         u32 tmp;
9448         int idx = BEND_IDX(steps);
9449
9450         if (WARN_ON(steps % 5 != 0))
9451                 return;
9452
9453         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9454                 return;
9455
9456         mutex_lock(&dev_priv->sb_lock);
9457
9458         if (steps % 10 != 0)
9459                 tmp = 0xAAAAAAAB;
9460         else
9461                 tmp = 0x00000000;
9462         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9463
9464         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9465         tmp &= 0xffff0000;
9466         tmp |= sscdivintphase[idx];
9467         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9468
9469         mutex_unlock(&dev_priv->sb_lock);
9470 }
9471
9472 #undef BEND_IDX
9473
9474 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9475 {
9476         u32 fuse_strap = I915_READ(FUSE_STRAP);
9477         u32 ctl = I915_READ(SPLL_CTL);
9478
9479         if ((ctl & SPLL_PLL_ENABLE) == 0)
9480                 return false;
9481
9482         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9483             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9484                 return true;
9485
9486         if (IS_BROADWELL(dev_priv) &&
9487             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9488                 return true;
9489
9490         return false;
9491 }
9492
9493 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9494                                enum intel_dpll_id id)
9495 {
9496         u32 fuse_strap = I915_READ(FUSE_STRAP);
9497         u32 ctl = I915_READ(WRPLL_CTL(id));
9498
9499         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9500                 return false;
9501
9502         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9503                 return true;
9504
9505         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9506             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9507             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9508                 return true;
9509
9510         return false;
9511 }
9512
9513 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9514 {
9515         struct intel_encoder *encoder;
9516         bool has_fdi = false;
9517
9518         for_each_intel_encoder(&dev_priv->drm, encoder) {
9519                 switch (encoder->type) {
9520                 case INTEL_OUTPUT_ANALOG:
9521                         has_fdi = true;
9522                         break;
9523                 default:
9524                         break;
9525                 }
9526         }
9527
9528         /*
9529          * The BIOS may have decided to use the PCH SSC
9530          * reference so we must not disable it until the
9531          * relevant PLLs have stopped relying on it. We'll
9532          * just leave the PCH SSC reference enabled in case
9533          * any active PLL is using it. It will get disabled
9534          * after runtime suspend if we don't have FDI.
9535          *
9536          * TODO: Move the whole reference clock handling
9537          * to the modeset sequence proper so that we can
9538          * actually enable/disable/reconfigure these things
9539          * safely. To do that we need to introduce a real
9540          * clock hierarchy. That would also allow us to do
9541          * clock bending finally.
9542          */
9543         dev_priv->pch_ssc_use = 0;
9544
9545         if (spll_uses_pch_ssc(dev_priv)) {
9546                 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9547                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9548         }
9549
9550         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9551                 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9552                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9553         }
9554
9555         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9556                 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9557                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9558         }
9559
9560         if (dev_priv->pch_ssc_use)
9561                 return;
9562
9563         if (has_fdi) {
9564                 lpt_bend_clkout_dp(dev_priv, 0);
9565                 lpt_enable_clkout_dp(dev_priv, true, true);
9566         } else {
9567                 lpt_disable_clkout_dp(dev_priv);
9568         }
9569 }
9570
9571 /*
9572  * Initialize reference clocks when the driver loads
9573  */
9574 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9575 {
9576         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9577                 ironlake_init_pch_refclk(dev_priv);
9578         else if (HAS_PCH_LPT(dev_priv))
9579                 lpt_init_pch_refclk(dev_priv);
9580 }
9581
9582 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9583 {
9584         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9585         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9586         enum pipe pipe = crtc->pipe;
9587         u32 val;
9588
9589         val = 0;
9590
9591         switch (crtc_state->pipe_bpp) {
9592         case 18:
9593                 val |= PIPECONF_6BPC;
9594                 break;
9595         case 24:
9596                 val |= PIPECONF_8BPC;
9597                 break;
9598         case 30:
9599                 val |= PIPECONF_10BPC;
9600                 break;
9601         case 36:
9602                 val |= PIPECONF_12BPC;
9603                 break;
9604         default:
9605                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9606                 BUG();
9607         }
9608
9609         if (crtc_state->dither)
9610                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9611
9612         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9613                 val |= PIPECONF_INTERLACED_ILK;
9614         else
9615                 val |= PIPECONF_PROGRESSIVE;
9616
9617         /*
9618          * This would end up with an odd purple hue over
9619          * the entire display. Make sure we don't do it.
9620          */
9621         WARN_ON(crtc_state->limited_color_range &&
9622                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
9623
9624         if (crtc_state->limited_color_range)
9625                 val |= PIPECONF_COLOR_RANGE_SELECT;
9626
9627         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9628                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
9629
9630         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9631
9632         val |= PIPECONF_FRAME_START_DELAY(0);
9633
9634         I915_WRITE(PIPECONF(pipe), val);
9635         POSTING_READ(PIPECONF(pipe));
9636 }
9637
9638 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9639 {
9640         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9641         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9642         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9643         u32 val = 0;
9644
9645         if (IS_HASWELL(dev_priv) && crtc_state->dither)
9646                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9647
9648         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9649                 val |= PIPECONF_INTERLACED_ILK;
9650         else
9651                 val |= PIPECONF_PROGRESSIVE;
9652
9653         if (IS_HASWELL(dev_priv) &&
9654             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9655                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
9656
9657         I915_WRITE(PIPECONF(cpu_transcoder), val);
9658         POSTING_READ(PIPECONF(cpu_transcoder));
9659 }
9660
9661 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9662 {
9663         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9665         u32 val = 0;
9666
9667         switch (crtc_state->pipe_bpp) {
9668         case 18:
9669                 val |= PIPEMISC_DITHER_6_BPC;
9670                 break;
9671         case 24:
9672                 val |= PIPEMISC_DITHER_8_BPC;
9673                 break;
9674         case 30:
9675                 val |= PIPEMISC_DITHER_10_BPC;
9676                 break;
9677         case 36:
9678                 val |= PIPEMISC_DITHER_12_BPC;
9679                 break;
9680         default:
9681                 MISSING_CASE(crtc_state->pipe_bpp);
9682                 break;
9683         }
9684
9685         if (crtc_state->dither)
9686                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9687
9688         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9689             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9690                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9691
9692         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9693                 val |= PIPEMISC_YUV420_ENABLE |
9694                         PIPEMISC_YUV420_MODE_FULL_BLEND;
9695
9696         if (INTEL_GEN(dev_priv) >= 11 &&
9697             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9698                                            BIT(PLANE_CURSOR))) == 0)
9699                 val |= PIPEMISC_HDR_MODE_PRECISION;
9700
9701         I915_WRITE(PIPEMISC(crtc->pipe), val);
9702 }
9703
9704 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9705 {
9706         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9707         u32 tmp;
9708
9709         tmp = I915_READ(PIPEMISC(crtc->pipe));
9710
9711         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9712         case PIPEMISC_DITHER_6_BPC:
9713                 return 18;
9714         case PIPEMISC_DITHER_8_BPC:
9715                 return 24;
9716         case PIPEMISC_DITHER_10_BPC:
9717                 return 30;
9718         case PIPEMISC_DITHER_12_BPC:
9719                 return 36;
9720         default:
9721                 MISSING_CASE(tmp);
9722                 return 0;
9723         }
9724 }
9725
9726 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9727 {
9728         /*
9729          * Account for spread spectrum to avoid
9730          * oversubscribing the link. Max center spread
9731          * is 2.5%; use 5% for safety's sake.
9732          */
9733         u32 bps = target_clock * bpp * 21 / 20;
9734         return DIV_ROUND_UP(bps, link_bw * 8);
9735 }
9736
9737 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9738 {
9739         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9740 }
9741
9742 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9743                                   struct intel_crtc_state *crtc_state,
9744                                   struct dpll *reduced_clock)
9745 {
9746         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9747         u32 dpll, fp, fp2;
9748         int factor;
9749
9750         /* Enable autotuning of the PLL clock (if permissible) */
9751         factor = 21;
9752         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9753                 if ((intel_panel_use_ssc(dev_priv) &&
9754                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9755                     (HAS_PCH_IBX(dev_priv) &&
9756                      intel_is_dual_link_lvds(dev_priv)))
9757                         factor = 25;
9758         } else if (crtc_state->sdvo_tv_clock) {
9759                 factor = 20;
9760         }
9761
9762         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9763
9764         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9765                 fp |= FP_CB_TUNE;
9766
9767         if (reduced_clock) {
9768                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9769
9770                 if (reduced_clock->m < factor * reduced_clock->n)
9771                         fp2 |= FP_CB_TUNE;
9772         } else {
9773                 fp2 = fp;
9774         }
9775
9776         dpll = 0;
9777
9778         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9779                 dpll |= DPLLB_MODE_LVDS;
9780         else
9781                 dpll |= DPLLB_MODE_DAC_SERIAL;
9782
9783         dpll |= (crtc_state->pixel_multiplier - 1)
9784                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9785
9786         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9787             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9788                 dpll |= DPLL_SDVO_HIGH_SPEED;
9789
9790         if (intel_crtc_has_dp_encoder(crtc_state))
9791                 dpll |= DPLL_SDVO_HIGH_SPEED;
9792
9793         /*
9794          * The high speed IO clock is only really required for
9795          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9796          * possible to share the DPLL between CRT and HDMI. Enabling
9797          * the clock needlessly does no real harm, except use up a
9798          * bit of power potentially.
9799          *
9800          * We'll limit this to IVB with 3 pipes, since it has only two
9801          * DPLLs and so DPLL sharing is the only way to get three pipes
9802          * driving PCH ports at the same time. On SNB we could do this,
9803          * and potentially avoid enabling the second DPLL, but it's not
9804          * clear if it''s a win or loss power wise. No point in doing
9805          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9806          */
9807         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
9808             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9809                 dpll |= DPLL_SDVO_HIGH_SPEED;
9810
9811         /* compute bitmask from p1 value */
9812         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9813         /* also FPA1 */
9814         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9815
9816         switch (crtc_state->dpll.p2) {
9817         case 5:
9818                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9819                 break;
9820         case 7:
9821                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9822                 break;
9823         case 10:
9824                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9825                 break;
9826         case 14:
9827                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9828                 break;
9829         }
9830
9831         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9832             intel_panel_use_ssc(dev_priv))
9833                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9834         else
9835                 dpll |= PLL_REF_INPUT_DREFCLK;
9836
9837         dpll |= DPLL_VCO_ENABLE;
9838
9839         crtc_state->dpll_hw_state.dpll = dpll;
9840         crtc_state->dpll_hw_state.fp0 = fp;
9841         crtc_state->dpll_hw_state.fp1 = fp2;
9842 }
9843
9844 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9845                                        struct intel_crtc_state *crtc_state)
9846 {
9847         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9848         struct intel_atomic_state *state =
9849                 to_intel_atomic_state(crtc_state->uapi.state);
9850         const struct intel_limit *limit;
9851         int refclk = 120000;
9852
9853         memset(&crtc_state->dpll_hw_state, 0,
9854                sizeof(crtc_state->dpll_hw_state));
9855
9856         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9857         if (!crtc_state->has_pch_encoder)
9858                 return 0;
9859
9860         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9861                 if (intel_panel_use_ssc(dev_priv)) {
9862                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9863                                       dev_priv->vbt.lvds_ssc_freq);
9864                         refclk = dev_priv->vbt.lvds_ssc_freq;
9865                 }
9866
9867                 if (intel_is_dual_link_lvds(dev_priv)) {
9868                         if (refclk == 100000)
9869                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9870                         else
9871                                 limit = &intel_limits_ironlake_dual_lvds;
9872                 } else {
9873                         if (refclk == 100000)
9874                                 limit = &intel_limits_ironlake_single_lvds_100m;
9875                         else
9876                                 limit = &intel_limits_ironlake_single_lvds;
9877                 }
9878         } else {
9879                 limit = &intel_limits_ironlake_dac;
9880         }
9881
9882         if (!crtc_state->clock_set &&
9883             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9884                                 refclk, NULL, &crtc_state->dpll)) {
9885                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9886                 return -EINVAL;
9887         }
9888
9889         ironlake_compute_dpll(crtc, crtc_state, NULL);
9890
9891         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9892                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9893                               pipe_name(crtc->pipe));
9894                 return -EINVAL;
9895         }
9896
9897         return 0;
9898 }
9899
9900 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9901                                          struct intel_link_m_n *m_n)
9902 {
9903         struct drm_device *dev = crtc->base.dev;
9904         struct drm_i915_private *dev_priv = to_i915(dev);
9905         enum pipe pipe = crtc->pipe;
9906
9907         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9908         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9909         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9910                 & ~TU_SIZE_MASK;
9911         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9912         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9913                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9914 }
9915
9916 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9917                                          enum transcoder transcoder,
9918                                          struct intel_link_m_n *m_n,
9919                                          struct intel_link_m_n *m2_n2)
9920 {
9921         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9922         enum pipe pipe = crtc->pipe;
9923
9924         if (INTEL_GEN(dev_priv) >= 5) {
9925                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9926                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9927                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9928                         & ~TU_SIZE_MASK;
9929                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9930                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9931                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9932
9933                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9934                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9935                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9936                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9937                                         & ~TU_SIZE_MASK;
9938                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9939                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9940                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9941                 }
9942         } else {
9943                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9944                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9945                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9946                         & ~TU_SIZE_MASK;
9947                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9948                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9949                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9950         }
9951 }
9952
9953 void intel_dp_get_m_n(struct intel_crtc *crtc,
9954                       struct intel_crtc_state *pipe_config)
9955 {
9956         if (pipe_config->has_pch_encoder)
9957                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9958         else
9959                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9960                                              &pipe_config->dp_m_n,
9961                                              &pipe_config->dp_m2_n2);
9962 }
9963
9964 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9965                                         struct intel_crtc_state *pipe_config)
9966 {
9967         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9968                                      &pipe_config->fdi_m_n, NULL);
9969 }
9970
9971 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9972                                     struct intel_crtc_state *pipe_config)
9973 {
9974         struct drm_device *dev = crtc->base.dev;
9975         struct drm_i915_private *dev_priv = to_i915(dev);
9976         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9977         u32 ps_ctrl = 0;
9978         int id = -1;
9979         int i;
9980
9981         /* find scaler attached to this pipe */
9982         for (i = 0; i < crtc->num_scalers; i++) {
9983                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9984                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9985                         id = i;
9986                         pipe_config->pch_pfit.enabled = true;
9987                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9988                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9989                         scaler_state->scalers[i].in_use = true;
9990                         break;
9991                 }
9992         }
9993
9994         scaler_state->scaler_id = id;
9995         if (id >= 0) {
9996                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9997         } else {
9998                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9999         }
10000 }
10001
10002 static void
10003 skylake_get_initial_plane_config(struct intel_crtc *crtc,
10004                                  struct intel_initial_plane_config *plane_config)
10005 {
10006         struct drm_device *dev = crtc->base.dev;
10007         struct drm_i915_private *dev_priv = to_i915(dev);
10008         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10009         enum plane_id plane_id = plane->id;
10010         enum pipe pipe;
10011         u32 val, base, offset, stride_mult, tiling, alpha;
10012         int fourcc, pixel_format;
10013         unsigned int aligned_height;
10014         struct drm_framebuffer *fb;
10015         struct intel_framebuffer *intel_fb;
10016
10017         if (!plane->get_hw_state(plane, &pipe))
10018                 return;
10019
10020         WARN_ON(pipe != crtc->pipe);
10021
10022         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10023         if (!intel_fb) {
10024                 DRM_DEBUG_KMS("failed to alloc fb\n");
10025                 return;
10026         }
10027
10028         fb = &intel_fb->base;
10029
10030         fb->dev = dev;
10031
10032         val = I915_READ(PLANE_CTL(pipe, plane_id));
10033
10034         if (INTEL_GEN(dev_priv) >= 11)
10035                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10036         else
10037                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10038
10039         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10040                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
10041                 alpha &= PLANE_COLOR_ALPHA_MASK;
10042         } else {
10043                 alpha = val & PLANE_CTL_ALPHA_MASK;
10044         }
10045
10046         fourcc = skl_format_to_fourcc(pixel_format,
10047                                       val & PLANE_CTL_ORDER_RGBX, alpha);
10048         fb->format = drm_format_info(fourcc);
10049
10050         tiling = val & PLANE_CTL_TILED_MASK;
10051         switch (tiling) {
10052         case PLANE_CTL_TILED_LINEAR:
10053                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10054                 break;
10055         case PLANE_CTL_TILED_X:
10056                 plane_config->tiling = I915_TILING_X;
10057                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10058                 break;
10059         case PLANE_CTL_TILED_Y:
10060                 plane_config->tiling = I915_TILING_Y;
10061                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10062                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
10063                 else
10064                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10065                 break;
10066         case PLANE_CTL_TILED_YF:
10067                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10068                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10069                 else
10070                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10071                 break;
10072         default:
10073                 MISSING_CASE(tiling);
10074                 goto error;
10075         }
10076
10077         /*
10078          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10079          * while i915 HW rotation is clockwise, thats why this swapping.
10080          */
10081         switch (val & PLANE_CTL_ROTATE_MASK) {
10082         case PLANE_CTL_ROTATE_0:
10083                 plane_config->rotation = DRM_MODE_ROTATE_0;
10084                 break;
10085         case PLANE_CTL_ROTATE_90:
10086                 plane_config->rotation = DRM_MODE_ROTATE_270;
10087                 break;
10088         case PLANE_CTL_ROTATE_180:
10089                 plane_config->rotation = DRM_MODE_ROTATE_180;
10090                 break;
10091         case PLANE_CTL_ROTATE_270:
10092                 plane_config->rotation = DRM_MODE_ROTATE_90;
10093                 break;
10094         }
10095
10096         if (INTEL_GEN(dev_priv) >= 10 &&
10097             val & PLANE_CTL_FLIP_HORIZONTAL)
10098                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10099
10100         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10101         plane_config->base = base;
10102
10103         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
10104
10105         val = I915_READ(PLANE_SIZE(pipe, plane_id));
10106         fb->height = ((val >> 16) & 0xffff) + 1;
10107         fb->width = ((val >> 0) & 0xffff) + 1;
10108
10109         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
10110         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10111         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10112
10113         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10114
10115         plane_config->size = fb->pitches[0] * aligned_height;
10116
10117         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10118                       crtc->base.name, plane->base.name, fb->width, fb->height,
10119                       fb->format->cpp[0] * 8, base, fb->pitches[0],
10120                       plane_config->size);
10121
10122         plane_config->fb = intel_fb;
10123         return;
10124
10125 error:
10126         kfree(intel_fb);
10127 }
10128
10129 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
10130                                      struct intel_crtc_state *pipe_config)
10131 {
10132         struct drm_device *dev = crtc->base.dev;
10133         struct drm_i915_private *dev_priv = to_i915(dev);
10134         u32 tmp;
10135
10136         tmp = I915_READ(PF_CTL(crtc->pipe));
10137
10138         if (tmp & PF_ENABLE) {
10139                 pipe_config->pch_pfit.enabled = true;
10140                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
10141                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
10142
10143                 /* We currently do not free assignements of panel fitters on
10144                  * ivb/hsw (since we don't use the higher upscaling modes which
10145                  * differentiates them) so just WARN about this case for now. */
10146                 if (IS_GEN(dev_priv, 7)) {
10147                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
10148                                 PF_PIPE_SEL_IVB(crtc->pipe));
10149                 }
10150         }
10151 }
10152
10153 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
10154                                      struct intel_crtc_state *pipe_config)
10155 {
10156         struct drm_device *dev = crtc->base.dev;
10157         struct drm_i915_private *dev_priv = to_i915(dev);
10158         enum intel_display_power_domain power_domain;
10159         intel_wakeref_t wakeref;
10160         u32 tmp;
10161         bool ret;
10162
10163         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10164         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10165         if (!wakeref)
10166                 return false;
10167
10168         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10169         pipe_config->shared_dpll = NULL;
10170         pipe_config->master_transcoder = INVALID_TRANSCODER;
10171
10172         ret = false;
10173         tmp = I915_READ(PIPECONF(crtc->pipe));
10174         if (!(tmp & PIPECONF_ENABLE))
10175                 goto out;
10176
10177         switch (tmp & PIPECONF_BPC_MASK) {
10178         case PIPECONF_6BPC:
10179                 pipe_config->pipe_bpp = 18;
10180                 break;
10181         case PIPECONF_8BPC:
10182                 pipe_config->pipe_bpp = 24;
10183                 break;
10184         case PIPECONF_10BPC:
10185                 pipe_config->pipe_bpp = 30;
10186                 break;
10187         case PIPECONF_12BPC:
10188                 pipe_config->pipe_bpp = 36;
10189                 break;
10190         default:
10191                 break;
10192         }
10193
10194         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10195                 pipe_config->limited_color_range = true;
10196
10197         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10198         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10199         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10200                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10201                 break;
10202         default:
10203                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10204                 break;
10205         }
10206
10207         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10208                 PIPECONF_GAMMA_MODE_SHIFT;
10209
10210         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10211
10212         i9xx_get_pipe_color_config(pipe_config);
10213         intel_color_get_config(pipe_config);
10214
10215         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10216                 struct intel_shared_dpll *pll;
10217                 enum intel_dpll_id pll_id;
10218
10219                 pipe_config->has_pch_encoder = true;
10220
10221                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
10222                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10223                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10224
10225                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10226
10227                 if (HAS_PCH_IBX(dev_priv)) {
10228                         /*
10229                          * The pipe->pch transcoder and pch transcoder->pll
10230                          * mapping is fixed.
10231                          */
10232                         pll_id = (enum intel_dpll_id) crtc->pipe;
10233                 } else {
10234                         tmp = I915_READ(PCH_DPLL_SEL);
10235                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10236                                 pll_id = DPLL_ID_PCH_PLL_B;
10237                         else
10238                                 pll_id= DPLL_ID_PCH_PLL_A;
10239                 }
10240
10241                 pipe_config->shared_dpll =
10242                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10243                 pll = pipe_config->shared_dpll;
10244
10245                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10246                                                 &pipe_config->dpll_hw_state));
10247
10248                 tmp = pipe_config->dpll_hw_state.dpll;
10249                 pipe_config->pixel_multiplier =
10250                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10251                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10252
10253                 ironlake_pch_clock_get(crtc, pipe_config);
10254         } else {
10255                 pipe_config->pixel_multiplier = 1;
10256         }
10257
10258         intel_get_pipe_timings(crtc, pipe_config);
10259         intel_get_pipe_src_size(crtc, pipe_config);
10260
10261         ironlake_get_pfit_config(crtc, pipe_config);
10262
10263         ret = true;
10264
10265 out:
10266         intel_display_power_put(dev_priv, power_domain, wakeref);
10267
10268         return ret;
10269 }
10270 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10271                                       struct intel_crtc_state *crtc_state)
10272 {
10273         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10274         struct intel_atomic_state *state =
10275                 to_intel_atomic_state(crtc_state->uapi.state);
10276
10277         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10278             INTEL_GEN(dev_priv) >= 11) {
10279                 struct intel_encoder *encoder =
10280                         intel_get_crtc_new_encoder(state, crtc_state);
10281
10282                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10283                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10284                                       pipe_name(crtc->pipe));
10285                         return -EINVAL;
10286                 }
10287         }
10288
10289         return 0;
10290 }
10291
10292 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10293                                    enum port port,
10294                                    struct intel_crtc_state *pipe_config)
10295 {
10296         enum intel_dpll_id id;
10297         u32 temp;
10298
10299         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10300         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10301
10302         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10303                 return;
10304
10305         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10306 }
10307
10308 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10309                                 enum port port,
10310                                 struct intel_crtc_state *pipe_config)
10311 {
10312         enum phy phy = intel_port_to_phy(dev_priv, port);
10313         enum icl_port_dpll_id port_dpll_id;
10314         enum intel_dpll_id id;
10315         u32 temp;
10316
10317         if (intel_phy_is_combo(dev_priv, phy)) {
10318                 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10319                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10320                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10321                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10322         } else if (intel_phy_is_tc(dev_priv, phy)) {
10323                 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10324
10325                 if (clk_sel == DDI_CLK_SEL_MG) {
10326                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10327                                                                     port));
10328                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10329                 } else {
10330                         WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10331                         id = DPLL_ID_ICL_TBTPLL;
10332                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10333                 }
10334         } else {
10335                 WARN(1, "Invalid port %x\n", port);
10336                 return;
10337         }
10338
10339         pipe_config->icl_port_dplls[port_dpll_id].pll =
10340                 intel_get_shared_dpll_by_id(dev_priv, id);
10341
10342         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10343 }
10344
10345 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10346                                 enum port port,
10347                                 struct intel_crtc_state *pipe_config)
10348 {
10349         enum intel_dpll_id id;
10350
10351         switch (port) {
10352         case PORT_A:
10353                 id = DPLL_ID_SKL_DPLL0;
10354                 break;
10355         case PORT_B:
10356                 id = DPLL_ID_SKL_DPLL1;
10357                 break;
10358         case PORT_C:
10359                 id = DPLL_ID_SKL_DPLL2;
10360                 break;
10361         default:
10362                 DRM_ERROR("Incorrect port type\n");
10363                 return;
10364         }
10365
10366         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10367 }
10368
10369 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10370                                 enum port port,
10371                                 struct intel_crtc_state *pipe_config)
10372 {
10373         enum intel_dpll_id id;
10374         u32 temp;
10375
10376         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10377         id = temp >> (port * 3 + 1);
10378
10379         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10380                 return;
10381
10382         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10383 }
10384
10385 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10386                                 enum port port,
10387                                 struct intel_crtc_state *pipe_config)
10388 {
10389         enum intel_dpll_id id;
10390         u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10391
10392         switch (ddi_pll_sel) {
10393         case PORT_CLK_SEL_WRPLL1:
10394                 id = DPLL_ID_WRPLL1;
10395                 break;
10396         case PORT_CLK_SEL_WRPLL2:
10397                 id = DPLL_ID_WRPLL2;
10398                 break;
10399         case PORT_CLK_SEL_SPLL:
10400                 id = DPLL_ID_SPLL;
10401                 break;
10402         case PORT_CLK_SEL_LCPLL_810:
10403                 id = DPLL_ID_LCPLL_810;
10404                 break;
10405         case PORT_CLK_SEL_LCPLL_1350:
10406                 id = DPLL_ID_LCPLL_1350;
10407                 break;
10408         case PORT_CLK_SEL_LCPLL_2700:
10409                 id = DPLL_ID_LCPLL_2700;
10410                 break;
10411         default:
10412                 MISSING_CASE(ddi_pll_sel);
10413                 /* fall through */
10414         case PORT_CLK_SEL_NONE:
10415                 return;
10416         }
10417
10418         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10419 }
10420
10421 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10422                                      struct intel_crtc_state *pipe_config,
10423                                      u64 *power_domain_mask,
10424                                      intel_wakeref_t *wakerefs)
10425 {
10426         struct drm_device *dev = crtc->base.dev;
10427         struct drm_i915_private *dev_priv = to_i915(dev);
10428         enum intel_display_power_domain power_domain;
10429         unsigned long panel_transcoder_mask = 0;
10430         unsigned long enabled_panel_transcoders = 0;
10431         enum transcoder panel_transcoder;
10432         intel_wakeref_t wf;
10433         u32 tmp;
10434
10435         if (INTEL_GEN(dev_priv) >= 11)
10436                 panel_transcoder_mask |=
10437                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10438
10439         if (HAS_TRANSCODER_EDP(dev_priv))
10440                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10441
10442         /*
10443          * The pipe->transcoder mapping is fixed with the exception of the eDP
10444          * and DSI transcoders handled below.
10445          */
10446         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10447
10448         /*
10449          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10450          * consistency and less surprising code; it's in always on power).
10451          */
10452         for_each_set_bit(panel_transcoder,
10453                          &panel_transcoder_mask,
10454                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10455                 bool force_thru = false;
10456                 enum pipe trans_pipe;
10457
10458                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10459                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10460                         continue;
10461
10462                 /*
10463                  * Log all enabled ones, only use the first one.
10464                  *
10465                  * FIXME: This won't work for two separate DSI displays.
10466                  */
10467                 enabled_panel_transcoders |= BIT(panel_transcoder);
10468                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10469                         continue;
10470
10471                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10472                 default:
10473                         WARN(1, "unknown pipe linked to transcoder %s\n",
10474                              transcoder_name(panel_transcoder));
10475                         /* fall through */
10476                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10477                         force_thru = true;
10478                         /* fall through */
10479                 case TRANS_DDI_EDP_INPUT_A_ON:
10480                         trans_pipe = PIPE_A;
10481                         break;
10482                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10483                         trans_pipe = PIPE_B;
10484                         break;
10485                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10486                         trans_pipe = PIPE_C;
10487                         break;
10488                 }
10489
10490                 if (trans_pipe == crtc->pipe) {
10491                         pipe_config->cpu_transcoder = panel_transcoder;
10492                         pipe_config->pch_pfit.force_thru = force_thru;
10493                 }
10494         }
10495
10496         /*
10497          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10498          */
10499         WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10500                 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10501
10502         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10503         WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10504
10505         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10506         if (!wf)
10507                 return false;
10508
10509         wakerefs[power_domain] = wf;
10510         *power_domain_mask |= BIT_ULL(power_domain);
10511
10512         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10513
10514         return tmp & PIPECONF_ENABLE;
10515 }
10516
10517 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10518                                          struct intel_crtc_state *pipe_config,
10519                                          u64 *power_domain_mask,
10520                                          intel_wakeref_t *wakerefs)
10521 {
10522         struct drm_device *dev = crtc->base.dev;
10523         struct drm_i915_private *dev_priv = to_i915(dev);
10524         enum intel_display_power_domain power_domain;
10525         enum transcoder cpu_transcoder;
10526         intel_wakeref_t wf;
10527         enum port port;
10528         u32 tmp;
10529
10530         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10531                 if (port == PORT_A)
10532                         cpu_transcoder = TRANSCODER_DSI_A;
10533                 else
10534                         cpu_transcoder = TRANSCODER_DSI_C;
10535
10536                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10537                 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10538
10539                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10540                 if (!wf)
10541                         continue;
10542
10543                 wakerefs[power_domain] = wf;
10544                 *power_domain_mask |= BIT_ULL(power_domain);
10545
10546                 /*
10547                  * The PLL needs to be enabled with a valid divider
10548                  * configuration, otherwise accessing DSI registers will hang
10549                  * the machine. See BSpec North Display Engine
10550                  * registers/MIPI[BXT]. We can break out here early, since we
10551                  * need the same DSI PLL to be enabled for both DSI ports.
10552                  */
10553                 if (!bxt_dsi_pll_is_enabled(dev_priv))
10554                         break;
10555
10556                 /* XXX: this works for video mode only */
10557                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10558                 if (!(tmp & DPI_ENABLE))
10559                         continue;
10560
10561                 tmp = I915_READ(MIPI_CTRL(port));
10562                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10563                         continue;
10564
10565                 pipe_config->cpu_transcoder = cpu_transcoder;
10566                 break;
10567         }
10568
10569         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10570 }
10571
10572 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10573                                        struct intel_crtc_state *pipe_config)
10574 {
10575         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10576         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
10577         struct intel_shared_dpll *pll;
10578         enum port port;
10579         u32 tmp;
10580
10581         if (transcoder_is_dsi(cpu_transcoder)) {
10582                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
10583                                                 PORT_A : PORT_B;
10584         } else {
10585                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
10586                 if (INTEL_GEN(dev_priv) >= 12)
10587                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10588                 else
10589                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10590         }
10591
10592         if (INTEL_GEN(dev_priv) >= 11)
10593                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10594         else if (IS_CANNONLAKE(dev_priv))
10595                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10596         else if (IS_GEN9_BC(dev_priv))
10597                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10598         else if (IS_GEN9_LP(dev_priv))
10599                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10600         else
10601                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10602
10603         pll = pipe_config->shared_dpll;
10604         if (pll) {
10605                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10606                                                 &pipe_config->dpll_hw_state));
10607         }
10608
10609         /*
10610          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10611          * DDI E. So just check whether this pipe is wired to DDI E and whether
10612          * the PCH transcoder is on.
10613          */
10614         if (INTEL_GEN(dev_priv) < 9 &&
10615             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10616                 pipe_config->has_pch_encoder = true;
10617
10618                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10619                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10620                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10621
10622                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10623         }
10624 }
10625
10626 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
10627                                                  enum transcoder cpu_transcoder)
10628 {
10629         u32 trans_port_sync, master_select;
10630
10631         trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
10632
10633         if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
10634                 return INVALID_TRANSCODER;
10635
10636         master_select = trans_port_sync &
10637                         PORT_SYNC_MODE_MASTER_SELECT_MASK;
10638         if (master_select == 0)
10639                 return TRANSCODER_EDP;
10640         else
10641                 return master_select - 1;
10642 }
10643
10644 static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
10645 {
10646         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
10647         u32 transcoders;
10648         enum transcoder cpu_transcoder;
10649
10650         crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
10651                                                                   crtc_state->cpu_transcoder);
10652
10653         transcoders = BIT(TRANSCODER_A) |
10654                 BIT(TRANSCODER_B) |
10655                 BIT(TRANSCODER_C) |
10656                 BIT(TRANSCODER_D);
10657         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
10658                 enum intel_display_power_domain power_domain;
10659                 intel_wakeref_t trans_wakeref;
10660
10661                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10662                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
10663                                                                    power_domain);
10664
10665                 if (!trans_wakeref)
10666                         continue;
10667
10668                 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
10669                     crtc_state->cpu_transcoder)
10670                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
10671
10672                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
10673         }
10674
10675         WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
10676                 crtc_state->sync_mode_slaves_mask);
10677 }
10678
10679 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10680                                     struct intel_crtc_state *pipe_config)
10681 {
10682         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10683         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10684         enum intel_display_power_domain power_domain;
10685         u64 power_domain_mask;
10686         bool active;
10687
10688         intel_crtc_init_scalers(crtc, pipe_config);
10689
10690         pipe_config->master_transcoder = INVALID_TRANSCODER;
10691
10692         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10693         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10694         if (!wf)
10695                 return false;
10696
10697         wakerefs[power_domain] = wf;
10698         power_domain_mask = BIT_ULL(power_domain);
10699
10700         pipe_config->shared_dpll = NULL;
10701
10702         active = hsw_get_transcoder_state(crtc, pipe_config,
10703                                           &power_domain_mask, wakerefs);
10704
10705         if (IS_GEN9_LP(dev_priv) &&
10706             bxt_get_dsi_transcoder_state(crtc, pipe_config,
10707                                          &power_domain_mask, wakerefs)) {
10708                 WARN_ON(active);
10709                 active = true;
10710         }
10711
10712         if (!active)
10713                 goto out;
10714
10715         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10716             INTEL_GEN(dev_priv) >= 11) {
10717                 haswell_get_ddi_port_state(crtc, pipe_config);
10718                 intel_get_pipe_timings(crtc, pipe_config);
10719         }
10720
10721         intel_get_pipe_src_size(crtc, pipe_config);
10722
10723         if (IS_HASWELL(dev_priv)) {
10724                 u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10725
10726                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
10727                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10728                 else
10729                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10730         } else {
10731                 pipe_config->output_format =
10732                         bdw_get_pipemisc_output_format(crtc);
10733
10734                 /*
10735                  * Currently there is no interface defined to
10736                  * check user preference between RGB/YCBCR444
10737                  * or YCBCR420. So the only possible case for
10738                  * YCBCR444 usage is driving YCBCR420 output
10739                  * with LSPCON, when pipe is configured for
10740                  * YCBCR444 output and LSPCON takes care of
10741                  * downsampling it.
10742                  */
10743                 pipe_config->lspcon_downsampling =
10744                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
10745         }
10746
10747         pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10748
10749         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10750
10751         if (INTEL_GEN(dev_priv) >= 9) {
10752                 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10753
10754                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10755                         pipe_config->gamma_enable = true;
10756
10757                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10758                         pipe_config->csc_enable = true;
10759         } else {
10760                 i9xx_get_pipe_color_config(pipe_config);
10761         }
10762
10763         intel_color_get_config(pipe_config);
10764
10765         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10766         WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10767
10768         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10769         if (wf) {
10770                 wakerefs[power_domain] = wf;
10771                 power_domain_mask |= BIT_ULL(power_domain);
10772
10773                 if (INTEL_GEN(dev_priv) >= 9)
10774                         skylake_get_pfit_config(crtc, pipe_config);
10775                 else
10776                         ironlake_get_pfit_config(crtc, pipe_config);
10777         }
10778
10779         if (hsw_crtc_supports_ips(crtc)) {
10780                 if (IS_HASWELL(dev_priv))
10781                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10782                 else {
10783                         /*
10784                          * We cannot readout IPS state on broadwell, set to
10785                          * true so we can set it to a defined state on first
10786                          * commit.
10787                          */
10788                         pipe_config->ips_enabled = true;
10789                 }
10790         }
10791
10792         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10793             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10794                 pipe_config->pixel_multiplier =
10795                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10796         } else {
10797                 pipe_config->pixel_multiplier = 1;
10798         }
10799
10800         if (INTEL_GEN(dev_priv) >= 11 &&
10801             !transcoder_is_dsi(pipe_config->cpu_transcoder))
10802                 icelake_get_trans_port_sync_config(pipe_config);
10803
10804 out:
10805         for_each_power_domain(power_domain, power_domain_mask)
10806                 intel_display_power_put(dev_priv,
10807                                         power_domain, wakerefs[power_domain]);
10808
10809         return active;
10810 }
10811
10812 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10813 {
10814         struct drm_i915_private *dev_priv =
10815                 to_i915(plane_state->uapi.plane->dev);
10816         const struct drm_framebuffer *fb = plane_state->hw.fb;
10817         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10818         u32 base;
10819
10820         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10821                 base = obj->phys_handle->busaddr;
10822         else
10823                 base = intel_plane_ggtt_offset(plane_state);
10824
10825         return base + plane_state->color_plane[0].offset;
10826 }
10827
10828 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10829 {
10830         int x = plane_state->uapi.dst.x1;
10831         int y = plane_state->uapi.dst.y1;
10832         u32 pos = 0;
10833
10834         if (x < 0) {
10835                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10836                 x = -x;
10837         }
10838         pos |= x << CURSOR_X_SHIFT;
10839
10840         if (y < 0) {
10841                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10842                 y = -y;
10843         }
10844         pos |= y << CURSOR_Y_SHIFT;
10845
10846         return pos;
10847 }
10848
10849 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10850 {
10851         const struct drm_mode_config *config =
10852                 &plane_state->uapi.plane->dev->mode_config;
10853         int width = drm_rect_width(&plane_state->uapi.dst);
10854         int height = drm_rect_height(&plane_state->uapi.dst);
10855
10856         return width > 0 && width <= config->cursor_width &&
10857                 height > 0 && height <= config->cursor_height;
10858 }
10859
10860 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10861 {
10862         struct drm_i915_private *dev_priv =
10863                 to_i915(plane_state->uapi.plane->dev);
10864         unsigned int rotation = plane_state->hw.rotation;
10865         int src_x, src_y;
10866         u32 offset;
10867         int ret;
10868
10869         ret = intel_plane_compute_gtt(plane_state);
10870         if (ret)
10871                 return ret;
10872
10873         if (!plane_state->uapi.visible)
10874                 return 0;
10875
10876         src_x = plane_state->uapi.src.x1 >> 16;
10877         src_y = plane_state->uapi.src.y1 >> 16;
10878
10879         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10880         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10881                                                     plane_state, 0);
10882
10883         if (src_x != 0 || src_y != 0) {
10884                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10885                 return -EINVAL;
10886         }
10887
10888         /*
10889          * Put the final coordinates back so that the src
10890          * coordinate checks will see the right values.
10891          */
10892         drm_rect_translate_to(&plane_state->uapi.src,
10893                               src_x << 16, src_y << 16);
10894
10895         /* ILK+ do this automagically in hardware */
10896         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
10897                 const struct drm_framebuffer *fb = plane_state->hw.fb;
10898                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
10899                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
10900
10901                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
10902         }
10903
10904         plane_state->color_plane[0].offset = offset;
10905         plane_state->color_plane[0].x = src_x;
10906         plane_state->color_plane[0].y = src_y;
10907
10908         return 0;
10909 }
10910
10911 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10912                               struct intel_plane_state *plane_state)
10913 {
10914         const struct drm_framebuffer *fb = plane_state->hw.fb;
10915         int ret;
10916
10917         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10918                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10919                 return -EINVAL;
10920         }
10921
10922         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
10923                                                   &crtc_state->uapi,
10924                                                   DRM_PLANE_HELPER_NO_SCALING,
10925                                                   DRM_PLANE_HELPER_NO_SCALING,
10926                                                   true, true);
10927         if (ret)
10928                 return ret;
10929
10930         /* Use the unclipped src/dst rectangles, which we program to hw */
10931         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
10932         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
10933
10934         ret = intel_cursor_check_surface(plane_state);
10935         if (ret)
10936                 return ret;
10937
10938         if (!plane_state->uapi.visible)
10939                 return 0;
10940
10941         ret = intel_plane_check_src_coordinates(plane_state);
10942         if (ret)
10943                 return ret;
10944
10945         return 0;
10946 }
10947
10948 static unsigned int
10949 i845_cursor_max_stride(struct intel_plane *plane,
10950                        u32 pixel_format, u64 modifier,
10951                        unsigned int rotation)
10952 {
10953         return 2048;
10954 }
10955
10956 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10957 {
10958         u32 cntl = 0;
10959
10960         if (crtc_state->gamma_enable)
10961                 cntl |= CURSOR_GAMMA_ENABLE;
10962
10963         return cntl;
10964 }
10965
10966 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10967                            const struct intel_plane_state *plane_state)
10968 {
10969         return CURSOR_ENABLE |
10970                 CURSOR_FORMAT_ARGB |
10971                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10972 }
10973
10974 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10975 {
10976         int width = drm_rect_width(&plane_state->uapi.dst);
10977
10978         /*
10979          * 845g/865g are only limited by the width of their cursors,
10980          * the height is arbitrary up to the precision of the register.
10981          */
10982         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10983 }
10984
10985 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10986                              struct intel_plane_state *plane_state)
10987 {
10988         const struct drm_framebuffer *fb = plane_state->hw.fb;
10989         int ret;
10990
10991         ret = intel_check_cursor(crtc_state, plane_state);
10992         if (ret)
10993                 return ret;
10994
10995         /* if we want to turn off the cursor ignore width and height */
10996         if (!fb)
10997                 return 0;
10998
10999         /* Check for which cursor types we support */
11000         if (!i845_cursor_size_ok(plane_state)) {
11001                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11002                           drm_rect_width(&plane_state->uapi.dst),
11003                           drm_rect_height(&plane_state->uapi.dst));
11004                 return -EINVAL;
11005         }
11006
11007         WARN_ON(plane_state->uapi.visible &&
11008                 plane_state->color_plane[0].stride != fb->pitches[0]);
11009
11010         switch (fb->pitches[0]) {
11011         case 256:
11012         case 512:
11013         case 1024:
11014         case 2048:
11015                 break;
11016         default:
11017                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
11018                               fb->pitches[0]);
11019                 return -EINVAL;
11020         }
11021
11022         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11023
11024         return 0;
11025 }
11026
11027 static void i845_update_cursor(struct intel_plane *plane,
11028                                const struct intel_crtc_state *crtc_state,
11029                                const struct intel_plane_state *plane_state)
11030 {
11031         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11032         u32 cntl = 0, base = 0, pos = 0, size = 0;
11033         unsigned long irqflags;
11034
11035         if (plane_state && plane_state->uapi.visible) {
11036                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11037                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11038
11039                 cntl = plane_state->ctl |
11040                         i845_cursor_ctl_crtc(crtc_state);
11041
11042                 size = (height << 12) | width;
11043
11044                 base = intel_cursor_base(plane_state);
11045                 pos = intel_cursor_position(plane_state);
11046         }
11047
11048         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11049
11050         /* On these chipsets we can only modify the base/size/stride
11051          * whilst the cursor is disabled.
11052          */
11053         if (plane->cursor.base != base ||
11054             plane->cursor.size != size ||
11055             plane->cursor.cntl != cntl) {
11056                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
11057                 I915_WRITE_FW(CURBASE(PIPE_A), base);
11058                 I915_WRITE_FW(CURSIZE, size);
11059                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11060                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
11061
11062                 plane->cursor.base = base;
11063                 plane->cursor.size = size;
11064                 plane->cursor.cntl = cntl;
11065         } else {
11066                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11067         }
11068
11069         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11070 }
11071
11072 static void i845_disable_cursor(struct intel_plane *plane,
11073                                 const struct intel_crtc_state *crtc_state)
11074 {
11075         i845_update_cursor(plane, crtc_state, NULL);
11076 }
11077
11078 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11079                                      enum pipe *pipe)
11080 {
11081         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11082         enum intel_display_power_domain power_domain;
11083         intel_wakeref_t wakeref;
11084         bool ret;
11085
11086         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11087         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11088         if (!wakeref)
11089                 return false;
11090
11091         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11092
11093         *pipe = PIPE_A;
11094
11095         intel_display_power_put(dev_priv, power_domain, wakeref);
11096
11097         return ret;
11098 }
11099
11100 static unsigned int
11101 i9xx_cursor_max_stride(struct intel_plane *plane,
11102                        u32 pixel_format, u64 modifier,
11103                        unsigned int rotation)
11104 {
11105         return plane->base.dev->mode_config.cursor_width * 4;
11106 }
11107
11108 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11109 {
11110         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11111         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11112         u32 cntl = 0;
11113
11114         if (INTEL_GEN(dev_priv) >= 11)
11115                 return cntl;
11116
11117         if (crtc_state->gamma_enable)
11118                 cntl = MCURSOR_GAMMA_ENABLE;
11119
11120         if (crtc_state->csc_enable)
11121                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11122
11123         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11124                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11125
11126         return cntl;
11127 }
11128
11129 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11130                            const struct intel_plane_state *plane_state)
11131 {
11132         struct drm_i915_private *dev_priv =
11133                 to_i915(plane_state->uapi.plane->dev);
11134         u32 cntl = 0;
11135
11136         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11137                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11138
11139         switch (drm_rect_width(&plane_state->uapi.dst)) {
11140         case 64:
11141                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11142                 break;
11143         case 128:
11144                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11145                 break;
11146         case 256:
11147                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11148                 break;
11149         default:
11150                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11151                 return 0;
11152         }
11153
11154         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11155                 cntl |= MCURSOR_ROTATE_180;
11156
11157         return cntl;
11158 }
11159
11160 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11161 {
11162         struct drm_i915_private *dev_priv =
11163                 to_i915(plane_state->uapi.plane->dev);
11164         int width = drm_rect_width(&plane_state->uapi.dst);
11165         int height = drm_rect_height(&plane_state->uapi.dst);
11166
11167         if (!intel_cursor_size_ok(plane_state))
11168                 return false;
11169
11170         /* Cursor width is limited to a few power-of-two sizes */
11171         switch (width) {
11172         case 256:
11173         case 128:
11174         case 64:
11175                 break;
11176         default:
11177                 return false;
11178         }
11179
11180         /*
11181          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11182          * height from 8 lines up to the cursor width, when the
11183          * cursor is not rotated. Everything else requires square
11184          * cursors.
11185          */
11186         if (HAS_CUR_FBC(dev_priv) &&
11187             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11188                 if (height < 8 || height > width)
11189                         return false;
11190         } else {
11191                 if (height != width)
11192                         return false;
11193         }
11194
11195         return true;
11196 }
11197
11198 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11199                              struct intel_plane_state *plane_state)
11200 {
11201         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11202         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11203         const struct drm_framebuffer *fb = plane_state->hw.fb;
11204         enum pipe pipe = plane->pipe;
11205         int ret;
11206
11207         ret = intel_check_cursor(crtc_state, plane_state);
11208         if (ret)
11209                 return ret;
11210
11211         /* if we want to turn off the cursor ignore width and height */
11212         if (!fb)
11213                 return 0;
11214
11215         /* Check for which cursor types we support */
11216         if (!i9xx_cursor_size_ok(plane_state)) {
11217                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11218                           drm_rect_width(&plane_state->uapi.dst),
11219                           drm_rect_height(&plane_state->uapi.dst));
11220                 return -EINVAL;
11221         }
11222
11223         WARN_ON(plane_state->uapi.visible &&
11224                 plane_state->color_plane[0].stride != fb->pitches[0]);
11225
11226         if (fb->pitches[0] !=
11227             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11228                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
11229                               fb->pitches[0],
11230                               drm_rect_width(&plane_state->uapi.dst));
11231                 return -EINVAL;
11232         }
11233
11234         /*
11235          * There's something wrong with the cursor on CHV pipe C.
11236          * If it straddles the left edge of the screen then
11237          * moving it away from the edge or disabling it often
11238          * results in a pipe underrun, and often that can lead to
11239          * dead pipe (constant underrun reported, and it scans
11240          * out just a solid color). To recover from that, the
11241          * display power well must be turned off and on again.
11242          * Refuse the put the cursor into that compromised position.
11243          */
11244         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11245             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11246                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11247                 return -EINVAL;
11248         }
11249
11250         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11251
11252         return 0;
11253 }
11254
11255 static void i9xx_update_cursor(struct intel_plane *plane,
11256                                const struct intel_crtc_state *crtc_state,
11257                                const struct intel_plane_state *plane_state)
11258 {
11259         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11260         enum pipe pipe = plane->pipe;
11261         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11262         unsigned long irqflags;
11263
11264         if (plane_state && plane_state->uapi.visible) {
11265                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11266                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11267
11268                 cntl = plane_state->ctl |
11269                         i9xx_cursor_ctl_crtc(crtc_state);
11270
11271                 if (width != height)
11272                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11273
11274                 base = intel_cursor_base(plane_state);
11275                 pos = intel_cursor_position(plane_state);
11276         }
11277
11278         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11279
11280         /*
11281          * On some platforms writing CURCNTR first will also
11282          * cause CURPOS to be armed by the CURBASE write.
11283          * Without the CURCNTR write the CURPOS write would
11284          * arm itself. Thus we always update CURCNTR before
11285          * CURPOS.
11286          *
11287          * On other platforms CURPOS always requires the
11288          * CURBASE write to arm the update. Additonally
11289          * a write to any of the cursor register will cancel
11290          * an already armed cursor update. Thus leaving out
11291          * the CURBASE write after CURPOS could lead to a
11292          * cursor that doesn't appear to move, or even change
11293          * shape. Thus we always write CURBASE.
11294          *
11295          * The other registers are armed by by the CURBASE write
11296          * except when the plane is getting enabled at which time
11297          * the CURCNTR write arms the update.
11298          */
11299
11300         if (INTEL_GEN(dev_priv) >= 9)
11301                 skl_write_cursor_wm(plane, crtc_state);
11302
11303         if (plane->cursor.base != base ||
11304             plane->cursor.size != fbc_ctl ||
11305             plane->cursor.cntl != cntl) {
11306                 if (HAS_CUR_FBC(dev_priv))
11307                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
11308                 I915_WRITE_FW(CURCNTR(pipe), cntl);
11309                 I915_WRITE_FW(CURPOS(pipe), pos);
11310                 I915_WRITE_FW(CURBASE(pipe), base);
11311
11312                 plane->cursor.base = base;
11313                 plane->cursor.size = fbc_ctl;
11314                 plane->cursor.cntl = cntl;
11315         } else {
11316                 I915_WRITE_FW(CURPOS(pipe), pos);
11317                 I915_WRITE_FW(CURBASE(pipe), base);
11318         }
11319
11320         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11321 }
11322
11323 static void i9xx_disable_cursor(struct intel_plane *plane,
11324                                 const struct intel_crtc_state *crtc_state)
11325 {
11326         i9xx_update_cursor(plane, crtc_state, NULL);
11327 }
11328
11329 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11330                                      enum pipe *pipe)
11331 {
11332         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11333         enum intel_display_power_domain power_domain;
11334         intel_wakeref_t wakeref;
11335         bool ret;
11336         u32 val;
11337
11338         /*
11339          * Not 100% correct for planes that can move between pipes,
11340          * but that's only the case for gen2-3 which don't have any
11341          * display power wells.
11342          */
11343         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11344         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11345         if (!wakeref)
11346                 return false;
11347
11348         val = I915_READ(CURCNTR(plane->pipe));
11349
11350         ret = val & MCURSOR_MODE;
11351
11352         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11353                 *pipe = plane->pipe;
11354         else
11355                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11356                         MCURSOR_PIPE_SELECT_SHIFT;
11357
11358         intel_display_power_put(dev_priv, power_domain, wakeref);
11359
11360         return ret;
11361 }
11362
11363 /* VESA 640x480x72Hz mode to set on the pipe */
11364 static const struct drm_display_mode load_detect_mode = {
11365         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11366                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11367 };
11368
11369 struct drm_framebuffer *
11370 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11371                          struct drm_mode_fb_cmd2 *mode_cmd)
11372 {
11373         struct intel_framebuffer *intel_fb;
11374         int ret;
11375
11376         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11377         if (!intel_fb)
11378                 return ERR_PTR(-ENOMEM);
11379
11380         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11381         if (ret)
11382                 goto err;
11383
11384         return &intel_fb->base;
11385
11386 err:
11387         kfree(intel_fb);
11388         return ERR_PTR(ret);
11389 }
11390
11391 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11392                                         struct drm_crtc *crtc)
11393 {
11394         struct drm_plane *plane;
11395         struct drm_plane_state *plane_state;
11396         int ret, i;
11397
11398         ret = drm_atomic_add_affected_planes(state, crtc);
11399         if (ret)
11400                 return ret;
11401
11402         for_each_new_plane_in_state(state, plane, plane_state, i) {
11403                 if (plane_state->crtc != crtc)
11404                         continue;
11405
11406                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11407                 if (ret)
11408                         return ret;
11409
11410                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11411         }
11412
11413         return 0;
11414 }
11415
11416 int intel_get_load_detect_pipe(struct drm_connector *connector,
11417                                struct intel_load_detect_pipe *old,
11418                                struct drm_modeset_acquire_ctx *ctx)
11419 {
11420         struct intel_crtc *intel_crtc;
11421         struct intel_encoder *intel_encoder =
11422                 intel_attached_encoder(connector);
11423         struct drm_crtc *possible_crtc;
11424         struct drm_encoder *encoder = &intel_encoder->base;
11425         struct drm_crtc *crtc = NULL;
11426         struct drm_device *dev = encoder->dev;
11427         struct drm_i915_private *dev_priv = to_i915(dev);
11428         struct drm_mode_config *config = &dev->mode_config;
11429         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11430         struct drm_connector_state *connector_state;
11431         struct intel_crtc_state *crtc_state;
11432         int ret, i = -1;
11433
11434         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11435                       connector->base.id, connector->name,
11436                       encoder->base.id, encoder->name);
11437
11438         old->restore_state = NULL;
11439
11440         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11441
11442         /*
11443          * Algorithm gets a little messy:
11444          *
11445          *   - if the connector already has an assigned crtc, use it (but make
11446          *     sure it's on first)
11447          *
11448          *   - try to find the first unused crtc that can drive this connector,
11449          *     and use that if we find one
11450          */
11451
11452         /* See if we already have a CRTC for this connector */
11453         if (connector->state->crtc) {
11454                 crtc = connector->state->crtc;
11455
11456                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11457                 if (ret)
11458                         goto fail;
11459
11460                 /* Make sure the crtc and connector are running */
11461                 goto found;
11462         }
11463
11464         /* Find an unused one (if possible) */
11465         for_each_crtc(dev, possible_crtc) {
11466                 i++;
11467                 if (!(encoder->possible_crtcs & (1 << i)))
11468                         continue;
11469
11470                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11471                 if (ret)
11472                         goto fail;
11473
11474                 if (possible_crtc->state->enable) {
11475                         drm_modeset_unlock(&possible_crtc->mutex);
11476                         continue;
11477                 }
11478
11479                 crtc = possible_crtc;
11480                 break;
11481         }
11482
11483         /*
11484          * If we didn't find an unused CRTC, don't use any.
11485          */
11486         if (!crtc) {
11487                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11488                 ret = -ENODEV;
11489                 goto fail;
11490         }
11491
11492 found:
11493         intel_crtc = to_intel_crtc(crtc);
11494
11495         state = drm_atomic_state_alloc(dev);
11496         restore_state = drm_atomic_state_alloc(dev);
11497         if (!state || !restore_state) {
11498                 ret = -ENOMEM;
11499                 goto fail;
11500         }
11501
11502         state->acquire_ctx = ctx;
11503         restore_state->acquire_ctx = ctx;
11504
11505         connector_state = drm_atomic_get_connector_state(state, connector);
11506         if (IS_ERR(connector_state)) {
11507                 ret = PTR_ERR(connector_state);
11508                 goto fail;
11509         }
11510
11511         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11512         if (ret)
11513                 goto fail;
11514
11515         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11516         if (IS_ERR(crtc_state)) {
11517                 ret = PTR_ERR(crtc_state);
11518                 goto fail;
11519         }
11520
11521         crtc_state->uapi.active = true;
11522
11523         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11524                                            &load_detect_mode);
11525         if (ret)
11526                 goto fail;
11527
11528         ret = intel_modeset_disable_planes(state, crtc);
11529         if (ret)
11530                 goto fail;
11531
11532         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11533         if (!ret)
11534                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11535         if (!ret)
11536                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11537         if (ret) {
11538                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11539                 goto fail;
11540         }
11541
11542         ret = drm_atomic_commit(state);
11543         if (ret) {
11544                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11545                 goto fail;
11546         }
11547
11548         old->restore_state = restore_state;
11549         drm_atomic_state_put(state);
11550
11551         /* let the connector get through one full cycle before testing */
11552         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11553         return true;
11554
11555 fail:
11556         if (state) {
11557                 drm_atomic_state_put(state);
11558                 state = NULL;
11559         }
11560         if (restore_state) {
11561                 drm_atomic_state_put(restore_state);
11562                 restore_state = NULL;
11563         }
11564
11565         if (ret == -EDEADLK)
11566                 return ret;
11567
11568         return false;
11569 }
11570
11571 void intel_release_load_detect_pipe(struct drm_connector *connector,
11572                                     struct intel_load_detect_pipe *old,
11573                                     struct drm_modeset_acquire_ctx *ctx)
11574 {
11575         struct intel_encoder *intel_encoder =
11576                 intel_attached_encoder(connector);
11577         struct drm_encoder *encoder = &intel_encoder->base;
11578         struct drm_atomic_state *state = old->restore_state;
11579         int ret;
11580
11581         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11582                       connector->base.id, connector->name,
11583                       encoder->base.id, encoder->name);
11584
11585         if (!state)
11586                 return;
11587
11588         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11589         if (ret)
11590                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11591         drm_atomic_state_put(state);
11592 }
11593
11594 static int i9xx_pll_refclk(struct drm_device *dev,
11595                            const struct intel_crtc_state *pipe_config)
11596 {
11597         struct drm_i915_private *dev_priv = to_i915(dev);
11598         u32 dpll = pipe_config->dpll_hw_state.dpll;
11599
11600         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11601                 return dev_priv->vbt.lvds_ssc_freq;
11602         else if (HAS_PCH_SPLIT(dev_priv))
11603                 return 120000;
11604         else if (!IS_GEN(dev_priv, 2))
11605                 return 96000;
11606         else
11607                 return 48000;
11608 }
11609
11610 /* Returns the clock of the currently programmed mode of the given pipe. */
11611 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11612                                 struct intel_crtc_state *pipe_config)
11613 {
11614         struct drm_device *dev = crtc->base.dev;
11615         struct drm_i915_private *dev_priv = to_i915(dev);
11616         enum pipe pipe = crtc->pipe;
11617         u32 dpll = pipe_config->dpll_hw_state.dpll;
11618         u32 fp;
11619         struct dpll clock;
11620         int port_clock;
11621         int refclk = i9xx_pll_refclk(dev, pipe_config);
11622
11623         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11624                 fp = pipe_config->dpll_hw_state.fp0;
11625         else
11626                 fp = pipe_config->dpll_hw_state.fp1;
11627
11628         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11629         if (IS_PINEVIEW(dev_priv)) {
11630                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11631                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11632         } else {
11633                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11634                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11635         }
11636
11637         if (!IS_GEN(dev_priv, 2)) {
11638                 if (IS_PINEVIEW(dev_priv))
11639                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11640                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11641                 else
11642                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11643                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11644
11645                 switch (dpll & DPLL_MODE_MASK) {
11646                 case DPLLB_MODE_DAC_SERIAL:
11647                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11648                                 5 : 10;
11649                         break;
11650                 case DPLLB_MODE_LVDS:
11651                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11652                                 7 : 14;
11653                         break;
11654                 default:
11655                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11656                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11657                         return;
11658                 }
11659
11660                 if (IS_PINEVIEW(dev_priv))
11661                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11662                 else
11663                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11664         } else {
11665                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11666                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11667
11668                 if (is_lvds) {
11669                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11670                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11671
11672                         if (lvds & LVDS_CLKB_POWER_UP)
11673                                 clock.p2 = 7;
11674                         else
11675                                 clock.p2 = 14;
11676                 } else {
11677                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11678                                 clock.p1 = 2;
11679                         else {
11680                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11681                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11682                         }
11683                         if (dpll & PLL_P2_DIVIDE_BY_4)
11684                                 clock.p2 = 4;
11685                         else
11686                                 clock.p2 = 2;
11687                 }
11688
11689                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11690         }
11691
11692         /*
11693          * This value includes pixel_multiplier. We will use
11694          * port_clock to compute adjusted_mode.crtc_clock in the
11695          * encoder's get_config() function.
11696          */
11697         pipe_config->port_clock = port_clock;
11698 }
11699
11700 int intel_dotclock_calculate(int link_freq,
11701                              const struct intel_link_m_n *m_n)
11702 {
11703         /*
11704          * The calculation for the data clock is:
11705          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11706          * But we want to avoid losing precison if possible, so:
11707          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11708          *
11709          * and the link clock is simpler:
11710          * link_clock = (m * link_clock) / n
11711          */
11712
11713         if (!m_n->link_n)
11714                 return 0;
11715
11716         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11717 }
11718
11719 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11720                                    struct intel_crtc_state *pipe_config)
11721 {
11722         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11723
11724         /* read out port_clock from the DPLL */
11725         i9xx_crtc_clock_get(crtc, pipe_config);
11726
11727         /*
11728          * In case there is an active pipe without active ports,
11729          * we may need some idea for the dotclock anyway.
11730          * Calculate one based on the FDI configuration.
11731          */
11732         pipe_config->hw.adjusted_mode.crtc_clock =
11733                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11734                                          &pipe_config->fdi_m_n);
11735 }
11736
11737 /* Returns the currently programmed mode of the given encoder. */
11738 struct drm_display_mode *
11739 intel_encoder_current_mode(struct intel_encoder *encoder)
11740 {
11741         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11742         struct intel_crtc_state *crtc_state;
11743         struct drm_display_mode *mode;
11744         struct intel_crtc *crtc;
11745         enum pipe pipe;
11746
11747         if (!encoder->get_hw_state(encoder, &pipe))
11748                 return NULL;
11749
11750         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11751
11752         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11753         if (!mode)
11754                 return NULL;
11755
11756         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11757         if (!crtc_state) {
11758                 kfree(mode);
11759                 return NULL;
11760         }
11761
11762         crtc_state->uapi.crtc = &crtc->base;
11763
11764         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11765                 kfree(crtc_state);
11766                 kfree(mode);
11767                 return NULL;
11768         }
11769
11770         encoder->get_config(encoder, crtc_state);
11771
11772         intel_mode_from_pipe_config(mode, crtc_state);
11773
11774         kfree(crtc_state);
11775
11776         return mode;
11777 }
11778
11779 static void intel_crtc_destroy(struct drm_crtc *crtc)
11780 {
11781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11782
11783         drm_crtc_cleanup(crtc);
11784         kfree(intel_crtc);
11785 }
11786
11787 /**
11788  * intel_wm_need_update - Check whether watermarks need updating
11789  * @cur: current plane state
11790  * @new: new plane state
11791  *
11792  * Check current plane state versus the new one to determine whether
11793  * watermarks need to be recalculated.
11794  *
11795  * Returns true or false.
11796  */
11797 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11798                                  struct intel_plane_state *new)
11799 {
11800         /* Update watermarks on tiling or size changes. */
11801         if (new->uapi.visible != cur->uapi.visible)
11802                 return true;
11803
11804         if (!cur->hw.fb || !new->hw.fb)
11805                 return false;
11806
11807         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
11808             cur->hw.rotation != new->hw.rotation ||
11809             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
11810             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
11811             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
11812             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
11813                 return true;
11814
11815         return false;
11816 }
11817
11818 static bool needs_scaling(const struct intel_plane_state *state)
11819 {
11820         int src_w = drm_rect_width(&state->uapi.src) >> 16;
11821         int src_h = drm_rect_height(&state->uapi.src) >> 16;
11822         int dst_w = drm_rect_width(&state->uapi.dst);
11823         int dst_h = drm_rect_height(&state->uapi.dst);
11824
11825         return (src_w != dst_w || src_h != dst_h);
11826 }
11827
11828 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11829                                     struct intel_crtc_state *crtc_state,
11830                                     const struct intel_plane_state *old_plane_state,
11831                                     struct intel_plane_state *plane_state)
11832 {
11833         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11834         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11835         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11836         bool mode_changed = needs_modeset(crtc_state);
11837         bool was_crtc_enabled = old_crtc_state->hw.active;
11838         bool is_crtc_enabled = crtc_state->hw.active;
11839         bool turn_off, turn_on, visible, was_visible;
11840         int ret;
11841
11842         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11843                 ret = skl_update_scaler_plane(crtc_state, plane_state);
11844                 if (ret)
11845                         return ret;
11846         }
11847
11848         was_visible = old_plane_state->uapi.visible;
11849         visible = plane_state->uapi.visible;
11850
11851         if (!was_crtc_enabled && WARN_ON(was_visible))
11852                 was_visible = false;
11853
11854         /*
11855          * Visibility is calculated as if the crtc was on, but
11856          * after scaler setup everything depends on it being off
11857          * when the crtc isn't active.
11858          *
11859          * FIXME this is wrong for watermarks. Watermarks should also
11860          * be computed as if the pipe would be active. Perhaps move
11861          * per-plane wm computation to the .check_plane() hook, and
11862          * only combine the results from all planes in the current place?
11863          */
11864         if (!is_crtc_enabled) {
11865                 plane_state->uapi.visible = visible = false;
11866                 crtc_state->active_planes &= ~BIT(plane->id);
11867                 crtc_state->data_rate[plane->id] = 0;
11868                 crtc_state->min_cdclk[plane->id] = 0;
11869         }
11870
11871         if (!was_visible && !visible)
11872                 return 0;
11873
11874         turn_off = was_visible && (!visible || mode_changed);
11875         turn_on = visible && (!was_visible || mode_changed);
11876
11877         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11878                          crtc->base.base.id, crtc->base.name,
11879                          plane->base.base.id, plane->base.name,
11880                          was_visible, visible,
11881                          turn_off, turn_on, mode_changed);
11882
11883         if (turn_on) {
11884                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11885                         crtc_state->update_wm_pre = true;
11886
11887                 /* must disable cxsr around plane enable/disable */
11888                 if (plane->id != PLANE_CURSOR)
11889                         crtc_state->disable_cxsr = true;
11890         } else if (turn_off) {
11891                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11892                         crtc_state->update_wm_post = true;
11893
11894                 /* must disable cxsr around plane enable/disable */
11895                 if (plane->id != PLANE_CURSOR)
11896                         crtc_state->disable_cxsr = true;
11897         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11898                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11899                         /* FIXME bollocks */
11900                         crtc_state->update_wm_pre = true;
11901                         crtc_state->update_wm_post = true;
11902                 }
11903         }
11904
11905         if (visible || was_visible)
11906                 crtc_state->fb_bits |= plane->frontbuffer_bit;
11907
11908         /*
11909          * ILK/SNB DVSACNTR/Sprite Enable
11910          * IVB SPR_CTL/Sprite Enable
11911          * "When in Self Refresh Big FIFO mode, a write to enable the
11912          *  plane will be internally buffered and delayed while Big FIFO
11913          *  mode is exiting."
11914          *
11915          * Which means that enabling the sprite can take an extra frame
11916          * when we start in big FIFO mode (LP1+). Thus we need to drop
11917          * down to LP0 and wait for vblank in order to make sure the
11918          * sprite gets enabled on the next vblank after the register write.
11919          * Doing otherwise would risk enabling the sprite one frame after
11920          * we've already signalled flip completion. We can resume LP1+
11921          * once the sprite has been enabled.
11922          *
11923          *
11924          * WaCxSRDisabledForSpriteScaling:ivb
11925          * IVB SPR_SCALE/Scaling Enable
11926          * "Low Power watermarks must be disabled for at least one
11927          *  frame before enabling sprite scaling, and kept disabled
11928          *  until sprite scaling is disabled."
11929          *
11930          * ILK/SNB DVSASCALE/Scaling Enable
11931          * "When in Self Refresh Big FIFO mode, scaling enable will be
11932          *  masked off while Big FIFO mode is exiting."
11933          *
11934          * Despite the w/a only being listed for IVB we assume that
11935          * the ILK/SNB note has similar ramifications, hence we apply
11936          * the w/a on all three platforms.
11937          *
11938          * With experimental results seems this is needed also for primary
11939          * plane, not only sprite plane.
11940          */
11941         if (plane->id != PLANE_CURSOR &&
11942             (IS_GEN_RANGE(dev_priv, 5, 6) ||
11943              IS_IVYBRIDGE(dev_priv)) &&
11944             (turn_on || (!needs_scaling(old_plane_state) &&
11945                          needs_scaling(plane_state))))
11946                 crtc_state->disable_lp_wm = true;
11947
11948         return 0;
11949 }
11950
11951 static bool encoders_cloneable(const struct intel_encoder *a,
11952                                const struct intel_encoder *b)
11953 {
11954         /* masks could be asymmetric, so check both ways */
11955         return a == b || (a->cloneable & (1 << b->type) &&
11956                           b->cloneable & (1 << a->type));
11957 }
11958
11959 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11960                                          struct intel_crtc *crtc,
11961                                          struct intel_encoder *encoder)
11962 {
11963         struct intel_encoder *source_encoder;
11964         struct drm_connector *connector;
11965         struct drm_connector_state *connector_state;
11966         int i;
11967
11968         for_each_new_connector_in_state(state, connector, connector_state, i) {
11969                 if (connector_state->crtc != &crtc->base)
11970                         continue;
11971
11972                 source_encoder =
11973                         to_intel_encoder(connector_state->best_encoder);
11974                 if (!encoders_cloneable(encoder, source_encoder))
11975                         return false;
11976         }
11977
11978         return true;
11979 }
11980
11981 static int icl_add_linked_planes(struct intel_atomic_state *state)
11982 {
11983         struct intel_plane *plane, *linked;
11984         struct intel_plane_state *plane_state, *linked_plane_state;
11985         int i;
11986
11987         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11988                 linked = plane_state->planar_linked_plane;
11989
11990                 if (!linked)
11991                         continue;
11992
11993                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11994                 if (IS_ERR(linked_plane_state))
11995                         return PTR_ERR(linked_plane_state);
11996
11997                 WARN_ON(linked_plane_state->planar_linked_plane != plane);
11998                 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
11999         }
12000
12001         return 0;
12002 }
12003
12004 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12005 {
12006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12007         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12008         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12009         struct intel_plane *plane, *linked;
12010         struct intel_plane_state *plane_state;
12011         int i;
12012
12013         if (INTEL_GEN(dev_priv) < 11)
12014                 return 0;
12015
12016         /*
12017          * Destroy all old plane links and make the slave plane invisible
12018          * in the crtc_state->active_planes mask.
12019          */
12020         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12021                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12022                         continue;
12023
12024                 plane_state->planar_linked_plane = NULL;
12025                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12026                         crtc_state->active_planes &= ~BIT(plane->id);
12027                         crtc_state->update_planes |= BIT(plane->id);
12028                 }
12029
12030                 plane_state->planar_slave = false;
12031         }
12032
12033         if (!crtc_state->nv12_planes)
12034                 return 0;
12035
12036         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12037                 struct intel_plane_state *linked_state = NULL;
12038
12039                 if (plane->pipe != crtc->pipe ||
12040                     !(crtc_state->nv12_planes & BIT(plane->id)))
12041                         continue;
12042
12043                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12044                         if (!icl_is_nv12_y_plane(linked->id))
12045                                 continue;
12046
12047                         if (crtc_state->active_planes & BIT(linked->id))
12048                                 continue;
12049
12050                         linked_state = intel_atomic_get_plane_state(state, linked);
12051                         if (IS_ERR(linked_state))
12052                                 return PTR_ERR(linked_state);
12053
12054                         break;
12055                 }
12056
12057                 if (!linked_state) {
12058                         DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
12059                                       hweight8(crtc_state->nv12_planes));
12060
12061                         return -EINVAL;
12062                 }
12063
12064                 plane_state->planar_linked_plane = linked;
12065
12066                 linked_state->planar_slave = true;
12067                 linked_state->planar_linked_plane = plane;
12068                 crtc_state->active_planes |= BIT(linked->id);
12069                 crtc_state->update_planes |= BIT(linked->id);
12070                 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
12071
12072                 /* Copy parameters to slave plane */
12073                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12074                 linked_state->color_ctl = plane_state->color_ctl;
12075                 linked_state->color_plane[0] = plane_state->color_plane[0];
12076
12077                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12078                 linked_state->uapi.src = plane_state->uapi.src;
12079                 linked_state->uapi.dst = plane_state->uapi.dst;
12080
12081                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12082                         if (linked->id == PLANE_SPRITE5)
12083                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12084                         else if (linked->id == PLANE_SPRITE4)
12085                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12086                         else
12087                                 MISSING_CASE(linked->id);
12088                 }
12089         }
12090
12091         return 0;
12092 }
12093
12094 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12095 {
12096         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12097         struct intel_atomic_state *state =
12098                 to_intel_atomic_state(new_crtc_state->uapi.state);
12099         const struct intel_crtc_state *old_crtc_state =
12100                 intel_atomic_get_old_crtc_state(state, crtc);
12101
12102         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12103 }
12104
12105 static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
12106 {
12107         struct drm_crtc *crtc = crtc_state->uapi.crtc;
12108         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12109         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12110         struct drm_connector *master_connector, *connector;
12111         struct drm_connector_state *connector_state;
12112         struct drm_connector_list_iter conn_iter;
12113         struct drm_crtc *master_crtc = NULL;
12114         struct drm_crtc_state *master_crtc_state;
12115         struct intel_crtc_state *master_pipe_config;
12116         int i, tile_group_id;
12117
12118         if (INTEL_GEN(dev_priv) < 11)
12119                 return 0;
12120
12121         /*
12122          * In case of tiled displays there could be one or more slaves but there is
12123          * only one master. Lets make the CRTC used by the connector corresponding
12124          * to the last horizonal and last vertical tile a master/genlock CRTC.
12125          * All the other CRTCs corresponding to other tiles of the same Tile group
12126          * are the slave CRTCs and hold a pointer to their genlock CRTC.
12127          */
12128         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
12129                 if (connector_state->crtc != crtc)
12130                         continue;
12131                 if (!connector->has_tile)
12132                         continue;
12133                 if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
12134                     crtc_state->hw.mode.vdisplay != connector->tile_v_size)
12135                         return 0;
12136                 if (connector->tile_h_loc == connector->num_h_tile - 1 &&
12137                     connector->tile_v_loc == connector->num_v_tile - 1)
12138                         continue;
12139                 crtc_state->sync_mode_slaves_mask = 0;
12140                 tile_group_id = connector->tile_group->id;
12141                 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
12142                 drm_for_each_connector_iter(master_connector, &conn_iter) {
12143                         struct drm_connector_state *master_conn_state = NULL;
12144
12145                         if (!master_connector->has_tile)
12146                                 continue;
12147                         if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
12148                             master_connector->tile_v_loc != master_connector->num_v_tile - 1)
12149                                 continue;
12150                         if (master_connector->tile_group->id != tile_group_id)
12151                                 continue;
12152
12153                         master_conn_state = drm_atomic_get_connector_state(&state->base,
12154                                                                            master_connector);
12155                         if (IS_ERR(master_conn_state)) {
12156                                 drm_connector_list_iter_end(&conn_iter);
12157                                 return PTR_ERR(master_conn_state);
12158                         }
12159                         if (master_conn_state->crtc) {
12160                                 master_crtc = master_conn_state->crtc;
12161                                 break;
12162                         }
12163                 }
12164                 drm_connector_list_iter_end(&conn_iter);
12165
12166                 if (!master_crtc) {
12167                         DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
12168                                       connector_state->crtc->base.id);
12169                         return -EINVAL;
12170                 }
12171
12172                 master_crtc_state = drm_atomic_get_crtc_state(&state->base,
12173                                                               master_crtc);
12174                 if (IS_ERR(master_crtc_state))
12175                         return PTR_ERR(master_crtc_state);
12176
12177                 master_pipe_config = to_intel_crtc_state(master_crtc_state);
12178                 crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
12179                 master_pipe_config->sync_mode_slaves_mask |=
12180                         BIT(crtc_state->cpu_transcoder);
12181                 DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
12182                               transcoder_name(crtc_state->master_transcoder),
12183                               crtc_state->uapi.crtc->base.id,
12184                               master_pipe_config->sync_mode_slaves_mask);
12185         }
12186
12187         return 0;
12188 }
12189
12190 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12191                                    struct intel_crtc *crtc)
12192 {
12193         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12194         struct intel_crtc_state *crtc_state =
12195                 intel_atomic_get_new_crtc_state(state, crtc);
12196         bool mode_changed = needs_modeset(crtc_state);
12197         int ret;
12198
12199         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12200             mode_changed && !crtc_state->hw.active)
12201                 crtc_state->update_wm_post = true;
12202
12203         if (mode_changed && crtc_state->hw.enable &&
12204             dev_priv->display.crtc_compute_clock &&
12205             !WARN_ON(crtc_state->shared_dpll)) {
12206                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12207                 if (ret)
12208                         return ret;
12209         }
12210
12211         /*
12212          * May need to update pipe gamma enable bits
12213          * when C8 planes are getting enabled/disabled.
12214          */
12215         if (c8_planes_changed(crtc_state))
12216                 crtc_state->uapi.color_mgmt_changed = true;
12217
12218         if (mode_changed || crtc_state->update_pipe ||
12219             crtc_state->uapi.color_mgmt_changed) {
12220                 ret = intel_color_check(crtc_state);
12221                 if (ret)
12222                         return ret;
12223         }
12224
12225         ret = 0;
12226         if (dev_priv->display.compute_pipe_wm) {
12227                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12228                 if (ret) {
12229                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12230                         return ret;
12231                 }
12232         }
12233
12234         if (dev_priv->display.compute_intermediate_wm) {
12235                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12236                         return 0;
12237
12238                 /*
12239                  * Calculate 'intermediate' watermarks that satisfy both the
12240                  * old state and the new state.  We can program these
12241                  * immediately.
12242                  */
12243                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12244                 if (ret) {
12245                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12246                         return ret;
12247                 }
12248         }
12249
12250         if (INTEL_GEN(dev_priv) >= 9) {
12251                 if (mode_changed || crtc_state->update_pipe)
12252                         ret = skl_update_scaler_crtc(crtc_state);
12253                 if (!ret)
12254                         ret = intel_atomic_setup_scalers(dev_priv, crtc,
12255                                                          crtc_state);
12256         }
12257
12258         if (HAS_IPS(dev_priv))
12259                 crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
12260
12261         return ret;
12262 }
12263
12264 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12265 {
12266         struct intel_connector *connector;
12267         struct drm_connector_list_iter conn_iter;
12268
12269         drm_connector_list_iter_begin(dev, &conn_iter);
12270         for_each_intel_connector_iter(connector, &conn_iter) {
12271                 if (connector->base.state->crtc)
12272                         drm_connector_put(&connector->base);
12273
12274                 if (connector->base.encoder) {
12275                         connector->base.state->best_encoder =
12276                                 connector->base.encoder;
12277                         connector->base.state->crtc =
12278                                 connector->base.encoder->crtc;
12279
12280                         drm_connector_get(&connector->base);
12281                 } else {
12282                         connector->base.state->best_encoder = NULL;
12283                         connector->base.state->crtc = NULL;
12284                 }
12285         }
12286         drm_connector_list_iter_end(&conn_iter);
12287 }
12288
12289 static int
12290 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12291                       struct intel_crtc_state *pipe_config)
12292 {
12293         struct drm_connector *connector = conn_state->connector;
12294         const struct drm_display_info *info = &connector->display_info;
12295         int bpp;
12296
12297         switch (conn_state->max_bpc) {
12298         case 6 ... 7:
12299                 bpp = 6 * 3;
12300                 break;
12301         case 8 ... 9:
12302                 bpp = 8 * 3;
12303                 break;
12304         case 10 ... 11:
12305                 bpp = 10 * 3;
12306                 break;
12307         case 12:
12308                 bpp = 12 * 3;
12309                 break;
12310         default:
12311                 return -EINVAL;
12312         }
12313
12314         if (bpp < pipe_config->pipe_bpp) {
12315                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12316                               "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12317                               connector->base.id, connector->name,
12318                               bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
12319                               pipe_config->pipe_bpp);
12320
12321                 pipe_config->pipe_bpp = bpp;
12322         }
12323
12324         return 0;
12325 }
12326
12327 static int
12328 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12329                           struct intel_crtc_state *pipe_config)
12330 {
12331         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12332         struct drm_atomic_state *state = pipe_config->uapi.state;
12333         struct drm_connector *connector;
12334         struct drm_connector_state *connector_state;
12335         int bpp, i;
12336
12337         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12338             IS_CHERRYVIEW(dev_priv)))
12339                 bpp = 10*3;
12340         else if (INTEL_GEN(dev_priv) >= 5)
12341                 bpp = 12*3;
12342         else
12343                 bpp = 8*3;
12344
12345         pipe_config->pipe_bpp = bpp;
12346
12347         /* Clamp display bpp to connector max bpp */
12348         for_each_new_connector_in_state(state, connector, connector_state, i) {
12349                 int ret;
12350
12351                 if (connector_state->crtc != &crtc->base)
12352                         continue;
12353
12354                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12355                 if (ret)
12356                         return ret;
12357         }
12358
12359         return 0;
12360 }
12361
12362 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12363 {
12364         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12365                       "type: 0x%x flags: 0x%x\n",
12366                       mode->crtc_clock,
12367                       mode->crtc_hdisplay, mode->crtc_hsync_start,
12368                       mode->crtc_hsync_end, mode->crtc_htotal,
12369                       mode->crtc_vdisplay, mode->crtc_vsync_start,
12370                       mode->crtc_vsync_end, mode->crtc_vtotal,
12371                       mode->type, mode->flags);
12372 }
12373
12374 static inline void
12375 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12376                       const char *id, unsigned int lane_count,
12377                       const struct intel_link_m_n *m_n)
12378 {
12379         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12380                       id, lane_count,
12381                       m_n->gmch_m, m_n->gmch_n,
12382                       m_n->link_m, m_n->link_n, m_n->tu);
12383 }
12384
12385 static void
12386 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12387                      const union hdmi_infoframe *frame)
12388 {
12389         if ((drm_debug & DRM_UT_KMS) == 0)
12390                 return;
12391
12392         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12393 }
12394
12395 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12396
12397 static const char * const output_type_str[] = {
12398         OUTPUT_TYPE(UNUSED),
12399         OUTPUT_TYPE(ANALOG),
12400         OUTPUT_TYPE(DVO),
12401         OUTPUT_TYPE(SDVO),
12402         OUTPUT_TYPE(LVDS),
12403         OUTPUT_TYPE(TVOUT),
12404         OUTPUT_TYPE(HDMI),
12405         OUTPUT_TYPE(DP),
12406         OUTPUT_TYPE(EDP),
12407         OUTPUT_TYPE(DSI),
12408         OUTPUT_TYPE(DDI),
12409         OUTPUT_TYPE(DP_MST),
12410 };
12411
12412 #undef OUTPUT_TYPE
12413
12414 static void snprintf_output_types(char *buf, size_t len,
12415                                   unsigned int output_types)
12416 {
12417         char *str = buf;
12418         int i;
12419
12420         str[0] = '\0';
12421
12422         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12423                 int r;
12424
12425                 if ((output_types & BIT(i)) == 0)
12426                         continue;
12427
12428                 r = snprintf(str, len, "%s%s",
12429                              str != buf ? "," : "", output_type_str[i]);
12430                 if (r >= len)
12431                         break;
12432                 str += r;
12433                 len -= r;
12434
12435                 output_types &= ~BIT(i);
12436         }
12437
12438         WARN_ON_ONCE(output_types != 0);
12439 }
12440
12441 static const char * const output_format_str[] = {
12442         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12443         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12444         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12445         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12446 };
12447
12448 static const char *output_formats(enum intel_output_format format)
12449 {
12450         if (format >= ARRAY_SIZE(output_format_str))
12451                 format = INTEL_OUTPUT_FORMAT_INVALID;
12452         return output_format_str[format];
12453 }
12454
12455 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12456 {
12457         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12458         const struct drm_framebuffer *fb = plane_state->hw.fb;
12459         struct drm_format_name_buf format_name;
12460
12461         if (!fb) {
12462                 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12463                               plane->base.base.id, plane->base.name,
12464                               yesno(plane_state->uapi.visible));
12465                 return;
12466         }
12467
12468         DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12469                       plane->base.base.id, plane->base.name,
12470                       fb->base.id, fb->width, fb->height,
12471                       drm_get_format_name(fb->format->format, &format_name),
12472                       yesno(plane_state->uapi.visible));
12473         DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12474                       plane_state->hw.rotation, plane_state->scaler_id);
12475         if (plane_state->uapi.visible)
12476                 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12477                               DRM_RECT_FP_ARG(&plane_state->uapi.src),
12478                               DRM_RECT_ARG(&plane_state->uapi.dst));
12479 }
12480
12481 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12482                                    struct intel_atomic_state *state,
12483                                    const char *context)
12484 {
12485         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12486         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12487         const struct intel_plane_state *plane_state;
12488         struct intel_plane *plane;
12489         char buf[64];
12490         int i;
12491
12492         DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12493                       crtc->base.base.id, crtc->base.name,
12494                       yesno(pipe_config->hw.enable), context);
12495
12496         if (!pipe_config->hw.enable)
12497                 goto dump_planes;
12498
12499         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12500         DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12501                       yesno(pipe_config->hw.active),
12502                       buf, pipe_config->output_types,
12503                       output_formats(pipe_config->output_format));
12504
12505         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12506                       transcoder_name(pipe_config->cpu_transcoder),
12507                       pipe_config->pipe_bpp, pipe_config->dither);
12508
12509         if (pipe_config->has_pch_encoder)
12510                 intel_dump_m_n_config(pipe_config, "fdi",
12511                                       pipe_config->fdi_lanes,
12512                                       &pipe_config->fdi_m_n);
12513
12514         if (intel_crtc_has_dp_encoder(pipe_config)) {
12515                 intel_dump_m_n_config(pipe_config, "dp m_n",
12516                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12517                 if (pipe_config->has_drrs)
12518                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12519                                               pipe_config->lane_count,
12520                                               &pipe_config->dp_m2_n2);
12521         }
12522
12523         DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12524                       pipe_config->has_audio, pipe_config->has_infoframe,
12525                       pipe_config->infoframes.enable);
12526
12527         if (pipe_config->infoframes.enable &
12528             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12529                 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12530         if (pipe_config->infoframes.enable &
12531             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12532                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12533         if (pipe_config->infoframes.enable &
12534             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12535                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12536         if (pipe_config->infoframes.enable &
12537             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12538                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12539
12540         DRM_DEBUG_KMS("requested mode:\n");
12541         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
12542         DRM_DEBUG_KMS("adjusted mode:\n");
12543         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
12544         intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
12545         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12546                       pipe_config->port_clock,
12547                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12548                       pipe_config->pixel_rate);
12549
12550         if (INTEL_GEN(dev_priv) >= 9)
12551                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12552                               crtc->num_scalers,
12553                               pipe_config->scaler_state.scaler_users,
12554                               pipe_config->scaler_state.scaler_id);
12555
12556         if (HAS_GMCH(dev_priv))
12557                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12558                               pipe_config->gmch_pfit.control,
12559                               pipe_config->gmch_pfit.pgm_ratios,
12560                               pipe_config->gmch_pfit.lvds_border_bits);
12561         else
12562                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12563                               pipe_config->pch_pfit.pos,
12564                               pipe_config->pch_pfit.size,
12565                               enableddisabled(pipe_config->pch_pfit.enabled),
12566                               yesno(pipe_config->pch_pfit.force_thru));
12567
12568         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12569                       pipe_config->ips_enabled, pipe_config->double_wide);
12570
12571         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12572
12573         if (IS_CHERRYVIEW(dev_priv))
12574                 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12575                               pipe_config->cgm_mode, pipe_config->gamma_mode,
12576                               pipe_config->gamma_enable, pipe_config->csc_enable);
12577         else
12578                 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12579                               pipe_config->csc_mode, pipe_config->gamma_mode,
12580                               pipe_config->gamma_enable, pipe_config->csc_enable);
12581
12582 dump_planes:
12583         if (!state)
12584                 return;
12585
12586         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12587                 if (plane->pipe == crtc->pipe)
12588                         intel_dump_plane_state(plane_state);
12589         }
12590 }
12591
12592 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12593 {
12594         struct drm_device *dev = state->base.dev;
12595         struct drm_connector *connector;
12596         struct drm_connector_list_iter conn_iter;
12597         unsigned int used_ports = 0;
12598         unsigned int used_mst_ports = 0;
12599         bool ret = true;
12600
12601         /*
12602          * We're going to peek into connector->state,
12603          * hence connection_mutex must be held.
12604          */
12605         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
12606
12607         /*
12608          * Walk the connector list instead of the encoder
12609          * list to detect the problem on ddi platforms
12610          * where there's just one encoder per digital port.
12611          */
12612         drm_connector_list_iter_begin(dev, &conn_iter);
12613         drm_for_each_connector_iter(connector, &conn_iter) {
12614                 struct drm_connector_state *connector_state;
12615                 struct intel_encoder *encoder;
12616
12617                 connector_state =
12618                         drm_atomic_get_new_connector_state(&state->base,
12619                                                            connector);
12620                 if (!connector_state)
12621                         connector_state = connector->state;
12622
12623                 if (!connector_state->best_encoder)
12624                         continue;
12625
12626                 encoder = to_intel_encoder(connector_state->best_encoder);
12627
12628                 WARN_ON(!connector_state->crtc);
12629
12630                 switch (encoder->type) {
12631                         unsigned int port_mask;
12632                 case INTEL_OUTPUT_DDI:
12633                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12634                                 break;
12635                         /* else, fall through */
12636                 case INTEL_OUTPUT_DP:
12637                 case INTEL_OUTPUT_HDMI:
12638                 case INTEL_OUTPUT_EDP:
12639                         port_mask = 1 << encoder->port;
12640
12641                         /* the same port mustn't appear more than once */
12642                         if (used_ports & port_mask)
12643                                 ret = false;
12644
12645                         used_ports |= port_mask;
12646                         break;
12647                 case INTEL_OUTPUT_DP_MST:
12648                         used_mst_ports |=
12649                                 1 << encoder->port;
12650                         break;
12651                 default:
12652                         break;
12653                 }
12654         }
12655         drm_connector_list_iter_end(&conn_iter);
12656
12657         /* can't mix MST and SST/HDMI on the same port */
12658         if (used_ports & used_mst_ports)
12659                 return false;
12660
12661         return ret;
12662 }
12663
12664 static void
12665 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
12666 {
12667         intel_crtc_copy_color_blobs(crtc_state);
12668 }
12669
12670 static void
12671 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
12672 {
12673         crtc_state->hw.enable = crtc_state->uapi.enable;
12674         crtc_state->hw.active = crtc_state->uapi.active;
12675         crtc_state->hw.mode = crtc_state->uapi.mode;
12676         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
12677         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
12678 }
12679
12680 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
12681 {
12682         crtc_state->uapi.enable = crtc_state->hw.enable;
12683         crtc_state->uapi.active = crtc_state->hw.active;
12684         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
12685
12686         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
12687
12688         /* copy color blobs to uapi */
12689         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
12690                                   crtc_state->hw.degamma_lut);
12691         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
12692                                   crtc_state->hw.gamma_lut);
12693         drm_property_replace_blob(&crtc_state->uapi.ctm,
12694                                   crtc_state->hw.ctm);
12695 }
12696
12697 static int
12698 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
12699 {
12700         struct drm_i915_private *dev_priv =
12701                 to_i915(crtc_state->uapi.crtc->dev);
12702         struct intel_crtc_state *saved_state;
12703
12704         saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12705         if (!saved_state)
12706                 return -ENOMEM;
12707
12708         /* free the old crtc_state->hw members */
12709         intel_crtc_free_hw_state(crtc_state);
12710
12711         /* FIXME: before the switch to atomic started, a new pipe_config was
12712          * kzalloc'd. Code that depends on any field being zero should be
12713          * fixed, so that the crtc_state can be safely duplicated. For now,
12714          * only fields that are know to not cause problems are preserved. */
12715
12716         saved_state->uapi = crtc_state->uapi;
12717         saved_state->scaler_state = crtc_state->scaler_state;
12718         saved_state->shared_dpll = crtc_state->shared_dpll;
12719         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12720         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12721                sizeof(saved_state->icl_port_dplls));
12722         saved_state->crc_enabled = crtc_state->crc_enabled;
12723         if (IS_G4X(dev_priv) ||
12724             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12725                 saved_state->wm = crtc_state->wm;
12726         /*
12727          * Save the slave bitmask which gets filled for master crtc state during
12728          * slave atomic check call.
12729          */
12730         if (is_trans_port_sync_master(crtc_state))
12731                 saved_state->sync_mode_slaves_mask =
12732                         crtc_state->sync_mode_slaves_mask;
12733
12734         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
12735         kfree(saved_state);
12736
12737         intel_crtc_copy_uapi_to_hw_state(crtc_state);
12738
12739         return 0;
12740 }
12741
12742 static int
12743 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12744 {
12745         struct drm_crtc *crtc = pipe_config->uapi.crtc;
12746         struct drm_atomic_state *state = pipe_config->uapi.state;
12747         struct intel_encoder *encoder;
12748         struct drm_connector *connector;
12749         struct drm_connector_state *connector_state;
12750         int base_bpp, ret;
12751         int i;
12752         bool retry = true;
12753
12754         pipe_config->cpu_transcoder =
12755                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12756
12757         /*
12758          * Sanitize sync polarity flags based on requested ones. If neither
12759          * positive or negative polarity is requested, treat this as meaning
12760          * negative polarity.
12761          */
12762         if (!(pipe_config->hw.adjusted_mode.flags &
12763               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12764                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12765
12766         if (!(pipe_config->hw.adjusted_mode.flags &
12767               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12768                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12769
12770         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12771                                         pipe_config);
12772         if (ret)
12773                 return ret;
12774
12775         base_bpp = pipe_config->pipe_bpp;
12776
12777         /*
12778          * Determine the real pipe dimensions. Note that stereo modes can
12779          * increase the actual pipe size due to the frame doubling and
12780          * insertion of additional space for blanks between the frame. This
12781          * is stored in the crtc timings. We use the requested mode to do this
12782          * computation to clearly distinguish it from the adjusted mode, which
12783          * can be changed by the connectors in the below retry loop.
12784          */
12785         drm_mode_get_hv_timing(&pipe_config->hw.mode,
12786                                &pipe_config->pipe_src_w,
12787                                &pipe_config->pipe_src_h);
12788
12789         for_each_new_connector_in_state(state, connector, connector_state, i) {
12790                 if (connector_state->crtc != crtc)
12791                         continue;
12792
12793                 encoder = to_intel_encoder(connector_state->best_encoder);
12794
12795                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12796                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12797                         return -EINVAL;
12798                 }
12799
12800                 /*
12801                  * Determine output_types before calling the .compute_config()
12802                  * hooks so that the hooks can use this information safely.
12803                  */
12804                 if (encoder->compute_output_type)
12805                         pipe_config->output_types |=
12806                                 BIT(encoder->compute_output_type(encoder, pipe_config,
12807                                                                  connector_state));
12808                 else
12809                         pipe_config->output_types |= BIT(encoder->type);
12810         }
12811
12812 encoder_retry:
12813         /* Ensure the port clock defaults are reset when retrying. */
12814         pipe_config->port_clock = 0;
12815         pipe_config->pixel_multiplier = 1;
12816
12817         /* Fill in default crtc timings, allow encoders to overwrite them. */
12818         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
12819                               CRTC_STEREO_DOUBLE);
12820
12821         /* Set the crtc_state defaults for trans_port_sync */
12822         pipe_config->master_transcoder = INVALID_TRANSCODER;
12823         ret = icl_add_sync_mode_crtcs(pipe_config);
12824         if (ret) {
12825                 DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
12826                               ret);
12827                 return ret;
12828         }
12829
12830         /* Pass our mode to the connectors and the CRTC to give them a chance to
12831          * adjust it according to limitations or connector properties, and also
12832          * a chance to reject the mode entirely.
12833          */
12834         for_each_new_connector_in_state(state, connector, connector_state, i) {
12835                 if (connector_state->crtc != crtc)
12836                         continue;
12837
12838                 encoder = to_intel_encoder(connector_state->best_encoder);
12839                 ret = encoder->compute_config(encoder, pipe_config,
12840                                               connector_state);
12841                 if (ret < 0) {
12842                         if (ret != -EDEADLK)
12843                                 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12844                                               ret);
12845                         return ret;
12846                 }
12847         }
12848
12849         /* Set default port clock if not overwritten by the encoder. Needs to be
12850          * done afterwards in case the encoder adjusts the mode. */
12851         if (!pipe_config->port_clock)
12852                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
12853                         * pipe_config->pixel_multiplier;
12854
12855         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12856         if (ret == -EDEADLK)
12857                 return ret;
12858         if (ret < 0) {
12859                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12860                 return ret;
12861         }
12862
12863         if (ret == RETRY) {
12864                 if (WARN(!retry, "loop in pipe configuration computation\n"))
12865                         return -EINVAL;
12866
12867                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12868                 retry = false;
12869                 goto encoder_retry;
12870         }
12871
12872         /* Dithering seems to not pass-through bits correctly when it should, so
12873          * only enable it on 6bpc panels and when its not a compliance
12874          * test requesting 6bpc video pattern.
12875          */
12876         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12877                 !pipe_config->dither_force_disable;
12878         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12879                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12880
12881         /*
12882          * Make drm_calc_timestamping_constants in
12883          * drm_atomic_helper_update_legacy_modeset_state() happy
12884          */
12885         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
12886
12887         return 0;
12888 }
12889
12890 bool intel_fuzzy_clock_check(int clock1, int clock2)
12891 {
12892         int diff;
12893
12894         if (clock1 == clock2)
12895                 return true;
12896
12897         if (!clock1 || !clock2)
12898                 return false;
12899
12900         diff = abs(clock1 - clock2);
12901
12902         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12903                 return true;
12904
12905         return false;
12906 }
12907
12908 static bool
12909 intel_compare_m_n(unsigned int m, unsigned int n,
12910                   unsigned int m2, unsigned int n2,
12911                   bool exact)
12912 {
12913         if (m == m2 && n == n2)
12914                 return true;
12915
12916         if (exact || !m || !n || !m2 || !n2)
12917                 return false;
12918
12919         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12920
12921         if (n > n2) {
12922                 while (n > n2) {
12923                         m2 <<= 1;
12924                         n2 <<= 1;
12925                 }
12926         } else if (n < n2) {
12927                 while (n < n2) {
12928                         m <<= 1;
12929                         n <<= 1;
12930                 }
12931         }
12932
12933         if (n != n2)
12934                 return false;
12935
12936         return intel_fuzzy_clock_check(m, m2);
12937 }
12938
12939 static bool
12940 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12941                        const struct intel_link_m_n *m2_n2,
12942                        bool exact)
12943 {
12944         return m_n->tu == m2_n2->tu &&
12945                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12946                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12947                 intel_compare_m_n(m_n->link_m, m_n->link_n,
12948                                   m2_n2->link_m, m2_n2->link_n, exact);
12949 }
12950
12951 static bool
12952 intel_compare_infoframe(const union hdmi_infoframe *a,
12953                         const union hdmi_infoframe *b)
12954 {
12955         return memcmp(a, b, sizeof(*a)) == 0;
12956 }
12957
12958 static void
12959 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12960                                bool fastset, const char *name,
12961                                const union hdmi_infoframe *a,
12962                                const union hdmi_infoframe *b)
12963 {
12964         if (fastset) {
12965                 if ((drm_debug & DRM_UT_KMS) == 0)
12966                         return;
12967
12968                 DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name);
12969                 DRM_DEBUG_KMS("expected:\n");
12970                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12971                 DRM_DEBUG_KMS("found:\n");
12972                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12973         } else {
12974                 DRM_ERROR("mismatch in %s infoframe\n", name);
12975                 DRM_ERROR("expected:\n");
12976                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12977                 DRM_ERROR("found:\n");
12978                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12979         }
12980 }
12981
12982 static void __printf(4, 5)
12983 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
12984                      const char *name, const char *format, ...)
12985 {
12986         struct va_format vaf;
12987         va_list args;
12988
12989         va_start(args, format);
12990         vaf.fmt = format;
12991         vaf.va = &args;
12992
12993         if (fastset)
12994                 DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
12995                               crtc->base.base.id, crtc->base.name, name, &vaf);
12996         else
12997                 DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
12998                           crtc->base.base.id, crtc->base.name, name, &vaf);
12999
13000         va_end(args);
13001 }
13002
13003 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13004 {
13005         if (i915_modparams.fastboot != -1)
13006                 return i915_modparams.fastboot;
13007
13008         /* Enable fastboot by default on Skylake and newer */
13009         if (INTEL_GEN(dev_priv) >= 9)
13010                 return true;
13011
13012         /* Enable fastboot by default on VLV and CHV */
13013         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13014                 return true;
13015
13016         /* Disabled by default on all others */
13017         return false;
13018 }
13019
13020 static bool
13021 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13022                           const struct intel_crtc_state *pipe_config,
13023                           bool fastset)
13024 {
13025         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13026         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13027         bool ret = true;
13028         u32 bp_gamma = 0;
13029         bool fixup_inherited = fastset &&
13030                 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
13031                 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
13032
13033         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13034                 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
13035                 ret = false;
13036         }
13037
13038 #define PIPE_CONF_CHECK_X(name) do { \
13039         if (current_config->name != pipe_config->name) { \
13040                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13041                                      "(expected 0x%08x, found 0x%08x)", \
13042                                      current_config->name, \
13043                                      pipe_config->name); \
13044                 ret = false; \
13045         } \
13046 } while (0)
13047
13048 #define PIPE_CONF_CHECK_I(name) do { \
13049         if (current_config->name != pipe_config->name) { \
13050                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13051                                      "(expected %i, found %i)", \
13052                                      current_config->name, \
13053                                      pipe_config->name); \
13054                 ret = false; \
13055         } \
13056 } while (0)
13057
13058 #define PIPE_CONF_CHECK_BOOL(name) do { \
13059         if (current_config->name != pipe_config->name) { \
13060                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13061                                      "(expected %s, found %s)", \
13062                                      yesno(current_config->name), \
13063                                      yesno(pipe_config->name)); \
13064                 ret = false; \
13065         } \
13066 } while (0)
13067
13068 /*
13069  * Checks state where we only read out the enabling, but not the entire
13070  * state itself (like full infoframes or ELD for audio). These states
13071  * require a full modeset on bootup to fix up.
13072  */
13073 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13074         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13075                 PIPE_CONF_CHECK_BOOL(name); \
13076         } else { \
13077                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13078                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13079                                      yesno(current_config->name), \
13080                                      yesno(pipe_config->name)); \
13081                 ret = false; \
13082         } \
13083 } while (0)
13084
13085 #define PIPE_CONF_CHECK_P(name) do { \
13086         if (current_config->name != pipe_config->name) { \
13087                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13088                                      "(expected %p, found %p)", \
13089                                      current_config->name, \
13090                                      pipe_config->name); \
13091                 ret = false; \
13092         } \
13093 } while (0)
13094
13095 #define PIPE_CONF_CHECK_M_N(name) do { \
13096         if (!intel_compare_link_m_n(&current_config->name, \
13097                                     &pipe_config->name,\
13098                                     !fastset)) { \
13099                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13100                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13101                                      "found tu %i, gmch %i/%i link %i/%i)", \
13102                                      current_config->name.tu, \
13103                                      current_config->name.gmch_m, \
13104                                      current_config->name.gmch_n, \
13105                                      current_config->name.link_m, \
13106                                      current_config->name.link_n, \
13107                                      pipe_config->name.tu, \
13108                                      pipe_config->name.gmch_m, \
13109                                      pipe_config->name.gmch_n, \
13110                                      pipe_config->name.link_m, \
13111                                      pipe_config->name.link_n); \
13112                 ret = false; \
13113         } \
13114 } while (0)
13115
13116 /* This is required for BDW+ where there is only one set of registers for
13117  * switching between high and low RR.
13118  * This macro can be used whenever a comparison has to be made between one
13119  * hw state and multiple sw state variables.
13120  */
13121 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13122         if (!intel_compare_link_m_n(&current_config->name, \
13123                                     &pipe_config->name, !fastset) && \
13124             !intel_compare_link_m_n(&current_config->alt_name, \
13125                                     &pipe_config->name, !fastset)) { \
13126                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13127                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13128                                      "or tu %i gmch %i/%i link %i/%i, " \
13129                                      "found tu %i, gmch %i/%i link %i/%i)", \
13130                                      current_config->name.tu, \
13131                                      current_config->name.gmch_m, \
13132                                      current_config->name.gmch_n, \
13133                                      current_config->name.link_m, \
13134                                      current_config->name.link_n, \
13135                                      current_config->alt_name.tu, \
13136                                      current_config->alt_name.gmch_m, \
13137                                      current_config->alt_name.gmch_n, \
13138                                      current_config->alt_name.link_m, \
13139                                      current_config->alt_name.link_n, \
13140                                      pipe_config->name.tu, \
13141                                      pipe_config->name.gmch_m, \
13142                                      pipe_config->name.gmch_n, \
13143                                      pipe_config->name.link_m, \
13144                                      pipe_config->name.link_n); \
13145                 ret = false; \
13146         } \
13147 } while (0)
13148
13149 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13150         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13151                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13152                                      "(%x) (expected %i, found %i)", \
13153                                      (mask), \
13154                                      current_config->name & (mask), \
13155                                      pipe_config->name & (mask)); \
13156                 ret = false; \
13157         } \
13158 } while (0)
13159
13160 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13161         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13162                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13163                                      "(expected %i, found %i)", \
13164                                      current_config->name, \
13165                                      pipe_config->name); \
13166                 ret = false; \
13167         } \
13168 } while (0)
13169
13170 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13171         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13172                                      &pipe_config->infoframes.name)) { \
13173                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13174                                                &current_config->infoframes.name, \
13175                                                &pipe_config->infoframes.name); \
13176                 ret = false; \
13177         } \
13178 } while (0)
13179
13180 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13181         if (current_config->name1 != pipe_config->name1) { \
13182                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13183                                 "(expected %i, found %i, won't compare lut values)", \
13184                                 current_config->name1, \
13185                                 pipe_config->name1); \
13186                 ret = false;\
13187         } else { \
13188                 if (!intel_color_lut_equal(current_config->name2, \
13189                                         pipe_config->name2, pipe_config->name1, \
13190                                         bit_precision)) { \
13191                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13192                                         "hw_state doesn't match sw_state"); \
13193                         ret = false; \
13194                 } \
13195         } \
13196 } while (0)
13197
13198 #define PIPE_CONF_QUIRK(quirk) \
13199         ((current_config->quirks | pipe_config->quirks) & (quirk))
13200
13201         PIPE_CONF_CHECK_I(cpu_transcoder);
13202
13203         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13204         PIPE_CONF_CHECK_I(fdi_lanes);
13205         PIPE_CONF_CHECK_M_N(fdi_m_n);
13206
13207         PIPE_CONF_CHECK_I(lane_count);
13208         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13209
13210         if (INTEL_GEN(dev_priv) < 8) {
13211                 PIPE_CONF_CHECK_M_N(dp_m_n);
13212
13213                 if (current_config->has_drrs)
13214                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13215         } else
13216                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13217
13218         PIPE_CONF_CHECK_X(output_types);
13219
13220         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13221         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13222         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13223         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13224         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13225         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13226
13227         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13228         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13229         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13230         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13231         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13232         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13233
13234         PIPE_CONF_CHECK_I(pixel_multiplier);
13235         PIPE_CONF_CHECK_I(output_format);
13236         PIPE_CONF_CHECK_I(dc3co_exitline);
13237         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13238         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13239             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13240                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13241
13242         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13243         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13244         PIPE_CONF_CHECK_BOOL(has_infoframe);
13245         PIPE_CONF_CHECK_BOOL(fec_enable);
13246
13247         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13248
13249         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13250                               DRM_MODE_FLAG_INTERLACE);
13251
13252         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13253                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13254                                       DRM_MODE_FLAG_PHSYNC);
13255                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13256                                       DRM_MODE_FLAG_NHSYNC);
13257                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13258                                       DRM_MODE_FLAG_PVSYNC);
13259                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13260                                       DRM_MODE_FLAG_NVSYNC);
13261         }
13262
13263         PIPE_CONF_CHECK_X(gmch_pfit.control);
13264         /* pfit ratios are autocomputed by the hw on gen4+ */
13265         if (INTEL_GEN(dev_priv) < 4)
13266                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13267         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13268
13269         /*
13270          * Changing the EDP transcoder input mux
13271          * (A_ONOFF vs. A_ON) requires a full modeset.
13272          */
13273         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13274
13275         if (!fastset) {
13276                 PIPE_CONF_CHECK_I(pipe_src_w);
13277                 PIPE_CONF_CHECK_I(pipe_src_h);
13278
13279                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13280                 if (current_config->pch_pfit.enabled) {
13281                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13282                         PIPE_CONF_CHECK_X(pch_pfit.size);
13283                 }
13284
13285                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13286                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13287
13288                 PIPE_CONF_CHECK_X(gamma_mode);
13289                 if (IS_CHERRYVIEW(dev_priv))
13290                         PIPE_CONF_CHECK_X(cgm_mode);
13291                 else
13292                         PIPE_CONF_CHECK_X(csc_mode);
13293                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13294                 PIPE_CONF_CHECK_BOOL(csc_enable);
13295
13296                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13297                 if (bp_gamma)
13298                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13299
13300         }
13301
13302         PIPE_CONF_CHECK_BOOL(double_wide);
13303
13304         PIPE_CONF_CHECK_P(shared_dpll);
13305         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13306         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13307         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13308         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13309         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13310         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13311         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13312         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13313         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13314         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13315         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13316         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13317         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13318         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13319         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13320         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13321         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13322         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13323         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13324         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13325         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13326         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13327         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13328         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13329         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13330         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13331         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13332         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13333         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13334         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13335         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13336
13337         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13338         PIPE_CONF_CHECK_X(dsi_pll.div);
13339
13340         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13341                 PIPE_CONF_CHECK_I(pipe_bpp);
13342
13343         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13344         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13345
13346         PIPE_CONF_CHECK_I(min_voltage_level);
13347
13348         PIPE_CONF_CHECK_X(infoframes.enable);
13349         PIPE_CONF_CHECK_X(infoframes.gcp);
13350         PIPE_CONF_CHECK_INFOFRAME(avi);
13351         PIPE_CONF_CHECK_INFOFRAME(spd);
13352         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13353         PIPE_CONF_CHECK_INFOFRAME(drm);
13354
13355         PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
13356         PIPE_CONF_CHECK_I(master_transcoder);
13357
13358 #undef PIPE_CONF_CHECK_X
13359 #undef PIPE_CONF_CHECK_I
13360 #undef PIPE_CONF_CHECK_BOOL
13361 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13362 #undef PIPE_CONF_CHECK_P
13363 #undef PIPE_CONF_CHECK_FLAGS
13364 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13365 #undef PIPE_CONF_CHECK_COLOR_LUT
13366 #undef PIPE_CONF_QUIRK
13367
13368         return ret;
13369 }
13370
13371 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13372                                            const struct intel_crtc_state *pipe_config)
13373 {
13374         if (pipe_config->has_pch_encoder) {
13375                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13376                                                             &pipe_config->fdi_m_n);
13377                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13378
13379                 /*
13380                  * FDI already provided one idea for the dotclock.
13381                  * Yell if the encoder disagrees.
13382                  */
13383                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13384                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13385                      fdi_dotclock, dotclock);
13386         }
13387 }
13388
13389 static void verify_wm_state(struct intel_crtc *crtc,
13390                             struct intel_crtc_state *new_crtc_state)
13391 {
13392         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13393         struct skl_hw_state {
13394                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13395                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13396                 struct skl_ddb_allocation ddb;
13397                 struct skl_pipe_wm wm;
13398         } *hw;
13399         struct skl_ddb_allocation *sw_ddb;
13400         struct skl_pipe_wm *sw_wm;
13401         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13402         const enum pipe pipe = crtc->pipe;
13403         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13404
13405         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13406                 return;
13407
13408         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13409         if (!hw)
13410                 return;
13411
13412         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13413         sw_wm = &new_crtc_state->wm.skl.optimal;
13414
13415         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13416
13417         skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13418         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13419
13420         if (INTEL_GEN(dev_priv) >= 11 &&
13421             hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13422                 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
13423                           sw_ddb->enabled_slices,
13424                           hw->ddb.enabled_slices);
13425
13426         /* planes */
13427         for_each_universal_plane(dev_priv, pipe, plane) {
13428                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13429
13430                 hw_plane_wm = &hw->wm.planes[plane];
13431                 sw_plane_wm = &sw_wm->planes[plane];
13432
13433                 /* Watermarks */
13434                 for (level = 0; level <= max_level; level++) {
13435                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13436                                                 &sw_plane_wm->wm[level]))
13437                                 continue;
13438
13439                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13440                                   pipe_name(pipe), plane + 1, level,
13441                                   sw_plane_wm->wm[level].plane_en,
13442                                   sw_plane_wm->wm[level].plane_res_b,
13443                                   sw_plane_wm->wm[level].plane_res_l,
13444                                   hw_plane_wm->wm[level].plane_en,
13445                                   hw_plane_wm->wm[level].plane_res_b,
13446                                   hw_plane_wm->wm[level].plane_res_l);
13447                 }
13448
13449                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13450                                          &sw_plane_wm->trans_wm)) {
13451                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13452                                   pipe_name(pipe), plane + 1,
13453                                   sw_plane_wm->trans_wm.plane_en,
13454                                   sw_plane_wm->trans_wm.plane_res_b,
13455                                   sw_plane_wm->trans_wm.plane_res_l,
13456                                   hw_plane_wm->trans_wm.plane_en,
13457                                   hw_plane_wm->trans_wm.plane_res_b,
13458                                   hw_plane_wm->trans_wm.plane_res_l);
13459                 }
13460
13461                 /* DDB */
13462                 hw_ddb_entry = &hw->ddb_y[plane];
13463                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13464
13465                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13466                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13467                                   pipe_name(pipe), plane + 1,
13468                                   sw_ddb_entry->start, sw_ddb_entry->end,
13469                                   hw_ddb_entry->start, hw_ddb_entry->end);
13470                 }
13471         }
13472
13473         /*
13474          * cursor
13475          * If the cursor plane isn't active, we may not have updated it's ddb
13476          * allocation. In that case since the ddb allocation will be updated
13477          * once the plane becomes visible, we can skip this check
13478          */
13479         if (1) {
13480                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13481
13482                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13483                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13484
13485                 /* Watermarks */
13486                 for (level = 0; level <= max_level; level++) {
13487                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13488                                                 &sw_plane_wm->wm[level]))
13489                                 continue;
13490
13491                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13492                                   pipe_name(pipe), level,
13493                                   sw_plane_wm->wm[level].plane_en,
13494                                   sw_plane_wm->wm[level].plane_res_b,
13495                                   sw_plane_wm->wm[level].plane_res_l,
13496                                   hw_plane_wm->wm[level].plane_en,
13497                                   hw_plane_wm->wm[level].plane_res_b,
13498                                   hw_plane_wm->wm[level].plane_res_l);
13499                 }
13500
13501                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13502                                          &sw_plane_wm->trans_wm)) {
13503                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13504                                   pipe_name(pipe),
13505                                   sw_plane_wm->trans_wm.plane_en,
13506                                   sw_plane_wm->trans_wm.plane_res_b,
13507                                   sw_plane_wm->trans_wm.plane_res_l,
13508                                   hw_plane_wm->trans_wm.plane_en,
13509                                   hw_plane_wm->trans_wm.plane_res_b,
13510                                   hw_plane_wm->trans_wm.plane_res_l);
13511                 }
13512
13513                 /* DDB */
13514                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13515                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13516
13517                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13518                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13519                                   pipe_name(pipe),
13520                                   sw_ddb_entry->start, sw_ddb_entry->end,
13521                                   hw_ddb_entry->start, hw_ddb_entry->end);
13522                 }
13523         }
13524
13525         kfree(hw);
13526 }
13527
13528 static void
13529 verify_connector_state(struct intel_atomic_state *state,
13530                        struct intel_crtc *crtc)
13531 {
13532         struct drm_connector *connector;
13533         struct drm_connector_state *new_conn_state;
13534         int i;
13535
13536         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13537                 struct drm_encoder *encoder = connector->encoder;
13538                 struct intel_crtc_state *crtc_state = NULL;
13539
13540                 if (new_conn_state->crtc != &crtc->base)
13541                         continue;
13542
13543                 if (crtc)
13544                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13545
13546                 intel_connector_verify_state(crtc_state, new_conn_state);
13547
13548                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13549                      "connector's atomic encoder doesn't match legacy encoder\n");
13550         }
13551 }
13552
13553 static void
13554 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13555 {
13556         struct intel_encoder *encoder;
13557         struct drm_connector *connector;
13558         struct drm_connector_state *old_conn_state, *new_conn_state;
13559         int i;
13560
13561         for_each_intel_encoder(&dev_priv->drm, encoder) {
13562                 bool enabled = false, found = false;
13563                 enum pipe pipe;
13564
13565                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13566                               encoder->base.base.id,
13567                               encoder->base.name);
13568
13569                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13570                                                    new_conn_state, i) {
13571                         if (old_conn_state->best_encoder == &encoder->base)
13572                                 found = true;
13573
13574                         if (new_conn_state->best_encoder != &encoder->base)
13575                                 continue;
13576                         found = enabled = true;
13577
13578                         I915_STATE_WARN(new_conn_state->crtc !=
13579                                         encoder->base.crtc,
13580                              "connector's crtc doesn't match encoder crtc\n");
13581                 }
13582
13583                 if (!found)
13584                         continue;
13585
13586                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13587                      "encoder's enabled state mismatch "
13588                      "(expected %i, found %i)\n",
13589                      !!encoder->base.crtc, enabled);
13590
13591                 if (!encoder->base.crtc) {
13592                         bool active;
13593
13594                         active = encoder->get_hw_state(encoder, &pipe);
13595                         I915_STATE_WARN(active,
13596                              "encoder detached but still enabled on pipe %c.\n",
13597                              pipe_name(pipe));
13598                 }
13599         }
13600 }
13601
13602 static void
13603 verify_crtc_state(struct intel_crtc *crtc,
13604                   struct intel_crtc_state *old_crtc_state,
13605                   struct intel_crtc_state *new_crtc_state)
13606 {
13607         struct drm_device *dev = crtc->base.dev;
13608         struct drm_i915_private *dev_priv = to_i915(dev);
13609         struct intel_encoder *encoder;
13610         struct intel_crtc_state *pipe_config;
13611         struct drm_atomic_state *state;
13612         bool active;
13613
13614         state = old_crtc_state->uapi.state;
13615         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
13616         intel_crtc_free_hw_state(old_crtc_state);
13617
13618         pipe_config = old_crtc_state;
13619         memset(pipe_config, 0, sizeof(*pipe_config));
13620         pipe_config->uapi.crtc = &crtc->base;
13621         pipe_config->uapi.state = state;
13622
13623         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13624
13625         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13626
13627         /* we keep both pipes enabled on 830 */
13628         if (IS_I830(dev_priv))
13629                 active = new_crtc_state->hw.active;
13630
13631         I915_STATE_WARN(new_crtc_state->hw.active != active,
13632                         "crtc active state doesn't match with hw state "
13633                         "(expected %i, found %i)\n",
13634                         new_crtc_state->hw.active, active);
13635
13636         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
13637                         "transitional active state does not match atomic hw state "
13638                         "(expected %i, found %i)\n",
13639                         new_crtc_state->hw.active, crtc->active);
13640
13641         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13642                 enum pipe pipe;
13643
13644                 active = encoder->get_hw_state(encoder, &pipe);
13645                 I915_STATE_WARN(active != new_crtc_state->hw.active,
13646                                 "[ENCODER:%i] active %i with crtc active %i\n",
13647                                 encoder->base.base.id, active,
13648                                 new_crtc_state->hw.active);
13649
13650                 I915_STATE_WARN(active && crtc->pipe != pipe,
13651                                 "Encoder connected to wrong pipe %c\n",
13652                                 pipe_name(pipe));
13653
13654                 if (active)
13655                         encoder->get_config(encoder, pipe_config);
13656         }
13657
13658         intel_crtc_compute_pixel_rate(pipe_config);
13659
13660         if (!new_crtc_state->hw.active)
13661                 return;
13662
13663         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13664
13665         if (!intel_pipe_config_compare(new_crtc_state,
13666                                        pipe_config, false)) {
13667                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13668                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13669                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13670         }
13671 }
13672
13673 static void
13674 intel_verify_planes(struct intel_atomic_state *state)
13675 {
13676         struct intel_plane *plane;
13677         const struct intel_plane_state *plane_state;
13678         int i;
13679
13680         for_each_new_intel_plane_in_state(state, plane,
13681                                           plane_state, i)
13682                 assert_plane(plane, plane_state->planar_slave ||
13683                              plane_state->uapi.visible);
13684 }
13685
13686 static void
13687 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13688                          struct intel_shared_dpll *pll,
13689                          struct intel_crtc *crtc,
13690                          struct intel_crtc_state *new_crtc_state)
13691 {
13692         struct intel_dpll_hw_state dpll_hw_state;
13693         unsigned int crtc_mask;
13694         bool active;
13695
13696         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13697
13698         DRM_DEBUG_KMS("%s\n", pll->info->name);
13699
13700         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13701
13702         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13703                 I915_STATE_WARN(!pll->on && pll->active_mask,
13704                      "pll in active use but not on in sw tracking\n");
13705                 I915_STATE_WARN(pll->on && !pll->active_mask,
13706                      "pll is on but not used by any active crtc\n");
13707                 I915_STATE_WARN(pll->on != active,
13708                      "pll on state mismatch (expected %i, found %i)\n",
13709                      pll->on, active);
13710         }
13711
13712         if (!crtc) {
13713                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13714                                 "more active pll users than references: %x vs %x\n",
13715                                 pll->active_mask, pll->state.crtc_mask);
13716
13717                 return;
13718         }
13719
13720         crtc_mask = drm_crtc_mask(&crtc->base);
13721
13722         if (new_crtc_state->hw.active)
13723                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13724                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13725                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13726         else
13727                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13728                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13729                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13730
13731         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13732                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13733                         crtc_mask, pll->state.crtc_mask);
13734
13735         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13736                                           &dpll_hw_state,
13737                                           sizeof(dpll_hw_state)),
13738                         "pll hw state mismatch\n");
13739 }
13740
13741 static void
13742 verify_shared_dpll_state(struct intel_crtc *crtc,
13743                          struct intel_crtc_state *old_crtc_state,
13744                          struct intel_crtc_state *new_crtc_state)
13745 {
13746         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13747
13748         if (new_crtc_state->shared_dpll)
13749                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13750
13751         if (old_crtc_state->shared_dpll &&
13752             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13753                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13754                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13755
13756                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13757                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13758                                 pipe_name(drm_crtc_index(&crtc->base)));
13759                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13760                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13761                                 pipe_name(drm_crtc_index(&crtc->base)));
13762         }
13763 }
13764
13765 static void
13766 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13767                           struct intel_atomic_state *state,
13768                           struct intel_crtc_state *old_crtc_state,
13769                           struct intel_crtc_state *new_crtc_state)
13770 {
13771         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13772                 return;
13773
13774         verify_wm_state(crtc, new_crtc_state);
13775         verify_connector_state(state, crtc);
13776         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13777         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13778 }
13779
13780 static void
13781 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13782 {
13783         int i;
13784
13785         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13786                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13787 }
13788
13789 static void
13790 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13791                               struct intel_atomic_state *state)
13792 {
13793         verify_encoder_state(dev_priv, state);
13794         verify_connector_state(state, NULL);
13795         verify_disabled_dpll_state(dev_priv);
13796 }
13797
13798 static void
13799 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
13800 {
13801         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13802         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13803         const struct drm_display_mode *adjusted_mode =
13804                 &crtc_state->hw.adjusted_mode;
13805
13806         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
13807
13808         /*
13809          * The scanline counter increments at the leading edge of hsync.
13810          *
13811          * On most platforms it starts counting from vtotal-1 on the
13812          * first active line. That means the scanline counter value is
13813          * always one less than what we would expect. Ie. just after
13814          * start of vblank, which also occurs at start of hsync (on the
13815          * last active line), the scanline counter will read vblank_start-1.
13816          *
13817          * On gen2 the scanline counter starts counting from 1 instead
13818          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13819          * to keep the value positive), instead of adding one.
13820          *
13821          * On HSW+ the behaviour of the scanline counter depends on the output
13822          * type. For DP ports it behaves like most other platforms, but on HDMI
13823          * there's an extra 1 line difference. So we need to add two instead of
13824          * one to the value.
13825          *
13826          * On VLV/CHV DSI the scanline counter would appear to increment
13827          * approx. 1/3 of a scanline before start of vblank. Unfortunately
13828          * that means we can't tell whether we're in vblank or not while
13829          * we're on that particular line. We must still set scanline_offset
13830          * to 1 so that the vblank timestamps come out correct when we query
13831          * the scanline counter from within the vblank interrupt handler.
13832          * However if queried just before the start of vblank we'll get an
13833          * answer that's slightly in the future.
13834          */
13835         if (IS_GEN(dev_priv, 2)) {
13836                 int vtotal;
13837
13838                 vtotal = adjusted_mode->crtc_vtotal;
13839                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13840                         vtotal /= 2;
13841
13842                 crtc->scanline_offset = vtotal - 1;
13843         } else if (HAS_DDI(dev_priv) &&
13844                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13845                 crtc->scanline_offset = 2;
13846         } else {
13847                 crtc->scanline_offset = 1;
13848         }
13849 }
13850
13851 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13852 {
13853         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13854         struct intel_crtc_state *new_crtc_state;
13855         struct intel_crtc *crtc;
13856         int i;
13857
13858         if (!dev_priv->display.crtc_compute_clock)
13859                 return;
13860
13861         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13862                 if (!needs_modeset(new_crtc_state))
13863                         continue;
13864
13865                 intel_release_shared_dplls(state, crtc);
13866         }
13867 }
13868
13869 /*
13870  * This implements the workaround described in the "notes" section of the mode
13871  * set sequence documentation. When going from no pipes or single pipe to
13872  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13873  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13874  */
13875 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13876 {
13877         struct intel_crtc_state *crtc_state;
13878         struct intel_crtc *crtc;
13879         struct intel_crtc_state *first_crtc_state = NULL;
13880         struct intel_crtc_state *other_crtc_state = NULL;
13881         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13882         int i;
13883
13884         /* look at all crtc's that are going to be enabled in during modeset */
13885         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13886                 if (!crtc_state->hw.active ||
13887                     !needs_modeset(crtc_state))
13888                         continue;
13889
13890                 if (first_crtc_state) {
13891                         other_crtc_state = crtc_state;
13892                         break;
13893                 } else {
13894                         first_crtc_state = crtc_state;
13895                         first_pipe = crtc->pipe;
13896                 }
13897         }
13898
13899         /* No workaround needed? */
13900         if (!first_crtc_state)
13901                 return 0;
13902
13903         /* w/a possibly needed, check how many crtc's are already enabled. */
13904         for_each_intel_crtc(state->base.dev, crtc) {
13905                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13906                 if (IS_ERR(crtc_state))
13907                         return PTR_ERR(crtc_state);
13908
13909                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13910
13911                 if (!crtc_state->hw.active ||
13912                     needs_modeset(crtc_state))
13913                         continue;
13914
13915                 /* 2 or more enabled crtcs means no need for w/a */
13916                 if (enabled_pipe != INVALID_PIPE)
13917                         return 0;
13918
13919                 enabled_pipe = crtc->pipe;
13920         }
13921
13922         if (enabled_pipe != INVALID_PIPE)
13923                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13924         else if (other_crtc_state)
13925                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13926
13927         return 0;
13928 }
13929
13930 static int intel_modeset_checks(struct intel_atomic_state *state)
13931 {
13932         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13933         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13934         struct intel_crtc *crtc;
13935         int ret, i;
13936
13937         /* keep the current setting */
13938         if (!state->cdclk.force_min_cdclk_changed)
13939                 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13940
13941         state->modeset = true;
13942         state->active_pipes = dev_priv->active_pipes;
13943         state->cdclk.logical = dev_priv->cdclk.logical;
13944         state->cdclk.actual = dev_priv->cdclk.actual;
13945
13946         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13947                                             new_crtc_state, i) {
13948                 if (new_crtc_state->hw.active)
13949                         state->active_pipes |= BIT(crtc->pipe);
13950                 else
13951                         state->active_pipes &= ~BIT(crtc->pipe);
13952
13953                 if (old_crtc_state->hw.active != new_crtc_state->hw.active)
13954                         state->active_pipe_changes |= BIT(crtc->pipe);
13955         }
13956
13957         if (state->active_pipe_changes) {
13958                 ret = intel_atomic_lock_global_state(state);
13959                 if (ret)
13960                         return ret;
13961         }
13962
13963         ret = intel_modeset_calc_cdclk(state);
13964         if (ret)
13965                 return ret;
13966
13967         intel_modeset_clear_plls(state);
13968
13969         if (IS_HASWELL(dev_priv))
13970                 return haswell_mode_set_planes_workaround(state);
13971
13972         return 0;
13973 }
13974
13975 /*
13976  * Handle calculation of various watermark data at the end of the atomic check
13977  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13978  * handlers to ensure that all derived state has been updated.
13979  */
13980 static int calc_watermark_data(struct intel_atomic_state *state)
13981 {
13982         struct drm_device *dev = state->base.dev;
13983         struct drm_i915_private *dev_priv = to_i915(dev);
13984
13985         /* Is there platform-specific watermark information to calculate? */
13986         if (dev_priv->display.compute_global_watermarks)
13987                 return dev_priv->display.compute_global_watermarks(state);
13988
13989         return 0;
13990 }
13991
13992 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13993                                      struct intel_crtc_state *new_crtc_state)
13994 {
13995         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
13996                 return;
13997
13998         new_crtc_state->uapi.mode_changed = false;
13999         new_crtc_state->update_pipe = true;
14000
14001         /*
14002          * If we're not doing the full modeset we want to
14003          * keep the current M/N values as they may be
14004          * sufficiently different to the computed values
14005          * to cause problems.
14006          *
14007          * FIXME: should really copy more fuzzy state here
14008          */
14009         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14010         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14011         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14012         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14013 }
14014
14015 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14016                                           struct intel_crtc *crtc,
14017                                           u8 plane_ids_mask)
14018 {
14019         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14020         struct intel_plane *plane;
14021
14022         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14023                 struct intel_plane_state *plane_state;
14024
14025                 if ((plane_ids_mask & BIT(plane->id)) == 0)
14026                         continue;
14027
14028                 plane_state = intel_atomic_get_plane_state(state, plane);
14029                 if (IS_ERR(plane_state))
14030                         return PTR_ERR(plane_state);
14031         }
14032
14033         return 0;
14034 }
14035
14036 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14037 {
14038         /* See {hsw,vlv,ivb}_plane_ratio() */
14039         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14040                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14041                 IS_IVYBRIDGE(dev_priv);
14042 }
14043
14044 static int intel_atomic_check_planes(struct intel_atomic_state *state,
14045                                      bool *need_modeset)
14046 {
14047         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14048         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14049         struct intel_plane_state *plane_state;
14050         struct intel_plane *plane;
14051         struct intel_crtc *crtc;
14052         int i, ret;
14053
14054         ret = icl_add_linked_planes(state);
14055         if (ret)
14056                 return ret;
14057
14058         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14059                 ret = intel_plane_atomic_check(state, plane);
14060                 if (ret) {
14061                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
14062                                          plane->base.base.id, plane->base.name);
14063                         return ret;
14064                 }
14065         }
14066
14067         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14068                                             new_crtc_state, i) {
14069                 u8 old_active_planes, new_active_planes;
14070
14071                 ret = icl_check_nv12_planes(new_crtc_state);
14072                 if (ret)
14073                         return ret;
14074
14075                 /*
14076                  * On some platforms the number of active planes affects
14077                  * the planes' minimum cdclk calculation. Add such planes
14078                  * to the state before we compute the minimum cdclk.
14079                  */
14080                 if (!active_planes_affects_min_cdclk(dev_priv))
14081                         continue;
14082
14083                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14084                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14085
14086                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
14087                         continue;
14088
14089                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14090                 if (ret)
14091                         return ret;
14092         }
14093
14094         /*
14095          * active_planes bitmask has been updated, and potentially
14096          * affected planes are part of the state. We can now
14097          * compute the minimum cdclk for each plane.
14098          */
14099         for_each_new_intel_plane_in_state(state, plane, plane_state, i)
14100                 *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
14101
14102         return 0;
14103 }
14104
14105 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14106 {
14107         struct intel_crtc_state *crtc_state;
14108         struct intel_crtc *crtc;
14109         int i;
14110
14111         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14112                 int ret = intel_crtc_atomic_check(state, crtc);
14113                 if (ret) {
14114                         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
14115                                          crtc->base.base.id, crtc->base.name);
14116                         return ret;
14117                 }
14118         }
14119
14120         return 0;
14121 }
14122
14123 /**
14124  * intel_atomic_check - validate state object
14125  * @dev: drm device
14126  * @_state: state to validate
14127  */
14128 static int intel_atomic_check(struct drm_device *dev,
14129                               struct drm_atomic_state *_state)
14130 {
14131         struct drm_i915_private *dev_priv = to_i915(dev);
14132         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14133         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14134         struct intel_crtc *crtc;
14135         int ret, i;
14136         bool any_ms = false;
14137
14138         /* Catch I915_MODE_FLAG_INHERITED */
14139         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14140                                             new_crtc_state, i) {
14141                 if (new_crtc_state->hw.mode.private_flags !=
14142                     old_crtc_state->hw.mode.private_flags)
14143                         new_crtc_state->uapi.mode_changed = true;
14144         }
14145
14146         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14147         if (ret)
14148                 goto fail;
14149
14150         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14151                                             new_crtc_state, i) {
14152                 if (!needs_modeset(new_crtc_state)) {
14153                         /* Light copy */
14154                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14155
14156                         continue;
14157                 }
14158
14159                 if (!new_crtc_state->uapi.enable) {
14160                         intel_crtc_copy_uapi_to_hw_state(new_crtc_state);
14161
14162                         any_ms = true;
14163                         continue;
14164                 }
14165
14166                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14167                 if (ret)
14168                         goto fail;
14169
14170                 ret = intel_modeset_pipe_config(new_crtc_state);
14171                 if (ret)
14172                         goto fail;
14173
14174                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14175
14176                 if (needs_modeset(new_crtc_state))
14177                         any_ms = true;
14178         }
14179
14180         if (any_ms && !check_digital_port_conflicts(state)) {
14181                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14182                 ret = EINVAL;
14183                 goto fail;
14184         }
14185
14186         ret = drm_dp_mst_atomic_check(&state->base);
14187         if (ret)
14188                 goto fail;
14189
14190         any_ms |= state->cdclk.force_min_cdclk_changed;
14191
14192         ret = intel_atomic_check_planes(state, &any_ms);
14193         if (ret)
14194                 goto fail;
14195
14196         if (any_ms) {
14197                 ret = intel_modeset_checks(state);
14198                 if (ret)
14199                         goto fail;
14200         } else {
14201                 state->cdclk.logical = dev_priv->cdclk.logical;
14202         }
14203
14204         ret = intel_atomic_check_crtcs(state);
14205         if (ret)
14206                 goto fail;
14207
14208         intel_fbc_choose_crtc(dev_priv, state);
14209         ret = calc_watermark_data(state);
14210         if (ret)
14211                 goto fail;
14212
14213         ret = intel_bw_atomic_check(state);
14214         if (ret)
14215                 goto fail;
14216
14217         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14218                                             new_crtc_state, i) {
14219                 if (!needs_modeset(new_crtc_state) &&
14220                     !new_crtc_state->update_pipe)
14221                         continue;
14222
14223                 intel_dump_pipe_config(new_crtc_state, state,
14224                                        needs_modeset(new_crtc_state) ?
14225                                        "[modeset]" : "[fastset]");
14226         }
14227
14228         return 0;
14229
14230  fail:
14231         if (ret == -EDEADLK)
14232                 return ret;
14233
14234         /*
14235          * FIXME would probably be nice to know which crtc specifically
14236          * caused the failure, in cases where we can pinpoint it.
14237          */
14238         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14239                                             new_crtc_state, i)
14240                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14241
14242         return ret;
14243 }
14244
14245 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14246 {
14247         return drm_atomic_helper_prepare_planes(state->base.dev,
14248                                                 &state->base);
14249 }
14250
14251 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14252 {
14253         struct drm_device *dev = crtc->base.dev;
14254         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14255
14256         if (!vblank->max_vblank_count)
14257                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14258
14259         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14260 }
14261
14262 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14263                                   struct intel_crtc_state *crtc_state)
14264 {
14265         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14266
14267         if (!IS_GEN(dev_priv, 2))
14268                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14269
14270         if (crtc_state->has_pch_encoder) {
14271                 enum pipe pch_transcoder =
14272                         intel_crtc_pch_transcoder(crtc);
14273
14274                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14275         }
14276 }
14277
14278 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14279                                const struct intel_crtc_state *new_crtc_state)
14280 {
14281         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14282         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14283
14284         /*
14285          * Update pipe size and adjust fitter if needed: the reason for this is
14286          * that in compute_mode_changes we check the native mode (not the pfit
14287          * mode) to see if we can flip rather than do a full mode set. In the
14288          * fastboot case, we'll flip, but if we don't update the pipesrc and
14289          * pfit state, we'll end up with a big fb scanned out into the wrong
14290          * sized surface.
14291          */
14292         intel_set_pipe_src_size(new_crtc_state);
14293
14294         /* on skylake this is done by detaching scalers */
14295         if (INTEL_GEN(dev_priv) >= 9) {
14296                 skl_detach_scalers(new_crtc_state);
14297
14298                 if (new_crtc_state->pch_pfit.enabled)
14299                         skylake_pfit_enable(new_crtc_state);
14300         } else if (HAS_PCH_SPLIT(dev_priv)) {
14301                 if (new_crtc_state->pch_pfit.enabled)
14302                         ironlake_pfit_enable(new_crtc_state);
14303                 else if (old_crtc_state->pch_pfit.enabled)
14304                         ironlake_pfit_disable(old_crtc_state);
14305         }
14306
14307         if (INTEL_GEN(dev_priv) >= 11)
14308                 icl_set_pipe_chicken(crtc);
14309 }
14310
14311 static void commit_pipe_config(struct intel_atomic_state *state,
14312                                struct intel_crtc_state *old_crtc_state,
14313                                struct intel_crtc_state *new_crtc_state)
14314 {
14315         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14316         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14317         bool modeset = needs_modeset(new_crtc_state);
14318
14319         /*
14320          * During modesets pipe configuration was programmed as the
14321          * CRTC was enabled.
14322          */
14323         if (!modeset) {
14324                 if (new_crtc_state->uapi.color_mgmt_changed ||
14325                     new_crtc_state->update_pipe)
14326                         intel_color_commit(new_crtc_state);
14327
14328                 if (INTEL_GEN(dev_priv) >= 9)
14329                         skl_detach_scalers(new_crtc_state);
14330
14331                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14332                         bdw_set_pipemisc(new_crtc_state);
14333
14334                 if (new_crtc_state->update_pipe)
14335                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
14336         }
14337
14338         if (dev_priv->display.atomic_update_watermarks)
14339                 dev_priv->display.atomic_update_watermarks(state, crtc);
14340 }
14341
14342 static void intel_update_crtc(struct intel_crtc *crtc,
14343                               struct intel_atomic_state *state,
14344                               struct intel_crtc_state *old_crtc_state,
14345                               struct intel_crtc_state *new_crtc_state)
14346 {
14347         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14348         bool modeset = needs_modeset(new_crtc_state);
14349         struct intel_plane_state *new_plane_state =
14350                 intel_atomic_get_new_plane_state(state,
14351                                                  to_intel_plane(crtc->base.primary));
14352
14353         if (modeset) {
14354                 intel_crtc_update_active_timings(new_crtc_state);
14355
14356                 dev_priv->display.crtc_enable(state, crtc);
14357
14358                 /* vblanks work again, re-enable pipe CRC. */
14359                 intel_crtc_enable_pipe_crc(crtc);
14360         } else {
14361                 if (new_crtc_state->preload_luts &&
14362                     (new_crtc_state->uapi.color_mgmt_changed ||
14363                      new_crtc_state->update_pipe))
14364                         intel_color_load_luts(new_crtc_state);
14365
14366                 intel_pre_plane_update(old_crtc_state, new_crtc_state);
14367
14368                 if (new_crtc_state->update_pipe)
14369                         intel_encoders_update_pipe(state, crtc);
14370         }
14371
14372         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14373                 intel_fbc_disable(crtc);
14374         else if (new_plane_state)
14375                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14376
14377         /* Perform vblank evasion around commit operation */
14378         intel_pipe_update_start(new_crtc_state);
14379
14380         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14381
14382         if (INTEL_GEN(dev_priv) >= 9)
14383                 skl_update_planes_on_crtc(state, crtc);
14384         else
14385                 i9xx_update_planes_on_crtc(state, crtc);
14386
14387         intel_pipe_update_end(new_crtc_state);
14388
14389         /*
14390          * We usually enable FIFO underrun interrupts as part of the
14391          * CRTC enable sequence during modesets.  But when we inherit a
14392          * valid pipe configuration from the BIOS we need to take care
14393          * of enabling them on the CRTC's first fastset.
14394          */
14395         if (new_crtc_state->update_pipe && !modeset &&
14396             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14397                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14398 }
14399
14400 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
14401 {
14402         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
14403         enum transcoder slave_transcoder;
14404
14405         WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
14406
14407         slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
14408         return intel_get_crtc_for_pipe(dev_priv,
14409                                        (enum pipe)slave_transcoder);
14410 }
14411
14412 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
14413                                           struct intel_crtc_state *old_crtc_state,
14414                                           struct intel_crtc_state *new_crtc_state,
14415                                           struct intel_crtc *crtc)
14416 {
14417         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14418
14419         intel_crtc_disable_planes(state, crtc);
14420
14421         /*
14422          * We need to disable pipe CRC before disabling the pipe,
14423          * or we race against vblank off.
14424          */
14425         intel_crtc_disable_pipe_crc(crtc);
14426
14427         dev_priv->display.crtc_disable(state, crtc);
14428         crtc->active = false;
14429         intel_fbc_disable(crtc);
14430         intel_disable_shared_dpll(old_crtc_state);
14431
14432         /*
14433          * Underruns don't always raise interrupts,
14434          * so check manually.
14435          */
14436         intel_check_cpu_fifo_underruns(dev_priv);
14437         intel_check_pch_fifo_underruns(dev_priv);
14438
14439         /* FIXME unify this for all platforms */
14440         if (!new_crtc_state->hw.active &&
14441             !HAS_GMCH(dev_priv) &&
14442             dev_priv->display.initial_watermarks)
14443                 dev_priv->display.initial_watermarks(state, crtc);
14444 }
14445
14446 static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
14447                                                    struct intel_crtc *crtc,
14448                                                    struct intel_crtc_state *old_crtc_state,
14449                                                    struct intel_crtc_state *new_crtc_state)
14450 {
14451         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14452         struct intel_crtc_state *new_slave_crtc_state =
14453                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14454         struct intel_crtc_state *old_slave_crtc_state =
14455                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14456
14457         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14458                 !old_slave_crtc_state);
14459
14460         /* Disable Slave first */
14461         intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
14462         if (old_slave_crtc_state->hw.active)
14463                 intel_old_crtc_state_disables(state,
14464                                               old_slave_crtc_state,
14465                                               new_slave_crtc_state,
14466                                               slave_crtc);
14467
14468         /* Disable Master */
14469         intel_pre_plane_update(old_crtc_state, new_crtc_state);
14470         if (old_crtc_state->hw.active)
14471                 intel_old_crtc_state_disables(state,
14472                                               old_crtc_state,
14473                                               new_crtc_state,
14474                                               crtc);
14475 }
14476
14477 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
14478 {
14479         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14480         struct intel_crtc *crtc;
14481         int i;
14482
14483         /*
14484          * Disable CRTC/pipes in reverse order because some features(MST in
14485          * TGL+) requires master and slave relationship between pipes, so it
14486          * should always pick the lowest pipe as master as it will be enabled
14487          * first and disable in the reverse order so the master will be the
14488          * last one to be disabled.
14489          */
14490         for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
14491                                                     new_crtc_state, i) {
14492                 if (!needs_modeset(new_crtc_state))
14493                         continue;
14494
14495                 /* In case of Transcoder port Sync master slave CRTCs can be
14496                  * assigned in any order and we need to make sure that
14497                  * slave CRTCs are disabled first and then master CRTC since
14498                  * Slave vblanks are masked till Master Vblanks.
14499                  */
14500                 if (is_trans_port_sync_mode(new_crtc_state)) {
14501                         if (is_trans_port_sync_master(new_crtc_state))
14502                                 intel_trans_port_sync_modeset_disables(state,
14503                                                                        crtc,
14504                                                                        old_crtc_state,
14505                                                                        new_crtc_state);
14506                         else
14507                                 continue;
14508                 } else {
14509                         intel_pre_plane_update(old_crtc_state, new_crtc_state);
14510
14511                         if (old_crtc_state->hw.active)
14512                                 intel_old_crtc_state_disables(state,
14513                                                               old_crtc_state,
14514                                                               new_crtc_state,
14515                                                               crtc);
14516                 }
14517         }
14518 }
14519
14520 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
14521 {
14522         struct intel_crtc *crtc;
14523         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14524         int i;
14525
14526         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14527                 if (!new_crtc_state->hw.active)
14528                         continue;
14529
14530                 intel_update_crtc(crtc, state, old_crtc_state,
14531                                   new_crtc_state);
14532         }
14533 }
14534
14535 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
14536                                               struct intel_atomic_state *state,
14537                                               struct intel_crtc_state *new_crtc_state)
14538 {
14539         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14540
14541         intel_crtc_update_active_timings(new_crtc_state);
14542         dev_priv->display.crtc_enable(state, crtc);
14543         intel_crtc_enable_pipe_crc(crtc);
14544 }
14545
14546 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
14547                                        struct intel_atomic_state *state)
14548 {
14549         struct drm_connector *uninitialized_var(conn);
14550         struct drm_connector_state *conn_state;
14551         struct intel_dp *intel_dp;
14552         int i;
14553
14554         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
14555                 if (conn_state->crtc == &crtc->base)
14556                         break;
14557         }
14558         intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
14559         intel_dp_stop_link_train(intel_dp);
14560 }
14561
14562 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
14563                                            struct intel_atomic_state *state)
14564 {
14565         struct intel_crtc_state *new_crtc_state =
14566                 intel_atomic_get_new_crtc_state(state, crtc);
14567         struct intel_crtc_state *old_crtc_state =
14568                 intel_atomic_get_old_crtc_state(state, crtc);
14569         struct intel_plane_state *new_plane_state =
14570                 intel_atomic_get_new_plane_state(state,
14571                                                  to_intel_plane(crtc->base.primary));
14572         bool modeset = needs_modeset(new_crtc_state);
14573
14574         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14575                 intel_fbc_disable(crtc);
14576         else if (new_plane_state)
14577                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14578
14579         /* Perform vblank evasion around commit operation */
14580         intel_pipe_update_start(new_crtc_state);
14581         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14582         skl_update_planes_on_crtc(state, crtc);
14583         intel_pipe_update_end(new_crtc_state);
14584
14585         /*
14586          * We usually enable FIFO underrun interrupts as part of the
14587          * CRTC enable sequence during modesets.  But when we inherit a
14588          * valid pipe configuration from the BIOS we need to take care
14589          * of enabling them on the CRTC's first fastset.
14590          */
14591         if (new_crtc_state->update_pipe && !modeset &&
14592             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14593                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14594 }
14595
14596 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
14597                                                struct intel_atomic_state *state,
14598                                                struct intel_crtc_state *old_crtc_state,
14599                                                struct intel_crtc_state *new_crtc_state)
14600 {
14601         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14602         struct intel_crtc_state *new_slave_crtc_state =
14603                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14604         struct intel_crtc_state *old_slave_crtc_state =
14605                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14606
14607         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14608                 !old_slave_crtc_state);
14609
14610         DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
14611                       crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
14612                       slave_crtc->base.name);
14613
14614         /* Enable seq for slave with with DP_TP_CTL left Idle until the
14615          * master is ready
14616          */
14617         intel_crtc_enable_trans_port_sync(slave_crtc,
14618                                           state,
14619                                           new_slave_crtc_state);
14620
14621         /* Enable seq for master with with DP_TP_CTL left Idle */
14622         intel_crtc_enable_trans_port_sync(crtc,
14623                                           state,
14624                                           new_crtc_state);
14625
14626         /* Set Slave's DP_TP_CTL to Normal */
14627         intel_set_dp_tp_ctl_normal(slave_crtc,
14628                                    state);
14629
14630         /* Set Master's DP_TP_CTL To Normal */
14631         usleep_range(200, 400);
14632         intel_set_dp_tp_ctl_normal(crtc,
14633                                    state);
14634
14635         /* Now do the post crtc enable for all master and slaves */
14636         intel_post_crtc_enable_updates(slave_crtc,
14637                                        state);
14638         intel_post_crtc_enable_updates(crtc,
14639                                        state);
14640 }
14641
14642 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
14643 {
14644         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14645         struct intel_crtc *crtc;
14646         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14647         unsigned int updated = 0;
14648         bool progress;
14649         int i;
14650         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
14651         u8 required_slices = state->wm_results.ddb.enabled_slices;
14652         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
14653
14654         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
14655                 /* ignore allocations for crtc's that have been turned off. */
14656                 if (new_crtc_state->hw.active)
14657                         entries[i] = old_crtc_state->wm.skl.ddb;
14658
14659         /* If 2nd DBuf slice required, enable it here */
14660         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
14661                 icl_dbuf_slices_update(dev_priv, required_slices);
14662
14663         /*
14664          * Whenever the number of active pipes changes, we need to make sure we
14665          * update the pipes in the right order so that their ddb allocations
14666          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14667          * cause pipe underruns and other bad stuff.
14668          */
14669         do {
14670                 progress = false;
14671
14672                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14673                         enum pipe pipe = crtc->pipe;
14674                         bool vbl_wait = false;
14675                         bool modeset = needs_modeset(new_crtc_state);
14676
14677                         if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
14678                                 continue;
14679
14680                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
14681                                                         entries,
14682                                                         INTEL_NUM_PIPES(dev_priv), i))
14683                                 continue;
14684
14685                         updated |= BIT(pipe);
14686                         entries[i] = new_crtc_state->wm.skl.ddb;
14687
14688                         /*
14689                          * If this is an already active pipe, it's DDB changed,
14690                          * and this isn't the last pipe that needs updating
14691                          * then we need to wait for a vblank to pass for the
14692                          * new ddb allocation to take effect.
14693                          */
14694                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
14695                                                  &old_crtc_state->wm.skl.ddb) &&
14696                             !modeset &&
14697                             state->wm_results.dirty_pipes != updated)
14698                                 vbl_wait = true;
14699
14700                         if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
14701                                 if (is_trans_port_sync_master(new_crtc_state))
14702                                         intel_update_trans_port_sync_crtcs(crtc,
14703                                                                            state,
14704                                                                            old_crtc_state,
14705                                                                            new_crtc_state);
14706                                 else
14707                                         continue;
14708                         } else {
14709                                 intel_update_crtc(crtc, state, old_crtc_state,
14710                                                   new_crtc_state);
14711                         }
14712
14713                         if (vbl_wait)
14714                                 intel_wait_for_vblank(dev_priv, pipe);
14715
14716                         progress = true;
14717                 }
14718         } while (progress);
14719
14720         /* If 2nd DBuf slice is no more required disable it */
14721         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
14722                 icl_dbuf_slices_update(dev_priv, required_slices);
14723 }
14724
14725 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14726 {
14727         struct intel_atomic_state *state, *next;
14728         struct llist_node *freed;
14729
14730         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14731         llist_for_each_entry_safe(state, next, freed, freed)
14732                 drm_atomic_state_put(&state->base);
14733 }
14734
14735 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14736 {
14737         struct drm_i915_private *dev_priv =
14738                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14739
14740         intel_atomic_helper_free_state(dev_priv);
14741 }
14742
14743 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
14744 {
14745         struct wait_queue_entry wait_fence, wait_reset;
14746         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
14747
14748         init_wait_entry(&wait_fence, 0);
14749         init_wait_entry(&wait_reset, 0);
14750         for (;;) {
14751                 prepare_to_wait(&intel_state->commit_ready.wait,
14752                                 &wait_fence, TASK_UNINTERRUPTIBLE);
14753                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14754                                               I915_RESET_MODESET),
14755                                 &wait_reset, TASK_UNINTERRUPTIBLE);
14756
14757
14758                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
14759                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
14760                         break;
14761
14762                 schedule();
14763         }
14764         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
14765         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14766                                   I915_RESET_MODESET),
14767                     &wait_reset);
14768 }
14769
14770 static void intel_atomic_cleanup_work(struct work_struct *work)
14771 {
14772         struct drm_atomic_state *state =
14773                 container_of(work, struct drm_atomic_state, commit_work);
14774         struct drm_i915_private *i915 = to_i915(state->dev);
14775
14776         drm_atomic_helper_cleanup_planes(&i915->drm, state);
14777         drm_atomic_helper_commit_cleanup_done(state);
14778         drm_atomic_state_put(state);
14779
14780         intel_atomic_helper_free_state(i915);
14781 }
14782
14783 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
14784 {
14785         struct drm_device *dev = state->base.dev;
14786         struct drm_i915_private *dev_priv = to_i915(dev);
14787         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14788         struct intel_crtc *crtc;
14789         u64 put_domains[I915_MAX_PIPES] = {};
14790         intel_wakeref_t wakeref = 0;
14791         int i;
14792
14793         intel_atomic_commit_fence_wait(state);
14794
14795         drm_atomic_helper_wait_for_dependencies(&state->base);
14796
14797         if (state->modeset)
14798                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14799
14800         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14801                                             new_crtc_state, i) {
14802                 if (needs_modeset(new_crtc_state) ||
14803                     new_crtc_state->update_pipe) {
14804
14805                         put_domains[crtc->pipe] =
14806                                 modeset_get_crtc_power_domains(new_crtc_state);
14807                 }
14808         }
14809
14810         intel_commit_modeset_disables(state);
14811
14812         /* FIXME: Eventually get rid of our crtc->config pointer */
14813         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14814                 crtc->config = new_crtc_state;
14815
14816         if (state->modeset) {
14817                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14818
14819                 intel_set_cdclk_pre_plane_update(dev_priv,
14820                                                  &state->cdclk.actual,
14821                                                  &dev_priv->cdclk.actual,
14822                                                  state->cdclk.pipe);
14823
14824                 /*
14825                  * SKL workaround: bspec recommends we disable the SAGV when we
14826                  * have more then one pipe enabled
14827                  */
14828                 if (!intel_can_enable_sagv(state))
14829                         intel_disable_sagv(dev_priv);
14830
14831                 intel_modeset_verify_disabled(dev_priv, state);
14832         }
14833
14834         /* Complete the events for pipes that have now been disabled */
14835         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14836                 bool modeset = needs_modeset(new_crtc_state);
14837
14838                 /* Complete events for now disable pipes here. */
14839                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
14840                         spin_lock_irq(&dev->event_lock);
14841                         drm_crtc_send_vblank_event(&crtc->base,
14842                                                    new_crtc_state->uapi.event);
14843                         spin_unlock_irq(&dev->event_lock);
14844
14845                         new_crtc_state->uapi.event = NULL;
14846                 }
14847         }
14848
14849         if (state->modeset)
14850                 intel_encoders_update_prepare(state);
14851
14852         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14853         dev_priv->display.commit_modeset_enables(state);
14854
14855         if (state->modeset) {
14856                 intel_encoders_update_complete(state);
14857
14858                 intel_set_cdclk_post_plane_update(dev_priv,
14859                                                   &state->cdclk.actual,
14860                                                   &dev_priv->cdclk.actual,
14861                                                   state->cdclk.pipe);
14862         }
14863
14864         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14865          * already, but still need the state for the delayed optimization. To
14866          * fix this:
14867          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14868          * - schedule that vblank worker _before_ calling hw_done
14869          * - at the start of commit_tail, cancel it _synchrously
14870          * - switch over to the vblank wait helper in the core after that since
14871          *   we don't need out special handling any more.
14872          */
14873         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14874
14875         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14876                 if (new_crtc_state->hw.active &&
14877                     !needs_modeset(new_crtc_state) &&
14878                     !new_crtc_state->preload_luts &&
14879                     (new_crtc_state->uapi.color_mgmt_changed ||
14880                      new_crtc_state->update_pipe))
14881                         intel_color_load_luts(new_crtc_state);
14882         }
14883
14884         /*
14885          * Now that the vblank has passed, we can go ahead and program the
14886          * optimal watermarks on platforms that need two-step watermark
14887          * programming.
14888          *
14889          * TODO: Move this (and other cleanup) to an async worker eventually.
14890          */
14891         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14892                 if (dev_priv->display.optimize_watermarks)
14893                         dev_priv->display.optimize_watermarks(state, crtc);
14894         }
14895
14896         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14897                 intel_post_plane_update(old_crtc_state);
14898
14899                 if (put_domains[i])
14900                         modeset_put_power_domains(dev_priv, put_domains[i]);
14901
14902                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14903         }
14904
14905         if (state->modeset)
14906                 intel_verify_planes(state);
14907
14908         if (state->modeset && intel_can_enable_sagv(state))
14909                 intel_enable_sagv(dev_priv);
14910
14911         drm_atomic_helper_commit_hw_done(&state->base);
14912
14913         if (state->modeset) {
14914                 /* As one of the primary mmio accessors, KMS has a high
14915                  * likelihood of triggering bugs in unclaimed access. After we
14916                  * finish modesetting, see if an error has been flagged, and if
14917                  * so enable debugging for the next modeset - and hope we catch
14918                  * the culprit.
14919                  */
14920                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14921                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14922         }
14923         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14924
14925         /*
14926          * Defer the cleanup of the old state to a separate worker to not
14927          * impede the current task (userspace for blocking modesets) that
14928          * are executed inline. For out-of-line asynchronous modesets/flips,
14929          * deferring to a new worker seems overkill, but we would place a
14930          * schedule point (cond_resched()) here anyway to keep latencies
14931          * down.
14932          */
14933         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14934         queue_work(system_highpri_wq, &state->base.commit_work);
14935 }
14936
14937 static void intel_atomic_commit_work(struct work_struct *work)
14938 {
14939         struct intel_atomic_state *state =
14940                 container_of(work, struct intel_atomic_state, base.commit_work);
14941
14942         intel_atomic_commit_tail(state);
14943 }
14944
14945 static int __i915_sw_fence_call
14946 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14947                           enum i915_sw_fence_notify notify)
14948 {
14949         struct intel_atomic_state *state =
14950                 container_of(fence, struct intel_atomic_state, commit_ready);
14951
14952         switch (notify) {
14953         case FENCE_COMPLETE:
14954                 /* we do blocking waits in the worker, nothing to do here */
14955                 break;
14956         case FENCE_FREE:
14957                 {
14958                         struct intel_atomic_helper *helper =
14959                                 &to_i915(state->base.dev)->atomic_helper;
14960
14961                         if (llist_add(&state->freed, &helper->free_list))
14962                                 schedule_work(&helper->free_work);
14963                         break;
14964                 }
14965         }
14966
14967         return NOTIFY_DONE;
14968 }
14969
14970 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14971 {
14972         struct intel_plane_state *old_plane_state, *new_plane_state;
14973         struct intel_plane *plane;
14974         int i;
14975
14976         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14977                                              new_plane_state, i)
14978                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
14979                                         to_intel_frontbuffer(new_plane_state->hw.fb),
14980                                         plane->frontbuffer_bit);
14981 }
14982
14983 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
14984 {
14985         struct intel_crtc *crtc;
14986
14987         for_each_intel_crtc(&dev_priv->drm, crtc)
14988                 drm_modeset_lock_assert_held(&crtc->base.mutex);
14989 }
14990
14991 static int intel_atomic_commit(struct drm_device *dev,
14992                                struct drm_atomic_state *_state,
14993                                bool nonblock)
14994 {
14995         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14996         struct drm_i915_private *dev_priv = to_i915(dev);
14997         int ret = 0;
14998
14999         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15000
15001         drm_atomic_state_get(&state->base);
15002         i915_sw_fence_init(&state->commit_ready,
15003                            intel_atomic_commit_ready);
15004
15005         /*
15006          * The intel_legacy_cursor_update() fast path takes care
15007          * of avoiding the vblank waits for simple cursor
15008          * movement and flips. For cursor on/off and size changes,
15009          * we want to perform the vblank waits so that watermark
15010          * updates happen during the correct frames. Gen9+ have
15011          * double buffered watermarks and so shouldn't need this.
15012          *
15013          * Unset state->legacy_cursor_update before the call to
15014          * drm_atomic_helper_setup_commit() because otherwise
15015          * drm_atomic_helper_wait_for_flip_done() is a noop and
15016          * we get FIFO underruns because we didn't wait
15017          * for vblank.
15018          *
15019          * FIXME doing watermarks and fb cleanup from a vblank worker
15020          * (assuming we had any) would solve these problems.
15021          */
15022         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15023                 struct intel_crtc_state *new_crtc_state;
15024                 struct intel_crtc *crtc;
15025                 int i;
15026
15027                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15028                         if (new_crtc_state->wm.need_postvbl_update ||
15029                             new_crtc_state->update_wm_post)
15030                                 state->base.legacy_cursor_update = false;
15031         }
15032
15033         ret = intel_atomic_prepare_commit(state);
15034         if (ret) {
15035                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
15036                 i915_sw_fence_commit(&state->commit_ready);
15037                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15038                 return ret;
15039         }
15040
15041         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15042         if (!ret)
15043                 ret = drm_atomic_helper_swap_state(&state->base, true);
15044
15045         if (ret) {
15046                 i915_sw_fence_commit(&state->commit_ready);
15047
15048                 drm_atomic_helper_cleanup_planes(dev, &state->base);
15049                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15050                 return ret;
15051         }
15052         dev_priv->wm.distrust_bios_wm = false;
15053         intel_shared_dpll_swap_state(state);
15054         intel_atomic_track_fbs(state);
15055
15056         if (state->global_state_changed) {
15057                 assert_global_state_locked(dev_priv);
15058
15059                 memcpy(dev_priv->min_cdclk, state->min_cdclk,
15060                        sizeof(state->min_cdclk));
15061                 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
15062                        sizeof(state->min_voltage_level));
15063                 dev_priv->active_pipes = state->active_pipes;
15064                 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
15065
15066                 intel_cdclk_swap_state(state);
15067         }
15068
15069         drm_atomic_state_get(&state->base);
15070         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15071
15072         i915_sw_fence_commit(&state->commit_ready);
15073         if (nonblock && state->modeset) {
15074                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15075         } else if (nonblock) {
15076                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15077         } else {
15078                 if (state->modeset)
15079                         flush_workqueue(dev_priv->modeset_wq);
15080                 intel_atomic_commit_tail(state);
15081         }
15082
15083         return 0;
15084 }
15085
15086 struct wait_rps_boost {
15087         struct wait_queue_entry wait;
15088
15089         struct drm_crtc *crtc;
15090         struct i915_request *request;
15091 };
15092
15093 static int do_rps_boost(struct wait_queue_entry *_wait,
15094                         unsigned mode, int sync, void *key)
15095 {
15096         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15097         struct i915_request *rq = wait->request;
15098
15099         /*
15100          * If we missed the vblank, but the request is already running it
15101          * is reasonable to assume that it will complete before the next
15102          * vblank without our intervention, so leave RPS alone.
15103          */
15104         if (!i915_request_started(rq))
15105                 intel_rps_boost(rq);
15106         i915_request_put(rq);
15107
15108         drm_crtc_vblank_put(wait->crtc);
15109
15110         list_del(&wait->wait.entry);
15111         kfree(wait);
15112         return 1;
15113 }
15114
15115 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15116                                        struct dma_fence *fence)
15117 {
15118         struct wait_rps_boost *wait;
15119
15120         if (!dma_fence_is_i915(fence))
15121                 return;
15122
15123         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15124                 return;
15125
15126         if (drm_crtc_vblank_get(crtc))
15127                 return;
15128
15129         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15130         if (!wait) {
15131                 drm_crtc_vblank_put(crtc);
15132                 return;
15133         }
15134
15135         wait->request = to_request(dma_fence_get(fence));
15136         wait->crtc = crtc;
15137
15138         wait->wait.func = do_rps_boost;
15139         wait->wait.flags = 0;
15140
15141         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15142 }
15143
15144 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15145 {
15146         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15147         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15148         struct drm_framebuffer *fb = plane_state->hw.fb;
15149         struct i915_vma *vma;
15150
15151         if (plane->id == PLANE_CURSOR &&
15152             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15153                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15154                 const int align = intel_cursor_alignment(dev_priv);
15155                 int err;
15156
15157                 err = i915_gem_object_attach_phys(obj, align);
15158                 if (err)
15159                         return err;
15160         }
15161
15162         vma = intel_pin_and_fence_fb_obj(fb,
15163                                          &plane_state->view,
15164                                          intel_plane_uses_fence(plane_state),
15165                                          &plane_state->flags);
15166         if (IS_ERR(vma))
15167                 return PTR_ERR(vma);
15168
15169         plane_state->vma = vma;
15170
15171         return 0;
15172 }
15173
15174 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15175 {
15176         struct i915_vma *vma;
15177
15178         vma = fetch_and_zero(&old_plane_state->vma);
15179         if (vma)
15180                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15181 }
15182
15183 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15184 {
15185         struct i915_sched_attr attr = {
15186                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15187         };
15188
15189         i915_gem_object_wait_priority(obj, 0, &attr);
15190 }
15191
15192 /**
15193  * intel_prepare_plane_fb - Prepare fb for usage on plane
15194  * @plane: drm plane to prepare for
15195  * @_new_plane_state: the plane state being prepared
15196  *
15197  * Prepares a framebuffer for usage on a display plane.  Generally this
15198  * involves pinning the underlying object and updating the frontbuffer tracking
15199  * bits.  Some older platforms need special physical address handling for
15200  * cursor planes.
15201  *
15202  * Returns 0 on success, negative error code on failure.
15203  */
15204 int
15205 intel_prepare_plane_fb(struct drm_plane *plane,
15206                        struct drm_plane_state *_new_plane_state)
15207 {
15208         struct intel_plane_state *new_plane_state =
15209                 to_intel_plane_state(_new_plane_state);
15210         struct intel_atomic_state *intel_state =
15211                 to_intel_atomic_state(new_plane_state->uapi.state);
15212         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15213         struct drm_framebuffer *fb = new_plane_state->hw.fb;
15214         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15215         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
15216         int ret;
15217
15218         if (old_obj) {
15219                 struct intel_crtc_state *crtc_state =
15220                         intel_atomic_get_new_crtc_state(intel_state,
15221                                                         to_intel_crtc(plane->state->crtc));
15222
15223                 /* Big Hammer, we also need to ensure that any pending
15224                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15225                  * current scanout is retired before unpinning the old
15226                  * framebuffer. Note that we rely on userspace rendering
15227                  * into the buffer attached to the pipe they are waiting
15228                  * on. If not, userspace generates a GPU hang with IPEHR
15229                  * point to the MI_WAIT_FOR_EVENT.
15230                  *
15231                  * This should only fail upon a hung GPU, in which case we
15232                  * can safely continue.
15233                  */
15234                 if (needs_modeset(crtc_state)) {
15235                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15236                                                               old_obj->base.resv, NULL,
15237                                                               false, 0,
15238                                                               GFP_KERNEL);
15239                         if (ret < 0)
15240                                 return ret;
15241                 }
15242         }
15243
15244         if (new_plane_state->uapi.fence) { /* explicit fencing */
15245                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
15246                                                     new_plane_state->uapi.fence,
15247                                                     I915_FENCE_TIMEOUT,
15248                                                     GFP_KERNEL);
15249                 if (ret < 0)
15250                         return ret;
15251         }
15252
15253         if (!obj)
15254                 return 0;
15255
15256         ret = i915_gem_object_pin_pages(obj);
15257         if (ret)
15258                 return ret;
15259
15260         ret = intel_plane_pin_fb(new_plane_state);
15261
15262         i915_gem_object_unpin_pages(obj);
15263         if (ret)
15264                 return ret;
15265
15266         fb_obj_bump_render_priority(obj);
15267         intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
15268
15269         if (!new_plane_state->uapi.fence) { /* implicit fencing */
15270                 struct dma_fence *fence;
15271
15272                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15273                                                       obj->base.resv, NULL,
15274                                                       false, I915_FENCE_TIMEOUT,
15275                                                       GFP_KERNEL);
15276                 if (ret < 0)
15277                         return ret;
15278
15279                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15280                 if (fence) {
15281                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15282                                                    fence);
15283                         dma_fence_put(fence);
15284                 }
15285         } else {
15286                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15287                                            new_plane_state->uapi.fence);
15288         }
15289
15290         /*
15291          * We declare pageflips to be interactive and so merit a small bias
15292          * towards upclocking to deliver the frame on time. By only changing
15293          * the RPS thresholds to sample more regularly and aim for higher
15294          * clocks we can hopefully deliver low power workloads (like kodi)
15295          * that are not quite steady state without resorting to forcing
15296          * maximum clocks following a vblank miss (see do_rps_boost()).
15297          */
15298         if (!intel_state->rps_interactive) {
15299                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15300                 intel_state->rps_interactive = true;
15301         }
15302
15303         return 0;
15304 }
15305
15306 /**
15307  * intel_cleanup_plane_fb - Cleans up an fb after plane use
15308  * @plane: drm plane to clean up for
15309  * @_old_plane_state: the state from the previous modeset
15310  *
15311  * Cleans up a framebuffer that has just been removed from a plane.
15312  */
15313 void
15314 intel_cleanup_plane_fb(struct drm_plane *plane,
15315                        struct drm_plane_state *_old_plane_state)
15316 {
15317         struct intel_plane_state *old_plane_state =
15318                 to_intel_plane_state(_old_plane_state);
15319         struct intel_atomic_state *intel_state =
15320                 to_intel_atomic_state(old_plane_state->uapi.state);
15321         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15322
15323         if (intel_state->rps_interactive) {
15324                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15325                 intel_state->rps_interactive = false;
15326         }
15327
15328         /* Should only be called after a successful intel_prepare_plane_fb()! */
15329         intel_plane_unpin_fb(old_plane_state);
15330 }
15331
15332 /**
15333  * intel_plane_destroy - destroy a plane
15334  * @plane: plane to destroy
15335  *
15336  * Common destruction function for all types of planes (primary, cursor,
15337  * sprite).
15338  */
15339 void intel_plane_destroy(struct drm_plane *plane)
15340 {
15341         drm_plane_cleanup(plane);
15342         kfree(to_intel_plane(plane));
15343 }
15344
15345 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15346                                             u32 format, u64 modifier)
15347 {
15348         switch (modifier) {
15349         case DRM_FORMAT_MOD_LINEAR:
15350         case I915_FORMAT_MOD_X_TILED:
15351                 break;
15352         default:
15353                 return false;
15354         }
15355
15356         switch (format) {
15357         case DRM_FORMAT_C8:
15358         case DRM_FORMAT_RGB565:
15359         case DRM_FORMAT_XRGB1555:
15360         case DRM_FORMAT_XRGB8888:
15361                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15362                         modifier == I915_FORMAT_MOD_X_TILED;
15363         default:
15364                 return false;
15365         }
15366 }
15367
15368 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15369                                             u32 format, u64 modifier)
15370 {
15371         switch (modifier) {
15372         case DRM_FORMAT_MOD_LINEAR:
15373         case I915_FORMAT_MOD_X_TILED:
15374                 break;
15375         default:
15376                 return false;
15377         }
15378
15379         switch (format) {
15380         case DRM_FORMAT_C8:
15381         case DRM_FORMAT_RGB565:
15382         case DRM_FORMAT_XRGB8888:
15383         case DRM_FORMAT_XBGR8888:
15384         case DRM_FORMAT_ARGB8888:
15385         case DRM_FORMAT_ABGR8888:
15386         case DRM_FORMAT_XRGB2101010:
15387         case DRM_FORMAT_XBGR2101010:
15388         case DRM_FORMAT_ARGB2101010:
15389         case DRM_FORMAT_ABGR2101010:
15390         case DRM_FORMAT_XBGR16161616F:
15391                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15392                         modifier == I915_FORMAT_MOD_X_TILED;
15393         default:
15394                 return false;
15395         }
15396 }
15397
15398 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15399                                               u32 format, u64 modifier)
15400 {
15401         return modifier == DRM_FORMAT_MOD_LINEAR &&
15402                 format == DRM_FORMAT_ARGB8888;
15403 }
15404
15405 static const struct drm_plane_funcs i965_plane_funcs = {
15406         .update_plane = drm_atomic_helper_update_plane,
15407         .disable_plane = drm_atomic_helper_disable_plane,
15408         .destroy = intel_plane_destroy,
15409         .atomic_duplicate_state = intel_plane_duplicate_state,
15410         .atomic_destroy_state = intel_plane_destroy_state,
15411         .format_mod_supported = i965_plane_format_mod_supported,
15412 };
15413
15414 static const struct drm_plane_funcs i8xx_plane_funcs = {
15415         .update_plane = drm_atomic_helper_update_plane,
15416         .disable_plane = drm_atomic_helper_disable_plane,
15417         .destroy = intel_plane_destroy,
15418         .atomic_duplicate_state = intel_plane_duplicate_state,
15419         .atomic_destroy_state = intel_plane_destroy_state,
15420         .format_mod_supported = i8xx_plane_format_mod_supported,
15421 };
15422
15423 static int
15424 intel_legacy_cursor_update(struct drm_plane *_plane,
15425                            struct drm_crtc *_crtc,
15426                            struct drm_framebuffer *fb,
15427                            int crtc_x, int crtc_y,
15428                            unsigned int crtc_w, unsigned int crtc_h,
15429                            u32 src_x, u32 src_y,
15430                            u32 src_w, u32 src_h,
15431                            struct drm_modeset_acquire_ctx *ctx)
15432 {
15433         struct intel_plane *plane = to_intel_plane(_plane);
15434         struct intel_crtc *crtc = to_intel_crtc(_crtc);
15435         struct intel_plane_state *old_plane_state =
15436                 to_intel_plane_state(plane->base.state);
15437         struct intel_plane_state *new_plane_state;
15438         struct intel_crtc_state *crtc_state =
15439                 to_intel_crtc_state(crtc->base.state);
15440         struct intel_crtc_state *new_crtc_state;
15441         int ret;
15442
15443         /*
15444          * When crtc is inactive or there is a modeset pending,
15445          * wait for it to complete in the slowpath
15446          */
15447         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
15448             crtc_state->update_pipe)
15449                 goto slow;
15450
15451         /*
15452          * Don't do an async update if there is an outstanding commit modifying
15453          * the plane.  This prevents our async update's changes from getting
15454          * overridden by a previous synchronous update's state.
15455          */
15456         if (old_plane_state->uapi.commit &&
15457             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
15458                 goto slow;
15459
15460         /*
15461          * If any parameters change that may affect watermarks,
15462          * take the slowpath. Only changing fb or position should be
15463          * in the fastpath.
15464          */
15465         if (old_plane_state->uapi.crtc != &crtc->base ||
15466             old_plane_state->uapi.src_w != src_w ||
15467             old_plane_state->uapi.src_h != src_h ||
15468             old_plane_state->uapi.crtc_w != crtc_w ||
15469             old_plane_state->uapi.crtc_h != crtc_h ||
15470             !old_plane_state->uapi.fb != !fb)
15471                 goto slow;
15472
15473         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
15474         if (!new_plane_state)
15475                 return -ENOMEM;
15476
15477         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
15478         if (!new_crtc_state) {
15479                 ret = -ENOMEM;
15480                 goto out_free;
15481         }
15482
15483         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
15484
15485         new_plane_state->uapi.src_x = src_x;
15486         new_plane_state->uapi.src_y = src_y;
15487         new_plane_state->uapi.src_w = src_w;
15488         new_plane_state->uapi.src_h = src_h;
15489         new_plane_state->uapi.crtc_x = crtc_x;
15490         new_plane_state->uapi.crtc_y = crtc_y;
15491         new_plane_state->uapi.crtc_w = crtc_w;
15492         new_plane_state->uapi.crtc_h = crtc_h;
15493
15494         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
15495                                                   old_plane_state, new_plane_state);
15496         if (ret)
15497                 goto out_free;
15498
15499         ret = intel_plane_pin_fb(new_plane_state);
15500         if (ret)
15501                 goto out_free;
15502
15503         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
15504                                 ORIGIN_FLIP);
15505         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15506                                 to_intel_frontbuffer(new_plane_state->hw.fb),
15507                                 plane->frontbuffer_bit);
15508
15509         /* Swap plane state */
15510         plane->base.state = &new_plane_state->uapi;
15511
15512         /*
15513          * We cannot swap crtc_state as it may be in use by an atomic commit or
15514          * page flip that's running simultaneously. If we swap crtc_state and
15515          * destroy the old state, we will cause a use-after-free there.
15516          *
15517          * Only update active_planes, which is needed for our internal
15518          * bookkeeping. Either value will do the right thing when updating
15519          * planes atomically. If the cursor was part of the atomic update then
15520          * we would have taken the slowpath.
15521          */
15522         crtc_state->active_planes = new_crtc_state->active_planes;
15523
15524         if (new_plane_state->uapi.visible)
15525                 intel_update_plane(plane, crtc_state, new_plane_state);
15526         else
15527                 intel_disable_plane(plane, crtc_state);
15528
15529         intel_plane_unpin_fb(old_plane_state);
15530
15531 out_free:
15532         if (new_crtc_state)
15533                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
15534         if (ret)
15535                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
15536         else
15537                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
15538         return ret;
15539
15540 slow:
15541         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
15542                                               crtc_x, crtc_y, crtc_w, crtc_h,
15543                                               src_x, src_y, src_w, src_h, ctx);
15544 }
15545
15546 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15547         .update_plane = intel_legacy_cursor_update,
15548         .disable_plane = drm_atomic_helper_disable_plane,
15549         .destroy = intel_plane_destroy,
15550         .atomic_duplicate_state = intel_plane_duplicate_state,
15551         .atomic_destroy_state = intel_plane_destroy_state,
15552         .format_mod_supported = intel_cursor_format_mod_supported,
15553 };
15554
15555 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
15556                                enum i9xx_plane_id i9xx_plane)
15557 {
15558         if (!HAS_FBC(dev_priv))
15559                 return false;
15560
15561         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15562                 return i9xx_plane == PLANE_A; /* tied to pipe A */
15563         else if (IS_IVYBRIDGE(dev_priv))
15564                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
15565                         i9xx_plane == PLANE_C;
15566         else if (INTEL_GEN(dev_priv) >= 4)
15567                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
15568         else
15569                 return i9xx_plane == PLANE_A;
15570 }
15571
15572 static struct intel_plane *
15573 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15574 {
15575         struct intel_plane *plane;
15576         const struct drm_plane_funcs *plane_funcs;
15577         unsigned int supported_rotations;
15578         unsigned int possible_crtcs;
15579         const u32 *formats;
15580         int num_formats;
15581         int ret, zpos;
15582
15583         if (INTEL_GEN(dev_priv) >= 9)
15584                 return skl_universal_plane_create(dev_priv, pipe,
15585                                                   PLANE_PRIMARY);
15586
15587         plane = intel_plane_alloc();
15588         if (IS_ERR(plane))
15589                 return plane;
15590
15591         plane->pipe = pipe;
15592         /*
15593          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15594          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15595          */
15596         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15597                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
15598         else
15599                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
15600         plane->id = PLANE_PRIMARY;
15601         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
15602
15603         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
15604         if (plane->has_fbc) {
15605                 struct intel_fbc *fbc = &dev_priv->fbc;
15606
15607                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
15608         }
15609
15610         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15611                 formats = vlv_primary_formats;
15612                 num_formats = ARRAY_SIZE(vlv_primary_formats);
15613         } else if (INTEL_GEN(dev_priv) >= 4) {
15614                 /*
15615                  * WaFP16GammaEnabling:ivb
15616                  * "Workaround : When using the 64-bit format, the plane
15617                  *  output on each color channel has one quarter amplitude.
15618                  *  It can be brought up to full amplitude by using pipe
15619                  *  gamma correction or pipe color space conversion to
15620                  *  multiply the plane output by four."
15621                  *
15622                  * There is no dedicated plane gamma for the primary plane,
15623                  * and using the pipe gamma/csc could conflict with other
15624                  * planes, so we choose not to expose fp16 on IVB primary
15625                  * planes. HSW primary planes no longer have this problem.
15626                  */
15627                 if (IS_IVYBRIDGE(dev_priv)) {
15628                         formats = ivb_primary_formats;
15629                         num_formats = ARRAY_SIZE(ivb_primary_formats);
15630                 } else {
15631                         formats = i965_primary_formats;
15632                         num_formats = ARRAY_SIZE(i965_primary_formats);
15633                 }
15634         } else {
15635                 formats = i8xx_primary_formats;
15636                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15637         }
15638
15639         if (INTEL_GEN(dev_priv) >= 4)
15640                 plane_funcs = &i965_plane_funcs;
15641         else
15642                 plane_funcs = &i8xx_plane_funcs;
15643
15644         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15645                 plane->min_cdclk = vlv_plane_min_cdclk;
15646         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15647                 plane->min_cdclk = hsw_plane_min_cdclk;
15648         else if (IS_IVYBRIDGE(dev_priv))
15649                 plane->min_cdclk = ivb_plane_min_cdclk;
15650         else
15651                 plane->min_cdclk = i9xx_plane_min_cdclk;
15652
15653         plane->max_stride = i9xx_plane_max_stride;
15654         plane->update_plane = i9xx_update_plane;
15655         plane->disable_plane = i9xx_disable_plane;
15656         plane->get_hw_state = i9xx_plane_get_hw_state;
15657         plane->check_plane = i9xx_plane_check;
15658
15659         possible_crtcs = BIT(pipe);
15660
15661         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15662                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15663                                                possible_crtcs, plane_funcs,
15664                                                formats, num_formats,
15665                                                i9xx_format_modifiers,
15666                                                DRM_PLANE_TYPE_PRIMARY,
15667                                                "primary %c", pipe_name(pipe));
15668         else
15669                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15670                                                possible_crtcs, plane_funcs,
15671                                                formats, num_formats,
15672                                                i9xx_format_modifiers,
15673                                                DRM_PLANE_TYPE_PRIMARY,
15674                                                "plane %c",
15675                                                plane_name(plane->i9xx_plane));
15676         if (ret)
15677                 goto fail;
15678
15679         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15680                 supported_rotations =
15681                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
15682                         DRM_MODE_REFLECT_X;
15683         } else if (INTEL_GEN(dev_priv) >= 4) {
15684                 supported_rotations =
15685                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
15686         } else {
15687                 supported_rotations = DRM_MODE_ROTATE_0;
15688         }
15689
15690         if (INTEL_GEN(dev_priv) >= 4)
15691                 drm_plane_create_rotation_property(&plane->base,
15692                                                    DRM_MODE_ROTATE_0,
15693                                                    supported_rotations);
15694
15695         zpos = 0;
15696         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
15697
15698         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
15699
15700         return plane;
15701
15702 fail:
15703         intel_plane_free(plane);
15704
15705         return ERR_PTR(ret);
15706 }
15707
15708 static struct intel_plane *
15709 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
15710                           enum pipe pipe)
15711 {
15712         unsigned int possible_crtcs;
15713         struct intel_plane *cursor;
15714         int ret, zpos;
15715
15716         cursor = intel_plane_alloc();
15717         if (IS_ERR(cursor))
15718                 return cursor;
15719
15720         cursor->pipe = pipe;
15721         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15722         cursor->id = PLANE_CURSOR;
15723         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15724
15725         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15726                 cursor->max_stride = i845_cursor_max_stride;
15727                 cursor->update_plane = i845_update_cursor;
15728                 cursor->disable_plane = i845_disable_cursor;
15729                 cursor->get_hw_state = i845_cursor_get_hw_state;
15730                 cursor->check_plane = i845_check_cursor;
15731         } else {
15732                 cursor->max_stride = i9xx_cursor_max_stride;
15733                 cursor->update_plane = i9xx_update_cursor;
15734                 cursor->disable_plane = i9xx_disable_cursor;
15735                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15736                 cursor->check_plane = i9xx_check_cursor;
15737         }
15738
15739         cursor->cursor.base = ~0;
15740         cursor->cursor.cntl = ~0;
15741
15742         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15743                 cursor->cursor.size = ~0;
15744
15745         possible_crtcs = BIT(pipe);
15746
15747         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15748                                        possible_crtcs, &intel_cursor_plane_funcs,
15749                                        intel_cursor_formats,
15750                                        ARRAY_SIZE(intel_cursor_formats),
15751                                        cursor_format_modifiers,
15752                                        DRM_PLANE_TYPE_CURSOR,
15753                                        "cursor %c", pipe_name(pipe));
15754         if (ret)
15755                 goto fail;
15756
15757         if (INTEL_GEN(dev_priv) >= 4)
15758                 drm_plane_create_rotation_property(&cursor->base,
15759                                                    DRM_MODE_ROTATE_0,
15760                                                    DRM_MODE_ROTATE_0 |
15761                                                    DRM_MODE_ROTATE_180);
15762
15763         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15764         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15765
15766         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15767
15768         return cursor;
15769
15770 fail:
15771         intel_plane_free(cursor);
15772
15773         return ERR_PTR(ret);
15774 }
15775
15776 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15777                                     struct intel_crtc_state *crtc_state)
15778 {
15779         struct intel_crtc_scaler_state *scaler_state =
15780                 &crtc_state->scaler_state;
15781         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15782         int i;
15783
15784         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
15785         if (!crtc->num_scalers)
15786                 return;
15787
15788         for (i = 0; i < crtc->num_scalers; i++) {
15789                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15790
15791                 scaler->in_use = 0;
15792                 scaler->mode = 0;
15793         }
15794
15795         scaler_state->scaler_id = -1;
15796 }
15797
15798 #define INTEL_CRTC_FUNCS \
15799         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15800         .set_config = drm_atomic_helper_set_config, \
15801         .destroy = intel_crtc_destroy, \
15802         .page_flip = drm_atomic_helper_page_flip, \
15803         .atomic_duplicate_state = intel_crtc_duplicate_state, \
15804         .atomic_destroy_state = intel_crtc_destroy_state, \
15805         .set_crc_source = intel_crtc_set_crc_source, \
15806         .verify_crc_source = intel_crtc_verify_crc_source, \
15807         .get_crc_sources = intel_crtc_get_crc_sources
15808
15809 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15810         INTEL_CRTC_FUNCS,
15811
15812         .get_vblank_counter = g4x_get_vblank_counter,
15813         .enable_vblank = bdw_enable_vblank,
15814         .disable_vblank = bdw_disable_vblank,
15815 };
15816
15817 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15818         INTEL_CRTC_FUNCS,
15819
15820         .get_vblank_counter = g4x_get_vblank_counter,
15821         .enable_vblank = ilk_enable_vblank,
15822         .disable_vblank = ilk_disable_vblank,
15823 };
15824
15825 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15826         INTEL_CRTC_FUNCS,
15827
15828         .get_vblank_counter = g4x_get_vblank_counter,
15829         .enable_vblank = i965_enable_vblank,
15830         .disable_vblank = i965_disable_vblank,
15831 };
15832
15833 static const struct drm_crtc_funcs i965_crtc_funcs = {
15834         INTEL_CRTC_FUNCS,
15835
15836         .get_vblank_counter = i915_get_vblank_counter,
15837         .enable_vblank = i965_enable_vblank,
15838         .disable_vblank = i965_disable_vblank,
15839 };
15840
15841 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
15842         INTEL_CRTC_FUNCS,
15843
15844         .get_vblank_counter = i915_get_vblank_counter,
15845         .enable_vblank = i915gm_enable_vblank,
15846         .disable_vblank = i915gm_disable_vblank,
15847 };
15848
15849 static const struct drm_crtc_funcs i915_crtc_funcs = {
15850         INTEL_CRTC_FUNCS,
15851
15852         .get_vblank_counter = i915_get_vblank_counter,
15853         .enable_vblank = i8xx_enable_vblank,
15854         .disable_vblank = i8xx_disable_vblank,
15855 };
15856
15857 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15858         INTEL_CRTC_FUNCS,
15859
15860         /* no hw vblank counter */
15861         .enable_vblank = i8xx_enable_vblank,
15862         .disable_vblank = i8xx_disable_vblank,
15863 };
15864
15865 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15866 {
15867         const struct drm_crtc_funcs *funcs;
15868         struct intel_crtc *intel_crtc;
15869         struct intel_crtc_state *crtc_state = NULL;
15870         struct intel_plane *primary = NULL;
15871         struct intel_plane *cursor = NULL;
15872         int sprite, ret;
15873
15874         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15875         if (!intel_crtc)
15876                 return -ENOMEM;
15877
15878         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15879         if (!crtc_state) {
15880                 ret = -ENOMEM;
15881                 goto fail;
15882         }
15883         __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
15884         intel_crtc->config = crtc_state;
15885
15886         primary = intel_primary_plane_create(dev_priv, pipe);
15887         if (IS_ERR(primary)) {
15888                 ret = PTR_ERR(primary);
15889                 goto fail;
15890         }
15891         intel_crtc->plane_ids_mask |= BIT(primary->id);
15892
15893         for_each_sprite(dev_priv, pipe, sprite) {
15894                 struct intel_plane *plane;
15895
15896                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15897                 if (IS_ERR(plane)) {
15898                         ret = PTR_ERR(plane);
15899                         goto fail;
15900                 }
15901                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15902         }
15903
15904         cursor = intel_cursor_plane_create(dev_priv, pipe);
15905         if (IS_ERR(cursor)) {
15906                 ret = PTR_ERR(cursor);
15907                 goto fail;
15908         }
15909         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15910
15911         if (HAS_GMCH(dev_priv)) {
15912                 if (IS_CHERRYVIEW(dev_priv) ||
15913                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15914                         funcs = &g4x_crtc_funcs;
15915                 else if (IS_GEN(dev_priv, 4))
15916                         funcs = &i965_crtc_funcs;
15917                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
15918                         funcs = &i915gm_crtc_funcs;
15919                 else if (IS_GEN(dev_priv, 3))
15920                         funcs = &i915_crtc_funcs;
15921                 else
15922                         funcs = &i8xx_crtc_funcs;
15923         } else {
15924                 if (INTEL_GEN(dev_priv) >= 8)
15925                         funcs = &bdw_crtc_funcs;
15926                 else
15927                         funcs = &ilk_crtc_funcs;
15928         }
15929
15930         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15931                                         &primary->base, &cursor->base,
15932                                         funcs, "pipe %c", pipe_name(pipe));
15933         if (ret)
15934                 goto fail;
15935
15936         intel_crtc->pipe = pipe;
15937
15938         /* initialize shared scalers */
15939         intel_crtc_init_scalers(intel_crtc, crtc_state);
15940
15941         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15942                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15943         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
15944
15945         if (INTEL_GEN(dev_priv) < 9) {
15946                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15947
15948                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15949                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15950                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
15951         }
15952
15953         intel_color_init(intel_crtc);
15954
15955         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15956
15957         return 0;
15958
15959 fail:
15960         /*
15961          * drm_mode_config_cleanup() will free up any
15962          * crtcs/planes already initialized.
15963          */
15964         kfree(crtc_state);
15965         kfree(intel_crtc);
15966
15967         return ret;
15968 }
15969
15970 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15971                                       struct drm_file *file)
15972 {
15973         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15974         struct drm_crtc *drmmode_crtc;
15975         struct intel_crtc *crtc;
15976
15977         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15978         if (!drmmode_crtc)
15979                 return -ENOENT;
15980
15981         crtc = to_intel_crtc(drmmode_crtc);
15982         pipe_from_crtc_id->pipe = crtc->pipe;
15983
15984         return 0;
15985 }
15986
15987 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
15988 {
15989         struct drm_device *dev = encoder->base.dev;
15990         struct intel_encoder *source_encoder;
15991         u32 possible_clones = 0;
15992
15993         for_each_intel_encoder(dev, source_encoder) {
15994                 if (encoders_cloneable(encoder, source_encoder))
15995                         possible_clones |= drm_encoder_mask(&source_encoder->base);
15996         }
15997
15998         return possible_clones;
15999 }
16000
16001 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
16002 {
16003         struct drm_device *dev = encoder->base.dev;
16004         struct intel_crtc *crtc;
16005         u32 possible_crtcs = 0;
16006
16007         for_each_intel_crtc(dev, crtc) {
16008                 if (encoder->pipe_mask & BIT(crtc->pipe))
16009                         possible_crtcs |= drm_crtc_mask(&crtc->base);
16010         }
16011
16012         return possible_crtcs;
16013 }
16014
16015 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16016 {
16017         if (!IS_MOBILE(dev_priv))
16018                 return false;
16019
16020         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
16021                 return false;
16022
16023         if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
16024                 return false;
16025
16026         return true;
16027 }
16028
16029 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16030 {
16031         if (INTEL_GEN(dev_priv) >= 9)
16032                 return false;
16033
16034         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16035                 return false;
16036
16037         if (HAS_PCH_LPT_H(dev_priv) &&
16038             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16039                 return false;
16040
16041         /* DDI E can't be used if DDI A requires 4 lanes */
16042         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16043                 return false;
16044
16045         if (!dev_priv->vbt.int_crt_support)
16046                 return false;
16047
16048         return true;
16049 }
16050
16051 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16052 {
16053         int pps_num;
16054         int pps_idx;
16055
16056         if (HAS_DDI(dev_priv))
16057                 return;
16058         /*
16059          * This w/a is needed at least on CPT/PPT, but to be sure apply it
16060          * everywhere where registers can be write protected.
16061          */
16062         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16063                 pps_num = 2;
16064         else
16065                 pps_num = 1;
16066
16067         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16068                 u32 val = I915_READ(PP_CONTROL(pps_idx));
16069
16070                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16071                 I915_WRITE(PP_CONTROL(pps_idx), val);
16072         }
16073 }
16074
16075 static void intel_pps_init(struct drm_i915_private *dev_priv)
16076 {
16077         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16078                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16079         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16080                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16081         else
16082                 dev_priv->pps_mmio_base = PPS_BASE;
16083
16084         intel_pps_unlock_regs_wa(dev_priv);
16085 }
16086
16087 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16088 {
16089         struct intel_encoder *encoder;
16090         bool dpd_is_edp = false;
16091
16092         intel_pps_init(dev_priv);
16093
16094         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16095                 return;
16096
16097         if (INTEL_GEN(dev_priv) >= 12) {
16098                 intel_ddi_init(dev_priv, PORT_A);
16099                 intel_ddi_init(dev_priv, PORT_B);
16100                 intel_ddi_init(dev_priv, PORT_D);
16101                 intel_ddi_init(dev_priv, PORT_E);
16102                 intel_ddi_init(dev_priv, PORT_F);
16103                 intel_ddi_init(dev_priv, PORT_G);
16104                 intel_ddi_init(dev_priv, PORT_H);
16105                 intel_ddi_init(dev_priv, PORT_I);
16106                 icl_dsi_init(dev_priv);
16107         } else if (IS_ELKHARTLAKE(dev_priv)) {
16108                 intel_ddi_init(dev_priv, PORT_A);
16109                 intel_ddi_init(dev_priv, PORT_B);
16110                 intel_ddi_init(dev_priv, PORT_C);
16111                 intel_ddi_init(dev_priv, PORT_D);
16112                 icl_dsi_init(dev_priv);
16113         } else if (IS_GEN(dev_priv, 11)) {
16114                 intel_ddi_init(dev_priv, PORT_A);
16115                 intel_ddi_init(dev_priv, PORT_B);
16116                 intel_ddi_init(dev_priv, PORT_C);
16117                 intel_ddi_init(dev_priv, PORT_D);
16118                 intel_ddi_init(dev_priv, PORT_E);
16119                 /*
16120                  * On some ICL SKUs port F is not present. No strap bits for
16121                  * this, so rely on VBT.
16122                  * Work around broken VBTs on SKUs known to have no port F.
16123                  */
16124                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16125                     intel_bios_is_port_present(dev_priv, PORT_F))
16126                         intel_ddi_init(dev_priv, PORT_F);
16127
16128                 icl_dsi_init(dev_priv);
16129         } else if (IS_GEN9_LP(dev_priv)) {
16130                 /*
16131                  * FIXME: Broxton doesn't support port detection via the
16132                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16133                  * detect the ports.
16134                  */
16135                 intel_ddi_init(dev_priv, PORT_A);
16136                 intel_ddi_init(dev_priv, PORT_B);
16137                 intel_ddi_init(dev_priv, PORT_C);
16138
16139                 vlv_dsi_init(dev_priv);
16140         } else if (HAS_DDI(dev_priv)) {
16141                 int found;
16142
16143                 if (intel_ddi_crt_present(dev_priv))
16144                         intel_crt_init(dev_priv);
16145
16146                 /*
16147                  * Haswell uses DDI functions to detect digital outputs.
16148                  * On SKL pre-D0 the strap isn't connected, so we assume
16149                  * it's there.
16150                  */
16151                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16152                 /* WaIgnoreDDIAStrap: skl */
16153                 if (found || IS_GEN9_BC(dev_priv))
16154                         intel_ddi_init(dev_priv, PORT_A);
16155
16156                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16157                  * register */
16158                 found = I915_READ(SFUSE_STRAP);
16159
16160                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16161                         intel_ddi_init(dev_priv, PORT_B);
16162                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16163                         intel_ddi_init(dev_priv, PORT_C);
16164                 if (found & SFUSE_STRAP_DDID_DETECTED)
16165                         intel_ddi_init(dev_priv, PORT_D);
16166                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16167                         intel_ddi_init(dev_priv, PORT_F);
16168                 /*
16169                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16170                  */
16171                 if (IS_GEN9_BC(dev_priv) &&
16172                     intel_bios_is_port_present(dev_priv, PORT_E))
16173                         intel_ddi_init(dev_priv, PORT_E);
16174
16175         } else if (HAS_PCH_SPLIT(dev_priv)) {
16176                 int found;
16177
16178                 /*
16179                  * intel_edp_init_connector() depends on this completing first,
16180                  * to prevent the registration of both eDP and LVDS and the
16181                  * incorrect sharing of the PPS.
16182                  */
16183                 intel_lvds_init(dev_priv);
16184                 intel_crt_init(dev_priv);
16185
16186                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16187
16188                 if (ilk_has_edp_a(dev_priv))
16189                         intel_dp_init(dev_priv, DP_A, PORT_A);
16190
16191                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
16192                         /* PCH SDVOB multiplex with HDMIB */
16193                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16194                         if (!found)
16195                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16196                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
16197                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16198                 }
16199
16200                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
16201                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16202
16203                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
16204                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16205
16206                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
16207                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16208
16209                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
16210                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16211         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16212                 bool has_edp, has_port;
16213
16214                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16215                         intel_crt_init(dev_priv);
16216
16217                 /*
16218                  * The DP_DETECTED bit is the latched state of the DDC
16219                  * SDA pin at boot. However since eDP doesn't require DDC
16220                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16221                  * eDP ports may have been muxed to an alternate function.
16222                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16223                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16224                  * detect eDP ports.
16225                  *
16226                  * Sadly the straps seem to be missing sometimes even for HDMI
16227                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16228                  * and VBT for the presence of the port. Additionally we can't
16229                  * trust the port type the VBT declares as we've seen at least
16230                  * HDMI ports that the VBT claim are DP or eDP.
16231                  */
16232                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16233                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16234                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
16235                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16236                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16237                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16238
16239                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16240                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16241                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
16242                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16243                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16244                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16245
16246                 if (IS_CHERRYVIEW(dev_priv)) {
16247                         /*
16248                          * eDP not supported on port D,
16249                          * so no need to worry about it
16250                          */
16251                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16252                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
16253                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16254                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
16255                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16256                 }
16257
16258                 vlv_dsi_init(dev_priv);
16259         } else if (IS_PINEVIEW(dev_priv)) {
16260                 intel_lvds_init(dev_priv);
16261                 intel_crt_init(dev_priv);
16262         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16263                 bool found = false;
16264
16265                 if (IS_MOBILE(dev_priv))
16266                         intel_lvds_init(dev_priv);
16267
16268                 intel_crt_init(dev_priv);
16269
16270                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16271                         DRM_DEBUG_KMS("probing SDVOB\n");
16272                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16273                         if (!found && IS_G4X(dev_priv)) {
16274                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
16275                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16276                         }
16277
16278                         if (!found && IS_G4X(dev_priv))
16279                                 intel_dp_init(dev_priv, DP_B, PORT_B);
16280                 }
16281
16282                 /* Before G4X SDVOC doesn't have its own detect register */
16283
16284                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16285                         DRM_DEBUG_KMS("probing SDVOC\n");
16286                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16287                 }
16288
16289                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
16290
16291                         if (IS_G4X(dev_priv)) {
16292                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
16293                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16294                         }
16295                         if (IS_G4X(dev_priv))
16296                                 intel_dp_init(dev_priv, DP_C, PORT_C);
16297                 }
16298
16299                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
16300                         intel_dp_init(dev_priv, DP_D, PORT_D);
16301
16302                 if (SUPPORTS_TV(dev_priv))
16303                         intel_tv_init(dev_priv);
16304         } else if (IS_GEN(dev_priv, 2)) {
16305                 if (IS_I85X(dev_priv))
16306                         intel_lvds_init(dev_priv);
16307
16308                 intel_crt_init(dev_priv);
16309                 intel_dvo_init(dev_priv);
16310         }
16311
16312         intel_psr_init(dev_priv);
16313
16314         for_each_intel_encoder(&dev_priv->drm, encoder) {
16315                 encoder->base.possible_crtcs =
16316                         intel_encoder_possible_crtcs(encoder);
16317                 encoder->base.possible_clones =
16318                         intel_encoder_possible_clones(encoder);
16319         }
16320
16321         intel_init_pch_refclk(dev_priv);
16322
16323         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16324 }
16325
16326 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16327 {
16328         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16329
16330         drm_framebuffer_cleanup(fb);
16331         intel_frontbuffer_put(intel_fb->frontbuffer);
16332
16333         kfree(intel_fb);
16334 }
16335
16336 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16337                                                 struct drm_file *file,
16338                                                 unsigned int *handle)
16339 {
16340         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16341
16342         if (obj->userptr.mm) {
16343                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
16344                 return -EINVAL;
16345         }
16346
16347         return drm_gem_handle_create(file, &obj->base, handle);
16348 }
16349
16350 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16351                                         struct drm_file *file,
16352                                         unsigned flags, unsigned color,
16353                                         struct drm_clip_rect *clips,
16354                                         unsigned num_clips)
16355 {
16356         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16357
16358         i915_gem_object_flush_if_display(obj);
16359         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16360
16361         return 0;
16362 }
16363
16364 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16365         .destroy = intel_user_framebuffer_destroy,
16366         .create_handle = intel_user_framebuffer_create_handle,
16367         .dirty = intel_user_framebuffer_dirty,
16368 };
16369
16370 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16371                                   struct drm_i915_gem_object *obj,
16372                                   struct drm_mode_fb_cmd2 *mode_cmd)
16373 {
16374         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16375         struct drm_framebuffer *fb = &intel_fb->base;
16376         u32 max_stride;
16377         unsigned int tiling, stride;
16378         int ret = -EINVAL;
16379         int i;
16380
16381         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16382         if (!intel_fb->frontbuffer)
16383                 return -ENOMEM;
16384
16385         i915_gem_object_lock(obj);
16386         tiling = i915_gem_object_get_tiling(obj);
16387         stride = i915_gem_object_get_stride(obj);
16388         i915_gem_object_unlock(obj);
16389
16390         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16391                 /*
16392                  * If there's a fence, enforce that
16393                  * the fb modifier and tiling mode match.
16394                  */
16395                 if (tiling != I915_TILING_NONE &&
16396                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16397                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
16398                         goto err;
16399                 }
16400         } else {
16401                 if (tiling == I915_TILING_X) {
16402                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16403                 } else if (tiling == I915_TILING_Y) {
16404                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
16405                         goto err;
16406                 }
16407         }
16408
16409         if (!drm_any_plane_has_format(&dev_priv->drm,
16410                                       mode_cmd->pixel_format,
16411                                       mode_cmd->modifier[0])) {
16412                 struct drm_format_name_buf format_name;
16413
16414                 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
16415                               drm_get_format_name(mode_cmd->pixel_format,
16416                                                   &format_name),
16417                               mode_cmd->modifier[0]);
16418                 goto err;
16419         }
16420
16421         /*
16422          * gen2/3 display engine uses the fence if present,
16423          * so the tiling mode must match the fb modifier exactly.
16424          */
16425         if (INTEL_GEN(dev_priv) < 4 &&
16426             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16427                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
16428                 goto err;
16429         }
16430
16431         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
16432                                          mode_cmd->modifier[0]);
16433         if (mode_cmd->pitches[0] > max_stride) {
16434                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
16435                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
16436                               "tiled" : "linear",
16437                               mode_cmd->pitches[0], max_stride);
16438                 goto err;
16439         }
16440
16441         /*
16442          * If there's a fence, enforce that
16443          * the fb pitch and fence stride match.
16444          */
16445         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
16446                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
16447                               mode_cmd->pitches[0], stride);
16448                 goto err;
16449         }
16450
16451         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16452         if (mode_cmd->offsets[0] != 0)
16453                 goto err;
16454
16455         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
16456
16457         for (i = 0; i < fb->format->num_planes; i++) {
16458                 u32 stride_alignment;
16459
16460                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
16461                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
16462                         goto err;
16463                 }
16464
16465                 stride_alignment = intel_fb_stride_alignment(fb, i);
16466
16467                 /*
16468                  * Display WA #0531: skl,bxt,kbl,glk
16469                  *
16470                  * Render decompression and plane width > 3840
16471                  * combined with horizontal panning requires the
16472                  * plane stride to be a multiple of 4. We'll just
16473                  * require the entire fb to accommodate that to avoid
16474                  * potential runtime errors at plane configuration time.
16475                  */
16476                 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
16477                     is_ccs_modifier(fb->modifier))
16478                         stride_alignment *= 4;
16479
16480                 if (fb->pitches[i] & (stride_alignment - 1)) {
16481                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
16482                                       i, fb->pitches[i], stride_alignment);
16483                         goto err;
16484                 }
16485
16486                 fb->obj[i] = &obj->base;
16487         }
16488
16489         ret = intel_fill_fb_info(dev_priv, fb);
16490         if (ret)
16491                 goto err;
16492
16493         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
16494         if (ret) {
16495                 DRM_ERROR("framebuffer init failed %d\n", ret);
16496                 goto err;
16497         }
16498
16499         return 0;
16500
16501 err:
16502         intel_frontbuffer_put(intel_fb->frontbuffer);
16503         return ret;
16504 }
16505
16506 static struct drm_framebuffer *
16507 intel_user_framebuffer_create(struct drm_device *dev,
16508                               struct drm_file *filp,
16509                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16510 {
16511         struct drm_framebuffer *fb;
16512         struct drm_i915_gem_object *obj;
16513         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16514
16515         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16516         if (!obj)
16517                 return ERR_PTR(-ENOENT);
16518
16519         fb = intel_framebuffer_create(obj, &mode_cmd);
16520         i915_gem_object_put(obj);
16521
16522         return fb;
16523 }
16524
16525 static void intel_atomic_state_free(struct drm_atomic_state *state)
16526 {
16527         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16528
16529         drm_atomic_state_default_release(state);
16530
16531         i915_sw_fence_fini(&intel_state->commit_ready);
16532
16533         kfree(state);
16534 }
16535
16536 static enum drm_mode_status
16537 intel_mode_valid(struct drm_device *dev,
16538                  const struct drm_display_mode *mode)
16539 {
16540         struct drm_i915_private *dev_priv = to_i915(dev);
16541         int hdisplay_max, htotal_max;
16542         int vdisplay_max, vtotal_max;
16543
16544         /*
16545          * Can't reject DBLSCAN here because Xorg ddxen can add piles
16546          * of DBLSCAN modes to the output's mode list when they detect
16547          * the scaling mode property on the connector. And they don't
16548          * ask the kernel to validate those modes in any way until
16549          * modeset time at which point the client gets a protocol error.
16550          * So in order to not upset those clients we silently ignore the
16551          * DBLSCAN flag on such connectors. For other connectors we will
16552          * reject modes with the DBLSCAN flag in encoder->compute_config().
16553          * And we always reject DBLSCAN modes in connector->mode_valid()
16554          * as we never want such modes on the connector's mode list.
16555          */
16556
16557         if (mode->vscan > 1)
16558                 return MODE_NO_VSCAN;
16559
16560         if (mode->flags & DRM_MODE_FLAG_HSKEW)
16561                 return MODE_H_ILLEGAL;
16562
16563         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
16564                            DRM_MODE_FLAG_NCSYNC |
16565                            DRM_MODE_FLAG_PCSYNC))
16566                 return MODE_HSYNC;
16567
16568         if (mode->flags & (DRM_MODE_FLAG_BCAST |
16569                            DRM_MODE_FLAG_PIXMUX |
16570                            DRM_MODE_FLAG_CLKDIV2))
16571                 return MODE_BAD;
16572
16573         /* Transcoder timing limits */
16574         if (INTEL_GEN(dev_priv) >= 11) {
16575                 hdisplay_max = 16384;
16576                 vdisplay_max = 8192;
16577                 htotal_max = 16384;
16578                 vtotal_max = 8192;
16579         } else if (INTEL_GEN(dev_priv) >= 9 ||
16580                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
16581                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
16582                 vdisplay_max = 4096;
16583                 htotal_max = 8192;
16584                 vtotal_max = 8192;
16585         } else if (INTEL_GEN(dev_priv) >= 3) {
16586                 hdisplay_max = 4096;
16587                 vdisplay_max = 4096;
16588                 htotal_max = 8192;
16589                 vtotal_max = 8192;
16590         } else {
16591                 hdisplay_max = 2048;
16592                 vdisplay_max = 2048;
16593                 htotal_max = 4096;
16594                 vtotal_max = 4096;
16595         }
16596
16597         if (mode->hdisplay > hdisplay_max ||
16598             mode->hsync_start > htotal_max ||
16599             mode->hsync_end > htotal_max ||
16600             mode->htotal > htotal_max)
16601                 return MODE_H_ILLEGAL;
16602
16603         if (mode->vdisplay > vdisplay_max ||
16604             mode->vsync_start > vtotal_max ||
16605             mode->vsync_end > vtotal_max ||
16606             mode->vtotal > vtotal_max)
16607                 return MODE_V_ILLEGAL;
16608
16609         if (INTEL_GEN(dev_priv) >= 5) {
16610                 if (mode->hdisplay < 64 ||
16611                     mode->htotal - mode->hdisplay < 32)
16612                         return MODE_H_ILLEGAL;
16613
16614                 if (mode->vtotal - mode->vdisplay < 5)
16615                         return MODE_V_ILLEGAL;
16616         } else {
16617                 if (mode->htotal - mode->hdisplay < 32)
16618                         return MODE_H_ILLEGAL;
16619
16620                 if (mode->vtotal - mode->vdisplay < 3)
16621                         return MODE_V_ILLEGAL;
16622         }
16623
16624         return MODE_OK;
16625 }
16626
16627 enum drm_mode_status
16628 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
16629                                 const struct drm_display_mode *mode)
16630 {
16631         int plane_width_max, plane_height_max;
16632
16633         /*
16634          * intel_mode_valid() should be
16635          * sufficient on older platforms.
16636          */
16637         if (INTEL_GEN(dev_priv) < 9)
16638                 return MODE_OK;
16639
16640         /*
16641          * Most people will probably want a fullscreen
16642          * plane so let's not advertize modes that are
16643          * too big for that.
16644          */
16645         if (INTEL_GEN(dev_priv) >= 11) {
16646                 plane_width_max = 5120;
16647                 plane_height_max = 4320;
16648         } else {
16649                 plane_width_max = 5120;
16650                 plane_height_max = 4096;
16651         }
16652
16653         if (mode->hdisplay > plane_width_max)
16654                 return MODE_H_ILLEGAL;
16655
16656         if (mode->vdisplay > plane_height_max)
16657                 return MODE_V_ILLEGAL;
16658
16659         return MODE_OK;
16660 }
16661
16662 static const struct drm_mode_config_funcs intel_mode_funcs = {
16663         .fb_create = intel_user_framebuffer_create,
16664         .get_format_info = intel_get_format_info,
16665         .output_poll_changed = intel_fbdev_output_poll_changed,
16666         .mode_valid = intel_mode_valid,
16667         .atomic_check = intel_atomic_check,
16668         .atomic_commit = intel_atomic_commit,
16669         .atomic_state_alloc = intel_atomic_state_alloc,
16670         .atomic_state_clear = intel_atomic_state_clear,
16671         .atomic_state_free = intel_atomic_state_free,
16672 };
16673
16674 /**
16675  * intel_init_display_hooks - initialize the display modesetting hooks
16676  * @dev_priv: device private
16677  */
16678 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16679 {
16680         intel_init_cdclk_hooks(dev_priv);
16681
16682         if (INTEL_GEN(dev_priv) >= 9) {
16683                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16684                 dev_priv->display.get_initial_plane_config =
16685                         skylake_get_initial_plane_config;
16686                 dev_priv->display.crtc_compute_clock =
16687                         haswell_crtc_compute_clock;
16688                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16689                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16690         } else if (HAS_DDI(dev_priv)) {
16691                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16692                 dev_priv->display.get_initial_plane_config =
16693                         i9xx_get_initial_plane_config;
16694                 dev_priv->display.crtc_compute_clock =
16695                         haswell_crtc_compute_clock;
16696                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16697                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16698         } else if (HAS_PCH_SPLIT(dev_priv)) {
16699                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16700                 dev_priv->display.get_initial_plane_config =
16701                         i9xx_get_initial_plane_config;
16702                 dev_priv->display.crtc_compute_clock =
16703                         ironlake_crtc_compute_clock;
16704                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16705                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16706         } else if (IS_CHERRYVIEW(dev_priv)) {
16707                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16708                 dev_priv->display.get_initial_plane_config =
16709                         i9xx_get_initial_plane_config;
16710                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16711                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16712                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16713         } else if (IS_VALLEYVIEW(dev_priv)) {
16714                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16715                 dev_priv->display.get_initial_plane_config =
16716                         i9xx_get_initial_plane_config;
16717                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16718                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16719                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16720         } else if (IS_G4X(dev_priv)) {
16721                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16722                 dev_priv->display.get_initial_plane_config =
16723                         i9xx_get_initial_plane_config;
16724                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16725                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16726                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16727         } else if (IS_PINEVIEW(dev_priv)) {
16728                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16729                 dev_priv->display.get_initial_plane_config =
16730                         i9xx_get_initial_plane_config;
16731                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16732                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16733                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16734         } else if (!IS_GEN(dev_priv, 2)) {
16735                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16736                 dev_priv->display.get_initial_plane_config =
16737                         i9xx_get_initial_plane_config;
16738                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16739                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16740                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16741         } else {
16742                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16743                 dev_priv->display.get_initial_plane_config =
16744                         i9xx_get_initial_plane_config;
16745                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16746                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16747                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16748         }
16749
16750         if (IS_GEN(dev_priv, 5)) {
16751                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16752         } else if (IS_GEN(dev_priv, 6)) {
16753                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16754         } else if (IS_IVYBRIDGE(dev_priv)) {
16755                 /* FIXME: detect B0+ stepping and use auto training */
16756                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16757         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16758                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16759         }
16760
16761         if (INTEL_GEN(dev_priv) >= 9)
16762                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
16763         else
16764                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
16765
16766 }
16767
16768 void intel_modeset_init_hw(struct drm_i915_private *i915)
16769 {
16770         intel_update_cdclk(i915);
16771         intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
16772         i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
16773 }
16774
16775 /*
16776  * Calculate what we think the watermarks should be for the state we've read
16777  * out of the hardware and then immediately program those watermarks so that
16778  * we ensure the hardware settings match our internal state.
16779  *
16780  * We can calculate what we think WM's should be by creating a duplicate of the
16781  * current state (which was constructed during hardware readout) and running it
16782  * through the atomic check code to calculate new watermark values in the
16783  * state object.
16784  */
16785 static void sanitize_watermarks(struct drm_device *dev)
16786 {
16787         struct drm_i915_private *dev_priv = to_i915(dev);
16788         struct drm_atomic_state *state;
16789         struct intel_atomic_state *intel_state;
16790         struct intel_crtc *crtc;
16791         struct intel_crtc_state *crtc_state;
16792         struct drm_modeset_acquire_ctx ctx;
16793         int ret;
16794         int i;
16795
16796         /* Only supported on platforms that use atomic watermark design */
16797         if (!dev_priv->display.optimize_watermarks)
16798                 return;
16799
16800         /*
16801          * We need to hold connection_mutex before calling duplicate_state so
16802          * that the connector loop is protected.
16803          */
16804         drm_modeset_acquire_init(&ctx, 0);
16805 retry:
16806         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16807         if (ret == -EDEADLK) {
16808                 drm_modeset_backoff(&ctx);
16809                 goto retry;
16810         } else if (WARN_ON(ret)) {
16811                 goto fail;
16812         }
16813
16814         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16815         if (WARN_ON(IS_ERR(state)))
16816                 goto fail;
16817
16818         intel_state = to_intel_atomic_state(state);
16819
16820         /*
16821          * Hardware readout is the only time we don't want to calculate
16822          * intermediate watermarks (since we don't trust the current
16823          * watermarks).
16824          */
16825         if (!HAS_GMCH(dev_priv))
16826                 intel_state->skip_intermediate_wm = true;
16827
16828         ret = intel_atomic_check(dev, state);
16829         if (ret) {
16830                 /*
16831                  * If we fail here, it means that the hardware appears to be
16832                  * programmed in a way that shouldn't be possible, given our
16833                  * understanding of watermark requirements.  This might mean a
16834                  * mistake in the hardware readout code or a mistake in the
16835                  * watermark calculations for a given platform.  Raise a WARN
16836                  * so that this is noticeable.
16837                  *
16838                  * If this actually happens, we'll have to just leave the
16839                  * BIOS-programmed watermarks untouched and hope for the best.
16840                  */
16841                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16842                 goto put_state;
16843         }
16844
16845         /* Write calculated watermark values back */
16846         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16847                 crtc_state->wm.need_postvbl_update = true;
16848                 dev_priv->display.optimize_watermarks(intel_state, crtc);
16849
16850                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16851         }
16852
16853 put_state:
16854         drm_atomic_state_put(state);
16855 fail:
16856         drm_modeset_drop_locks(&ctx);
16857         drm_modeset_acquire_fini(&ctx);
16858 }
16859
16860 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16861 {
16862         if (IS_GEN(dev_priv, 5)) {
16863                 u32 fdi_pll_clk =
16864                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16865
16866                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16867         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16868                 dev_priv->fdi_pll_freq = 270000;
16869         } else {
16870                 return;
16871         }
16872
16873         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16874 }
16875
16876 static int intel_initial_commit(struct drm_device *dev)
16877 {
16878         struct drm_atomic_state *state = NULL;
16879         struct drm_modeset_acquire_ctx ctx;
16880         struct intel_crtc *crtc;
16881         int ret = 0;
16882
16883         state = drm_atomic_state_alloc(dev);
16884         if (!state)
16885                 return -ENOMEM;
16886
16887         drm_modeset_acquire_init(&ctx, 0);
16888
16889 retry:
16890         state->acquire_ctx = &ctx;
16891
16892         for_each_intel_crtc(dev, crtc) {
16893                 struct intel_crtc_state *crtc_state =
16894                         intel_atomic_get_crtc_state(state, crtc);
16895
16896                 if (IS_ERR(crtc_state)) {
16897                         ret = PTR_ERR(crtc_state);
16898                         goto out;
16899                 }
16900
16901                 if (crtc_state->hw.active) {
16902                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
16903                         if (ret)
16904                                 goto out;
16905
16906                         /*
16907                          * FIXME hack to force a LUT update to avoid the
16908                          * plane update forcing the pipe gamma on without
16909                          * having a proper LUT loaded. Remove once we
16910                          * have readout for pipe gamma enable.
16911                          */
16912                         crtc_state->uapi.color_mgmt_changed = true;
16913                 }
16914         }
16915
16916         ret = drm_atomic_commit(state);
16917
16918 out:
16919         if (ret == -EDEADLK) {
16920                 drm_atomic_state_clear(state);
16921                 drm_modeset_backoff(&ctx);
16922                 goto retry;
16923         }
16924
16925         drm_atomic_state_put(state);
16926
16927         drm_modeset_drop_locks(&ctx);
16928         drm_modeset_acquire_fini(&ctx);
16929
16930         return ret;
16931 }
16932
16933 static void intel_mode_config_init(struct drm_i915_private *i915)
16934 {
16935         struct drm_mode_config *mode_config = &i915->drm.mode_config;
16936
16937         drm_mode_config_init(&i915->drm);
16938
16939         mode_config->min_width = 0;
16940         mode_config->min_height = 0;
16941
16942         mode_config->preferred_depth = 24;
16943         mode_config->prefer_shadow = 1;
16944
16945         mode_config->allow_fb_modifiers = true;
16946
16947         mode_config->funcs = &intel_mode_funcs;
16948
16949         /*
16950          * Maximum framebuffer dimensions, chosen to match
16951          * the maximum render engine surface size on gen4+.
16952          */
16953         if (INTEL_GEN(i915) >= 7) {
16954                 mode_config->max_width = 16384;
16955                 mode_config->max_height = 16384;
16956         } else if (INTEL_GEN(i915) >= 4) {
16957                 mode_config->max_width = 8192;
16958                 mode_config->max_height = 8192;
16959         } else if (IS_GEN(i915, 3)) {
16960                 mode_config->max_width = 4096;
16961                 mode_config->max_height = 4096;
16962         } else {
16963                 mode_config->max_width = 2048;
16964                 mode_config->max_height = 2048;
16965         }
16966
16967         if (IS_I845G(i915) || IS_I865G(i915)) {
16968                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
16969                 mode_config->cursor_height = 1023;
16970         } else if (IS_GEN(i915, 2)) {
16971                 mode_config->cursor_width = 64;
16972                 mode_config->cursor_height = 64;
16973         } else {
16974                 mode_config->cursor_width = 256;
16975                 mode_config->cursor_height = 256;
16976         }
16977 }
16978
16979 int intel_modeset_init(struct drm_i915_private *i915)
16980 {
16981         struct drm_device *dev = &i915->drm;
16982         enum pipe pipe;
16983         struct intel_crtc *crtc;
16984         int ret;
16985
16986         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16987         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16988                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16989
16990         intel_mode_config_init(i915);
16991
16992         ret = intel_bw_init(i915);
16993         if (ret)
16994                 return ret;
16995
16996         init_llist_head(&i915->atomic_helper.free_list);
16997         INIT_WORK(&i915->atomic_helper.free_work,
16998                   intel_atomic_helper_free_state_worker);
16999
17000         intel_init_quirks(i915);
17001
17002         intel_fbc_init(i915);
17003
17004         intel_init_pm(i915);
17005
17006         intel_panel_sanitize_ssc(i915);
17007
17008         intel_gmbus_setup(i915);
17009
17010         DRM_DEBUG_KMS("%d display pipe%s available.\n",
17011                       INTEL_NUM_PIPES(i915),
17012                       INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17013
17014         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
17015                 for_each_pipe(i915, pipe) {
17016                         ret = intel_crtc_init(i915, pipe);
17017                         if (ret) {
17018                                 drm_mode_config_cleanup(dev);
17019                                 return ret;
17020                         }
17021                 }
17022         }
17023
17024         intel_shared_dpll_init(dev);
17025         intel_update_fdi_pll_freq(i915);
17026
17027         intel_update_czclk(i915);
17028         intel_modeset_init_hw(i915);
17029
17030         intel_hdcp_component_init(i915);
17031
17032         if (i915->max_cdclk_freq == 0)
17033                 intel_update_max_cdclk(i915);
17034
17035         /* Just disable it once at startup */
17036         intel_vga_disable(i915);
17037         intel_setup_outputs(i915);
17038
17039         drm_modeset_lock_all(dev);
17040         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17041         drm_modeset_unlock_all(dev);
17042
17043         for_each_intel_crtc(dev, crtc) {
17044                 struct intel_initial_plane_config plane_config = {};
17045
17046                 if (!crtc->active)
17047                         continue;
17048
17049                 /*
17050                  * Note that reserving the BIOS fb up front prevents us
17051                  * from stuffing other stolen allocations like the ring
17052                  * on top.  This prevents some ugliness at boot time, and
17053                  * can even allow for smooth boot transitions if the BIOS
17054                  * fb is large enough for the active pipe configuration.
17055                  */
17056                 i915->display.get_initial_plane_config(crtc, &plane_config);
17057
17058                 /*
17059                  * If the fb is shared between multiple heads, we'll
17060                  * just get the first one.
17061                  */
17062                 intel_find_initial_plane_obj(crtc, &plane_config);
17063         }
17064
17065         /*
17066          * Make sure hardware watermarks really match the state we read out.
17067          * Note that we need to do this after reconstructing the BIOS fb's
17068          * since the watermark calculation done here will use pstate->fb.
17069          */
17070         if (!HAS_GMCH(i915))
17071                 sanitize_watermarks(dev);
17072
17073         /*
17074          * Force all active planes to recompute their states. So that on
17075          * mode_setcrtc after probe, all the intel_plane_state variables
17076          * are already calculated and there is no assert_plane warnings
17077          * during bootup.
17078          */
17079         ret = intel_initial_commit(dev);
17080         if (ret)
17081                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
17082
17083         return 0;
17084 }
17085
17086 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17087 {
17088         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17089         /* 640x480@60Hz, ~25175 kHz */
17090         struct dpll clock = {
17091                 .m1 = 18,
17092                 .m2 = 7,
17093                 .p1 = 13,
17094                 .p2 = 4,
17095                 .n = 2,
17096         };
17097         u32 dpll, fp;
17098         int i;
17099
17100         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
17101
17102         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17103                       pipe_name(pipe), clock.vco, clock.dot);
17104
17105         fp = i9xx_dpll_compute_fp(&clock);
17106         dpll = DPLL_DVO_2X_MODE |
17107                 DPLL_VGA_MODE_DIS |
17108                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17109                 PLL_P2_DIVIDE_BY_4 |
17110                 PLL_REF_INPUT_DREFCLK |
17111                 DPLL_VCO_ENABLE;
17112
17113         I915_WRITE(FP0(pipe), fp);
17114         I915_WRITE(FP1(pipe), fp);
17115
17116         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17117         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17118         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17119         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17120         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17121         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17122         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17123
17124         /*
17125          * Apparently we need to have VGA mode enabled prior to changing
17126          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17127          * dividers, even though the register value does change.
17128          */
17129         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17130         I915_WRITE(DPLL(pipe), dpll);
17131
17132         /* Wait for the clocks to stabilize. */
17133         POSTING_READ(DPLL(pipe));
17134         udelay(150);
17135
17136         /* The pixel multiplier can only be updated once the
17137          * DPLL is enabled and the clocks are stable.
17138          *
17139          * So write it again.
17140          */
17141         I915_WRITE(DPLL(pipe), dpll);
17142
17143         /* We do this three times for luck */
17144         for (i = 0; i < 3 ; i++) {
17145                 I915_WRITE(DPLL(pipe), dpll);
17146                 POSTING_READ(DPLL(pipe));
17147                 udelay(150); /* wait for warmup */
17148         }
17149
17150         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17151         POSTING_READ(PIPECONF(pipe));
17152
17153         intel_wait_for_pipe_scanline_moving(crtc);
17154 }
17155
17156 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17157 {
17158         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17159
17160         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
17161                       pipe_name(pipe));
17162
17163         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
17164         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
17165         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
17166         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
17167         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
17168
17169         I915_WRITE(PIPECONF(pipe), 0);
17170         POSTING_READ(PIPECONF(pipe));
17171
17172         intel_wait_for_pipe_scanline_stopped(crtc);
17173
17174         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
17175         POSTING_READ(DPLL(pipe));
17176 }
17177
17178 static void
17179 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17180 {
17181         struct intel_crtc *crtc;
17182
17183         if (INTEL_GEN(dev_priv) >= 4)
17184                 return;
17185
17186         for_each_intel_crtc(&dev_priv->drm, crtc) {
17187                 struct intel_plane *plane =
17188                         to_intel_plane(crtc->base.primary);
17189                 struct intel_crtc *plane_crtc;
17190                 enum pipe pipe;
17191
17192                 if (!plane->get_hw_state(plane, &pipe))
17193                         continue;
17194
17195                 if (pipe == crtc->pipe)
17196                         continue;
17197
17198                 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17199                               plane->base.base.id, plane->base.name);
17200
17201                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17202                 intel_plane_disable_noatomic(plane_crtc, plane);
17203         }
17204 }
17205
17206 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17207 {
17208         struct drm_device *dev = crtc->base.dev;
17209         struct intel_encoder *encoder;
17210
17211         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17212                 return true;
17213
17214         return false;
17215 }
17216
17217 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17218 {
17219         struct drm_device *dev = encoder->base.dev;
17220         struct intel_connector *connector;
17221
17222         for_each_connector_on_encoder(dev, &encoder->base, connector)
17223                 return connector;
17224
17225         return NULL;
17226 }
17227
17228 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17229                               enum pipe pch_transcoder)
17230 {
17231         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17232                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17233 }
17234
17235 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
17236 {
17237         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
17238         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
17239         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17240
17241         if (INTEL_GEN(dev_priv) >= 9 ||
17242             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17243                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
17244                 u32 val;
17245
17246                 if (transcoder_is_dsi(cpu_transcoder))
17247                         return;
17248
17249                 val = I915_READ(reg);
17250                 val &= ~HSW_FRAME_START_DELAY_MASK;
17251                 val |= HSW_FRAME_START_DELAY(0);
17252                 I915_WRITE(reg, val);
17253         } else {
17254                 i915_reg_t reg = PIPECONF(cpu_transcoder);
17255                 u32 val;
17256
17257                 val = I915_READ(reg);
17258                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
17259                 val |= PIPECONF_FRAME_START_DELAY(0);
17260                 I915_WRITE(reg, val);
17261         }
17262
17263         if (!crtc_state->has_pch_encoder)
17264                 return;
17265
17266         if (HAS_PCH_IBX(dev_priv)) {
17267                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
17268                 u32 val;
17269
17270                 val = I915_READ(reg);
17271                 val &= ~TRANS_FRAME_START_DELAY_MASK;
17272                 val |= TRANS_FRAME_START_DELAY(0);
17273                 I915_WRITE(reg, val);
17274         } else {
17275                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
17276                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
17277                 u32 val;
17278
17279                 val = I915_READ(reg);
17280                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
17281                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
17282                 I915_WRITE(reg, val);
17283         }
17284 }
17285
17286 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17287                                 struct drm_modeset_acquire_ctx *ctx)
17288 {
17289         struct drm_device *dev = crtc->base.dev;
17290         struct drm_i915_private *dev_priv = to_i915(dev);
17291         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17292
17293         if (crtc_state->hw.active) {
17294                 struct intel_plane *plane;
17295
17296                 /* Clear any frame start delays used for debugging left by the BIOS */
17297                 intel_sanitize_frame_start_delay(crtc_state);
17298
17299                 /* Disable everything but the primary plane */
17300                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17301                         const struct intel_plane_state *plane_state =
17302                                 to_intel_plane_state(plane->base.state);
17303
17304                         if (plane_state->uapi.visible &&
17305                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17306                                 intel_plane_disable_noatomic(crtc, plane);
17307                 }
17308
17309                 /*
17310                  * Disable any background color set by the BIOS, but enable the
17311                  * gamma and CSC to match how we program our planes.
17312                  */
17313                 if (INTEL_GEN(dev_priv) >= 9)
17314                         I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
17315                                    SKL_BOTTOM_COLOR_GAMMA_ENABLE |
17316                                    SKL_BOTTOM_COLOR_CSC_ENABLE);
17317         }
17318
17319         /* Adjust the state of the output pipe according to whether we
17320          * have active connectors/encoders. */
17321         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
17322                 intel_crtc_disable_noatomic(&crtc->base, ctx);
17323
17324         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
17325                 /*
17326                  * We start out with underrun reporting disabled to avoid races.
17327                  * For correct bookkeeping mark this on active crtcs.
17328                  *
17329                  * Also on gmch platforms we dont have any hardware bits to
17330                  * disable the underrun reporting. Which means we need to start
17331                  * out with underrun reporting disabled also on inactive pipes,
17332                  * since otherwise we'll complain about the garbage we read when
17333                  * e.g. coming up after runtime pm.
17334                  *
17335                  * No protection against concurrent access is required - at
17336                  * worst a fifo underrun happens which also sets this to false.
17337                  */
17338                 crtc->cpu_fifo_underrun_disabled = true;
17339                 /*
17340                  * We track the PCH trancoder underrun reporting state
17341                  * within the crtc. With crtc for pipe A housing the underrun
17342                  * reporting state for PCH transcoder A, crtc for pipe B housing
17343                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
17344                  * and marking underrun reporting as disabled for the non-existing
17345                  * PCH transcoders B and C would prevent enabling the south
17346                  * error interrupt (see cpt_can_enable_serr_int()).
17347                  */
17348                 if (has_pch_trancoder(dev_priv, crtc->pipe))
17349                         crtc->pch_fifo_underrun_disabled = true;
17350         }
17351 }
17352
17353 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
17354 {
17355         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
17356
17357         /*
17358          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
17359          * the hardware when a high res displays plugged in. DPLL P
17360          * divider is zero, and the pipe timings are bonkers. We'll
17361          * try to disable everything in that case.
17362          *
17363          * FIXME would be nice to be able to sanitize this state
17364          * without several WARNs, but for now let's take the easy
17365          * road.
17366          */
17367         return IS_GEN(dev_priv, 6) &&
17368                 crtc_state->hw.active &&
17369                 crtc_state->shared_dpll &&
17370                 crtc_state->port_clock == 0;
17371 }
17372
17373 static void intel_sanitize_encoder(struct intel_encoder *encoder)
17374 {
17375         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
17376         struct intel_connector *connector;
17377         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
17378         struct intel_crtc_state *crtc_state = crtc ?
17379                 to_intel_crtc_state(crtc->base.state) : NULL;
17380
17381         /* We need to check both for a crtc link (meaning that the
17382          * encoder is active and trying to read from a pipe) and the
17383          * pipe itself being active. */
17384         bool has_active_crtc = crtc_state &&
17385                 crtc_state->hw.active;
17386
17387         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
17388                 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
17389                               pipe_name(crtc->pipe));
17390                 has_active_crtc = false;
17391         }
17392
17393         connector = intel_encoder_find_connector(encoder);
17394         if (connector && !has_active_crtc) {
17395                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
17396                               encoder->base.base.id,
17397                               encoder->base.name);
17398
17399                 /* Connector is active, but has no active pipe. This is
17400                  * fallout from our resume register restoring. Disable
17401                  * the encoder manually again. */
17402                 if (crtc_state) {
17403                         struct drm_encoder *best_encoder;
17404
17405                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
17406                                       encoder->base.base.id,
17407                                       encoder->base.name);
17408
17409                         /* avoid oopsing in case the hooks consult best_encoder */
17410                         best_encoder = connector->base.state->best_encoder;
17411                         connector->base.state->best_encoder = &encoder->base;
17412
17413                         if (encoder->disable)
17414                                 encoder->disable(encoder, crtc_state,
17415                                                  connector->base.state);
17416                         if (encoder->post_disable)
17417                                 encoder->post_disable(encoder, crtc_state,
17418                                                       connector->base.state);
17419
17420                         connector->base.state->best_encoder = best_encoder;
17421                 }
17422                 encoder->base.crtc = NULL;
17423
17424                 /* Inconsistent output/port/pipe state happens presumably due to
17425                  * a bug in one of the get_hw_state functions. Or someplace else
17426                  * in our code, like the register restore mess on resume. Clamp
17427                  * things to off as a safer default. */
17428
17429                 connector->base.dpms = DRM_MODE_DPMS_OFF;
17430                 connector->base.encoder = NULL;
17431         }
17432
17433         /* notify opregion of the sanitized encoder state */
17434         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
17435
17436         if (INTEL_GEN(dev_priv) >= 11)
17437                 icl_sanitize_encoder_pll_mapping(encoder);
17438 }
17439
17440 /* FIXME read out full plane state for all planes */
17441 static void readout_plane_state(struct drm_i915_private *dev_priv)
17442 {
17443         struct intel_plane *plane;
17444         struct intel_crtc *crtc;
17445
17446         for_each_intel_plane(&dev_priv->drm, plane) {
17447                 struct intel_plane_state *plane_state =
17448                         to_intel_plane_state(plane->base.state);
17449                 struct intel_crtc_state *crtc_state;
17450                 enum pipe pipe = PIPE_A;
17451                 bool visible;
17452
17453                 visible = plane->get_hw_state(plane, &pipe);
17454
17455                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17456                 crtc_state = to_intel_crtc_state(crtc->base.state);
17457
17458                 intel_set_plane_visible(crtc_state, plane_state, visible);
17459
17460                 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
17461                               plane->base.base.id, plane->base.name,
17462                               enableddisabled(visible), pipe_name(pipe));
17463         }
17464
17465         for_each_intel_crtc(&dev_priv->drm, crtc) {
17466                 struct intel_crtc_state *crtc_state =
17467                         to_intel_crtc_state(crtc->base.state);
17468
17469                 fixup_active_planes(crtc_state);
17470         }
17471 }
17472
17473 static void intel_modeset_readout_hw_state(struct drm_device *dev)
17474 {
17475         struct drm_i915_private *dev_priv = to_i915(dev);
17476         enum pipe pipe;
17477         struct intel_crtc *crtc;
17478         struct intel_encoder *encoder;
17479         struct intel_connector *connector;
17480         struct drm_connector_list_iter conn_iter;
17481         int i;
17482
17483         dev_priv->active_pipes = 0;
17484
17485         for_each_intel_crtc(dev, crtc) {
17486                 struct intel_crtc_state *crtc_state =
17487                         to_intel_crtc_state(crtc->base.state);
17488
17489                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
17490                 intel_crtc_free_hw_state(crtc_state);
17491                 memset(crtc_state, 0, sizeof(*crtc_state));
17492                 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
17493
17494                 crtc_state->hw.active = crtc_state->hw.enable =
17495                         dev_priv->display.get_pipe_config(crtc, crtc_state);
17496
17497                 crtc->base.enabled = crtc_state->hw.enable;
17498                 crtc->active = crtc_state->hw.active;
17499
17500                 if (crtc_state->hw.active)
17501                         dev_priv->active_pipes |= BIT(crtc->pipe);
17502
17503                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17504                               crtc->base.base.id, crtc->base.name,
17505                               enableddisabled(crtc_state->hw.active));
17506         }
17507
17508         readout_plane_state(dev_priv);
17509
17510         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17511                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17512
17513                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
17514                                                         &pll->state.hw_state);
17515
17516                 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
17517                     pll->info->id == DPLL_ID_EHL_DPLL4) {
17518                         pll->wakeref = intel_display_power_get(dev_priv,
17519                                                                POWER_DOMAIN_DPLL_DC_OFF);
17520                 }
17521
17522                 pll->state.crtc_mask = 0;
17523                 for_each_intel_crtc(dev, crtc) {
17524                         struct intel_crtc_state *crtc_state =
17525                                 to_intel_crtc_state(crtc->base.state);
17526
17527                         if (crtc_state->hw.active &&
17528                             crtc_state->shared_dpll == pll)
17529                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17530                 }
17531                 pll->active_mask = pll->state.crtc_mask;
17532
17533                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17534                               pll->info->name, pll->state.crtc_mask, pll->on);
17535         }
17536
17537         for_each_intel_encoder(dev, encoder) {
17538                 pipe = 0;
17539
17540                 if (encoder->get_hw_state(encoder, &pipe)) {
17541                         struct intel_crtc_state *crtc_state;
17542
17543                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17544                         crtc_state = to_intel_crtc_state(crtc->base.state);
17545
17546                         encoder->base.crtc = &crtc->base;
17547                         encoder->get_config(encoder, crtc_state);
17548                 } else {
17549                         encoder->base.crtc = NULL;
17550                 }
17551
17552                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17553                               encoder->base.base.id, encoder->base.name,
17554                               enableddisabled(encoder->base.crtc),
17555                               pipe_name(pipe));
17556         }
17557
17558         drm_connector_list_iter_begin(dev, &conn_iter);
17559         for_each_intel_connector_iter(connector, &conn_iter) {
17560                 if (connector->get_hw_state(connector)) {
17561                         struct intel_crtc_state *crtc_state;
17562                         struct intel_crtc *crtc;
17563
17564                         connector->base.dpms = DRM_MODE_DPMS_ON;
17565
17566                         encoder = connector->encoder;
17567                         connector->base.encoder = &encoder->base;
17568
17569                         crtc = to_intel_crtc(encoder->base.crtc);
17570                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
17571
17572                         if (crtc_state && crtc_state->hw.active) {
17573                                 /*
17574                                  * This has to be done during hardware readout
17575                                  * because anything calling .crtc_disable may
17576                                  * rely on the connector_mask being accurate.
17577                                  */
17578                                 crtc_state->uapi.connector_mask |=
17579                                         drm_connector_mask(&connector->base);
17580                                 crtc_state->uapi.encoder_mask |=
17581                                         drm_encoder_mask(&encoder->base);
17582                         }
17583                 } else {
17584                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17585                         connector->base.encoder = NULL;
17586                 }
17587                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17588                               connector->base.base.id, connector->base.name,
17589                               enableddisabled(connector->base.encoder));
17590         }
17591         drm_connector_list_iter_end(&conn_iter);
17592
17593         for_each_intel_crtc(dev, crtc) {
17594                 struct intel_bw_state *bw_state =
17595                         to_intel_bw_state(dev_priv->bw_obj.state);
17596                 struct intel_crtc_state *crtc_state =
17597                         to_intel_crtc_state(crtc->base.state);
17598                 struct intel_plane *plane;
17599                 int min_cdclk = 0;
17600
17601                 if (crtc_state->hw.active) {
17602                         struct drm_display_mode *mode = &crtc_state->hw.mode;
17603
17604                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
17605                                                     crtc_state);
17606
17607                         *mode = crtc_state->hw.adjusted_mode;
17608                         mode->hdisplay = crtc_state->pipe_src_w;
17609                         mode->vdisplay = crtc_state->pipe_src_h;
17610
17611                         /*
17612                          * The initial mode needs to be set in order to keep
17613                          * the atomic core happy. It wants a valid mode if the
17614                          * crtc's enabled, so we do the above call.
17615                          *
17616                          * But we don't set all the derived state fully, hence
17617                          * set a flag to indicate that a full recalculation is
17618                          * needed on the next commit.
17619                          */
17620                         mode->private_flags = I915_MODE_FLAG_INHERITED;
17621
17622                         intel_crtc_compute_pixel_rate(crtc_state);
17623
17624                         intel_crtc_update_active_timings(crtc_state);
17625
17626                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
17627                 }
17628
17629                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
17630                         const struct intel_plane_state *plane_state =
17631                                 to_intel_plane_state(plane->base.state);
17632
17633                         /*
17634                          * FIXME don't have the fb yet, so can't
17635                          * use intel_plane_data_rate() :(
17636                          */
17637                         if (plane_state->uapi.visible)
17638                                 crtc_state->data_rate[plane->id] =
17639                                         4 * crtc_state->pixel_rate;
17640                         /*
17641                          * FIXME don't have the fb yet, so can't
17642                          * use plane->min_cdclk() :(
17643                          */
17644                         if (plane_state->uapi.visible && plane->min_cdclk) {
17645                                 if (crtc_state->double_wide ||
17646                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
17647                                         crtc_state->min_cdclk[plane->id] =
17648                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
17649                                 else
17650                                         crtc_state->min_cdclk[plane->id] =
17651                                                 crtc_state->pixel_rate;
17652                         }
17653                         DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n",
17654                                       plane->base.base.id, plane->base.name,
17655                                       crtc_state->min_cdclk[plane->id]);
17656                 }
17657
17658                 if (crtc_state->hw.active) {
17659                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
17660                         if (WARN_ON(min_cdclk < 0))
17661                                 min_cdclk = 0;
17662                 }
17663
17664                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
17665                 dev_priv->min_voltage_level[crtc->pipe] =
17666                         crtc_state->min_voltage_level;
17667
17668                 intel_bw_crtc_update(bw_state, crtc_state);
17669
17670                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17671         }
17672 }
17673
17674 static void
17675 get_encoder_power_domains(struct drm_i915_private *dev_priv)
17676 {
17677         struct intel_encoder *encoder;
17678
17679         for_each_intel_encoder(&dev_priv->drm, encoder) {
17680                 struct intel_crtc_state *crtc_state;
17681
17682                 if (!encoder->get_power_domains)
17683                         continue;
17684
17685                 /*
17686                  * MST-primary and inactive encoders don't have a crtc state
17687                  * and neither of these require any power domain references.
17688                  */
17689                 if (!encoder->base.crtc)
17690                         continue;
17691
17692                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
17693                 encoder->get_power_domains(encoder, crtc_state);
17694         }
17695 }
17696
17697 static void intel_early_display_was(struct drm_i915_private *dev_priv)
17698 {
17699         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
17700         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
17701                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
17702                            DARBF_GATING_DIS);
17703
17704         if (IS_HASWELL(dev_priv)) {
17705                 /*
17706                  * WaRsPkgCStateDisplayPMReq:hsw
17707                  * System hang if this isn't done before disabling all planes!
17708                  */
17709                 I915_WRITE(CHICKEN_PAR1_1,
17710                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
17711         }
17712 }
17713
17714 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
17715                                        enum port port, i915_reg_t hdmi_reg)
17716 {
17717         u32 val = I915_READ(hdmi_reg);
17718
17719         if (val & SDVO_ENABLE ||
17720             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
17721                 return;
17722
17723         DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
17724                       port_name(port));
17725
17726         val &= ~SDVO_PIPE_SEL_MASK;
17727         val |= SDVO_PIPE_SEL(PIPE_A);
17728
17729         I915_WRITE(hdmi_reg, val);
17730 }
17731
17732 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
17733                                      enum port port, i915_reg_t dp_reg)
17734 {
17735         u32 val = I915_READ(dp_reg);
17736
17737         if (val & DP_PORT_EN ||
17738             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
17739                 return;
17740
17741         DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
17742                       port_name(port));
17743
17744         val &= ~DP_PIPE_SEL_MASK;
17745         val |= DP_PIPE_SEL(PIPE_A);
17746
17747         I915_WRITE(dp_reg, val);
17748 }
17749
17750 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
17751 {
17752         /*
17753          * The BIOS may select transcoder B on some of the PCH
17754          * ports even it doesn't enable the port. This would trip
17755          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
17756          * Sanitize the transcoder select bits to prevent that. We
17757          * assume that the BIOS never actually enabled the port,
17758          * because if it did we'd actually have to toggle the port
17759          * on and back off to make the transcoder A select stick
17760          * (see. intel_dp_link_down(), intel_disable_hdmi(),
17761          * intel_disable_sdvo()).
17762          */
17763         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
17764         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
17765         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
17766
17767         /* PCH SDVOB multiplex with HDMIB */
17768         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
17769         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
17770         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
17771 }
17772
17773 /* Scan out the current hw modeset state,
17774  * and sanitizes it to the current state
17775  */
17776 static void
17777 intel_modeset_setup_hw_state(struct drm_device *dev,
17778                              struct drm_modeset_acquire_ctx *ctx)
17779 {
17780         struct drm_i915_private *dev_priv = to_i915(dev);
17781         struct intel_encoder *encoder;
17782         struct intel_crtc *crtc;
17783         intel_wakeref_t wakeref;
17784         int i;
17785
17786         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17787
17788         intel_early_display_was(dev_priv);
17789         intel_modeset_readout_hw_state(dev);
17790
17791         /* HW state is read out, now we need to sanitize this mess. */
17792
17793         /* Sanitize the TypeC port mode upfront, encoders depend on this */
17794         for_each_intel_encoder(dev, encoder) {
17795                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17796
17797                 /* We need to sanitize only the MST primary port. */
17798                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17799                     intel_phy_is_tc(dev_priv, phy))
17800                         intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17801         }
17802
17803         get_encoder_power_domains(dev_priv);
17804
17805         if (HAS_PCH_IBX(dev_priv))
17806                 ibx_sanitize_pch_ports(dev_priv);
17807
17808         /*
17809          * intel_sanitize_plane_mapping() may need to do vblank
17810          * waits, so we need vblank interrupts restored beforehand.
17811          */
17812         for_each_intel_crtc(&dev_priv->drm, crtc) {
17813                 struct intel_crtc_state *crtc_state =
17814                         to_intel_crtc_state(crtc->base.state);
17815
17816                 drm_crtc_vblank_reset(&crtc->base);
17817
17818                 if (crtc_state->hw.active)
17819                         intel_crtc_vblank_on(crtc_state);
17820         }
17821
17822         intel_sanitize_plane_mapping(dev_priv);
17823
17824         for_each_intel_encoder(dev, encoder)
17825                 intel_sanitize_encoder(encoder);
17826
17827         for_each_intel_crtc(&dev_priv->drm, crtc) {
17828                 struct intel_crtc_state *crtc_state =
17829                         crtc_state = to_intel_crtc_state(crtc->base.state);
17830
17831                 intel_sanitize_crtc(crtc, ctx);
17832                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17833         }
17834
17835         intel_modeset_update_connector_atomic_state(dev);
17836
17837         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17838                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17839
17840                 if (!pll->on || pll->active_mask)
17841                         continue;
17842
17843                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17844                               pll->info->name);
17845
17846                 pll->info->funcs->disable(dev_priv, pll);
17847                 pll->on = false;
17848         }
17849
17850         if (IS_G4X(dev_priv)) {
17851                 g4x_wm_get_hw_state(dev_priv);
17852                 g4x_wm_sanitize(dev_priv);
17853         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17854                 vlv_wm_get_hw_state(dev_priv);
17855                 vlv_wm_sanitize(dev_priv);
17856         } else if (INTEL_GEN(dev_priv) >= 9) {
17857                 skl_wm_get_hw_state(dev_priv);
17858         } else if (HAS_PCH_SPLIT(dev_priv)) {
17859                 ilk_wm_get_hw_state(dev_priv);
17860         }
17861
17862         for_each_intel_crtc(dev, crtc) {
17863                 struct intel_crtc_state *crtc_state =
17864                         to_intel_crtc_state(crtc->base.state);
17865                 u64 put_domains;
17866
17867                 put_domains = modeset_get_crtc_power_domains(crtc_state);
17868                 if (WARN_ON(put_domains))
17869                         modeset_put_power_domains(dev_priv, put_domains);
17870         }
17871
17872         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17873
17874         intel_fbc_init_pipe_state(dev_priv);
17875 }
17876
17877 void intel_display_resume(struct drm_device *dev)
17878 {
17879         struct drm_i915_private *dev_priv = to_i915(dev);
17880         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17881         struct drm_modeset_acquire_ctx ctx;
17882         int ret;
17883
17884         dev_priv->modeset_restore_state = NULL;
17885         if (state)
17886                 state->acquire_ctx = &ctx;
17887
17888         drm_modeset_acquire_init(&ctx, 0);
17889
17890         while (1) {
17891                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17892                 if (ret != -EDEADLK)
17893                         break;
17894
17895                 drm_modeset_backoff(&ctx);
17896         }
17897
17898         if (!ret)
17899                 ret = __intel_display_resume(dev, state, &ctx);
17900
17901         intel_enable_ipc(dev_priv);
17902         drm_modeset_drop_locks(&ctx);
17903         drm_modeset_acquire_fini(&ctx);
17904
17905         if (ret)
17906                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17907         if (state)
17908                 drm_atomic_state_put(state);
17909 }
17910
17911 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
17912 {
17913         struct intel_connector *connector;
17914         struct drm_connector_list_iter conn_iter;
17915
17916         /* Kill all the work that may have been queued by hpd. */
17917         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
17918         for_each_intel_connector_iter(connector, &conn_iter) {
17919                 if (connector->modeset_retry_work.func)
17920                         cancel_work_sync(&connector->modeset_retry_work);
17921                 if (connector->hdcp.shim) {
17922                         cancel_delayed_work_sync(&connector->hdcp.check_work);
17923                         cancel_work_sync(&connector->hdcp.prop_work);
17924                 }
17925         }
17926         drm_connector_list_iter_end(&conn_iter);
17927 }
17928
17929 void intel_modeset_driver_remove(struct drm_i915_private *i915)
17930 {
17931         flush_workqueue(i915->flip_wq);
17932         flush_workqueue(i915->modeset_wq);
17933
17934         flush_work(&i915->atomic_helper.free_work);
17935         WARN_ON(!llist_empty(&i915->atomic_helper.free_list));
17936
17937         /*
17938          * Interrupts and polling as the first thing to avoid creating havoc.
17939          * Too much stuff here (turning of connectors, ...) would
17940          * experience fancy races otherwise.
17941          */
17942         intel_irq_uninstall(i915);
17943
17944         /*
17945          * Due to the hpd irq storm handling the hotplug work can re-arm the
17946          * poll handlers. Hence disable polling after hpd handling is shut down.
17947          */
17948         intel_hpd_poll_fini(i915);
17949
17950         /* poll work can call into fbdev, hence clean that up afterwards */
17951         intel_fbdev_fini(i915);
17952
17953         intel_unregister_dsm_handler();
17954
17955         intel_fbc_global_disable(i915);
17956
17957         /* flush any delayed tasks or pending work */
17958         flush_scheduled_work();
17959
17960         intel_hdcp_component_fini(i915);
17961
17962         drm_mode_config_cleanup(&i915->drm);
17963
17964         intel_overlay_cleanup(i915);
17965
17966         intel_gmbus_teardown(i915);
17967
17968         destroy_workqueue(i915->flip_wq);
17969         destroy_workqueue(i915->modeset_wq);
17970
17971         intel_fbc_cleanup_cfb(i915);
17972 }
17973
17974 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17975
17976 struct intel_display_error_state {
17977
17978         u32 power_well_driver;
17979
17980         struct intel_cursor_error_state {
17981                 u32 control;
17982                 u32 position;
17983                 u32 base;
17984                 u32 size;
17985         } cursor[I915_MAX_PIPES];
17986
17987         struct intel_pipe_error_state {
17988                 bool power_domain_on;
17989                 u32 source;
17990                 u32 stat;
17991         } pipe[I915_MAX_PIPES];
17992
17993         struct intel_plane_error_state {
17994                 u32 control;
17995                 u32 stride;
17996                 u32 size;
17997                 u32 pos;
17998                 u32 addr;
17999                 u32 surface;
18000                 u32 tile_offset;
18001         } plane[I915_MAX_PIPES];
18002
18003         struct intel_transcoder_error_state {
18004                 bool available;
18005                 bool power_domain_on;
18006                 enum transcoder cpu_transcoder;
18007
18008                 u32 conf;
18009
18010                 u32 htotal;
18011                 u32 hblank;
18012                 u32 hsync;
18013                 u32 vtotal;
18014                 u32 vblank;
18015                 u32 vsync;
18016         } transcoder[5];
18017 };
18018
18019 struct intel_display_error_state *
18020 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
18021 {
18022         struct intel_display_error_state *error;
18023         int transcoders[] = {
18024                 TRANSCODER_A,
18025                 TRANSCODER_B,
18026                 TRANSCODER_C,
18027                 TRANSCODER_D,
18028                 TRANSCODER_EDP,
18029         };
18030         int i;
18031
18032         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
18033
18034         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
18035                 return NULL;
18036
18037         error = kzalloc(sizeof(*error), GFP_ATOMIC);
18038         if (error == NULL)
18039                 return NULL;
18040
18041         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18042                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
18043
18044         for_each_pipe(dev_priv, i) {
18045                 error->pipe[i].power_domain_on =
18046                         __intel_display_power_is_enabled(dev_priv,
18047                                                          POWER_DOMAIN_PIPE(i));
18048                 if (!error->pipe[i].power_domain_on)
18049                         continue;
18050
18051                 error->cursor[i].control = I915_READ(CURCNTR(i));
18052                 error->cursor[i].position = I915_READ(CURPOS(i));
18053                 error->cursor[i].base = I915_READ(CURBASE(i));
18054
18055                 error->plane[i].control = I915_READ(DSPCNTR(i));
18056                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
18057                 if (INTEL_GEN(dev_priv) <= 3) {
18058                         error->plane[i].size = I915_READ(DSPSIZE(i));
18059                         error->plane[i].pos = I915_READ(DSPPOS(i));
18060                 }
18061                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18062                         error->plane[i].addr = I915_READ(DSPADDR(i));
18063                 if (INTEL_GEN(dev_priv) >= 4) {
18064                         error->plane[i].surface = I915_READ(DSPSURF(i));
18065                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
18066                 }
18067
18068                 error->pipe[i].source = I915_READ(PIPESRC(i));
18069
18070                 if (HAS_GMCH(dev_priv))
18071                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
18072         }
18073
18074         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18075                 enum transcoder cpu_transcoder = transcoders[i];
18076
18077                 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
18078                         continue;
18079
18080                 error->transcoder[i].available = true;
18081                 error->transcoder[i].power_domain_on =
18082                         __intel_display_power_is_enabled(dev_priv,
18083                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18084                 if (!error->transcoder[i].power_domain_on)
18085                         continue;
18086
18087                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18088
18089                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
18090                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
18091                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
18092                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
18093                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
18094                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
18095                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
18096         }
18097
18098         return error;
18099 }
18100
18101 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18102
18103 void
18104 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18105                                 struct intel_display_error_state *error)
18106 {
18107         struct drm_i915_private *dev_priv = m->i915;
18108         int i;
18109
18110         if (!error)
18111                 return;
18112
18113         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18114         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18115                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18116                            error->power_well_driver);
18117         for_each_pipe(dev_priv, i) {
18118                 err_printf(m, "Pipe [%d]:\n", i);
18119                 err_printf(m, "  Power: %s\n",
18120                            onoff(error->pipe[i].power_domain_on));
18121                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
18122                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
18123
18124                 err_printf(m, "Plane [%d]:\n", i);
18125                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
18126                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
18127                 if (INTEL_GEN(dev_priv) <= 3) {
18128                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
18129                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
18130                 }
18131                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18132                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
18133                 if (INTEL_GEN(dev_priv) >= 4) {
18134                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
18135                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
18136                 }
18137
18138                 err_printf(m, "Cursor [%d]:\n", i);
18139                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
18140                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
18141                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
18142         }
18143
18144         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18145                 if (!error->transcoder[i].available)
18146                         continue;
18147
18148                 err_printf(m, "CPU transcoder: %s\n",
18149                            transcoder_name(error->transcoder[i].cpu_transcoder));
18150                 err_printf(m, "  Power: %s\n",
18151                            onoff(error->transcoder[i].power_domain_on));
18152                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
18153                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
18154                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
18155                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
18156                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
18157                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
18158                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
18159         }
18160 }
18161
18162 #endif