drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <drm/i915_drm.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_RGB565,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 /* Primary plane formats for vlv/chv */
 116 static const u32 vlv_primary_formats[] = {
 117         DRM_FORMAT_C8,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_XRGB8888,
 120         DRM_FORMAT_XBGR8888,
 121         DRM_FORMAT_ARGB8888,
 122         DRM_FORMAT_ABGR8888,
 123         DRM_FORMAT_XRGB2101010,
 124         DRM_FORMAT_XBGR2101010,
 125         DRM_FORMAT_ARGB2101010,
 126         DRM_FORMAT_ABGR2101010,
 127         DRM_FORMAT_XBGR16161616F,
 128 };
 129
 130 static const u64 i9xx_format_modifiers[] = {
 131         I915_FORMAT_MOD_X_TILED,
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 /* Cursor formats */
 137 static const u32 intel_cursor_formats[] = {
 138         DRM_FORMAT_ARGB8888,
 139 };
 140
 141 static const u64 cursor_format_modifiers[] = {
 142         DRM_FORMAT_MOD_LINEAR,
 143         DRM_FORMAT_MOD_INVALID
 144 };
 145
 146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 147                                 struct intel_crtc_state *pipe_config);
 148 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 149                                    struct intel_crtc_state *pipe_config);
 150
 151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 152                                   struct drm_i915_gem_object *obj,
 153                                   struct drm_mode_fb_cmd2 *mode_cmd);
 154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 157                                          const struct intel_link_m_n *m_n,
 158                                          const struct intel_link_m_n *m2_n2);
 159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 160 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 161 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
 162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 163 static void vlv_prepare_pll(struct intel_crtc *crtc,
 164                             const struct intel_crtc_state *pipe_config);
 165 static void chv_prepare_pll(struct intel_crtc *crtc,
 166                             const struct intel_crtc_state *pipe_config);
 167 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 168                                     struct intel_crtc_state *crtc_state);
 169 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
 170 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 171 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 173                                          struct drm_modeset_acquire_ctx *ctx);
 174
 175 struct intel_limit {
 176         struct {
 177                 int min, max;
 178         } dot, vco, n, m, m1, m2, p, p1;
 179
 180         struct {
 181                 int dot_limit;
 182                 int p2_slow, p2_fast;
 183         } p2;
 184 };
 185
 186 /* returns HPLL frequency in kHz */
 187 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 188 {
 189         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 190
 191         /* Obtain SKU information */
 192         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 193                 CCK_FUSE_HPLL_FREQ_MASK;
 194
 195         return vco_freq[hpll_freq] * 1000;
 196 }
 197
 198 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 199                       const char *name, u32 reg, int ref_freq)
 200 {
 201         u32 val;
 202         int divider;
 203
 204         val = vlv_cck_read(dev_priv, reg);
 205         divider = val & CCK_FREQUENCY_VALUES;
 206
 207         WARN((val & CCK_FREQUENCY_STATUS) !=
 208              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 209              "%s change in progress\n", name);
 210
 211         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 212 }
 213
 214 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 215                            const char *name, u32 reg)
 216 {
 217         int hpll;
 218
 219         vlv_cck_get(dev_priv);
 220
 221         if (dev_priv->hpll_freq == 0)
 222                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 223
 224         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 225
 226         vlv_cck_put(dev_priv);
 227
 228         return hpll;
 229 }
 230
 231 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 232 {
 233         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 234                 return;
 235
 236         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 237                                                       CCK_CZ_CLOCK_CONTROL);
 238
 239         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 240 }
 241
 242 static inline u32 /* units of 100MHz */
 243 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 244                     const struct intel_crtc_state *pipe_config)
 245 {
 246         if (HAS_DDI(dev_priv))
 247                 return pipe_config->port_clock; /* SPLL */
 248         else
 249                 return dev_priv->fdi_pll_freq;
 250 }
 251
 252 static const struct intel_limit intel_limits_i8xx_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 908000, .max = 1512000 },
 255         .n = { .min = 2, .max = 16 },
 256         .m = { .min = 96, .max = 140 },
 257         .m1 = { .min = 18, .max = 26 },
 258         .m2 = { .min = 6, .max = 16 },
 259         .p = { .min = 4, .max = 128 },
 260         .p1 = { .min = 2, .max = 33 },
 261         .p2 = { .dot_limit = 165000,
 262                 .p2_slow = 4, .p2_fast = 2 },
 263 };
 264
 265 static const struct intel_limit intel_limits_i8xx_dvo = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 908000, .max = 1512000 },
 268         .n = { .min = 2, .max = 16 },
 269         .m = { .min = 96, .max = 140 },
 270         .m1 = { .min = 18, .max = 26 },
 271         .m2 = { .min = 6, .max = 16 },
 272         .p = { .min = 4, .max = 128 },
 273         .p1 = { .min = 2, .max = 33 },
 274         .p2 = { .dot_limit = 165000,
 275                 .p2_slow = 4, .p2_fast = 4 },
 276 };
 277
 278 static const struct intel_limit intel_limits_i8xx_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 908000, .max = 1512000 },
 281         .n = { .min = 2, .max = 16 },
 282         .m = { .min = 96, .max = 140 },
 283         .m1 = { .min = 18, .max = 26 },
 284         .m2 = { .min = 6, .max = 16 },
 285         .p = { .min = 4, .max = 128 },
 286         .p1 = { .min = 1, .max = 6 },
 287         .p2 = { .dot_limit = 165000,
 288                 .p2_slow = 14, .p2_fast = 7 },
 289 };
 290
 291 static const struct intel_limit intel_limits_i9xx_sdvo = {
 292         .dot = { .min = 20000, .max = 400000 },
 293         .vco = { .min = 1400000, .max = 2800000 },
 294         .n = { .min = 1, .max = 6 },
 295         .m = { .min = 70, .max = 120 },
 296         .m1 = { .min = 8, .max = 18 },
 297         .m2 = { .min = 3, .max = 7 },
 298         .p = { .min = 5, .max = 80 },
 299         .p1 = { .min = 1, .max = 8 },
 300         .p2 = { .dot_limit = 200000,
 301                 .p2_slow = 10, .p2_fast = 5 },
 302 };
 303
 304 static const struct intel_limit intel_limits_i9xx_lvds = {
 305         .dot = { .min = 20000, .max = 400000 },
 306         .vco = { .min = 1400000, .max = 2800000 },
 307         .n = { .min = 1, .max = 6 },
 308         .m = { .min = 70, .max = 120 },
 309         .m1 = { .min = 8, .max = 18 },
 310         .m2 = { .min = 3, .max = 7 },
 311         .p = { .min = 7, .max = 98 },
 312         .p1 = { .min = 1, .max = 8 },
 313         .p2 = { .dot_limit = 112000,
 314                 .p2_slow = 14, .p2_fast = 7 },
 315 };
 316
 317
 318 static const struct intel_limit intel_limits_g4x_sdvo = {
 319         .dot = { .min = 25000, .max = 270000 },
 320         .vco = { .min = 1750000, .max = 3500000},
 321         .n = { .min = 1, .max = 4 },
 322         .m = { .min = 104, .max = 138 },
 323         .m1 = { .min = 17, .max = 23 },
 324         .m2 = { .min = 5, .max = 11 },
 325         .p = { .min = 10, .max = 30 },
 326         .p1 = { .min = 1, .max = 3},
 327         .p2 = { .dot_limit = 270000,
 328                 .p2_slow = 10,
 329                 .p2_fast = 10
 330         },
 331 };
 332
 333 static const struct intel_limit intel_limits_g4x_hdmi = {
 334         .dot = { .min = 22000, .max = 400000 },
 335         .vco = { .min = 1750000, .max = 3500000},
 336         .n = { .min = 1, .max = 4 },
 337         .m = { .min = 104, .max = 138 },
 338         .m1 = { .min = 16, .max = 23 },
 339         .m2 = { .min = 5, .max = 11 },
 340         .p = { .min = 5, .max = 80 },
 341         .p1 = { .min = 1, .max = 8},
 342         .p2 = { .dot_limit = 165000,
 343                 .p2_slow = 10, .p2_fast = 5 },
 344 };
 345
 346 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 347         .dot = { .min = 20000, .max = 115000 },
 348         .vco = { .min = 1750000, .max = 3500000 },
 349         .n = { .min = 1, .max = 3 },
 350         .m = { .min = 104, .max = 138 },
 351         .m1 = { .min = 17, .max = 23 },
 352         .m2 = { .min = 5, .max = 11 },
 353         .p = { .min = 28, .max = 112 },
 354         .p1 = { .min = 2, .max = 8 },
 355         .p2 = { .dot_limit = 0,
 356                 .p2_slow = 14, .p2_fast = 14
 357         },
 358 };
 359
 360 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 361         .dot = { .min = 80000, .max = 224000 },
 362         .vco = { .min = 1750000, .max = 3500000 },
 363         .n = { .min = 1, .max = 3 },
 364         .m = { .min = 104, .max = 138 },
 365         .m1 = { .min = 17, .max = 23 },
 366         .m2 = { .min = 5, .max = 11 },
 367         .p = { .min = 14, .max = 42 },
 368         .p1 = { .min = 2, .max = 6 },
 369         .p2 = { .dot_limit = 0,
 370                 .p2_slow = 7, .p2_fast = 7
 371         },
 372 };
 373
 374 static const struct intel_limit intel_limits_pineview_sdvo = {
 375         .dot = { .min = 20000, .max = 400000},
 376         .vco = { .min = 1700000, .max = 3500000 },
 377         /* Pineview's Ncounter is a ring counter */
 378         .n = { .min = 3, .max = 6 },
 379         .m = { .min = 2, .max = 256 },
 380         /* Pineview only has one combined m divider, which we treat as m2. */
 381         .m1 = { .min = 0, .max = 0 },
 382         .m2 = { .min = 0, .max = 254 },
 383         .p = { .min = 5, .max = 80 },
 384         .p1 = { .min = 1, .max = 8 },
 385         .p2 = { .dot_limit = 200000,
 386                 .p2_slow = 10, .p2_fast = 5 },
 387 };
 388
 389 static const struct intel_limit intel_limits_pineview_lvds = {
 390         .dot = { .min = 20000, .max = 400000 },
 391         .vco = { .min = 1700000, .max = 3500000 },
 392         .n = { .min = 3, .max = 6 },
 393         .m = { .min = 2, .max = 256 },
 394         .m1 = { .min = 0, .max = 0 },
 395         .m2 = { .min = 0, .max = 254 },
 396         .p = { .min = 7, .max = 112 },
 397         .p1 = { .min = 1, .max = 8 },
 398         .p2 = { .dot_limit = 112000,
 399                 .p2_slow = 14, .p2_fast = 14 },
 400 };
 401
 402 /* Ironlake / Sandybridge
 403  *
 404  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 405  * the range value for them is (actual_value - 2).
 406  */
 407 static const struct intel_limit intel_limits_ironlake_dac = {
 408         .dot = { .min = 25000, .max = 350000 },
 409         .vco = { .min = 1760000, .max = 3510000 },
 410         .n = { .min = 1, .max = 5 },
 411         .m = { .min = 79, .max = 127 },
 412         .m1 = { .min = 12, .max = 22 },
 413         .m2 = { .min = 5, .max = 9 },
 414         .p = { .min = 5, .max = 80 },
 415         .p1 = { .min = 1, .max = 8 },
 416         .p2 = { .dot_limit = 225000,
 417                 .p2_slow = 10, .p2_fast = 5 },
 418 };
 419
 420 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 421         .dot = { .min = 25000, .max = 350000 },
 422         .vco = { .min = 1760000, .max = 3510000 },
 423         .n = { .min = 1, .max = 3 },
 424         .m = { .min = 79, .max = 118 },
 425         .m1 = { .min = 12, .max = 22 },
 426         .m2 = { .min = 5, .max = 9 },
 427         .p = { .min = 28, .max = 112 },
 428         .p1 = { .min = 2, .max = 8 },
 429         .p2 = { .dot_limit = 225000,
 430                 .p2_slow = 14, .p2_fast = 14 },
 431 };
 432
 433 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 434         .dot = { .min = 25000, .max = 350000 },
 435         .vco = { .min = 1760000, .max = 3510000 },
 436         .n = { .min = 1, .max = 3 },
 437         .m = { .min = 79, .max = 127 },
 438         .m1 = { .min = 12, .max = 22 },
 439         .m2 = { .min = 5, .max = 9 },
 440         .p = { .min = 14, .max = 56 },
 441         .p1 = { .min = 2, .max = 8 },
 442         .p2 = { .dot_limit = 225000,
 443                 .p2_slow = 7, .p2_fast = 7 },
 444 };
 445
 446 /* LVDS 100mhz refclk limits. */
 447 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 448         .dot = { .min = 25000, .max = 350000 },
 449         .vco = { .min = 1760000, .max = 3510000 },
 450         .n = { .min = 1, .max = 2 },
 451         .m = { .min = 79, .max = 126 },
 452         .m1 = { .min = 12, .max = 22 },
 453         .m2 = { .min = 5, .max = 9 },
 454         .p = { .min = 28, .max = 112 },
 455         .p1 = { .min = 2, .max = 8 },
 456         .p2 = { .dot_limit = 225000,
 457                 .p2_slow = 14, .p2_fast = 14 },
 458 };
 459
 460 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 461         .dot = { .min = 25000, .max = 350000 },
 462         .vco = { .min = 1760000, .max = 3510000 },
 463         .n = { .min = 1, .max = 3 },
 464         .m = { .min = 79, .max = 126 },
 465         .m1 = { .min = 12, .max = 22 },
 466         .m2 = { .min = 5, .max = 9 },
 467         .p = { .min = 14, .max = 42 },
 468         .p1 = { .min = 2, .max = 6 },
 469         .p2 = { .dot_limit = 225000,
 470                 .p2_slow = 7, .p2_fast = 7 },
 471 };
 472
 473 static const struct intel_limit intel_limits_vlv = {
 474          /*
 475           * These are the data rate limits (measured in fast clocks)
 476           * since those are the strictest limits we have. The fast
 477           * clock and actual rate limits are more relaxed, so checking
 478           * them would make no difference.
 479           */
 480         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 481         .vco = { .min = 4000000, .max = 6000000 },
 482         .n = { .min = 1, .max = 7 },
 483         .m1 = { .min = 2, .max = 3 },
 484         .m2 = { .min = 11, .max = 156 },
 485         .p1 = { .min = 2, .max = 3 },
 486         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 487 };
 488
 489 static const struct intel_limit intel_limits_chv = {
 490         /*
 491          * These are the data rate limits (measured in fast clocks)
 492          * since those are the strictest limits we have.  The fast
 493          * clock and actual rate limits are more relaxed, so checking
 494          * them would make no difference.
 495          */
 496         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 497         .vco = { .min = 4800000, .max = 6480000 },
 498         .n = { .min = 1, .max = 1 },
 499         .m1 = { .min = 2, .max = 2 },
 500         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 501         .p1 = { .min = 2, .max = 4 },
 502         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 503 };
 504
 505 static const struct intel_limit intel_limits_bxt = {
 506         /* FIXME: find real dot limits */
 507         .dot = { .min = 0, .max = INT_MAX },
 508         .vco = { .min = 4800000, .max = 6700000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         /* FIXME: find real m2 limits */
 512         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 513         .p1 = { .min = 2, .max = 4 },
 514         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 515 };
 516
 517 /* WA Display #0827: Gen9:all */
 518 static void
 519 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 520 {
 521         if (enable)
 522                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 523                            I915_READ(CLKGATE_DIS_PSL(pipe)) |
 524                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 525         else
 526                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 527                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 528                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 529 }
 530
 531 /* Wa_2006604312:icl */
 532 static void
 533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 534                        bool enable)
 535 {
 536         if (enable)
 537                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 538                            I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 539         else
 540                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 541                            I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 542 }
 543
 544 static bool
 545 needs_modeset(const struct intel_crtc_state *state)
 546 {
 547         return drm_atomic_crtc_needs_modeset(&state->uapi);
 548 }
 549
 550 bool
 551 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 552 {
 553         return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
 554                 crtc_state->sync_mode_slaves_mask);
 555 }
 556
 557 static bool
 558 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 559 {
 560         return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
 561                 crtc_state->sync_mode_slaves_mask);
 562 }
 563
 564 static bool
 565 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 566 {
 567         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 568 }
 569
 570 /*
 571  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 572  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 573  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 574  * The helpers' return value is the rate of the clock that is fed to the
 575  * display engine's pipe which can be the above fast dot clock rate or a
 576  * divided-down version of it.
 577  */
 578 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 579 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 580 {
 581         clock->m = clock->m2 + 2;
 582         clock->p = clock->p1 * clock->p2;
 583         if (WARN_ON(clock->n == 0 || clock->p == 0))
 584                 return 0;
 585         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 586         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 587
 588         return clock->dot;
 589 }
 590
 591 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 592 {
 593         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 594 }
 595
 596 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 597 {
 598         clock->m = i9xx_dpll_compute_m(clock);
 599         clock->p = clock->p1 * clock->p2;
 600         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 601                 return 0;
 602         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 603         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 604
 605         return clock->dot;
 606 }
 607
 608 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 609 {
 610         clock->m = clock->m1 * clock->m2;
 611         clock->p = clock->p1 * clock->p2;
 612         if (WARN_ON(clock->n == 0 || clock->p == 0))
 613                 return 0;
 614         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 615         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 616
 617         return clock->dot / 5;
 618 }
 619
 620 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 621 {
 622         clock->m = clock->m1 * clock->m2;
 623         clock->p = clock->p1 * clock->p2;
 624         if (WARN_ON(clock->n == 0 || clock->p == 0))
 625                 return 0;
 626         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 627                                            clock->n << 22);
 628         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 629
 630         return clock->dot / 5;
 631 }
 632
 633 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 634
 635 /*
 636  * Returns whether the given set of divisors are valid for a given refclk with
 637  * the given connectors.
 638  */
 639 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 640                                const struct intel_limit *limit,
 641                                const struct dpll *clock)
 642 {
 643         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 644                 INTELPllInvalid("n out of range\n");
 645         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 646                 INTELPllInvalid("p1 out of range\n");
 647         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 648                 INTELPllInvalid("m2 out of range\n");
 649         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 650                 INTELPllInvalid("m1 out of range\n");
 651
 652         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 653             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 654                 if (clock->m1 <= clock->m2)
 655                         INTELPllInvalid("m1 <= m2\n");
 656
 657         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 658             !IS_GEN9_LP(dev_priv)) {
 659                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 660                         INTELPllInvalid("p out of range\n");
 661                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 662                         INTELPllInvalid("m out of range\n");
 663         }
 664
 665         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 666                 INTELPllInvalid("vco out of range\n");
 667         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 668          * connector, etc., rather than just a single range.
 669          */
 670         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 671                 INTELPllInvalid("dot out of range\n");
 672
 673         return true;
 674 }
 675
 676 static int
 677 i9xx_select_p2_div(const struct intel_limit *limit,
 678                    const struct intel_crtc_state *crtc_state,
 679                    int target)
 680 {
 681         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 682
 683         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 684                 /*
 685                  * For LVDS just rely on its current settings for dual-channel.
 686                  * We haven't figured out how to reliably set up different
 687                  * single/dual channel state, if we even can.
 688                  */
 689                 if (intel_is_dual_link_lvds(dev_priv))
 690                         return limit->p2.p2_fast;
 691                 else
 692                         return limit->p2.p2_slow;
 693         } else {
 694                 if (target < limit->p2.dot_limit)
 695                         return limit->p2.p2_slow;
 696                 else
 697                         return limit->p2.p2_fast;
 698         }
 699 }
 700
 701 /*
 702  * Returns a set of divisors for the desired target clock with the given
 703  * refclk, or FALSE.  The returned values represent the clock equation:
 704  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 705  *
 706  * Target and reference clocks are specified in kHz.
 707  *
 708  * If match_clock is provided, then best_clock P divider must match the P
 709  * divider from @match_clock used for LVDS downclocking.
 710  */
 711 static bool
 712 i9xx_find_best_dpll(const struct intel_limit *limit,
 713                     struct intel_crtc_state *crtc_state,
 714                     int target, int refclk, struct dpll *match_clock,
 715                     struct dpll *best_clock)
 716 {
 717         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 718         struct dpll clock;
 719         int err = target;
 720
 721         memset(best_clock, 0, sizeof(*best_clock));
 722
 723         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 724
 725         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 726              clock.m1++) {
 727                 for (clock.m2 = limit->m2.min;
 728                      clock.m2 <= limit->m2.max; clock.m2++) {
 729                         if (clock.m2 >= clock.m1)
 730                                 break;
 731                         for (clock.n = limit->n.min;
 732                              clock.n <= limit->n.max; clock.n++) {
 733                                 for (clock.p1 = limit->p1.min;
 734                                         clock.p1 <= limit->p1.max; clock.p1++) {
 735                                         int this_err;
 736
 737                                         i9xx_calc_dpll_params(refclk, &clock);
 738                                         if (!intel_PLL_is_valid(to_i915(dev),
 739                                                                 limit,
 740                                                                 &clock))
 741                                                 continue;
 742                                         if (match_clock &&
 743                                             clock.p != match_clock->p)
 744                                                 continue;
 745
 746                                         this_err = abs(clock.dot - target);
 747                                         if (this_err < err) {
 748                                                 *best_clock = clock;
 749                                                 err = this_err;
 750                                         }
 751                                 }
 752                         }
 753                 }
 754         }
 755
 756         return (err != target);
 757 }
 758
 759 /*
 760  * Returns a set of divisors for the desired target clock with the given
 761  * refclk, or FALSE.  The returned values represent the clock equation:
 762  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 763  *
 764  * Target and reference clocks are specified in kHz.
 765  *
 766  * If match_clock is provided, then best_clock P divider must match the P
 767  * divider from @match_clock used for LVDS downclocking.
 768  */
 769 static bool
 770 pnv_find_best_dpll(const struct intel_limit *limit,
 771                    struct intel_crtc_state *crtc_state,
 772                    int target, int refclk, struct dpll *match_clock,
 773                    struct dpll *best_clock)
 774 {
 775         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 776         struct dpll clock;
 777         int err = target;
 778
 779         memset(best_clock, 0, sizeof(*best_clock));
 780
 781         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 782
 783         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 784              clock.m1++) {
 785                 for (clock.m2 = limit->m2.min;
 786                      clock.m2 <= limit->m2.max; clock.m2++) {
 787                         for (clock.n = limit->n.min;
 788                              clock.n <= limit->n.max; clock.n++) {
 789                                 for (clock.p1 = limit->p1.min;
 790                                         clock.p1 <= limit->p1.max; clock.p1++) {
 791                                         int this_err;
 792
 793                                         pnv_calc_dpll_params(refclk, &clock);
 794                                         if (!intel_PLL_is_valid(to_i915(dev),
 795                                                                 limit,
 796                                                                 &clock))
 797                                                 continue;
 798                                         if (match_clock &&
 799                                             clock.p != match_clock->p)
 800                                                 continue;
 801
 802                                         this_err = abs(clock.dot - target);
 803                                         if (this_err < err) {
 804                                                 *best_clock = clock;
 805                                                 err = this_err;
 806                                         }
 807                                 }
 808                         }
 809                 }
 810         }
 811
 812         return (err != target);
 813 }
 814
 815 /*
 816  * Returns a set of divisors for the desired target clock with the given
 817  * refclk, or FALSE.  The returned values represent the clock equation:
 818  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 819  *
 820  * Target and reference clocks are specified in kHz.
 821  *
 822  * If match_clock is provided, then best_clock P divider must match the P
 823  * divider from @match_clock used for LVDS downclocking.
 824  */
 825 static bool
 826 g4x_find_best_dpll(const struct intel_limit *limit,
 827                    struct intel_crtc_state *crtc_state,
 828                    int target, int refclk, struct dpll *match_clock,
 829                    struct dpll *best_clock)
 830 {
 831         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 832         struct dpll clock;
 833         int max_n;
 834         bool found = false;
 835         /* approximately equals target * 0.00585 */
 836         int err_most = (target >> 8) + (target >> 9);
 837
 838         memset(best_clock, 0, sizeof(*best_clock));
 839
 840         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 841
 842         max_n = limit->n.max;
 843         /* based on hardware requirement, prefer smaller n to precision */
 844         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 845                 /* based on hardware requirement, prefere larger m1,m2 */
 846                 for (clock.m1 = limit->m1.max;
 847                      clock.m1 >= limit->m1.min; clock.m1--) {
 848                         for (clock.m2 = limit->m2.max;
 849                              clock.m2 >= limit->m2.min; clock.m2--) {
 850                                 for (clock.p1 = limit->p1.max;
 851                                      clock.p1 >= limit->p1.min; clock.p1--) {
 852                                         int this_err;
 853
 854                                         i9xx_calc_dpll_params(refclk, &clock);
 855                                         if (!intel_PLL_is_valid(to_i915(dev),
 856                                                                 limit,
 857                                                                 &clock))
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err_most) {
 862                                                 *best_clock = clock;
 863                                                 err_most = this_err;
 864                                                 max_n = clock.n;
 865                                                 found = true;
 866                                         }
 867                                 }
 868                         }
 869                 }
 870         }
 871         return found;
 872 }
 873
 874 /*
 875  * Check if the calculated PLL configuration is more optimal compared to the
 876  * best configuration and error found so far. Return the calculated error.
 877  */
 878 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 879                                const struct dpll *calculated_clock,
 880                                const struct dpll *best_clock,
 881                                unsigned int best_error_ppm,
 882                                unsigned int *error_ppm)
 883 {
 884         /*
 885          * For CHV ignore the error and consider only the P value.
 886          * Prefer a bigger P value based on HW requirements.
 887          */
 888         if (IS_CHERRYVIEW(to_i915(dev))) {
 889                 *error_ppm = 0;
 890
 891                 return calculated_clock->p > best_clock->p;
 892         }
 893
 894         if (WARN_ON_ONCE(!target_freq))
 895                 return false;
 896
 897         *error_ppm = div_u64(1000000ULL *
 898                                 abs(target_freq - calculated_clock->dot),
 899                              target_freq);
 900         /*
 901          * Prefer a better P value over a better (smaller) error if the error
 902          * is small. Ensure this preference for future configurations too by
 903          * setting the error to 0.
 904          */
 905         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 906                 *error_ppm = 0;
 907
 908                 return true;
 909         }
 910
 911         return *error_ppm + 10 < best_error_ppm;
 912 }
 913
 914 /*
 915  * Returns a set of divisors for the desired target clock with the given
 916  * refclk, or FALSE.  The returned values represent the clock equation:
 917  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 918  */
 919 static bool
 920 vlv_find_best_dpll(const struct intel_limit *limit,
 921                    struct intel_crtc_state *crtc_state,
 922                    int target, int refclk, struct dpll *match_clock,
 923                    struct dpll *best_clock)
 924 {
 925         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 926         struct drm_device *dev = crtc->base.dev;
 927         struct dpll clock;
 928         unsigned int bestppm = 1000000;
 929         /* min update 19.2 MHz */
 930         int max_n = min(limit->n.max, refclk / 19200);
 931         bool found = false;
 932
 933         target *= 5; /* fast clock */
 934
 935         memset(best_clock, 0, sizeof(*best_clock));
 936
 937         /* based on hardware requirement, prefer smaller n to precision */
 938         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 939                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 940                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 941                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 942                                 clock.p = clock.p1 * clock.p2;
 943                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 944                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 945                                         unsigned int ppm;
 946
 947                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 948                                                                      refclk * clock.m1);
 949
 950                                         vlv_calc_dpll_params(refclk, &clock);
 951
 952                                         if (!intel_PLL_is_valid(to_i915(dev),
 953                                                                 limit,
 954                                                                 &clock))
 955                                                 continue;
 956
 957                                         if (!vlv_PLL_is_optimal(dev, target,
 958                                                                 &clock,
 959                                                                 best_clock,
 960                                                                 bestppm, &ppm))
 961                                                 continue;
 962
 963                                         *best_clock = clock;
 964                                         bestppm = ppm;
 965                                         found = true;
 966                                 }
 967                         }
 968                 }
 969         }
 970
 971         return found;
 972 }
 973
 974 /*
 975  * Returns a set of divisors for the desired target clock with the given
 976  * refclk, or FALSE.  The returned values represent the clock equation:
 977  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 978  */
 979 static bool
 980 chv_find_best_dpll(const struct intel_limit *limit,
 981                    struct intel_crtc_state *crtc_state,
 982                    int target, int refclk, struct dpll *match_clock,
 983                    struct dpll *best_clock)
 984 {
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 986         struct drm_device *dev = crtc->base.dev;
 987         unsigned int best_error_ppm;
 988         struct dpll clock;
 989         u64 m2;
 990         int found = false;
 991
 992         memset(best_clock, 0, sizeof(*best_clock));
 993         best_error_ppm = 1000000;
 994
 995         /*
 996          * Based on hardware doc, the n always set to 1, and m1 always
 997          * set to 2.  If requires to support 200Mhz refclk, we need to
 998          * revisit this because n may not 1 anymore.
 999          */
1000         clock.n = 1, clock.m1 = 2;
1001         target *= 5;    /* fast clock */
1002
1003         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004                 for (clock.p2 = limit->p2.p2_fast;
1005                                 clock.p2 >= limit->p2.p2_slow;
1006                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007                         unsigned int error_ppm;
1008
1009                         clock.p = clock.p1 * clock.p2;
1010
1011                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1012                                                    refclk * clock.m1);
1013
1014                         if (m2 > INT_MAX/clock.m1)
1015                                 continue;
1016
1017                         clock.m2 = m2;
1018
1019                         chv_calc_dpll_params(refclk, &clock);
1020
1021                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1022                                 continue;
1023
1024                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025                                                 best_error_ppm, &error_ppm))
1026                                 continue;
1027
1028                         *best_clock = clock;
1029                         best_error_ppm = error_ppm;
1030                         found = true;
1031                 }
1032         }
1033
1034         return found;
1035 }
1036
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1038                         struct dpll *best_clock)
1039 {
1040         int refclk = 100000;
1041         const struct intel_limit *limit = &intel_limits_bxt;
1042
1043         return chv_find_best_dpll(limit, crtc_state,
1044                                   crtc_state->port_clock, refclk,
1045                                   NULL, best_clock);
1046 }
1047
1048 bool intel_crtc_active(struct intel_crtc *crtc)
1049 {
1050         /* Be paranoid as we can arrive here with only partial
1051          * state retrieved from the hardware during setup.
1052          *
1053          * We can ditch the adjusted_mode.crtc_clock check as soon
1054          * as Haswell has gained clock readout/fastboot support.
1055          *
1056          * We can ditch the crtc->primary->state->fb check as soon as we can
1057          * properly reconstruct framebuffers.
1058          *
1059          * FIXME: The intel_crtc->active here should be switched to
1060          * crtc->state->active once we have proper CRTC states wired up
1061          * for atomic.
1062          */
1063         return crtc->active && crtc->base.primary->state->fb &&
1064                 crtc->config->hw.adjusted_mode.crtc_clock;
1065 }
1066
1067 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1068                                              enum pipe pipe)
1069 {
1070         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1071
1072         return crtc->config->cpu_transcoder;
1073 }
1074
1075 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1076                                     enum pipe pipe)
1077 {
1078         i915_reg_t reg = PIPEDSL(pipe);
1079         u32 line1, line2;
1080         u32 line_mask;
1081
1082         if (IS_GEN(dev_priv, 2))
1083                 line_mask = DSL_LINEMASK_GEN2;
1084         else
1085                 line_mask = DSL_LINEMASK_GEN3;
1086
1087         line1 = I915_READ(reg) & line_mask;
1088         msleep(5);
1089         line2 = I915_READ(reg) & line_mask;
1090
1091         return line1 != line2;
1092 }
1093
1094 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1095 {
1096         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1097         enum pipe pipe = crtc->pipe;
1098
1099         /* Wait for the display line to settle/start moving */
1100         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1101                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1102                           pipe_name(pipe), onoff(state));
1103 }
1104
1105 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1106 {
1107         wait_for_pipe_scanline_moving(crtc, false);
1108 }
1109
1110 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1111 {
1112         wait_for_pipe_scanline_moving(crtc, true);
1113 }
1114
1115 static void
1116 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1117 {
1118         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1119         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1120
1121         if (INTEL_GEN(dev_priv) >= 4) {
1122                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1123                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1124
1125                 /* Wait for the Pipe State to go off */
1126                 if (intel_de_wait_for_clear(dev_priv, reg,
1127                                             I965_PIPECONF_ACTIVE, 100))
1128                         WARN(1, "pipe_off wait timed out\n");
1129         } else {
1130                 intel_wait_for_pipe_scanline_stopped(crtc);
1131         }
1132 }
1133
1134 /* Only for pre-ILK configs */
1135 void assert_pll(struct drm_i915_private *dev_priv,
1136                 enum pipe pipe, bool state)
1137 {
1138         u32 val;
1139         bool cur_state;
1140
1141         val = I915_READ(DPLL(pipe));
1142         cur_state = !!(val & DPLL_VCO_ENABLE);
1143         I915_STATE_WARN(cur_state != state,
1144              "PLL state assertion failure (expected %s, current %s)\n",
1145                         onoff(state), onoff(cur_state));
1146 }
1147
1148 /* XXX: the dsi pll is shared between MIPI DSI ports */
1149 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1150 {
1151         u32 val;
1152         bool cur_state;
1153
1154         vlv_cck_get(dev_priv);
1155         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1156         vlv_cck_put(dev_priv);
1157
1158         cur_state = val & DSI_PLL_VCO_EN;
1159         I915_STATE_WARN(cur_state != state,
1160              "DSI PLL state assertion failure (expected %s, current %s)\n",
1161                         onoff(state), onoff(cur_state));
1162 }
1163
1164 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1165                           enum pipe pipe, bool state)
1166 {
1167         bool cur_state;
1168         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1169                                                                       pipe);
1170
1171         if (HAS_DDI(dev_priv)) {
1172                 /* DDI does not have a specific FDI_TX register */
1173                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1174                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1175         } else {
1176                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1177                 cur_state = !!(val & FDI_TX_ENABLE);
1178         }
1179         I915_STATE_WARN(cur_state != state,
1180              "FDI TX state assertion failure (expected %s, current %s)\n",
1181                         onoff(state), onoff(cur_state));
1182 }
1183 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1184 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1185
1186 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1187                           enum pipe pipe, bool state)
1188 {
1189         u32 val;
1190         bool cur_state;
1191
1192         val = I915_READ(FDI_RX_CTL(pipe));
1193         cur_state = !!(val & FDI_RX_ENABLE);
1194         I915_STATE_WARN(cur_state != state,
1195              "FDI RX state assertion failure (expected %s, current %s)\n",
1196                         onoff(state), onoff(cur_state));
1197 }
1198 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1199 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1200
1201 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1202                                       enum pipe pipe)
1203 {
1204         u32 val;
1205
1206         /* ILK FDI PLL is always enabled */
1207         if (IS_GEN(dev_priv, 5))
1208                 return;
1209
1210         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1211         if (HAS_DDI(dev_priv))
1212                 return;
1213
1214         val = I915_READ(FDI_TX_CTL(pipe));
1215         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1216 }
1217
1218 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1219                        enum pipe pipe, bool state)
1220 {
1221         u32 val;
1222         bool cur_state;
1223
1224         val = I915_READ(FDI_RX_CTL(pipe));
1225         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1226         I915_STATE_WARN(cur_state != state,
1227              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1228                         onoff(state), onoff(cur_state));
1229 }
1230
1231 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1232 {
1233         i915_reg_t pp_reg;
1234         u32 val;
1235         enum pipe panel_pipe = INVALID_PIPE;
1236         bool locked = true;
1237
1238         if (WARN_ON(HAS_DDI(dev_priv)))
1239                 return;
1240
1241         if (HAS_PCH_SPLIT(dev_priv)) {
1242                 u32 port_sel;
1243
1244                 pp_reg = PP_CONTROL(0);
1245                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1246
1247                 switch (port_sel) {
1248                 case PANEL_PORT_SELECT_LVDS:
1249                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1250                         break;
1251                 case PANEL_PORT_SELECT_DPA:
1252                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1253                         break;
1254                 case PANEL_PORT_SELECT_DPC:
1255                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1256                         break;
1257                 case PANEL_PORT_SELECT_DPD:
1258                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1259                         break;
1260                 default:
1261                         MISSING_CASE(port_sel);
1262                         break;
1263                 }
1264         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1265                 /* presumably write lock depends on pipe, not port select */
1266                 pp_reg = PP_CONTROL(pipe);
1267                 panel_pipe = pipe;
1268         } else {
1269                 u32 port_sel;
1270
1271                 pp_reg = PP_CONTROL(0);
1272                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1273
1274                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1275                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1276         }
1277
1278         val = I915_READ(pp_reg);
1279         if (!(val & PANEL_POWER_ON) ||
1280             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1281                 locked = false;
1282
1283         I915_STATE_WARN(panel_pipe == pipe && locked,
1284              "panel assertion failure, pipe %c regs locked\n",
1285              pipe_name(pipe));
1286 }
1287
1288 void assert_pipe(struct drm_i915_private *dev_priv,
1289                  enum pipe pipe, bool state)
1290 {
1291         bool cur_state;
1292         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1293                                                                       pipe);
1294         enum intel_display_power_domain power_domain;
1295         intel_wakeref_t wakeref;
1296
1297         /* we keep both pipes enabled on 830 */
1298         if (IS_I830(dev_priv))
1299                 state = true;
1300
1301         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1302         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1303         if (wakeref) {
1304                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1305                 cur_state = !!(val & PIPECONF_ENABLE);
1306
1307                 intel_display_power_put(dev_priv, power_domain, wakeref);
1308         } else {
1309                 cur_state = false;
1310         }
1311
1312         I915_STATE_WARN(cur_state != state,
1313              "pipe %c assertion failure (expected %s, current %s)\n",
1314                         pipe_name(pipe), onoff(state), onoff(cur_state));
1315 }
1316
1317 static void assert_plane(struct intel_plane *plane, bool state)
1318 {
1319         enum pipe pipe;
1320         bool cur_state;
1321
1322         cur_state = plane->get_hw_state(plane, &pipe);
1323
1324         I915_STATE_WARN(cur_state != state,
1325                         "%s assertion failure (expected %s, current %s)\n",
1326                         plane->base.name, onoff(state), onoff(cur_state));
1327 }
1328
1329 #define assert_plane_enabled(p) assert_plane(p, true)
1330 #define assert_plane_disabled(p) assert_plane(p, false)
1331
1332 static void assert_planes_disabled(struct intel_crtc *crtc)
1333 {
1334         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1335         struct intel_plane *plane;
1336
1337         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1338                 assert_plane_disabled(plane);
1339 }
1340
1341 static void assert_vblank_disabled(struct drm_crtc *crtc)
1342 {
1343         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1344                 drm_crtc_vblank_put(crtc);
1345 }
1346
1347 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1348                                     enum pipe pipe)
1349 {
1350         u32 val;
1351         bool enabled;
1352
1353         val = I915_READ(PCH_TRANSCONF(pipe));
1354         enabled = !!(val & TRANS_ENABLE);
1355         I915_STATE_WARN(enabled,
1356              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1357              pipe_name(pipe));
1358 }
1359
1360 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1361                                    enum pipe pipe, enum port port,
1362                                    i915_reg_t dp_reg)
1363 {
1364         enum pipe port_pipe;
1365         bool state;
1366
1367         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1368
1369         I915_STATE_WARN(state && port_pipe == pipe,
1370                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1371                         port_name(port), pipe_name(pipe));
1372
1373         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1374                         "IBX PCH DP %c still using transcoder B\n",
1375                         port_name(port));
1376 }
1377
1378 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1379                                      enum pipe pipe, enum port port,
1380                                      i915_reg_t hdmi_reg)
1381 {
1382         enum pipe port_pipe;
1383         bool state;
1384
1385         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1386
1387         I915_STATE_WARN(state && port_pipe == pipe,
1388                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1389                         port_name(port), pipe_name(pipe));
1390
1391         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1392                         "IBX PCH HDMI %c still using transcoder B\n",
1393                         port_name(port));
1394 }
1395
1396 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1397                                       enum pipe pipe)
1398 {
1399         enum pipe port_pipe;
1400
1401         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1402         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1403         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1404
1405         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1406                         port_pipe == pipe,
1407                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1408                         pipe_name(pipe));
1409
1410         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1411                         port_pipe == pipe,
1412                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1413                         pipe_name(pipe));
1414
1415         /* PCH SDVOB multiplex with HDMIB */
1416         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1417         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1418         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1419 }
1420
1421 static void _vlv_enable_pll(struct intel_crtc *crtc,
1422                             const struct intel_crtc_state *pipe_config)
1423 {
1424         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1425         enum pipe pipe = crtc->pipe;
1426
1427         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1428         POSTING_READ(DPLL(pipe));
1429         udelay(150);
1430
1431         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1432                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1433 }
1434
1435 static void vlv_enable_pll(struct intel_crtc *crtc,
1436                            const struct intel_crtc_state *pipe_config)
1437 {
1438         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1439         enum pipe pipe = crtc->pipe;
1440
1441         assert_pipe_disabled(dev_priv, pipe);
1442
1443         /* PLL is protected by panel, make sure we can write it */
1444         assert_panel_unlocked(dev_priv, pipe);
1445
1446         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1447                 _vlv_enable_pll(crtc, pipe_config);
1448
1449         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1450         POSTING_READ(DPLL_MD(pipe));
1451 }
1452
1453
1454 static void _chv_enable_pll(struct intel_crtc *crtc,
1455                             const struct intel_crtc_state *pipe_config)
1456 {
1457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1458         enum pipe pipe = crtc->pipe;
1459         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1460         u32 tmp;
1461
1462         vlv_dpio_get(dev_priv);
1463
1464         /* Enable back the 10bit clock to display controller */
1465         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1466         tmp |= DPIO_DCLKP_EN;
1467         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1468
1469         vlv_dpio_put(dev_priv);
1470
1471         /*
1472          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1473          */
1474         udelay(1);
1475
1476         /* Enable PLL */
1477         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1478
1479         /* Check PLL is locked */
1480         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1481                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1482 }
1483
1484 static void chv_enable_pll(struct intel_crtc *crtc,
1485                            const struct intel_crtc_state *pipe_config)
1486 {
1487         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1488         enum pipe pipe = crtc->pipe;
1489
1490         assert_pipe_disabled(dev_priv, pipe);
1491
1492         /* PLL is protected by panel, make sure we can write it */
1493         assert_panel_unlocked(dev_priv, pipe);
1494
1495         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1496                 _chv_enable_pll(crtc, pipe_config);
1497
1498         if (pipe != PIPE_A) {
1499                 /*
1500                  * WaPixelRepeatModeFixForC0:chv
1501                  *
1502                  * DPLLCMD is AWOL. Use chicken bits to propagate
1503                  * the value from DPLLBMD to either pipe B or C.
1504                  */
1505                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1506                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1507                 I915_WRITE(CBR4_VLV, 0);
1508                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1509
1510                 /*
1511                  * DPLLB VGA mode also seems to cause problems.
1512                  * We should always have it disabled.
1513                  */
1514                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1515         } else {
1516                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1517                 POSTING_READ(DPLL_MD(pipe));
1518         }
1519 }
1520
1521 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1522 {
1523         if (IS_I830(dev_priv))
1524                 return false;
1525
1526         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1527 }
1528
1529 static void i9xx_enable_pll(struct intel_crtc *crtc,
1530                             const struct intel_crtc_state *crtc_state)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1533         i915_reg_t reg = DPLL(crtc->pipe);
1534         u32 dpll = crtc_state->dpll_hw_state.dpll;
1535         int i;
1536
1537         assert_pipe_disabled(dev_priv, crtc->pipe);
1538
1539         /* PLL is protected by panel, make sure we can write it */
1540         if (i9xx_has_pps(dev_priv))
1541                 assert_panel_unlocked(dev_priv, crtc->pipe);
1542
1543         /*
1544          * Apparently we need to have VGA mode enabled prior to changing
1545          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1546          * dividers, even though the register value does change.
1547          */
1548         I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1549         I915_WRITE(reg, dpll);
1550
1551         /* Wait for the clocks to stabilize. */
1552         POSTING_READ(reg);
1553         udelay(150);
1554
1555         if (INTEL_GEN(dev_priv) >= 4) {
1556                 I915_WRITE(DPLL_MD(crtc->pipe),
1557                            crtc_state->dpll_hw_state.dpll_md);
1558         } else {
1559                 /* The pixel multiplier can only be updated once the
1560                  * DPLL is enabled and the clocks are stable.
1561                  *
1562                  * So write it again.
1563                  */
1564                 I915_WRITE(reg, dpll);
1565         }
1566
1567         /* We do this three times for luck */
1568         for (i = 0; i < 3; i++) {
1569                 I915_WRITE(reg, dpll);
1570                 POSTING_READ(reg);
1571                 udelay(150); /* wait for warmup */
1572         }
1573 }
1574
1575 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1576 {
1577         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1578         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1579         enum pipe pipe = crtc->pipe;
1580
1581         /* Don't disable pipe or pipe PLLs if needed */
1582         if (IS_I830(dev_priv))
1583                 return;
1584
1585         /* Make sure the pipe isn't still relying on us */
1586         assert_pipe_disabled(dev_priv, pipe);
1587
1588         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1589         POSTING_READ(DPLL(pipe));
1590 }
1591
1592 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1593 {
1594         u32 val;
1595
1596         /* Make sure the pipe isn't still relying on us */
1597         assert_pipe_disabled(dev_priv, pipe);
1598
1599         val = DPLL_INTEGRATED_REF_CLK_VLV |
1600                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1601         if (pipe != PIPE_A)
1602                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1603
1604         I915_WRITE(DPLL(pipe), val);
1605         POSTING_READ(DPLL(pipe));
1606 }
1607
1608 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1609 {
1610         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1611         u32 val;
1612
1613         /* Make sure the pipe isn't still relying on us */
1614         assert_pipe_disabled(dev_priv, pipe);
1615
1616         val = DPLL_SSC_REF_CLK_CHV |
1617                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1618         if (pipe != PIPE_A)
1619                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1620
1621         I915_WRITE(DPLL(pipe), val);
1622         POSTING_READ(DPLL(pipe));
1623
1624         vlv_dpio_get(dev_priv);
1625
1626         /* Disable 10bit clock to display controller */
1627         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1628         val &= ~DPIO_DCLKP_EN;
1629         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1630
1631         vlv_dpio_put(dev_priv);
1632 }
1633
1634 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1635                          struct intel_digital_port *dport,
1636                          unsigned int expected_mask)
1637 {
1638         u32 port_mask;
1639         i915_reg_t dpll_reg;
1640
1641         switch (dport->base.port) {
1642         case PORT_B:
1643                 port_mask = DPLL_PORTB_READY_MASK;
1644                 dpll_reg = DPLL(0);
1645                 break;
1646         case PORT_C:
1647                 port_mask = DPLL_PORTC_READY_MASK;
1648                 dpll_reg = DPLL(0);
1649                 expected_mask <<= 4;
1650                 break;
1651         case PORT_D:
1652                 port_mask = DPLL_PORTD_READY_MASK;
1653                 dpll_reg = DPIO_PHY_STATUS;
1654                 break;
1655         default:
1656                 BUG();
1657         }
1658
1659         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1660                                        port_mask, expected_mask, 1000))
1661                 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1662                      dport->base.base.base.id, dport->base.base.name,
1663                      I915_READ(dpll_reg) & port_mask, expected_mask);
1664 }
1665
1666 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1667 {
1668         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1669         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1670         enum pipe pipe = crtc->pipe;
1671         i915_reg_t reg;
1672         u32 val, pipeconf_val;
1673
1674         /* Make sure PCH DPLL is enabled */
1675         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1676
1677         /* FDI must be feeding us bits for PCH ports */
1678         assert_fdi_tx_enabled(dev_priv, pipe);
1679         assert_fdi_rx_enabled(dev_priv, pipe);
1680
1681         if (HAS_PCH_CPT(dev_priv)) {
1682                 reg = TRANS_CHICKEN2(pipe);
1683                 val = I915_READ(reg);
1684                 /*
1685                  * Workaround: Set the timing override bit
1686                  * before enabling the pch transcoder.
1687                  */
1688                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1689                 /* Configure frame start delay to match the CPU */
1690                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1691                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1692                 I915_WRITE(reg, val);
1693         }
1694
1695         reg = PCH_TRANSCONF(pipe);
1696         val = I915_READ(reg);
1697         pipeconf_val = I915_READ(PIPECONF(pipe));
1698
1699         if (HAS_PCH_IBX(dev_priv)) {
1700                 /* Configure frame start delay to match the CPU */
1701                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1702                 val |= TRANS_FRAME_START_DELAY(0);
1703
1704                 /*
1705                  * Make the BPC in transcoder be consistent with
1706                  * that in pipeconf reg. For HDMI we must use 8bpc
1707                  * here for both 8bpc and 12bpc.
1708                  */
1709                 val &= ~PIPECONF_BPC_MASK;
1710                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1711                         val |= PIPECONF_8BPC;
1712                 else
1713                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1714         }
1715
1716         val &= ~TRANS_INTERLACE_MASK;
1717         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1718                 if (HAS_PCH_IBX(dev_priv) &&
1719                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1720                         val |= TRANS_LEGACY_INTERLACED_ILK;
1721                 else
1722                         val |= TRANS_INTERLACED;
1723         } else {
1724                 val |= TRANS_PROGRESSIVE;
1725         }
1726
1727         I915_WRITE(reg, val | TRANS_ENABLE);
1728         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1729                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1730 }
1731
1732 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1733                                       enum transcoder cpu_transcoder)
1734 {
1735         u32 val, pipeconf_val;
1736
1737         /* FDI must be feeding us bits for PCH ports */
1738         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1739         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1740
1741         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1742         /* Workaround: set timing override bit. */
1743         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1744         /* Configure frame start delay to match the CPU */
1745         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1746         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1747         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1748
1749         val = TRANS_ENABLE;
1750         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1751
1752         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1753             PIPECONF_INTERLACED_ILK)
1754                 val |= TRANS_INTERLACED;
1755         else
1756                 val |= TRANS_PROGRESSIVE;
1757
1758         I915_WRITE(LPT_TRANSCONF, val);
1759         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1760                                   TRANS_STATE_ENABLE, 100))
1761                 DRM_ERROR("Failed to enable PCH transcoder\n");
1762 }
1763
1764 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1765                                             enum pipe pipe)
1766 {
1767         i915_reg_t reg;
1768         u32 val;
1769
1770         /* FDI relies on the transcoder */
1771         assert_fdi_tx_disabled(dev_priv, pipe);
1772         assert_fdi_rx_disabled(dev_priv, pipe);
1773
1774         /* Ports must be off as well */
1775         assert_pch_ports_disabled(dev_priv, pipe);
1776
1777         reg = PCH_TRANSCONF(pipe);
1778         val = I915_READ(reg);
1779         val &= ~TRANS_ENABLE;
1780         I915_WRITE(reg, val);
1781         /* wait for PCH transcoder off, transcoder state */
1782         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1783                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1784
1785         if (HAS_PCH_CPT(dev_priv)) {
1786                 /* Workaround: Clear the timing override chicken bit again. */
1787                 reg = TRANS_CHICKEN2(pipe);
1788                 val = I915_READ(reg);
1789                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1790                 I915_WRITE(reg, val);
1791         }
1792 }
1793
1794 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1795 {
1796         u32 val;
1797
1798         val = I915_READ(LPT_TRANSCONF);
1799         val &= ~TRANS_ENABLE;
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         /* wait for PCH transcoder off, transcoder state */
1802         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE, 50))
1804                 DRM_ERROR("Failed to disable PCH transcoder\n");
1805
1806         /* Workaround: clear timing override bit. */
1807         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1808         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1809         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1810 }
1811
1812 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1813 {
1814         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1815
1816         if (HAS_PCH_LPT(dev_priv))
1817                 return PIPE_A;
1818         else
1819                 return crtc->pipe;
1820 }
1821
1822 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1823 {
1824         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1825
1826         /*
1827          * On i965gm the hardware frame counter reads
1828          * zero when the TV encoder is enabled :(
1829          */
1830         if (IS_I965GM(dev_priv) &&
1831             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1832                 return 0;
1833
1834         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1835                 return 0xffffffff; /* full 32 bit counter */
1836         else if (INTEL_GEN(dev_priv) >= 3)
1837                 return 0xffffff; /* only 24 bits of frame count */
1838         else
1839                 return 0; /* Gen2 doesn't have a hardware frame counter */
1840 }
1841
1842 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1843 {
1844         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1845
1846         assert_vblank_disabled(&crtc->base);
1847         drm_crtc_set_max_vblank_count(&crtc->base,
1848                                       intel_crtc_max_vblank_count(crtc_state));
1849         drm_crtc_vblank_on(&crtc->base);
1850 }
1851
1852 static void intel_crtc_vblank_off(struct intel_crtc *crtc)
1853 {
1854         drm_crtc_vblank_off(&crtc->base);
1855         assert_vblank_disabled(&crtc->base);
1856 }
1857
1858 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1859 {
1860         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1861         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1862         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1863         enum pipe pipe = crtc->pipe;
1864         i915_reg_t reg;
1865         u32 val;
1866
1867         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1868
1869         assert_planes_disabled(crtc);
1870
1871         /*
1872          * A pipe without a PLL won't actually be able to drive bits from
1873          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1874          * need the check.
1875          */
1876         if (HAS_GMCH(dev_priv)) {
1877                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1878                         assert_dsi_pll_enabled(dev_priv);
1879                 else
1880                         assert_pll_enabled(dev_priv, pipe);
1881         } else {
1882                 if (new_crtc_state->has_pch_encoder) {
1883                         /* if driving the PCH, we need FDI enabled */
1884                         assert_fdi_rx_pll_enabled(dev_priv,
1885                                                   intel_crtc_pch_transcoder(crtc));
1886                         assert_fdi_tx_pll_enabled(dev_priv,
1887                                                   (enum pipe) cpu_transcoder);
1888                 }
1889                 /* FIXME: assert CPU port conditions for SNB+ */
1890         }
1891
1892         trace_intel_pipe_enable(crtc);
1893
1894         reg = PIPECONF(cpu_transcoder);
1895         val = I915_READ(reg);
1896         if (val & PIPECONF_ENABLE) {
1897                 /* we keep both pipes enabled on 830 */
1898                 WARN_ON(!IS_I830(dev_priv));
1899                 return;
1900         }
1901
1902         I915_WRITE(reg, val | PIPECONF_ENABLE);
1903         POSTING_READ(reg);
1904
1905         /*
1906          * Until the pipe starts PIPEDSL reads will return a stale value,
1907          * which causes an apparent vblank timestamp jump when PIPEDSL
1908          * resets to its proper value. That also messes up the frame count
1909          * when it's derived from the timestamps. So let's wait for the
1910          * pipe to start properly before we call drm_crtc_vblank_on()
1911          */
1912         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1913                 intel_wait_for_pipe_scanline_moving(crtc);
1914 }
1915
1916 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1917 {
1918         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1919         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1920         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1921         enum pipe pipe = crtc->pipe;
1922         i915_reg_t reg;
1923         u32 val;
1924
1925         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1926
1927         /*
1928          * Make sure planes won't keep trying to pump pixels to us,
1929          * or we might hang the display.
1930          */
1931         assert_planes_disabled(crtc);
1932
1933         trace_intel_pipe_disable(crtc);
1934
1935         reg = PIPECONF(cpu_transcoder);
1936         val = I915_READ(reg);
1937         if ((val & PIPECONF_ENABLE) == 0)
1938                 return;
1939
1940         /*
1941          * Double wide has implications for planes
1942          * so best keep it disabled when not needed.
1943          */
1944         if (old_crtc_state->double_wide)
1945                 val &= ~PIPECONF_DOUBLE_WIDE;
1946
1947         /* Don't disable pipe or pipe PLLs if needed */
1948         if (!IS_I830(dev_priv))
1949                 val &= ~PIPECONF_ENABLE;
1950
1951         I915_WRITE(reg, val);
1952         if ((val & PIPECONF_ENABLE) == 0)
1953                 intel_wait_for_pipe_off(old_crtc_state);
1954 }
1955
1956 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1957 {
1958         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1959 }
1960
1961 static unsigned int
1962 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1963 {
1964         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1965         unsigned int cpp = fb->format->cpp[color_plane];
1966
1967         switch (fb->modifier) {
1968         case DRM_FORMAT_MOD_LINEAR:
1969                 return intel_tile_size(dev_priv);
1970         case I915_FORMAT_MOD_X_TILED:
1971                 if (IS_GEN(dev_priv, 2))
1972                         return 128;
1973                 else
1974                         return 512;
1975         case I915_FORMAT_MOD_Y_TILED_CCS:
1976                 if (color_plane == 1)
1977                         return 128;
1978                 /* fall through */
1979         case I915_FORMAT_MOD_Y_TILED:
1980                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1981                         return 128;
1982                 else
1983                         return 512;
1984         case I915_FORMAT_MOD_Yf_TILED_CCS:
1985                 if (color_plane == 1)
1986                         return 128;
1987                 /* fall through */
1988         case I915_FORMAT_MOD_Yf_TILED:
1989                 switch (cpp) {
1990                 case 1:
1991                         return 64;
1992                 case 2:
1993                 case 4:
1994                         return 128;
1995                 case 8:
1996                 case 16:
1997                         return 256;
1998                 default:
1999                         MISSING_CASE(cpp);
2000                         return cpp;
2001                 }
2002                 break;
2003         default:
2004                 MISSING_CASE(fb->modifier);
2005                 return cpp;
2006         }
2007 }
2008
2009 static unsigned int
2010 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2011 {
2012         return intel_tile_size(to_i915(fb->dev)) /
2013                 intel_tile_width_bytes(fb, color_plane);
2014 }
2015
2016 /* Return the tile dimensions in pixel units */
2017 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2018                             unsigned int *tile_width,
2019                             unsigned int *tile_height)
2020 {
2021         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2022         unsigned int cpp = fb->format->cpp[color_plane];
2023
2024         *tile_width = tile_width_bytes / cpp;
2025         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2026 }
2027
2028 unsigned int
2029 intel_fb_align_height(const struct drm_framebuffer *fb,
2030                       int color_plane, unsigned int height)
2031 {
2032         unsigned int tile_height = intel_tile_height(fb, color_plane);
2033
2034         return ALIGN(height, tile_height);
2035 }
2036
2037 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2038 {
2039         unsigned int size = 0;
2040         int i;
2041
2042         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2043                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2044
2045         return size;
2046 }
2047
2048 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2049 {
2050         unsigned int size = 0;
2051         int i;
2052
2053         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2054                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2055
2056         return size;
2057 }
2058
2059 static void
2060 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2061                         const struct drm_framebuffer *fb,
2062                         unsigned int rotation)
2063 {
2064         view->type = I915_GGTT_VIEW_NORMAL;
2065         if (drm_rotation_90_or_270(rotation)) {
2066                 view->type = I915_GGTT_VIEW_ROTATED;
2067                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2068         }
2069 }
2070
2071 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2072 {
2073         if (IS_I830(dev_priv))
2074                 return 16 * 1024;
2075         else if (IS_I85X(dev_priv))
2076                 return 256;
2077         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2078                 return 32;
2079         else
2080                 return 4 * 1024;
2081 }
2082
2083 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2084 {
2085         if (INTEL_GEN(dev_priv) >= 9)
2086                 return 256 * 1024;
2087         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2088                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2089                 return 128 * 1024;
2090         else if (INTEL_GEN(dev_priv) >= 4)
2091                 return 4 * 1024;
2092         else
2093                 return 0;
2094 }
2095
2096 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2097                                          int color_plane)
2098 {
2099         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2100
2101         /* AUX_DIST needs only 4K alignment */
2102         if (color_plane == 1)
2103                 return 4096;
2104
2105         switch (fb->modifier) {
2106         case DRM_FORMAT_MOD_LINEAR:
2107                 return intel_linear_alignment(dev_priv);
2108         case I915_FORMAT_MOD_X_TILED:
2109                 if (INTEL_GEN(dev_priv) >= 9)
2110                         return 256 * 1024;
2111                 return 0;
2112         case I915_FORMAT_MOD_Y_TILED_CCS:
2113         case I915_FORMAT_MOD_Yf_TILED_CCS:
2114         case I915_FORMAT_MOD_Y_TILED:
2115         case I915_FORMAT_MOD_Yf_TILED:
2116                 return 1 * 1024 * 1024;
2117         default:
2118                 MISSING_CASE(fb->modifier);
2119                 return 0;
2120         }
2121 }
2122
2123 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2124 {
2125         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2126         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2127
2128         return INTEL_GEN(dev_priv) < 4 ||
2129                 (plane->has_fbc &&
2130                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2131 }
2132
2133 struct i915_vma *
2134 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2135                            const struct i915_ggtt_view *view,
2136                            bool uses_fence,
2137                            unsigned long *out_flags)
2138 {
2139         struct drm_device *dev = fb->dev;
2140         struct drm_i915_private *dev_priv = to_i915(dev);
2141         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2142         intel_wakeref_t wakeref;
2143         struct i915_vma *vma;
2144         unsigned int pinctl;
2145         u32 alignment;
2146
2147         if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2148                 return ERR_PTR(-EINVAL);
2149
2150         alignment = intel_surf_alignment(fb, 0);
2151
2152         /* Note that the w/a also requires 64 PTE of padding following the
2153          * bo. We currently fill all unused PTE with the shadow page and so
2154          * we should always have valid PTE following the scanout preventing
2155          * the VT-d warning.
2156          */
2157         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2158                 alignment = 256 * 1024;
2159
2160         /*
2161          * Global gtt pte registers are special registers which actually forward
2162          * writes to a chunk of system memory. Which means that there is no risk
2163          * that the register values disappear as soon as we call
2164          * intel_runtime_pm_put(), so it is correct to wrap only the
2165          * pin/unpin/fence and not more.
2166          */
2167         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2168         i915_gem_object_lock(obj);
2169
2170         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2171
2172         pinctl = 0;
2173
2174         /* Valleyview is definitely limited to scanning out the first
2175          * 512MiB. Lets presume this behaviour was inherited from the
2176          * g4x display engine and that all earlier gen are similarly
2177          * limited. Testing suggests that it is a little more
2178          * complicated than this. For example, Cherryview appears quite
2179          * happy to scanout from anywhere within its global aperture.
2180          */
2181         if (HAS_GMCH(dev_priv))
2182                 pinctl |= PIN_MAPPABLE;
2183
2184         vma = i915_gem_object_pin_to_display_plane(obj,
2185                                                    alignment, view, pinctl);
2186         if (IS_ERR(vma))
2187                 goto err;
2188
2189         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2190                 int ret;
2191
2192                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2193                  * fence, whereas 965+ only requires a fence if using
2194                  * framebuffer compression.  For simplicity, we always, when
2195                  * possible, install a fence as the cost is not that onerous.
2196                  *
2197                  * If we fail to fence the tiled scanout, then either the
2198                  * modeset will reject the change (which is highly unlikely as
2199                  * the affected systems, all but one, do not have unmappable
2200                  * space) or we will not be able to enable full powersaving
2201                  * techniques (also likely not to apply due to various limits
2202                  * FBC and the like impose on the size of the buffer, which
2203                  * presumably we violated anyway with this unmappable buffer).
2204                  * Anyway, it is presumably better to stumble onwards with
2205                  * something and try to run the system in a "less than optimal"
2206                  * mode that matches the user configuration.
2207                  */
2208                 ret = i915_vma_pin_fence(vma);
2209                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2210                         i915_gem_object_unpin_from_display_plane(vma);
2211                         vma = ERR_PTR(ret);
2212                         goto err;
2213                 }
2214
2215                 if (ret == 0 && vma->fence)
2216                         *out_flags |= PLANE_HAS_FENCE;
2217         }
2218
2219         i915_vma_get(vma);
2220 err:
2221         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2222
2223         i915_gem_object_unlock(obj);
2224         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2225         return vma;
2226 }
2227
2228 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2229 {
2230         i915_gem_object_lock(vma->obj);
2231         if (flags & PLANE_HAS_FENCE)
2232                 i915_vma_unpin_fence(vma);
2233         i915_gem_object_unpin_from_display_plane(vma);
2234         i915_gem_object_unlock(vma->obj);
2235
2236         i915_vma_put(vma);
2237 }
2238
2239 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2240                           unsigned int rotation)
2241 {
2242         if (drm_rotation_90_or_270(rotation))
2243                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2244         else
2245                 return fb->pitches[color_plane];
2246 }
2247
2248 /*
2249  * Convert the x/y offsets into a linear offset.
2250  * Only valid with 0/180 degree rotation, which is fine since linear
2251  * offset is only used with linear buffers on pre-hsw and tiled buffers
2252  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2253  */
2254 u32 intel_fb_xy_to_linear(int x, int y,
2255                           const struct intel_plane_state *state,
2256                           int color_plane)
2257 {
2258         const struct drm_framebuffer *fb = state->hw.fb;
2259         unsigned int cpp = fb->format->cpp[color_plane];
2260         unsigned int pitch = state->color_plane[color_plane].stride;
2261
2262         return y * pitch + x * cpp;
2263 }
2264
2265 /*
2266  * Add the x/y offsets derived from fb->offsets[] to the user
2267  * specified plane src x/y offsets. The resulting x/y offsets
2268  * specify the start of scanout from the beginning of the gtt mapping.
2269  */
2270 void intel_add_fb_offsets(int *x, int *y,
2271                           const struct intel_plane_state *state,
2272                           int color_plane)
2273
2274 {
2275         *x += state->color_plane[color_plane].x;
2276         *y += state->color_plane[color_plane].y;
2277 }
2278
2279 static u32 intel_adjust_tile_offset(int *x, int *y,
2280                                     unsigned int tile_width,
2281                                     unsigned int tile_height,
2282                                     unsigned int tile_size,
2283                                     unsigned int pitch_tiles,
2284                                     u32 old_offset,
2285                                     u32 new_offset)
2286 {
2287         unsigned int pitch_pixels = pitch_tiles * tile_width;
2288         unsigned int tiles;
2289
2290         WARN_ON(old_offset & (tile_size - 1));
2291         WARN_ON(new_offset & (tile_size - 1));
2292         WARN_ON(new_offset > old_offset);
2293
2294         tiles = (old_offset - new_offset) / tile_size;
2295
2296         *y += tiles / pitch_tiles * tile_height;
2297         *x += tiles % pitch_tiles * tile_width;
2298
2299         /* minimize x in case it got needlessly big */
2300         *y += *x / pitch_pixels * tile_height;
2301         *x %= pitch_pixels;
2302
2303         return new_offset;
2304 }
2305
2306 static bool is_surface_linear(u64 modifier, int color_plane)
2307 {
2308         return modifier == DRM_FORMAT_MOD_LINEAR;
2309 }
2310
2311 static u32 intel_adjust_aligned_offset(int *x, int *y,
2312                                        const struct drm_framebuffer *fb,
2313                                        int color_plane,
2314                                        unsigned int rotation,
2315                                        unsigned int pitch,
2316                                        u32 old_offset, u32 new_offset)
2317 {
2318         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2319         unsigned int cpp = fb->format->cpp[color_plane];
2320
2321         WARN_ON(new_offset > old_offset);
2322
2323         if (!is_surface_linear(fb->modifier, color_plane)) {
2324                 unsigned int tile_size, tile_width, tile_height;
2325                 unsigned int pitch_tiles;
2326
2327                 tile_size = intel_tile_size(dev_priv);
2328                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2329
2330                 if (drm_rotation_90_or_270(rotation)) {
2331                         pitch_tiles = pitch / tile_height;
2332                         swap(tile_width, tile_height);
2333                 } else {
2334                         pitch_tiles = pitch / (tile_width * cpp);
2335                 }
2336
2337                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2338                                          tile_size, pitch_tiles,
2339                                          old_offset, new_offset);
2340         } else {
2341                 old_offset += *y * pitch + *x * cpp;
2342
2343                 *y = (old_offset - new_offset) / pitch;
2344                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2345         }
2346
2347         return new_offset;
2348 }
2349
2350 /*
2351  * Adjust the tile offset by moving the difference into
2352  * the x/y offsets.
2353  */
2354 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2355                                              const struct intel_plane_state *state,
2356                                              int color_plane,
2357                                              u32 old_offset, u32 new_offset)
2358 {
2359         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2360                                            state->hw.rotation,
2361                                            state->color_plane[color_plane].stride,
2362                                            old_offset, new_offset);
2363 }
2364
2365 /*
2366  * Computes the aligned offset to the base tile and adjusts
2367  * x, y. bytes per pixel is assumed to be a power-of-two.
2368  *
2369  * In the 90/270 rotated case, x and y are assumed
2370  * to be already rotated to match the rotated GTT view, and
2371  * pitch is the tile_height aligned framebuffer height.
2372  *
2373  * This function is used when computing the derived information
2374  * under intel_framebuffer, so using any of that information
2375  * here is not allowed. Anything under drm_framebuffer can be
2376  * used. This is why the user has to pass in the pitch since it
2377  * is specified in the rotated orientation.
2378  */
2379 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2380                                         int *x, int *y,
2381                                         const struct drm_framebuffer *fb,
2382                                         int color_plane,
2383                                         unsigned int pitch,
2384                                         unsigned int rotation,
2385                                         u32 alignment)
2386 {
2387         unsigned int cpp = fb->format->cpp[color_plane];
2388         u32 offset, offset_aligned;
2389
2390         if (alignment)
2391                 alignment--;
2392
2393         if (!is_surface_linear(fb->modifier, color_plane)) {
2394                 unsigned int tile_size, tile_width, tile_height;
2395                 unsigned int tile_rows, tiles, pitch_tiles;
2396
2397                 tile_size = intel_tile_size(dev_priv);
2398                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2399
2400                 if (drm_rotation_90_or_270(rotation)) {
2401                         pitch_tiles = pitch / tile_height;
2402                         swap(tile_width, tile_height);
2403                 } else {
2404                         pitch_tiles = pitch / (tile_width * cpp);
2405                 }
2406
2407                 tile_rows = *y / tile_height;
2408                 *y %= tile_height;
2409
2410                 tiles = *x / tile_width;
2411                 *x %= tile_width;
2412
2413                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2414                 offset_aligned = offset & ~alignment;
2415
2416                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2417                                          tile_size, pitch_tiles,
2418                                          offset, offset_aligned);
2419         } else {
2420                 offset = *y * pitch + *x * cpp;
2421                 offset_aligned = offset & ~alignment;
2422
2423                 *y = (offset & alignment) / pitch;
2424                 *x = ((offset & alignment) - *y * pitch) / cpp;
2425         }
2426
2427         return offset_aligned;
2428 }
2429
2430 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2431                                               const struct intel_plane_state *state,
2432                                               int color_plane)
2433 {
2434         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2435         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2436         const struct drm_framebuffer *fb = state->hw.fb;
2437         unsigned int rotation = state->hw.rotation;
2438         int pitch = state->color_plane[color_plane].stride;
2439         u32 alignment;
2440
2441         if (intel_plane->id == PLANE_CURSOR)
2442                 alignment = intel_cursor_alignment(dev_priv);
2443         else
2444                 alignment = intel_surf_alignment(fb, color_plane);
2445
2446         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2447                                             pitch, rotation, alignment);
2448 }
2449
2450 /* Convert the fb->offset[] into x/y offsets */
2451 static int intel_fb_offset_to_xy(int *x, int *y,
2452                                  const struct drm_framebuffer *fb,
2453                                  int color_plane)
2454 {
2455         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2456         unsigned int height;
2457
2458         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2459             fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2460                 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2461                               fb->offsets[color_plane], color_plane);
2462                 return -EINVAL;
2463         }
2464
2465         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2466         height = ALIGN(height, intel_tile_height(fb, color_plane));
2467
2468         /* Catch potential overflows early */
2469         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2470                             fb->offsets[color_plane])) {
2471                 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2472                               fb->offsets[color_plane], fb->pitches[color_plane],
2473                               color_plane);
2474                 return -ERANGE;
2475         }
2476
2477         *x = 0;
2478         *y = 0;
2479
2480         intel_adjust_aligned_offset(x, y,
2481                                     fb, color_plane, DRM_MODE_ROTATE_0,
2482                                     fb->pitches[color_plane],
2483                                     fb->offsets[color_plane], 0);
2484
2485         return 0;
2486 }
2487
2488 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2489 {
2490         switch (fb_modifier) {
2491         case I915_FORMAT_MOD_X_TILED:
2492                 return I915_TILING_X;
2493         case I915_FORMAT_MOD_Y_TILED:
2494         case I915_FORMAT_MOD_Y_TILED_CCS:
2495                 return I915_TILING_Y;
2496         default:
2497                 return I915_TILING_NONE;
2498         }
2499 }
2500
2501 /*
2502  * From the Sky Lake PRM:
2503  * "The Color Control Surface (CCS) contains the compression status of
2504  *  the cache-line pairs. The compression state of the cache-line pair
2505  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2506  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2507  *  cache-line-pairs. CCS is always Y tiled."
2508  *
2509  * Since cache line pairs refers to horizontally adjacent cache lines,
2510  * each cache line in the CCS corresponds to an area of 32x16 cache
2511  * lines on the main surface. Since each pixel is 4 bytes, this gives
2512  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2513  * main surface.
2514  */
2515 static const struct drm_format_info ccs_formats[] = {
2516         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2517           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2518         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2519           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2520         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2521           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2522         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2523           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2524 };
2525
2526 static const struct drm_format_info *
2527 lookup_format_info(const struct drm_format_info formats[],
2528                    int num_formats, u32 format)
2529 {
2530         int i;
2531
2532         for (i = 0; i < num_formats; i++) {
2533                 if (formats[i].format == format)
2534                         return &formats[i];
2535         }
2536
2537         return NULL;
2538 }
2539
2540 static const struct drm_format_info *
2541 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2542 {
2543         switch (cmd->modifier[0]) {
2544         case I915_FORMAT_MOD_Y_TILED_CCS:
2545         case I915_FORMAT_MOD_Yf_TILED_CCS:
2546                 return lookup_format_info(ccs_formats,
2547                                           ARRAY_SIZE(ccs_formats),
2548                                           cmd->pixel_format);
2549         default:
2550                 return NULL;
2551         }
2552 }
2553
2554 bool is_ccs_modifier(u64 modifier)
2555 {
2556         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2557                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2558 }
2559
2560 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2561                               u32 pixel_format, u64 modifier)
2562 {
2563         struct intel_crtc *crtc;
2564         struct intel_plane *plane;
2565
2566         /*
2567          * We assume the primary plane for pipe A has
2568          * the highest stride limits of them all.
2569          */
2570         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2571         if (!crtc)
2572                 return 0;
2573
2574         plane = to_intel_plane(crtc->base.primary);
2575
2576         return plane->max_stride(plane, pixel_format, modifier,
2577                                  DRM_MODE_ROTATE_0);
2578 }
2579
2580 static
2581 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2582                         u32 pixel_format, u64 modifier)
2583 {
2584         /*
2585          * Arbitrary limit for gen4+ chosen to match the
2586          * render engine max stride.
2587          *
2588          * The new CCS hash mode makes remapping impossible
2589          */
2590         if (!is_ccs_modifier(modifier)) {
2591                 if (INTEL_GEN(dev_priv) >= 7)
2592                         return 256*1024;
2593                 else if (INTEL_GEN(dev_priv) >= 4)
2594                         return 128*1024;
2595         }
2596
2597         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2598 }
2599
2600 static u32
2601 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2602 {
2603         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2604
2605         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2606                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2607                                                            fb->format->format,
2608                                                            fb->modifier);
2609
2610                 /*
2611                  * To make remapping with linear generally feasible
2612                  * we need the stride to be page aligned.
2613                  */
2614                 if (fb->pitches[color_plane] > max_stride)
2615                         return intel_tile_size(dev_priv);
2616                 else
2617                         return 64;
2618         } else {
2619                 return intel_tile_width_bytes(fb, color_plane);
2620         }
2621 }
2622
2623 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2624 {
2625         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2626         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2627         const struct drm_framebuffer *fb = plane_state->hw.fb;
2628         int i;
2629
2630         /* We don't want to deal with remapping with cursors */
2631         if (plane->id == PLANE_CURSOR)
2632                 return false;
2633
2634         /*
2635          * The display engine limits already match/exceed the
2636          * render engine limits, so not much point in remapping.
2637          * Would also need to deal with the fence POT alignment
2638          * and gen2 2KiB GTT tile size.
2639          */
2640         if (INTEL_GEN(dev_priv) < 4)
2641                 return false;
2642
2643         /*
2644          * The new CCS hash mode isn't compatible with remapping as
2645          * the virtual address of the pages affects the compressed data.
2646          */
2647         if (is_ccs_modifier(fb->modifier))
2648                 return false;
2649
2650         /* Linear needs a page aligned stride for remapping */
2651         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2652                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2653
2654                 for (i = 0; i < fb->format->num_planes; i++) {
2655                         if (fb->pitches[i] & alignment)
2656                                 return false;
2657                 }
2658         }
2659
2660         return true;
2661 }
2662
2663 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2664 {
2665         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2666         const struct drm_framebuffer *fb = plane_state->hw.fb;
2667         unsigned int rotation = plane_state->hw.rotation;
2668         u32 stride, max_stride;
2669
2670         /*
2671          * No remapping for invisible planes since we don't have
2672          * an actual source viewport to remap.
2673          */
2674         if (!plane_state->uapi.visible)
2675                 return false;
2676
2677         if (!intel_plane_can_remap(plane_state))
2678                 return false;
2679
2680         /*
2681          * FIXME: aux plane limits on gen9+ are
2682          * unclear in Bspec, for now no checking.
2683          */
2684         stride = intel_fb_pitch(fb, 0, rotation);
2685         max_stride = plane->max_stride(plane, fb->format->format,
2686                                        fb->modifier, rotation);
2687
2688         return stride > max_stride;
2689 }
2690
2691 static int
2692 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2693                    struct drm_framebuffer *fb)
2694 {
2695         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2696         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2697         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2698         u32 gtt_offset_rotated = 0;
2699         unsigned int max_size = 0;
2700         int i, num_planes = fb->format->num_planes;
2701         unsigned int tile_size = intel_tile_size(dev_priv);
2702
2703         for (i = 0; i < num_planes; i++) {
2704                 unsigned int width, height;
2705                 unsigned int cpp, size;
2706                 u32 offset;
2707                 int x, y;
2708                 int ret;
2709
2710                 cpp = fb->format->cpp[i];
2711                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2712                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2713
2714                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2715                 if (ret) {
2716                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2717                                       i, fb->offsets[i]);
2718                         return ret;
2719                 }
2720
2721                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2722                         int hsub = fb->format->hsub;
2723                         int vsub = fb->format->vsub;
2724                         int tile_width, tile_height;
2725                         int main_x, main_y;
2726                         int ccs_x, ccs_y;
2727
2728                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2729                         tile_width *= hsub;
2730                         tile_height *= vsub;
2731
2732                         ccs_x = (x * hsub) % tile_width;
2733                         ccs_y = (y * vsub) % tile_height;
2734                         main_x = intel_fb->normal[0].x % tile_width;
2735                         main_y = intel_fb->normal[0].y % tile_height;
2736
2737                         /*
2738                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2739                          * x/y offsets must match between CCS and the main surface.
2740                          */
2741                         if (main_x != ccs_x || main_y != ccs_y) {
2742                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2743                                               main_x, main_y,
2744                                               ccs_x, ccs_y,
2745                                               intel_fb->normal[0].x,
2746                                               intel_fb->normal[0].y,
2747                                               x, y);
2748                                 return -EINVAL;
2749                         }
2750                 }
2751
2752                 /*
2753                  * The fence (if used) is aligned to the start of the object
2754                  * so having the framebuffer wrap around across the edge of the
2755                  * fenced region doesn't really work. We have no API to configure
2756                  * the fence start offset within the object (nor could we probably
2757                  * on gen2/3). So it's just easier if we just require that the
2758                  * fb layout agrees with the fence layout. We already check that the
2759                  * fb stride matches the fence stride elsewhere.
2760                  */
2761                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2762                     (x + width) * cpp > fb->pitches[i]) {
2763                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2764                                       i, fb->offsets[i]);
2765                         return -EINVAL;
2766                 }
2767
2768                 /*
2769                  * First pixel of the framebuffer from
2770                  * the start of the normal gtt mapping.
2771                  */
2772                 intel_fb->normal[i].x = x;
2773                 intel_fb->normal[i].y = y;
2774
2775                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2776                                                       fb->pitches[i],
2777                                                       DRM_MODE_ROTATE_0,
2778                                                       tile_size);
2779                 offset /= tile_size;
2780
2781                 if (!is_surface_linear(fb->modifier, i)) {
2782                         unsigned int tile_width, tile_height;
2783                         unsigned int pitch_tiles;
2784                         struct drm_rect r;
2785
2786                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2787
2788                         rot_info->plane[i].offset = offset;
2789                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2790                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2791                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2792
2793                         intel_fb->rotated[i].pitch =
2794                                 rot_info->plane[i].height * tile_height;
2795
2796                         /* how many tiles does this plane need */
2797                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2798                         /*
2799                          * If the plane isn't horizontally tile aligned,
2800                          * we need one more tile.
2801                          */
2802                         if (x != 0)
2803                                 size++;
2804
2805                         /* rotate the x/y offsets to match the GTT view */
2806                         drm_rect_init(&r, x, y, width, height);
2807                         drm_rect_rotate(&r,
2808                                         rot_info->plane[i].width * tile_width,
2809                                         rot_info->plane[i].height * tile_height,
2810                                         DRM_MODE_ROTATE_270);
2811                         x = r.x1;
2812                         y = r.y1;
2813
2814                         /* rotate the tile dimensions to match the GTT view */
2815                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2816                         swap(tile_width, tile_height);
2817
2818                         /*
2819                          * We only keep the x/y offsets, so push all of the
2820                          * gtt offset into the x/y offsets.
2821                          */
2822                         intel_adjust_tile_offset(&x, &y,
2823                                                  tile_width, tile_height,
2824                                                  tile_size, pitch_tiles,
2825                                                  gtt_offset_rotated * tile_size, 0);
2826
2827                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2828
2829                         /*
2830                          * First pixel of the framebuffer from
2831                          * the start of the rotated gtt mapping.
2832                          */
2833                         intel_fb->rotated[i].x = x;
2834                         intel_fb->rotated[i].y = y;
2835                 } else {
2836                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2837                                             x * cpp, tile_size);
2838                 }
2839
2840                 /* how many tiles in total needed in the bo */
2841                 max_size = max(max_size, offset + size);
2842         }
2843
2844         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2845                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2846                               mul_u32_u32(max_size, tile_size), obj->base.size);
2847                 return -EINVAL;
2848         }
2849
2850         return 0;
2851 }
2852
2853 static void
2854 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2855 {
2856         struct drm_i915_private *dev_priv =
2857                 to_i915(plane_state->uapi.plane->dev);
2858         struct drm_framebuffer *fb = plane_state->hw.fb;
2859         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2860         struct intel_rotation_info *info = &plane_state->view.rotated;
2861         unsigned int rotation = plane_state->hw.rotation;
2862         int i, num_planes = fb->format->num_planes;
2863         unsigned int tile_size = intel_tile_size(dev_priv);
2864         unsigned int src_x, src_y;
2865         unsigned int src_w, src_h;
2866         u32 gtt_offset = 0;
2867
2868         memset(&plane_state->view, 0, sizeof(plane_state->view));
2869         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2870                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2871
2872         src_x = plane_state->uapi.src.x1 >> 16;
2873         src_y = plane_state->uapi.src.y1 >> 16;
2874         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2875         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2876
2877         WARN_ON(is_ccs_modifier(fb->modifier));
2878
2879         /* Make src coordinates relative to the viewport */
2880         drm_rect_translate(&plane_state->uapi.src,
2881                            -(src_x << 16), -(src_y << 16));
2882
2883         /* Rotate src coordinates to match rotated GTT view */
2884         if (drm_rotation_90_or_270(rotation))
2885                 drm_rect_rotate(&plane_state->uapi.src,
2886                                 src_w << 16, src_h << 16,
2887                                 DRM_MODE_ROTATE_270);
2888
2889         for (i = 0; i < num_planes; i++) {
2890                 unsigned int hsub = i ? fb->format->hsub : 1;
2891                 unsigned int vsub = i ? fb->format->vsub : 1;
2892                 unsigned int cpp = fb->format->cpp[i];
2893                 unsigned int tile_width, tile_height;
2894                 unsigned int width, height;
2895                 unsigned int pitch_tiles;
2896                 unsigned int x, y;
2897                 u32 offset;
2898
2899                 intel_tile_dims(fb, i, &tile_width, &tile_height);
2900
2901                 x = src_x / hsub;
2902                 y = src_y / vsub;
2903                 width = src_w / hsub;
2904                 height = src_h / vsub;
2905
2906                 /*
2907                  * First pixel of the src viewport from the
2908                  * start of the normal gtt mapping.
2909                  */
2910                 x += intel_fb->normal[i].x;
2911                 y += intel_fb->normal[i].y;
2912
2913                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2914                                                       fb, i, fb->pitches[i],
2915                                                       DRM_MODE_ROTATE_0, tile_size);
2916                 offset /= tile_size;
2917
2918                 info->plane[i].offset = offset;
2919                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2920                                                      tile_width * cpp);
2921                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2922                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2923
2924                 if (drm_rotation_90_or_270(rotation)) {
2925                         struct drm_rect r;
2926
2927                         /* rotate the x/y offsets to match the GTT view */
2928                         drm_rect_init(&r, x, y, width, height);
2929                         drm_rect_rotate(&r,
2930                                         info->plane[i].width * tile_width,
2931                                         info->plane[i].height * tile_height,
2932                                         DRM_MODE_ROTATE_270);
2933                         x = r.x1;
2934                         y = r.y1;
2935
2936                         pitch_tiles = info->plane[i].height;
2937                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2938
2939                         /* rotate the tile dimensions to match the GTT view */
2940                         swap(tile_width, tile_height);
2941                 } else {
2942                         pitch_tiles = info->plane[i].width;
2943                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2944                 }
2945
2946                 /*
2947                  * We only keep the x/y offsets, so push all of the
2948                  * gtt offset into the x/y offsets.
2949                  */
2950                 intel_adjust_tile_offset(&x, &y,
2951                                          tile_width, tile_height,
2952                                          tile_size, pitch_tiles,
2953                                          gtt_offset * tile_size, 0);
2954
2955                 gtt_offset += info->plane[i].width * info->plane[i].height;
2956
2957                 plane_state->color_plane[i].offset = 0;
2958                 plane_state->color_plane[i].x = x;
2959                 plane_state->color_plane[i].y = y;
2960         }
2961 }
2962
2963 static int
2964 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2965 {
2966         const struct intel_framebuffer *fb =
2967                 to_intel_framebuffer(plane_state->hw.fb);
2968         unsigned int rotation = plane_state->hw.rotation;
2969         int i, num_planes;
2970
2971         if (!fb)
2972                 return 0;
2973
2974         num_planes = fb->base.format->num_planes;
2975
2976         if (intel_plane_needs_remap(plane_state)) {
2977                 intel_plane_remap_gtt(plane_state);
2978
2979                 /*
2980                  * Sometimes even remapping can't overcome
2981                  * the stride limitations :( Can happen with
2982                  * big plane sizes and suitably misaligned
2983                  * offsets.
2984                  */
2985                 return intel_plane_check_stride(plane_state);
2986         }
2987
2988         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2989
2990         for (i = 0; i < num_planes; i++) {
2991                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2992                 plane_state->color_plane[i].offset = 0;
2993
2994                 if (drm_rotation_90_or_270(rotation)) {
2995                         plane_state->color_plane[i].x = fb->rotated[i].x;
2996                         plane_state->color_plane[i].y = fb->rotated[i].y;
2997                 } else {
2998                         plane_state->color_plane[i].x = fb->normal[i].x;
2999                         plane_state->color_plane[i].y = fb->normal[i].y;
3000                 }
3001         }
3002
3003         /* Rotate src coordinates to match rotated GTT view */
3004         if (drm_rotation_90_or_270(rotation))
3005                 drm_rect_rotate(&plane_state->uapi.src,
3006                                 fb->base.width << 16, fb->base.height << 16,
3007                                 DRM_MODE_ROTATE_270);
3008
3009         return intel_plane_check_stride(plane_state);
3010 }
3011
3012 static int i9xx_format_to_fourcc(int format)
3013 {
3014         switch (format) {
3015         case DISPPLANE_8BPP:
3016                 return DRM_FORMAT_C8;
3017         case DISPPLANE_BGRA555:
3018                 return DRM_FORMAT_ARGB1555;
3019         case DISPPLANE_BGRX555:
3020                 return DRM_FORMAT_XRGB1555;
3021         case DISPPLANE_BGRX565:
3022                 return DRM_FORMAT_RGB565;
3023         default:
3024         case DISPPLANE_BGRX888:
3025                 return DRM_FORMAT_XRGB8888;
3026         case DISPPLANE_RGBX888:
3027                 return DRM_FORMAT_XBGR8888;
3028         case DISPPLANE_BGRA888:
3029                 return DRM_FORMAT_ARGB8888;
3030         case DISPPLANE_RGBA888:
3031                 return DRM_FORMAT_ABGR8888;
3032         case DISPPLANE_BGRX101010:
3033                 return DRM_FORMAT_XRGB2101010;
3034         case DISPPLANE_RGBX101010:
3035                 return DRM_FORMAT_XBGR2101010;
3036         case DISPPLANE_BGRA101010:
3037                 return DRM_FORMAT_ARGB2101010;
3038         case DISPPLANE_RGBA101010:
3039                 return DRM_FORMAT_ABGR2101010;
3040         case DISPPLANE_RGBX161616:
3041                 return DRM_FORMAT_XBGR16161616F;
3042         }
3043 }
3044
3045 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3046 {
3047         switch (format) {
3048         case PLANE_CTL_FORMAT_RGB_565:
3049                 return DRM_FORMAT_RGB565;
3050         case PLANE_CTL_FORMAT_NV12:
3051                 return DRM_FORMAT_NV12;
3052         case PLANE_CTL_FORMAT_P010:
3053                 return DRM_FORMAT_P010;
3054         case PLANE_CTL_FORMAT_P012:
3055                 return DRM_FORMAT_P012;
3056         case PLANE_CTL_FORMAT_P016:
3057                 return DRM_FORMAT_P016;
3058         case PLANE_CTL_FORMAT_Y210:
3059                 return DRM_FORMAT_Y210;
3060         case PLANE_CTL_FORMAT_Y212:
3061                 return DRM_FORMAT_Y212;
3062         case PLANE_CTL_FORMAT_Y216:
3063                 return DRM_FORMAT_Y216;
3064         case PLANE_CTL_FORMAT_Y410:
3065                 return DRM_FORMAT_XVYU2101010;
3066         case PLANE_CTL_FORMAT_Y412:
3067                 return DRM_FORMAT_XVYU12_16161616;
3068         case PLANE_CTL_FORMAT_Y416:
3069                 return DRM_FORMAT_XVYU16161616;
3070         default:
3071         case PLANE_CTL_FORMAT_XRGB_8888:
3072                 if (rgb_order) {
3073                         if (alpha)
3074                                 return DRM_FORMAT_ABGR8888;
3075                         else
3076                                 return DRM_FORMAT_XBGR8888;
3077                 } else {
3078                         if (alpha)
3079                                 return DRM_FORMAT_ARGB8888;
3080                         else
3081                                 return DRM_FORMAT_XRGB8888;
3082                 }
3083         case PLANE_CTL_FORMAT_XRGB_2101010:
3084                 if (rgb_order) {
3085                         if (alpha)
3086                                 return DRM_FORMAT_ABGR2101010;
3087                         else
3088                                 return DRM_FORMAT_XBGR2101010;
3089                 } else {
3090                         if (alpha)
3091                                 return DRM_FORMAT_ARGB2101010;
3092                         else
3093                                 return DRM_FORMAT_XRGB2101010;
3094                 }
3095         case PLANE_CTL_FORMAT_XRGB_16161616F:
3096                 if (rgb_order) {
3097                         if (alpha)
3098                                 return DRM_FORMAT_ABGR16161616F;
3099                         else
3100                                 return DRM_FORMAT_XBGR16161616F;
3101                 } else {
3102                         if (alpha)
3103                                 return DRM_FORMAT_ARGB16161616F;
3104                         else
3105                                 return DRM_FORMAT_XRGB16161616F;
3106                 }
3107         }
3108 }
3109
3110 static bool
3111 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3112                               struct intel_initial_plane_config *plane_config)
3113 {
3114         struct drm_device *dev = crtc->base.dev;
3115         struct drm_i915_private *dev_priv = to_i915(dev);
3116         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3117         struct drm_framebuffer *fb = &plane_config->fb->base;
3118         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3119         u32 size_aligned = round_up(plane_config->base + plane_config->size,
3120                                     PAGE_SIZE);
3121         struct drm_i915_gem_object *obj;
3122         bool ret = false;
3123
3124         size_aligned -= base_aligned;
3125
3126         if (plane_config->size == 0)
3127                 return false;
3128
3129         /* If the FB is too big, just don't use it since fbdev is not very
3130          * important and we should probably use that space with FBC or other
3131          * features. */
3132         if (size_aligned * 2 > dev_priv->stolen_usable_size)
3133                 return false;
3134
3135         switch (fb->modifier) {
3136         case DRM_FORMAT_MOD_LINEAR:
3137         case I915_FORMAT_MOD_X_TILED:
3138         case I915_FORMAT_MOD_Y_TILED:
3139                 break;
3140         default:
3141                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3142                                  fb->modifier);
3143                 return false;
3144         }
3145
3146         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3147                                                              base_aligned,
3148                                                              base_aligned,
3149                                                              size_aligned);
3150         if (IS_ERR(obj))
3151                 return false;
3152
3153         switch (plane_config->tiling) {
3154         case I915_TILING_NONE:
3155                 break;
3156         case I915_TILING_X:
3157         case I915_TILING_Y:
3158                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3159                 break;
3160         default:
3161                 MISSING_CASE(plane_config->tiling);
3162                 goto out;
3163         }
3164
3165         mode_cmd.pixel_format = fb->format->format;
3166         mode_cmd.width = fb->width;
3167         mode_cmd.height = fb->height;
3168         mode_cmd.pitches[0] = fb->pitches[0];
3169         mode_cmd.modifier[0] = fb->modifier;
3170         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3171
3172         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3173                 DRM_DEBUG_KMS("intel fb init failed\n");
3174                 goto out;
3175         }
3176
3177
3178         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3179         ret = true;
3180 out:
3181         i915_gem_object_put(obj);
3182         return ret;
3183 }
3184
3185 static void
3186 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3187                         struct intel_plane_state *plane_state,
3188                         bool visible)
3189 {
3190         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3191
3192         plane_state->uapi.visible = visible;
3193
3194         if (visible)
3195                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3196         else
3197                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3198 }
3199
3200 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3201 {
3202         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3203         struct drm_plane *plane;
3204
3205         /*
3206          * Active_planes aliases if multiple "primary" or cursor planes
3207          * have been used on the same (or wrong) pipe. plane_mask uses
3208          * unique ids, hence we can use that to reconstruct active_planes.
3209          */
3210         crtc_state->active_planes = 0;
3211
3212         drm_for_each_plane_mask(plane, &dev_priv->drm,
3213                                 crtc_state->uapi.plane_mask)
3214                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3215 }
3216
3217 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3218                                          struct intel_plane *plane)
3219 {
3220         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3221         struct intel_crtc_state *crtc_state =
3222                 to_intel_crtc_state(crtc->base.state);
3223         struct intel_plane_state *plane_state =
3224                 to_intel_plane_state(plane->base.state);
3225
3226         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3227                       plane->base.base.id, plane->base.name,
3228                       crtc->base.base.id, crtc->base.name);
3229
3230         intel_set_plane_visible(crtc_state, plane_state, false);
3231         fixup_active_planes(crtc_state);
3232         crtc_state->data_rate[plane->id] = 0;
3233         crtc_state->min_cdclk[plane->id] = 0;
3234
3235         if (plane->id == PLANE_PRIMARY)
3236                 hsw_disable_ips(crtc_state);
3237
3238         /*
3239          * Vblank time updates from the shadow to live plane control register
3240          * are blocked if the memory self-refresh mode is active at that
3241          * moment. So to make sure the plane gets truly disabled, disable
3242          * first the self-refresh mode. The self-refresh enable bit in turn
3243          * will be checked/applied by the HW only at the next frame start
3244          * event which is after the vblank start event, so we need to have a
3245          * wait-for-vblank between disabling the plane and the pipe.
3246          */
3247         if (HAS_GMCH(dev_priv) &&
3248             intel_set_memory_cxsr(dev_priv, false))
3249                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3250
3251         /*
3252          * Gen2 reports pipe underruns whenever all planes are disabled.
3253          * So disable underrun reporting before all the planes get disabled.
3254          */
3255         if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3256                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3257
3258         intel_disable_plane(plane, crtc_state);
3259 }
3260
3261 static struct intel_frontbuffer *
3262 to_intel_frontbuffer(struct drm_framebuffer *fb)
3263 {
3264         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3265 }
3266
3267 static void
3268 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3269                              struct intel_initial_plane_config *plane_config)
3270 {
3271         struct drm_device *dev = intel_crtc->base.dev;
3272         struct drm_i915_private *dev_priv = to_i915(dev);
3273         struct drm_crtc *c;
3274         struct drm_plane *primary = intel_crtc->base.primary;
3275         struct drm_plane_state *plane_state = primary->state;
3276         struct intel_plane *intel_plane = to_intel_plane(primary);
3277         struct intel_plane_state *intel_state =
3278                 to_intel_plane_state(plane_state);
3279         struct drm_framebuffer *fb;
3280
3281         if (!plane_config->fb)
3282                 return;
3283
3284         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3285                 fb = &plane_config->fb->base;
3286                 goto valid_fb;
3287         }
3288
3289         kfree(plane_config->fb);
3290
3291         /*
3292          * Failed to alloc the obj, check to see if we should share
3293          * an fb with another CRTC instead
3294          */
3295         for_each_crtc(dev, c) {
3296                 struct intel_plane_state *state;
3297
3298                 if (c == &intel_crtc->base)
3299                         continue;
3300
3301                 if (!to_intel_crtc(c)->active)
3302                         continue;
3303
3304                 state = to_intel_plane_state(c->primary->state);
3305                 if (!state->vma)
3306                         continue;
3307
3308                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3309                         fb = state->hw.fb;
3310                         drm_framebuffer_get(fb);
3311                         goto valid_fb;
3312                 }
3313         }
3314
3315         /*
3316          * We've failed to reconstruct the BIOS FB.  Current display state
3317          * indicates that the primary plane is visible, but has a NULL FB,
3318          * which will lead to problems later if we don't fix it up.  The
3319          * simplest solution is to just disable the primary plane now and
3320          * pretend the BIOS never had it enabled.
3321          */
3322         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3323
3324         return;
3325
3326 valid_fb:
3327         intel_state->hw.rotation = plane_config->rotation;
3328         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3329                                 intel_state->hw.rotation);
3330         intel_state->color_plane[0].stride =
3331                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3332
3333         intel_state->vma =
3334                 intel_pin_and_fence_fb_obj(fb,
3335                                            &intel_state->view,
3336                                            intel_plane_uses_fence(intel_state),
3337                                            &intel_state->flags);
3338         if (IS_ERR(intel_state->vma)) {
3339                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3340                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
3341
3342                 intel_state->vma = NULL;
3343                 drm_framebuffer_put(fb);
3344                 return;
3345         }
3346
3347         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3348
3349         plane_state->src_x = 0;
3350         plane_state->src_y = 0;
3351         plane_state->src_w = fb->width << 16;
3352         plane_state->src_h = fb->height << 16;
3353
3354         plane_state->crtc_x = 0;
3355         plane_state->crtc_y = 0;
3356         plane_state->crtc_w = fb->width;
3357         plane_state->crtc_h = fb->height;
3358
3359         intel_state->uapi.src = drm_plane_state_src(plane_state);
3360         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3361
3362         if (plane_config->tiling)
3363                 dev_priv->preserve_bios_swizzle = true;
3364
3365         plane_state->fb = fb;
3366         plane_state->crtc = &intel_crtc->base;
3367         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3368
3369         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3370                   &to_intel_frontbuffer(fb)->bits);
3371 }
3372
3373 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3374                                int color_plane,
3375                                unsigned int rotation)
3376 {
3377         int cpp = fb->format->cpp[color_plane];
3378
3379         switch (fb->modifier) {
3380         case DRM_FORMAT_MOD_LINEAR:
3381         case I915_FORMAT_MOD_X_TILED:
3382                 /*
3383                  * Validated limit is 4k, but has 5k should
3384                  * work apart from the following features:
3385                  * - Ytile (already limited to 4k)
3386                  * - FP16 (already limited to 4k)
3387                  * - render compression (already limited to 4k)
3388                  * - KVMR sprite and cursor (don't care)
3389                  * - horizontal panning (TODO verify this)
3390                  * - pipe and plane scaling (TODO verify this)
3391                  */
3392                 if (cpp == 8)
3393                         return 4096;
3394                 else
3395                         return 5120;
3396         case I915_FORMAT_MOD_Y_TILED_CCS:
3397         case I915_FORMAT_MOD_Yf_TILED_CCS:
3398                 /* FIXME AUX plane? */
3399         case I915_FORMAT_MOD_Y_TILED:
3400         case I915_FORMAT_MOD_Yf_TILED:
3401                 if (cpp == 8)
3402                         return 2048;
3403                 else
3404                         return 4096;
3405         default:
3406                 MISSING_CASE(fb->modifier);
3407                 return 2048;
3408         }
3409 }
3410
3411 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3412                                int color_plane,
3413                                unsigned int rotation)
3414 {
3415         int cpp = fb->format->cpp[color_plane];
3416
3417         switch (fb->modifier) {
3418         case DRM_FORMAT_MOD_LINEAR:
3419         case I915_FORMAT_MOD_X_TILED:
3420                 if (cpp == 8)
3421                         return 4096;
3422                 else
3423                         return 5120;
3424         case I915_FORMAT_MOD_Y_TILED_CCS:
3425         case I915_FORMAT_MOD_Yf_TILED_CCS:
3426                 /* FIXME AUX plane? */
3427         case I915_FORMAT_MOD_Y_TILED:
3428         case I915_FORMAT_MOD_Yf_TILED:
3429                 if (cpp == 8)
3430                         return 2048;
3431                 else
3432                         return 5120;
3433         default:
3434                 MISSING_CASE(fb->modifier);
3435                 return 2048;
3436         }
3437 }
3438
3439 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3440                                int color_plane,
3441                                unsigned int rotation)
3442 {
3443         return 5120;
3444 }
3445
3446 static int skl_max_plane_height(void)
3447 {
3448         return 4096;
3449 }
3450
3451 static int icl_max_plane_height(void)
3452 {
3453         return 4320;
3454 }
3455
3456 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3457                                            int main_x, int main_y, u32 main_offset)
3458 {
3459         const struct drm_framebuffer *fb = plane_state->hw.fb;
3460         int hsub = fb->format->hsub;
3461         int vsub = fb->format->vsub;
3462         int aux_x = plane_state->color_plane[1].x;
3463         int aux_y = plane_state->color_plane[1].y;
3464         u32 aux_offset = plane_state->color_plane[1].offset;
3465         u32 alignment = intel_surf_alignment(fb, 1);
3466
3467         while (aux_offset >= main_offset && aux_y <= main_y) {
3468                 int x, y;
3469
3470                 if (aux_x == main_x && aux_y == main_y)
3471                         break;
3472
3473                 if (aux_offset == 0)
3474                         break;
3475
3476                 x = aux_x / hsub;
3477                 y = aux_y / vsub;
3478                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3479                                                                aux_offset, aux_offset - alignment);
3480                 aux_x = x * hsub + aux_x % hsub;
3481                 aux_y = y * vsub + aux_y % vsub;
3482         }
3483
3484         if (aux_x != main_x || aux_y != main_y)
3485                 return false;
3486
3487         plane_state->color_plane[1].offset = aux_offset;
3488         plane_state->color_plane[1].x = aux_x;
3489         plane_state->color_plane[1].y = aux_y;
3490
3491         return true;
3492 }
3493
3494 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3495 {
3496         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3497         const struct drm_framebuffer *fb = plane_state->hw.fb;
3498         unsigned int rotation = plane_state->hw.rotation;
3499         int x = plane_state->uapi.src.x1 >> 16;
3500         int y = plane_state->uapi.src.y1 >> 16;
3501         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3502         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3503         int max_width;
3504         int max_height;
3505         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3506
3507         if (INTEL_GEN(dev_priv) >= 11)
3508                 max_width = icl_max_plane_width(fb, 0, rotation);
3509         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3510                 max_width = glk_max_plane_width(fb, 0, rotation);
3511         else
3512                 max_width = skl_max_plane_width(fb, 0, rotation);
3513
3514         if (INTEL_GEN(dev_priv) >= 11)
3515                 max_height = icl_max_plane_height();
3516         else
3517                 max_height = skl_max_plane_height();
3518
3519         if (w > max_width || h > max_height) {
3520                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3521                               w, h, max_width, max_height);
3522                 return -EINVAL;
3523         }
3524
3525         intel_add_fb_offsets(&x, &y, plane_state, 0);
3526         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3527         alignment = intel_surf_alignment(fb, 0);
3528
3529         /*
3530          * AUX surface offset is specified as the distance from the
3531          * main surface offset, and it must be non-negative. Make
3532          * sure that is what we will get.
3533          */
3534         if (offset > aux_offset)
3535                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3536                                                            offset, aux_offset & ~(alignment - 1));
3537
3538         /*
3539          * When using an X-tiled surface, the plane blows up
3540          * if the x offset + width exceed the stride.
3541          *
3542          * TODO: linear and Y-tiled seem fine, Yf untested,
3543          */
3544         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3545                 int cpp = fb->format->cpp[0];
3546
3547                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3548                         if (offset == 0) {
3549                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3550                                 return -EINVAL;
3551                         }
3552
3553                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3554                                                                    offset, offset - alignment);
3555                 }
3556         }
3557
3558         /*
3559          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3560          * they match with the main surface x/y offsets.
3561          */
3562         if (is_ccs_modifier(fb->modifier)) {
3563                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3564                         if (offset == 0)
3565                                 break;
3566
3567                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3568                                                                    offset, offset - alignment);
3569                 }
3570
3571                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3572                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3573                         return -EINVAL;
3574                 }
3575         }
3576
3577         plane_state->color_plane[0].offset = offset;
3578         plane_state->color_plane[0].x = x;
3579         plane_state->color_plane[0].y = y;
3580
3581         /*
3582          * Put the final coordinates back so that the src
3583          * coordinate checks will see the right values.
3584          */
3585         drm_rect_translate_to(&plane_state->uapi.src,
3586                               x << 16, y << 16);
3587
3588         return 0;
3589 }
3590
3591 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3592 {
3593         const struct drm_framebuffer *fb = plane_state->hw.fb;
3594         unsigned int rotation = plane_state->hw.rotation;
3595         int max_width = skl_max_plane_width(fb, 1, rotation);
3596         int max_height = 4096;
3597         int x = plane_state->uapi.src.x1 >> 17;
3598         int y = plane_state->uapi.src.y1 >> 17;
3599         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3600         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3601         u32 offset;
3602
3603         intel_add_fb_offsets(&x, &y, plane_state, 1);
3604         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3605
3606         /* FIXME not quite sure how/if these apply to the chroma plane */
3607         if (w > max_width || h > max_height) {
3608                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3609                               w, h, max_width, max_height);
3610                 return -EINVAL;
3611         }
3612
3613         plane_state->color_plane[1].offset = offset;
3614         plane_state->color_plane[1].x = x;
3615         plane_state->color_plane[1].y = y;
3616
3617         return 0;
3618 }
3619
3620 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3621 {
3622         const struct drm_framebuffer *fb = plane_state->hw.fb;
3623         int src_x = plane_state->uapi.src.x1 >> 16;
3624         int src_y = plane_state->uapi.src.y1 >> 16;
3625         int hsub = fb->format->hsub;
3626         int vsub = fb->format->vsub;
3627         int x = src_x / hsub;
3628         int y = src_y / vsub;
3629         u32 offset;
3630
3631         intel_add_fb_offsets(&x, &y, plane_state, 1);
3632         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3633
3634         plane_state->color_plane[1].offset = offset;
3635         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3636         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3637
3638         return 0;
3639 }
3640
3641 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3642 {
3643         const struct drm_framebuffer *fb = plane_state->hw.fb;
3644         int ret;
3645
3646         ret = intel_plane_compute_gtt(plane_state);
3647         if (ret)
3648                 return ret;
3649
3650         if (!plane_state->uapi.visible)
3651                 return 0;
3652
3653         /*
3654          * Handle the AUX surface first since
3655          * the main surface setup depends on it.
3656          */
3657         if (drm_format_info_is_yuv_semiplanar(fb->format)) {
3658                 ret = skl_check_nv12_aux_surface(plane_state);
3659                 if (ret)
3660                         return ret;
3661         } else if (is_ccs_modifier(fb->modifier)) {
3662                 ret = skl_check_ccs_aux_surface(plane_state);
3663                 if (ret)
3664                         return ret;
3665         } else {
3666                 plane_state->color_plane[1].offset = ~0xfff;
3667                 plane_state->color_plane[1].x = 0;
3668                 plane_state->color_plane[1].y = 0;
3669         }
3670
3671         ret = skl_check_main_surface(plane_state);
3672         if (ret)
3673                 return ret;
3674
3675         return 0;
3676 }
3677
3678 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
3679                              const struct intel_plane_state *plane_state,
3680                              unsigned int *num, unsigned int *den)
3681 {
3682         const struct drm_framebuffer *fb = plane_state->hw.fb;
3683         unsigned int cpp = fb->format->cpp[0];
3684
3685         /*
3686          * g4x bspec says 64bpp pixel rate can't exceed 80%
3687          * of cdclk when the sprite plane is enabled on the
3688          * same pipe. ilk/snb bspec says 64bpp pixel rate is
3689          * never allowed to exceed 80% of cdclk. Let's just go
3690          * with the ilk/snb limit always.
3691          */
3692         if (cpp == 8) {
3693                 *num = 10;
3694                 *den = 8;
3695         } else {
3696                 *num = 1;
3697                 *den = 1;
3698         }
3699 }
3700
3701 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
3702                                 const struct intel_plane_state *plane_state)
3703 {
3704         unsigned int pixel_rate;
3705         unsigned int num, den;
3706
3707         /*
3708          * Note that crtc_state->pixel_rate accounts for both
3709          * horizontal and vertical panel fitter downscaling factors.
3710          * Pre-HSW bspec tells us to only consider the horizontal
3711          * downscaling factor here. We ignore that and just consider
3712          * both for simplicity.
3713          */
3714         pixel_rate = crtc_state->pixel_rate;
3715
3716         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
3717
3718         /* two pixels per clock with double wide pipe */
3719         if (crtc_state->double_wide)
3720                 den *= 2;
3721
3722         return DIV_ROUND_UP(pixel_rate * num, den);
3723 }
3724
3725 unsigned int
3726 i9xx_plane_max_stride(struct intel_plane *plane,
3727                       u32 pixel_format, u64 modifier,
3728                       unsigned int rotation)
3729 {
3730         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3731
3732         if (!HAS_GMCH(dev_priv)) {
3733                 return 32*1024;
3734         } else if (INTEL_GEN(dev_priv) >= 4) {
3735                 if (modifier == I915_FORMAT_MOD_X_TILED)
3736                         return 16*1024;
3737                 else
3738                         return 32*1024;
3739         } else if (INTEL_GEN(dev_priv) >= 3) {
3740                 if (modifier == I915_FORMAT_MOD_X_TILED)
3741                         return 8*1024;
3742                 else
3743                         return 16*1024;
3744         } else {
3745                 if (plane->i9xx_plane == PLANE_C)
3746                         return 4*1024;
3747                 else
3748                         return 8*1024;
3749         }
3750 }
3751
3752 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3753 {
3754         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3755         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3756         u32 dspcntr = 0;
3757
3758         if (crtc_state->gamma_enable)
3759                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3760
3761         if (crtc_state->csc_enable)
3762                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3763
3764         if (INTEL_GEN(dev_priv) < 5)
3765                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3766
3767         return dspcntr;
3768 }
3769
3770 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3771                           const struct intel_plane_state *plane_state)
3772 {
3773         struct drm_i915_private *dev_priv =
3774                 to_i915(plane_state->uapi.plane->dev);
3775         const struct drm_framebuffer *fb = plane_state->hw.fb;
3776         unsigned int rotation = plane_state->hw.rotation;
3777         u32 dspcntr;
3778
3779         dspcntr = DISPLAY_PLANE_ENABLE;
3780
3781         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3782             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3783                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3784
3785         switch (fb->format->format) {
3786         case DRM_FORMAT_C8:
3787                 dspcntr |= DISPPLANE_8BPP;
3788                 break;
3789         case DRM_FORMAT_XRGB1555:
3790                 dspcntr |= DISPPLANE_BGRX555;
3791                 break;
3792         case DRM_FORMAT_ARGB1555:
3793                 dspcntr |= DISPPLANE_BGRA555;
3794                 break;
3795         case DRM_FORMAT_RGB565:
3796                 dspcntr |= DISPPLANE_BGRX565;
3797                 break;
3798         case DRM_FORMAT_XRGB8888:
3799                 dspcntr |= DISPPLANE_BGRX888;
3800                 break;
3801         case DRM_FORMAT_XBGR8888:
3802                 dspcntr |= DISPPLANE_RGBX888;
3803                 break;
3804         case DRM_FORMAT_ARGB8888:
3805                 dspcntr |= DISPPLANE_BGRA888;
3806                 break;
3807         case DRM_FORMAT_ABGR8888:
3808                 dspcntr |= DISPPLANE_RGBA888;
3809                 break;
3810         case DRM_FORMAT_XRGB2101010:
3811                 dspcntr |= DISPPLANE_BGRX101010;
3812                 break;
3813         case DRM_FORMAT_XBGR2101010:
3814                 dspcntr |= DISPPLANE_RGBX101010;
3815                 break;
3816         case DRM_FORMAT_ARGB2101010:
3817                 dspcntr |= DISPPLANE_BGRA101010;
3818                 break;
3819         case DRM_FORMAT_ABGR2101010:
3820                 dspcntr |= DISPPLANE_RGBA101010;
3821                 break;
3822         case DRM_FORMAT_XBGR16161616F:
3823                 dspcntr |= DISPPLANE_RGBX161616;
3824                 break;
3825         default:
3826                 MISSING_CASE(fb->format->format);
3827                 return 0;
3828         }
3829
3830         if (INTEL_GEN(dev_priv) >= 4 &&
3831             fb->modifier == I915_FORMAT_MOD_X_TILED)
3832                 dspcntr |= DISPPLANE_TILED;
3833
3834         if (rotation & DRM_MODE_ROTATE_180)
3835                 dspcntr |= DISPPLANE_ROTATE_180;
3836
3837         if (rotation & DRM_MODE_REFLECT_X)
3838                 dspcntr |= DISPPLANE_MIRROR;
3839
3840         return dspcntr;
3841 }
3842
3843 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3844 {
3845         struct drm_i915_private *dev_priv =
3846                 to_i915(plane_state->uapi.plane->dev);
3847         const struct drm_framebuffer *fb = plane_state->hw.fb;
3848         int src_x, src_y, src_w;
3849         u32 offset;
3850         int ret;
3851
3852         ret = intel_plane_compute_gtt(plane_state);
3853         if (ret)
3854                 return ret;
3855
3856         if (!plane_state->uapi.visible)
3857                 return 0;
3858
3859         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3860         src_x = plane_state->uapi.src.x1 >> 16;
3861         src_y = plane_state->uapi.src.y1 >> 16;
3862
3863         /* Undocumented hardware limit on i965/g4x/vlv/chv */
3864         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
3865                 return -EINVAL;
3866
3867         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3868
3869         if (INTEL_GEN(dev_priv) >= 4)
3870                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3871                                                             plane_state, 0);
3872         else
3873                 offset = 0;
3874
3875         /*
3876          * Put the final coordinates back so that the src
3877          * coordinate checks will see the right values.
3878          */
3879         drm_rect_translate_to(&plane_state->uapi.src,
3880                               src_x << 16, src_y << 16);
3881
3882         /* HSW/BDW do this automagically in hardware */
3883         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3884                 unsigned int rotation = plane_state->hw.rotation;
3885                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3886                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3887
3888                 if (rotation & DRM_MODE_ROTATE_180) {
3889                         src_x += src_w - 1;
3890                         src_y += src_h - 1;
3891                 } else if (rotation & DRM_MODE_REFLECT_X) {
3892                         src_x += src_w - 1;
3893                 }
3894         }
3895
3896         plane_state->color_plane[0].offset = offset;
3897         plane_state->color_plane[0].x = src_x;
3898         plane_state->color_plane[0].y = src_y;
3899
3900         return 0;
3901 }
3902
3903 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3904 {
3905         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3906         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3907
3908         if (IS_CHERRYVIEW(dev_priv))
3909                 return i9xx_plane == PLANE_B;
3910         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3911                 return false;
3912         else if (IS_GEN(dev_priv, 4))
3913                 return i9xx_plane == PLANE_C;
3914         else
3915                 return i9xx_plane == PLANE_B ||
3916                         i9xx_plane == PLANE_C;
3917 }
3918
3919 static int
3920 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3921                  struct intel_plane_state *plane_state)
3922 {
3923         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3924         int ret;
3925
3926         ret = chv_plane_check_rotation(plane_state);
3927         if (ret)
3928                 return ret;
3929
3930         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
3931                                                   &crtc_state->uapi,
3932                                                   DRM_PLANE_HELPER_NO_SCALING,
3933                                                   DRM_PLANE_HELPER_NO_SCALING,
3934                                                   i9xx_plane_has_windowing(plane),
3935                                                   true);
3936         if (ret)
3937                 return ret;
3938
3939         ret = i9xx_check_plane_surface(plane_state);
3940         if (ret)
3941                 return ret;
3942
3943         if (!plane_state->uapi.visible)
3944                 return 0;
3945
3946         ret = intel_plane_check_src_coordinates(plane_state);
3947         if (ret)
3948                 return ret;
3949
3950         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3951
3952         return 0;
3953 }
3954
3955 static void i9xx_update_plane(struct intel_plane *plane,
3956                               const struct intel_crtc_state *crtc_state,
3957                               const struct intel_plane_state *plane_state)
3958 {
3959         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3960         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3961         u32 linear_offset;
3962         int x = plane_state->color_plane[0].x;
3963         int y = plane_state->color_plane[0].y;
3964         int crtc_x = plane_state->uapi.dst.x1;
3965         int crtc_y = plane_state->uapi.dst.y1;
3966         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
3967         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
3968         unsigned long irqflags;
3969         u32 dspaddr_offset;
3970         u32 dspcntr;
3971
3972         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3973
3974         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3975
3976         if (INTEL_GEN(dev_priv) >= 4)
3977                 dspaddr_offset = plane_state->color_plane[0].offset;
3978         else
3979                 dspaddr_offset = linear_offset;
3980
3981         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3982
3983         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3984
3985         if (INTEL_GEN(dev_priv) < 4) {
3986                 /*
3987                  * PLANE_A doesn't actually have a full window
3988                  * generator but let's assume we still need to
3989                  * program whatever is there.
3990                  */
3991                 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3992                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3993                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3994         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3995                 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3996                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3997                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3998                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3999         }
4000
4001         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4002                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
4003         } else if (INTEL_GEN(dev_priv) >= 4) {
4004                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
4005                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
4006         }
4007
4008         /*
4009          * The control register self-arms if the plane was previously
4010          * disabled. Try to make the plane enable atomic by writing
4011          * the control register just before the surface register.
4012          */
4013         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
4014         if (INTEL_GEN(dev_priv) >= 4)
4015                 I915_WRITE_FW(DSPSURF(i9xx_plane),
4016                               intel_plane_ggtt_offset(plane_state) +
4017                               dspaddr_offset);
4018         else
4019                 I915_WRITE_FW(DSPADDR(i9xx_plane),
4020                               intel_plane_ggtt_offset(plane_state) +
4021                               dspaddr_offset);
4022
4023         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4024 }
4025
4026 static void i9xx_disable_plane(struct intel_plane *plane,
4027                                const struct intel_crtc_state *crtc_state)
4028 {
4029         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4030         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4031         unsigned long irqflags;
4032         u32 dspcntr;
4033
4034         /*
4035          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4036          * enable on ilk+ affect the pipe bottom color as
4037          * well, so we must configure them even if the plane
4038          * is disabled.
4039          *
4040          * On pre-g4x there is no way to gamma correct the
4041          * pipe bottom color but we'll keep on doing this
4042          * anyway so that the crtc state readout works correctly.
4043          */
4044         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4045
4046         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4047
4048         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
4049         if (INTEL_GEN(dev_priv) >= 4)
4050                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
4051         else
4052                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
4053
4054         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4055 }
4056
4057 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4058                                     enum pipe *pipe)
4059 {
4060         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4061         enum intel_display_power_domain power_domain;
4062         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4063         intel_wakeref_t wakeref;
4064         bool ret;
4065         u32 val;
4066
4067         /*
4068          * Not 100% correct for planes that can move between pipes,
4069          * but that's only the case for gen2-4 which don't have any
4070          * display power wells.
4071          */
4072         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4073         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4074         if (!wakeref)
4075                 return false;
4076
4077         val = I915_READ(DSPCNTR(i9xx_plane));
4078
4079         ret = val & DISPLAY_PLANE_ENABLE;
4080
4081         if (INTEL_GEN(dev_priv) >= 5)
4082                 *pipe = plane->pipe;
4083         else
4084                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4085                         DISPPLANE_SEL_PIPE_SHIFT;
4086
4087         intel_display_power_put(dev_priv, power_domain, wakeref);
4088
4089         return ret;
4090 }
4091
4092 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4093 {
4094         struct drm_device *dev = intel_crtc->base.dev;
4095         struct drm_i915_private *dev_priv = to_i915(dev);
4096
4097         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4098         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4099         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4100 }
4101
4102 /*
4103  * This function detaches (aka. unbinds) unused scalers in hardware
4104  */
4105 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4106 {
4107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4108         const struct intel_crtc_scaler_state *scaler_state =
4109                 &crtc_state->scaler_state;
4110         int i;
4111
4112         /* loop through and disable scalers that aren't in use */
4113         for (i = 0; i < intel_crtc->num_scalers; i++) {
4114                 if (!scaler_state->scalers[i].in_use)
4115                         skl_detach_scaler(intel_crtc, i);
4116         }
4117 }
4118
4119 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4120                                           int color_plane, unsigned int rotation)
4121 {
4122         /*
4123          * The stride is either expressed as a multiple of 64 bytes chunks for
4124          * linear buffers or in number of tiles for tiled buffers.
4125          */
4126         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
4127                 return 64;
4128         else if (drm_rotation_90_or_270(rotation))
4129                 return intel_tile_height(fb, color_plane);
4130         else
4131                 return intel_tile_width_bytes(fb, color_plane);
4132 }
4133
4134 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4135                      int color_plane)
4136 {
4137         const struct drm_framebuffer *fb = plane_state->hw.fb;
4138         unsigned int rotation = plane_state->hw.rotation;
4139         u32 stride = plane_state->color_plane[color_plane].stride;
4140
4141         if (color_plane >= fb->format->num_planes)
4142                 return 0;
4143
4144         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4145 }
4146
4147 static u32 skl_plane_ctl_format(u32 pixel_format)
4148 {
4149         switch (pixel_format) {
4150         case DRM_FORMAT_C8:
4151                 return PLANE_CTL_FORMAT_INDEXED;
4152         case DRM_FORMAT_RGB565:
4153                 return PLANE_CTL_FORMAT_RGB_565;
4154         case DRM_FORMAT_XBGR8888:
4155         case DRM_FORMAT_ABGR8888:
4156                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4157         case DRM_FORMAT_XRGB8888:
4158         case DRM_FORMAT_ARGB8888:
4159                 return PLANE_CTL_FORMAT_XRGB_8888;
4160         case DRM_FORMAT_XBGR2101010:
4161         case DRM_FORMAT_ABGR2101010:
4162                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4163         case DRM_FORMAT_XRGB2101010:
4164         case DRM_FORMAT_ARGB2101010:
4165                 return PLANE_CTL_FORMAT_XRGB_2101010;
4166         case DRM_FORMAT_XBGR16161616F:
4167         case DRM_FORMAT_ABGR16161616F:
4168                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4169         case DRM_FORMAT_XRGB16161616F:
4170         case DRM_FORMAT_ARGB16161616F:
4171                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4172         case DRM_FORMAT_YUYV:
4173                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4174         case DRM_FORMAT_YVYU:
4175                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4176         case DRM_FORMAT_UYVY:
4177                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4178         case DRM_FORMAT_VYUY:
4179                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4180         case DRM_FORMAT_NV12:
4181                 return PLANE_CTL_FORMAT_NV12;
4182         case DRM_FORMAT_P010:
4183                 return PLANE_CTL_FORMAT_P010;
4184         case DRM_FORMAT_P012:
4185                 return PLANE_CTL_FORMAT_P012;
4186         case DRM_FORMAT_P016:
4187                 return PLANE_CTL_FORMAT_P016;
4188         case DRM_FORMAT_Y210:
4189                 return PLANE_CTL_FORMAT_Y210;
4190         case DRM_FORMAT_Y212:
4191                 return PLANE_CTL_FORMAT_Y212;
4192         case DRM_FORMAT_Y216:
4193                 return PLANE_CTL_FORMAT_Y216;
4194         case DRM_FORMAT_XVYU2101010:
4195                 return PLANE_CTL_FORMAT_Y410;
4196         case DRM_FORMAT_XVYU12_16161616:
4197                 return PLANE_CTL_FORMAT_Y412;
4198         case DRM_FORMAT_XVYU16161616:
4199                 return PLANE_CTL_FORMAT_Y416;
4200         default:
4201                 MISSING_CASE(pixel_format);
4202         }
4203
4204         return 0;
4205 }
4206
4207 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4208 {
4209         if (!plane_state->hw.fb->format->has_alpha)
4210                 return PLANE_CTL_ALPHA_DISABLE;
4211
4212         switch (plane_state->hw.pixel_blend_mode) {
4213         case DRM_MODE_BLEND_PIXEL_NONE:
4214                 return PLANE_CTL_ALPHA_DISABLE;
4215         case DRM_MODE_BLEND_PREMULTI:
4216                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4217         case DRM_MODE_BLEND_COVERAGE:
4218                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4219         default:
4220                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4221                 return PLANE_CTL_ALPHA_DISABLE;
4222         }
4223 }
4224
4225 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4226 {
4227         if (!plane_state->hw.fb->format->has_alpha)
4228                 return PLANE_COLOR_ALPHA_DISABLE;
4229
4230         switch (plane_state->hw.pixel_blend_mode) {
4231         case DRM_MODE_BLEND_PIXEL_NONE:
4232                 return PLANE_COLOR_ALPHA_DISABLE;
4233         case DRM_MODE_BLEND_PREMULTI:
4234                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4235         case DRM_MODE_BLEND_COVERAGE:
4236                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4237         default:
4238                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4239                 return PLANE_COLOR_ALPHA_DISABLE;
4240         }
4241 }
4242
4243 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4244 {
4245         switch (fb_modifier) {
4246         case DRM_FORMAT_MOD_LINEAR:
4247                 break;
4248         case I915_FORMAT_MOD_X_TILED:
4249                 return PLANE_CTL_TILED_X;
4250         case I915_FORMAT_MOD_Y_TILED:
4251                 return PLANE_CTL_TILED_Y;
4252         case I915_FORMAT_MOD_Y_TILED_CCS:
4253                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4254         case I915_FORMAT_MOD_Yf_TILED:
4255                 return PLANE_CTL_TILED_YF;
4256         case I915_FORMAT_MOD_Yf_TILED_CCS:
4257                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4258         default:
4259                 MISSING_CASE(fb_modifier);
4260         }
4261
4262         return 0;
4263 }
4264
4265 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4266 {
4267         switch (rotate) {
4268         case DRM_MODE_ROTATE_0:
4269                 break;
4270         /*
4271          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4272          * while i915 HW rotation is clockwise, thats why this swapping.
4273          */
4274         case DRM_MODE_ROTATE_90:
4275                 return PLANE_CTL_ROTATE_270;
4276         case DRM_MODE_ROTATE_180:
4277                 return PLANE_CTL_ROTATE_180;
4278         case DRM_MODE_ROTATE_270:
4279                 return PLANE_CTL_ROTATE_90;
4280         default:
4281                 MISSING_CASE(rotate);
4282         }
4283
4284         return 0;
4285 }
4286
4287 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4288 {
4289         switch (reflect) {
4290         case 0:
4291                 break;
4292         case DRM_MODE_REFLECT_X:
4293                 return PLANE_CTL_FLIP_HORIZONTAL;
4294         case DRM_MODE_REFLECT_Y:
4295         default:
4296                 MISSING_CASE(reflect);
4297         }
4298
4299         return 0;
4300 }
4301
4302 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4303 {
4304         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4305         u32 plane_ctl = 0;
4306
4307         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4308                 return plane_ctl;
4309
4310         if (crtc_state->gamma_enable)
4311                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4312
4313         if (crtc_state->csc_enable)
4314                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4315
4316         return plane_ctl;
4317 }
4318
4319 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4320                   const struct intel_plane_state *plane_state)
4321 {
4322         struct drm_i915_private *dev_priv =
4323                 to_i915(plane_state->uapi.plane->dev);
4324         const struct drm_framebuffer *fb = plane_state->hw.fb;
4325         unsigned int rotation = plane_state->hw.rotation;
4326         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4327         u32 plane_ctl;
4328
4329         plane_ctl = PLANE_CTL_ENABLE;
4330
4331         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4332                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4333                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4334
4335                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4336                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4337
4338                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4339                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4340         }
4341
4342         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4343         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4344         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4345
4346         if (INTEL_GEN(dev_priv) >= 10)
4347                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4348                                                 DRM_MODE_REFLECT_MASK);
4349
4350         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4351                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4352         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4353                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4354
4355         return plane_ctl;
4356 }
4357
4358 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4359 {
4360         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4361         u32 plane_color_ctl = 0;
4362
4363         if (INTEL_GEN(dev_priv) >= 11)
4364                 return plane_color_ctl;
4365
4366         if (crtc_state->gamma_enable)
4367                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4368
4369         if (crtc_state->csc_enable)
4370                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4371
4372         return plane_color_ctl;
4373 }
4374
4375 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4376                         const struct intel_plane_state *plane_state)
4377 {
4378         struct drm_i915_private *dev_priv =
4379                 to_i915(plane_state->uapi.plane->dev);
4380         const struct drm_framebuffer *fb = plane_state->hw.fb;
4381         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4382         u32 plane_color_ctl = 0;
4383
4384         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4385         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4386
4387         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4388                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4389                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4390                 else
4391                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4392
4393                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4394                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4395         } else if (fb->format->is_yuv) {
4396                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4397         }
4398
4399         return plane_color_ctl;
4400 }
4401
4402 static int
4403 __intel_display_resume(struct drm_device *dev,
4404                        struct drm_atomic_state *state,
4405                        struct drm_modeset_acquire_ctx *ctx)
4406 {
4407         struct drm_crtc_state *crtc_state;
4408         struct drm_crtc *crtc;
4409         int i, ret;
4410
4411         intel_modeset_setup_hw_state(dev, ctx);
4412         intel_vga_redisable(to_i915(dev));
4413
4414         if (!state)
4415                 return 0;
4416
4417         /*
4418          * We've duplicated the state, pointers to the old state are invalid.
4419          *
4420          * Don't attempt to use the old state until we commit the duplicated state.
4421          */
4422         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4423                 /*
4424                  * Force recalculation even if we restore
4425                  * current state. With fast modeset this may not result
4426                  * in a modeset when the state is compatible.
4427                  */
4428                 crtc_state->mode_changed = true;
4429         }
4430
4431         /* ignore any reset values/BIOS leftovers in the WM registers */
4432         if (!HAS_GMCH(to_i915(dev)))
4433                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4434
4435         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4436
4437         WARN_ON(ret == -EDEADLK);
4438         return ret;
4439 }
4440
4441 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4442 {
4443         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4444                 intel_has_gpu_reset(&dev_priv->gt));
4445 }
4446
4447 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4448 {
4449         struct drm_device *dev = &dev_priv->drm;
4450         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4451         struct drm_atomic_state *state;
4452         int ret;
4453
4454         /* reset doesn't touch the display */
4455         if (!i915_modparams.force_reset_modeset_test &&
4456             !gpu_reset_clobbers_display(dev_priv))
4457                 return;
4458
4459         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4460         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4461         smp_mb__after_atomic();
4462         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4463
4464         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4465                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4466                 intel_gt_set_wedged(&dev_priv->gt);
4467         }
4468
4469         /*
4470          * Need mode_config.mutex so that we don't
4471          * trample ongoing ->detect() and whatnot.
4472          */
4473         mutex_lock(&dev->mode_config.mutex);
4474         drm_modeset_acquire_init(ctx, 0);
4475         while (1) {
4476                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4477                 if (ret != -EDEADLK)
4478                         break;
4479
4480                 drm_modeset_backoff(ctx);
4481         }
4482         /*
4483          * Disabling the crtcs gracefully seems nicer. Also the
4484          * g33 docs say we should at least disable all the planes.
4485          */
4486         state = drm_atomic_helper_duplicate_state(dev, ctx);
4487         if (IS_ERR(state)) {
4488                 ret = PTR_ERR(state);
4489                 DRM_ERROR("Duplicating state failed with %i\n", ret);
4490                 return;
4491         }
4492
4493         ret = drm_atomic_helper_disable_all(dev, ctx);
4494         if (ret) {
4495                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4496                 drm_atomic_state_put(state);
4497                 return;
4498         }
4499
4500         dev_priv->modeset_restore_state = state;
4501         state->acquire_ctx = ctx;
4502 }
4503
4504 void intel_finish_reset(struct drm_i915_private *dev_priv)
4505 {
4506         struct drm_device *dev = &dev_priv->drm;
4507         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4508         struct drm_atomic_state *state;
4509         int ret;
4510
4511         /* reset doesn't touch the display */
4512         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4513                 return;
4514
4515         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4516         if (!state)
4517                 goto unlock;
4518
4519         /* reset doesn't touch the display */
4520         if (!gpu_reset_clobbers_display(dev_priv)) {
4521                 /* for testing only restore the display */
4522                 ret = __intel_display_resume(dev, state, ctx);
4523                 if (ret)
4524                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4525         } else {
4526                 /*
4527                  * The display has been reset as well,
4528                  * so need a full re-initialization.
4529                  */
4530                 intel_pps_unlock_regs_wa(dev_priv);
4531                 intel_modeset_init_hw(dev_priv);
4532                 intel_init_clock_gating(dev_priv);
4533
4534                 spin_lock_irq(&dev_priv->irq_lock);
4535                 if (dev_priv->display.hpd_irq_setup)
4536                         dev_priv->display.hpd_irq_setup(dev_priv);
4537                 spin_unlock_irq(&dev_priv->irq_lock);
4538
4539                 ret = __intel_display_resume(dev, state, ctx);
4540                 if (ret)
4541                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4542
4543                 intel_hpd_init(dev_priv);
4544         }
4545
4546         drm_atomic_state_put(state);
4547 unlock:
4548         drm_modeset_drop_locks(ctx);
4549         drm_modeset_acquire_fini(ctx);
4550         mutex_unlock(&dev->mode_config.mutex);
4551
4552         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4553 }
4554
4555 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4556 {
4557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4558         enum pipe pipe = crtc->pipe;
4559         u32 tmp;
4560
4561         tmp = I915_READ(PIPE_CHICKEN(pipe));
4562
4563         /*
4564          * Display WA #1153: icl
4565          * enable hardware to bypass the alpha math
4566          * and rounding for per-pixel values 00 and 0xff
4567          */
4568         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4569         /*
4570          * Display WA # 1605353570: icl
4571          * Set the pixel rounding bit to 1 for allowing
4572          * passthrough of Frame buffer pixels unmodified
4573          * across pipe
4574          */
4575         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4576         I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4577 }
4578
4579 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
4580 {
4581         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4582         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4583         u32 trans_ddi_func_ctl2_val;
4584         u8 master_select;
4585
4586         /*
4587          * Configure the master select and enable Transcoder Port Sync for
4588          * Slave CRTCs transcoder.
4589          */
4590         if (crtc_state->master_transcoder == INVALID_TRANSCODER)
4591                 return;
4592
4593         if (crtc_state->master_transcoder == TRANSCODER_EDP)
4594                 master_select = 0;
4595         else
4596                 master_select = crtc_state->master_transcoder + 1;
4597
4598         /* Set the master select bits for Tranascoder Port Sync */
4599         trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
4600                                    PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
4601                 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
4602         /* Enable Transcoder Port Sync */
4603         trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
4604
4605         I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
4606                    trans_ddi_func_ctl2_val);
4607 }
4608
4609 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
4610 {
4611         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4612         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4613         i915_reg_t reg;
4614         u32 trans_ddi_func_ctl2_val;
4615
4616         if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
4617                 return;
4618
4619         DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
4620                       transcoder_name(old_crtc_state->cpu_transcoder));
4621
4622         reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
4623         trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
4624                                     PORT_SYNC_MODE_MASTER_SELECT_MASK);
4625         I915_WRITE(reg, trans_ddi_func_ctl2_val);
4626 }
4627
4628 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4629 {
4630         struct drm_device *dev = crtc->base.dev;
4631         struct drm_i915_private *dev_priv = to_i915(dev);
4632         enum pipe pipe = crtc->pipe;
4633         i915_reg_t reg;
4634         u32 temp;
4635
4636         /* enable normal train */
4637         reg = FDI_TX_CTL(pipe);
4638         temp = I915_READ(reg);
4639         if (IS_IVYBRIDGE(dev_priv)) {
4640                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4641                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4642         } else {
4643                 temp &= ~FDI_LINK_TRAIN_NONE;
4644                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4645         }
4646         I915_WRITE(reg, temp);
4647
4648         reg = FDI_RX_CTL(pipe);
4649         temp = I915_READ(reg);
4650         if (HAS_PCH_CPT(dev_priv)) {
4651                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4652                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4653         } else {
4654                 temp &= ~FDI_LINK_TRAIN_NONE;
4655                 temp |= FDI_LINK_TRAIN_NONE;
4656         }
4657         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4658
4659         /* wait one idle pattern time */
4660         POSTING_READ(reg);
4661         udelay(1000);
4662
4663         /* IVB wants error correction enabled */
4664         if (IS_IVYBRIDGE(dev_priv))
4665                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4666                            FDI_FE_ERRC_ENABLE);
4667 }
4668
4669 /* The FDI link training functions for ILK/Ibexpeak. */
4670 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4671                                     const struct intel_crtc_state *crtc_state)
4672 {
4673         struct drm_device *dev = crtc->base.dev;
4674         struct drm_i915_private *dev_priv = to_i915(dev);
4675         enum pipe pipe = crtc->pipe;
4676         i915_reg_t reg;
4677         u32 temp, tries;
4678
4679         /* FDI needs bits from pipe first */
4680         assert_pipe_enabled(dev_priv, pipe);
4681
4682         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4683            for train result */
4684         reg = FDI_RX_IMR(pipe);
4685         temp = I915_READ(reg);
4686         temp &= ~FDI_RX_SYMBOL_LOCK;
4687         temp &= ~FDI_RX_BIT_LOCK;
4688         I915_WRITE(reg, temp);
4689         I915_READ(reg);
4690         udelay(150);
4691
4692         /* enable CPU FDI TX and PCH FDI RX */
4693         reg = FDI_TX_CTL(pipe);
4694         temp = I915_READ(reg);
4695         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4696         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4697         temp &= ~FDI_LINK_TRAIN_NONE;
4698         temp |= FDI_LINK_TRAIN_PATTERN_1;
4699         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4700
4701         reg = FDI_RX_CTL(pipe);
4702         temp = I915_READ(reg);
4703         temp &= ~FDI_LINK_TRAIN_NONE;
4704         temp |= FDI_LINK_TRAIN_PATTERN_1;
4705         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4706
4707         POSTING_READ(reg);
4708         udelay(150);
4709
4710         /* Ironlake workaround, enable clock pointer after FDI enable*/
4711         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4712         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4713                    FDI_RX_PHASE_SYNC_POINTER_EN);
4714
4715         reg = FDI_RX_IIR(pipe);
4716         for (tries = 0; tries < 5; tries++) {
4717                 temp = I915_READ(reg);
4718                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4719
4720                 if ((temp & FDI_RX_BIT_LOCK)) {
4721                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4722                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4723                         break;
4724                 }
4725         }
4726         if (tries == 5)
4727                 DRM_ERROR("FDI train 1 fail!\n");
4728
4729         /* Train 2 */
4730         reg = FDI_TX_CTL(pipe);
4731         temp = I915_READ(reg);
4732         temp &= ~FDI_LINK_TRAIN_NONE;
4733         temp |= FDI_LINK_TRAIN_PATTERN_2;
4734         I915_WRITE(reg, temp);
4735
4736         reg = FDI_RX_CTL(pipe);
4737         temp = I915_READ(reg);
4738         temp &= ~FDI_LINK_TRAIN_NONE;
4739         temp |= FDI_LINK_TRAIN_PATTERN_2;
4740         I915_WRITE(reg, temp);
4741
4742         POSTING_READ(reg);
4743         udelay(150);
4744
4745         reg = FDI_RX_IIR(pipe);
4746         for (tries = 0; tries < 5; tries++) {
4747                 temp = I915_READ(reg);
4748                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4749
4750                 if (temp & FDI_RX_SYMBOL_LOCK) {
4751                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4752                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4753                         break;
4754                 }
4755         }
4756         if (tries == 5)
4757                 DRM_ERROR("FDI train 2 fail!\n");
4758
4759         DRM_DEBUG_KMS("FDI train done\n");
4760
4761 }
4762
4763 static const int snb_b_fdi_train_param[] = {
4764         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4765         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4766         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4767         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4768 };
4769
4770 /* The FDI link training functions for SNB/Cougarpoint. */
4771 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4772                                 const struct intel_crtc_state *crtc_state)
4773 {
4774         struct drm_device *dev = crtc->base.dev;
4775         struct drm_i915_private *dev_priv = to_i915(dev);
4776         enum pipe pipe = crtc->pipe;
4777         i915_reg_t reg;
4778         u32 temp, i, retry;
4779
4780         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4781            for train result */
4782         reg = FDI_RX_IMR(pipe);
4783         temp = I915_READ(reg);
4784         temp &= ~FDI_RX_SYMBOL_LOCK;
4785         temp &= ~FDI_RX_BIT_LOCK;
4786         I915_WRITE(reg, temp);
4787
4788         POSTING_READ(reg);
4789         udelay(150);
4790
4791         /* enable CPU FDI TX and PCH FDI RX */
4792         reg = FDI_TX_CTL(pipe);
4793         temp = I915_READ(reg);
4794         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4795         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4796         temp &= ~FDI_LINK_TRAIN_NONE;
4797         temp |= FDI_LINK_TRAIN_PATTERN_1;
4798         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4799         /* SNB-B */
4800         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4801         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4802
4803         I915_WRITE(FDI_RX_MISC(pipe),
4804                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4805
4806         reg = FDI_RX_CTL(pipe);
4807         temp = I915_READ(reg);
4808         if (HAS_PCH_CPT(dev_priv)) {
4809                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4810                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4811         } else {
4812                 temp &= ~FDI_LINK_TRAIN_NONE;
4813                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4814         }
4815         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4816
4817         POSTING_READ(reg);
4818         udelay(150);
4819
4820         for (i = 0; i < 4; i++) {
4821                 reg = FDI_TX_CTL(pipe);
4822                 temp = I915_READ(reg);
4823                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4824                 temp |= snb_b_fdi_train_param[i];
4825                 I915_WRITE(reg, temp);
4826
4827                 POSTING_READ(reg);
4828                 udelay(500);
4829
4830                 for (retry = 0; retry < 5; retry++) {
4831                         reg = FDI_RX_IIR(pipe);
4832                         temp = I915_READ(reg);
4833                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4834                         if (temp & FDI_RX_BIT_LOCK) {
4835                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4836                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4837                                 break;
4838                         }
4839                         udelay(50);
4840                 }
4841                 if (retry < 5)
4842                         break;
4843         }
4844         if (i == 4)
4845                 DRM_ERROR("FDI train 1 fail!\n");
4846
4847         /* Train 2 */
4848         reg = FDI_TX_CTL(pipe);
4849         temp = I915_READ(reg);
4850         temp &= ~FDI_LINK_TRAIN_NONE;
4851         temp |= FDI_LINK_TRAIN_PATTERN_2;
4852         if (IS_GEN(dev_priv, 6)) {
4853                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4854                 /* SNB-B */
4855                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4856         }
4857         I915_WRITE(reg, temp);
4858
4859         reg = FDI_RX_CTL(pipe);
4860         temp = I915_READ(reg);
4861         if (HAS_PCH_CPT(dev_priv)) {
4862                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4863                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4864         } else {
4865                 temp &= ~FDI_LINK_TRAIN_NONE;
4866                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4867         }
4868         I915_WRITE(reg, temp);
4869
4870         POSTING_READ(reg);
4871         udelay(150);
4872
4873         for (i = 0; i < 4; i++) {
4874                 reg = FDI_TX_CTL(pipe);
4875                 temp = I915_READ(reg);
4876                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4877                 temp |= snb_b_fdi_train_param[i];
4878                 I915_WRITE(reg, temp);
4879
4880                 POSTING_READ(reg);
4881                 udelay(500);
4882
4883                 for (retry = 0; retry < 5; retry++) {
4884                         reg = FDI_RX_IIR(pipe);
4885                         temp = I915_READ(reg);
4886                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4887                         if (temp & FDI_RX_SYMBOL_LOCK) {
4888                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4889                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4890                                 break;
4891                         }
4892                         udelay(50);
4893                 }
4894                 if (retry < 5)
4895                         break;
4896         }
4897         if (i == 4)
4898                 DRM_ERROR("FDI train 2 fail!\n");
4899
4900         DRM_DEBUG_KMS("FDI train done.\n");
4901 }
4902
4903 /* Manual link training for Ivy Bridge A0 parts */
4904 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4905                                       const struct intel_crtc_state *crtc_state)
4906 {
4907         struct drm_device *dev = crtc->base.dev;
4908         struct drm_i915_private *dev_priv = to_i915(dev);
4909         enum pipe pipe = crtc->pipe;
4910         i915_reg_t reg;
4911         u32 temp, i, j;
4912
4913         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4914            for train result */
4915         reg = FDI_RX_IMR(pipe);
4916         temp = I915_READ(reg);
4917         temp &= ~FDI_RX_SYMBOL_LOCK;
4918         temp &= ~FDI_RX_BIT_LOCK;
4919         I915_WRITE(reg, temp);
4920
4921         POSTING_READ(reg);
4922         udelay(150);
4923
4924         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4925                       I915_READ(FDI_RX_IIR(pipe)));
4926
4927         /* Try each vswing and preemphasis setting twice before moving on */
4928         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4929                 /* disable first in case we need to retry */
4930                 reg = FDI_TX_CTL(pipe);
4931                 temp = I915_READ(reg);
4932                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4933                 temp &= ~FDI_TX_ENABLE;
4934                 I915_WRITE(reg, temp);
4935
4936                 reg = FDI_RX_CTL(pipe);
4937                 temp = I915_READ(reg);
4938                 temp &= ~FDI_LINK_TRAIN_AUTO;
4939                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4940                 temp &= ~FDI_RX_ENABLE;
4941                 I915_WRITE(reg, temp);
4942
4943                 /* enable CPU FDI TX and PCH FDI RX */
4944                 reg = FDI_TX_CTL(pipe);
4945                 temp = I915_READ(reg);
4946                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4947                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4948                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4949                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4950                 temp |= snb_b_fdi_train_param[j/2];
4951                 temp |= FDI_COMPOSITE_SYNC;
4952                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4953
4954                 I915_WRITE(FDI_RX_MISC(pipe),
4955                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4956
4957                 reg = FDI_RX_CTL(pipe);
4958                 temp = I915_READ(reg);
4959                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4960                 temp |= FDI_COMPOSITE_SYNC;
4961                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4962
4963                 POSTING_READ(reg);
4964                 udelay(1); /* should be 0.5us */
4965
4966                 for (i = 0; i < 4; i++) {
4967                         reg = FDI_RX_IIR(pipe);
4968                         temp = I915_READ(reg);
4969                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4970
4971                         if (temp & FDI_RX_BIT_LOCK ||
4972                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4973                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4974                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4975                                               i);
4976                                 break;
4977                         }
4978                         udelay(1); /* should be 0.5us */
4979                 }
4980                 if (i == 4) {
4981                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4982                         continue;
4983                 }
4984
4985                 /* Train 2 */
4986                 reg = FDI_TX_CTL(pipe);
4987                 temp = I915_READ(reg);
4988                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4989                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4990                 I915_WRITE(reg, temp);
4991
4992                 reg = FDI_RX_CTL(pipe);
4993                 temp = I915_READ(reg);
4994                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4995                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4996                 I915_WRITE(reg, temp);
4997
4998                 POSTING_READ(reg);
4999                 udelay(2); /* should be 1.5us */
5000
5001                 for (i = 0; i < 4; i++) {
5002                         reg = FDI_RX_IIR(pipe);
5003                         temp = I915_READ(reg);
5004                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
5005
5006                         if (temp & FDI_RX_SYMBOL_LOCK ||
5007                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
5008                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
5009                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
5010                                               i);
5011                                 goto train_done;
5012                         }
5013                         udelay(2); /* should be 1.5us */
5014                 }
5015                 if (i == 4)
5016                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
5017         }
5018
5019 train_done:
5020         DRM_DEBUG_KMS("FDI train done.\n");
5021 }
5022
5023 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5024 {
5025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5026         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5027         enum pipe pipe = intel_crtc->pipe;
5028         i915_reg_t reg;
5029         u32 temp;
5030
5031         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5032         reg = FDI_RX_CTL(pipe);
5033         temp = I915_READ(reg);
5034         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5035         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5036         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5037         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
5038
5039         POSTING_READ(reg);
5040         udelay(200);
5041
5042         /* Switch from Rawclk to PCDclk */
5043         temp = I915_READ(reg);
5044         I915_WRITE(reg, temp | FDI_PCDCLK);
5045
5046         POSTING_READ(reg);
5047         udelay(200);
5048
5049         /* Enable CPU FDI TX PLL, always on for Ironlake */
5050         reg = FDI_TX_CTL(pipe);
5051         temp = I915_READ(reg);
5052         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5053                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5054
5055                 POSTING_READ(reg);
5056                 udelay(100);
5057         }
5058 }
5059
5060 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
5061 {
5062         struct drm_device *dev = intel_crtc->base.dev;
5063         struct drm_i915_private *dev_priv = to_i915(dev);
5064         enum pipe pipe = intel_crtc->pipe;
5065         i915_reg_t reg;
5066         u32 temp;
5067
5068         /* Switch from PCDclk to Rawclk */
5069         reg = FDI_RX_CTL(pipe);
5070         temp = I915_READ(reg);
5071         I915_WRITE(reg, temp & ~FDI_PCDCLK);
5072
5073         /* Disable CPU FDI TX PLL */
5074         reg = FDI_TX_CTL(pipe);
5075         temp = I915_READ(reg);
5076         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
5077
5078         POSTING_READ(reg);
5079         udelay(100);
5080
5081         reg = FDI_RX_CTL(pipe);
5082         temp = I915_READ(reg);
5083         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
5084
5085         /* Wait for the clocks to turn off. */
5086         POSTING_READ(reg);
5087         udelay(100);
5088 }
5089
5090 static void ironlake_fdi_disable(struct intel_crtc *crtc)
5091 {
5092         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5093         enum pipe pipe = crtc->pipe;
5094         i915_reg_t reg;
5095         u32 temp;
5096
5097         /* disable CPU FDI tx and PCH FDI rx */
5098         reg = FDI_TX_CTL(pipe);
5099         temp = I915_READ(reg);
5100         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
5101         POSTING_READ(reg);
5102
5103         reg = FDI_RX_CTL(pipe);
5104         temp = I915_READ(reg);
5105         temp &= ~(0x7 << 16);
5106         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5107         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
5108
5109         POSTING_READ(reg);
5110         udelay(100);
5111
5112         /* Ironlake workaround, disable clock pointer after downing FDI */
5113         if (HAS_PCH_IBX(dev_priv))
5114                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
5115
5116         /* still set train pattern 1 */
5117         reg = FDI_TX_CTL(pipe);
5118         temp = I915_READ(reg);
5119         temp &= ~FDI_LINK_TRAIN_NONE;
5120         temp |= FDI_LINK_TRAIN_PATTERN_1;
5121         I915_WRITE(reg, temp);
5122
5123         reg = FDI_RX_CTL(pipe);
5124         temp = I915_READ(reg);
5125         if (HAS_PCH_CPT(dev_priv)) {
5126                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5127                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5128         } else {
5129                 temp &= ~FDI_LINK_TRAIN_NONE;
5130                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5131         }
5132         /* BPC in FDI rx is consistent with that in PIPECONF */
5133         temp &= ~(0x07 << 16);
5134         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5135         I915_WRITE(reg, temp);
5136
5137         POSTING_READ(reg);
5138         udelay(100);
5139 }
5140
5141 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5142 {
5143         struct drm_crtc *crtc;
5144         bool cleanup_done;
5145
5146         drm_for_each_crtc(crtc, &dev_priv->drm) {
5147                 struct drm_crtc_commit *commit;
5148                 spin_lock(&crtc->commit_lock);
5149                 commit = list_first_entry_or_null(&crtc->commit_list,
5150                                                   struct drm_crtc_commit, commit_entry);
5151                 cleanup_done = commit ?
5152                         try_wait_for_completion(&commit->cleanup_done) : true;
5153                 spin_unlock(&crtc->commit_lock);
5154
5155                 if (cleanup_done)
5156                         continue;
5157
5158                 drm_crtc_wait_one_vblank(crtc);
5159
5160                 return true;
5161         }
5162
5163         return false;
5164 }
5165
5166 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5167 {
5168         u32 temp;
5169
5170         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
5171
5172         mutex_lock(&dev_priv->sb_lock);
5173
5174         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5175         temp |= SBI_SSCCTL_DISABLE;
5176         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5177
5178         mutex_unlock(&dev_priv->sb_lock);
5179 }
5180
5181 /* Program iCLKIP clock to the desired frequency */
5182 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5183 {
5184         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5185         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5186         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5187         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5188         u32 temp;
5189
5190         lpt_disable_iclkip(dev_priv);
5191
5192         /* The iCLK virtual clock root frequency is in MHz,
5193          * but the adjusted_mode->crtc_clock in in KHz. To get the
5194          * divisors, it is necessary to divide one by another, so we
5195          * convert the virtual clock precision to KHz here for higher
5196          * precision.
5197          */
5198         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5199                 u32 iclk_virtual_root_freq = 172800 * 1000;
5200                 u32 iclk_pi_range = 64;
5201                 u32 desired_divisor;
5202
5203                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5204                                                     clock << auxdiv);
5205                 divsel = (desired_divisor / iclk_pi_range) - 2;
5206                 phaseinc = desired_divisor % iclk_pi_range;
5207
5208                 /*
5209                  * Near 20MHz is a corner case which is
5210                  * out of range for the 7-bit divisor
5211                  */
5212                 if (divsel <= 0x7f)
5213                         break;
5214         }
5215
5216         /* This should not happen with any sane values */
5217         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5218                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5219         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5220                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5221
5222         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5223                         clock,
5224                         auxdiv,
5225                         divsel,
5226                         phasedir,
5227                         phaseinc);
5228
5229         mutex_lock(&dev_priv->sb_lock);
5230
5231         /* Program SSCDIVINTPHASE6 */
5232         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5233         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5234         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5235         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5236         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5237         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5238         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5239         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5240
5241         /* Program SSCAUXDIV */
5242         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5243         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5244         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5245         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5246
5247         /* Enable modulator and associated divider */
5248         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5249         temp &= ~SBI_SSCCTL_DISABLE;
5250         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5251
5252         mutex_unlock(&dev_priv->sb_lock);
5253
5254         /* Wait for initialization time */
5255         udelay(24);
5256
5257         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5258 }
5259
5260 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5261 {
5262         u32 divsel, phaseinc, auxdiv;
5263         u32 iclk_virtual_root_freq = 172800 * 1000;
5264         u32 iclk_pi_range = 64;
5265         u32 desired_divisor;
5266         u32 temp;
5267
5268         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5269                 return 0;
5270
5271         mutex_lock(&dev_priv->sb_lock);
5272
5273         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5274         if (temp & SBI_SSCCTL_DISABLE) {
5275                 mutex_unlock(&dev_priv->sb_lock);
5276                 return 0;
5277         }
5278
5279         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5280         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5281                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5282         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5283                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5284
5285         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5286         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5287                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5288
5289         mutex_unlock(&dev_priv->sb_lock);
5290
5291         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5292
5293         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5294                                  desired_divisor << auxdiv);
5295 }
5296
5297 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5298                                                 enum pipe pch_transcoder)
5299 {
5300         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5301         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5302         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5303
5304         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5305                    I915_READ(HTOTAL(cpu_transcoder)));
5306         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5307                    I915_READ(HBLANK(cpu_transcoder)));
5308         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5309                    I915_READ(HSYNC(cpu_transcoder)));
5310
5311         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5312                    I915_READ(VTOTAL(cpu_transcoder)));
5313         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5314                    I915_READ(VBLANK(cpu_transcoder)));
5315         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5316                    I915_READ(VSYNC(cpu_transcoder)));
5317         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5318                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
5319 }
5320
5321 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5322 {
5323         u32 temp;
5324
5325         temp = I915_READ(SOUTH_CHICKEN1);
5326         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5327                 return;
5328
5329         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5330         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5331
5332         temp &= ~FDI_BC_BIFURCATION_SELECT;
5333         if (enable)
5334                 temp |= FDI_BC_BIFURCATION_SELECT;
5335
5336         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5337         I915_WRITE(SOUTH_CHICKEN1, temp);
5338         POSTING_READ(SOUTH_CHICKEN1);
5339 }
5340
5341 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5342 {
5343         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5344         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5345
5346         switch (crtc->pipe) {
5347         case PIPE_A:
5348                 break;
5349         case PIPE_B:
5350                 if (crtc_state->fdi_lanes > 2)
5351                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5352                 else
5353                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5354
5355                 break;
5356         case PIPE_C:
5357                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5358
5359                 break;
5360         default:
5361                 BUG();
5362         }
5363 }
5364
5365 /*
5366  * Finds the encoder associated with the given CRTC. This can only be
5367  * used when we know that the CRTC isn't feeding multiple encoders!
5368  */
5369 static struct intel_encoder *
5370 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5371                            const struct intel_crtc_state *crtc_state)
5372 {
5373         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5374         const struct drm_connector_state *connector_state;
5375         const struct drm_connector *connector;
5376         struct intel_encoder *encoder = NULL;
5377         int num_encoders = 0;
5378         int i;
5379
5380         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5381                 if (connector_state->crtc != &crtc->base)
5382                         continue;
5383
5384                 encoder = to_intel_encoder(connector_state->best_encoder);
5385                 num_encoders++;
5386         }
5387
5388         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5389              num_encoders, pipe_name(crtc->pipe));
5390
5391         return encoder;
5392 }
5393
5394 /*
5395  * Enable PCH resources required for PCH ports:
5396  *   - PCH PLLs
5397  *   - FDI training & RX/TX
5398  *   - update transcoder timings
5399  *   - DP transcoding bits
5400  *   - transcoder
5401  */
5402 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5403                                 const struct intel_crtc_state *crtc_state)
5404 {
5405         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5406         struct drm_device *dev = crtc->base.dev;
5407         struct drm_i915_private *dev_priv = to_i915(dev);
5408         enum pipe pipe = crtc->pipe;
5409         u32 temp;
5410
5411         assert_pch_transcoder_disabled(dev_priv, pipe);
5412
5413         if (IS_IVYBRIDGE(dev_priv))
5414                 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5415
5416         /* Write the TU size bits before fdi link training, so that error
5417          * detection works. */
5418         I915_WRITE(FDI_RX_TUSIZE1(pipe),
5419                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5420
5421         /* For PCH output, training FDI link */
5422         dev_priv->display.fdi_link_train(crtc, crtc_state);
5423
5424         /* We need to program the right clock selection before writing the pixel
5425          * mutliplier into the DPLL. */
5426         if (HAS_PCH_CPT(dev_priv)) {
5427                 u32 sel;
5428
5429                 temp = I915_READ(PCH_DPLL_SEL);
5430                 temp |= TRANS_DPLL_ENABLE(pipe);
5431                 sel = TRANS_DPLLB_SEL(pipe);
5432                 if (crtc_state->shared_dpll ==
5433                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5434                         temp |= sel;
5435                 else
5436                         temp &= ~sel;
5437                 I915_WRITE(PCH_DPLL_SEL, temp);
5438         }
5439
5440         /* XXX: pch pll's can be enabled any time before we enable the PCH
5441          * transcoder, and we actually should do this to not upset any PCH
5442          * transcoder that already use the clock when we share it.
5443          *
5444          * Note that enable_shared_dpll tries to do the right thing, but
5445          * get_shared_dpll unconditionally resets the pll - we need that to have
5446          * the right LVDS enable sequence. */
5447         intel_enable_shared_dpll(crtc_state);
5448
5449         /* set transcoder timing, panel must allow it */
5450         assert_panel_unlocked(dev_priv, pipe);
5451         ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5452
5453         intel_fdi_normal_train(crtc);
5454
5455         /* For PCH DP, enable TRANS_DP_CTL */
5456         if (HAS_PCH_CPT(dev_priv) &&
5457             intel_crtc_has_dp_encoder(crtc_state)) {
5458                 const struct drm_display_mode *adjusted_mode =
5459                         &crtc_state->hw.adjusted_mode;
5460                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5461                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5462                 enum port port;
5463
5464                 temp = I915_READ(reg);
5465                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5466                           TRANS_DP_SYNC_MASK |
5467                           TRANS_DP_BPC_MASK);
5468                 temp |= TRANS_DP_OUTPUT_ENABLE;
5469                 temp |= bpc << 9; /* same format but at 11:9 */
5470
5471                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5472                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5473                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5474                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5475
5476                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5477                 WARN_ON(port < PORT_B || port > PORT_D);
5478                 temp |= TRANS_DP_PORT_SEL(port);
5479
5480                 I915_WRITE(reg, temp);
5481         }
5482
5483         ironlake_enable_pch_transcoder(crtc_state);
5484 }
5485
5486 static void lpt_pch_enable(const struct intel_atomic_state *state,
5487                            const struct intel_crtc_state *crtc_state)
5488 {
5489         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5490         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5491         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5492
5493         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5494
5495         lpt_program_iclkip(crtc_state);
5496
5497         /* Set transcoder timing. */
5498         ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5499
5500         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5501 }
5502
5503 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5504                                enum pipe pipe)
5505 {
5506         i915_reg_t dslreg = PIPEDSL(pipe);
5507         u32 temp;
5508
5509         temp = I915_READ(dslreg);
5510         udelay(500);
5511         if (wait_for(I915_READ(dslreg) != temp, 5)) {
5512                 if (wait_for(I915_READ(dslreg) != temp, 5))
5513                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5514         }
5515 }
5516
5517 /*
5518  * The hardware phase 0.0 refers to the center of the pixel.
5519  * We want to start from the top/left edge which is phase
5520  * -0.5. That matches how the hardware calculates the scaling
5521  * factors (from top-left of the first pixel to bottom-right
5522  * of the last pixel, as opposed to the pixel centers).
5523  *
5524  * For 4:2:0 subsampled chroma planes we obviously have to
5525  * adjust that so that the chroma sample position lands in
5526  * the right spot.
5527  *
5528  * Note that for packed YCbCr 4:2:2 formats there is no way to
5529  * control chroma siting. The hardware simply replicates the
5530  * chroma samples for both of the luma samples, and thus we don't
5531  * actually get the expected MPEG2 chroma siting convention :(
5532  * The same behaviour is observed on pre-SKL platforms as well.
5533  *
5534  * Theory behind the formula (note that we ignore sub-pixel
5535  * source coordinates):
5536  * s = source sample position
5537  * d = destination sample position
5538  *
5539  * Downscaling 4:1:
5540  * -0.5
5541  * | 0.0
5542  * | |     1.5 (initial phase)
5543  * | |     |
5544  * v v     v
5545  * | s | s | s | s |
5546  * |       d       |
5547  *
5548  * Upscaling 1:4:
5549  * -0.5
5550  * | -0.375 (initial phase)
5551  * | |     0.0
5552  * | |     |
5553  * v v     v
5554  * |       s       |
5555  * | d | d | d | d |
5556  */
5557 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5558 {
5559         int phase = -0x8000;
5560         u16 trip = 0;
5561
5562         if (chroma_cosited)
5563                 phase += (sub - 1) * 0x8000 / sub;
5564
5565         phase += scale / (2 * sub);
5566
5567         /*
5568          * Hardware initial phase limited to [-0.5:1.5].
5569          * Since the max hardware scale factor is 3.0, we
5570          * should never actually excdeed 1.0 here.
5571          */
5572         WARN_ON(phase < -0x8000 || phase > 0x18000);
5573
5574         if (phase < 0)
5575                 phase = 0x10000 + phase;
5576         else
5577                 trip = PS_PHASE_TRIP;
5578
5579         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5580 }
5581
5582 #define SKL_MIN_SRC_W 8
5583 #define SKL_MAX_SRC_W 4096
5584 #define SKL_MIN_SRC_H 8
5585 #define SKL_MAX_SRC_H 4096
5586 #define SKL_MIN_DST_W 8
5587 #define SKL_MAX_DST_W 4096
5588 #define SKL_MIN_DST_H 8
5589 #define SKL_MAX_DST_H 4096
5590 #define ICL_MAX_SRC_W 5120
5591 #define ICL_MAX_SRC_H 4096
5592 #define ICL_MAX_DST_W 5120
5593 #define ICL_MAX_DST_H 4096
5594 #define SKL_MIN_YUV_420_SRC_W 16
5595 #define SKL_MIN_YUV_420_SRC_H 16
5596
5597 static int
5598 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5599                   unsigned int scaler_user, int *scaler_id,
5600                   int src_w, int src_h, int dst_w, int dst_h,
5601                   const struct drm_format_info *format, bool need_scaler)
5602 {
5603         struct intel_crtc_scaler_state *scaler_state =
5604                 &crtc_state->scaler_state;
5605         struct intel_crtc *intel_crtc =
5606                 to_intel_crtc(crtc_state->uapi.crtc);
5607         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5608         const struct drm_display_mode *adjusted_mode =
5609                 &crtc_state->hw.adjusted_mode;
5610
5611         /*
5612          * Src coordinates are already rotated by 270 degrees for
5613          * the 90/270 degree plane rotation cases (to match the
5614          * GTT mapping), hence no need to account for rotation here.
5615          */
5616         if (src_w != dst_w || src_h != dst_h)
5617                 need_scaler = true;
5618
5619         /*
5620          * Scaling/fitting not supported in IF-ID mode in GEN9+
5621          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5622          * Once NV12 is enabled, handle it here while allocating scaler
5623          * for NV12.
5624          */
5625         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
5626             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5627                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5628                 return -EINVAL;
5629         }
5630
5631         /*
5632          * if plane is being disabled or scaler is no more required or force detach
5633          *  - free scaler binded to this plane/crtc
5634          *  - in order to do this, update crtc->scaler_usage
5635          *
5636          * Here scaler state in crtc_state is set free so that
5637          * scaler can be assigned to other user. Actual register
5638          * update to free the scaler is done in plane/panel-fit programming.
5639          * For this purpose crtc/plane_state->scaler_id isn't reset here.
5640          */
5641         if (force_detach || !need_scaler) {
5642                 if (*scaler_id >= 0) {
5643                         scaler_state->scaler_users &= ~(1 << scaler_user);
5644                         scaler_state->scalers[*scaler_id].in_use = 0;
5645
5646                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5647                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5648                                 intel_crtc->pipe, scaler_user, *scaler_id,
5649                                 scaler_state->scaler_users);
5650                         *scaler_id = -1;
5651                 }
5652                 return 0;
5653         }
5654
5655         if (format && drm_format_info_is_yuv_semiplanar(format) &&
5656             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5657                 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5658                 return -EINVAL;
5659         }
5660
5661         /* range checks */
5662         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5663             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5664             (INTEL_GEN(dev_priv) >= 11 &&
5665              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5666               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5667             (INTEL_GEN(dev_priv) < 11 &&
5668              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5669               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5670                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5671                         "size is out of scaler range\n",
5672                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5673                 return -EINVAL;
5674         }
5675
5676         /* mark this plane as a scaler user in crtc_state */
5677         scaler_state->scaler_users |= (1 << scaler_user);
5678         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5679                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5680                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5681                 scaler_state->scaler_users);
5682
5683         return 0;
5684 }
5685
5686 /**
5687  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5688  *
5689  * @state: crtc's scaler state
5690  *
5691  * Return
5692  *     0 - scaler_usage updated successfully
5693  *    error - requested scaling cannot be supported or other error condition
5694  */
5695 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5696 {
5697         const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
5698         bool need_scaler = false;
5699
5700         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5701                 need_scaler = true;
5702
5703         return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
5704                                  &state->scaler_state.scaler_id,
5705                                  state->pipe_src_w, state->pipe_src_h,
5706                                  adjusted_mode->crtc_hdisplay,
5707                                  adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5708 }
5709
5710 /**
5711  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5712  * @crtc_state: crtc's scaler state
5713  * @plane_state: atomic plane state to update
5714  *
5715  * Return
5716  *     0 - scaler_usage updated successfully
5717  *    error - requested scaling cannot be supported or other error condition
5718  */
5719 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5720                                    struct intel_plane_state *plane_state)
5721 {
5722         struct intel_plane *intel_plane =
5723                 to_intel_plane(plane_state->uapi.plane);
5724         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5725         struct drm_framebuffer *fb = plane_state->hw.fb;
5726         int ret;
5727         bool force_detach = !fb || !plane_state->uapi.visible;
5728         bool need_scaler = false;
5729
5730         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5731         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5732             fb && drm_format_info_is_yuv_semiplanar(fb->format))
5733                 need_scaler = true;
5734
5735         ret = skl_update_scaler(crtc_state, force_detach,
5736                                 drm_plane_index(&intel_plane->base),
5737                                 &plane_state->scaler_id,
5738                                 drm_rect_width(&plane_state->uapi.src) >> 16,
5739                                 drm_rect_height(&plane_state->uapi.src) >> 16,
5740                                 drm_rect_width(&plane_state->uapi.dst),
5741                                 drm_rect_height(&plane_state->uapi.dst),
5742                                 fb ? fb->format : NULL, need_scaler);
5743
5744         if (ret || plane_state->scaler_id < 0)
5745                 return ret;
5746
5747         /* check colorkey */
5748         if (plane_state->ckey.flags) {
5749                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5750                               intel_plane->base.base.id,
5751                               intel_plane->base.name);
5752                 return -EINVAL;
5753         }
5754
5755         /* Check src format */
5756         switch (fb->format->format) {
5757         case DRM_FORMAT_RGB565:
5758         case DRM_FORMAT_XBGR8888:
5759         case DRM_FORMAT_XRGB8888:
5760         case DRM_FORMAT_ABGR8888:
5761         case DRM_FORMAT_ARGB8888:
5762         case DRM_FORMAT_XRGB2101010:
5763         case DRM_FORMAT_XBGR2101010:
5764         case DRM_FORMAT_ARGB2101010:
5765         case DRM_FORMAT_ABGR2101010:
5766         case DRM_FORMAT_YUYV:
5767         case DRM_FORMAT_YVYU:
5768         case DRM_FORMAT_UYVY:
5769         case DRM_FORMAT_VYUY:
5770         case DRM_FORMAT_NV12:
5771         case DRM_FORMAT_P010:
5772         case DRM_FORMAT_P012:
5773         case DRM_FORMAT_P016:
5774         case DRM_FORMAT_Y210:
5775         case DRM_FORMAT_Y212:
5776         case DRM_FORMAT_Y216:
5777         case DRM_FORMAT_XVYU2101010:
5778         case DRM_FORMAT_XVYU12_16161616:
5779         case DRM_FORMAT_XVYU16161616:
5780                 break;
5781         case DRM_FORMAT_XBGR16161616F:
5782         case DRM_FORMAT_ABGR16161616F:
5783         case DRM_FORMAT_XRGB16161616F:
5784         case DRM_FORMAT_ARGB16161616F:
5785                 if (INTEL_GEN(dev_priv) >= 11)
5786                         break;
5787                 /* fall through */
5788         default:
5789                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5790                               intel_plane->base.base.id, intel_plane->base.name,
5791                               fb->base.id, fb->format->format);
5792                 return -EINVAL;
5793         }
5794
5795         return 0;
5796 }
5797
5798 static void skylake_scaler_disable(struct intel_crtc *crtc)
5799 {
5800         int i;
5801
5802         for (i = 0; i < crtc->num_scalers; i++)
5803                 skl_detach_scaler(crtc, i);
5804 }
5805
5806 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5807 {
5808         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5809         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5810         enum pipe pipe = crtc->pipe;
5811         const struct intel_crtc_scaler_state *scaler_state =
5812                 &crtc_state->scaler_state;
5813
5814         if (crtc_state->pch_pfit.enabled) {
5815                 u16 uv_rgb_hphase, uv_rgb_vphase;
5816                 int pfit_w, pfit_h, hscale, vscale;
5817                 int id;
5818
5819                 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5820                         return;
5821
5822                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5823                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5824
5825                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5826                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5827
5828                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5829                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5830
5831                 id = scaler_state->scaler_id;
5832                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5833                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5834                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5835                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5836                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5837                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5838                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5839                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5840         }
5841 }
5842
5843 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5844 {
5845         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5846         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5847         enum pipe pipe = crtc->pipe;
5848
5849         if (crtc_state->pch_pfit.enabled) {
5850                 /* Force use of hard-coded filter coefficients
5851                  * as some pre-programmed values are broken,
5852                  * e.g. x201.
5853                  */
5854                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5855                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5856                                                  PF_PIPE_SEL_IVB(pipe));
5857                 else
5858                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5859                 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5860                 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5861         }
5862 }
5863
5864 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5865 {
5866         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5867         struct drm_device *dev = crtc->base.dev;
5868         struct drm_i915_private *dev_priv = to_i915(dev);
5869
5870         if (!crtc_state->ips_enabled)
5871                 return;
5872
5873         /*
5874          * We can only enable IPS after we enable a plane and wait for a vblank
5875          * This function is called from post_plane_update, which is run after
5876          * a vblank wait.
5877          */
5878         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5879
5880         if (IS_BROADWELL(dev_priv)) {
5881                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5882                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5883                 /* Quoting Art Runyan: "its not safe to expect any particular
5884                  * value in IPS_CTL bit 31 after enabling IPS through the
5885                  * mailbox." Moreover, the mailbox may return a bogus state,
5886                  * so we need to just enable it and continue on.
5887                  */
5888         } else {
5889                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5890                 /* The bit only becomes 1 in the next vblank, so this wait here
5891                  * is essentially intel_wait_for_vblank. If we don't have this
5892                  * and don't wait for vblanks until the end of crtc_enable, then
5893                  * the HW state readout code will complain that the expected
5894                  * IPS_CTL value is not the one we read. */
5895                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5896                         DRM_ERROR("Timed out waiting for IPS enable\n");
5897         }
5898 }
5899
5900 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5901 {
5902         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5903         struct drm_device *dev = crtc->base.dev;
5904         struct drm_i915_private *dev_priv = to_i915(dev);
5905
5906         if (!crtc_state->ips_enabled)
5907                 return;
5908
5909         if (IS_BROADWELL(dev_priv)) {
5910                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5911                 /*
5912                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5913                  * 42ms timeout value leads to occasional timeouts so use 100ms
5914                  * instead.
5915                  */
5916                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5917                         DRM_ERROR("Timed out waiting for IPS disable\n");
5918         } else {
5919                 I915_WRITE(IPS_CTL, 0);
5920                 POSTING_READ(IPS_CTL);
5921         }
5922
5923         /* We need to wait for a vblank before we can disable the plane. */
5924         intel_wait_for_vblank(dev_priv, crtc->pipe);
5925 }
5926
5927 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5928 {
5929         if (intel_crtc->overlay)
5930                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5931
5932         /* Let userspace switch the overlay on again. In most cases userspace
5933          * has to recompute where to put it anyway.
5934          */
5935 }
5936
5937 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5938                                        const struct intel_crtc_state *new_crtc_state)
5939 {
5940         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5941         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5942
5943         if (!old_crtc_state->ips_enabled)
5944                 return false;
5945
5946         if (needs_modeset(new_crtc_state))
5947                 return true;
5948
5949         /*
5950          * Workaround : Do not read or write the pipe palette/gamma data while
5951          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5952          *
5953          * Disable IPS before we program the LUT.
5954          */
5955         if (IS_HASWELL(dev_priv) &&
5956             (new_crtc_state->uapi.color_mgmt_changed ||
5957              new_crtc_state->update_pipe) &&
5958             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5959                 return true;
5960
5961         return !new_crtc_state->ips_enabled;
5962 }
5963
5964 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5965                                        const struct intel_crtc_state *new_crtc_state)
5966 {
5967         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5968         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5969
5970         if (!new_crtc_state->ips_enabled)
5971                 return false;
5972
5973         if (needs_modeset(new_crtc_state))
5974                 return true;
5975
5976         /*
5977          * Workaround : Do not read or write the pipe palette/gamma data while
5978          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5979          *
5980          * Re-enable IPS after the LUT has been programmed.
5981          */
5982         if (IS_HASWELL(dev_priv) &&
5983             (new_crtc_state->uapi.color_mgmt_changed ||
5984              new_crtc_state->update_pipe) &&
5985             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5986                 return true;
5987
5988         /*
5989          * We can't read out IPS on broadwell, assume the worst and
5990          * forcibly enable IPS on the first fastset.
5991          */
5992         if (new_crtc_state->update_pipe &&
5993             old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5994                 return true;
5995
5996         return !old_crtc_state->ips_enabled;
5997 }
5998
5999 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6000 {
6001         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6002
6003         if (!crtc_state->nv12_planes)
6004                 return false;
6005
6006         /* WA Display #0827: Gen9:all */
6007         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6008                 return true;
6009
6010         return false;
6011 }
6012
6013 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6014 {
6015         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6016
6017         /* Wa_2006604312:icl */
6018         if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
6019                 return true;
6020
6021         return false;
6022 }
6023
6024 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6025                             const struct intel_crtc_state *new_crtc_state)
6026 {
6027         return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6028                 new_crtc_state->active_planes;
6029 }
6030
6031 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6032                              const struct intel_crtc_state *new_crtc_state)
6033 {
6034         return old_crtc_state->active_planes &&
6035                 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6036 }
6037
6038 static void intel_post_plane_update(struct intel_atomic_state *state,
6039                                     struct intel_crtc *crtc)
6040 {
6041         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6042         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
6043         const struct intel_crtc_state *old_crtc_state =
6044                 intel_atomic_get_old_crtc_state(state, crtc);
6045         const struct intel_crtc_state *new_crtc_state =
6046                 intel_atomic_get_new_crtc_state(state, crtc);
6047         const struct intel_plane_state *new_primary_state =
6048                 intel_atomic_get_new_plane_state(state, primary);
6049         enum pipe pipe = crtc->pipe;
6050
6051         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6052
6053         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6054                 intel_update_watermarks(crtc);
6055
6056         if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6057                 hsw_enable_ips(new_crtc_state);
6058
6059         if (new_primary_state)
6060                 intel_fbc_post_update(crtc);
6061
6062         if (needs_nv12_wa(old_crtc_state) &&
6063             !needs_nv12_wa(new_crtc_state))
6064                 skl_wa_827(dev_priv, pipe, false);
6065
6066         if (needs_scalerclk_wa(old_crtc_state) &&
6067             !needs_scalerclk_wa(new_crtc_state))
6068                 icl_wa_scalerclkgating(dev_priv, pipe, false);
6069 }
6070
6071 static void intel_pre_plane_update(struct intel_atomic_state *state,
6072                                    struct intel_crtc *crtc)
6073 {
6074         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6075         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
6076         const struct intel_crtc_state *old_crtc_state =
6077                 intel_atomic_get_old_crtc_state(state, crtc);
6078         const struct intel_crtc_state *new_crtc_state =
6079                 intel_atomic_get_new_crtc_state(state, crtc);
6080         const struct intel_plane_state *new_primary_state =
6081                 intel_atomic_get_new_plane_state(state, primary);
6082         enum pipe pipe = crtc->pipe;
6083
6084         if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6085                 hsw_disable_ips(old_crtc_state);
6086
6087         if (new_primary_state)
6088                 intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
6089
6090         /* Display WA 827 */
6091         if (!needs_nv12_wa(old_crtc_state) &&
6092             needs_nv12_wa(new_crtc_state))
6093                 skl_wa_827(dev_priv, pipe, true);
6094
6095         /* Wa_2006604312:icl */
6096         if (!needs_scalerclk_wa(old_crtc_state) &&
6097             needs_scalerclk_wa(new_crtc_state))
6098                 icl_wa_scalerclkgating(dev_priv, pipe, true);
6099
6100         /*
6101          * Vblank time updates from the shadow to live plane control register
6102          * are blocked if the memory self-refresh mode is active at that
6103          * moment. So to make sure the plane gets truly disabled, disable
6104          * first the self-refresh mode. The self-refresh enable bit in turn
6105          * will be checked/applied by the HW only at the next frame start
6106          * event which is after the vblank start event, so we need to have a
6107          * wait-for-vblank between disabling the plane and the pipe.
6108          */
6109         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6110             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6111                 intel_wait_for_vblank(dev_priv, pipe);
6112
6113         /*
6114          * IVB workaround: must disable low power watermarks for at least
6115          * one frame before enabling scaling.  LP watermarks can be re-enabled
6116          * when scaling is disabled.
6117          *
6118          * WaCxSRDisabledForSpriteScaling:ivb
6119          */
6120         if (old_crtc_state->hw.active &&
6121             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6122                 intel_wait_for_vblank(dev_priv, pipe);
6123
6124         /*
6125          * If we're doing a modeset we don't need to do any
6126          * pre-vblank watermark programming here.
6127          */
6128         if (!needs_modeset(new_crtc_state)) {
6129                 /*
6130                  * For platforms that support atomic watermarks, program the
6131                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6132                  * will be the intermediate values that are safe for both pre- and
6133                  * post- vblank; when vblank happens, the 'active' values will be set
6134                  * to the final 'target' values and we'll do this again to get the
6135                  * optimal watermarks.  For gen9+ platforms, the values we program here
6136                  * will be the final target values which will get automatically latched
6137                  * at vblank time; no further programming will be necessary.
6138                  *
6139                  * If a platform hasn't been transitioned to atomic watermarks yet,
6140                  * we'll continue to update watermarks the old way, if flags tell
6141                  * us to.
6142                  */
6143                 if (dev_priv->display.initial_watermarks)
6144                         dev_priv->display.initial_watermarks(state, crtc);
6145                 else if (new_crtc_state->update_wm_pre)
6146                         intel_update_watermarks(crtc);
6147         }
6148
6149         /*
6150          * Gen2 reports pipe underruns whenever all planes are disabled.
6151          * So disable underrun reporting before all the planes get disabled.
6152          *
6153          * We do this after .initial_watermarks() so that we have a
6154          * chance of catching underruns with the intermediate watermarks
6155          * vs. the old plane configuration.
6156          */
6157         if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6158                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6159 }
6160
6161 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6162                                       struct intel_crtc *crtc)
6163 {
6164         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6165         const struct intel_crtc_state *new_crtc_state =
6166                 intel_atomic_get_new_crtc_state(state, crtc);
6167         unsigned int update_mask = new_crtc_state->update_planes;
6168         const struct intel_plane_state *old_plane_state;
6169         struct intel_plane *plane;
6170         unsigned fb_bits = 0;
6171         int i;
6172
6173         intel_crtc_dpms_overlay_disable(crtc);
6174
6175         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6176                 if (crtc->pipe != plane->pipe ||
6177                     !(update_mask & BIT(plane->id)))
6178                         continue;
6179
6180                 intel_disable_plane(plane, new_crtc_state);
6181
6182                 if (old_plane_state->uapi.visible)
6183                         fb_bits |= plane->frontbuffer_bit;
6184         }
6185
6186         intel_frontbuffer_flip(dev_priv, fb_bits);
6187 }
6188
6189 /*
6190  * intel_connector_primary_encoder - get the primary encoder for a connector
6191  * @connector: connector for which to return the encoder
6192  *
6193  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6194  * all connectors to their encoder, except for DP-MST connectors which have
6195  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6196  * pointed to by as many DP-MST connectors as there are pipes.
6197  */
6198 static struct intel_encoder *
6199 intel_connector_primary_encoder(struct intel_connector *connector)
6200 {
6201         struct intel_encoder *encoder;
6202
6203         if (connector->mst_port)
6204                 return &dp_to_dig_port(connector->mst_port)->base;
6205
6206         encoder = intel_attached_encoder(&connector->base);
6207         WARN_ON(!encoder);
6208
6209         return encoder;
6210 }
6211
6212 static bool
6213 intel_connector_needs_modeset(struct intel_atomic_state *state,
6214                               const struct drm_connector_state *old_conn_state,
6215                               const struct drm_connector_state *new_conn_state)
6216 {
6217         struct intel_crtc *old_crtc = old_conn_state->crtc ?
6218                                       to_intel_crtc(old_conn_state->crtc) : NULL;
6219         struct intel_crtc *new_crtc = new_conn_state->crtc ?
6220                                       to_intel_crtc(new_conn_state->crtc) : NULL;
6221
6222         return new_crtc != old_crtc ||
6223                (new_crtc &&
6224                 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6225 }
6226
6227 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6228 {
6229         struct drm_connector_state *old_conn_state;
6230         struct drm_connector_state *new_conn_state;
6231         struct drm_connector *conn;
6232         int i;
6233
6234         for_each_oldnew_connector_in_state(&state->base, conn,
6235                                            old_conn_state, new_conn_state, i) {
6236                 struct intel_encoder *encoder;
6237                 struct intel_crtc *crtc;
6238
6239                 if (!intel_connector_needs_modeset(state,
6240                                                    old_conn_state,
6241                                                    new_conn_state))
6242                         continue;
6243
6244                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6245                 if (!encoder->update_prepare)
6246                         continue;
6247
6248                 crtc = new_conn_state->crtc ?
6249                         to_intel_crtc(new_conn_state->crtc) : NULL;
6250                 encoder->update_prepare(state, encoder, crtc);
6251         }
6252 }
6253
6254 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6255 {
6256         struct drm_connector_state *old_conn_state;
6257         struct drm_connector_state *new_conn_state;
6258         struct drm_connector *conn;
6259         int i;
6260
6261         for_each_oldnew_connector_in_state(&state->base, conn,
6262                                            old_conn_state, new_conn_state, i) {
6263                 struct intel_encoder *encoder;
6264                 struct intel_crtc *crtc;
6265
6266                 if (!intel_connector_needs_modeset(state,
6267                                                    old_conn_state,
6268                                                    new_conn_state))
6269                         continue;
6270
6271                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6272                 if (!encoder->update_complete)
6273                         continue;
6274
6275                 crtc = new_conn_state->crtc ?
6276                         to_intel_crtc(new_conn_state->crtc) : NULL;
6277                 encoder->update_complete(state, encoder, crtc);
6278         }
6279 }
6280
6281 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6282                                           struct intel_crtc *crtc)
6283 {
6284         const struct intel_crtc_state *crtc_state =
6285                 intel_atomic_get_new_crtc_state(state, crtc);
6286         const struct drm_connector_state *conn_state;
6287         struct drm_connector *conn;
6288         int i;
6289
6290         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6291                 struct intel_encoder *encoder =
6292                         to_intel_encoder(conn_state->best_encoder);
6293
6294                 if (conn_state->crtc != &crtc->base)
6295                         continue;
6296
6297                 if (encoder->pre_pll_enable)
6298                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6299         }
6300 }
6301
6302 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6303                                       struct intel_crtc *crtc)
6304 {
6305         const struct intel_crtc_state *crtc_state =
6306                 intel_atomic_get_new_crtc_state(state, crtc);
6307         const struct drm_connector_state *conn_state;
6308         struct drm_connector *conn;
6309         int i;
6310
6311         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6312                 struct intel_encoder *encoder =
6313                         to_intel_encoder(conn_state->best_encoder);
6314
6315                 if (conn_state->crtc != &crtc->base)
6316                         continue;
6317
6318                 if (encoder->pre_enable)
6319                         encoder->pre_enable(encoder, crtc_state, conn_state);
6320         }
6321 }
6322
6323 static void intel_encoders_enable(struct intel_atomic_state *state,
6324                                   struct intel_crtc *crtc)
6325 {
6326         const struct intel_crtc_state *crtc_state =
6327                 intel_atomic_get_new_crtc_state(state, crtc);
6328         const struct drm_connector_state *conn_state;
6329         struct drm_connector *conn;
6330         int i;
6331
6332         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6333                 struct intel_encoder *encoder =
6334                         to_intel_encoder(conn_state->best_encoder);
6335
6336                 if (conn_state->crtc != &crtc->base)
6337                         continue;
6338
6339                 if (encoder->enable)
6340                         encoder->enable(encoder, crtc_state, conn_state);
6341                 intel_opregion_notify_encoder(encoder, true);
6342         }
6343 }
6344
6345 static void intel_encoders_disable(struct intel_atomic_state *state,
6346                                    struct intel_crtc *crtc)
6347 {
6348         const struct intel_crtc_state *old_crtc_state =
6349                 intel_atomic_get_old_crtc_state(state, crtc);
6350         const struct drm_connector_state *old_conn_state;
6351         struct drm_connector *conn;
6352         int i;
6353
6354         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6355                 struct intel_encoder *encoder =
6356                         to_intel_encoder(old_conn_state->best_encoder);
6357
6358                 if (old_conn_state->crtc != &crtc->base)
6359                         continue;
6360
6361                 intel_opregion_notify_encoder(encoder, false);
6362                 if (encoder->disable)
6363                         encoder->disable(encoder, old_crtc_state, old_conn_state);
6364         }
6365 }
6366
6367 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6368                                         struct intel_crtc *crtc)
6369 {
6370         const struct intel_crtc_state *old_crtc_state =
6371                 intel_atomic_get_old_crtc_state(state, crtc);
6372         const struct drm_connector_state *old_conn_state;
6373         struct drm_connector *conn;
6374         int i;
6375
6376         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6377                 struct intel_encoder *encoder =
6378                         to_intel_encoder(old_conn_state->best_encoder);
6379
6380                 if (old_conn_state->crtc != &crtc->base)
6381                         continue;
6382
6383                 if (encoder->post_disable)
6384                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6385         }
6386 }
6387
6388 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6389                                             struct intel_crtc *crtc)
6390 {
6391         const struct intel_crtc_state *old_crtc_state =
6392                 intel_atomic_get_old_crtc_state(state, crtc);
6393         const struct drm_connector_state *old_conn_state;
6394         struct drm_connector *conn;
6395         int i;
6396
6397         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6398                 struct intel_encoder *encoder =
6399                         to_intel_encoder(old_conn_state->best_encoder);
6400
6401                 if (old_conn_state->crtc != &crtc->base)
6402                         continue;
6403
6404                 if (encoder->post_pll_disable)
6405                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6406         }
6407 }
6408
6409 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6410                                        struct intel_crtc *crtc)
6411 {
6412         const struct intel_crtc_state *crtc_state =
6413                 intel_atomic_get_new_crtc_state(state, crtc);
6414         const struct drm_connector_state *conn_state;
6415         struct drm_connector *conn;
6416         int i;
6417
6418         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6419                 struct intel_encoder *encoder =
6420                         to_intel_encoder(conn_state->best_encoder);
6421
6422                 if (conn_state->crtc != &crtc->base)
6423                         continue;
6424
6425                 if (encoder->update_pipe)
6426                         encoder->update_pipe(encoder, crtc_state, conn_state);
6427         }
6428 }
6429
6430 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6431 {
6432         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6433         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6434
6435         plane->disable_plane(plane, crtc_state);
6436 }
6437
6438 static void ironlake_crtc_enable(struct intel_atomic_state *state,
6439                                  struct intel_crtc *crtc)
6440 {
6441         const struct intel_crtc_state *new_crtc_state =
6442                 intel_atomic_get_new_crtc_state(state, crtc);
6443         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6444         enum pipe pipe = crtc->pipe;
6445
6446         if (WARN_ON(crtc->active))
6447                 return;
6448
6449         /*
6450          * Sometimes spurious CPU pipe underruns happen during FDI
6451          * training, at least with VGA+HDMI cloning. Suppress them.
6452          *
6453          * On ILK we get an occasional spurious CPU pipe underruns
6454          * between eDP port A enable and vdd enable. Also PCH port
6455          * enable seems to result in the occasional CPU pipe underrun.
6456          *
6457          * Spurious PCH underruns also occur during PCH enabling.
6458          */
6459         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6460         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6461
6462         if (new_crtc_state->has_pch_encoder)
6463                 intel_prepare_shared_dpll(new_crtc_state);
6464
6465         if (intel_crtc_has_dp_encoder(new_crtc_state))
6466                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6467
6468         intel_set_pipe_timings(new_crtc_state);
6469         intel_set_pipe_src_size(new_crtc_state);
6470
6471         if (new_crtc_state->has_pch_encoder)
6472                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6473                                              &new_crtc_state->fdi_m_n, NULL);
6474
6475         ironlake_set_pipeconf(new_crtc_state);
6476
6477         crtc->active = true;
6478
6479         intel_encoders_pre_enable(state, crtc);
6480
6481         if (new_crtc_state->has_pch_encoder) {
6482                 /* Note: FDI PLL enabling _must_ be done before we enable the
6483                  * cpu pipes, hence this is separate from all the other fdi/pch
6484                  * enabling. */
6485                 ironlake_fdi_pll_enable(new_crtc_state);
6486         } else {
6487                 assert_fdi_tx_disabled(dev_priv, pipe);
6488                 assert_fdi_rx_disabled(dev_priv, pipe);
6489         }
6490
6491         ironlake_pfit_enable(new_crtc_state);
6492
6493         /*
6494          * On ILK+ LUT must be loaded before the pipe is running but with
6495          * clocks enabled
6496          */
6497         intel_color_load_luts(new_crtc_state);
6498         intel_color_commit(new_crtc_state);
6499         /* update DSPCNTR to configure gamma for pipe bottom color */
6500         intel_disable_primary_plane(new_crtc_state);
6501
6502         if (dev_priv->display.initial_watermarks)
6503                 dev_priv->display.initial_watermarks(state, crtc);
6504         intel_enable_pipe(new_crtc_state);
6505
6506         if (new_crtc_state->has_pch_encoder)
6507                 ironlake_pch_enable(state, new_crtc_state);
6508
6509         intel_crtc_vblank_on(new_crtc_state);
6510
6511         intel_encoders_enable(state, crtc);
6512
6513         if (HAS_PCH_CPT(dev_priv))
6514                 cpt_verify_modeset(dev_priv, pipe);
6515
6516         /*
6517          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6518          * And a second vblank wait is needed at least on ILK with
6519          * some interlaced HDMI modes. Let's do the double wait always
6520          * in case there are more corner cases we don't know about.
6521          */
6522         if (new_crtc_state->has_pch_encoder) {
6523                 intel_wait_for_vblank(dev_priv, pipe);
6524                 intel_wait_for_vblank(dev_priv, pipe);
6525         }
6526         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6527         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6528 }
6529
6530 /* IPS only exists on ULT machines and is tied to pipe A. */
6531 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6532 {
6533         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6534 }
6535
6536 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6537                                             enum pipe pipe, bool apply)
6538 {
6539         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6540         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6541
6542         if (apply)
6543                 val |= mask;
6544         else
6545                 val &= ~mask;
6546
6547         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6548 }
6549
6550 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6551 {
6552         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6553         enum pipe pipe = crtc->pipe;
6554         u32 val;
6555
6556         val = MBUS_DBOX_A_CREDIT(2);
6557
6558         if (INTEL_GEN(dev_priv) >= 12) {
6559                 val |= MBUS_DBOX_BW_CREDIT(2);
6560                 val |= MBUS_DBOX_B_CREDIT(12);
6561         } else {
6562                 val |= MBUS_DBOX_BW_CREDIT(1);
6563                 val |= MBUS_DBOX_B_CREDIT(8);
6564         }
6565
6566         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6567 }
6568
6569 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
6570 {
6571         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6572         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6573         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
6574         u32 val;
6575
6576         val = I915_READ(reg);
6577         val &= ~HSW_FRAME_START_DELAY_MASK;
6578         val |= HSW_FRAME_START_DELAY(0);
6579         I915_WRITE(reg, val);
6580 }
6581
6582 static void haswell_crtc_enable(struct intel_atomic_state *state,
6583                                 struct intel_crtc *crtc)
6584 {
6585         const struct intel_crtc_state *new_crtc_state =
6586                 intel_atomic_get_new_crtc_state(state, crtc);
6587         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6588         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
6589         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
6590         bool psl_clkgate_wa;
6591
6592         if (WARN_ON(crtc->active))
6593                 return;
6594
6595         intel_encoders_pre_pll_enable(state, crtc);
6596
6597         if (new_crtc_state->shared_dpll)
6598                 intel_enable_shared_dpll(new_crtc_state);
6599
6600         intel_encoders_pre_enable(state, crtc);
6601
6602         if (intel_crtc_has_dp_encoder(new_crtc_state))
6603                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6604
6605         if (!transcoder_is_dsi(cpu_transcoder))
6606                 intel_set_pipe_timings(new_crtc_state);
6607
6608         if (INTEL_GEN(dev_priv) >= 11)
6609                 icl_enable_trans_port_sync(new_crtc_state);
6610
6611         intel_set_pipe_src_size(new_crtc_state);
6612
6613         if (cpu_transcoder != TRANSCODER_EDP &&
6614             !transcoder_is_dsi(cpu_transcoder))
6615                 I915_WRITE(PIPE_MULT(cpu_transcoder),
6616                            new_crtc_state->pixel_multiplier - 1);
6617
6618         if (new_crtc_state->has_pch_encoder)
6619                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6620                                              &new_crtc_state->fdi_m_n, NULL);
6621
6622         if (!transcoder_is_dsi(cpu_transcoder)) {
6623                 hsw_set_frame_start_delay(new_crtc_state);
6624                 haswell_set_pipeconf(new_crtc_state);
6625         }
6626
6627         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6628                 bdw_set_pipemisc(new_crtc_state);
6629
6630         crtc->active = true;
6631
6632         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6633         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6634                 new_crtc_state->pch_pfit.enabled;
6635         if (psl_clkgate_wa)
6636                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6637
6638         if (INTEL_GEN(dev_priv) >= 9)
6639                 skylake_pfit_enable(new_crtc_state);
6640         else
6641                 ironlake_pfit_enable(new_crtc_state);
6642
6643         /*
6644          * On ILK+ LUT must be loaded before the pipe is running but with
6645          * clocks enabled
6646          */
6647         intel_color_load_luts(new_crtc_state);
6648         intel_color_commit(new_crtc_state);
6649         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6650         if (INTEL_GEN(dev_priv) < 9)
6651                 intel_disable_primary_plane(new_crtc_state);
6652
6653         if (INTEL_GEN(dev_priv) >= 11)
6654                 icl_set_pipe_chicken(crtc);
6655
6656         if (!transcoder_is_dsi(cpu_transcoder))
6657                 intel_ddi_enable_transcoder_func(new_crtc_state);
6658
6659         if (dev_priv->display.initial_watermarks)
6660                 dev_priv->display.initial_watermarks(state, crtc);
6661
6662         if (INTEL_GEN(dev_priv) >= 11)
6663                 icl_pipe_mbus_enable(crtc);
6664
6665         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6666         if (!transcoder_is_dsi(cpu_transcoder))
6667                 intel_enable_pipe(new_crtc_state);
6668
6669         if (new_crtc_state->has_pch_encoder)
6670                 lpt_pch_enable(state, new_crtc_state);
6671
6672         intel_crtc_vblank_on(new_crtc_state);
6673
6674         intel_encoders_enable(state, crtc);
6675
6676         if (psl_clkgate_wa) {
6677                 intel_wait_for_vblank(dev_priv, pipe);
6678                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6679         }
6680
6681         /* If we change the relative order between pipe/planes enabling, we need
6682          * to change the workaround. */
6683         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
6684         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6685                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6686                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6687         }
6688 }
6689
6690 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6691 {
6692         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6693         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6694         enum pipe pipe = crtc->pipe;
6695
6696         /* To avoid upsetting the power well on haswell only disable the pfit if
6697          * it's in use. The hw state code will make sure we get this right. */
6698         if (old_crtc_state->pch_pfit.enabled) {
6699                 I915_WRITE(PF_CTL(pipe), 0);
6700                 I915_WRITE(PF_WIN_POS(pipe), 0);
6701                 I915_WRITE(PF_WIN_SZ(pipe), 0);
6702         }
6703 }
6704
6705 static void ironlake_crtc_disable(struct intel_atomic_state *state,
6706                                   struct intel_crtc *crtc)
6707 {
6708         const struct intel_crtc_state *old_crtc_state =
6709                 intel_atomic_get_old_crtc_state(state, crtc);
6710         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6711         enum pipe pipe = crtc->pipe;
6712
6713         /*
6714          * Sometimes spurious CPU pipe underruns happen when the
6715          * pipe is already disabled, but FDI RX/TX is still enabled.
6716          * Happens at least with VGA+HDMI cloning. Suppress them.
6717          */
6718         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6719         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6720
6721         intel_encoders_disable(state, crtc);
6722
6723         intel_crtc_vblank_off(crtc);
6724
6725         intel_disable_pipe(old_crtc_state);
6726
6727         ironlake_pfit_disable(old_crtc_state);
6728
6729         if (old_crtc_state->has_pch_encoder)
6730                 ironlake_fdi_disable(crtc);
6731
6732         intel_encoders_post_disable(state, crtc);
6733
6734         if (old_crtc_state->has_pch_encoder) {
6735                 ironlake_disable_pch_transcoder(dev_priv, pipe);
6736
6737                 if (HAS_PCH_CPT(dev_priv)) {
6738                         i915_reg_t reg;
6739                         u32 temp;
6740
6741                         /* disable TRANS_DP_CTL */
6742                         reg = TRANS_DP_CTL(pipe);
6743                         temp = I915_READ(reg);
6744                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6745                                   TRANS_DP_PORT_SEL_MASK);
6746                         temp |= TRANS_DP_PORT_SEL_NONE;
6747                         I915_WRITE(reg, temp);
6748
6749                         /* disable DPLL_SEL */
6750                         temp = I915_READ(PCH_DPLL_SEL);
6751                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6752                         I915_WRITE(PCH_DPLL_SEL, temp);
6753                 }
6754
6755                 ironlake_fdi_pll_disable(crtc);
6756         }
6757
6758         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6759         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6760 }
6761
6762 static void haswell_crtc_disable(struct intel_atomic_state *state,
6763                                  struct intel_crtc *crtc)
6764 {
6765         const struct intel_crtc_state *old_crtc_state =
6766                 intel_atomic_get_old_crtc_state(state, crtc);
6767         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6768         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6769
6770         intel_encoders_disable(state, crtc);
6771
6772         intel_crtc_vblank_off(crtc);
6773
6774         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6775         if (!transcoder_is_dsi(cpu_transcoder))
6776                 intel_disable_pipe(old_crtc_state);
6777
6778         if (INTEL_GEN(dev_priv) >= 11)
6779                 icl_disable_transcoder_port_sync(old_crtc_state);
6780
6781         if (!transcoder_is_dsi(cpu_transcoder))
6782                 intel_ddi_disable_transcoder_func(old_crtc_state);
6783
6784         intel_dsc_disable(old_crtc_state);
6785
6786         if (INTEL_GEN(dev_priv) >= 9)
6787                 skylake_scaler_disable(crtc);
6788         else
6789                 ironlake_pfit_disable(old_crtc_state);
6790
6791         intel_encoders_post_disable(state, crtc);
6792
6793         intel_encoders_post_pll_disable(state, crtc);
6794 }
6795
6796 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6797 {
6798         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6799         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6800
6801         if (!crtc_state->gmch_pfit.control)
6802                 return;
6803
6804         /*
6805          * The panel fitter should only be adjusted whilst the pipe is disabled,
6806          * according to register description and PRM.
6807          */
6808         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6809         assert_pipe_disabled(dev_priv, crtc->pipe);
6810
6811         I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6812         I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6813
6814         /* Border color in case we don't scale up to the full screen. Black by
6815          * default, change to something else for debugging. */
6816         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6817 }
6818
6819 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6820 {
6821         if (phy == PHY_NONE)
6822                 return false;
6823
6824         if (IS_ELKHARTLAKE(dev_priv))
6825                 return phy <= PHY_C;
6826
6827         if (INTEL_GEN(dev_priv) >= 11)
6828                 return phy <= PHY_B;
6829
6830         return false;
6831 }
6832
6833 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6834 {
6835         if (INTEL_GEN(dev_priv) >= 12)
6836                 return phy >= PHY_D && phy <= PHY_I;
6837
6838         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6839                 return phy >= PHY_C && phy <= PHY_F;
6840
6841         return false;
6842 }
6843
6844 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6845 {
6846         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6847                 return PHY_A;
6848
6849         return (enum phy)port;
6850 }
6851
6852 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6853 {
6854         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6855                 return PORT_TC_NONE;
6856
6857         if (INTEL_GEN(dev_priv) >= 12)
6858                 return port - PORT_D;
6859
6860         return port - PORT_C;
6861 }
6862
6863 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6864 {
6865         switch (port) {
6866         case PORT_A:
6867                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6868         case PORT_B:
6869                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6870         case PORT_C:
6871                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6872         case PORT_D:
6873                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6874         case PORT_E:
6875                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6876         case PORT_F:
6877                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6878         case PORT_G:
6879                 return POWER_DOMAIN_PORT_DDI_G_LANES;
6880         default:
6881                 MISSING_CASE(port);
6882                 return POWER_DOMAIN_PORT_OTHER;
6883         }
6884 }
6885
6886 enum intel_display_power_domain
6887 intel_aux_power_domain(struct intel_digital_port *dig_port)
6888 {
6889         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6890         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6891
6892         if (intel_phy_is_tc(dev_priv, phy) &&
6893             dig_port->tc_mode == TC_PORT_TBT_ALT) {
6894                 switch (dig_port->aux_ch) {
6895                 case AUX_CH_C:
6896                         return POWER_DOMAIN_AUX_C_TBT;
6897                 case AUX_CH_D:
6898                         return POWER_DOMAIN_AUX_D_TBT;
6899                 case AUX_CH_E:
6900                         return POWER_DOMAIN_AUX_E_TBT;
6901                 case AUX_CH_F:
6902                         return POWER_DOMAIN_AUX_F_TBT;
6903                 case AUX_CH_G:
6904                         return POWER_DOMAIN_AUX_G_TBT;
6905                 default:
6906                         MISSING_CASE(dig_port->aux_ch);
6907                         return POWER_DOMAIN_AUX_C_TBT;
6908                 }
6909         }
6910
6911         switch (dig_port->aux_ch) {
6912         case AUX_CH_A:
6913                 return POWER_DOMAIN_AUX_A;
6914         case AUX_CH_B:
6915                 return POWER_DOMAIN_AUX_B;
6916         case AUX_CH_C:
6917                 return POWER_DOMAIN_AUX_C;
6918         case AUX_CH_D:
6919                 return POWER_DOMAIN_AUX_D;
6920         case AUX_CH_E:
6921                 return POWER_DOMAIN_AUX_E;
6922         case AUX_CH_F:
6923                 return POWER_DOMAIN_AUX_F;
6924         case AUX_CH_G:
6925                 return POWER_DOMAIN_AUX_G;
6926         default:
6927                 MISSING_CASE(dig_port->aux_ch);
6928                 return POWER_DOMAIN_AUX_A;
6929         }
6930 }
6931
6932 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6933 {
6934         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6935         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6936         struct drm_encoder *encoder;
6937         enum pipe pipe = crtc->pipe;
6938         u64 mask;
6939         enum transcoder transcoder = crtc_state->cpu_transcoder;
6940
6941         if (!crtc_state->hw.active)
6942                 return 0;
6943
6944         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6945         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6946         if (crtc_state->pch_pfit.enabled ||
6947             crtc_state->pch_pfit.force_thru)
6948                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6949
6950         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6951                                   crtc_state->uapi.encoder_mask) {
6952                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6953
6954                 mask |= BIT_ULL(intel_encoder->power_domain);
6955         }
6956
6957         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6958                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6959
6960         if (crtc_state->shared_dpll)
6961                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6962
6963         return mask;
6964 }
6965
6966 static u64
6967 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6968 {
6969         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6970         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6971         enum intel_display_power_domain domain;
6972         u64 domains, new_domains, old_domains;
6973
6974         old_domains = crtc->enabled_power_domains;
6975         crtc->enabled_power_domains = new_domains =
6976                 get_crtc_power_domains(crtc_state);
6977
6978         domains = new_domains & ~old_domains;
6979
6980         for_each_power_domain(domain, domains)
6981                 intel_display_power_get(dev_priv, domain);
6982
6983         return old_domains & ~new_domains;
6984 }
6985
6986 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6987                                       u64 domains)
6988 {
6989         enum intel_display_power_domain domain;
6990
6991         for_each_power_domain(domain, domains)
6992                 intel_display_power_put_unchecked(dev_priv, domain);
6993 }
6994
6995 static void valleyview_crtc_enable(struct intel_atomic_state *state,
6996                                    struct intel_crtc *crtc)
6997 {
6998         const struct intel_crtc_state *new_crtc_state =
6999                 intel_atomic_get_new_crtc_state(state, crtc);
7000         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7001         enum pipe pipe = crtc->pipe;
7002
7003         if (WARN_ON(crtc->active))
7004                 return;
7005
7006         if (intel_crtc_has_dp_encoder(new_crtc_state))
7007                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7008
7009         intel_set_pipe_timings(new_crtc_state);
7010         intel_set_pipe_src_size(new_crtc_state);
7011
7012         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7013                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7014                 I915_WRITE(CHV_CANVAS(pipe), 0);
7015         }
7016
7017         i9xx_set_pipeconf(new_crtc_state);
7018
7019         crtc->active = true;
7020
7021         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7022
7023         intel_encoders_pre_pll_enable(state, crtc);
7024
7025         if (IS_CHERRYVIEW(dev_priv)) {
7026                 chv_prepare_pll(crtc, new_crtc_state);
7027                 chv_enable_pll(crtc, new_crtc_state);
7028         } else {
7029                 vlv_prepare_pll(crtc, new_crtc_state);
7030                 vlv_enable_pll(crtc, new_crtc_state);
7031         }
7032
7033         intel_encoders_pre_enable(state, crtc);
7034
7035         i9xx_pfit_enable(new_crtc_state);
7036
7037         intel_color_load_luts(new_crtc_state);
7038         intel_color_commit(new_crtc_state);
7039         /* update DSPCNTR to configure gamma for pipe bottom color */
7040         intel_disable_primary_plane(new_crtc_state);
7041
7042         dev_priv->display.initial_watermarks(state, crtc);
7043         intel_enable_pipe(new_crtc_state);
7044
7045         intel_crtc_vblank_on(new_crtc_state);
7046
7047         intel_encoders_enable(state, crtc);
7048 }
7049
7050 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7051 {
7052         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7053         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7054
7055         I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
7056         I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
7057 }
7058
7059 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7060                              struct intel_crtc *crtc)
7061 {
7062         const struct intel_crtc_state *new_crtc_state =
7063                 intel_atomic_get_new_crtc_state(state, crtc);
7064         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7065         enum pipe pipe = crtc->pipe;
7066
7067         if (WARN_ON(crtc->active))
7068                 return;
7069
7070         i9xx_set_pll_dividers(new_crtc_state);
7071
7072         if (intel_crtc_has_dp_encoder(new_crtc_state))
7073                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7074
7075         intel_set_pipe_timings(new_crtc_state);
7076         intel_set_pipe_src_size(new_crtc_state);
7077
7078         i9xx_set_pipeconf(new_crtc_state);
7079
7080         crtc->active = true;
7081
7082         if (!IS_GEN(dev_priv, 2))
7083                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7084
7085         intel_encoders_pre_enable(state, crtc);
7086
7087         i9xx_enable_pll(crtc, new_crtc_state);
7088
7089         i9xx_pfit_enable(new_crtc_state);
7090
7091         intel_color_load_luts(new_crtc_state);
7092         intel_color_commit(new_crtc_state);
7093         /* update DSPCNTR to configure gamma for pipe bottom color */
7094         intel_disable_primary_plane(new_crtc_state);
7095
7096         if (dev_priv->display.initial_watermarks)
7097                 dev_priv->display.initial_watermarks(state, crtc);
7098         else
7099                 intel_update_watermarks(crtc);
7100         intel_enable_pipe(new_crtc_state);
7101
7102         intel_crtc_vblank_on(new_crtc_state);
7103
7104         intel_encoders_enable(state, crtc);
7105 }
7106
7107 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7108 {
7109         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7110         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7111
7112         if (!old_crtc_state->gmch_pfit.control)
7113                 return;
7114
7115         assert_pipe_disabled(dev_priv, crtc->pipe);
7116
7117         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
7118                       I915_READ(PFIT_CONTROL));
7119         I915_WRITE(PFIT_CONTROL, 0);
7120 }
7121
7122 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7123                               struct intel_crtc *crtc)
7124 {
7125         struct intel_crtc_state *old_crtc_state =
7126                 intel_atomic_get_old_crtc_state(state, crtc);
7127         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7128         enum pipe pipe = crtc->pipe;
7129
7130         /*
7131          * On gen2 planes are double buffered but the pipe isn't, so we must
7132          * wait for planes to fully turn off before disabling the pipe.
7133          */
7134         if (IS_GEN(dev_priv, 2))
7135                 intel_wait_for_vblank(dev_priv, pipe);
7136
7137         intel_encoders_disable(state, crtc);
7138
7139         intel_crtc_vblank_off(crtc);
7140
7141         intel_disable_pipe(old_crtc_state);
7142
7143         i9xx_pfit_disable(old_crtc_state);
7144
7145         intel_encoders_post_disable(state, crtc);
7146
7147         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7148                 if (IS_CHERRYVIEW(dev_priv))
7149                         chv_disable_pll(dev_priv, pipe);
7150                 else if (IS_VALLEYVIEW(dev_priv))
7151                         vlv_disable_pll(dev_priv, pipe);
7152                 else
7153                         i9xx_disable_pll(old_crtc_state);
7154         }
7155
7156         intel_encoders_post_pll_disable(state, crtc);
7157
7158         if (!IS_GEN(dev_priv, 2))
7159                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7160
7161         if (!dev_priv->display.initial_watermarks)
7162                 intel_update_watermarks(crtc);
7163
7164         /* clock the pipe down to 640x480@60 to potentially save power */
7165         if (IS_I830(dev_priv))
7166                 i830_enable_pipe(dev_priv, pipe);
7167 }
7168
7169 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7170                                         struct drm_modeset_acquire_ctx *ctx)
7171 {
7172         struct intel_encoder *encoder;
7173         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7174         struct intel_bw_state *bw_state =
7175                 to_intel_bw_state(dev_priv->bw_obj.state);
7176         struct intel_crtc_state *crtc_state =
7177                 to_intel_crtc_state(crtc->base.state);
7178         enum intel_display_power_domain domain;
7179         struct intel_plane *plane;
7180         struct drm_atomic_state *state;
7181         struct intel_crtc_state *temp_crtc_state;
7182         enum pipe pipe = crtc->pipe;
7183         u64 domains;
7184         int ret;
7185
7186         if (!crtc_state->hw.active)
7187                 return;
7188
7189         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7190                 const struct intel_plane_state *plane_state =
7191                         to_intel_plane_state(plane->base.state);
7192
7193                 if (plane_state->uapi.visible)
7194                         intel_plane_disable_noatomic(crtc, plane);
7195         }
7196
7197         state = drm_atomic_state_alloc(&dev_priv->drm);
7198         if (!state) {
7199                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7200                               crtc->base.base.id, crtc->base.name);
7201                 return;
7202         }
7203
7204         state->acquire_ctx = ctx;
7205
7206         /* Everything's already locked, -EDEADLK can't happen. */
7207         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7208         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7209
7210         WARN_ON(IS_ERR(temp_crtc_state) || ret);
7211
7212         dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7213
7214         drm_atomic_state_put(state);
7215
7216         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7217                       crtc->base.base.id, crtc->base.name);
7218
7219         crtc->active = false;
7220         crtc->base.enabled = false;
7221
7222         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7223         crtc_state->uapi.active = false;
7224         crtc_state->uapi.connector_mask = 0;
7225         crtc_state->uapi.encoder_mask = 0;
7226         intel_crtc_free_hw_state(crtc_state);
7227         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7228
7229         for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7230                 encoder->base.crtc = NULL;
7231
7232         intel_fbc_disable(crtc);
7233         intel_update_watermarks(crtc);
7234         intel_disable_shared_dpll(crtc_state);
7235
7236         domains = crtc->enabled_power_domains;
7237         for_each_power_domain(domain, domains)
7238                 intel_display_power_put_unchecked(dev_priv, domain);
7239         crtc->enabled_power_domains = 0;
7240
7241         dev_priv->active_pipes &= ~BIT(pipe);
7242         dev_priv->min_cdclk[pipe] = 0;
7243         dev_priv->min_voltage_level[pipe] = 0;
7244
7245         bw_state->data_rate[pipe] = 0;
7246         bw_state->num_active_planes[pipe] = 0;
7247 }
7248
7249 /*
7250  * turn all crtc's off, but do not adjust state
7251  * This has to be paired with a call to intel_modeset_setup_hw_state.
7252  */
7253 int intel_display_suspend(struct drm_device *dev)
7254 {
7255         struct drm_i915_private *dev_priv = to_i915(dev);
7256         struct drm_atomic_state *state;
7257         int ret;
7258
7259         state = drm_atomic_helper_suspend(dev);
7260         ret = PTR_ERR_OR_ZERO(state);
7261         if (ret)
7262                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7263         else
7264                 dev_priv->modeset_restore_state = state;
7265         return ret;
7266 }
7267
7268 void intel_encoder_destroy(struct drm_encoder *encoder)
7269 {
7270         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7271
7272         drm_encoder_cleanup(encoder);
7273         kfree(intel_encoder);
7274 }
7275
7276 /* Cross check the actual hw state with our own modeset state tracking (and it's
7277  * internal consistency). */
7278 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7279                                          struct drm_connector_state *conn_state)
7280 {
7281         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7282
7283         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7284                       connector->base.base.id,
7285                       connector->base.name);
7286
7287         if (connector->get_hw_state(connector)) {
7288                 struct intel_encoder *encoder = connector->encoder;
7289
7290                 I915_STATE_WARN(!crtc_state,
7291                          "connector enabled without attached crtc\n");
7292
7293                 if (!crtc_state)
7294                         return;
7295
7296                 I915_STATE_WARN(!crtc_state->hw.active,
7297                                 "connector is active, but attached crtc isn't\n");
7298
7299                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7300                         return;
7301
7302                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7303                         "atomic encoder doesn't match attached encoder\n");
7304
7305                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7306                         "attached encoder crtc differs from connector crtc\n");
7307         } else {
7308                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7309                                 "attached crtc is active, but connector isn't\n");
7310                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7311                         "best encoder set without crtc!\n");
7312         }
7313 }
7314
7315 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7316 {
7317         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7318                 return crtc_state->fdi_lanes;
7319
7320         return 0;
7321 }
7322
7323 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7324                                      struct intel_crtc_state *pipe_config)
7325 {
7326         struct drm_i915_private *dev_priv = to_i915(dev);
7327         struct drm_atomic_state *state = pipe_config->uapi.state;
7328         struct intel_crtc *other_crtc;
7329         struct intel_crtc_state *other_crtc_state;
7330
7331         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7332                       pipe_name(pipe), pipe_config->fdi_lanes);
7333         if (pipe_config->fdi_lanes > 4) {
7334                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7335                               pipe_name(pipe), pipe_config->fdi_lanes);
7336                 return -EINVAL;
7337         }
7338
7339         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7340                 if (pipe_config->fdi_lanes > 2) {
7341                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7342                                       pipe_config->fdi_lanes);
7343                         return -EINVAL;
7344                 } else {
7345                         return 0;
7346                 }
7347         }
7348
7349         if (INTEL_NUM_PIPES(dev_priv) == 2)
7350                 return 0;
7351
7352         /* Ivybridge 3 pipe is really complicated */
7353         switch (pipe) {
7354         case PIPE_A:
7355                 return 0;
7356         case PIPE_B:
7357                 if (pipe_config->fdi_lanes <= 2)
7358                         return 0;
7359
7360                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7361                 other_crtc_state =
7362                         intel_atomic_get_crtc_state(state, other_crtc);
7363                 if (IS_ERR(other_crtc_state))
7364                         return PTR_ERR(other_crtc_state);
7365
7366                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7367                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7368                                       pipe_name(pipe), pipe_config->fdi_lanes);
7369                         return -EINVAL;
7370                 }
7371                 return 0;
7372         case PIPE_C:
7373                 if (pipe_config->fdi_lanes > 2) {
7374                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7375                                       pipe_name(pipe), pipe_config->fdi_lanes);
7376                         return -EINVAL;
7377                 }
7378
7379                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7380                 other_crtc_state =
7381                         intel_atomic_get_crtc_state(state, other_crtc);
7382                 if (IS_ERR(other_crtc_state))
7383                         return PTR_ERR(other_crtc_state);
7384
7385                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7386                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7387                         return -EINVAL;
7388                 }
7389                 return 0;
7390         default:
7391                 BUG();
7392         }
7393 }
7394
7395 #define RETRY 1
7396 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7397                                        struct intel_crtc_state *pipe_config)
7398 {
7399         struct drm_device *dev = intel_crtc->base.dev;
7400         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7401         int lane, link_bw, fdi_dotclock, ret;
7402         bool needs_recompute = false;
7403
7404 retry:
7405         /* FDI is a binary signal running at ~2.7GHz, encoding
7406          * each output octet as 10 bits. The actual frequency
7407          * is stored as a divider into a 100MHz clock, and the
7408          * mode pixel clock is stored in units of 1KHz.
7409          * Hence the bw of each lane in terms of the mode signal
7410          * is:
7411          */
7412         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7413
7414         fdi_dotclock = adjusted_mode->crtc_clock;
7415
7416         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7417                                            pipe_config->pipe_bpp);
7418
7419         pipe_config->fdi_lanes = lane;
7420
7421         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7422                                link_bw, &pipe_config->fdi_m_n, false, false);
7423
7424         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7425         if (ret == -EDEADLK)
7426                 return ret;
7427
7428         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7429                 pipe_config->pipe_bpp -= 2*3;
7430                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7431                               pipe_config->pipe_bpp);
7432                 needs_recompute = true;
7433                 pipe_config->bw_constrained = true;
7434
7435                 goto retry;
7436         }
7437
7438         if (needs_recompute)
7439                 return RETRY;
7440
7441         return ret;
7442 }
7443
7444 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7445 {
7446         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7447         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7448
7449         /* IPS only exists on ULT machines and is tied to pipe A. */
7450         if (!hsw_crtc_supports_ips(crtc))
7451                 return false;
7452
7453         if (!i915_modparams.enable_ips)
7454                 return false;
7455
7456         if (crtc_state->pipe_bpp > 24)
7457                 return false;
7458
7459         /*
7460          * We compare against max which means we must take
7461          * the increased cdclk requirement into account when
7462          * calculating the new cdclk.
7463          *
7464          * Should measure whether using a lower cdclk w/o IPS
7465          */
7466         if (IS_BROADWELL(dev_priv) &&
7467             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7468                 return false;
7469
7470         return true;
7471 }
7472
7473 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7474 {
7475         struct drm_i915_private *dev_priv =
7476                 to_i915(crtc_state->uapi.crtc->dev);
7477         struct intel_atomic_state *intel_state =
7478                 to_intel_atomic_state(crtc_state->uapi.state);
7479
7480         if (!hsw_crtc_state_ips_capable(crtc_state))
7481                 return false;
7482
7483         /*
7484          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7485          * enabled and disabled dynamically based on package C states,
7486          * user space can't make reliable use of the CRCs, so let's just
7487          * completely disable it.
7488          */
7489         if (crtc_state->crc_enabled)
7490                 return false;
7491
7492         /* IPS should be fine as long as at least one plane is enabled. */
7493         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7494                 return false;
7495
7496         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7497         if (IS_BROADWELL(dev_priv) &&
7498             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7499                 return false;
7500
7501         return true;
7502 }
7503
7504 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7505 {
7506         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7507
7508         /* GDG double wide on either pipe, otherwise pipe A only */
7509         return INTEL_GEN(dev_priv) < 4 &&
7510                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7511 }
7512
7513 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7514 {
7515         u32 pixel_rate;
7516
7517         pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7518
7519         /*
7520          * We only use IF-ID interlacing. If we ever use
7521          * PF-ID we'll need to adjust the pixel_rate here.
7522          */
7523
7524         if (pipe_config->pch_pfit.enabled) {
7525                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7526                 u32 pfit_size = pipe_config->pch_pfit.size;
7527
7528                 pipe_w = pipe_config->pipe_src_w;
7529                 pipe_h = pipe_config->pipe_src_h;
7530
7531                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7532                 pfit_h = pfit_size & 0xFFFF;
7533                 if (pipe_w < pfit_w)
7534                         pipe_w = pfit_w;
7535                 if (pipe_h < pfit_h)
7536                         pipe_h = pfit_h;
7537
7538                 if (WARN_ON(!pfit_w || !pfit_h))
7539                         return pixel_rate;
7540
7541                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7542                                      pfit_w * pfit_h);
7543         }
7544
7545         return pixel_rate;
7546 }
7547
7548 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7549 {
7550         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7551
7552         if (HAS_GMCH(dev_priv))
7553                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7554                 crtc_state->pixel_rate =
7555                         crtc_state->hw.adjusted_mode.crtc_clock;
7556         else
7557                 crtc_state->pixel_rate =
7558                         ilk_pipe_pixel_rate(crtc_state);
7559 }
7560
7561 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7562                                      struct intel_crtc_state *pipe_config)
7563 {
7564         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7565         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7566         int clock_limit = dev_priv->max_dotclk_freq;
7567
7568         if (INTEL_GEN(dev_priv) < 4) {
7569                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7570
7571                 /*
7572                  * Enable double wide mode when the dot clock
7573                  * is > 90% of the (display) core speed.
7574                  */
7575                 if (intel_crtc_supports_double_wide(crtc) &&
7576                     adjusted_mode->crtc_clock > clock_limit) {
7577                         clock_limit = dev_priv->max_dotclk_freq;
7578                         pipe_config->double_wide = true;
7579                 }
7580         }
7581
7582         if (adjusted_mode->crtc_clock > clock_limit) {
7583                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7584                               adjusted_mode->crtc_clock, clock_limit,
7585                               yesno(pipe_config->double_wide));
7586                 return -EINVAL;
7587         }
7588
7589         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7590              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7591              pipe_config->hw.ctm) {
7592                 /*
7593                  * There is only one pipe CSC unit per pipe, and we need that
7594                  * for output conversion from RGB->YCBCR. So if CTM is already
7595                  * applied we can't support YCBCR420 output.
7596                  */
7597                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7598                 return -EINVAL;
7599         }
7600
7601         /*
7602          * Pipe horizontal size must be even in:
7603          * - DVO ganged mode
7604          * - LVDS dual channel mode
7605          * - Double wide pipe
7606          */
7607         if (pipe_config->pipe_src_w & 1) {
7608                 if (pipe_config->double_wide) {
7609                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7610                         return -EINVAL;
7611                 }
7612
7613                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7614                     intel_is_dual_link_lvds(dev_priv)) {
7615                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7616                         return -EINVAL;
7617                 }
7618         }
7619
7620         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7621          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7622          */
7623         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7624                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7625                 return -EINVAL;
7626
7627         intel_crtc_compute_pixel_rate(pipe_config);
7628
7629         if (pipe_config->has_pch_encoder)
7630                 return ironlake_fdi_compute_config(crtc, pipe_config);
7631
7632         return 0;
7633 }
7634
7635 static void
7636 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7637 {
7638         while (*num > DATA_LINK_M_N_MASK ||
7639                *den > DATA_LINK_M_N_MASK) {
7640                 *num >>= 1;
7641                 *den >>= 1;
7642         }
7643 }
7644
7645 static void compute_m_n(unsigned int m, unsigned int n,
7646                         u32 *ret_m, u32 *ret_n,
7647                         bool constant_n)
7648 {
7649         /*
7650          * Several DP dongles in particular seem to be fussy about
7651          * too large link M/N values. Give N value as 0x8000 that
7652          * should be acceptable by specific devices. 0x8000 is the
7653          * specified fixed N value for asynchronous clock mode,
7654          * which the devices expect also in synchronous clock mode.
7655          */
7656         if (constant_n)
7657                 *ret_n = 0x8000;
7658         else
7659                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7660
7661         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7662         intel_reduce_m_n_ratio(ret_m, ret_n);
7663 }
7664
7665 void
7666 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7667                        int pixel_clock, int link_clock,
7668                        struct intel_link_m_n *m_n,
7669                        bool constant_n, bool fec_enable)
7670 {
7671         u32 data_clock = bits_per_pixel * pixel_clock;
7672
7673         if (fec_enable)
7674                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
7675
7676         m_n->tu = 64;
7677         compute_m_n(data_clock,
7678                     link_clock * nlanes * 8,
7679                     &m_n->gmch_m, &m_n->gmch_n,
7680                     constant_n);
7681
7682         compute_m_n(pixel_clock, link_clock,
7683                     &m_n->link_m, &m_n->link_n,
7684                     constant_n);
7685 }
7686
7687 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
7688 {
7689         /*
7690          * There may be no VBT; and if the BIOS enabled SSC we can
7691          * just keep using it to avoid unnecessary flicker.  Whereas if the
7692          * BIOS isn't using it, don't assume it will work even if the VBT
7693          * indicates as much.
7694          */
7695         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7696                 bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) &
7697                         DREF_SSC1_ENABLE;
7698
7699                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
7700                         DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n",
7701                                       enableddisabled(bios_lvds_use_ssc),
7702                                       enableddisabled(dev_priv->vbt.lvds_use_ssc));
7703                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
7704                 }
7705         }
7706 }
7707
7708 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7709 {
7710         if (i915_modparams.panel_use_ssc >= 0)
7711                 return i915_modparams.panel_use_ssc != 0;
7712         return dev_priv->vbt.lvds_use_ssc
7713                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7714 }
7715
7716 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7717 {
7718         return (1 << dpll->n) << 16 | dpll->m2;
7719 }
7720
7721 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7722 {
7723         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7724 }
7725
7726 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7727                                      struct intel_crtc_state *crtc_state,
7728                                      struct dpll *reduced_clock)
7729 {
7730         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7731         u32 fp, fp2 = 0;
7732
7733         if (IS_PINEVIEW(dev_priv)) {
7734                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7735                 if (reduced_clock)
7736                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7737         } else {
7738                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7739                 if (reduced_clock)
7740                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7741         }
7742
7743         crtc_state->dpll_hw_state.fp0 = fp;
7744
7745         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7746             reduced_clock) {
7747                 crtc_state->dpll_hw_state.fp1 = fp2;
7748         } else {
7749                 crtc_state->dpll_hw_state.fp1 = fp;
7750         }
7751 }
7752
7753 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7754                 pipe)
7755 {
7756         u32 reg_val;
7757
7758         /*
7759          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7760          * and set it to a reasonable value instead.
7761          */
7762         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7763         reg_val &= 0xffffff00;
7764         reg_val |= 0x00000030;
7765         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7766
7767         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7768         reg_val &= 0x00ffffff;
7769         reg_val |= 0x8c000000;
7770         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7771
7772         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7773         reg_val &= 0xffffff00;
7774         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7775
7776         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7777         reg_val &= 0x00ffffff;
7778         reg_val |= 0xb0000000;
7779         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7780 }
7781
7782 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7783                                          const struct intel_link_m_n *m_n)
7784 {
7785         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7786         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7787         enum pipe pipe = crtc->pipe;
7788
7789         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7790         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7791         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7792         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7793 }
7794
7795 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7796                                  enum transcoder transcoder)
7797 {
7798         if (IS_HASWELL(dev_priv))
7799                 return transcoder == TRANSCODER_EDP;
7800
7801         /*
7802          * Strictly speaking some registers are available before
7803          * gen7, but we only support DRRS on gen7+
7804          */
7805         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7806 }
7807
7808 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7809                                          const struct intel_link_m_n *m_n,
7810                                          const struct intel_link_m_n *m2_n2)
7811 {
7812         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7813         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7814         enum pipe pipe = crtc->pipe;
7815         enum transcoder transcoder = crtc_state->cpu_transcoder;
7816
7817         if (INTEL_GEN(dev_priv) >= 5) {
7818                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7819                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7820                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7821                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7822                 /*
7823                  *  M2_N2 registers are set only if DRRS is supported
7824                  * (to make sure the registers are not unnecessarily accessed).
7825                  */
7826                 if (m2_n2 && crtc_state->has_drrs &&
7827                     transcoder_has_m2_n2(dev_priv, transcoder)) {
7828                         I915_WRITE(PIPE_DATA_M2(transcoder),
7829                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7830                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7831                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7832                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7833                 }
7834         } else {
7835                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7836                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7837                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7838                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7839         }
7840 }
7841
7842 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7843 {
7844         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7845
7846         if (m_n == M1_N1) {
7847                 dp_m_n = &crtc_state->dp_m_n;
7848                 dp_m2_n2 = &crtc_state->dp_m2_n2;
7849         } else if (m_n == M2_N2) {
7850
7851                 /*
7852                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7853                  * needs to be programmed into M1_N1.
7854                  */
7855                 dp_m_n = &crtc_state->dp_m2_n2;
7856         } else {
7857                 DRM_ERROR("Unsupported divider value\n");
7858                 return;
7859         }
7860
7861         if (crtc_state->has_pch_encoder)
7862                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7863         else
7864                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7865 }
7866
7867 static void vlv_compute_dpll(struct intel_crtc *crtc,
7868                              struct intel_crtc_state *pipe_config)
7869 {
7870         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7871                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7872         if (crtc->pipe != PIPE_A)
7873                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7874
7875         /* DPLL not used with DSI, but still need the rest set up */
7876         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7877                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7878                         DPLL_EXT_BUFFER_ENABLE_VLV;
7879
7880         pipe_config->dpll_hw_state.dpll_md =
7881                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7882 }
7883
7884 static void chv_compute_dpll(struct intel_crtc *crtc,
7885                              struct intel_crtc_state *pipe_config)
7886 {
7887         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7888                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7889         if (crtc->pipe != PIPE_A)
7890                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7891
7892         /* DPLL not used with DSI, but still need the rest set up */
7893         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7894                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7895
7896         pipe_config->dpll_hw_state.dpll_md =
7897                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7898 }
7899
7900 static void vlv_prepare_pll(struct intel_crtc *crtc,
7901                             const struct intel_crtc_state *pipe_config)
7902 {
7903         struct drm_device *dev = crtc->base.dev;
7904         struct drm_i915_private *dev_priv = to_i915(dev);
7905         enum pipe pipe = crtc->pipe;
7906         u32 mdiv;
7907         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7908         u32 coreclk, reg_val;
7909
7910         /* Enable Refclk */
7911         I915_WRITE(DPLL(pipe),
7912                    pipe_config->dpll_hw_state.dpll &
7913                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7914
7915         /* No need to actually set up the DPLL with DSI */
7916         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7917                 return;
7918
7919         vlv_dpio_get(dev_priv);
7920
7921         bestn = pipe_config->dpll.n;
7922         bestm1 = pipe_config->dpll.m1;
7923         bestm2 = pipe_config->dpll.m2;
7924         bestp1 = pipe_config->dpll.p1;
7925         bestp2 = pipe_config->dpll.p2;
7926
7927         /* See eDP HDMI DPIO driver vbios notes doc */
7928
7929         /* PLL B needs special handling */
7930         if (pipe == PIPE_B)
7931                 vlv_pllb_recal_opamp(dev_priv, pipe);
7932
7933         /* Set up Tx target for periodic Rcomp update */
7934         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7935
7936         /* Disable target IRef on PLL */
7937         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7938         reg_val &= 0x00ffffff;
7939         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7940
7941         /* Disable fast lock */
7942         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7943
7944         /* Set idtafcrecal before PLL is enabled */
7945         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7946         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7947         mdiv |= ((bestn << DPIO_N_SHIFT));
7948         mdiv |= (1 << DPIO_K_SHIFT);
7949
7950         /*
7951          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7952          * but we don't support that).
7953          * Note: don't use the DAC post divider as it seems unstable.
7954          */
7955         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7956         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7957
7958         mdiv |= DPIO_ENABLE_CALIBRATION;
7959         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7960
7961         /* Set HBR and RBR LPF coefficients */
7962         if (pipe_config->port_clock == 162000 ||
7963             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7964             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7965                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7966                                  0x009f0003);
7967         else
7968                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7969                                  0x00d0000f);
7970
7971         if (intel_crtc_has_dp_encoder(pipe_config)) {
7972                 /* Use SSC source */
7973                 if (pipe == PIPE_A)
7974                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7975                                          0x0df40000);
7976                 else
7977                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7978                                          0x0df70000);
7979         } else { /* HDMI or VGA */
7980                 /* Use bend source */
7981                 if (pipe == PIPE_A)
7982                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7983                                          0x0df70000);
7984                 else
7985                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7986                                          0x0df40000);
7987         }
7988
7989         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7990         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7991         if (intel_crtc_has_dp_encoder(pipe_config))
7992                 coreclk |= 0x01000000;
7993         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7994
7995         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7996
7997         vlv_dpio_put(dev_priv);
7998 }
7999
8000 static void chv_prepare_pll(struct intel_crtc *crtc,
8001                             const struct intel_crtc_state *pipe_config)
8002 {
8003         struct drm_device *dev = crtc->base.dev;
8004         struct drm_i915_private *dev_priv = to_i915(dev);
8005         enum pipe pipe = crtc->pipe;
8006         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8007         u32 loopfilter, tribuf_calcntr;
8008         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8009         u32 dpio_val;
8010         int vco;
8011
8012         /* Enable Refclk and SSC */
8013         I915_WRITE(DPLL(pipe),
8014                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8015
8016         /* No need to actually set up the DPLL with DSI */
8017         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8018                 return;
8019
8020         bestn = pipe_config->dpll.n;
8021         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8022         bestm1 = pipe_config->dpll.m1;
8023         bestm2 = pipe_config->dpll.m2 >> 22;
8024         bestp1 = pipe_config->dpll.p1;
8025         bestp2 = pipe_config->dpll.p2;
8026         vco = pipe_config->dpll.vco;
8027         dpio_val = 0;
8028         loopfilter = 0;
8029
8030         vlv_dpio_get(dev_priv);
8031
8032         /* p1 and p2 divider */
8033         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8034                         5 << DPIO_CHV_S1_DIV_SHIFT |
8035                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8036                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8037                         1 << DPIO_CHV_K_DIV_SHIFT);
8038
8039         /* Feedback post-divider - m2 */
8040         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8041
8042         /* Feedback refclk divider - n and m1 */
8043         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8044                         DPIO_CHV_M1_DIV_BY_2 |
8045                         1 << DPIO_CHV_N_DIV_SHIFT);
8046
8047         /* M2 fraction division */
8048         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8049
8050         /* M2 fraction division enable */
8051         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8052         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8053         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8054         if (bestm2_frac)
8055                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8056         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8057
8058         /* Program digital lock detect threshold */
8059         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8060         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8061                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8062         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8063         if (!bestm2_frac)
8064                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8065         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8066
8067         /* Loop filter */
8068         if (vco == 5400000) {
8069                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8070                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8071                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8072                 tribuf_calcntr = 0x9;
8073         } else if (vco <= 6200000) {
8074                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8075                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8076                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8077                 tribuf_calcntr = 0x9;
8078         } else if (vco <= 6480000) {
8079                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8080                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8081                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8082                 tribuf_calcntr = 0x8;
8083         } else {
8084                 /* Not supported. Apply the same limits as in the max case */
8085                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8086                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8087                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8088                 tribuf_calcntr = 0;
8089         }
8090         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8091
8092         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8093         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8094         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8095         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8096
8097         /* AFC Recal */
8098         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8099                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8100                         DPIO_AFC_RECAL);
8101
8102         vlv_dpio_put(dev_priv);
8103 }
8104
8105 /**
8106  * vlv_force_pll_on - forcibly enable just the PLL
8107  * @dev_priv: i915 private structure
8108  * @pipe: pipe PLL to enable
8109  * @dpll: PLL configuration
8110  *
8111  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8112  * in cases where we need the PLL enabled even when @pipe is not going to
8113  * be enabled.
8114  */
8115 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8116                      const struct dpll *dpll)
8117 {
8118         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8119         struct intel_crtc_state *pipe_config;
8120
8121         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8122         if (!pipe_config)
8123                 return -ENOMEM;
8124
8125         pipe_config->uapi.crtc = &crtc->base;
8126         pipe_config->pixel_multiplier = 1;
8127         pipe_config->dpll = *dpll;
8128
8129         if (IS_CHERRYVIEW(dev_priv)) {
8130                 chv_compute_dpll(crtc, pipe_config);
8131                 chv_prepare_pll(crtc, pipe_config);
8132                 chv_enable_pll(crtc, pipe_config);
8133         } else {
8134                 vlv_compute_dpll(crtc, pipe_config);
8135                 vlv_prepare_pll(crtc, pipe_config);
8136                 vlv_enable_pll(crtc, pipe_config);
8137         }
8138
8139         kfree(pipe_config);
8140
8141         return 0;
8142 }
8143
8144 /**
8145  * vlv_force_pll_off - forcibly disable just the PLL
8146  * @dev_priv: i915 private structure
8147  * @pipe: pipe PLL to disable
8148  *
8149  * Disable the PLL for @pipe. To be used in cases where we need
8150  * the PLL enabled even when @pipe is not going to be enabled.
8151  */
8152 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8153 {
8154         if (IS_CHERRYVIEW(dev_priv))
8155                 chv_disable_pll(dev_priv, pipe);
8156         else
8157                 vlv_disable_pll(dev_priv, pipe);
8158 }
8159
8160 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8161                               struct intel_crtc_state *crtc_state,
8162                               struct dpll *reduced_clock)
8163 {
8164         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8165         u32 dpll;
8166         struct dpll *clock = &crtc_state->dpll;
8167
8168         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8169
8170         dpll = DPLL_VGA_MODE_DIS;
8171
8172         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8173                 dpll |= DPLLB_MODE_LVDS;
8174         else
8175                 dpll |= DPLLB_MODE_DAC_SERIAL;
8176
8177         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8178             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8179                 dpll |= (crtc_state->pixel_multiplier - 1)
8180                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8181         }
8182
8183         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8184             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8185                 dpll |= DPLL_SDVO_HIGH_SPEED;
8186
8187         if (intel_crtc_has_dp_encoder(crtc_state))
8188                 dpll |= DPLL_SDVO_HIGH_SPEED;
8189
8190         /* compute bitmask from p1 value */
8191         if (IS_PINEVIEW(dev_priv))
8192                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8193         else {
8194                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8195                 if (IS_G4X(dev_priv) && reduced_clock)
8196                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8197         }
8198         switch (clock->p2) {
8199         case 5:
8200                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8201                 break;
8202         case 7:
8203                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8204                 break;
8205         case 10:
8206                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8207                 break;
8208         case 14:
8209                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8210                 break;
8211         }
8212         if (INTEL_GEN(dev_priv) >= 4)
8213                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8214
8215         if (crtc_state->sdvo_tv_clock)
8216                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8217         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8218                  intel_panel_use_ssc(dev_priv))
8219                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8220         else
8221                 dpll |= PLL_REF_INPUT_DREFCLK;
8222
8223         dpll |= DPLL_VCO_ENABLE;
8224         crtc_state->dpll_hw_state.dpll = dpll;
8225
8226         if (INTEL_GEN(dev_priv) >= 4) {
8227                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8228                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8229                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8230         }
8231 }
8232
8233 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8234                               struct intel_crtc_state *crtc_state,
8235                               struct dpll *reduced_clock)
8236 {
8237         struct drm_device *dev = crtc->base.dev;
8238         struct drm_i915_private *dev_priv = to_i915(dev);
8239         u32 dpll;
8240         struct dpll *clock = &crtc_state->dpll;
8241
8242         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8243
8244         dpll = DPLL_VGA_MODE_DIS;
8245
8246         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8247                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8248         } else {
8249                 if (clock->p1 == 2)
8250                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8251                 else
8252                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8253                 if (clock->p2 == 4)
8254                         dpll |= PLL_P2_DIVIDE_BY_4;
8255         }
8256
8257         /*
8258          * Bspec:
8259          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8260          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8261          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8262          *  Enable) must be set to “1” in both the DPLL A Control Register
8263          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8264          *
8265          * For simplicity We simply keep both bits always enabled in
8266          * both DPLLS. The spec says we should disable the DVO 2X clock
8267          * when not needed, but this seems to work fine in practice.
8268          */
8269         if (IS_I830(dev_priv) ||
8270             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8271                 dpll |= DPLL_DVO_2X_MODE;
8272
8273         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8274             intel_panel_use_ssc(dev_priv))
8275                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8276         else
8277                 dpll |= PLL_REF_INPUT_DREFCLK;
8278
8279         dpll |= DPLL_VCO_ENABLE;
8280         crtc_state->dpll_hw_state.dpll = dpll;
8281 }
8282
8283 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8284 {
8285         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8286         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8287         enum pipe pipe = crtc->pipe;
8288         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8289         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8290         u32 crtc_vtotal, crtc_vblank_end;
8291         int vsyncshift = 0;
8292
8293         /* We need to be careful not to changed the adjusted mode, for otherwise
8294          * the hw state checker will get angry at the mismatch. */
8295         crtc_vtotal = adjusted_mode->crtc_vtotal;
8296         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8297
8298         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8299                 /* the chip adds 2 halflines automatically */
8300                 crtc_vtotal -= 1;
8301                 crtc_vblank_end -= 1;
8302
8303                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8304                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8305                 else
8306                         vsyncshift = adjusted_mode->crtc_hsync_start -
8307                                 adjusted_mode->crtc_htotal / 2;
8308                 if (vsyncshift < 0)
8309                         vsyncshift += adjusted_mode->crtc_htotal;
8310         }
8311
8312         if (INTEL_GEN(dev_priv) > 3)
8313                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8314
8315         I915_WRITE(HTOTAL(cpu_transcoder),
8316                    (adjusted_mode->crtc_hdisplay - 1) |
8317                    ((adjusted_mode->crtc_htotal - 1) << 16));
8318         I915_WRITE(HBLANK(cpu_transcoder),
8319                    (adjusted_mode->crtc_hblank_start - 1) |
8320                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8321         I915_WRITE(HSYNC(cpu_transcoder),
8322                    (adjusted_mode->crtc_hsync_start - 1) |
8323                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8324
8325         I915_WRITE(VTOTAL(cpu_transcoder),
8326                    (adjusted_mode->crtc_vdisplay - 1) |
8327                    ((crtc_vtotal - 1) << 16));
8328         I915_WRITE(VBLANK(cpu_transcoder),
8329                    (adjusted_mode->crtc_vblank_start - 1) |
8330                    ((crtc_vblank_end - 1) << 16));
8331         I915_WRITE(VSYNC(cpu_transcoder),
8332                    (adjusted_mode->crtc_vsync_start - 1) |
8333                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8334
8335         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8336          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8337          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8338          * bits. */
8339         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8340             (pipe == PIPE_B || pipe == PIPE_C))
8341                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8342
8343 }
8344
8345 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8346 {
8347         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8348         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8349         enum pipe pipe = crtc->pipe;
8350
8351         /* pipesrc controls the size that is scaled from, which should
8352          * always be the user's requested size.
8353          */
8354         I915_WRITE(PIPESRC(pipe),
8355                    ((crtc_state->pipe_src_w - 1) << 16) |
8356                    (crtc_state->pipe_src_h - 1));
8357 }
8358
8359 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8360 {
8361         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8362         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8363
8364         if (IS_GEN(dev_priv, 2))
8365                 return false;
8366
8367         if (INTEL_GEN(dev_priv) >= 9 ||
8368             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8369                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8370         else
8371                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8372 }
8373
8374 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8375                                    struct intel_crtc_state *pipe_config)
8376 {
8377         struct drm_device *dev = crtc->base.dev;
8378         struct drm_i915_private *dev_priv = to_i915(dev);
8379         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8380         u32 tmp;
8381
8382         tmp = I915_READ(HTOTAL(cpu_transcoder));
8383         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8384         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8385
8386         if (!transcoder_is_dsi(cpu_transcoder)) {
8387                 tmp = I915_READ(HBLANK(cpu_transcoder));
8388                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8389                                                         (tmp & 0xffff) + 1;
8390                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8391                                                 ((tmp >> 16) & 0xffff) + 1;
8392         }
8393         tmp = I915_READ(HSYNC(cpu_transcoder));
8394         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8395         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8396
8397         tmp = I915_READ(VTOTAL(cpu_transcoder));
8398         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8399         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8400
8401         if (!transcoder_is_dsi(cpu_transcoder)) {
8402                 tmp = I915_READ(VBLANK(cpu_transcoder));
8403                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8404                                                         (tmp & 0xffff) + 1;
8405                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8406                                                 ((tmp >> 16) & 0xffff) + 1;
8407         }
8408         tmp = I915_READ(VSYNC(cpu_transcoder));
8409         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8410         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8411
8412         if (intel_pipe_is_interlaced(pipe_config)) {
8413                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8414                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8415                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8416         }
8417 }
8418
8419 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8420                                     struct intel_crtc_state *pipe_config)
8421 {
8422         struct drm_device *dev = crtc->base.dev;
8423         struct drm_i915_private *dev_priv = to_i915(dev);
8424         u32 tmp;
8425
8426         tmp = I915_READ(PIPESRC(crtc->pipe));
8427         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8428         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8429
8430         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8431         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8432 }
8433
8434 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8435                                  struct intel_crtc_state *pipe_config)
8436 {
8437         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8438         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8439         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8440         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8441
8442         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8443         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8444         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8445         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8446
8447         mode->flags = pipe_config->hw.adjusted_mode.flags;
8448         mode->type = DRM_MODE_TYPE_DRIVER;
8449
8450         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8451
8452         mode->hsync = drm_mode_hsync(mode);
8453         mode->vrefresh = drm_mode_vrefresh(mode);
8454         drm_mode_set_name(mode);
8455 }
8456
8457 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8458 {
8459         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8460         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8461         u32 pipeconf;
8462
8463         pipeconf = 0;
8464
8465         /* we keep both pipes enabled on 830 */
8466         if (IS_I830(dev_priv))
8467                 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8468
8469         if (crtc_state->double_wide)
8470                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8471
8472         /* only g4x and later have fancy bpc/dither controls */
8473         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8474             IS_CHERRYVIEW(dev_priv)) {
8475                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8476                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8477                         pipeconf |= PIPECONF_DITHER_EN |
8478                                     PIPECONF_DITHER_TYPE_SP;
8479
8480                 switch (crtc_state->pipe_bpp) {
8481                 case 18:
8482                         pipeconf |= PIPECONF_6BPC;
8483                         break;
8484                 case 24:
8485                         pipeconf |= PIPECONF_8BPC;
8486                         break;
8487                 case 30:
8488                         pipeconf |= PIPECONF_10BPC;
8489                         break;
8490                 default:
8491                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8492                         BUG();
8493                 }
8494         }
8495
8496         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8497                 if (INTEL_GEN(dev_priv) < 4 ||
8498                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8499                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8500                 else
8501                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8502         } else {
8503                 pipeconf |= PIPECONF_PROGRESSIVE;
8504         }
8505
8506         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8507              crtc_state->limited_color_range)
8508                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8509
8510         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8511
8512         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8513
8514         I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8515         POSTING_READ(PIPECONF(crtc->pipe));
8516 }
8517
8518 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8519                                    struct intel_crtc_state *crtc_state)
8520 {
8521         struct drm_device *dev = crtc->base.dev;
8522         struct drm_i915_private *dev_priv = to_i915(dev);
8523         const struct intel_limit *limit;
8524         int refclk = 48000;
8525
8526         memset(&crtc_state->dpll_hw_state, 0,
8527                sizeof(crtc_state->dpll_hw_state));
8528
8529         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8530                 if (intel_panel_use_ssc(dev_priv)) {
8531                         refclk = dev_priv->vbt.lvds_ssc_freq;
8532                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8533                 }
8534
8535                 limit = &intel_limits_i8xx_lvds;
8536         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8537                 limit = &intel_limits_i8xx_dvo;
8538         } else {
8539                 limit = &intel_limits_i8xx_dac;
8540         }
8541
8542         if (!crtc_state->clock_set &&
8543             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8544                                  refclk, NULL, &crtc_state->dpll)) {
8545                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8546                 return -EINVAL;
8547         }
8548
8549         i8xx_compute_dpll(crtc, crtc_state, NULL);
8550
8551         return 0;
8552 }
8553
8554 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8555                                   struct intel_crtc_state *crtc_state)
8556 {
8557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8558         const struct intel_limit *limit;
8559         int refclk = 96000;
8560
8561         memset(&crtc_state->dpll_hw_state, 0,
8562                sizeof(crtc_state->dpll_hw_state));
8563
8564         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8565                 if (intel_panel_use_ssc(dev_priv)) {
8566                         refclk = dev_priv->vbt.lvds_ssc_freq;
8567                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8568                 }
8569
8570                 if (intel_is_dual_link_lvds(dev_priv))
8571                         limit = &intel_limits_g4x_dual_channel_lvds;
8572                 else
8573                         limit = &intel_limits_g4x_single_channel_lvds;
8574         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8575                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8576                 limit = &intel_limits_g4x_hdmi;
8577         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8578                 limit = &intel_limits_g4x_sdvo;
8579         } else {
8580                 /* The option is for other outputs */
8581                 limit = &intel_limits_i9xx_sdvo;
8582         }
8583
8584         if (!crtc_state->clock_set &&
8585             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8586                                 refclk, NULL, &crtc_state->dpll)) {
8587                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8588                 return -EINVAL;
8589         }
8590
8591         i9xx_compute_dpll(crtc, crtc_state, NULL);
8592
8593         return 0;
8594 }
8595
8596 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8597                                   struct intel_crtc_state *crtc_state)
8598 {
8599         struct drm_device *dev = crtc->base.dev;
8600         struct drm_i915_private *dev_priv = to_i915(dev);
8601         const struct intel_limit *limit;
8602         int refclk = 96000;
8603
8604         memset(&crtc_state->dpll_hw_state, 0,
8605                sizeof(crtc_state->dpll_hw_state));
8606
8607         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8608                 if (intel_panel_use_ssc(dev_priv)) {
8609                         refclk = dev_priv->vbt.lvds_ssc_freq;
8610                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8611                 }
8612
8613                 limit = &intel_limits_pineview_lvds;
8614         } else {
8615                 limit = &intel_limits_pineview_sdvo;
8616         }
8617
8618         if (!crtc_state->clock_set &&
8619             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8620                                 refclk, NULL, &crtc_state->dpll)) {
8621                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8622                 return -EINVAL;
8623         }
8624
8625         i9xx_compute_dpll(crtc, crtc_state, NULL);
8626
8627         return 0;
8628 }
8629
8630 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8631                                    struct intel_crtc_state *crtc_state)
8632 {
8633         struct drm_device *dev = crtc->base.dev;
8634         struct drm_i915_private *dev_priv = to_i915(dev);
8635         const struct intel_limit *limit;
8636         int refclk = 96000;
8637
8638         memset(&crtc_state->dpll_hw_state, 0,
8639                sizeof(crtc_state->dpll_hw_state));
8640
8641         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8642                 if (intel_panel_use_ssc(dev_priv)) {
8643                         refclk = dev_priv->vbt.lvds_ssc_freq;
8644                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8645                 }
8646
8647                 limit = &intel_limits_i9xx_lvds;
8648         } else {
8649                 limit = &intel_limits_i9xx_sdvo;
8650         }
8651
8652         if (!crtc_state->clock_set &&
8653             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8654                                  refclk, NULL, &crtc_state->dpll)) {
8655                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8656                 return -EINVAL;
8657         }
8658
8659         i9xx_compute_dpll(crtc, crtc_state, NULL);
8660
8661         return 0;
8662 }
8663
8664 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8665                                   struct intel_crtc_state *crtc_state)
8666 {
8667         int refclk = 100000;
8668         const struct intel_limit *limit = &intel_limits_chv;
8669
8670         memset(&crtc_state->dpll_hw_state, 0,
8671                sizeof(crtc_state->dpll_hw_state));
8672
8673         if (!crtc_state->clock_set &&
8674             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8675                                 refclk, NULL, &crtc_state->dpll)) {
8676                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8677                 return -EINVAL;
8678         }
8679
8680         chv_compute_dpll(crtc, crtc_state);
8681
8682         return 0;
8683 }
8684
8685 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8686                                   struct intel_crtc_state *crtc_state)
8687 {
8688         int refclk = 100000;
8689         const struct intel_limit *limit = &intel_limits_vlv;
8690
8691         memset(&crtc_state->dpll_hw_state, 0,
8692                sizeof(crtc_state->dpll_hw_state));
8693
8694         if (!crtc_state->clock_set &&
8695             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8696                                 refclk, NULL, &crtc_state->dpll)) {
8697                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8698                 return -EINVAL;
8699         }
8700
8701         vlv_compute_dpll(crtc, crtc_state);
8702
8703         return 0;
8704 }
8705
8706 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8707 {
8708         if (IS_I830(dev_priv))
8709                 return false;
8710
8711         return INTEL_GEN(dev_priv) >= 4 ||
8712                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8713 }
8714
8715 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8716                                  struct intel_crtc_state *pipe_config)
8717 {
8718         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8719         u32 tmp;
8720
8721         if (!i9xx_has_pfit(dev_priv))
8722                 return;
8723
8724         tmp = I915_READ(PFIT_CONTROL);
8725         if (!(tmp & PFIT_ENABLE))
8726                 return;
8727
8728         /* Check whether the pfit is attached to our pipe. */
8729         if (INTEL_GEN(dev_priv) < 4) {
8730                 if (crtc->pipe != PIPE_B)
8731                         return;
8732         } else {
8733                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8734                         return;
8735         }
8736
8737         pipe_config->gmch_pfit.control = tmp;
8738         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8739 }
8740
8741 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8742                                struct intel_crtc_state *pipe_config)
8743 {
8744         struct drm_device *dev = crtc->base.dev;
8745         struct drm_i915_private *dev_priv = to_i915(dev);
8746         enum pipe pipe = crtc->pipe;
8747         struct dpll clock;
8748         u32 mdiv;
8749         int refclk = 100000;
8750
8751         /* In case of DSI, DPLL will not be used */
8752         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8753                 return;
8754
8755         vlv_dpio_get(dev_priv);
8756         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8757         vlv_dpio_put(dev_priv);
8758
8759         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8760         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8761         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8762         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8763         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8764
8765         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8766 }
8767
8768 static void
8769 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8770                               struct intel_initial_plane_config *plane_config)
8771 {
8772         struct drm_device *dev = crtc->base.dev;
8773         struct drm_i915_private *dev_priv = to_i915(dev);
8774         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8775         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8776         enum pipe pipe;
8777         u32 val, base, offset;
8778         int fourcc, pixel_format;
8779         unsigned int aligned_height;
8780         struct drm_framebuffer *fb;
8781         struct intel_framebuffer *intel_fb;
8782
8783         if (!plane->get_hw_state(plane, &pipe))
8784                 return;
8785
8786         WARN_ON(pipe != crtc->pipe);
8787
8788         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8789         if (!intel_fb) {
8790                 DRM_DEBUG_KMS("failed to alloc fb\n");
8791                 return;
8792         }
8793
8794         fb = &intel_fb->base;
8795
8796         fb->dev = dev;
8797
8798         val = I915_READ(DSPCNTR(i9xx_plane));
8799
8800         if (INTEL_GEN(dev_priv) >= 4) {
8801                 if (val & DISPPLANE_TILED) {
8802                         plane_config->tiling = I915_TILING_X;
8803                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8804                 }
8805
8806                 if (val & DISPPLANE_ROTATE_180)
8807                         plane_config->rotation = DRM_MODE_ROTATE_180;
8808         }
8809
8810         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8811             val & DISPPLANE_MIRROR)
8812                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8813
8814         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8815         fourcc = i9xx_format_to_fourcc(pixel_format);
8816         fb->format = drm_format_info(fourcc);
8817
8818         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8819                 offset = I915_READ(DSPOFFSET(i9xx_plane));
8820                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8821         } else if (INTEL_GEN(dev_priv) >= 4) {
8822                 if (plane_config->tiling)
8823                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
8824                 else
8825                         offset = I915_READ(DSPLINOFF(i9xx_plane));
8826                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8827         } else {
8828                 base = I915_READ(DSPADDR(i9xx_plane));
8829         }
8830         plane_config->base = base;
8831
8832         val = I915_READ(PIPESRC(pipe));
8833         fb->width = ((val >> 16) & 0xfff) + 1;
8834         fb->height = ((val >> 0) & 0xfff) + 1;
8835
8836         val = I915_READ(DSPSTRIDE(i9xx_plane));
8837         fb->pitches[0] = val & 0xffffffc0;
8838
8839         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8840
8841         plane_config->size = fb->pitches[0] * aligned_height;
8842
8843         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8844                       crtc->base.name, plane->base.name, fb->width, fb->height,
8845                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8846                       plane_config->size);
8847
8848         plane_config->fb = intel_fb;
8849 }
8850
8851 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8852                                struct intel_crtc_state *pipe_config)
8853 {
8854         struct drm_device *dev = crtc->base.dev;
8855         struct drm_i915_private *dev_priv = to_i915(dev);
8856         enum pipe pipe = crtc->pipe;
8857         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8858         struct dpll clock;
8859         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8860         int refclk = 100000;
8861
8862         /* In case of DSI, DPLL will not be used */
8863         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8864                 return;
8865
8866         vlv_dpio_get(dev_priv);
8867         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8868         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8869         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8870         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8871         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8872         vlv_dpio_put(dev_priv);
8873
8874         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8875         clock.m2 = (pll_dw0 & 0xff) << 22;
8876         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8877                 clock.m2 |= pll_dw2 & 0x3fffff;
8878         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8879         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8880         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8881
8882         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8883 }
8884
8885 static enum intel_output_format
8886 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
8887 {
8888         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8889         u32 tmp;
8890
8891         tmp = I915_READ(PIPEMISC(crtc->pipe));
8892
8893         if (tmp & PIPEMISC_YUV420_ENABLE) {
8894                 /* We support 4:2:0 in full blend mode only */
8895                 WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
8896
8897                 return INTEL_OUTPUT_FORMAT_YCBCR420;
8898         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8899                 return INTEL_OUTPUT_FORMAT_YCBCR444;
8900         } else {
8901                 return INTEL_OUTPUT_FORMAT_RGB;
8902         }
8903 }
8904
8905 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8906 {
8907         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8908         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8909         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8910         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8911         u32 tmp;
8912
8913         tmp = I915_READ(DSPCNTR(i9xx_plane));
8914
8915         if (tmp & DISPPLANE_GAMMA_ENABLE)
8916                 crtc_state->gamma_enable = true;
8917
8918         if (!HAS_GMCH(dev_priv) &&
8919             tmp & DISPPLANE_PIPE_CSC_ENABLE)
8920                 crtc_state->csc_enable = true;
8921 }
8922
8923 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8924                                  struct intel_crtc_state *pipe_config)
8925 {
8926         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8927         enum intel_display_power_domain power_domain;
8928         intel_wakeref_t wakeref;
8929         u32 tmp;
8930         bool ret;
8931
8932         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8933         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8934         if (!wakeref)
8935                 return false;
8936
8937         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8938         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8939         pipe_config->shared_dpll = NULL;
8940         pipe_config->master_transcoder = INVALID_TRANSCODER;
8941
8942         ret = false;
8943
8944         tmp = I915_READ(PIPECONF(crtc->pipe));
8945         if (!(tmp & PIPECONF_ENABLE))
8946                 goto out;
8947
8948         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8949             IS_CHERRYVIEW(dev_priv)) {
8950                 switch (tmp & PIPECONF_BPC_MASK) {
8951                 case PIPECONF_6BPC:
8952                         pipe_config->pipe_bpp = 18;
8953                         break;
8954                 case PIPECONF_8BPC:
8955                         pipe_config->pipe_bpp = 24;
8956                         break;
8957                 case PIPECONF_10BPC:
8958                         pipe_config->pipe_bpp = 30;
8959                         break;
8960                 default:
8961                         break;
8962                 }
8963         }
8964
8965         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8966             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8967                 pipe_config->limited_color_range = true;
8968
8969         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8970                 PIPECONF_GAMMA_MODE_SHIFT;
8971
8972         if (IS_CHERRYVIEW(dev_priv))
8973                 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8974
8975         i9xx_get_pipe_color_config(pipe_config);
8976         intel_color_get_config(pipe_config);
8977
8978         if (INTEL_GEN(dev_priv) < 4)
8979                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8980
8981         intel_get_pipe_timings(crtc, pipe_config);
8982         intel_get_pipe_src_size(crtc, pipe_config);
8983
8984         i9xx_get_pfit_config(crtc, pipe_config);
8985
8986         if (INTEL_GEN(dev_priv) >= 4) {
8987                 /* No way to read it out on pipes B and C */
8988                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8989                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8990                 else
8991                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8992                 pipe_config->pixel_multiplier =
8993                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8994                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8995                 pipe_config->dpll_hw_state.dpll_md = tmp;
8996         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8997                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8998                 tmp = I915_READ(DPLL(crtc->pipe));
8999                 pipe_config->pixel_multiplier =
9000                         ((tmp & SDVO_MULTIPLIER_MASK)
9001                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9002         } else {
9003                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9004                  * port and will be fixed up in the encoder->get_config
9005                  * function. */
9006                 pipe_config->pixel_multiplier = 1;
9007         }
9008         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
9009         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9010                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
9011                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
9012         } else {
9013                 /* Mask out read-only status bits. */
9014                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9015                                                      DPLL_PORTC_READY_MASK |
9016                                                      DPLL_PORTB_READY_MASK);
9017         }
9018
9019         if (IS_CHERRYVIEW(dev_priv))
9020                 chv_crtc_clock_get(crtc, pipe_config);
9021         else if (IS_VALLEYVIEW(dev_priv))
9022                 vlv_crtc_clock_get(crtc, pipe_config);
9023         else
9024                 i9xx_crtc_clock_get(crtc, pipe_config);
9025
9026         /*
9027          * Normally the dotclock is filled in by the encoder .get_config()
9028          * but in case the pipe is enabled w/o any ports we need a sane
9029          * default.
9030          */
9031         pipe_config->hw.adjusted_mode.crtc_clock =
9032                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9033
9034         ret = true;
9035
9036 out:
9037         intel_display_power_put(dev_priv, power_domain, wakeref);
9038
9039         return ret;
9040 }
9041
9042 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
9043 {
9044         struct intel_encoder *encoder;
9045         int i;
9046         u32 val, final;
9047         bool has_lvds = false;
9048         bool has_cpu_edp = false;
9049         bool has_panel = false;
9050         bool has_ck505 = false;
9051         bool can_ssc = false;
9052         bool using_ssc_source = false;
9053
9054         /* We need to take the global config into account */
9055         for_each_intel_encoder(&dev_priv->drm, encoder) {
9056                 switch (encoder->type) {
9057                 case INTEL_OUTPUT_LVDS:
9058                         has_panel = true;
9059                         has_lvds = true;
9060                         break;
9061                 case INTEL_OUTPUT_EDP:
9062                         has_panel = true;
9063                         if (encoder->port == PORT_A)
9064                                 has_cpu_edp = true;
9065                         break;
9066                 default:
9067                         break;
9068                 }
9069         }
9070
9071         if (HAS_PCH_IBX(dev_priv)) {
9072                 has_ck505 = dev_priv->vbt.display_clock_mode;
9073                 can_ssc = has_ck505;
9074         } else {
9075                 has_ck505 = false;
9076                 can_ssc = true;
9077         }
9078
9079         /* Check if any DPLLs are using the SSC source */
9080         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9081                 u32 temp = I915_READ(PCH_DPLL(i));
9082
9083                 if (!(temp & DPLL_VCO_ENABLE))
9084                         continue;
9085
9086                 if ((temp & PLL_REF_INPUT_MASK) ==
9087                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9088                         using_ssc_source = true;
9089                         break;
9090                 }
9091         }
9092
9093         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9094                       has_panel, has_lvds, has_ck505, using_ssc_source);
9095
9096         /* Ironlake: try to setup display ref clock before DPLL
9097          * enabling. This is only under driver's control after
9098          * PCH B stepping, previous chipset stepping should be
9099          * ignoring this setting.
9100          */
9101         val = I915_READ(PCH_DREF_CONTROL);
9102
9103         /* As we must carefully and slowly disable/enable each source in turn,
9104          * compute the final state we want first and check if we need to
9105          * make any changes at all.
9106          */
9107         final = val;
9108         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9109         if (has_ck505)
9110                 final |= DREF_NONSPREAD_CK505_ENABLE;
9111         else
9112                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9113
9114         final &= ~DREF_SSC_SOURCE_MASK;
9115         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9116         final &= ~DREF_SSC1_ENABLE;
9117
9118         if (has_panel) {
9119                 final |= DREF_SSC_SOURCE_ENABLE;
9120
9121                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9122                         final |= DREF_SSC1_ENABLE;
9123
9124                 if (has_cpu_edp) {
9125                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9126                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9127                         else
9128                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9129                 } else
9130                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9131         } else if (using_ssc_source) {
9132                 final |= DREF_SSC_SOURCE_ENABLE;
9133                 final |= DREF_SSC1_ENABLE;
9134         }
9135
9136         if (final == val)
9137                 return;
9138
9139         /* Always enable nonspread source */
9140         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9141
9142         if (has_ck505)
9143                 val |= DREF_NONSPREAD_CK505_ENABLE;
9144         else
9145                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9146
9147         if (has_panel) {
9148                 val &= ~DREF_SSC_SOURCE_MASK;
9149                 val |= DREF_SSC_SOURCE_ENABLE;
9150
9151                 /* SSC must be turned on before enabling the CPU output  */
9152                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9153                         DRM_DEBUG_KMS("Using SSC on panel\n");
9154                         val |= DREF_SSC1_ENABLE;
9155                 } else
9156                         val &= ~DREF_SSC1_ENABLE;
9157
9158                 /* Get SSC going before enabling the outputs */
9159                 I915_WRITE(PCH_DREF_CONTROL, val);
9160                 POSTING_READ(PCH_DREF_CONTROL);
9161                 udelay(200);
9162
9163                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9164
9165                 /* Enable CPU source on CPU attached eDP */
9166                 if (has_cpu_edp) {
9167                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9168                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9169                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9170                         } else
9171                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9172                 } else
9173                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9174
9175                 I915_WRITE(PCH_DREF_CONTROL, val);
9176                 POSTING_READ(PCH_DREF_CONTROL);
9177                 udelay(200);
9178         } else {
9179                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9180
9181                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9182
9183                 /* Turn off CPU output */
9184                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9185
9186                 I915_WRITE(PCH_DREF_CONTROL, val);
9187                 POSTING_READ(PCH_DREF_CONTROL);
9188                 udelay(200);
9189
9190                 if (!using_ssc_source) {
9191                         DRM_DEBUG_KMS("Disabling SSC source\n");
9192
9193                         /* Turn off the SSC source */
9194                         val &= ~DREF_SSC_SOURCE_MASK;
9195                         val |= DREF_SSC_SOURCE_DISABLE;
9196
9197                         /* Turn off SSC1 */
9198                         val &= ~DREF_SSC1_ENABLE;
9199
9200                         I915_WRITE(PCH_DREF_CONTROL, val);
9201                         POSTING_READ(PCH_DREF_CONTROL);
9202                         udelay(200);
9203                 }
9204         }
9205
9206         BUG_ON(val != final);
9207 }
9208
9209 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9210 {
9211         u32 tmp;
9212
9213         tmp = I915_READ(SOUTH_CHICKEN2);
9214         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9215         I915_WRITE(SOUTH_CHICKEN2, tmp);
9216
9217         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9218                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9219                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9220
9221         tmp = I915_READ(SOUTH_CHICKEN2);
9222         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9223         I915_WRITE(SOUTH_CHICKEN2, tmp);
9224
9225         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9226                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9227                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9228 }
9229
9230 /* WaMPhyProgramming:hsw */
9231 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9232 {
9233         u32 tmp;
9234
9235         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9236         tmp &= ~(0xFF << 24);
9237         tmp |= (0x12 << 24);
9238         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9239
9240         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9241         tmp |= (1 << 11);
9242         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9243
9244         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9245         tmp |= (1 << 11);
9246         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9247
9248         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9249         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9250         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9251
9252         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9253         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9254         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9255
9256         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9257         tmp &= ~(7 << 13);
9258         tmp |= (5 << 13);
9259         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9260
9261         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9262         tmp &= ~(7 << 13);
9263         tmp |= (5 << 13);
9264         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9265
9266         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9267         tmp &= ~0xFF;
9268         tmp |= 0x1C;
9269         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9270
9271         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9272         tmp &= ~0xFF;
9273         tmp |= 0x1C;
9274         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9275
9276         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9277         tmp &= ~(0xFF << 16);
9278         tmp |= (0x1C << 16);
9279         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9280
9281         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9282         tmp &= ~(0xFF << 16);
9283         tmp |= (0x1C << 16);
9284         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9285
9286         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9287         tmp |= (1 << 27);
9288         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9289
9290         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9291         tmp |= (1 << 27);
9292         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9293
9294         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9295         tmp &= ~(0xF << 28);
9296         tmp |= (4 << 28);
9297         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9298
9299         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9300         tmp &= ~(0xF << 28);
9301         tmp |= (4 << 28);
9302         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9303 }
9304
9305 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9306  * Programming" based on the parameters passed:
9307  * - Sequence to enable CLKOUT_DP
9308  * - Sequence to enable CLKOUT_DP without spread
9309  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9310  */
9311 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9312                                  bool with_spread, bool with_fdi)
9313 {
9314         u32 reg, tmp;
9315
9316         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9317                 with_spread = true;
9318         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9319             with_fdi, "LP PCH doesn't have FDI\n"))
9320                 with_fdi = false;
9321
9322         mutex_lock(&dev_priv->sb_lock);
9323
9324         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9325         tmp &= ~SBI_SSCCTL_DISABLE;
9326         tmp |= SBI_SSCCTL_PATHALT;
9327         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9328
9329         udelay(24);
9330
9331         if (with_spread) {
9332                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9333                 tmp &= ~SBI_SSCCTL_PATHALT;
9334                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9335
9336                 if (with_fdi) {
9337                         lpt_reset_fdi_mphy(dev_priv);
9338                         lpt_program_fdi_mphy(dev_priv);
9339                 }
9340         }
9341
9342         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9343         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9344         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9345         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9346
9347         mutex_unlock(&dev_priv->sb_lock);
9348 }
9349
9350 /* Sequence to disable CLKOUT_DP */
9351 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9352 {
9353         u32 reg, tmp;
9354
9355         mutex_lock(&dev_priv->sb_lock);
9356
9357         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9358         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9359         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9360         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9361
9362         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9363         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9364                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9365                         tmp |= SBI_SSCCTL_PATHALT;
9366                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9367                         udelay(32);
9368                 }
9369                 tmp |= SBI_SSCCTL_DISABLE;
9370                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9371         }
9372
9373         mutex_unlock(&dev_priv->sb_lock);
9374 }
9375
9376 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9377
9378 static const u16 sscdivintphase[] = {
9379         [BEND_IDX( 50)] = 0x3B23,
9380         [BEND_IDX( 45)] = 0x3B23,
9381         [BEND_IDX( 40)] = 0x3C23,
9382         [BEND_IDX( 35)] = 0x3C23,
9383         [BEND_IDX( 30)] = 0x3D23,
9384         [BEND_IDX( 25)] = 0x3D23,
9385         [BEND_IDX( 20)] = 0x3E23,
9386         [BEND_IDX( 15)] = 0x3E23,
9387         [BEND_IDX( 10)] = 0x3F23,
9388         [BEND_IDX(  5)] = 0x3F23,
9389         [BEND_IDX(  0)] = 0x0025,
9390         [BEND_IDX( -5)] = 0x0025,
9391         [BEND_IDX(-10)] = 0x0125,
9392         [BEND_IDX(-15)] = 0x0125,
9393         [BEND_IDX(-20)] = 0x0225,
9394         [BEND_IDX(-25)] = 0x0225,
9395         [BEND_IDX(-30)] = 0x0325,
9396         [BEND_IDX(-35)] = 0x0325,
9397         [BEND_IDX(-40)] = 0x0425,
9398         [BEND_IDX(-45)] = 0x0425,
9399         [BEND_IDX(-50)] = 0x0525,
9400 };
9401
9402 /*
9403  * Bend CLKOUT_DP
9404  * steps -50 to 50 inclusive, in steps of 5
9405  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9406  * change in clock period = -(steps / 10) * 5.787 ps
9407  */
9408 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9409 {
9410         u32 tmp;
9411         int idx = BEND_IDX(steps);
9412
9413         if (WARN_ON(steps % 5 != 0))
9414                 return;
9415
9416         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9417                 return;
9418
9419         mutex_lock(&dev_priv->sb_lock);
9420
9421         if (steps % 10 != 0)
9422                 tmp = 0xAAAAAAAB;
9423         else
9424                 tmp = 0x00000000;
9425         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9426
9427         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9428         tmp &= 0xffff0000;
9429         tmp |= sscdivintphase[idx];
9430         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9431
9432         mutex_unlock(&dev_priv->sb_lock);
9433 }
9434
9435 #undef BEND_IDX
9436
9437 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9438 {
9439         u32 fuse_strap = I915_READ(FUSE_STRAP);
9440         u32 ctl = I915_READ(SPLL_CTL);
9441
9442         if ((ctl & SPLL_PLL_ENABLE) == 0)
9443                 return false;
9444
9445         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9446             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9447                 return true;
9448
9449         if (IS_BROADWELL(dev_priv) &&
9450             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9451                 return true;
9452
9453         return false;
9454 }
9455
9456 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9457                                enum intel_dpll_id id)
9458 {
9459         u32 fuse_strap = I915_READ(FUSE_STRAP);
9460         u32 ctl = I915_READ(WRPLL_CTL(id));
9461
9462         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9463                 return false;
9464
9465         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9466                 return true;
9467
9468         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9469             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9470             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9471                 return true;
9472
9473         return false;
9474 }
9475
9476 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9477 {
9478         struct intel_encoder *encoder;
9479         bool has_fdi = false;
9480
9481         for_each_intel_encoder(&dev_priv->drm, encoder) {
9482                 switch (encoder->type) {
9483                 case INTEL_OUTPUT_ANALOG:
9484                         has_fdi = true;
9485                         break;
9486                 default:
9487                         break;
9488                 }
9489         }
9490
9491         /*
9492          * The BIOS may have decided to use the PCH SSC
9493          * reference so we must not disable it until the
9494          * relevant PLLs have stopped relying on it. We'll
9495          * just leave the PCH SSC reference enabled in case
9496          * any active PLL is using it. It will get disabled
9497          * after runtime suspend if we don't have FDI.
9498          *
9499          * TODO: Move the whole reference clock handling
9500          * to the modeset sequence proper so that we can
9501          * actually enable/disable/reconfigure these things
9502          * safely. To do that we need to introduce a real
9503          * clock hierarchy. That would also allow us to do
9504          * clock bending finally.
9505          */
9506         dev_priv->pch_ssc_use = 0;
9507
9508         if (spll_uses_pch_ssc(dev_priv)) {
9509                 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9510                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9511         }
9512
9513         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9514                 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9515                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9516         }
9517
9518         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9519                 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9520                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9521         }
9522
9523         if (dev_priv->pch_ssc_use)
9524                 return;
9525
9526         if (has_fdi) {
9527                 lpt_bend_clkout_dp(dev_priv, 0);
9528                 lpt_enable_clkout_dp(dev_priv, true, true);
9529         } else {
9530                 lpt_disable_clkout_dp(dev_priv);
9531         }
9532 }
9533
9534 /*
9535  * Initialize reference clocks when the driver loads
9536  */
9537 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9538 {
9539         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9540                 ironlake_init_pch_refclk(dev_priv);
9541         else if (HAS_PCH_LPT(dev_priv))
9542                 lpt_init_pch_refclk(dev_priv);
9543 }
9544
9545 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9546 {
9547         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9548         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9549         enum pipe pipe = crtc->pipe;
9550         u32 val;
9551
9552         val = 0;
9553
9554         switch (crtc_state->pipe_bpp) {
9555         case 18:
9556                 val |= PIPECONF_6BPC;
9557                 break;
9558         case 24:
9559                 val |= PIPECONF_8BPC;
9560                 break;
9561         case 30:
9562                 val |= PIPECONF_10BPC;
9563                 break;
9564         case 36:
9565                 val |= PIPECONF_12BPC;
9566                 break;
9567         default:
9568                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9569                 BUG();
9570         }
9571
9572         if (crtc_state->dither)
9573                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9574
9575         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9576                 val |= PIPECONF_INTERLACED_ILK;
9577         else
9578                 val |= PIPECONF_PROGRESSIVE;
9579
9580         /*
9581          * This would end up with an odd purple hue over
9582          * the entire display. Make sure we don't do it.
9583          */
9584         WARN_ON(crtc_state->limited_color_range &&
9585                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
9586
9587         if (crtc_state->limited_color_range)
9588                 val |= PIPECONF_COLOR_RANGE_SELECT;
9589
9590         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9591                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
9592
9593         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9594
9595         val |= PIPECONF_FRAME_START_DELAY(0);
9596
9597         I915_WRITE(PIPECONF(pipe), val);
9598         POSTING_READ(PIPECONF(pipe));
9599 }
9600
9601 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9602 {
9603         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9604         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9605         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9606         u32 val = 0;
9607
9608         if (IS_HASWELL(dev_priv) && crtc_state->dither)
9609                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9610
9611         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9612                 val |= PIPECONF_INTERLACED_ILK;
9613         else
9614                 val |= PIPECONF_PROGRESSIVE;
9615
9616         if (IS_HASWELL(dev_priv) &&
9617             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9618                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
9619
9620         I915_WRITE(PIPECONF(cpu_transcoder), val);
9621         POSTING_READ(PIPECONF(cpu_transcoder));
9622 }
9623
9624 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9625 {
9626         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9627         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9628         u32 val = 0;
9629
9630         switch (crtc_state->pipe_bpp) {
9631         case 18:
9632                 val |= PIPEMISC_DITHER_6_BPC;
9633                 break;
9634         case 24:
9635                 val |= PIPEMISC_DITHER_8_BPC;
9636                 break;
9637         case 30:
9638                 val |= PIPEMISC_DITHER_10_BPC;
9639                 break;
9640         case 36:
9641                 val |= PIPEMISC_DITHER_12_BPC;
9642                 break;
9643         default:
9644                 MISSING_CASE(crtc_state->pipe_bpp);
9645                 break;
9646         }
9647
9648         if (crtc_state->dither)
9649                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9650
9651         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9652             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9653                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9654
9655         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9656                 val |= PIPEMISC_YUV420_ENABLE |
9657                         PIPEMISC_YUV420_MODE_FULL_BLEND;
9658
9659         if (INTEL_GEN(dev_priv) >= 11 &&
9660             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9661                                            BIT(PLANE_CURSOR))) == 0)
9662                 val |= PIPEMISC_HDR_MODE_PRECISION;
9663
9664         I915_WRITE(PIPEMISC(crtc->pipe), val);
9665 }
9666
9667 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9668 {
9669         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9670         u32 tmp;
9671
9672         tmp = I915_READ(PIPEMISC(crtc->pipe));
9673
9674         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9675         case PIPEMISC_DITHER_6_BPC:
9676                 return 18;
9677         case PIPEMISC_DITHER_8_BPC:
9678                 return 24;
9679         case PIPEMISC_DITHER_10_BPC:
9680                 return 30;
9681         case PIPEMISC_DITHER_12_BPC:
9682                 return 36;
9683         default:
9684                 MISSING_CASE(tmp);
9685                 return 0;
9686         }
9687 }
9688
9689 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9690 {
9691         /*
9692          * Account for spread spectrum to avoid
9693          * oversubscribing the link. Max center spread
9694          * is 2.5%; use 5% for safety's sake.
9695          */
9696         u32 bps = target_clock * bpp * 21 / 20;
9697         return DIV_ROUND_UP(bps, link_bw * 8);
9698 }
9699
9700 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9701 {
9702         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9703 }
9704
9705 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9706                                   struct intel_crtc_state *crtc_state,
9707                                   struct dpll *reduced_clock)
9708 {
9709         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9710         u32 dpll, fp, fp2;
9711         int factor;
9712
9713         /* Enable autotuning of the PLL clock (if permissible) */
9714         factor = 21;
9715         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9716                 if ((intel_panel_use_ssc(dev_priv) &&
9717                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9718                     (HAS_PCH_IBX(dev_priv) &&
9719                      intel_is_dual_link_lvds(dev_priv)))
9720                         factor = 25;
9721         } else if (crtc_state->sdvo_tv_clock) {
9722                 factor = 20;
9723         }
9724
9725         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9726
9727         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9728                 fp |= FP_CB_TUNE;
9729
9730         if (reduced_clock) {
9731                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9732
9733                 if (reduced_clock->m < factor * reduced_clock->n)
9734                         fp2 |= FP_CB_TUNE;
9735         } else {
9736                 fp2 = fp;
9737         }
9738
9739         dpll = 0;
9740
9741         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9742                 dpll |= DPLLB_MODE_LVDS;
9743         else
9744                 dpll |= DPLLB_MODE_DAC_SERIAL;
9745
9746         dpll |= (crtc_state->pixel_multiplier - 1)
9747                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9748
9749         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9750             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9751                 dpll |= DPLL_SDVO_HIGH_SPEED;
9752
9753         if (intel_crtc_has_dp_encoder(crtc_state))
9754                 dpll |= DPLL_SDVO_HIGH_SPEED;
9755
9756         /*
9757          * The high speed IO clock is only really required for
9758          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9759          * possible to share the DPLL between CRT and HDMI. Enabling
9760          * the clock needlessly does no real harm, except use up a
9761          * bit of power potentially.
9762          *
9763          * We'll limit this to IVB with 3 pipes, since it has only two
9764          * DPLLs and so DPLL sharing is the only way to get three pipes
9765          * driving PCH ports at the same time. On SNB we could do this,
9766          * and potentially avoid enabling the second DPLL, but it's not
9767          * clear if it''s a win or loss power wise. No point in doing
9768          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9769          */
9770         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
9771             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9772                 dpll |= DPLL_SDVO_HIGH_SPEED;
9773
9774         /* compute bitmask from p1 value */
9775         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9776         /* also FPA1 */
9777         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9778
9779         switch (crtc_state->dpll.p2) {
9780         case 5:
9781                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9782                 break;
9783         case 7:
9784                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9785                 break;
9786         case 10:
9787                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9788                 break;
9789         case 14:
9790                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9791                 break;
9792         }
9793
9794         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9795             intel_panel_use_ssc(dev_priv))
9796                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9797         else
9798                 dpll |= PLL_REF_INPUT_DREFCLK;
9799
9800         dpll |= DPLL_VCO_ENABLE;
9801
9802         crtc_state->dpll_hw_state.dpll = dpll;
9803         crtc_state->dpll_hw_state.fp0 = fp;
9804         crtc_state->dpll_hw_state.fp1 = fp2;
9805 }
9806
9807 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9808                                        struct intel_crtc_state *crtc_state)
9809 {
9810         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9811         struct intel_atomic_state *state =
9812                 to_intel_atomic_state(crtc_state->uapi.state);
9813         const struct intel_limit *limit;
9814         int refclk = 120000;
9815
9816         memset(&crtc_state->dpll_hw_state, 0,
9817                sizeof(crtc_state->dpll_hw_state));
9818
9819         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9820         if (!crtc_state->has_pch_encoder)
9821                 return 0;
9822
9823         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9824                 if (intel_panel_use_ssc(dev_priv)) {
9825                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9826                                       dev_priv->vbt.lvds_ssc_freq);
9827                         refclk = dev_priv->vbt.lvds_ssc_freq;
9828                 }
9829
9830                 if (intel_is_dual_link_lvds(dev_priv)) {
9831                         if (refclk == 100000)
9832                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9833                         else
9834                                 limit = &intel_limits_ironlake_dual_lvds;
9835                 } else {
9836                         if (refclk == 100000)
9837                                 limit = &intel_limits_ironlake_single_lvds_100m;
9838                         else
9839                                 limit = &intel_limits_ironlake_single_lvds;
9840                 }
9841         } else {
9842                 limit = &intel_limits_ironlake_dac;
9843         }
9844
9845         if (!crtc_state->clock_set &&
9846             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9847                                 refclk, NULL, &crtc_state->dpll)) {
9848                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9849                 return -EINVAL;
9850         }
9851
9852         ironlake_compute_dpll(crtc, crtc_state, NULL);
9853
9854         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9855                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9856                               pipe_name(crtc->pipe));
9857                 return -EINVAL;
9858         }
9859
9860         return 0;
9861 }
9862
9863 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9864                                          struct intel_link_m_n *m_n)
9865 {
9866         struct drm_device *dev = crtc->base.dev;
9867         struct drm_i915_private *dev_priv = to_i915(dev);
9868         enum pipe pipe = crtc->pipe;
9869
9870         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9871         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9872         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9873                 & ~TU_SIZE_MASK;
9874         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9875         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9876                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9877 }
9878
9879 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9880                                          enum transcoder transcoder,
9881                                          struct intel_link_m_n *m_n,
9882                                          struct intel_link_m_n *m2_n2)
9883 {
9884         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9885         enum pipe pipe = crtc->pipe;
9886
9887         if (INTEL_GEN(dev_priv) >= 5) {
9888                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9889                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9890                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9891                         & ~TU_SIZE_MASK;
9892                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9893                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9894                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9895
9896                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9897                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9898                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9899                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9900                                         & ~TU_SIZE_MASK;
9901                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9902                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9903                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9904                 }
9905         } else {
9906                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9907                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9908                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9909                         & ~TU_SIZE_MASK;
9910                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9911                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9912                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9913         }
9914 }
9915
9916 void intel_dp_get_m_n(struct intel_crtc *crtc,
9917                       struct intel_crtc_state *pipe_config)
9918 {
9919         if (pipe_config->has_pch_encoder)
9920                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9921         else
9922                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9923                                              &pipe_config->dp_m_n,
9924                                              &pipe_config->dp_m2_n2);
9925 }
9926
9927 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9928                                         struct intel_crtc_state *pipe_config)
9929 {
9930         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9931                                      &pipe_config->fdi_m_n, NULL);
9932 }
9933
9934 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9935                                     struct intel_crtc_state *pipe_config)
9936 {
9937         struct drm_device *dev = crtc->base.dev;
9938         struct drm_i915_private *dev_priv = to_i915(dev);
9939         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9940         u32 ps_ctrl = 0;
9941         int id = -1;
9942         int i;
9943
9944         /* find scaler attached to this pipe */
9945         for (i = 0; i < crtc->num_scalers; i++) {
9946                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9947                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9948                         id = i;
9949                         pipe_config->pch_pfit.enabled = true;
9950                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9951                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9952                         scaler_state->scalers[i].in_use = true;
9953                         break;
9954                 }
9955         }
9956
9957         scaler_state->scaler_id = id;
9958         if (id >= 0) {
9959                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9960         } else {
9961                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9962         }
9963 }
9964
9965 static void
9966 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9967                                  struct intel_initial_plane_config *plane_config)
9968 {
9969         struct drm_device *dev = crtc->base.dev;
9970         struct drm_i915_private *dev_priv = to_i915(dev);
9971         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9972         enum plane_id plane_id = plane->id;
9973         enum pipe pipe;
9974         u32 val, base, offset, stride_mult, tiling, alpha;
9975         int fourcc, pixel_format;
9976         unsigned int aligned_height;
9977         struct drm_framebuffer *fb;
9978         struct intel_framebuffer *intel_fb;
9979
9980         if (!plane->get_hw_state(plane, &pipe))
9981                 return;
9982
9983         WARN_ON(pipe != crtc->pipe);
9984
9985         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9986         if (!intel_fb) {
9987                 DRM_DEBUG_KMS("failed to alloc fb\n");
9988                 return;
9989         }
9990
9991         fb = &intel_fb->base;
9992
9993         fb->dev = dev;
9994
9995         val = I915_READ(PLANE_CTL(pipe, plane_id));
9996
9997         if (INTEL_GEN(dev_priv) >= 11)
9998                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9999         else
10000                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10001
10002         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10003                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
10004                 alpha &= PLANE_COLOR_ALPHA_MASK;
10005         } else {
10006                 alpha = val & PLANE_CTL_ALPHA_MASK;
10007         }
10008
10009         fourcc = skl_format_to_fourcc(pixel_format,
10010                                       val & PLANE_CTL_ORDER_RGBX, alpha);
10011         fb->format = drm_format_info(fourcc);
10012
10013         tiling = val & PLANE_CTL_TILED_MASK;
10014         switch (tiling) {
10015         case PLANE_CTL_TILED_LINEAR:
10016                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10017                 break;
10018         case PLANE_CTL_TILED_X:
10019                 plane_config->tiling = I915_TILING_X;
10020                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10021                 break;
10022         case PLANE_CTL_TILED_Y:
10023                 plane_config->tiling = I915_TILING_Y;
10024                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10025                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
10026                 else
10027                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10028                 break;
10029         case PLANE_CTL_TILED_YF:
10030                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10031                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10032                 else
10033                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10034                 break;
10035         default:
10036                 MISSING_CASE(tiling);
10037                 goto error;
10038         }
10039
10040         /*
10041          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10042          * while i915 HW rotation is clockwise, thats why this swapping.
10043          */
10044         switch (val & PLANE_CTL_ROTATE_MASK) {
10045         case PLANE_CTL_ROTATE_0:
10046                 plane_config->rotation = DRM_MODE_ROTATE_0;
10047                 break;
10048         case PLANE_CTL_ROTATE_90:
10049                 plane_config->rotation = DRM_MODE_ROTATE_270;
10050                 break;
10051         case PLANE_CTL_ROTATE_180:
10052                 plane_config->rotation = DRM_MODE_ROTATE_180;
10053                 break;
10054         case PLANE_CTL_ROTATE_270:
10055                 plane_config->rotation = DRM_MODE_ROTATE_90;
10056                 break;
10057         }
10058
10059         if (INTEL_GEN(dev_priv) >= 10 &&
10060             val & PLANE_CTL_FLIP_HORIZONTAL)
10061                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10062
10063         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10064         plane_config->base = base;
10065
10066         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
10067
10068         val = I915_READ(PLANE_SIZE(pipe, plane_id));
10069         fb->height = ((val >> 16) & 0xffff) + 1;
10070         fb->width = ((val >> 0) & 0xffff) + 1;
10071
10072         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
10073         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10074         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10075
10076         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10077
10078         plane_config->size = fb->pitches[0] * aligned_height;
10079
10080         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10081                       crtc->base.name, plane->base.name, fb->width, fb->height,
10082                       fb->format->cpp[0] * 8, base, fb->pitches[0],
10083                       plane_config->size);
10084
10085         plane_config->fb = intel_fb;
10086         return;
10087
10088 error:
10089         kfree(intel_fb);
10090 }
10091
10092 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
10093                                      struct intel_crtc_state *pipe_config)
10094 {
10095         struct drm_device *dev = crtc->base.dev;
10096         struct drm_i915_private *dev_priv = to_i915(dev);
10097         u32 tmp;
10098
10099         tmp = I915_READ(PF_CTL(crtc->pipe));
10100
10101         if (tmp & PF_ENABLE) {
10102                 pipe_config->pch_pfit.enabled = true;
10103                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
10104                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
10105
10106                 /* We currently do not free assignements of panel fitters on
10107                  * ivb/hsw (since we don't use the higher upscaling modes which
10108                  * differentiates them) so just WARN about this case for now. */
10109                 if (IS_GEN(dev_priv, 7)) {
10110                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
10111                                 PF_PIPE_SEL_IVB(crtc->pipe));
10112                 }
10113         }
10114 }
10115
10116 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
10117                                      struct intel_crtc_state *pipe_config)
10118 {
10119         struct drm_device *dev = crtc->base.dev;
10120         struct drm_i915_private *dev_priv = to_i915(dev);
10121         enum intel_display_power_domain power_domain;
10122         intel_wakeref_t wakeref;
10123         u32 tmp;
10124         bool ret;
10125
10126         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10127         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10128         if (!wakeref)
10129                 return false;
10130
10131         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10132         pipe_config->shared_dpll = NULL;
10133         pipe_config->master_transcoder = INVALID_TRANSCODER;
10134
10135         ret = false;
10136         tmp = I915_READ(PIPECONF(crtc->pipe));
10137         if (!(tmp & PIPECONF_ENABLE))
10138                 goto out;
10139
10140         switch (tmp & PIPECONF_BPC_MASK) {
10141         case PIPECONF_6BPC:
10142                 pipe_config->pipe_bpp = 18;
10143                 break;
10144         case PIPECONF_8BPC:
10145                 pipe_config->pipe_bpp = 24;
10146                 break;
10147         case PIPECONF_10BPC:
10148                 pipe_config->pipe_bpp = 30;
10149                 break;
10150         case PIPECONF_12BPC:
10151                 pipe_config->pipe_bpp = 36;
10152                 break;
10153         default:
10154                 break;
10155         }
10156
10157         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10158                 pipe_config->limited_color_range = true;
10159
10160         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10161         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10162         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10163                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10164                 break;
10165         default:
10166                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10167                 break;
10168         }
10169
10170         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10171                 PIPECONF_GAMMA_MODE_SHIFT;
10172
10173         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10174
10175         i9xx_get_pipe_color_config(pipe_config);
10176         intel_color_get_config(pipe_config);
10177
10178         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10179                 struct intel_shared_dpll *pll;
10180                 enum intel_dpll_id pll_id;
10181
10182                 pipe_config->has_pch_encoder = true;
10183
10184                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
10185                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10186                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10187
10188                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10189
10190                 if (HAS_PCH_IBX(dev_priv)) {
10191                         /*
10192                          * The pipe->pch transcoder and pch transcoder->pll
10193                          * mapping is fixed.
10194                          */
10195                         pll_id = (enum intel_dpll_id) crtc->pipe;
10196                 } else {
10197                         tmp = I915_READ(PCH_DPLL_SEL);
10198                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10199                                 pll_id = DPLL_ID_PCH_PLL_B;
10200                         else
10201                                 pll_id= DPLL_ID_PCH_PLL_A;
10202                 }
10203
10204                 pipe_config->shared_dpll =
10205                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10206                 pll = pipe_config->shared_dpll;
10207
10208                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10209                                                 &pipe_config->dpll_hw_state));
10210
10211                 tmp = pipe_config->dpll_hw_state.dpll;
10212                 pipe_config->pixel_multiplier =
10213                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10214                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10215
10216                 ironlake_pch_clock_get(crtc, pipe_config);
10217         } else {
10218                 pipe_config->pixel_multiplier = 1;
10219         }
10220
10221         intel_get_pipe_timings(crtc, pipe_config);
10222         intel_get_pipe_src_size(crtc, pipe_config);
10223
10224         ironlake_get_pfit_config(crtc, pipe_config);
10225
10226         ret = true;
10227
10228 out:
10229         intel_display_power_put(dev_priv, power_domain, wakeref);
10230
10231         return ret;
10232 }
10233 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10234                                       struct intel_crtc_state *crtc_state)
10235 {
10236         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10237         struct intel_atomic_state *state =
10238                 to_intel_atomic_state(crtc_state->uapi.state);
10239
10240         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10241             INTEL_GEN(dev_priv) >= 11) {
10242                 struct intel_encoder *encoder =
10243                         intel_get_crtc_new_encoder(state, crtc_state);
10244
10245                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10246                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10247                                       pipe_name(crtc->pipe));
10248                         return -EINVAL;
10249                 }
10250         }
10251
10252         return 0;
10253 }
10254
10255 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10256                                    enum port port,
10257                                    struct intel_crtc_state *pipe_config)
10258 {
10259         enum intel_dpll_id id;
10260         u32 temp;
10261
10262         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10263         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10264
10265         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10266                 return;
10267
10268         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10269 }
10270
10271 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10272                                 enum port port,
10273                                 struct intel_crtc_state *pipe_config)
10274 {
10275         enum phy phy = intel_port_to_phy(dev_priv, port);
10276         enum icl_port_dpll_id port_dpll_id;
10277         enum intel_dpll_id id;
10278         u32 temp;
10279
10280         if (intel_phy_is_combo(dev_priv, phy)) {
10281                 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10282                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10283                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10284                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10285         } else if (intel_phy_is_tc(dev_priv, phy)) {
10286                 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10287
10288                 if (clk_sel == DDI_CLK_SEL_MG) {
10289                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10290                                                                     port));
10291                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10292                 } else {
10293                         WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10294                         id = DPLL_ID_ICL_TBTPLL;
10295                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10296                 }
10297         } else {
10298                 WARN(1, "Invalid port %x\n", port);
10299                 return;
10300         }
10301
10302         pipe_config->icl_port_dplls[port_dpll_id].pll =
10303                 intel_get_shared_dpll_by_id(dev_priv, id);
10304
10305         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10306 }
10307
10308 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10309                                 enum port port,
10310                                 struct intel_crtc_state *pipe_config)
10311 {
10312         enum intel_dpll_id id;
10313
10314         switch (port) {
10315         case PORT_A:
10316                 id = DPLL_ID_SKL_DPLL0;
10317                 break;
10318         case PORT_B:
10319                 id = DPLL_ID_SKL_DPLL1;
10320                 break;
10321         case PORT_C:
10322                 id = DPLL_ID_SKL_DPLL2;
10323                 break;
10324         default:
10325                 DRM_ERROR("Incorrect port type\n");
10326                 return;
10327         }
10328
10329         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10330 }
10331
10332 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10333                                 enum port port,
10334                                 struct intel_crtc_state *pipe_config)
10335 {
10336         enum intel_dpll_id id;
10337         u32 temp;
10338
10339         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10340         id = temp >> (port * 3 + 1);
10341
10342         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10343                 return;
10344
10345         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10346 }
10347
10348 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10349                                 enum port port,
10350                                 struct intel_crtc_state *pipe_config)
10351 {
10352         enum intel_dpll_id id;
10353         u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10354
10355         switch (ddi_pll_sel) {
10356         case PORT_CLK_SEL_WRPLL1:
10357                 id = DPLL_ID_WRPLL1;
10358                 break;
10359         case PORT_CLK_SEL_WRPLL2:
10360                 id = DPLL_ID_WRPLL2;
10361                 break;
10362         case PORT_CLK_SEL_SPLL:
10363                 id = DPLL_ID_SPLL;
10364                 break;
10365         case PORT_CLK_SEL_LCPLL_810:
10366                 id = DPLL_ID_LCPLL_810;
10367                 break;
10368         case PORT_CLK_SEL_LCPLL_1350:
10369                 id = DPLL_ID_LCPLL_1350;
10370                 break;
10371         case PORT_CLK_SEL_LCPLL_2700:
10372                 id = DPLL_ID_LCPLL_2700;
10373                 break;
10374         default:
10375                 MISSING_CASE(ddi_pll_sel);
10376                 /* fall through */
10377         case PORT_CLK_SEL_NONE:
10378                 return;
10379         }
10380
10381         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10382 }
10383
10384 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10385                                      struct intel_crtc_state *pipe_config,
10386                                      u64 *power_domain_mask,
10387                                      intel_wakeref_t *wakerefs)
10388 {
10389         struct drm_device *dev = crtc->base.dev;
10390         struct drm_i915_private *dev_priv = to_i915(dev);
10391         enum intel_display_power_domain power_domain;
10392         unsigned long panel_transcoder_mask = 0;
10393         unsigned long enabled_panel_transcoders = 0;
10394         enum transcoder panel_transcoder;
10395         intel_wakeref_t wf;
10396         u32 tmp;
10397
10398         if (INTEL_GEN(dev_priv) >= 11)
10399                 panel_transcoder_mask |=
10400                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10401
10402         if (HAS_TRANSCODER_EDP(dev_priv))
10403                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10404
10405         /*
10406          * The pipe->transcoder mapping is fixed with the exception of the eDP
10407          * and DSI transcoders handled below.
10408          */
10409         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10410
10411         /*
10412          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10413          * consistency and less surprising code; it's in always on power).
10414          */
10415         for_each_set_bit(panel_transcoder,
10416                          &panel_transcoder_mask,
10417                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10418                 bool force_thru = false;
10419                 enum pipe trans_pipe;
10420
10421                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10422                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10423                         continue;
10424
10425                 /*
10426                  * Log all enabled ones, only use the first one.
10427                  *
10428                  * FIXME: This won't work for two separate DSI displays.
10429                  */
10430                 enabled_panel_transcoders |= BIT(panel_transcoder);
10431                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10432                         continue;
10433
10434                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10435                 default:
10436                         WARN(1, "unknown pipe linked to transcoder %s\n",
10437                              transcoder_name(panel_transcoder));
10438                         /* fall through */
10439                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10440                         force_thru = true;
10441                         /* fall through */
10442                 case TRANS_DDI_EDP_INPUT_A_ON:
10443                         trans_pipe = PIPE_A;
10444                         break;
10445                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10446                         trans_pipe = PIPE_B;
10447                         break;
10448                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10449                         trans_pipe = PIPE_C;
10450                         break;
10451                 }
10452
10453                 if (trans_pipe == crtc->pipe) {
10454                         pipe_config->cpu_transcoder = panel_transcoder;
10455                         pipe_config->pch_pfit.force_thru = force_thru;
10456                 }
10457         }
10458
10459         /*
10460          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10461          */
10462         WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10463                 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10464
10465         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10466         WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10467
10468         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10469         if (!wf)
10470                 return false;
10471
10472         wakerefs[power_domain] = wf;
10473         *power_domain_mask |= BIT_ULL(power_domain);
10474
10475         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10476
10477         return tmp & PIPECONF_ENABLE;
10478 }
10479
10480 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10481                                          struct intel_crtc_state *pipe_config,
10482                                          u64 *power_domain_mask,
10483                                          intel_wakeref_t *wakerefs)
10484 {
10485         struct drm_device *dev = crtc->base.dev;
10486         struct drm_i915_private *dev_priv = to_i915(dev);
10487         enum intel_display_power_domain power_domain;
10488         enum transcoder cpu_transcoder;
10489         intel_wakeref_t wf;
10490         enum port port;
10491         u32 tmp;
10492
10493         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10494                 if (port == PORT_A)
10495                         cpu_transcoder = TRANSCODER_DSI_A;
10496                 else
10497                         cpu_transcoder = TRANSCODER_DSI_C;
10498
10499                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10500                 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10501
10502                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10503                 if (!wf)
10504                         continue;
10505
10506                 wakerefs[power_domain] = wf;
10507                 *power_domain_mask |= BIT_ULL(power_domain);
10508
10509                 /*
10510                  * The PLL needs to be enabled with a valid divider
10511                  * configuration, otherwise accessing DSI registers will hang
10512                  * the machine. See BSpec North Display Engine
10513                  * registers/MIPI[BXT]. We can break out here early, since we
10514                  * need the same DSI PLL to be enabled for both DSI ports.
10515                  */
10516                 if (!bxt_dsi_pll_is_enabled(dev_priv))
10517                         break;
10518
10519                 /* XXX: this works for video mode only */
10520                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10521                 if (!(tmp & DPI_ENABLE))
10522                         continue;
10523
10524                 tmp = I915_READ(MIPI_CTRL(port));
10525                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10526                         continue;
10527
10528                 pipe_config->cpu_transcoder = cpu_transcoder;
10529                 break;
10530         }
10531
10532         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10533 }
10534
10535 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10536                                        struct intel_crtc_state *pipe_config)
10537 {
10538         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10539         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
10540         struct intel_shared_dpll *pll;
10541         enum port port;
10542         u32 tmp;
10543
10544         if (transcoder_is_dsi(cpu_transcoder)) {
10545                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
10546                                                 PORT_A : PORT_B;
10547         } else {
10548                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
10549                 if (INTEL_GEN(dev_priv) >= 12)
10550                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10551                 else
10552                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10553         }
10554
10555         if (INTEL_GEN(dev_priv) >= 11)
10556                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10557         else if (IS_CANNONLAKE(dev_priv))
10558                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10559         else if (IS_GEN9_BC(dev_priv))
10560                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10561         else if (IS_GEN9_LP(dev_priv))
10562                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10563         else
10564                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10565
10566         pll = pipe_config->shared_dpll;
10567         if (pll) {
10568                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10569                                                 &pipe_config->dpll_hw_state));
10570         }
10571
10572         /*
10573          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10574          * DDI E. So just check whether this pipe is wired to DDI E and whether
10575          * the PCH transcoder is on.
10576          */
10577         if (INTEL_GEN(dev_priv) < 9 &&
10578             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10579                 pipe_config->has_pch_encoder = true;
10580
10581                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10582                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10583                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10584
10585                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10586         }
10587 }
10588
10589 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
10590                                                  enum transcoder cpu_transcoder)
10591 {
10592         u32 trans_port_sync, master_select;
10593
10594         trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
10595
10596         if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
10597                 return INVALID_TRANSCODER;
10598
10599         master_select = trans_port_sync &
10600                         PORT_SYNC_MODE_MASTER_SELECT_MASK;
10601         if (master_select == 0)
10602                 return TRANSCODER_EDP;
10603         else
10604                 return master_select - 1;
10605 }
10606
10607 static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
10608 {
10609         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
10610         u32 transcoders;
10611         enum transcoder cpu_transcoder;
10612
10613         crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
10614                                                                   crtc_state->cpu_transcoder);
10615
10616         transcoders = BIT(TRANSCODER_A) |
10617                 BIT(TRANSCODER_B) |
10618                 BIT(TRANSCODER_C) |
10619                 BIT(TRANSCODER_D);
10620         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
10621                 enum intel_display_power_domain power_domain;
10622                 intel_wakeref_t trans_wakeref;
10623
10624                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10625                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
10626                                                                    power_domain);
10627
10628                 if (!trans_wakeref)
10629                         continue;
10630
10631                 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
10632                     crtc_state->cpu_transcoder)
10633                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
10634
10635                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
10636         }
10637
10638         WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
10639                 crtc_state->sync_mode_slaves_mask);
10640 }
10641
10642 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10643                                     struct intel_crtc_state *pipe_config)
10644 {
10645         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10646         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10647         enum intel_display_power_domain power_domain;
10648         u64 power_domain_mask;
10649         bool active;
10650
10651         intel_crtc_init_scalers(crtc, pipe_config);
10652
10653         pipe_config->master_transcoder = INVALID_TRANSCODER;
10654
10655         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10656         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10657         if (!wf)
10658                 return false;
10659
10660         wakerefs[power_domain] = wf;
10661         power_domain_mask = BIT_ULL(power_domain);
10662
10663         pipe_config->shared_dpll = NULL;
10664
10665         active = hsw_get_transcoder_state(crtc, pipe_config,
10666                                           &power_domain_mask, wakerefs);
10667
10668         if (IS_GEN9_LP(dev_priv) &&
10669             bxt_get_dsi_transcoder_state(crtc, pipe_config,
10670                                          &power_domain_mask, wakerefs)) {
10671                 WARN_ON(active);
10672                 active = true;
10673         }
10674
10675         if (!active)
10676                 goto out;
10677
10678         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10679             INTEL_GEN(dev_priv) >= 11) {
10680                 haswell_get_ddi_port_state(crtc, pipe_config);
10681                 intel_get_pipe_timings(crtc, pipe_config);
10682         }
10683
10684         intel_get_pipe_src_size(crtc, pipe_config);
10685
10686         if (IS_HASWELL(dev_priv)) {
10687                 u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10688
10689                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
10690                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10691                 else
10692                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10693         } else {
10694                 pipe_config->output_format =
10695                         bdw_get_pipemisc_output_format(crtc);
10696
10697                 /*
10698                  * Currently there is no interface defined to
10699                  * check user preference between RGB/YCBCR444
10700                  * or YCBCR420. So the only possible case for
10701                  * YCBCR444 usage is driving YCBCR420 output
10702                  * with LSPCON, when pipe is configured for
10703                  * YCBCR444 output and LSPCON takes care of
10704                  * downsampling it.
10705                  */
10706                 pipe_config->lspcon_downsampling =
10707                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
10708         }
10709
10710         pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10711
10712         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10713
10714         if (INTEL_GEN(dev_priv) >= 9) {
10715                 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10716
10717                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10718                         pipe_config->gamma_enable = true;
10719
10720                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10721                         pipe_config->csc_enable = true;
10722         } else {
10723                 i9xx_get_pipe_color_config(pipe_config);
10724         }
10725
10726         intel_color_get_config(pipe_config);
10727
10728         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10729         WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10730
10731         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10732         if (wf) {
10733                 wakerefs[power_domain] = wf;
10734                 power_domain_mask |= BIT_ULL(power_domain);
10735
10736                 if (INTEL_GEN(dev_priv) >= 9)
10737                         skylake_get_pfit_config(crtc, pipe_config);
10738                 else
10739                         ironlake_get_pfit_config(crtc, pipe_config);
10740         }
10741
10742         if (hsw_crtc_supports_ips(crtc)) {
10743                 if (IS_HASWELL(dev_priv))
10744                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10745                 else {
10746                         /*
10747                          * We cannot readout IPS state on broadwell, set to
10748                          * true so we can set it to a defined state on first
10749                          * commit.
10750                          */
10751                         pipe_config->ips_enabled = true;
10752                 }
10753         }
10754
10755         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10756             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10757                 pipe_config->pixel_multiplier =
10758                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10759         } else {
10760                 pipe_config->pixel_multiplier = 1;
10761         }
10762
10763         if (INTEL_GEN(dev_priv) >= 11 &&
10764             !transcoder_is_dsi(pipe_config->cpu_transcoder))
10765                 icelake_get_trans_port_sync_config(pipe_config);
10766
10767 out:
10768         for_each_power_domain(power_domain, power_domain_mask)
10769                 intel_display_power_put(dev_priv,
10770                                         power_domain, wakerefs[power_domain]);
10771
10772         return active;
10773 }
10774
10775 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10776 {
10777         struct drm_i915_private *dev_priv =
10778                 to_i915(plane_state->uapi.plane->dev);
10779         const struct drm_framebuffer *fb = plane_state->hw.fb;
10780         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10781         u32 base;
10782
10783         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10784                 base = obj->phys_handle->busaddr;
10785         else
10786                 base = intel_plane_ggtt_offset(plane_state);
10787
10788         return base + plane_state->color_plane[0].offset;
10789 }
10790
10791 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10792 {
10793         int x = plane_state->uapi.dst.x1;
10794         int y = plane_state->uapi.dst.y1;
10795         u32 pos = 0;
10796
10797         if (x < 0) {
10798                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10799                 x = -x;
10800         }
10801         pos |= x << CURSOR_X_SHIFT;
10802
10803         if (y < 0) {
10804                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10805                 y = -y;
10806         }
10807         pos |= y << CURSOR_Y_SHIFT;
10808
10809         return pos;
10810 }
10811
10812 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10813 {
10814         const struct drm_mode_config *config =
10815                 &plane_state->uapi.plane->dev->mode_config;
10816         int width = drm_rect_width(&plane_state->uapi.dst);
10817         int height = drm_rect_height(&plane_state->uapi.dst);
10818
10819         return width > 0 && width <= config->cursor_width &&
10820                 height > 0 && height <= config->cursor_height;
10821 }
10822
10823 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10824 {
10825         struct drm_i915_private *dev_priv =
10826                 to_i915(plane_state->uapi.plane->dev);
10827         unsigned int rotation = plane_state->hw.rotation;
10828         int src_x, src_y;
10829         u32 offset;
10830         int ret;
10831
10832         ret = intel_plane_compute_gtt(plane_state);
10833         if (ret)
10834                 return ret;
10835
10836         if (!plane_state->uapi.visible)
10837                 return 0;
10838
10839         src_x = plane_state->uapi.src.x1 >> 16;
10840         src_y = plane_state->uapi.src.y1 >> 16;
10841
10842         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10843         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10844                                                     plane_state, 0);
10845
10846         if (src_x != 0 || src_y != 0) {
10847                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10848                 return -EINVAL;
10849         }
10850
10851         /*
10852          * Put the final coordinates back so that the src
10853          * coordinate checks will see the right values.
10854          */
10855         drm_rect_translate_to(&plane_state->uapi.src,
10856                               src_x << 16, src_y << 16);
10857
10858         /* ILK+ do this automagically in hardware */
10859         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
10860                 const struct drm_framebuffer *fb = plane_state->hw.fb;
10861                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
10862                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
10863
10864                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
10865         }
10866
10867         plane_state->color_plane[0].offset = offset;
10868         plane_state->color_plane[0].x = src_x;
10869         plane_state->color_plane[0].y = src_y;
10870
10871         return 0;
10872 }
10873
10874 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10875                               struct intel_plane_state *plane_state)
10876 {
10877         const struct drm_framebuffer *fb = plane_state->hw.fb;
10878         int ret;
10879
10880         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10881                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10882                 return -EINVAL;
10883         }
10884
10885         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
10886                                                   &crtc_state->uapi,
10887                                                   DRM_PLANE_HELPER_NO_SCALING,
10888                                                   DRM_PLANE_HELPER_NO_SCALING,
10889                                                   true, true);
10890         if (ret)
10891                 return ret;
10892
10893         /* Use the unclipped src/dst rectangles, which we program to hw */
10894         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
10895         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
10896
10897         ret = intel_cursor_check_surface(plane_state);
10898         if (ret)
10899                 return ret;
10900
10901         if (!plane_state->uapi.visible)
10902                 return 0;
10903
10904         ret = intel_plane_check_src_coordinates(plane_state);
10905         if (ret)
10906                 return ret;
10907
10908         return 0;
10909 }
10910
10911 static unsigned int
10912 i845_cursor_max_stride(struct intel_plane *plane,
10913                        u32 pixel_format, u64 modifier,
10914                        unsigned int rotation)
10915 {
10916         return 2048;
10917 }
10918
10919 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10920 {
10921         u32 cntl = 0;
10922
10923         if (crtc_state->gamma_enable)
10924                 cntl |= CURSOR_GAMMA_ENABLE;
10925
10926         return cntl;
10927 }
10928
10929 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10930                            const struct intel_plane_state *plane_state)
10931 {
10932         return CURSOR_ENABLE |
10933                 CURSOR_FORMAT_ARGB |
10934                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10935 }
10936
10937 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10938 {
10939         int width = drm_rect_width(&plane_state->uapi.dst);
10940
10941         /*
10942          * 845g/865g are only limited by the width of their cursors,
10943          * the height is arbitrary up to the precision of the register.
10944          */
10945         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10946 }
10947
10948 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10949                              struct intel_plane_state *plane_state)
10950 {
10951         const struct drm_framebuffer *fb = plane_state->hw.fb;
10952         int ret;
10953
10954         ret = intel_check_cursor(crtc_state, plane_state);
10955         if (ret)
10956                 return ret;
10957
10958         /* if we want to turn off the cursor ignore width and height */
10959         if (!fb)
10960                 return 0;
10961
10962         /* Check for which cursor types we support */
10963         if (!i845_cursor_size_ok(plane_state)) {
10964                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10965                           drm_rect_width(&plane_state->uapi.dst),
10966                           drm_rect_height(&plane_state->uapi.dst));
10967                 return -EINVAL;
10968         }
10969
10970         WARN_ON(plane_state->uapi.visible &&
10971                 plane_state->color_plane[0].stride != fb->pitches[0]);
10972
10973         switch (fb->pitches[0]) {
10974         case 256:
10975         case 512:
10976         case 1024:
10977         case 2048:
10978                 break;
10979         default:
10980                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10981                               fb->pitches[0]);
10982                 return -EINVAL;
10983         }
10984
10985         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10986
10987         return 0;
10988 }
10989
10990 static void i845_update_cursor(struct intel_plane *plane,
10991                                const struct intel_crtc_state *crtc_state,
10992                                const struct intel_plane_state *plane_state)
10993 {
10994         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10995         u32 cntl = 0, base = 0, pos = 0, size = 0;
10996         unsigned long irqflags;
10997
10998         if (plane_state && plane_state->uapi.visible) {
10999                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11000                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11001
11002                 cntl = plane_state->ctl |
11003                         i845_cursor_ctl_crtc(crtc_state);
11004
11005                 size = (height << 12) | width;
11006
11007                 base = intel_cursor_base(plane_state);
11008                 pos = intel_cursor_position(plane_state);
11009         }
11010
11011         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11012
11013         /* On these chipsets we can only modify the base/size/stride
11014          * whilst the cursor is disabled.
11015          */
11016         if (plane->cursor.base != base ||
11017             plane->cursor.size != size ||
11018             plane->cursor.cntl != cntl) {
11019                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
11020                 I915_WRITE_FW(CURBASE(PIPE_A), base);
11021                 I915_WRITE_FW(CURSIZE, size);
11022                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11023                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
11024
11025                 plane->cursor.base = base;
11026                 plane->cursor.size = size;
11027                 plane->cursor.cntl = cntl;
11028         } else {
11029                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11030         }
11031
11032         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11033 }
11034
11035 static void i845_disable_cursor(struct intel_plane *plane,
11036                                 const struct intel_crtc_state *crtc_state)
11037 {
11038         i845_update_cursor(plane, crtc_state, NULL);
11039 }
11040
11041 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11042                                      enum pipe *pipe)
11043 {
11044         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11045         enum intel_display_power_domain power_domain;
11046         intel_wakeref_t wakeref;
11047         bool ret;
11048
11049         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11050         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11051         if (!wakeref)
11052                 return false;
11053
11054         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11055
11056         *pipe = PIPE_A;
11057
11058         intel_display_power_put(dev_priv, power_domain, wakeref);
11059
11060         return ret;
11061 }
11062
11063 static unsigned int
11064 i9xx_cursor_max_stride(struct intel_plane *plane,
11065                        u32 pixel_format, u64 modifier,
11066                        unsigned int rotation)
11067 {
11068         return plane->base.dev->mode_config.cursor_width * 4;
11069 }
11070
11071 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11072 {
11073         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11075         u32 cntl = 0;
11076
11077         if (INTEL_GEN(dev_priv) >= 11)
11078                 return cntl;
11079
11080         if (crtc_state->gamma_enable)
11081                 cntl = MCURSOR_GAMMA_ENABLE;
11082
11083         if (crtc_state->csc_enable)
11084                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11085
11086         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11087                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11088
11089         return cntl;
11090 }
11091
11092 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11093                            const struct intel_plane_state *plane_state)
11094 {
11095         struct drm_i915_private *dev_priv =
11096                 to_i915(plane_state->uapi.plane->dev);
11097         u32 cntl = 0;
11098
11099         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11100                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11101
11102         switch (drm_rect_width(&plane_state->uapi.dst)) {
11103         case 64:
11104                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11105                 break;
11106         case 128:
11107                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11108                 break;
11109         case 256:
11110                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11111                 break;
11112         default:
11113                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11114                 return 0;
11115         }
11116
11117         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11118                 cntl |= MCURSOR_ROTATE_180;
11119
11120         return cntl;
11121 }
11122
11123 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11124 {
11125         struct drm_i915_private *dev_priv =
11126                 to_i915(plane_state->uapi.plane->dev);
11127         int width = drm_rect_width(&plane_state->uapi.dst);
11128         int height = drm_rect_height(&plane_state->uapi.dst);
11129
11130         if (!intel_cursor_size_ok(plane_state))
11131                 return false;
11132
11133         /* Cursor width is limited to a few power-of-two sizes */
11134         switch (width) {
11135         case 256:
11136         case 128:
11137         case 64:
11138                 break;
11139         default:
11140                 return false;
11141         }
11142
11143         /*
11144          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11145          * height from 8 lines up to the cursor width, when the
11146          * cursor is not rotated. Everything else requires square
11147          * cursors.
11148          */
11149         if (HAS_CUR_FBC(dev_priv) &&
11150             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11151                 if (height < 8 || height > width)
11152                         return false;
11153         } else {
11154                 if (height != width)
11155                         return false;
11156         }
11157
11158         return true;
11159 }
11160
11161 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11162                              struct intel_plane_state *plane_state)
11163 {
11164         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11165         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11166         const struct drm_framebuffer *fb = plane_state->hw.fb;
11167         enum pipe pipe = plane->pipe;
11168         int ret;
11169
11170         ret = intel_check_cursor(crtc_state, plane_state);
11171         if (ret)
11172                 return ret;
11173
11174         /* if we want to turn off the cursor ignore width and height */
11175         if (!fb)
11176                 return 0;
11177
11178         /* Check for which cursor types we support */
11179         if (!i9xx_cursor_size_ok(plane_state)) {
11180                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11181                           drm_rect_width(&plane_state->uapi.dst),
11182                           drm_rect_height(&plane_state->uapi.dst));
11183                 return -EINVAL;
11184         }
11185
11186         WARN_ON(plane_state->uapi.visible &&
11187                 plane_state->color_plane[0].stride != fb->pitches[0]);
11188
11189         if (fb->pitches[0] !=
11190             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11191                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
11192                               fb->pitches[0],
11193                               drm_rect_width(&plane_state->uapi.dst));
11194                 return -EINVAL;
11195         }
11196
11197         /*
11198          * There's something wrong with the cursor on CHV pipe C.
11199          * If it straddles the left edge of the screen then
11200          * moving it away from the edge or disabling it often
11201          * results in a pipe underrun, and often that can lead to
11202          * dead pipe (constant underrun reported, and it scans
11203          * out just a solid color). To recover from that, the
11204          * display power well must be turned off and on again.
11205          * Refuse the put the cursor into that compromised position.
11206          */
11207         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11208             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11209                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11210                 return -EINVAL;
11211         }
11212
11213         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11214
11215         return 0;
11216 }
11217
11218 static void i9xx_update_cursor(struct intel_plane *plane,
11219                                const struct intel_crtc_state *crtc_state,
11220                                const struct intel_plane_state *plane_state)
11221 {
11222         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11223         enum pipe pipe = plane->pipe;
11224         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11225         unsigned long irqflags;
11226
11227         if (plane_state && plane_state->uapi.visible) {
11228                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11229                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11230
11231                 cntl = plane_state->ctl |
11232                         i9xx_cursor_ctl_crtc(crtc_state);
11233
11234                 if (width != height)
11235                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11236
11237                 base = intel_cursor_base(plane_state);
11238                 pos = intel_cursor_position(plane_state);
11239         }
11240
11241         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11242
11243         /*
11244          * On some platforms writing CURCNTR first will also
11245          * cause CURPOS to be armed by the CURBASE write.
11246          * Without the CURCNTR write the CURPOS write would
11247          * arm itself. Thus we always update CURCNTR before
11248          * CURPOS.
11249          *
11250          * On other platforms CURPOS always requires the
11251          * CURBASE write to arm the update. Additonally
11252          * a write to any of the cursor register will cancel
11253          * an already armed cursor update. Thus leaving out
11254          * the CURBASE write after CURPOS could lead to a
11255          * cursor that doesn't appear to move, or even change
11256          * shape. Thus we always write CURBASE.
11257          *
11258          * The other registers are armed by by the CURBASE write
11259          * except when the plane is getting enabled at which time
11260          * the CURCNTR write arms the update.
11261          */
11262
11263         if (INTEL_GEN(dev_priv) >= 9)
11264                 skl_write_cursor_wm(plane, crtc_state);
11265
11266         if (plane->cursor.base != base ||
11267             plane->cursor.size != fbc_ctl ||
11268             plane->cursor.cntl != cntl) {
11269                 if (HAS_CUR_FBC(dev_priv))
11270                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
11271                 I915_WRITE_FW(CURCNTR(pipe), cntl);
11272                 I915_WRITE_FW(CURPOS(pipe), pos);
11273                 I915_WRITE_FW(CURBASE(pipe), base);
11274
11275                 plane->cursor.base = base;
11276                 plane->cursor.size = fbc_ctl;
11277                 plane->cursor.cntl = cntl;
11278         } else {
11279                 I915_WRITE_FW(CURPOS(pipe), pos);
11280                 I915_WRITE_FW(CURBASE(pipe), base);
11281         }
11282
11283         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11284 }
11285
11286 static void i9xx_disable_cursor(struct intel_plane *plane,
11287                                 const struct intel_crtc_state *crtc_state)
11288 {
11289         i9xx_update_cursor(plane, crtc_state, NULL);
11290 }
11291
11292 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11293                                      enum pipe *pipe)
11294 {
11295         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11296         enum intel_display_power_domain power_domain;
11297         intel_wakeref_t wakeref;
11298         bool ret;
11299         u32 val;
11300
11301         /*
11302          * Not 100% correct for planes that can move between pipes,
11303          * but that's only the case for gen2-3 which don't have any
11304          * display power wells.
11305          */
11306         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11307         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11308         if (!wakeref)
11309                 return false;
11310
11311         val = I915_READ(CURCNTR(plane->pipe));
11312
11313         ret = val & MCURSOR_MODE;
11314
11315         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11316                 *pipe = plane->pipe;
11317         else
11318                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11319                         MCURSOR_PIPE_SELECT_SHIFT;
11320
11321         intel_display_power_put(dev_priv, power_domain, wakeref);
11322
11323         return ret;
11324 }
11325
11326 /* VESA 640x480x72Hz mode to set on the pipe */
11327 static const struct drm_display_mode load_detect_mode = {
11328         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11329                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11330 };
11331
11332 struct drm_framebuffer *
11333 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11334                          struct drm_mode_fb_cmd2 *mode_cmd)
11335 {
11336         struct intel_framebuffer *intel_fb;
11337         int ret;
11338
11339         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11340         if (!intel_fb)
11341                 return ERR_PTR(-ENOMEM);
11342
11343         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11344         if (ret)
11345                 goto err;
11346
11347         return &intel_fb->base;
11348
11349 err:
11350         kfree(intel_fb);
11351         return ERR_PTR(ret);
11352 }
11353
11354 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11355                                         struct drm_crtc *crtc)
11356 {
11357         struct drm_plane *plane;
11358         struct drm_plane_state *plane_state;
11359         int ret, i;
11360
11361         ret = drm_atomic_add_affected_planes(state, crtc);
11362         if (ret)
11363                 return ret;
11364
11365         for_each_new_plane_in_state(state, plane, plane_state, i) {
11366                 if (plane_state->crtc != crtc)
11367                         continue;
11368
11369                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11370                 if (ret)
11371                         return ret;
11372
11373                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11374         }
11375
11376         return 0;
11377 }
11378
11379 int intel_get_load_detect_pipe(struct drm_connector *connector,
11380                                struct intel_load_detect_pipe *old,
11381                                struct drm_modeset_acquire_ctx *ctx)
11382 {
11383         struct intel_crtc *intel_crtc;
11384         struct intel_encoder *intel_encoder =
11385                 intel_attached_encoder(connector);
11386         struct drm_crtc *possible_crtc;
11387         struct drm_encoder *encoder = &intel_encoder->base;
11388         struct drm_crtc *crtc = NULL;
11389         struct drm_device *dev = encoder->dev;
11390         struct drm_i915_private *dev_priv = to_i915(dev);
11391         struct drm_mode_config *config = &dev->mode_config;
11392         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11393         struct drm_connector_state *connector_state;
11394         struct intel_crtc_state *crtc_state;
11395         int ret, i = -1;
11396
11397         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11398                       connector->base.id, connector->name,
11399                       encoder->base.id, encoder->name);
11400
11401         old->restore_state = NULL;
11402
11403         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11404
11405         /*
11406          * Algorithm gets a little messy:
11407          *
11408          *   - if the connector already has an assigned crtc, use it (but make
11409          *     sure it's on first)
11410          *
11411          *   - try to find the first unused crtc that can drive this connector,
11412          *     and use that if we find one
11413          */
11414
11415         /* See if we already have a CRTC for this connector */
11416         if (connector->state->crtc) {
11417                 crtc = connector->state->crtc;
11418
11419                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11420                 if (ret)
11421                         goto fail;
11422
11423                 /* Make sure the crtc and connector are running */
11424                 goto found;
11425         }
11426
11427         /* Find an unused one (if possible) */
11428         for_each_crtc(dev, possible_crtc) {
11429                 i++;
11430                 if (!(encoder->possible_crtcs & (1 << i)))
11431                         continue;
11432
11433                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11434                 if (ret)
11435                         goto fail;
11436
11437                 if (possible_crtc->state->enable) {
11438                         drm_modeset_unlock(&possible_crtc->mutex);
11439                         continue;
11440                 }
11441
11442                 crtc = possible_crtc;
11443                 break;
11444         }
11445
11446         /*
11447          * If we didn't find an unused CRTC, don't use any.
11448          */
11449         if (!crtc) {
11450                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11451                 ret = -ENODEV;
11452                 goto fail;
11453         }
11454
11455 found:
11456         intel_crtc = to_intel_crtc(crtc);
11457
11458         state = drm_atomic_state_alloc(dev);
11459         restore_state = drm_atomic_state_alloc(dev);
11460         if (!state || !restore_state) {
11461                 ret = -ENOMEM;
11462                 goto fail;
11463         }
11464
11465         state->acquire_ctx = ctx;
11466         restore_state->acquire_ctx = ctx;
11467
11468         connector_state = drm_atomic_get_connector_state(state, connector);
11469         if (IS_ERR(connector_state)) {
11470                 ret = PTR_ERR(connector_state);
11471                 goto fail;
11472         }
11473
11474         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11475         if (ret)
11476                 goto fail;
11477
11478         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11479         if (IS_ERR(crtc_state)) {
11480                 ret = PTR_ERR(crtc_state);
11481                 goto fail;
11482         }
11483
11484         crtc_state->uapi.active = true;
11485
11486         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11487                                            &load_detect_mode);
11488         if (ret)
11489                 goto fail;
11490
11491         ret = intel_modeset_disable_planes(state, crtc);
11492         if (ret)
11493                 goto fail;
11494
11495         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11496         if (!ret)
11497                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11498         if (!ret)
11499                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11500         if (ret) {
11501                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11502                 goto fail;
11503         }
11504
11505         ret = drm_atomic_commit(state);
11506         if (ret) {
11507                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11508                 goto fail;
11509         }
11510
11511         old->restore_state = restore_state;
11512         drm_atomic_state_put(state);
11513
11514         /* let the connector get through one full cycle before testing */
11515         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11516         return true;
11517
11518 fail:
11519         if (state) {
11520                 drm_atomic_state_put(state);
11521                 state = NULL;
11522         }
11523         if (restore_state) {
11524                 drm_atomic_state_put(restore_state);
11525                 restore_state = NULL;
11526         }
11527
11528         if (ret == -EDEADLK)
11529                 return ret;
11530
11531         return false;
11532 }
11533
11534 void intel_release_load_detect_pipe(struct drm_connector *connector,
11535                                     struct intel_load_detect_pipe *old,
11536                                     struct drm_modeset_acquire_ctx *ctx)
11537 {
11538         struct intel_encoder *intel_encoder =
11539                 intel_attached_encoder(connector);
11540         struct drm_encoder *encoder = &intel_encoder->base;
11541         struct drm_atomic_state *state = old->restore_state;
11542         int ret;
11543
11544         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11545                       connector->base.id, connector->name,
11546                       encoder->base.id, encoder->name);
11547
11548         if (!state)
11549                 return;
11550
11551         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11552         if (ret)
11553                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11554         drm_atomic_state_put(state);
11555 }
11556
11557 static int i9xx_pll_refclk(struct drm_device *dev,
11558                            const struct intel_crtc_state *pipe_config)
11559 {
11560         struct drm_i915_private *dev_priv = to_i915(dev);
11561         u32 dpll = pipe_config->dpll_hw_state.dpll;
11562
11563         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11564                 return dev_priv->vbt.lvds_ssc_freq;
11565         else if (HAS_PCH_SPLIT(dev_priv))
11566                 return 120000;
11567         else if (!IS_GEN(dev_priv, 2))
11568                 return 96000;
11569         else
11570                 return 48000;
11571 }
11572
11573 /* Returns the clock of the currently programmed mode of the given pipe. */
11574 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11575                                 struct intel_crtc_state *pipe_config)
11576 {
11577         struct drm_device *dev = crtc->base.dev;
11578         struct drm_i915_private *dev_priv = to_i915(dev);
11579         enum pipe pipe = crtc->pipe;
11580         u32 dpll = pipe_config->dpll_hw_state.dpll;
11581         u32 fp;
11582         struct dpll clock;
11583         int port_clock;
11584         int refclk = i9xx_pll_refclk(dev, pipe_config);
11585
11586         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11587                 fp = pipe_config->dpll_hw_state.fp0;
11588         else
11589                 fp = pipe_config->dpll_hw_state.fp1;
11590
11591         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11592         if (IS_PINEVIEW(dev_priv)) {
11593                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11594                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11595         } else {
11596                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11597                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11598         }
11599
11600         if (!IS_GEN(dev_priv, 2)) {
11601                 if (IS_PINEVIEW(dev_priv))
11602                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11603                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11604                 else
11605                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11606                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11607
11608                 switch (dpll & DPLL_MODE_MASK) {
11609                 case DPLLB_MODE_DAC_SERIAL:
11610                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11611                                 5 : 10;
11612                         break;
11613                 case DPLLB_MODE_LVDS:
11614                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11615                                 7 : 14;
11616                         break;
11617                 default:
11618                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11619                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11620                         return;
11621                 }
11622
11623                 if (IS_PINEVIEW(dev_priv))
11624                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11625                 else
11626                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11627         } else {
11628                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11629                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11630
11631                 if (is_lvds) {
11632                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11633                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11634
11635                         if (lvds & LVDS_CLKB_POWER_UP)
11636                                 clock.p2 = 7;
11637                         else
11638                                 clock.p2 = 14;
11639                 } else {
11640                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11641                                 clock.p1 = 2;
11642                         else {
11643                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11644                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11645                         }
11646                         if (dpll & PLL_P2_DIVIDE_BY_4)
11647                                 clock.p2 = 4;
11648                         else
11649                                 clock.p2 = 2;
11650                 }
11651
11652                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11653         }
11654
11655         /*
11656          * This value includes pixel_multiplier. We will use
11657          * port_clock to compute adjusted_mode.crtc_clock in the
11658          * encoder's get_config() function.
11659          */
11660         pipe_config->port_clock = port_clock;
11661 }
11662
11663 int intel_dotclock_calculate(int link_freq,
11664                              const struct intel_link_m_n *m_n)
11665 {
11666         /*
11667          * The calculation for the data clock is:
11668          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11669          * But we want to avoid losing precison if possible, so:
11670          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11671          *
11672          * and the link clock is simpler:
11673          * link_clock = (m * link_clock) / n
11674          */
11675
11676         if (!m_n->link_n)
11677                 return 0;
11678
11679         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11680 }
11681
11682 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11683                                    struct intel_crtc_state *pipe_config)
11684 {
11685         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11686
11687         /* read out port_clock from the DPLL */
11688         i9xx_crtc_clock_get(crtc, pipe_config);
11689
11690         /*
11691          * In case there is an active pipe without active ports,
11692          * we may need some idea for the dotclock anyway.
11693          * Calculate one based on the FDI configuration.
11694          */
11695         pipe_config->hw.adjusted_mode.crtc_clock =
11696                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11697                                          &pipe_config->fdi_m_n);
11698 }
11699
11700 /* Returns the currently programmed mode of the given encoder. */
11701 struct drm_display_mode *
11702 intel_encoder_current_mode(struct intel_encoder *encoder)
11703 {
11704         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11705         struct intel_crtc_state *crtc_state;
11706         struct drm_display_mode *mode;
11707         struct intel_crtc *crtc;
11708         enum pipe pipe;
11709
11710         if (!encoder->get_hw_state(encoder, &pipe))
11711                 return NULL;
11712
11713         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11714
11715         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11716         if (!mode)
11717                 return NULL;
11718
11719         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11720         if (!crtc_state) {
11721                 kfree(mode);
11722                 return NULL;
11723         }
11724
11725         crtc_state->uapi.crtc = &crtc->base;
11726
11727         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11728                 kfree(crtc_state);
11729                 kfree(mode);
11730                 return NULL;
11731         }
11732
11733         encoder->get_config(encoder, crtc_state);
11734
11735         intel_mode_from_pipe_config(mode, crtc_state);
11736
11737         kfree(crtc_state);
11738
11739         return mode;
11740 }
11741
11742 static void intel_crtc_destroy(struct drm_crtc *crtc)
11743 {
11744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11745
11746         drm_crtc_cleanup(crtc);
11747         kfree(intel_crtc);
11748 }
11749
11750 /**
11751  * intel_wm_need_update - Check whether watermarks need updating
11752  * @cur: current plane state
11753  * @new: new plane state
11754  *
11755  * Check current plane state versus the new one to determine whether
11756  * watermarks need to be recalculated.
11757  *
11758  * Returns true or false.
11759  */
11760 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11761                                  struct intel_plane_state *new)
11762 {
11763         /* Update watermarks on tiling or size changes. */
11764         if (new->uapi.visible != cur->uapi.visible)
11765                 return true;
11766
11767         if (!cur->hw.fb || !new->hw.fb)
11768                 return false;
11769
11770         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
11771             cur->hw.rotation != new->hw.rotation ||
11772             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
11773             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
11774             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
11775             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
11776                 return true;
11777
11778         return false;
11779 }
11780
11781 static bool needs_scaling(const struct intel_plane_state *state)
11782 {
11783         int src_w = drm_rect_width(&state->uapi.src) >> 16;
11784         int src_h = drm_rect_height(&state->uapi.src) >> 16;
11785         int dst_w = drm_rect_width(&state->uapi.dst);
11786         int dst_h = drm_rect_height(&state->uapi.dst);
11787
11788         return (src_w != dst_w || src_h != dst_h);
11789 }
11790
11791 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11792                                     struct intel_crtc_state *crtc_state,
11793                                     const struct intel_plane_state *old_plane_state,
11794                                     struct intel_plane_state *plane_state)
11795 {
11796         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11797         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11798         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11799         bool mode_changed = needs_modeset(crtc_state);
11800         bool was_crtc_enabled = old_crtc_state->hw.active;
11801         bool is_crtc_enabled = crtc_state->hw.active;
11802         bool turn_off, turn_on, visible, was_visible;
11803         int ret;
11804
11805         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11806                 ret = skl_update_scaler_plane(crtc_state, plane_state);
11807                 if (ret)
11808                         return ret;
11809         }
11810
11811         was_visible = old_plane_state->uapi.visible;
11812         visible = plane_state->uapi.visible;
11813
11814         if (!was_crtc_enabled && WARN_ON(was_visible))
11815                 was_visible = false;
11816
11817         /*
11818          * Visibility is calculated as if the crtc was on, but
11819          * after scaler setup everything depends on it being off
11820          * when the crtc isn't active.
11821          *
11822          * FIXME this is wrong for watermarks. Watermarks should also
11823          * be computed as if the pipe would be active. Perhaps move
11824          * per-plane wm computation to the .check_plane() hook, and
11825          * only combine the results from all planes in the current place?
11826          */
11827         if (!is_crtc_enabled) {
11828                 plane_state->uapi.visible = visible = false;
11829                 crtc_state->active_planes &= ~BIT(plane->id);
11830                 crtc_state->data_rate[plane->id] = 0;
11831                 crtc_state->min_cdclk[plane->id] = 0;
11832         }
11833
11834         if (!was_visible && !visible)
11835                 return 0;
11836
11837         turn_off = was_visible && (!visible || mode_changed);
11838         turn_on = visible && (!was_visible || mode_changed);
11839
11840         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11841                          crtc->base.base.id, crtc->base.name,
11842                          plane->base.base.id, plane->base.name,
11843                          was_visible, visible,
11844                          turn_off, turn_on, mode_changed);
11845
11846         if (turn_on) {
11847                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11848                         crtc_state->update_wm_pre = true;
11849
11850                 /* must disable cxsr around plane enable/disable */
11851                 if (plane->id != PLANE_CURSOR)
11852                         crtc_state->disable_cxsr = true;
11853         } else if (turn_off) {
11854                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11855                         crtc_state->update_wm_post = true;
11856
11857                 /* must disable cxsr around plane enable/disable */
11858                 if (plane->id != PLANE_CURSOR)
11859                         crtc_state->disable_cxsr = true;
11860         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11861                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11862                         /* FIXME bollocks */
11863                         crtc_state->update_wm_pre = true;
11864                         crtc_state->update_wm_post = true;
11865                 }
11866         }
11867
11868         if (visible || was_visible)
11869                 crtc_state->fb_bits |= plane->frontbuffer_bit;
11870
11871         /*
11872          * ILK/SNB DVSACNTR/Sprite Enable
11873          * IVB SPR_CTL/Sprite Enable
11874          * "When in Self Refresh Big FIFO mode, a write to enable the
11875          *  plane will be internally buffered and delayed while Big FIFO
11876          *  mode is exiting."
11877          *
11878          * Which means that enabling the sprite can take an extra frame
11879          * when we start in big FIFO mode (LP1+). Thus we need to drop
11880          * down to LP0 and wait for vblank in order to make sure the
11881          * sprite gets enabled on the next vblank after the register write.
11882          * Doing otherwise would risk enabling the sprite one frame after
11883          * we've already signalled flip completion. We can resume LP1+
11884          * once the sprite has been enabled.
11885          *
11886          *
11887          * WaCxSRDisabledForSpriteScaling:ivb
11888          * IVB SPR_SCALE/Scaling Enable
11889          * "Low Power watermarks must be disabled for at least one
11890          *  frame before enabling sprite scaling, and kept disabled
11891          *  until sprite scaling is disabled."
11892          *
11893          * ILK/SNB DVSASCALE/Scaling Enable
11894          * "When in Self Refresh Big FIFO mode, scaling enable will be
11895          *  masked off while Big FIFO mode is exiting."
11896          *
11897          * Despite the w/a only being listed for IVB we assume that
11898          * the ILK/SNB note has similar ramifications, hence we apply
11899          * the w/a on all three platforms.
11900          *
11901          * With experimental results seems this is needed also for primary
11902          * plane, not only sprite plane.
11903          */
11904         if (plane->id != PLANE_CURSOR &&
11905             (IS_GEN_RANGE(dev_priv, 5, 6) ||
11906              IS_IVYBRIDGE(dev_priv)) &&
11907             (turn_on || (!needs_scaling(old_plane_state) &&
11908                          needs_scaling(plane_state))))
11909                 crtc_state->disable_lp_wm = true;
11910
11911         return 0;
11912 }
11913
11914 static bool encoders_cloneable(const struct intel_encoder *a,
11915                                const struct intel_encoder *b)
11916 {
11917         /* masks could be asymmetric, so check both ways */
11918         return a == b || (a->cloneable & (1 << b->type) &&
11919                           b->cloneable & (1 << a->type));
11920 }
11921
11922 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11923                                          struct intel_crtc *crtc,
11924                                          struct intel_encoder *encoder)
11925 {
11926         struct intel_encoder *source_encoder;
11927         struct drm_connector *connector;
11928         struct drm_connector_state *connector_state;
11929         int i;
11930
11931         for_each_new_connector_in_state(state, connector, connector_state, i) {
11932                 if (connector_state->crtc != &crtc->base)
11933                         continue;
11934
11935                 source_encoder =
11936                         to_intel_encoder(connector_state->best_encoder);
11937                 if (!encoders_cloneable(encoder, source_encoder))
11938                         return false;
11939         }
11940
11941         return true;
11942 }
11943
11944 static int icl_add_linked_planes(struct intel_atomic_state *state)
11945 {
11946         struct intel_plane *plane, *linked;
11947         struct intel_plane_state *plane_state, *linked_plane_state;
11948         int i;
11949
11950         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11951                 linked = plane_state->planar_linked_plane;
11952
11953                 if (!linked)
11954                         continue;
11955
11956                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11957                 if (IS_ERR(linked_plane_state))
11958                         return PTR_ERR(linked_plane_state);
11959
11960                 WARN_ON(linked_plane_state->planar_linked_plane != plane);
11961                 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
11962         }
11963
11964         return 0;
11965 }
11966
11967 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11968 {
11969         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11970         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11971         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
11972         struct intel_plane *plane, *linked;
11973         struct intel_plane_state *plane_state;
11974         int i;
11975
11976         if (INTEL_GEN(dev_priv) < 11)
11977                 return 0;
11978
11979         /*
11980          * Destroy all old plane links and make the slave plane invisible
11981          * in the crtc_state->active_planes mask.
11982          */
11983         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11984                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
11985                         continue;
11986
11987                 plane_state->planar_linked_plane = NULL;
11988                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
11989                         crtc_state->active_planes &= ~BIT(plane->id);
11990                         crtc_state->update_planes |= BIT(plane->id);
11991                 }
11992
11993                 plane_state->planar_slave = false;
11994         }
11995
11996         if (!crtc_state->nv12_planes)
11997                 return 0;
11998
11999         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12000                 struct intel_plane_state *linked_state = NULL;
12001
12002                 if (plane->pipe != crtc->pipe ||
12003                     !(crtc_state->nv12_planes & BIT(plane->id)))
12004                         continue;
12005
12006                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12007                         if (!icl_is_nv12_y_plane(linked->id))
12008                                 continue;
12009
12010                         if (crtc_state->active_planes & BIT(linked->id))
12011                                 continue;
12012
12013                         linked_state = intel_atomic_get_plane_state(state, linked);
12014                         if (IS_ERR(linked_state))
12015                                 return PTR_ERR(linked_state);
12016
12017                         break;
12018                 }
12019
12020                 if (!linked_state) {
12021                         DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
12022                                       hweight8(crtc_state->nv12_planes));
12023
12024                         return -EINVAL;
12025                 }
12026
12027                 plane_state->planar_linked_plane = linked;
12028
12029                 linked_state->planar_slave = true;
12030                 linked_state->planar_linked_plane = plane;
12031                 crtc_state->active_planes |= BIT(linked->id);
12032                 crtc_state->update_planes |= BIT(linked->id);
12033                 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
12034
12035                 /* Copy parameters to slave plane */
12036                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12037                 linked_state->color_ctl = plane_state->color_ctl;
12038                 linked_state->color_plane[0] = plane_state->color_plane[0];
12039
12040                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12041                 linked_state->uapi.src = plane_state->uapi.src;
12042                 linked_state->uapi.dst = plane_state->uapi.dst;
12043
12044                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12045                         if (linked->id == PLANE_SPRITE5)
12046                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12047                         else if (linked->id == PLANE_SPRITE4)
12048                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12049                         else
12050                                 MISSING_CASE(linked->id);
12051                 }
12052         }
12053
12054         return 0;
12055 }
12056
12057 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12058 {
12059         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12060         struct intel_atomic_state *state =
12061                 to_intel_atomic_state(new_crtc_state->uapi.state);
12062         const struct intel_crtc_state *old_crtc_state =
12063                 intel_atomic_get_old_crtc_state(state, crtc);
12064
12065         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12066 }
12067
12068 static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
12069 {
12070         struct drm_crtc *crtc = crtc_state->uapi.crtc;
12071         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12072         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12073         struct drm_connector *master_connector, *connector;
12074         struct drm_connector_state *connector_state;
12075         struct drm_connector_list_iter conn_iter;
12076         struct drm_crtc *master_crtc = NULL;
12077         struct drm_crtc_state *master_crtc_state;
12078         struct intel_crtc_state *master_pipe_config;
12079         int i, tile_group_id;
12080
12081         if (INTEL_GEN(dev_priv) < 11)
12082                 return 0;
12083
12084         /*
12085          * In case of tiled displays there could be one or more slaves but there is
12086          * only one master. Lets make the CRTC used by the connector corresponding
12087          * to the last horizonal and last vertical tile a master/genlock CRTC.
12088          * All the other CRTCs corresponding to other tiles of the same Tile group
12089          * are the slave CRTCs and hold a pointer to their genlock CRTC.
12090          */
12091         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
12092                 if (connector_state->crtc != crtc)
12093                         continue;
12094                 if (!connector->has_tile)
12095                         continue;
12096                 if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
12097                     crtc_state->hw.mode.vdisplay != connector->tile_v_size)
12098                         return 0;
12099                 if (connector->tile_h_loc == connector->num_h_tile - 1 &&
12100                     connector->tile_v_loc == connector->num_v_tile - 1)
12101                         continue;
12102                 crtc_state->sync_mode_slaves_mask = 0;
12103                 tile_group_id = connector->tile_group->id;
12104                 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
12105                 drm_for_each_connector_iter(master_connector, &conn_iter) {
12106                         struct drm_connector_state *master_conn_state = NULL;
12107
12108                         if (!master_connector->has_tile)
12109                                 continue;
12110                         if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
12111                             master_connector->tile_v_loc != master_connector->num_v_tile - 1)
12112                                 continue;
12113                         if (master_connector->tile_group->id != tile_group_id)
12114                                 continue;
12115
12116                         master_conn_state = drm_atomic_get_connector_state(&state->base,
12117                                                                            master_connector);
12118                         if (IS_ERR(master_conn_state)) {
12119                                 drm_connector_list_iter_end(&conn_iter);
12120                                 return PTR_ERR(master_conn_state);
12121                         }
12122                         if (master_conn_state->crtc) {
12123                                 master_crtc = master_conn_state->crtc;
12124                                 break;
12125                         }
12126                 }
12127                 drm_connector_list_iter_end(&conn_iter);
12128
12129                 if (!master_crtc) {
12130                         DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
12131                                       connector_state->crtc->base.id);
12132                         return -EINVAL;
12133                 }
12134
12135                 master_crtc_state = drm_atomic_get_crtc_state(&state->base,
12136                                                               master_crtc);
12137                 if (IS_ERR(master_crtc_state))
12138                         return PTR_ERR(master_crtc_state);
12139
12140                 master_pipe_config = to_intel_crtc_state(master_crtc_state);
12141                 crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
12142                 master_pipe_config->sync_mode_slaves_mask |=
12143                         BIT(crtc_state->cpu_transcoder);
12144                 DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
12145                               transcoder_name(crtc_state->master_transcoder),
12146                               crtc_state->uapi.crtc->base.id,
12147                               master_pipe_config->sync_mode_slaves_mask);
12148         }
12149
12150         return 0;
12151 }
12152
12153 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12154                                    struct intel_crtc *crtc)
12155 {
12156         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12157         struct intel_crtc_state *crtc_state =
12158                 intel_atomic_get_new_crtc_state(state, crtc);
12159         bool mode_changed = needs_modeset(crtc_state);
12160         int ret;
12161
12162         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12163             mode_changed && !crtc_state->hw.active)
12164                 crtc_state->update_wm_post = true;
12165
12166         if (mode_changed && crtc_state->hw.enable &&
12167             dev_priv->display.crtc_compute_clock &&
12168             !WARN_ON(crtc_state->shared_dpll)) {
12169                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12170                 if (ret)
12171                         return ret;
12172         }
12173
12174         /*
12175          * May need to update pipe gamma enable bits
12176          * when C8 planes are getting enabled/disabled.
12177          */
12178         if (c8_planes_changed(crtc_state))
12179                 crtc_state->uapi.color_mgmt_changed = true;
12180
12181         if (mode_changed || crtc_state->update_pipe ||
12182             crtc_state->uapi.color_mgmt_changed) {
12183                 ret = intel_color_check(crtc_state);
12184                 if (ret)
12185                         return ret;
12186         }
12187
12188         ret = 0;
12189         if (dev_priv->display.compute_pipe_wm) {
12190                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12191                 if (ret) {
12192                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12193                         return ret;
12194                 }
12195         }
12196
12197         if (dev_priv->display.compute_intermediate_wm) {
12198                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12199                         return 0;
12200
12201                 /*
12202                  * Calculate 'intermediate' watermarks that satisfy both the
12203                  * old state and the new state.  We can program these
12204                  * immediately.
12205                  */
12206                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12207                 if (ret) {
12208                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12209                         return ret;
12210                 }
12211         }
12212
12213         if (INTEL_GEN(dev_priv) >= 9) {
12214                 if (mode_changed || crtc_state->update_pipe)
12215                         ret = skl_update_scaler_crtc(crtc_state);
12216                 if (!ret)
12217                         ret = intel_atomic_setup_scalers(dev_priv, crtc,
12218                                                          crtc_state);
12219         }
12220
12221         if (HAS_IPS(dev_priv))
12222                 crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
12223
12224         return ret;
12225 }
12226
12227 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12228 {
12229         struct intel_connector *connector;
12230         struct drm_connector_list_iter conn_iter;
12231
12232         drm_connector_list_iter_begin(dev, &conn_iter);
12233         for_each_intel_connector_iter(connector, &conn_iter) {
12234                 if (connector->base.state->crtc)
12235                         drm_connector_put(&connector->base);
12236
12237                 if (connector->base.encoder) {
12238                         connector->base.state->best_encoder =
12239                                 connector->base.encoder;
12240                         connector->base.state->crtc =
12241                                 connector->base.encoder->crtc;
12242
12243                         drm_connector_get(&connector->base);
12244                 } else {
12245                         connector->base.state->best_encoder = NULL;
12246                         connector->base.state->crtc = NULL;
12247                 }
12248         }
12249         drm_connector_list_iter_end(&conn_iter);
12250 }
12251
12252 static int
12253 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12254                       struct intel_crtc_state *pipe_config)
12255 {
12256         struct drm_connector *connector = conn_state->connector;
12257         const struct drm_display_info *info = &connector->display_info;
12258         int bpp;
12259
12260         switch (conn_state->max_bpc) {
12261         case 6 ... 7:
12262                 bpp = 6 * 3;
12263                 break;
12264         case 8 ... 9:
12265                 bpp = 8 * 3;
12266                 break;
12267         case 10 ... 11:
12268                 bpp = 10 * 3;
12269                 break;
12270         case 12:
12271                 bpp = 12 * 3;
12272                 break;
12273         default:
12274                 return -EINVAL;
12275         }
12276
12277         if (bpp < pipe_config->pipe_bpp) {
12278                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12279                               "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12280                               connector->base.id, connector->name,
12281                               bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
12282                               pipe_config->pipe_bpp);
12283
12284                 pipe_config->pipe_bpp = bpp;
12285         }
12286
12287         return 0;
12288 }
12289
12290 static int
12291 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12292                           struct intel_crtc_state *pipe_config)
12293 {
12294         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12295         struct drm_atomic_state *state = pipe_config->uapi.state;
12296         struct drm_connector *connector;
12297         struct drm_connector_state *connector_state;
12298         int bpp, i;
12299
12300         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12301             IS_CHERRYVIEW(dev_priv)))
12302                 bpp = 10*3;
12303         else if (INTEL_GEN(dev_priv) >= 5)
12304                 bpp = 12*3;
12305         else
12306                 bpp = 8*3;
12307
12308         pipe_config->pipe_bpp = bpp;
12309
12310         /* Clamp display bpp to connector max bpp */
12311         for_each_new_connector_in_state(state, connector, connector_state, i) {
12312                 int ret;
12313
12314                 if (connector_state->crtc != &crtc->base)
12315                         continue;
12316
12317                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12318                 if (ret)
12319                         return ret;
12320         }
12321
12322         return 0;
12323 }
12324
12325 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12326 {
12327         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12328                       "type: 0x%x flags: 0x%x\n",
12329                       mode->crtc_clock,
12330                       mode->crtc_hdisplay, mode->crtc_hsync_start,
12331                       mode->crtc_hsync_end, mode->crtc_htotal,
12332                       mode->crtc_vdisplay, mode->crtc_vsync_start,
12333                       mode->crtc_vsync_end, mode->crtc_vtotal,
12334                       mode->type, mode->flags);
12335 }
12336
12337 static inline void
12338 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12339                       const char *id, unsigned int lane_count,
12340                       const struct intel_link_m_n *m_n)
12341 {
12342         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12343                       id, lane_count,
12344                       m_n->gmch_m, m_n->gmch_n,
12345                       m_n->link_m, m_n->link_n, m_n->tu);
12346 }
12347
12348 static void
12349 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12350                      const union hdmi_infoframe *frame)
12351 {
12352         if ((drm_debug & DRM_UT_KMS) == 0)
12353                 return;
12354
12355         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12356 }
12357
12358 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12359
12360 static const char * const output_type_str[] = {
12361         OUTPUT_TYPE(UNUSED),
12362         OUTPUT_TYPE(ANALOG),
12363         OUTPUT_TYPE(DVO),
12364         OUTPUT_TYPE(SDVO),
12365         OUTPUT_TYPE(LVDS),
12366         OUTPUT_TYPE(TVOUT),
12367         OUTPUT_TYPE(HDMI),
12368         OUTPUT_TYPE(DP),
12369         OUTPUT_TYPE(EDP),
12370         OUTPUT_TYPE(DSI),
12371         OUTPUT_TYPE(DDI),
12372         OUTPUT_TYPE(DP_MST),
12373 };
12374
12375 #undef OUTPUT_TYPE
12376
12377 static void snprintf_output_types(char *buf, size_t len,
12378                                   unsigned int output_types)
12379 {
12380         char *str = buf;
12381         int i;
12382
12383         str[0] = '\0';
12384
12385         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12386                 int r;
12387
12388                 if ((output_types & BIT(i)) == 0)
12389                         continue;
12390
12391                 r = snprintf(str, len, "%s%s",
12392                              str != buf ? "," : "", output_type_str[i]);
12393                 if (r >= len)
12394                         break;
12395                 str += r;
12396                 len -= r;
12397
12398                 output_types &= ~BIT(i);
12399         }
12400
12401         WARN_ON_ONCE(output_types != 0);
12402 }
12403
12404 static const char * const output_format_str[] = {
12405         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12406         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12407         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12408         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12409 };
12410
12411 static const char *output_formats(enum intel_output_format format)
12412 {
12413         if (format >= ARRAY_SIZE(output_format_str))
12414                 format = INTEL_OUTPUT_FORMAT_INVALID;
12415         return output_format_str[format];
12416 }
12417
12418 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12419 {
12420         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12421         const struct drm_framebuffer *fb = plane_state->hw.fb;
12422         struct drm_format_name_buf format_name;
12423
12424         if (!fb) {
12425                 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12426                               plane->base.base.id, plane->base.name,
12427                               yesno(plane_state->uapi.visible));
12428                 return;
12429         }
12430
12431         DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12432                       plane->base.base.id, plane->base.name,
12433                       fb->base.id, fb->width, fb->height,
12434                       drm_get_format_name(fb->format->format, &format_name),
12435                       yesno(plane_state->uapi.visible));
12436         DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12437                       plane_state->hw.rotation, plane_state->scaler_id);
12438         if (plane_state->uapi.visible)
12439                 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12440                               DRM_RECT_FP_ARG(&plane_state->uapi.src),
12441                               DRM_RECT_ARG(&plane_state->uapi.dst));
12442 }
12443
12444 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12445                                    struct intel_atomic_state *state,
12446                                    const char *context)
12447 {
12448         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12450         const struct intel_plane_state *plane_state;
12451         struct intel_plane *plane;
12452         char buf[64];
12453         int i;
12454
12455         DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12456                       crtc->base.base.id, crtc->base.name,
12457                       yesno(pipe_config->hw.enable), context);
12458
12459         if (!pipe_config->hw.enable)
12460                 goto dump_planes;
12461
12462         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12463         DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12464                       yesno(pipe_config->hw.active),
12465                       buf, pipe_config->output_types,
12466                       output_formats(pipe_config->output_format));
12467
12468         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12469                       transcoder_name(pipe_config->cpu_transcoder),
12470                       pipe_config->pipe_bpp, pipe_config->dither);
12471
12472         if (pipe_config->has_pch_encoder)
12473                 intel_dump_m_n_config(pipe_config, "fdi",
12474                                       pipe_config->fdi_lanes,
12475                                       &pipe_config->fdi_m_n);
12476
12477         if (intel_crtc_has_dp_encoder(pipe_config)) {
12478                 intel_dump_m_n_config(pipe_config, "dp m_n",
12479                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12480                 if (pipe_config->has_drrs)
12481                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12482                                               pipe_config->lane_count,
12483                                               &pipe_config->dp_m2_n2);
12484         }
12485
12486         DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12487                       pipe_config->has_audio, pipe_config->has_infoframe,
12488                       pipe_config->infoframes.enable);
12489
12490         if (pipe_config->infoframes.enable &
12491             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12492                 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12493         if (pipe_config->infoframes.enable &
12494             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12495                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12496         if (pipe_config->infoframes.enable &
12497             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12498                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12499         if (pipe_config->infoframes.enable &
12500             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12501                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12502
12503         DRM_DEBUG_KMS("requested mode:\n");
12504         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
12505         DRM_DEBUG_KMS("adjusted mode:\n");
12506         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
12507         intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
12508         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12509                       pipe_config->port_clock,
12510                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12511                       pipe_config->pixel_rate);
12512
12513         if (INTEL_GEN(dev_priv) >= 9)
12514                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12515                               crtc->num_scalers,
12516                               pipe_config->scaler_state.scaler_users,
12517                               pipe_config->scaler_state.scaler_id);
12518
12519         if (HAS_GMCH(dev_priv))
12520                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12521                               pipe_config->gmch_pfit.control,
12522                               pipe_config->gmch_pfit.pgm_ratios,
12523                               pipe_config->gmch_pfit.lvds_border_bits);
12524         else
12525                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12526                               pipe_config->pch_pfit.pos,
12527                               pipe_config->pch_pfit.size,
12528                               enableddisabled(pipe_config->pch_pfit.enabled),
12529                               yesno(pipe_config->pch_pfit.force_thru));
12530
12531         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12532                       pipe_config->ips_enabled, pipe_config->double_wide);
12533
12534         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12535
12536         if (IS_CHERRYVIEW(dev_priv))
12537                 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12538                               pipe_config->cgm_mode, pipe_config->gamma_mode,
12539                               pipe_config->gamma_enable, pipe_config->csc_enable);
12540         else
12541                 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12542                               pipe_config->csc_mode, pipe_config->gamma_mode,
12543                               pipe_config->gamma_enable, pipe_config->csc_enable);
12544
12545 dump_planes:
12546         if (!state)
12547                 return;
12548
12549         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12550                 if (plane->pipe == crtc->pipe)
12551                         intel_dump_plane_state(plane_state);
12552         }
12553 }
12554
12555 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12556 {
12557         struct drm_device *dev = state->base.dev;
12558         struct drm_connector *connector;
12559         struct drm_connector_list_iter conn_iter;
12560         unsigned int used_ports = 0;
12561         unsigned int used_mst_ports = 0;
12562         bool ret = true;
12563
12564         /*
12565          * We're going to peek into connector->state,
12566          * hence connection_mutex must be held.
12567          */
12568         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
12569
12570         /*
12571          * Walk the connector list instead of the encoder
12572          * list to detect the problem on ddi platforms
12573          * where there's just one encoder per digital port.
12574          */
12575         drm_connector_list_iter_begin(dev, &conn_iter);
12576         drm_for_each_connector_iter(connector, &conn_iter) {
12577                 struct drm_connector_state *connector_state;
12578                 struct intel_encoder *encoder;
12579
12580                 connector_state =
12581                         drm_atomic_get_new_connector_state(&state->base,
12582                                                            connector);
12583                 if (!connector_state)
12584                         connector_state = connector->state;
12585
12586                 if (!connector_state->best_encoder)
12587                         continue;
12588
12589                 encoder = to_intel_encoder(connector_state->best_encoder);
12590
12591                 WARN_ON(!connector_state->crtc);
12592
12593                 switch (encoder->type) {
12594                         unsigned int port_mask;
12595                 case INTEL_OUTPUT_DDI:
12596                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12597                                 break;
12598                         /* else, fall through */
12599                 case INTEL_OUTPUT_DP:
12600                 case INTEL_OUTPUT_HDMI:
12601                 case INTEL_OUTPUT_EDP:
12602                         port_mask = 1 << encoder->port;
12603
12604                         /* the same port mustn't appear more than once */
12605                         if (used_ports & port_mask)
12606                                 ret = false;
12607
12608                         used_ports |= port_mask;
12609                         break;
12610                 case INTEL_OUTPUT_DP_MST:
12611                         used_mst_ports |=
12612                                 1 << encoder->port;
12613                         break;
12614                 default:
12615                         break;
12616                 }
12617         }
12618         drm_connector_list_iter_end(&conn_iter);
12619
12620         /* can't mix MST and SST/HDMI on the same port */
12621         if (used_ports & used_mst_ports)
12622                 return false;
12623
12624         return ret;
12625 }
12626
12627 static void
12628 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
12629 {
12630         intel_crtc_copy_color_blobs(crtc_state);
12631 }
12632
12633 static void
12634 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
12635 {
12636         crtc_state->hw.enable = crtc_state->uapi.enable;
12637         crtc_state->hw.active = crtc_state->uapi.active;
12638         crtc_state->hw.mode = crtc_state->uapi.mode;
12639         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
12640         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
12641 }
12642
12643 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
12644 {
12645         crtc_state->uapi.enable = crtc_state->hw.enable;
12646         crtc_state->uapi.active = crtc_state->hw.active;
12647         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
12648
12649         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
12650
12651         /* copy color blobs to uapi */
12652         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
12653                                   crtc_state->hw.degamma_lut);
12654         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
12655                                   crtc_state->hw.gamma_lut);
12656         drm_property_replace_blob(&crtc_state->uapi.ctm,
12657                                   crtc_state->hw.ctm);
12658 }
12659
12660 static int
12661 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
12662 {
12663         struct drm_i915_private *dev_priv =
12664                 to_i915(crtc_state->uapi.crtc->dev);
12665         struct intel_crtc_state *saved_state;
12666
12667         saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12668         if (!saved_state)
12669                 return -ENOMEM;
12670
12671         /* free the old crtc_state->hw members */
12672         intel_crtc_free_hw_state(crtc_state);
12673
12674         /* FIXME: before the switch to atomic started, a new pipe_config was
12675          * kzalloc'd. Code that depends on any field being zero should be
12676          * fixed, so that the crtc_state can be safely duplicated. For now,
12677          * only fields that are know to not cause problems are preserved. */
12678
12679         saved_state->uapi = crtc_state->uapi;
12680         saved_state->scaler_state = crtc_state->scaler_state;
12681         saved_state->shared_dpll = crtc_state->shared_dpll;
12682         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12683         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12684                sizeof(saved_state->icl_port_dplls));
12685         saved_state->crc_enabled = crtc_state->crc_enabled;
12686         if (IS_G4X(dev_priv) ||
12687             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12688                 saved_state->wm = crtc_state->wm;
12689         /*
12690          * Save the slave bitmask which gets filled for master crtc state during
12691          * slave atomic check call.
12692          */
12693         if (is_trans_port_sync_master(crtc_state))
12694                 saved_state->sync_mode_slaves_mask =
12695                         crtc_state->sync_mode_slaves_mask;
12696
12697         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
12698         kfree(saved_state);
12699
12700         intel_crtc_copy_uapi_to_hw_state(crtc_state);
12701
12702         return 0;
12703 }
12704
12705 static int
12706 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12707 {
12708         struct drm_crtc *crtc = pipe_config->uapi.crtc;
12709         struct drm_atomic_state *state = pipe_config->uapi.state;
12710         struct intel_encoder *encoder;
12711         struct drm_connector *connector;
12712         struct drm_connector_state *connector_state;
12713         int base_bpp, ret;
12714         int i;
12715         bool retry = true;
12716
12717         pipe_config->cpu_transcoder =
12718                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12719
12720         /*
12721          * Sanitize sync polarity flags based on requested ones. If neither
12722          * positive or negative polarity is requested, treat this as meaning
12723          * negative polarity.
12724          */
12725         if (!(pipe_config->hw.adjusted_mode.flags &
12726               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12727                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12728
12729         if (!(pipe_config->hw.adjusted_mode.flags &
12730               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12731                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12732
12733         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12734                                         pipe_config);
12735         if (ret)
12736                 return ret;
12737
12738         base_bpp = pipe_config->pipe_bpp;
12739
12740         /*
12741          * Determine the real pipe dimensions. Note that stereo modes can
12742          * increase the actual pipe size due to the frame doubling and
12743          * insertion of additional space for blanks between the frame. This
12744          * is stored in the crtc timings. We use the requested mode to do this
12745          * computation to clearly distinguish it from the adjusted mode, which
12746          * can be changed by the connectors in the below retry loop.
12747          */
12748         drm_mode_get_hv_timing(&pipe_config->hw.mode,
12749                                &pipe_config->pipe_src_w,
12750                                &pipe_config->pipe_src_h);
12751
12752         for_each_new_connector_in_state(state, connector, connector_state, i) {
12753                 if (connector_state->crtc != crtc)
12754                         continue;
12755
12756                 encoder = to_intel_encoder(connector_state->best_encoder);
12757
12758                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12759                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12760                         return -EINVAL;
12761                 }
12762
12763                 /*
12764                  * Determine output_types before calling the .compute_config()
12765                  * hooks so that the hooks can use this information safely.
12766                  */
12767                 if (encoder->compute_output_type)
12768                         pipe_config->output_types |=
12769                                 BIT(encoder->compute_output_type(encoder, pipe_config,
12770                                                                  connector_state));
12771                 else
12772                         pipe_config->output_types |= BIT(encoder->type);
12773         }
12774
12775 encoder_retry:
12776         /* Ensure the port clock defaults are reset when retrying. */
12777         pipe_config->port_clock = 0;
12778         pipe_config->pixel_multiplier = 1;
12779
12780         /* Fill in default crtc timings, allow encoders to overwrite them. */
12781         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
12782                               CRTC_STEREO_DOUBLE);
12783
12784         /* Set the crtc_state defaults for trans_port_sync */
12785         pipe_config->master_transcoder = INVALID_TRANSCODER;
12786         ret = icl_add_sync_mode_crtcs(pipe_config);
12787         if (ret) {
12788                 DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
12789                               ret);
12790                 return ret;
12791         }
12792
12793         /* Pass our mode to the connectors and the CRTC to give them a chance to
12794          * adjust it according to limitations or connector properties, and also
12795          * a chance to reject the mode entirely.
12796          */
12797         for_each_new_connector_in_state(state, connector, connector_state, i) {
12798                 if (connector_state->crtc != crtc)
12799                         continue;
12800
12801                 encoder = to_intel_encoder(connector_state->best_encoder);
12802                 ret = encoder->compute_config(encoder, pipe_config,
12803                                               connector_state);
12804                 if (ret < 0) {
12805                         if (ret != -EDEADLK)
12806                                 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12807                                               ret);
12808                         return ret;
12809                 }
12810         }
12811
12812         /* Set default port clock if not overwritten by the encoder. Needs to be
12813          * done afterwards in case the encoder adjusts the mode. */
12814         if (!pipe_config->port_clock)
12815                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
12816                         * pipe_config->pixel_multiplier;
12817
12818         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12819         if (ret == -EDEADLK)
12820                 return ret;
12821         if (ret < 0) {
12822                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12823                 return ret;
12824         }
12825
12826         if (ret == RETRY) {
12827                 if (WARN(!retry, "loop in pipe configuration computation\n"))
12828                         return -EINVAL;
12829
12830                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12831                 retry = false;
12832                 goto encoder_retry;
12833         }
12834
12835         /* Dithering seems to not pass-through bits correctly when it should, so
12836          * only enable it on 6bpc panels and when its not a compliance
12837          * test requesting 6bpc video pattern.
12838          */
12839         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12840                 !pipe_config->dither_force_disable;
12841         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12842                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12843
12844         /*
12845          * Make drm_calc_timestamping_constants in
12846          * drm_atomic_helper_update_legacy_modeset_state() happy
12847          */
12848         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
12849
12850         return 0;
12851 }
12852
12853 bool intel_fuzzy_clock_check(int clock1, int clock2)
12854 {
12855         int diff;
12856
12857         if (clock1 == clock2)
12858                 return true;
12859
12860         if (!clock1 || !clock2)
12861                 return false;
12862
12863         diff = abs(clock1 - clock2);
12864
12865         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12866                 return true;
12867
12868         return false;
12869 }
12870
12871 static bool
12872 intel_compare_m_n(unsigned int m, unsigned int n,
12873                   unsigned int m2, unsigned int n2,
12874                   bool exact)
12875 {
12876         if (m == m2 && n == n2)
12877                 return true;
12878
12879         if (exact || !m || !n || !m2 || !n2)
12880                 return false;
12881
12882         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12883
12884         if (n > n2) {
12885                 while (n > n2) {
12886                         m2 <<= 1;
12887                         n2 <<= 1;
12888                 }
12889         } else if (n < n2) {
12890                 while (n < n2) {
12891                         m <<= 1;
12892                         n <<= 1;
12893                 }
12894         }
12895
12896         if (n != n2)
12897                 return false;
12898
12899         return intel_fuzzy_clock_check(m, m2);
12900 }
12901
12902 static bool
12903 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12904                        const struct intel_link_m_n *m2_n2,
12905                        bool exact)
12906 {
12907         return m_n->tu == m2_n2->tu &&
12908                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12909                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12910                 intel_compare_m_n(m_n->link_m, m_n->link_n,
12911                                   m2_n2->link_m, m2_n2->link_n, exact);
12912 }
12913
12914 static bool
12915 intel_compare_infoframe(const union hdmi_infoframe *a,
12916                         const union hdmi_infoframe *b)
12917 {
12918         return memcmp(a, b, sizeof(*a)) == 0;
12919 }
12920
12921 static void
12922 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12923                                bool fastset, const char *name,
12924                                const union hdmi_infoframe *a,
12925                                const union hdmi_infoframe *b)
12926 {
12927         if (fastset) {
12928                 if ((drm_debug & DRM_UT_KMS) == 0)
12929                         return;
12930
12931                 DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name);
12932                 DRM_DEBUG_KMS("expected:\n");
12933                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12934                 DRM_DEBUG_KMS("found:\n");
12935                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12936         } else {
12937                 DRM_ERROR("mismatch in %s infoframe\n", name);
12938                 DRM_ERROR("expected:\n");
12939                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12940                 DRM_ERROR("found:\n");
12941                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12942         }
12943 }
12944
12945 static void __printf(4, 5)
12946 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
12947                      const char *name, const char *format, ...)
12948 {
12949         struct va_format vaf;
12950         va_list args;
12951
12952         va_start(args, format);
12953         vaf.fmt = format;
12954         vaf.va = &args;
12955
12956         if (fastset)
12957                 DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
12958                               crtc->base.base.id, crtc->base.name, name, &vaf);
12959         else
12960                 DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
12961                           crtc->base.base.id, crtc->base.name, name, &vaf);
12962
12963         va_end(args);
12964 }
12965
12966 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12967 {
12968         if (i915_modparams.fastboot != -1)
12969                 return i915_modparams.fastboot;
12970
12971         /* Enable fastboot by default on Skylake and newer */
12972         if (INTEL_GEN(dev_priv) >= 9)
12973                 return true;
12974
12975         /* Enable fastboot by default on VLV and CHV */
12976         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12977                 return true;
12978
12979         /* Disabled by default on all others */
12980         return false;
12981 }
12982
12983 static bool
12984 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
12985                           const struct intel_crtc_state *pipe_config,
12986                           bool fastset)
12987 {
12988         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
12989         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12990         bool ret = true;
12991         u32 bp_gamma = 0;
12992         bool fixup_inherited = fastset &&
12993                 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12994                 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
12995
12996         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12997                 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12998                 ret = false;
12999         }
13000
13001 #define PIPE_CONF_CHECK_X(name) do { \
13002         if (current_config->name != pipe_config->name) { \
13003                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13004                                      "(expected 0x%08x, found 0x%08x)", \
13005                                      current_config->name, \
13006                                      pipe_config->name); \
13007                 ret = false; \
13008         } \
13009 } while (0)
13010
13011 #define PIPE_CONF_CHECK_I(name) do { \
13012         if (current_config->name != pipe_config->name) { \
13013                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13014                                      "(expected %i, found %i)", \
13015                                      current_config->name, \
13016                                      pipe_config->name); \
13017                 ret = false; \
13018         } \
13019 } while (0)
13020
13021 #define PIPE_CONF_CHECK_BOOL(name) do { \
13022         if (current_config->name != pipe_config->name) { \
13023                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13024                                      "(expected %s, found %s)", \
13025                                      yesno(current_config->name), \
13026                                      yesno(pipe_config->name)); \
13027                 ret = false; \
13028         } \
13029 } while (0)
13030
13031 /*
13032  * Checks state where we only read out the enabling, but not the entire
13033  * state itself (like full infoframes or ELD for audio). These states
13034  * require a full modeset on bootup to fix up.
13035  */
13036 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13037         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13038                 PIPE_CONF_CHECK_BOOL(name); \
13039         } else { \
13040                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13041                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13042                                      yesno(current_config->name), \
13043                                      yesno(pipe_config->name)); \
13044                 ret = false; \
13045         } \
13046 } while (0)
13047
13048 #define PIPE_CONF_CHECK_P(name) do { \
13049         if (current_config->name != pipe_config->name) { \
13050                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13051                                      "(expected %p, found %p)", \
13052                                      current_config->name, \
13053                                      pipe_config->name); \
13054                 ret = false; \
13055         } \
13056 } while (0)
13057
13058 #define PIPE_CONF_CHECK_M_N(name) do { \
13059         if (!intel_compare_link_m_n(&current_config->name, \
13060                                     &pipe_config->name,\
13061                                     !fastset)) { \
13062                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13063                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13064                                      "found tu %i, gmch %i/%i link %i/%i)", \
13065                                      current_config->name.tu, \
13066                                      current_config->name.gmch_m, \
13067                                      current_config->name.gmch_n, \
13068                                      current_config->name.link_m, \
13069                                      current_config->name.link_n, \
13070                                      pipe_config->name.tu, \
13071                                      pipe_config->name.gmch_m, \
13072                                      pipe_config->name.gmch_n, \
13073                                      pipe_config->name.link_m, \
13074                                      pipe_config->name.link_n); \
13075                 ret = false; \
13076         } \
13077 } while (0)
13078
13079 /* This is required for BDW+ where there is only one set of registers for
13080  * switching between high and low RR.
13081  * This macro can be used whenever a comparison has to be made between one
13082  * hw state and multiple sw state variables.
13083  */
13084 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13085         if (!intel_compare_link_m_n(&current_config->name, \
13086                                     &pipe_config->name, !fastset) && \
13087             !intel_compare_link_m_n(&current_config->alt_name, \
13088                                     &pipe_config->name, !fastset)) { \
13089                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13090                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13091                                      "or tu %i gmch %i/%i link %i/%i, " \
13092                                      "found tu %i, gmch %i/%i link %i/%i)", \
13093                                      current_config->name.tu, \
13094                                      current_config->name.gmch_m, \
13095                                      current_config->name.gmch_n, \
13096                                      current_config->name.link_m, \
13097                                      current_config->name.link_n, \
13098                                      current_config->alt_name.tu, \
13099                                      current_config->alt_name.gmch_m, \
13100                                      current_config->alt_name.gmch_n, \
13101                                      current_config->alt_name.link_m, \
13102                                      current_config->alt_name.link_n, \
13103                                      pipe_config->name.tu, \
13104                                      pipe_config->name.gmch_m, \
13105                                      pipe_config->name.gmch_n, \
13106                                      pipe_config->name.link_m, \
13107                                      pipe_config->name.link_n); \
13108                 ret = false; \
13109         } \
13110 } while (0)
13111
13112 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13113         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13114                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13115                                      "(%x) (expected %i, found %i)", \
13116                                      (mask), \
13117                                      current_config->name & (mask), \
13118                                      pipe_config->name & (mask)); \
13119                 ret = false; \
13120         } \
13121 } while (0)
13122
13123 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13124         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13125                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13126                                      "(expected %i, found %i)", \
13127                                      current_config->name, \
13128                                      pipe_config->name); \
13129                 ret = false; \
13130         } \
13131 } while (0)
13132
13133 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13134         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13135                                      &pipe_config->infoframes.name)) { \
13136                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13137                                                &current_config->infoframes.name, \
13138                                                &pipe_config->infoframes.name); \
13139                 ret = false; \
13140         } \
13141 } while (0)
13142
13143 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13144         if (current_config->name1 != pipe_config->name1) { \
13145                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13146                                 "(expected %i, found %i, won't compare lut values)", \
13147                                 current_config->name1, \
13148                                 pipe_config->name1); \
13149                 ret = false;\
13150         } else { \
13151                 if (!intel_color_lut_equal(current_config->name2, \
13152                                         pipe_config->name2, pipe_config->name1, \
13153                                         bit_precision)) { \
13154                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13155                                         "hw_state doesn't match sw_state"); \
13156                         ret = false; \
13157                 } \
13158         } \
13159 } while (0)
13160
13161 #define PIPE_CONF_QUIRK(quirk) \
13162         ((current_config->quirks | pipe_config->quirks) & (quirk))
13163
13164         PIPE_CONF_CHECK_I(cpu_transcoder);
13165
13166         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13167         PIPE_CONF_CHECK_I(fdi_lanes);
13168         PIPE_CONF_CHECK_M_N(fdi_m_n);
13169
13170         PIPE_CONF_CHECK_I(lane_count);
13171         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13172
13173         if (INTEL_GEN(dev_priv) < 8) {
13174                 PIPE_CONF_CHECK_M_N(dp_m_n);
13175
13176                 if (current_config->has_drrs)
13177                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13178         } else
13179                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13180
13181         PIPE_CONF_CHECK_X(output_types);
13182
13183         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13184         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13185         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13186         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13187         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13188         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13189
13190         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13191         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13192         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13193         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13194         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13195         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13196
13197         PIPE_CONF_CHECK_I(pixel_multiplier);
13198         PIPE_CONF_CHECK_I(output_format);
13199         PIPE_CONF_CHECK_I(dc3co_exitline);
13200         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13201         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13202             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13203                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13204
13205         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13206         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13207         PIPE_CONF_CHECK_BOOL(has_infoframe);
13208         PIPE_CONF_CHECK_BOOL(fec_enable);
13209
13210         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13211
13212         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13213                               DRM_MODE_FLAG_INTERLACE);
13214
13215         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13216                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13217                                       DRM_MODE_FLAG_PHSYNC);
13218                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13219                                       DRM_MODE_FLAG_NHSYNC);
13220                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13221                                       DRM_MODE_FLAG_PVSYNC);
13222                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13223                                       DRM_MODE_FLAG_NVSYNC);
13224         }
13225
13226         PIPE_CONF_CHECK_X(gmch_pfit.control);
13227         /* pfit ratios are autocomputed by the hw on gen4+ */
13228         if (INTEL_GEN(dev_priv) < 4)
13229                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13230         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13231
13232         /*
13233          * Changing the EDP transcoder input mux
13234          * (A_ONOFF vs. A_ON) requires a full modeset.
13235          */
13236         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13237
13238         if (!fastset) {
13239                 PIPE_CONF_CHECK_I(pipe_src_w);
13240                 PIPE_CONF_CHECK_I(pipe_src_h);
13241
13242                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13243                 if (current_config->pch_pfit.enabled) {
13244                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13245                         PIPE_CONF_CHECK_X(pch_pfit.size);
13246                 }
13247
13248                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13249                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13250
13251                 PIPE_CONF_CHECK_X(gamma_mode);
13252                 if (IS_CHERRYVIEW(dev_priv))
13253                         PIPE_CONF_CHECK_X(cgm_mode);
13254                 else
13255                         PIPE_CONF_CHECK_X(csc_mode);
13256                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13257                 PIPE_CONF_CHECK_BOOL(csc_enable);
13258
13259                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13260                 if (bp_gamma)
13261                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13262
13263         }
13264
13265         PIPE_CONF_CHECK_BOOL(double_wide);
13266
13267         PIPE_CONF_CHECK_P(shared_dpll);
13268         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13269         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13270         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13271         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13272         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13273         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13274         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13275         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13276         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13277         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13278         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13279         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13280         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13281         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13282         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13283         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13284         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13285         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13286         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13287         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13288         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13289         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13290         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13291         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13292         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13293         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13294         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13295         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13296         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13297         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13298         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13299
13300         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13301         PIPE_CONF_CHECK_X(dsi_pll.div);
13302
13303         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13304                 PIPE_CONF_CHECK_I(pipe_bpp);
13305
13306         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13307         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13308
13309         PIPE_CONF_CHECK_I(min_voltage_level);
13310
13311         PIPE_CONF_CHECK_X(infoframes.enable);
13312         PIPE_CONF_CHECK_X(infoframes.gcp);
13313         PIPE_CONF_CHECK_INFOFRAME(avi);
13314         PIPE_CONF_CHECK_INFOFRAME(spd);
13315         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13316         PIPE_CONF_CHECK_INFOFRAME(drm);
13317
13318         PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
13319         PIPE_CONF_CHECK_I(master_transcoder);
13320
13321 #undef PIPE_CONF_CHECK_X
13322 #undef PIPE_CONF_CHECK_I
13323 #undef PIPE_CONF_CHECK_BOOL
13324 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13325 #undef PIPE_CONF_CHECK_P
13326 #undef PIPE_CONF_CHECK_FLAGS
13327 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13328 #undef PIPE_CONF_CHECK_COLOR_LUT
13329 #undef PIPE_CONF_QUIRK
13330
13331         return ret;
13332 }
13333
13334 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13335                                            const struct intel_crtc_state *pipe_config)
13336 {
13337         if (pipe_config->has_pch_encoder) {
13338                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13339                                                             &pipe_config->fdi_m_n);
13340                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13341
13342                 /*
13343                  * FDI already provided one idea for the dotclock.
13344                  * Yell if the encoder disagrees.
13345                  */
13346                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13347                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13348                      fdi_dotclock, dotclock);
13349         }
13350 }
13351
13352 static void verify_wm_state(struct intel_crtc *crtc,
13353                             struct intel_crtc_state *new_crtc_state)
13354 {
13355         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13356         struct skl_hw_state {
13357                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13358                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13359                 struct skl_ddb_allocation ddb;
13360                 struct skl_pipe_wm wm;
13361         } *hw;
13362         struct skl_ddb_allocation *sw_ddb;
13363         struct skl_pipe_wm *sw_wm;
13364         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13365         const enum pipe pipe = crtc->pipe;
13366         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13367
13368         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13369                 return;
13370
13371         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13372         if (!hw)
13373                 return;
13374
13375         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13376         sw_wm = &new_crtc_state->wm.skl.optimal;
13377
13378         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13379
13380         skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13381         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13382
13383         if (INTEL_GEN(dev_priv) >= 11 &&
13384             hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13385                 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
13386                           sw_ddb->enabled_slices,
13387                           hw->ddb.enabled_slices);
13388
13389         /* planes */
13390         for_each_universal_plane(dev_priv, pipe, plane) {
13391                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13392
13393                 hw_plane_wm = &hw->wm.planes[plane];
13394                 sw_plane_wm = &sw_wm->planes[plane];
13395
13396                 /* Watermarks */
13397                 for (level = 0; level <= max_level; level++) {
13398                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13399                                                 &sw_plane_wm->wm[level]))
13400                                 continue;
13401
13402                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13403                                   pipe_name(pipe), plane + 1, level,
13404                                   sw_plane_wm->wm[level].plane_en,
13405                                   sw_plane_wm->wm[level].plane_res_b,
13406                                   sw_plane_wm->wm[level].plane_res_l,
13407                                   hw_plane_wm->wm[level].plane_en,
13408                                   hw_plane_wm->wm[level].plane_res_b,
13409                                   hw_plane_wm->wm[level].plane_res_l);
13410                 }
13411
13412                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13413                                          &sw_plane_wm->trans_wm)) {
13414                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13415                                   pipe_name(pipe), plane + 1,
13416                                   sw_plane_wm->trans_wm.plane_en,
13417                                   sw_plane_wm->trans_wm.plane_res_b,
13418                                   sw_plane_wm->trans_wm.plane_res_l,
13419                                   hw_plane_wm->trans_wm.plane_en,
13420                                   hw_plane_wm->trans_wm.plane_res_b,
13421                                   hw_plane_wm->trans_wm.plane_res_l);
13422                 }
13423
13424                 /* DDB */
13425                 hw_ddb_entry = &hw->ddb_y[plane];
13426                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13427
13428                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13429                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13430                                   pipe_name(pipe), plane + 1,
13431                                   sw_ddb_entry->start, sw_ddb_entry->end,
13432                                   hw_ddb_entry->start, hw_ddb_entry->end);
13433                 }
13434         }
13435
13436         /*
13437          * cursor
13438          * If the cursor plane isn't active, we may not have updated it's ddb
13439          * allocation. In that case since the ddb allocation will be updated
13440          * once the plane becomes visible, we can skip this check
13441          */
13442         if (1) {
13443                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13444
13445                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13446                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13447
13448                 /* Watermarks */
13449                 for (level = 0; level <= max_level; level++) {
13450                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13451                                                 &sw_plane_wm->wm[level]))
13452                                 continue;
13453
13454                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13455                                   pipe_name(pipe), level,
13456                                   sw_plane_wm->wm[level].plane_en,
13457                                   sw_plane_wm->wm[level].plane_res_b,
13458                                   sw_plane_wm->wm[level].plane_res_l,
13459                                   hw_plane_wm->wm[level].plane_en,
13460                                   hw_plane_wm->wm[level].plane_res_b,
13461                                   hw_plane_wm->wm[level].plane_res_l);
13462                 }
13463
13464                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13465                                          &sw_plane_wm->trans_wm)) {
13466                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13467                                   pipe_name(pipe),
13468                                   sw_plane_wm->trans_wm.plane_en,
13469                                   sw_plane_wm->trans_wm.plane_res_b,
13470                                   sw_plane_wm->trans_wm.plane_res_l,
13471                                   hw_plane_wm->trans_wm.plane_en,
13472                                   hw_plane_wm->trans_wm.plane_res_b,
13473                                   hw_plane_wm->trans_wm.plane_res_l);
13474                 }
13475
13476                 /* DDB */
13477                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13478                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13479
13480                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13481                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13482                                   pipe_name(pipe),
13483                                   sw_ddb_entry->start, sw_ddb_entry->end,
13484                                   hw_ddb_entry->start, hw_ddb_entry->end);
13485                 }
13486         }
13487
13488         kfree(hw);
13489 }
13490
13491 static void
13492 verify_connector_state(struct intel_atomic_state *state,
13493                        struct intel_crtc *crtc)
13494 {
13495         struct drm_connector *connector;
13496         struct drm_connector_state *new_conn_state;
13497         int i;
13498
13499         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13500                 struct drm_encoder *encoder = connector->encoder;
13501                 struct intel_crtc_state *crtc_state = NULL;
13502
13503                 if (new_conn_state->crtc != &crtc->base)
13504                         continue;
13505
13506                 if (crtc)
13507                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13508
13509                 intel_connector_verify_state(crtc_state, new_conn_state);
13510
13511                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13512                      "connector's atomic encoder doesn't match legacy encoder\n");
13513         }
13514 }
13515
13516 static void
13517 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13518 {
13519         struct intel_encoder *encoder;
13520         struct drm_connector *connector;
13521         struct drm_connector_state *old_conn_state, *new_conn_state;
13522         int i;
13523
13524         for_each_intel_encoder(&dev_priv->drm, encoder) {
13525                 bool enabled = false, found = false;
13526                 enum pipe pipe;
13527
13528                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13529                               encoder->base.base.id,
13530                               encoder->base.name);
13531
13532                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13533                                                    new_conn_state, i) {
13534                         if (old_conn_state->best_encoder == &encoder->base)
13535                                 found = true;
13536
13537                         if (new_conn_state->best_encoder != &encoder->base)
13538                                 continue;
13539                         found = enabled = true;
13540
13541                         I915_STATE_WARN(new_conn_state->crtc !=
13542                                         encoder->base.crtc,
13543                              "connector's crtc doesn't match encoder crtc\n");
13544                 }
13545
13546                 if (!found)
13547                         continue;
13548
13549                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13550                      "encoder's enabled state mismatch "
13551                      "(expected %i, found %i)\n",
13552                      !!encoder->base.crtc, enabled);
13553
13554                 if (!encoder->base.crtc) {
13555                         bool active;
13556
13557                         active = encoder->get_hw_state(encoder, &pipe);
13558                         I915_STATE_WARN(active,
13559                              "encoder detached but still enabled on pipe %c.\n",
13560                              pipe_name(pipe));
13561                 }
13562         }
13563 }
13564
13565 static void
13566 verify_crtc_state(struct intel_crtc *crtc,
13567                   struct intel_crtc_state *old_crtc_state,
13568                   struct intel_crtc_state *new_crtc_state)
13569 {
13570         struct drm_device *dev = crtc->base.dev;
13571         struct drm_i915_private *dev_priv = to_i915(dev);
13572         struct intel_encoder *encoder;
13573         struct intel_crtc_state *pipe_config;
13574         struct drm_atomic_state *state;
13575         bool active;
13576
13577         state = old_crtc_state->uapi.state;
13578         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
13579         intel_crtc_free_hw_state(old_crtc_state);
13580
13581         pipe_config = old_crtc_state;
13582         memset(pipe_config, 0, sizeof(*pipe_config));
13583         pipe_config->uapi.crtc = &crtc->base;
13584         pipe_config->uapi.state = state;
13585
13586         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13587
13588         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13589
13590         /* we keep both pipes enabled on 830 */
13591         if (IS_I830(dev_priv))
13592                 active = new_crtc_state->hw.active;
13593
13594         I915_STATE_WARN(new_crtc_state->hw.active != active,
13595                         "crtc active state doesn't match with hw state "
13596                         "(expected %i, found %i)\n",
13597                         new_crtc_state->hw.active, active);
13598
13599         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
13600                         "transitional active state does not match atomic hw state "
13601                         "(expected %i, found %i)\n",
13602                         new_crtc_state->hw.active, crtc->active);
13603
13604         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13605                 enum pipe pipe;
13606
13607                 active = encoder->get_hw_state(encoder, &pipe);
13608                 I915_STATE_WARN(active != new_crtc_state->hw.active,
13609                                 "[ENCODER:%i] active %i with crtc active %i\n",
13610                                 encoder->base.base.id, active,
13611                                 new_crtc_state->hw.active);
13612
13613                 I915_STATE_WARN(active && crtc->pipe != pipe,
13614                                 "Encoder connected to wrong pipe %c\n",
13615                                 pipe_name(pipe));
13616
13617                 if (active)
13618                         encoder->get_config(encoder, pipe_config);
13619         }
13620
13621         intel_crtc_compute_pixel_rate(pipe_config);
13622
13623         if (!new_crtc_state->hw.active)
13624                 return;
13625
13626         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13627
13628         if (!intel_pipe_config_compare(new_crtc_state,
13629                                        pipe_config, false)) {
13630                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13631                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13632                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13633         }
13634 }
13635
13636 static void
13637 intel_verify_planes(struct intel_atomic_state *state)
13638 {
13639         struct intel_plane *plane;
13640         const struct intel_plane_state *plane_state;
13641         int i;
13642
13643         for_each_new_intel_plane_in_state(state, plane,
13644                                           plane_state, i)
13645                 assert_plane(plane, plane_state->planar_slave ||
13646                              plane_state->uapi.visible);
13647 }
13648
13649 static void
13650 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13651                          struct intel_shared_dpll *pll,
13652                          struct intel_crtc *crtc,
13653                          struct intel_crtc_state *new_crtc_state)
13654 {
13655         struct intel_dpll_hw_state dpll_hw_state;
13656         unsigned int crtc_mask;
13657         bool active;
13658
13659         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13660
13661         DRM_DEBUG_KMS("%s\n", pll->info->name);
13662
13663         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13664
13665         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13666                 I915_STATE_WARN(!pll->on && pll->active_mask,
13667                      "pll in active use but not on in sw tracking\n");
13668                 I915_STATE_WARN(pll->on && !pll->active_mask,
13669                      "pll is on but not used by any active crtc\n");
13670                 I915_STATE_WARN(pll->on != active,
13671                      "pll on state mismatch (expected %i, found %i)\n",
13672                      pll->on, active);
13673         }
13674
13675         if (!crtc) {
13676                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13677                                 "more active pll users than references: %x vs %x\n",
13678                                 pll->active_mask, pll->state.crtc_mask);
13679
13680                 return;
13681         }
13682
13683         crtc_mask = drm_crtc_mask(&crtc->base);
13684
13685         if (new_crtc_state->hw.active)
13686                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13687                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13688                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13689         else
13690                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13691                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13692                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13693
13694         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13695                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13696                         crtc_mask, pll->state.crtc_mask);
13697
13698         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13699                                           &dpll_hw_state,
13700                                           sizeof(dpll_hw_state)),
13701                         "pll hw state mismatch\n");
13702 }
13703
13704 static void
13705 verify_shared_dpll_state(struct intel_crtc *crtc,
13706                          struct intel_crtc_state *old_crtc_state,
13707                          struct intel_crtc_state *new_crtc_state)
13708 {
13709         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13710
13711         if (new_crtc_state->shared_dpll)
13712                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13713
13714         if (old_crtc_state->shared_dpll &&
13715             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13716                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13717                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13718
13719                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13720                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13721                                 pipe_name(drm_crtc_index(&crtc->base)));
13722                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13723                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13724                                 pipe_name(drm_crtc_index(&crtc->base)));
13725         }
13726 }
13727
13728 static void
13729 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13730                           struct intel_atomic_state *state,
13731                           struct intel_crtc_state *old_crtc_state,
13732                           struct intel_crtc_state *new_crtc_state)
13733 {
13734         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13735                 return;
13736
13737         verify_wm_state(crtc, new_crtc_state);
13738         verify_connector_state(state, crtc);
13739         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13740         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13741 }
13742
13743 static void
13744 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13745 {
13746         int i;
13747
13748         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13749                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13750 }
13751
13752 static void
13753 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13754                               struct intel_atomic_state *state)
13755 {
13756         verify_encoder_state(dev_priv, state);
13757         verify_connector_state(state, NULL);
13758         verify_disabled_dpll_state(dev_priv);
13759 }
13760
13761 static void
13762 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
13763 {
13764         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13765         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13766         const struct drm_display_mode *adjusted_mode =
13767                 &crtc_state->hw.adjusted_mode;
13768
13769         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
13770
13771         /*
13772          * The scanline counter increments at the leading edge of hsync.
13773          *
13774          * On most platforms it starts counting from vtotal-1 on the
13775          * first active line. That means the scanline counter value is
13776          * always one less than what we would expect. Ie. just after
13777          * start of vblank, which also occurs at start of hsync (on the
13778          * last active line), the scanline counter will read vblank_start-1.
13779          *
13780          * On gen2 the scanline counter starts counting from 1 instead
13781          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13782          * to keep the value positive), instead of adding one.
13783          *
13784          * On HSW+ the behaviour of the scanline counter depends on the output
13785          * type. For DP ports it behaves like most other platforms, but on HDMI
13786          * there's an extra 1 line difference. So we need to add two instead of
13787          * one to the value.
13788          *
13789          * On VLV/CHV DSI the scanline counter would appear to increment
13790          * approx. 1/3 of a scanline before start of vblank. Unfortunately
13791          * that means we can't tell whether we're in vblank or not while
13792          * we're on that particular line. We must still set scanline_offset
13793          * to 1 so that the vblank timestamps come out correct when we query
13794          * the scanline counter from within the vblank interrupt handler.
13795          * However if queried just before the start of vblank we'll get an
13796          * answer that's slightly in the future.
13797          */
13798         if (IS_GEN(dev_priv, 2)) {
13799                 int vtotal;
13800
13801                 vtotal = adjusted_mode->crtc_vtotal;
13802                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13803                         vtotal /= 2;
13804
13805                 crtc->scanline_offset = vtotal - 1;
13806         } else if (HAS_DDI(dev_priv) &&
13807                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13808                 crtc->scanline_offset = 2;
13809         } else {
13810                 crtc->scanline_offset = 1;
13811         }
13812 }
13813
13814 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13815 {
13816         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13817         struct intel_crtc_state *new_crtc_state;
13818         struct intel_crtc *crtc;
13819         int i;
13820
13821         if (!dev_priv->display.crtc_compute_clock)
13822                 return;
13823
13824         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13825                 if (!needs_modeset(new_crtc_state))
13826                         continue;
13827
13828                 intel_release_shared_dplls(state, crtc);
13829         }
13830 }
13831
13832 /*
13833  * This implements the workaround described in the "notes" section of the mode
13834  * set sequence documentation. When going from no pipes or single pipe to
13835  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13836  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13837  */
13838 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13839 {
13840         struct intel_crtc_state *crtc_state;
13841         struct intel_crtc *crtc;
13842         struct intel_crtc_state *first_crtc_state = NULL;
13843         struct intel_crtc_state *other_crtc_state = NULL;
13844         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13845         int i;
13846
13847         /* look at all crtc's that are going to be enabled in during modeset */
13848         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13849                 if (!crtc_state->hw.active ||
13850                     !needs_modeset(crtc_state))
13851                         continue;
13852
13853                 if (first_crtc_state) {
13854                         other_crtc_state = crtc_state;
13855                         break;
13856                 } else {
13857                         first_crtc_state = crtc_state;
13858                         first_pipe = crtc->pipe;
13859                 }
13860         }
13861
13862         /* No workaround needed? */
13863         if (!first_crtc_state)
13864                 return 0;
13865
13866         /* w/a possibly needed, check how many crtc's are already enabled. */
13867         for_each_intel_crtc(state->base.dev, crtc) {
13868                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13869                 if (IS_ERR(crtc_state))
13870                         return PTR_ERR(crtc_state);
13871
13872                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13873
13874                 if (!crtc_state->hw.active ||
13875                     needs_modeset(crtc_state))
13876                         continue;
13877
13878                 /* 2 or more enabled crtcs means no need for w/a */
13879                 if (enabled_pipe != INVALID_PIPE)
13880                         return 0;
13881
13882                 enabled_pipe = crtc->pipe;
13883         }
13884
13885         if (enabled_pipe != INVALID_PIPE)
13886                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13887         else if (other_crtc_state)
13888                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13889
13890         return 0;
13891 }
13892
13893 static int intel_modeset_checks(struct intel_atomic_state *state)
13894 {
13895         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13896         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13897         struct intel_crtc *crtc;
13898         int ret, i;
13899
13900         /* keep the current setting */
13901         if (!state->cdclk.force_min_cdclk_changed)
13902                 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13903
13904         state->modeset = true;
13905         state->active_pipes = dev_priv->active_pipes;
13906         state->cdclk.logical = dev_priv->cdclk.logical;
13907         state->cdclk.actual = dev_priv->cdclk.actual;
13908
13909         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13910                                             new_crtc_state, i) {
13911                 if (new_crtc_state->hw.active)
13912                         state->active_pipes |= BIT(crtc->pipe);
13913                 else
13914                         state->active_pipes &= ~BIT(crtc->pipe);
13915
13916                 if (old_crtc_state->hw.active != new_crtc_state->hw.active)
13917                         state->active_pipe_changes |= BIT(crtc->pipe);
13918         }
13919
13920         if (state->active_pipe_changes) {
13921                 ret = intel_atomic_lock_global_state(state);
13922                 if (ret)
13923                         return ret;
13924         }
13925
13926         ret = intel_modeset_calc_cdclk(state);
13927         if (ret)
13928                 return ret;
13929
13930         intel_modeset_clear_plls(state);
13931
13932         if (IS_HASWELL(dev_priv))
13933                 return haswell_mode_set_planes_workaround(state);
13934
13935         return 0;
13936 }
13937
13938 /*
13939  * Handle calculation of various watermark data at the end of the atomic check
13940  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13941  * handlers to ensure that all derived state has been updated.
13942  */
13943 static int calc_watermark_data(struct intel_atomic_state *state)
13944 {
13945         struct drm_device *dev = state->base.dev;
13946         struct drm_i915_private *dev_priv = to_i915(dev);
13947
13948         /* Is there platform-specific watermark information to calculate? */
13949         if (dev_priv->display.compute_global_watermarks)
13950                 return dev_priv->display.compute_global_watermarks(state);
13951
13952         return 0;
13953 }
13954
13955 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13956                                      struct intel_crtc_state *new_crtc_state)
13957 {
13958         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
13959                 return;
13960
13961         new_crtc_state->uapi.mode_changed = false;
13962         new_crtc_state->update_pipe = true;
13963
13964         /*
13965          * If we're not doing the full modeset we want to
13966          * keep the current M/N values as they may be
13967          * sufficiently different to the computed values
13968          * to cause problems.
13969          *
13970          * FIXME: should really copy more fuzzy state here
13971          */
13972         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
13973         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
13974         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
13975         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
13976 }
13977
13978 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
13979                                           struct intel_crtc *crtc,
13980                                           u8 plane_ids_mask)
13981 {
13982         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13983         struct intel_plane *plane;
13984
13985         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13986                 struct intel_plane_state *plane_state;
13987
13988                 if ((plane_ids_mask & BIT(plane->id)) == 0)
13989                         continue;
13990
13991                 plane_state = intel_atomic_get_plane_state(state, plane);
13992                 if (IS_ERR(plane_state))
13993                         return PTR_ERR(plane_state);
13994         }
13995
13996         return 0;
13997 }
13998
13999 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14000 {
14001         /* See {hsw,vlv,ivb}_plane_ratio() */
14002         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14003                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14004                 IS_IVYBRIDGE(dev_priv);
14005 }
14006
14007 static int intel_atomic_check_planes(struct intel_atomic_state *state,
14008                                      bool *need_modeset)
14009 {
14010         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14011         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14012         struct intel_plane_state *plane_state;
14013         struct intel_plane *plane;
14014         struct intel_crtc *crtc;
14015         int i, ret;
14016
14017         ret = icl_add_linked_planes(state);
14018         if (ret)
14019                 return ret;
14020
14021         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14022                 ret = intel_plane_atomic_check(state, plane);
14023                 if (ret) {
14024                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
14025                                          plane->base.base.id, plane->base.name);
14026                         return ret;
14027                 }
14028         }
14029
14030         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14031                                             new_crtc_state, i) {
14032                 u8 old_active_planes, new_active_planes;
14033
14034                 ret = icl_check_nv12_planes(new_crtc_state);
14035                 if (ret)
14036                         return ret;
14037
14038                 /*
14039                  * On some platforms the number of active planes affects
14040                  * the planes' minimum cdclk calculation. Add such planes
14041                  * to the state before we compute the minimum cdclk.
14042                  */
14043                 if (!active_planes_affects_min_cdclk(dev_priv))
14044                         continue;
14045
14046                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14047                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14048
14049                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
14050                         continue;
14051
14052                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14053                 if (ret)
14054                         return ret;
14055         }
14056
14057         /*
14058          * active_planes bitmask has been updated, and potentially
14059          * affected planes are part of the state. We can now
14060          * compute the minimum cdclk for each plane.
14061          */
14062         for_each_new_intel_plane_in_state(state, plane, plane_state, i)
14063                 *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
14064
14065         return 0;
14066 }
14067
14068 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14069 {
14070         struct intel_crtc_state *crtc_state;
14071         struct intel_crtc *crtc;
14072         int i;
14073
14074         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14075                 int ret = intel_crtc_atomic_check(state, crtc);
14076                 if (ret) {
14077                         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
14078                                          crtc->base.base.id, crtc->base.name);
14079                         return ret;
14080                 }
14081         }
14082
14083         return 0;
14084 }
14085
14086 /**
14087  * intel_atomic_check - validate state object
14088  * @dev: drm device
14089  * @_state: state to validate
14090  */
14091 static int intel_atomic_check(struct drm_device *dev,
14092                               struct drm_atomic_state *_state)
14093 {
14094         struct drm_i915_private *dev_priv = to_i915(dev);
14095         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14096         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14097         struct intel_crtc *crtc;
14098         int ret, i;
14099         bool any_ms = false;
14100
14101         /* Catch I915_MODE_FLAG_INHERITED */
14102         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14103                                             new_crtc_state, i) {
14104                 if (new_crtc_state->hw.mode.private_flags !=
14105                     old_crtc_state->hw.mode.private_flags)
14106                         new_crtc_state->uapi.mode_changed = true;
14107         }
14108
14109         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14110         if (ret)
14111                 goto fail;
14112
14113         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14114                                             new_crtc_state, i) {
14115                 if (!needs_modeset(new_crtc_state)) {
14116                         /* Light copy */
14117                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14118
14119                         continue;
14120                 }
14121
14122                 if (!new_crtc_state->uapi.enable) {
14123                         intel_crtc_copy_uapi_to_hw_state(new_crtc_state);
14124
14125                         any_ms = true;
14126                         continue;
14127                 }
14128
14129                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14130                 if (ret)
14131                         goto fail;
14132
14133                 ret = intel_modeset_pipe_config(new_crtc_state);
14134                 if (ret)
14135                         goto fail;
14136
14137                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14138
14139                 if (needs_modeset(new_crtc_state))
14140                         any_ms = true;
14141         }
14142
14143         if (any_ms && !check_digital_port_conflicts(state)) {
14144                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14145                 ret = EINVAL;
14146                 goto fail;
14147         }
14148
14149         ret = drm_dp_mst_atomic_check(&state->base);
14150         if (ret)
14151                 goto fail;
14152
14153         any_ms |= state->cdclk.force_min_cdclk_changed;
14154
14155         ret = intel_atomic_check_planes(state, &any_ms);
14156         if (ret)
14157                 goto fail;
14158
14159         if (any_ms) {
14160                 ret = intel_modeset_checks(state);
14161                 if (ret)
14162                         goto fail;
14163         } else {
14164                 state->cdclk.logical = dev_priv->cdclk.logical;
14165         }
14166
14167         ret = intel_atomic_check_crtcs(state);
14168         if (ret)
14169                 goto fail;
14170
14171         intel_fbc_choose_crtc(dev_priv, state);
14172         ret = calc_watermark_data(state);
14173         if (ret)
14174                 goto fail;
14175
14176         ret = intel_bw_atomic_check(state);
14177         if (ret)
14178                 goto fail;
14179
14180         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14181                                             new_crtc_state, i) {
14182                 if (!needs_modeset(new_crtc_state) &&
14183                     !new_crtc_state->update_pipe)
14184                         continue;
14185
14186                 intel_dump_pipe_config(new_crtc_state, state,
14187                                        needs_modeset(new_crtc_state) ?
14188                                        "[modeset]" : "[fastset]");
14189         }
14190
14191         return 0;
14192
14193  fail:
14194         if (ret == -EDEADLK)
14195                 return ret;
14196
14197         /*
14198          * FIXME would probably be nice to know which crtc specifically
14199          * caused the failure, in cases where we can pinpoint it.
14200          */
14201         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14202                                             new_crtc_state, i)
14203                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14204
14205         return ret;
14206 }
14207
14208 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14209 {
14210         return drm_atomic_helper_prepare_planes(state->base.dev,
14211                                                 &state->base);
14212 }
14213
14214 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14215 {
14216         struct drm_device *dev = crtc->base.dev;
14217         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14218
14219         if (!vblank->max_vblank_count)
14220                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14221
14222         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14223 }
14224
14225 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14226                                   struct intel_crtc_state *crtc_state)
14227 {
14228         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14229
14230         if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
14231                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14232
14233         if (crtc_state->has_pch_encoder) {
14234                 enum pipe pch_transcoder =
14235                         intel_crtc_pch_transcoder(crtc);
14236
14237                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14238         }
14239 }
14240
14241 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14242                                const struct intel_crtc_state *new_crtc_state)
14243 {
14244         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14245         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14246
14247         /*
14248          * Update pipe size and adjust fitter if needed: the reason for this is
14249          * that in compute_mode_changes we check the native mode (not the pfit
14250          * mode) to see if we can flip rather than do a full mode set. In the
14251          * fastboot case, we'll flip, but if we don't update the pipesrc and
14252          * pfit state, we'll end up with a big fb scanned out into the wrong
14253          * sized surface.
14254          */
14255         intel_set_pipe_src_size(new_crtc_state);
14256
14257         /* on skylake this is done by detaching scalers */
14258         if (INTEL_GEN(dev_priv) >= 9) {
14259                 skl_detach_scalers(new_crtc_state);
14260
14261                 if (new_crtc_state->pch_pfit.enabled)
14262                         skylake_pfit_enable(new_crtc_state);
14263         } else if (HAS_PCH_SPLIT(dev_priv)) {
14264                 if (new_crtc_state->pch_pfit.enabled)
14265                         ironlake_pfit_enable(new_crtc_state);
14266                 else if (old_crtc_state->pch_pfit.enabled)
14267                         ironlake_pfit_disable(old_crtc_state);
14268         }
14269
14270         if (INTEL_GEN(dev_priv) >= 11)
14271                 icl_set_pipe_chicken(crtc);
14272 }
14273
14274 static void commit_pipe_config(struct intel_atomic_state *state,
14275                                struct intel_crtc_state *old_crtc_state,
14276                                struct intel_crtc_state *new_crtc_state)
14277 {
14278         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14279         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14280         bool modeset = needs_modeset(new_crtc_state);
14281
14282         /*
14283          * During modesets pipe configuration was programmed as the
14284          * CRTC was enabled.
14285          */
14286         if (!modeset) {
14287                 if (new_crtc_state->uapi.color_mgmt_changed ||
14288                     new_crtc_state->update_pipe)
14289                         intel_color_commit(new_crtc_state);
14290
14291                 if (INTEL_GEN(dev_priv) >= 9)
14292                         skl_detach_scalers(new_crtc_state);
14293
14294                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14295                         bdw_set_pipemisc(new_crtc_state);
14296
14297                 if (new_crtc_state->update_pipe)
14298                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
14299         }
14300
14301         if (dev_priv->display.atomic_update_watermarks)
14302                 dev_priv->display.atomic_update_watermarks(state, crtc);
14303 }
14304
14305 static void intel_update_crtc(struct intel_crtc *crtc,
14306                               struct intel_atomic_state *state,
14307                               struct intel_crtc_state *old_crtc_state,
14308                               struct intel_crtc_state *new_crtc_state)
14309 {
14310         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14311         bool modeset = needs_modeset(new_crtc_state);
14312         struct intel_plane_state *new_plane_state =
14313                 intel_atomic_get_new_plane_state(state,
14314                                                  to_intel_plane(crtc->base.primary));
14315
14316         if (modeset) {
14317                 intel_crtc_update_active_timings(new_crtc_state);
14318
14319                 dev_priv->display.crtc_enable(state, crtc);
14320
14321                 /* vblanks work again, re-enable pipe CRC. */
14322                 intel_crtc_enable_pipe_crc(crtc);
14323         } else {
14324                 if (new_crtc_state->preload_luts &&
14325                     (new_crtc_state->uapi.color_mgmt_changed ||
14326                      new_crtc_state->update_pipe))
14327                         intel_color_load_luts(new_crtc_state);
14328
14329                 intel_pre_plane_update(state, crtc);
14330
14331                 if (new_crtc_state->update_pipe)
14332                         intel_encoders_update_pipe(state, crtc);
14333         }
14334
14335         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14336                 intel_fbc_disable(crtc);
14337         else if (new_plane_state)
14338                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14339
14340         /* Perform vblank evasion around commit operation */
14341         intel_pipe_update_start(new_crtc_state);
14342
14343         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14344
14345         if (INTEL_GEN(dev_priv) >= 9)
14346                 skl_update_planes_on_crtc(state, crtc);
14347         else
14348                 i9xx_update_planes_on_crtc(state, crtc);
14349
14350         intel_pipe_update_end(new_crtc_state);
14351
14352         /*
14353          * We usually enable FIFO underrun interrupts as part of the
14354          * CRTC enable sequence during modesets.  But when we inherit a
14355          * valid pipe configuration from the BIOS we need to take care
14356          * of enabling them on the CRTC's first fastset.
14357          */
14358         if (new_crtc_state->update_pipe && !modeset &&
14359             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14360                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14361 }
14362
14363 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
14364 {
14365         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
14366         enum transcoder slave_transcoder;
14367
14368         WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
14369
14370         slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
14371         return intel_get_crtc_for_pipe(dev_priv,
14372                                        (enum pipe)slave_transcoder);
14373 }
14374
14375 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
14376                                           struct intel_crtc_state *old_crtc_state,
14377                                           struct intel_crtc_state *new_crtc_state,
14378                                           struct intel_crtc *crtc)
14379 {
14380         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14381
14382         intel_crtc_disable_planes(state, crtc);
14383
14384         /*
14385          * We need to disable pipe CRC before disabling the pipe,
14386          * or we race against vblank off.
14387          */
14388         intel_crtc_disable_pipe_crc(crtc);
14389
14390         dev_priv->display.crtc_disable(state, crtc);
14391         crtc->active = false;
14392         intel_fbc_disable(crtc);
14393         intel_disable_shared_dpll(old_crtc_state);
14394
14395         /* FIXME unify this for all platforms */
14396         if (!new_crtc_state->hw.active &&
14397             !HAS_GMCH(dev_priv) &&
14398             dev_priv->display.initial_watermarks)
14399                 dev_priv->display.initial_watermarks(state, crtc);
14400 }
14401
14402 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
14403 {
14404         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14405         struct intel_crtc *crtc;
14406         u32 handled = 0;
14407         int i;
14408
14409         /* Only disable port sync slaves */
14410         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14411                                             new_crtc_state, i) {
14412                 if (!needs_modeset(new_crtc_state))
14413                         continue;
14414
14415                 if (!old_crtc_state->hw.active)
14416                         continue;
14417
14418                 /* In case of Transcoder port Sync master slave CRTCs can be
14419                  * assigned in any order and we need to make sure that
14420                  * slave CRTCs are disabled first and then master CRTC since
14421                  * Slave vblanks are masked till Master Vblanks.
14422                  */
14423                 if (!is_trans_port_sync_slave(old_crtc_state))
14424                         continue;
14425
14426                 intel_pre_plane_update(state, crtc);
14427                 intel_old_crtc_state_disables(state, old_crtc_state,
14428                                               new_crtc_state, crtc);
14429                 handled |= BIT(crtc->pipe);
14430         }
14431
14432         /* Disable everything else left on */
14433         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14434                                             new_crtc_state, i) {
14435                 if (!needs_modeset(new_crtc_state) ||
14436                     (handled & BIT(crtc->pipe)))
14437                         continue;
14438
14439                 intel_pre_plane_update(state, crtc);
14440                 if (old_crtc_state->hw.active)
14441                         intel_old_crtc_state_disables(state, old_crtc_state,
14442                                                       new_crtc_state, crtc);
14443         }
14444 }
14445
14446 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
14447 {
14448         struct intel_crtc *crtc;
14449         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14450         int i;
14451
14452         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14453                 if (!new_crtc_state->hw.active)
14454                         continue;
14455
14456                 intel_update_crtc(crtc, state, old_crtc_state,
14457                                   new_crtc_state);
14458         }
14459 }
14460
14461 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
14462                                               struct intel_atomic_state *state,
14463                                               struct intel_crtc_state *new_crtc_state)
14464 {
14465         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14466
14467         intel_crtc_update_active_timings(new_crtc_state);
14468         dev_priv->display.crtc_enable(state, crtc);
14469         intel_crtc_enable_pipe_crc(crtc);
14470 }
14471
14472 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
14473                                        struct intel_atomic_state *state)
14474 {
14475         struct drm_connector *uninitialized_var(conn);
14476         struct drm_connector_state *conn_state;
14477         struct intel_dp *intel_dp;
14478         int i;
14479
14480         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
14481                 if (conn_state->crtc == &crtc->base)
14482                         break;
14483         }
14484         intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
14485         intel_dp_stop_link_train(intel_dp);
14486 }
14487
14488 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
14489                                            struct intel_atomic_state *state)
14490 {
14491         struct intel_crtc_state *new_crtc_state =
14492                 intel_atomic_get_new_crtc_state(state, crtc);
14493         struct intel_crtc_state *old_crtc_state =
14494                 intel_atomic_get_old_crtc_state(state, crtc);
14495         struct intel_plane_state *new_plane_state =
14496                 intel_atomic_get_new_plane_state(state,
14497                                                  to_intel_plane(crtc->base.primary));
14498         bool modeset = needs_modeset(new_crtc_state);
14499
14500         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14501                 intel_fbc_disable(crtc);
14502         else if (new_plane_state)
14503                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14504
14505         /* Perform vblank evasion around commit operation */
14506         intel_pipe_update_start(new_crtc_state);
14507         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14508         skl_update_planes_on_crtc(state, crtc);
14509         intel_pipe_update_end(new_crtc_state);
14510
14511         /*
14512          * We usually enable FIFO underrun interrupts as part of the
14513          * CRTC enable sequence during modesets.  But when we inherit a
14514          * valid pipe configuration from the BIOS we need to take care
14515          * of enabling them on the CRTC's first fastset.
14516          */
14517         if (new_crtc_state->update_pipe && !modeset &&
14518             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14519                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14520 }
14521
14522 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
14523                                                struct intel_atomic_state *state,
14524                                                struct intel_crtc_state *old_crtc_state,
14525                                                struct intel_crtc_state *new_crtc_state)
14526 {
14527         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14528         struct intel_crtc_state *new_slave_crtc_state =
14529                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14530         struct intel_crtc_state *old_slave_crtc_state =
14531                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14532
14533         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14534                 !old_slave_crtc_state);
14535
14536         DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
14537                       crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
14538                       slave_crtc->base.name);
14539
14540         /* Enable seq for slave with with DP_TP_CTL left Idle until the
14541          * master is ready
14542          */
14543         intel_crtc_enable_trans_port_sync(slave_crtc,
14544                                           state,
14545                                           new_slave_crtc_state);
14546
14547         /* Enable seq for master with with DP_TP_CTL left Idle */
14548         intel_crtc_enable_trans_port_sync(crtc,
14549                                           state,
14550                                           new_crtc_state);
14551
14552         /* Set Slave's DP_TP_CTL to Normal */
14553         intel_set_dp_tp_ctl_normal(slave_crtc,
14554                                    state);
14555
14556         /* Set Master's DP_TP_CTL To Normal */
14557         usleep_range(200, 400);
14558         intel_set_dp_tp_ctl_normal(crtc,
14559                                    state);
14560
14561         /* Now do the post crtc enable for all master and slaves */
14562         intel_post_crtc_enable_updates(slave_crtc,
14563                                        state);
14564         intel_post_crtc_enable_updates(crtc,
14565                                        state);
14566 }
14567
14568 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
14569 {
14570         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14571         struct intel_crtc *crtc;
14572         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14573         unsigned int updated = 0;
14574         bool progress;
14575         int i;
14576         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
14577         u8 required_slices = state->wm_results.ddb.enabled_slices;
14578         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
14579
14580         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
14581                 /* ignore allocations for crtc's that have been turned off. */
14582                 if (!needs_modeset(new_crtc_state) && new_crtc_state->hw.active)
14583                         entries[i] = old_crtc_state->wm.skl.ddb;
14584
14585         /* If 2nd DBuf slice required, enable it here */
14586         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
14587                 icl_dbuf_slices_update(dev_priv, required_slices);
14588
14589         /*
14590          * Whenever the number of active pipes changes, we need to make sure we
14591          * update the pipes in the right order so that their ddb allocations
14592          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14593          * cause pipe underruns and other bad stuff.
14594          */
14595         do {
14596                 progress = false;
14597
14598                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14599                         enum pipe pipe = crtc->pipe;
14600                         bool vbl_wait = false;
14601                         bool modeset = needs_modeset(new_crtc_state);
14602
14603                         if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
14604                                 continue;
14605
14606                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
14607                                                         entries,
14608                                                         INTEL_NUM_PIPES(dev_priv), i))
14609                                 continue;
14610
14611                         updated |= BIT(pipe);
14612                         entries[i] = new_crtc_state->wm.skl.ddb;
14613
14614                         /*
14615                          * If this is an already active pipe, it's DDB changed,
14616                          * and this isn't the last pipe that needs updating
14617                          * then we need to wait for a vblank to pass for the
14618                          * new ddb allocation to take effect.
14619                          */
14620                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
14621                                                  &old_crtc_state->wm.skl.ddb) &&
14622                             !modeset &&
14623                             state->wm_results.dirty_pipes != updated)
14624                                 vbl_wait = true;
14625
14626                         if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
14627                                 if (is_trans_port_sync_master(new_crtc_state))
14628                                         intel_update_trans_port_sync_crtcs(crtc,
14629                                                                            state,
14630                                                                            old_crtc_state,
14631                                                                            new_crtc_state);
14632                                 else
14633                                         continue;
14634                         } else {
14635                                 intel_update_crtc(crtc, state, old_crtc_state,
14636                                                   new_crtc_state);
14637                         }
14638
14639                         if (vbl_wait)
14640                                 intel_wait_for_vblank(dev_priv, pipe);
14641
14642                         progress = true;
14643                 }
14644         } while (progress);
14645
14646         /* If 2nd DBuf slice is no more required disable it */
14647         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
14648                 icl_dbuf_slices_update(dev_priv, required_slices);
14649 }
14650
14651 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14652 {
14653         struct intel_atomic_state *state, *next;
14654         struct llist_node *freed;
14655
14656         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14657         llist_for_each_entry_safe(state, next, freed, freed)
14658                 drm_atomic_state_put(&state->base);
14659 }
14660
14661 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14662 {
14663         struct drm_i915_private *dev_priv =
14664                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14665
14666         intel_atomic_helper_free_state(dev_priv);
14667 }
14668
14669 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
14670 {
14671         struct wait_queue_entry wait_fence, wait_reset;
14672         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
14673
14674         init_wait_entry(&wait_fence, 0);
14675         init_wait_entry(&wait_reset, 0);
14676         for (;;) {
14677                 prepare_to_wait(&intel_state->commit_ready.wait,
14678                                 &wait_fence, TASK_UNINTERRUPTIBLE);
14679                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14680                                               I915_RESET_MODESET),
14681                                 &wait_reset, TASK_UNINTERRUPTIBLE);
14682
14683
14684                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
14685                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
14686                         break;
14687
14688                 schedule();
14689         }
14690         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
14691         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14692                                   I915_RESET_MODESET),
14693                     &wait_reset);
14694 }
14695
14696 static void intel_atomic_cleanup_work(struct work_struct *work)
14697 {
14698         struct drm_atomic_state *state =
14699                 container_of(work, struct drm_atomic_state, commit_work);
14700         struct drm_i915_private *i915 = to_i915(state->dev);
14701
14702         drm_atomic_helper_cleanup_planes(&i915->drm, state);
14703         drm_atomic_helper_commit_cleanup_done(state);
14704         drm_atomic_state_put(state);
14705
14706         intel_atomic_helper_free_state(i915);
14707 }
14708
14709 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
14710 {
14711         struct drm_device *dev = state->base.dev;
14712         struct drm_i915_private *dev_priv = to_i915(dev);
14713         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14714         struct intel_crtc *crtc;
14715         u64 put_domains[I915_MAX_PIPES] = {};
14716         intel_wakeref_t wakeref = 0;
14717         int i;
14718
14719         intel_atomic_commit_fence_wait(state);
14720
14721         drm_atomic_helper_wait_for_dependencies(&state->base);
14722
14723         if (state->modeset)
14724                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14725
14726         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14727                                             new_crtc_state, i) {
14728                 if (needs_modeset(new_crtc_state) ||
14729                     new_crtc_state->update_pipe) {
14730
14731                         put_domains[crtc->pipe] =
14732                                 modeset_get_crtc_power_domains(new_crtc_state);
14733                 }
14734         }
14735
14736         intel_commit_modeset_disables(state);
14737
14738         /* FIXME: Eventually get rid of our crtc->config pointer */
14739         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14740                 crtc->config = new_crtc_state;
14741
14742         if (state->modeset) {
14743                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14744
14745                 intel_set_cdclk_pre_plane_update(dev_priv,
14746                                                  &state->cdclk.actual,
14747                                                  &dev_priv->cdclk.actual,
14748                                                  state->cdclk.pipe);
14749
14750                 /*
14751                  * SKL workaround: bspec recommends we disable the SAGV when we
14752                  * have more then one pipe enabled
14753                  */
14754                 if (!intel_can_enable_sagv(state))
14755                         intel_disable_sagv(dev_priv);
14756
14757                 intel_modeset_verify_disabled(dev_priv, state);
14758         }
14759
14760         /* Complete the events for pipes that have now been disabled */
14761         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14762                 bool modeset = needs_modeset(new_crtc_state);
14763
14764                 /* Complete events for now disable pipes here. */
14765                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
14766                         spin_lock_irq(&dev->event_lock);
14767                         drm_crtc_send_vblank_event(&crtc->base,
14768                                                    new_crtc_state->uapi.event);
14769                         spin_unlock_irq(&dev->event_lock);
14770
14771                         new_crtc_state->uapi.event = NULL;
14772                 }
14773         }
14774
14775         if (state->modeset)
14776                 intel_encoders_update_prepare(state);
14777
14778         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14779         dev_priv->display.commit_modeset_enables(state);
14780
14781         if (state->modeset) {
14782                 intel_encoders_update_complete(state);
14783
14784                 intel_set_cdclk_post_plane_update(dev_priv,
14785                                                   &state->cdclk.actual,
14786                                                   &dev_priv->cdclk.actual,
14787                                                   state->cdclk.pipe);
14788         }
14789
14790         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14791          * already, but still need the state for the delayed optimization. To
14792          * fix this:
14793          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14794          * - schedule that vblank worker _before_ calling hw_done
14795          * - at the start of commit_tail, cancel it _synchrously
14796          * - switch over to the vblank wait helper in the core after that since
14797          *   we don't need out special handling any more.
14798          */
14799         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14800
14801         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14802                 if (new_crtc_state->hw.active &&
14803                     !needs_modeset(new_crtc_state) &&
14804                     !new_crtc_state->preload_luts &&
14805                     (new_crtc_state->uapi.color_mgmt_changed ||
14806                      new_crtc_state->update_pipe))
14807                         intel_color_load_luts(new_crtc_state);
14808         }
14809
14810         /*
14811          * Now that the vblank has passed, we can go ahead and program the
14812          * optimal watermarks on platforms that need two-step watermark
14813          * programming.
14814          *
14815          * TODO: Move this (and other cleanup) to an async worker eventually.
14816          */
14817         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14818                                             new_crtc_state, i) {
14819                 /*
14820                  * Gen2 reports pipe underruns whenever all planes are disabled.
14821                  * So re-enable underrun reporting after some planes get enabled.
14822                  *
14823                  * We do this before .optimize_watermarks() so that we have a
14824                  * chance of catching underruns with the intermediate watermarks
14825                  * vs. the new plane configuration.
14826                  */
14827                 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
14828                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14829
14830                 if (dev_priv->display.optimize_watermarks)
14831                         dev_priv->display.optimize_watermarks(state, crtc);
14832         }
14833
14834         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14835                 intel_post_plane_update(state, crtc);
14836
14837                 if (put_domains[i])
14838                         modeset_put_power_domains(dev_priv, put_domains[i]);
14839
14840                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14841         }
14842
14843         /* Underruns don't always raise interrupts, so check manually */
14844         intel_check_cpu_fifo_underruns(dev_priv);
14845         intel_check_pch_fifo_underruns(dev_priv);
14846
14847         if (state->modeset)
14848                 intel_verify_planes(state);
14849
14850         if (state->modeset && intel_can_enable_sagv(state))
14851                 intel_enable_sagv(dev_priv);
14852
14853         drm_atomic_helper_commit_hw_done(&state->base);
14854
14855         if (state->modeset) {
14856                 /* As one of the primary mmio accessors, KMS has a high
14857                  * likelihood of triggering bugs in unclaimed access. After we
14858                  * finish modesetting, see if an error has been flagged, and if
14859                  * so enable debugging for the next modeset - and hope we catch
14860                  * the culprit.
14861                  */
14862                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14863                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14864         }
14865         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14866
14867         /*
14868          * Defer the cleanup of the old state to a separate worker to not
14869          * impede the current task (userspace for blocking modesets) that
14870          * are executed inline. For out-of-line asynchronous modesets/flips,
14871          * deferring to a new worker seems overkill, but we would place a
14872          * schedule point (cond_resched()) here anyway to keep latencies
14873          * down.
14874          */
14875         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14876         queue_work(system_highpri_wq, &state->base.commit_work);
14877 }
14878
14879 static void intel_atomic_commit_work(struct work_struct *work)
14880 {
14881         struct intel_atomic_state *state =
14882                 container_of(work, struct intel_atomic_state, base.commit_work);
14883
14884         intel_atomic_commit_tail(state);
14885 }
14886
14887 static int __i915_sw_fence_call
14888 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14889                           enum i915_sw_fence_notify notify)
14890 {
14891         struct intel_atomic_state *state =
14892                 container_of(fence, struct intel_atomic_state, commit_ready);
14893
14894         switch (notify) {
14895         case FENCE_COMPLETE:
14896                 /* we do blocking waits in the worker, nothing to do here */
14897                 break;
14898         case FENCE_FREE:
14899                 {
14900                         struct intel_atomic_helper *helper =
14901                                 &to_i915(state->base.dev)->atomic_helper;
14902
14903                         if (llist_add(&state->freed, &helper->free_list))
14904                                 schedule_work(&helper->free_work);
14905                         break;
14906                 }
14907         }
14908
14909         return NOTIFY_DONE;
14910 }
14911
14912 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14913 {
14914         struct intel_plane_state *old_plane_state, *new_plane_state;
14915         struct intel_plane *plane;
14916         int i;
14917
14918         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14919                                              new_plane_state, i)
14920                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
14921                                         to_intel_frontbuffer(new_plane_state->hw.fb),
14922                                         plane->frontbuffer_bit);
14923 }
14924
14925 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
14926 {
14927         struct intel_crtc *crtc;
14928
14929         for_each_intel_crtc(&dev_priv->drm, crtc)
14930                 drm_modeset_lock_assert_held(&crtc->base.mutex);
14931 }
14932
14933 static int intel_atomic_commit(struct drm_device *dev,
14934                                struct drm_atomic_state *_state,
14935                                bool nonblock)
14936 {
14937         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14938         struct drm_i915_private *dev_priv = to_i915(dev);
14939         int ret = 0;
14940
14941         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
14942
14943         drm_atomic_state_get(&state->base);
14944         i915_sw_fence_init(&state->commit_ready,
14945                            intel_atomic_commit_ready);
14946
14947         /*
14948          * The intel_legacy_cursor_update() fast path takes care
14949          * of avoiding the vblank waits for simple cursor
14950          * movement and flips. For cursor on/off and size changes,
14951          * we want to perform the vblank waits so that watermark
14952          * updates happen during the correct frames. Gen9+ have
14953          * double buffered watermarks and so shouldn't need this.
14954          *
14955          * Unset state->legacy_cursor_update before the call to
14956          * drm_atomic_helper_setup_commit() because otherwise
14957          * drm_atomic_helper_wait_for_flip_done() is a noop and
14958          * we get FIFO underruns because we didn't wait
14959          * for vblank.
14960          *
14961          * FIXME doing watermarks and fb cleanup from a vblank worker
14962          * (assuming we had any) would solve these problems.
14963          */
14964         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
14965                 struct intel_crtc_state *new_crtc_state;
14966                 struct intel_crtc *crtc;
14967                 int i;
14968
14969                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14970                         if (new_crtc_state->wm.need_postvbl_update ||
14971                             new_crtc_state->update_wm_post)
14972                                 state->base.legacy_cursor_update = false;
14973         }
14974
14975         ret = intel_atomic_prepare_commit(state);
14976         if (ret) {
14977                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14978                 i915_sw_fence_commit(&state->commit_ready);
14979                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14980                 return ret;
14981         }
14982
14983         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
14984         if (!ret)
14985                 ret = drm_atomic_helper_swap_state(&state->base, true);
14986
14987         if (ret) {
14988                 i915_sw_fence_commit(&state->commit_ready);
14989
14990                 drm_atomic_helper_cleanup_planes(dev, &state->base);
14991                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14992                 return ret;
14993         }
14994         dev_priv->wm.distrust_bios_wm = false;
14995         intel_shared_dpll_swap_state(state);
14996         intel_atomic_track_fbs(state);
14997
14998         if (state->global_state_changed) {
14999                 assert_global_state_locked(dev_priv);
15000
15001                 memcpy(dev_priv->min_cdclk, state->min_cdclk,
15002                        sizeof(state->min_cdclk));
15003                 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
15004                        sizeof(state->min_voltage_level));
15005                 dev_priv->active_pipes = state->active_pipes;
15006                 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
15007
15008                 intel_cdclk_swap_state(state);
15009         }
15010
15011         drm_atomic_state_get(&state->base);
15012         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15013
15014         i915_sw_fence_commit(&state->commit_ready);
15015         if (nonblock && state->modeset) {
15016                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15017         } else if (nonblock) {
15018                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15019         } else {
15020                 if (state->modeset)
15021                         flush_workqueue(dev_priv->modeset_wq);
15022                 intel_atomic_commit_tail(state);
15023         }
15024
15025         return 0;
15026 }
15027
15028 struct wait_rps_boost {
15029         struct wait_queue_entry wait;
15030
15031         struct drm_crtc *crtc;
15032         struct i915_request *request;
15033 };
15034
15035 static int do_rps_boost(struct wait_queue_entry *_wait,
15036                         unsigned mode, int sync, void *key)
15037 {
15038         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15039         struct i915_request *rq = wait->request;
15040
15041         /*
15042          * If we missed the vblank, but the request is already running it
15043          * is reasonable to assume that it will complete before the next
15044          * vblank without our intervention, so leave RPS alone.
15045          */
15046         if (!i915_request_started(rq))
15047                 intel_rps_boost(rq);
15048         i915_request_put(rq);
15049
15050         drm_crtc_vblank_put(wait->crtc);
15051
15052         list_del(&wait->wait.entry);
15053         kfree(wait);
15054         return 1;
15055 }
15056
15057 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15058                                        struct dma_fence *fence)
15059 {
15060         struct wait_rps_boost *wait;
15061
15062         if (!dma_fence_is_i915(fence))
15063                 return;
15064
15065         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15066                 return;
15067
15068         if (drm_crtc_vblank_get(crtc))
15069                 return;
15070
15071         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15072         if (!wait) {
15073                 drm_crtc_vblank_put(crtc);
15074                 return;
15075         }
15076
15077         wait->request = to_request(dma_fence_get(fence));
15078         wait->crtc = crtc;
15079
15080         wait->wait.func = do_rps_boost;
15081         wait->wait.flags = 0;
15082
15083         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15084 }
15085
15086 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15087 {
15088         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15089         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15090         struct drm_framebuffer *fb = plane_state->hw.fb;
15091         struct i915_vma *vma;
15092
15093         if (plane->id == PLANE_CURSOR &&
15094             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15095                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15096                 const int align = intel_cursor_alignment(dev_priv);
15097                 int err;
15098
15099                 err = i915_gem_object_attach_phys(obj, align);
15100                 if (err)
15101                         return err;
15102         }
15103
15104         vma = intel_pin_and_fence_fb_obj(fb,
15105                                          &plane_state->view,
15106                                          intel_plane_uses_fence(plane_state),
15107                                          &plane_state->flags);
15108         if (IS_ERR(vma))
15109                 return PTR_ERR(vma);
15110
15111         plane_state->vma = vma;
15112
15113         return 0;
15114 }
15115
15116 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15117 {
15118         struct i915_vma *vma;
15119
15120         vma = fetch_and_zero(&old_plane_state->vma);
15121         if (vma)
15122                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15123 }
15124
15125 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15126 {
15127         struct i915_sched_attr attr = {
15128                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15129         };
15130
15131         i915_gem_object_wait_priority(obj, 0, &attr);
15132 }
15133
15134 /**
15135  * intel_prepare_plane_fb - Prepare fb for usage on plane
15136  * @plane: drm plane to prepare for
15137  * @_new_plane_state: the plane state being prepared
15138  *
15139  * Prepares a framebuffer for usage on a display plane.  Generally this
15140  * involves pinning the underlying object and updating the frontbuffer tracking
15141  * bits.  Some older platforms need special physical address handling for
15142  * cursor planes.
15143  *
15144  * Returns 0 on success, negative error code on failure.
15145  */
15146 int
15147 intel_prepare_plane_fb(struct drm_plane *plane,
15148                        struct drm_plane_state *_new_plane_state)
15149 {
15150         struct intel_plane_state *new_plane_state =
15151                 to_intel_plane_state(_new_plane_state);
15152         struct intel_atomic_state *intel_state =
15153                 to_intel_atomic_state(new_plane_state->uapi.state);
15154         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15155         struct drm_framebuffer *fb = new_plane_state->hw.fb;
15156         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15157         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
15158         int ret;
15159
15160         if (old_obj) {
15161                 struct intel_crtc_state *crtc_state =
15162                         intel_atomic_get_new_crtc_state(intel_state,
15163                                                         to_intel_crtc(plane->state->crtc));
15164
15165                 /* Big Hammer, we also need to ensure that any pending
15166                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15167                  * current scanout is retired before unpinning the old
15168                  * framebuffer. Note that we rely on userspace rendering
15169                  * into the buffer attached to the pipe they are waiting
15170                  * on. If not, userspace generates a GPU hang with IPEHR
15171                  * point to the MI_WAIT_FOR_EVENT.
15172                  *
15173                  * This should only fail upon a hung GPU, in which case we
15174                  * can safely continue.
15175                  */
15176                 if (needs_modeset(crtc_state)) {
15177                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15178                                                               old_obj->base.resv, NULL,
15179                                                               false, 0,
15180                                                               GFP_KERNEL);
15181                         if (ret < 0)
15182                                 return ret;
15183                 }
15184         }
15185
15186         if (new_plane_state->uapi.fence) { /* explicit fencing */
15187                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
15188                                                     new_plane_state->uapi.fence,
15189                                                     I915_FENCE_TIMEOUT,
15190                                                     GFP_KERNEL);
15191                 if (ret < 0)
15192                         return ret;
15193         }
15194
15195         if (!obj)
15196                 return 0;
15197
15198         ret = i915_gem_object_pin_pages(obj);
15199         if (ret)
15200                 return ret;
15201
15202         ret = intel_plane_pin_fb(new_plane_state);
15203
15204         i915_gem_object_unpin_pages(obj);
15205         if (ret)
15206                 return ret;
15207
15208         fb_obj_bump_render_priority(obj);
15209         intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
15210
15211         if (!new_plane_state->uapi.fence) { /* implicit fencing */
15212                 struct dma_fence *fence;
15213
15214                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15215                                                       obj->base.resv, NULL,
15216                                                       false, I915_FENCE_TIMEOUT,
15217                                                       GFP_KERNEL);
15218                 if (ret < 0)
15219                         return ret;
15220
15221                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15222                 if (fence) {
15223                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15224                                                    fence);
15225                         dma_fence_put(fence);
15226                 }
15227         } else {
15228                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15229                                            new_plane_state->uapi.fence);
15230         }
15231
15232         /*
15233          * We declare pageflips to be interactive and so merit a small bias
15234          * towards upclocking to deliver the frame on time. By only changing
15235          * the RPS thresholds to sample more regularly and aim for higher
15236          * clocks we can hopefully deliver low power workloads (like kodi)
15237          * that are not quite steady state without resorting to forcing
15238          * maximum clocks following a vblank miss (see do_rps_boost()).
15239          */
15240         if (!intel_state->rps_interactive) {
15241                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15242                 intel_state->rps_interactive = true;
15243         }
15244
15245         return 0;
15246 }
15247
15248 /**
15249  * intel_cleanup_plane_fb - Cleans up an fb after plane use
15250  * @plane: drm plane to clean up for
15251  * @_old_plane_state: the state from the previous modeset
15252  *
15253  * Cleans up a framebuffer that has just been removed from a plane.
15254  */
15255 void
15256 intel_cleanup_plane_fb(struct drm_plane *plane,
15257                        struct drm_plane_state *_old_plane_state)
15258 {
15259         struct intel_plane_state *old_plane_state =
15260                 to_intel_plane_state(_old_plane_state);
15261         struct intel_atomic_state *intel_state =
15262                 to_intel_atomic_state(old_plane_state->uapi.state);
15263         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15264
15265         if (intel_state->rps_interactive) {
15266                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15267                 intel_state->rps_interactive = false;
15268         }
15269
15270         /* Should only be called after a successful intel_prepare_plane_fb()! */
15271         intel_plane_unpin_fb(old_plane_state);
15272 }
15273
15274 /**
15275  * intel_plane_destroy - destroy a plane
15276  * @plane: plane to destroy
15277  *
15278  * Common destruction function for all types of planes (primary, cursor,
15279  * sprite).
15280  */
15281 void intel_plane_destroy(struct drm_plane *plane)
15282 {
15283         drm_plane_cleanup(plane);
15284         kfree(to_intel_plane(plane));
15285 }
15286
15287 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15288                                             u32 format, u64 modifier)
15289 {
15290         switch (modifier) {
15291         case DRM_FORMAT_MOD_LINEAR:
15292         case I915_FORMAT_MOD_X_TILED:
15293                 break;
15294         default:
15295                 return false;
15296         }
15297
15298         switch (format) {
15299         case DRM_FORMAT_C8:
15300         case DRM_FORMAT_RGB565:
15301         case DRM_FORMAT_XRGB1555:
15302         case DRM_FORMAT_XRGB8888:
15303                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15304                         modifier == I915_FORMAT_MOD_X_TILED;
15305         default:
15306                 return false;
15307         }
15308 }
15309
15310 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15311                                             u32 format, u64 modifier)
15312 {
15313         switch (modifier) {
15314         case DRM_FORMAT_MOD_LINEAR:
15315         case I915_FORMAT_MOD_X_TILED:
15316                 break;
15317         default:
15318                 return false;
15319         }
15320
15321         switch (format) {
15322         case DRM_FORMAT_C8:
15323         case DRM_FORMAT_RGB565:
15324         case DRM_FORMAT_XRGB8888:
15325         case DRM_FORMAT_XBGR8888:
15326         case DRM_FORMAT_ARGB8888:
15327         case DRM_FORMAT_ABGR8888:
15328         case DRM_FORMAT_XRGB2101010:
15329         case DRM_FORMAT_XBGR2101010:
15330         case DRM_FORMAT_ARGB2101010:
15331         case DRM_FORMAT_ABGR2101010:
15332         case DRM_FORMAT_XBGR16161616F:
15333                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15334                         modifier == I915_FORMAT_MOD_X_TILED;
15335         default:
15336                 return false;
15337         }
15338 }
15339
15340 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15341                                               u32 format, u64 modifier)
15342 {
15343         return modifier == DRM_FORMAT_MOD_LINEAR &&
15344                 format == DRM_FORMAT_ARGB8888;
15345 }
15346
15347 static const struct drm_plane_funcs i965_plane_funcs = {
15348         .update_plane = drm_atomic_helper_update_plane,
15349         .disable_plane = drm_atomic_helper_disable_plane,
15350         .destroy = intel_plane_destroy,
15351         .atomic_duplicate_state = intel_plane_duplicate_state,
15352         .atomic_destroy_state = intel_plane_destroy_state,
15353         .format_mod_supported = i965_plane_format_mod_supported,
15354 };
15355
15356 static const struct drm_plane_funcs i8xx_plane_funcs = {
15357         .update_plane = drm_atomic_helper_update_plane,
15358         .disable_plane = drm_atomic_helper_disable_plane,
15359         .destroy = intel_plane_destroy,
15360         .atomic_duplicate_state = intel_plane_duplicate_state,
15361         .atomic_destroy_state = intel_plane_destroy_state,
15362         .format_mod_supported = i8xx_plane_format_mod_supported,
15363 };
15364
15365 static int
15366 intel_legacy_cursor_update(struct drm_plane *_plane,
15367                            struct drm_crtc *_crtc,
15368                            struct drm_framebuffer *fb,
15369                            int crtc_x, int crtc_y,
15370                            unsigned int crtc_w, unsigned int crtc_h,
15371                            u32 src_x, u32 src_y,
15372                            u32 src_w, u32 src_h,
15373                            struct drm_modeset_acquire_ctx *ctx)
15374 {
15375         struct intel_plane *plane = to_intel_plane(_plane);
15376         struct intel_crtc *crtc = to_intel_crtc(_crtc);
15377         struct intel_plane_state *old_plane_state =
15378                 to_intel_plane_state(plane->base.state);
15379         struct intel_plane_state *new_plane_state;
15380         struct intel_crtc_state *crtc_state =
15381                 to_intel_crtc_state(crtc->base.state);
15382         struct intel_crtc_state *new_crtc_state;
15383         int ret;
15384
15385         /*
15386          * When crtc is inactive or there is a modeset pending,
15387          * wait for it to complete in the slowpath
15388          */
15389         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
15390             crtc_state->update_pipe)
15391                 goto slow;
15392
15393         /*
15394          * Don't do an async update if there is an outstanding commit modifying
15395          * the plane.  This prevents our async update's changes from getting
15396          * overridden by a previous synchronous update's state.
15397          */
15398         if (old_plane_state->uapi.commit &&
15399             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
15400                 goto slow;
15401
15402         /*
15403          * If any parameters change that may affect watermarks,
15404          * take the slowpath. Only changing fb or position should be
15405          * in the fastpath.
15406          */
15407         if (old_plane_state->uapi.crtc != &crtc->base ||
15408             old_plane_state->uapi.src_w != src_w ||
15409             old_plane_state->uapi.src_h != src_h ||
15410             old_plane_state->uapi.crtc_w != crtc_w ||
15411             old_plane_state->uapi.crtc_h != crtc_h ||
15412             !old_plane_state->uapi.fb != !fb)
15413                 goto slow;
15414
15415         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
15416         if (!new_plane_state)
15417                 return -ENOMEM;
15418
15419         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
15420         if (!new_crtc_state) {
15421                 ret = -ENOMEM;
15422                 goto out_free;
15423         }
15424
15425         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
15426
15427         new_plane_state->uapi.src_x = src_x;
15428         new_plane_state->uapi.src_y = src_y;
15429         new_plane_state->uapi.src_w = src_w;
15430         new_plane_state->uapi.src_h = src_h;
15431         new_plane_state->uapi.crtc_x = crtc_x;
15432         new_plane_state->uapi.crtc_y = crtc_y;
15433         new_plane_state->uapi.crtc_w = crtc_w;
15434         new_plane_state->uapi.crtc_h = crtc_h;
15435
15436         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
15437                                                   old_plane_state, new_plane_state);
15438         if (ret)
15439                 goto out_free;
15440
15441         ret = intel_plane_pin_fb(new_plane_state);
15442         if (ret)
15443                 goto out_free;
15444
15445         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
15446                                 ORIGIN_FLIP);
15447         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15448                                 to_intel_frontbuffer(new_plane_state->hw.fb),
15449                                 plane->frontbuffer_bit);
15450
15451         /* Swap plane state */
15452         plane->base.state = &new_plane_state->uapi;
15453
15454         /*
15455          * We cannot swap crtc_state as it may be in use by an atomic commit or
15456          * page flip that's running simultaneously. If we swap crtc_state and
15457          * destroy the old state, we will cause a use-after-free there.
15458          *
15459          * Only update active_planes, which is needed for our internal
15460          * bookkeeping. Either value will do the right thing when updating
15461          * planes atomically. If the cursor was part of the atomic update then
15462          * we would have taken the slowpath.
15463          */
15464         crtc_state->active_planes = new_crtc_state->active_planes;
15465
15466         if (new_plane_state->uapi.visible)
15467                 intel_update_plane(plane, crtc_state, new_plane_state);
15468         else
15469                 intel_disable_plane(plane, crtc_state);
15470
15471         intel_plane_unpin_fb(old_plane_state);
15472
15473 out_free:
15474         if (new_crtc_state)
15475                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
15476         if (ret)
15477                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
15478         else
15479                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
15480         return ret;
15481
15482 slow:
15483         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
15484                                               crtc_x, crtc_y, crtc_w, crtc_h,
15485                                               src_x, src_y, src_w, src_h, ctx);
15486 }
15487
15488 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15489         .update_plane = intel_legacy_cursor_update,
15490         .disable_plane = drm_atomic_helper_disable_plane,
15491         .destroy = intel_plane_destroy,
15492         .atomic_duplicate_state = intel_plane_duplicate_state,
15493         .atomic_destroy_state = intel_plane_destroy_state,
15494         .format_mod_supported = intel_cursor_format_mod_supported,
15495 };
15496
15497 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
15498                                enum i9xx_plane_id i9xx_plane)
15499 {
15500         if (!HAS_FBC(dev_priv))
15501                 return false;
15502
15503         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15504                 return i9xx_plane == PLANE_A; /* tied to pipe A */
15505         else if (IS_IVYBRIDGE(dev_priv))
15506                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
15507                         i9xx_plane == PLANE_C;
15508         else if (INTEL_GEN(dev_priv) >= 4)
15509                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
15510         else
15511                 return i9xx_plane == PLANE_A;
15512 }
15513
15514 static struct intel_plane *
15515 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15516 {
15517         struct intel_plane *plane;
15518         const struct drm_plane_funcs *plane_funcs;
15519         unsigned int supported_rotations;
15520         unsigned int possible_crtcs;
15521         const u32 *formats;
15522         int num_formats;
15523         int ret, zpos;
15524
15525         if (INTEL_GEN(dev_priv) >= 9)
15526                 return skl_universal_plane_create(dev_priv, pipe,
15527                                                   PLANE_PRIMARY);
15528
15529         plane = intel_plane_alloc();
15530         if (IS_ERR(plane))
15531                 return plane;
15532
15533         plane->pipe = pipe;
15534         /*
15535          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15536          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15537          */
15538         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15539                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
15540         else
15541                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
15542         plane->id = PLANE_PRIMARY;
15543         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
15544
15545         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
15546         if (plane->has_fbc) {
15547                 struct intel_fbc *fbc = &dev_priv->fbc;
15548
15549                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
15550         }
15551
15552         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15553                 formats = vlv_primary_formats;
15554                 num_formats = ARRAY_SIZE(vlv_primary_formats);
15555         } else if (INTEL_GEN(dev_priv) >= 4) {
15556                 /*
15557                  * WaFP16GammaEnabling:ivb
15558                  * "Workaround : When using the 64-bit format, the plane
15559                  *  output on each color channel has one quarter amplitude.
15560                  *  It can be brought up to full amplitude by using pipe
15561                  *  gamma correction or pipe color space conversion to
15562                  *  multiply the plane output by four."
15563                  *
15564                  * There is no dedicated plane gamma for the primary plane,
15565                  * and using the pipe gamma/csc could conflict with other
15566                  * planes, so we choose not to expose fp16 on IVB primary
15567                  * planes. HSW primary planes no longer have this problem.
15568                  */
15569                 if (IS_IVYBRIDGE(dev_priv)) {
15570                         formats = ivb_primary_formats;
15571                         num_formats = ARRAY_SIZE(ivb_primary_formats);
15572                 } else {
15573                         formats = i965_primary_formats;
15574                         num_formats = ARRAY_SIZE(i965_primary_formats);
15575                 }
15576         } else {
15577                 formats = i8xx_primary_formats;
15578                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15579         }
15580
15581         if (INTEL_GEN(dev_priv) >= 4)
15582                 plane_funcs = &i965_plane_funcs;
15583         else
15584                 plane_funcs = &i8xx_plane_funcs;
15585
15586         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15587                 plane->min_cdclk = vlv_plane_min_cdclk;
15588         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15589                 plane->min_cdclk = hsw_plane_min_cdclk;
15590         else if (IS_IVYBRIDGE(dev_priv))
15591                 plane->min_cdclk = ivb_plane_min_cdclk;
15592         else
15593                 plane->min_cdclk = i9xx_plane_min_cdclk;
15594
15595         plane->max_stride = i9xx_plane_max_stride;
15596         plane->update_plane = i9xx_update_plane;
15597         plane->disable_plane = i9xx_disable_plane;
15598         plane->get_hw_state = i9xx_plane_get_hw_state;
15599         plane->check_plane = i9xx_plane_check;
15600
15601         possible_crtcs = BIT(pipe);
15602
15603         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15604                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15605                                                possible_crtcs, plane_funcs,
15606                                                formats, num_formats,
15607                                                i9xx_format_modifiers,
15608                                                DRM_PLANE_TYPE_PRIMARY,
15609                                                "primary %c", pipe_name(pipe));
15610         else
15611                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15612                                                possible_crtcs, plane_funcs,
15613                                                formats, num_formats,
15614                                                i9xx_format_modifiers,
15615                                                DRM_PLANE_TYPE_PRIMARY,
15616                                                "plane %c",
15617                                                plane_name(plane->i9xx_plane));
15618         if (ret)
15619                 goto fail;
15620
15621         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15622                 supported_rotations =
15623                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
15624                         DRM_MODE_REFLECT_X;
15625         } else if (INTEL_GEN(dev_priv) >= 4) {
15626                 supported_rotations =
15627                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
15628         } else {
15629                 supported_rotations = DRM_MODE_ROTATE_0;
15630         }
15631
15632         if (INTEL_GEN(dev_priv) >= 4)
15633                 drm_plane_create_rotation_property(&plane->base,
15634                                                    DRM_MODE_ROTATE_0,
15635                                                    supported_rotations);
15636
15637         zpos = 0;
15638         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
15639
15640         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
15641
15642         return plane;
15643
15644 fail:
15645         intel_plane_free(plane);
15646
15647         return ERR_PTR(ret);
15648 }
15649
15650 static struct intel_plane *
15651 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
15652                           enum pipe pipe)
15653 {
15654         unsigned int possible_crtcs;
15655         struct intel_plane *cursor;
15656         int ret, zpos;
15657
15658         cursor = intel_plane_alloc();
15659         if (IS_ERR(cursor))
15660                 return cursor;
15661
15662         cursor->pipe = pipe;
15663         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15664         cursor->id = PLANE_CURSOR;
15665         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15666
15667         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15668                 cursor->max_stride = i845_cursor_max_stride;
15669                 cursor->update_plane = i845_update_cursor;
15670                 cursor->disable_plane = i845_disable_cursor;
15671                 cursor->get_hw_state = i845_cursor_get_hw_state;
15672                 cursor->check_plane = i845_check_cursor;
15673         } else {
15674                 cursor->max_stride = i9xx_cursor_max_stride;
15675                 cursor->update_plane = i9xx_update_cursor;
15676                 cursor->disable_plane = i9xx_disable_cursor;
15677                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15678                 cursor->check_plane = i9xx_check_cursor;
15679         }
15680
15681         cursor->cursor.base = ~0;
15682         cursor->cursor.cntl = ~0;
15683
15684         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15685                 cursor->cursor.size = ~0;
15686
15687         possible_crtcs = BIT(pipe);
15688
15689         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15690                                        possible_crtcs, &intel_cursor_plane_funcs,
15691                                        intel_cursor_formats,
15692                                        ARRAY_SIZE(intel_cursor_formats),
15693                                        cursor_format_modifiers,
15694                                        DRM_PLANE_TYPE_CURSOR,
15695                                        "cursor %c", pipe_name(pipe));
15696         if (ret)
15697                 goto fail;
15698
15699         if (INTEL_GEN(dev_priv) >= 4)
15700                 drm_plane_create_rotation_property(&cursor->base,
15701                                                    DRM_MODE_ROTATE_0,
15702                                                    DRM_MODE_ROTATE_0 |
15703                                                    DRM_MODE_ROTATE_180);
15704
15705         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15706         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15707
15708         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15709
15710         return cursor;
15711
15712 fail:
15713         intel_plane_free(cursor);
15714
15715         return ERR_PTR(ret);
15716 }
15717
15718 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15719                                     struct intel_crtc_state *crtc_state)
15720 {
15721         struct intel_crtc_scaler_state *scaler_state =
15722                 &crtc_state->scaler_state;
15723         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15724         int i;
15725
15726         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
15727         if (!crtc->num_scalers)
15728                 return;
15729
15730         for (i = 0; i < crtc->num_scalers; i++) {
15731                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15732
15733                 scaler->in_use = 0;
15734                 scaler->mode = 0;
15735         }
15736
15737         scaler_state->scaler_id = -1;
15738 }
15739
15740 #define INTEL_CRTC_FUNCS \
15741         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15742         .set_config = drm_atomic_helper_set_config, \
15743         .destroy = intel_crtc_destroy, \
15744         .page_flip = drm_atomic_helper_page_flip, \
15745         .atomic_duplicate_state = intel_crtc_duplicate_state, \
15746         .atomic_destroy_state = intel_crtc_destroy_state, \
15747         .set_crc_source = intel_crtc_set_crc_source, \
15748         .verify_crc_source = intel_crtc_verify_crc_source, \
15749         .get_crc_sources = intel_crtc_get_crc_sources
15750
15751 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15752         INTEL_CRTC_FUNCS,
15753
15754         .get_vblank_counter = g4x_get_vblank_counter,
15755         .enable_vblank = bdw_enable_vblank,
15756         .disable_vblank = bdw_disable_vblank,
15757 };
15758
15759 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15760         INTEL_CRTC_FUNCS,
15761
15762         .get_vblank_counter = g4x_get_vblank_counter,
15763         .enable_vblank = ilk_enable_vblank,
15764         .disable_vblank = ilk_disable_vblank,
15765 };
15766
15767 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15768         INTEL_CRTC_FUNCS,
15769
15770         .get_vblank_counter = g4x_get_vblank_counter,
15771         .enable_vblank = i965_enable_vblank,
15772         .disable_vblank = i965_disable_vblank,
15773 };
15774
15775 static const struct drm_crtc_funcs i965_crtc_funcs = {
15776         INTEL_CRTC_FUNCS,
15777
15778         .get_vblank_counter = i915_get_vblank_counter,
15779         .enable_vblank = i965_enable_vblank,
15780         .disable_vblank = i965_disable_vblank,
15781 };
15782
15783 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
15784         INTEL_CRTC_FUNCS,
15785
15786         .get_vblank_counter = i915_get_vblank_counter,
15787         .enable_vblank = i915gm_enable_vblank,
15788         .disable_vblank = i915gm_disable_vblank,
15789 };
15790
15791 static const struct drm_crtc_funcs i915_crtc_funcs = {
15792         INTEL_CRTC_FUNCS,
15793
15794         .get_vblank_counter = i915_get_vblank_counter,
15795         .enable_vblank = i8xx_enable_vblank,
15796         .disable_vblank = i8xx_disable_vblank,
15797 };
15798
15799 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15800         INTEL_CRTC_FUNCS,
15801
15802         /* no hw vblank counter */
15803         .enable_vblank = i8xx_enable_vblank,
15804         .disable_vblank = i8xx_disable_vblank,
15805 };
15806
15807 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15808 {
15809         const struct drm_crtc_funcs *funcs;
15810         struct intel_crtc *intel_crtc;
15811         struct intel_crtc_state *crtc_state = NULL;
15812         struct intel_plane *primary = NULL;
15813         struct intel_plane *cursor = NULL;
15814         int sprite, ret;
15815
15816         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15817         if (!intel_crtc)
15818                 return -ENOMEM;
15819
15820         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15821         if (!crtc_state) {
15822                 ret = -ENOMEM;
15823                 goto fail;
15824         }
15825         __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
15826         intel_crtc->config = crtc_state;
15827
15828         primary = intel_primary_plane_create(dev_priv, pipe);
15829         if (IS_ERR(primary)) {
15830                 ret = PTR_ERR(primary);
15831                 goto fail;
15832         }
15833         intel_crtc->plane_ids_mask |= BIT(primary->id);
15834
15835         for_each_sprite(dev_priv, pipe, sprite) {
15836                 struct intel_plane *plane;
15837
15838                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15839                 if (IS_ERR(plane)) {
15840                         ret = PTR_ERR(plane);
15841                         goto fail;
15842                 }
15843                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15844         }
15845
15846         cursor = intel_cursor_plane_create(dev_priv, pipe);
15847         if (IS_ERR(cursor)) {
15848                 ret = PTR_ERR(cursor);
15849                 goto fail;
15850         }
15851         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15852
15853         if (HAS_GMCH(dev_priv)) {
15854                 if (IS_CHERRYVIEW(dev_priv) ||
15855                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15856                         funcs = &g4x_crtc_funcs;
15857                 else if (IS_GEN(dev_priv, 4))
15858                         funcs = &i965_crtc_funcs;
15859                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
15860                         funcs = &i915gm_crtc_funcs;
15861                 else if (IS_GEN(dev_priv, 3))
15862                         funcs = &i915_crtc_funcs;
15863                 else
15864                         funcs = &i8xx_crtc_funcs;
15865         } else {
15866                 if (INTEL_GEN(dev_priv) >= 8)
15867                         funcs = &bdw_crtc_funcs;
15868                 else
15869                         funcs = &ilk_crtc_funcs;
15870         }
15871
15872         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15873                                         &primary->base, &cursor->base,
15874                                         funcs, "pipe %c", pipe_name(pipe));
15875         if (ret)
15876                 goto fail;
15877
15878         intel_crtc->pipe = pipe;
15879
15880         /* initialize shared scalers */
15881         intel_crtc_init_scalers(intel_crtc, crtc_state);
15882
15883         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15884                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15885         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
15886
15887         if (INTEL_GEN(dev_priv) < 9) {
15888                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15889
15890                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15891                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15892                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
15893         }
15894
15895         intel_color_init(intel_crtc);
15896
15897         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15898
15899         return 0;
15900
15901 fail:
15902         /*
15903          * drm_mode_config_cleanup() will free up any
15904          * crtcs/planes already initialized.
15905          */
15906         kfree(crtc_state);
15907         kfree(intel_crtc);
15908
15909         return ret;
15910 }
15911
15912 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15913                                       struct drm_file *file)
15914 {
15915         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15916         struct drm_crtc *drmmode_crtc;
15917         struct intel_crtc *crtc;
15918
15919         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15920         if (!drmmode_crtc)
15921                 return -ENOENT;
15922
15923         crtc = to_intel_crtc(drmmode_crtc);
15924         pipe_from_crtc_id->pipe = crtc->pipe;
15925
15926         return 0;
15927 }
15928
15929 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
15930 {
15931         struct drm_device *dev = encoder->base.dev;
15932         struct intel_encoder *source_encoder;
15933         u32 possible_clones = 0;
15934
15935         for_each_intel_encoder(dev, source_encoder) {
15936                 if (encoders_cloneable(encoder, source_encoder))
15937                         possible_clones |= drm_encoder_mask(&source_encoder->base);
15938         }
15939
15940         return possible_clones;
15941 }
15942
15943 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
15944 {
15945         struct drm_device *dev = encoder->base.dev;
15946         struct intel_crtc *crtc;
15947         u32 possible_crtcs = 0;
15948
15949         for_each_intel_crtc(dev, crtc) {
15950                 if (encoder->pipe_mask & BIT(crtc->pipe))
15951                         possible_crtcs |= drm_crtc_mask(&crtc->base);
15952         }
15953
15954         return possible_crtcs;
15955 }
15956
15957 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
15958 {
15959         if (!IS_MOBILE(dev_priv))
15960                 return false;
15961
15962         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15963                 return false;
15964
15965         if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15966                 return false;
15967
15968         return true;
15969 }
15970
15971 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
15972 {
15973         if (INTEL_GEN(dev_priv) >= 9)
15974                 return false;
15975
15976         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15977                 return false;
15978
15979         if (HAS_PCH_LPT_H(dev_priv) &&
15980             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15981                 return false;
15982
15983         /* DDI E can't be used if DDI A requires 4 lanes */
15984         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15985                 return false;
15986
15987         if (!dev_priv->vbt.int_crt_support)
15988                 return false;
15989
15990         return true;
15991 }
15992
15993 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15994 {
15995         int pps_num;
15996         int pps_idx;
15997
15998         if (HAS_DDI(dev_priv))
15999                 return;
16000         /*
16001          * This w/a is needed at least on CPT/PPT, but to be sure apply it
16002          * everywhere where registers can be write protected.
16003          */
16004         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16005                 pps_num = 2;
16006         else
16007                 pps_num = 1;
16008
16009         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16010                 u32 val = I915_READ(PP_CONTROL(pps_idx));
16011
16012                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16013                 I915_WRITE(PP_CONTROL(pps_idx), val);
16014         }
16015 }
16016
16017 static void intel_pps_init(struct drm_i915_private *dev_priv)
16018 {
16019         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16020                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16021         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16022                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16023         else
16024                 dev_priv->pps_mmio_base = PPS_BASE;
16025
16026         intel_pps_unlock_regs_wa(dev_priv);
16027 }
16028
16029 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16030 {
16031         struct intel_encoder *encoder;
16032         bool dpd_is_edp = false;
16033
16034         intel_pps_init(dev_priv);
16035
16036         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16037                 return;
16038
16039         if (INTEL_GEN(dev_priv) >= 12) {
16040                 intel_ddi_init(dev_priv, PORT_A);
16041                 intel_ddi_init(dev_priv, PORT_B);
16042                 intel_ddi_init(dev_priv, PORT_D);
16043                 intel_ddi_init(dev_priv, PORT_E);
16044                 intel_ddi_init(dev_priv, PORT_F);
16045                 intel_ddi_init(dev_priv, PORT_G);
16046                 intel_ddi_init(dev_priv, PORT_H);
16047                 intel_ddi_init(dev_priv, PORT_I);
16048                 icl_dsi_init(dev_priv);
16049         } else if (IS_ELKHARTLAKE(dev_priv)) {
16050                 intel_ddi_init(dev_priv, PORT_A);
16051                 intel_ddi_init(dev_priv, PORT_B);
16052                 intel_ddi_init(dev_priv, PORT_C);
16053                 intel_ddi_init(dev_priv, PORT_D);
16054                 icl_dsi_init(dev_priv);
16055         } else if (IS_GEN(dev_priv, 11)) {
16056                 intel_ddi_init(dev_priv, PORT_A);
16057                 intel_ddi_init(dev_priv, PORT_B);
16058                 intel_ddi_init(dev_priv, PORT_C);
16059                 intel_ddi_init(dev_priv, PORT_D);
16060                 intel_ddi_init(dev_priv, PORT_E);
16061                 /*
16062                  * On some ICL SKUs port F is not present. No strap bits for
16063                  * this, so rely on VBT.
16064                  * Work around broken VBTs on SKUs known to have no port F.
16065                  */
16066                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16067                     intel_bios_is_port_present(dev_priv, PORT_F))
16068                         intel_ddi_init(dev_priv, PORT_F);
16069
16070                 icl_dsi_init(dev_priv);
16071         } else if (IS_GEN9_LP(dev_priv)) {
16072                 /*
16073                  * FIXME: Broxton doesn't support port detection via the
16074                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16075                  * detect the ports.
16076                  */
16077                 intel_ddi_init(dev_priv, PORT_A);
16078                 intel_ddi_init(dev_priv, PORT_B);
16079                 intel_ddi_init(dev_priv, PORT_C);
16080
16081                 vlv_dsi_init(dev_priv);
16082         } else if (HAS_DDI(dev_priv)) {
16083                 int found;
16084
16085                 if (intel_ddi_crt_present(dev_priv))
16086                         intel_crt_init(dev_priv);
16087
16088                 /*
16089                  * Haswell uses DDI functions to detect digital outputs.
16090                  * On SKL pre-D0 the strap isn't connected, so we assume
16091                  * it's there.
16092                  */
16093                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16094                 /* WaIgnoreDDIAStrap: skl */
16095                 if (found || IS_GEN9_BC(dev_priv))
16096                         intel_ddi_init(dev_priv, PORT_A);
16097
16098                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16099                  * register */
16100                 found = I915_READ(SFUSE_STRAP);
16101
16102                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16103                         intel_ddi_init(dev_priv, PORT_B);
16104                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16105                         intel_ddi_init(dev_priv, PORT_C);
16106                 if (found & SFUSE_STRAP_DDID_DETECTED)
16107                         intel_ddi_init(dev_priv, PORT_D);
16108                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16109                         intel_ddi_init(dev_priv, PORT_F);
16110                 /*
16111                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16112                  */
16113                 if (IS_GEN9_BC(dev_priv) &&
16114                     intel_bios_is_port_present(dev_priv, PORT_E))
16115                         intel_ddi_init(dev_priv, PORT_E);
16116
16117         } else if (HAS_PCH_SPLIT(dev_priv)) {
16118                 int found;
16119
16120                 /*
16121                  * intel_edp_init_connector() depends on this completing first,
16122                  * to prevent the registration of both eDP and LVDS and the
16123                  * incorrect sharing of the PPS.
16124                  */
16125                 intel_lvds_init(dev_priv);
16126                 intel_crt_init(dev_priv);
16127
16128                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16129
16130                 if (ilk_has_edp_a(dev_priv))
16131                         intel_dp_init(dev_priv, DP_A, PORT_A);
16132
16133                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
16134                         /* PCH SDVOB multiplex with HDMIB */
16135                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16136                         if (!found)
16137                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16138                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
16139                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16140                 }
16141
16142                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
16143                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16144
16145                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
16146                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16147
16148                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
16149                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16150
16151                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
16152                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16153         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16154                 bool has_edp, has_port;
16155
16156                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16157                         intel_crt_init(dev_priv);
16158
16159                 /*
16160                  * The DP_DETECTED bit is the latched state of the DDC
16161                  * SDA pin at boot. However since eDP doesn't require DDC
16162                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16163                  * eDP ports may have been muxed to an alternate function.
16164                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16165                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16166                  * detect eDP ports.
16167                  *
16168                  * Sadly the straps seem to be missing sometimes even for HDMI
16169                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16170                  * and VBT for the presence of the port. Additionally we can't
16171                  * trust the port type the VBT declares as we've seen at least
16172                  * HDMI ports that the VBT claim are DP or eDP.
16173                  */
16174                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16175                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16176                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
16177                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16178                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16179                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16180
16181                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16182                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16183                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
16184                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16185                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16186                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16187
16188                 if (IS_CHERRYVIEW(dev_priv)) {
16189                         /*
16190                          * eDP not supported on port D,
16191                          * so no need to worry about it
16192                          */
16193                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16194                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
16195                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16196                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
16197                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16198                 }
16199
16200                 vlv_dsi_init(dev_priv);
16201         } else if (IS_PINEVIEW(dev_priv)) {
16202                 intel_lvds_init(dev_priv);
16203                 intel_crt_init(dev_priv);
16204         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16205                 bool found = false;
16206
16207                 if (IS_MOBILE(dev_priv))
16208                         intel_lvds_init(dev_priv);
16209
16210                 intel_crt_init(dev_priv);
16211
16212                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16213                         DRM_DEBUG_KMS("probing SDVOB\n");
16214                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16215                         if (!found && IS_G4X(dev_priv)) {
16216                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
16217                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16218                         }
16219
16220                         if (!found && IS_G4X(dev_priv))
16221                                 intel_dp_init(dev_priv, DP_B, PORT_B);
16222                 }
16223
16224                 /* Before G4X SDVOC doesn't have its own detect register */
16225
16226                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16227                         DRM_DEBUG_KMS("probing SDVOC\n");
16228                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16229                 }
16230
16231                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
16232
16233                         if (IS_G4X(dev_priv)) {
16234                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
16235                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16236                         }
16237                         if (IS_G4X(dev_priv))
16238                                 intel_dp_init(dev_priv, DP_C, PORT_C);
16239                 }
16240
16241                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
16242                         intel_dp_init(dev_priv, DP_D, PORT_D);
16243
16244                 if (SUPPORTS_TV(dev_priv))
16245                         intel_tv_init(dev_priv);
16246         } else if (IS_GEN(dev_priv, 2)) {
16247                 if (IS_I85X(dev_priv))
16248                         intel_lvds_init(dev_priv);
16249
16250                 intel_crt_init(dev_priv);
16251                 intel_dvo_init(dev_priv);
16252         }
16253
16254         intel_psr_init(dev_priv);
16255
16256         for_each_intel_encoder(&dev_priv->drm, encoder) {
16257                 encoder->base.possible_crtcs =
16258                         intel_encoder_possible_crtcs(encoder);
16259                 encoder->base.possible_clones =
16260                         intel_encoder_possible_clones(encoder);
16261         }
16262
16263         intel_init_pch_refclk(dev_priv);
16264
16265         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16266 }
16267
16268 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16269 {
16270         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16271
16272         drm_framebuffer_cleanup(fb);
16273         intel_frontbuffer_put(intel_fb->frontbuffer);
16274
16275         kfree(intel_fb);
16276 }
16277
16278 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16279                                                 struct drm_file *file,
16280                                                 unsigned int *handle)
16281 {
16282         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16283
16284         if (obj->userptr.mm) {
16285                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
16286                 return -EINVAL;
16287         }
16288
16289         return drm_gem_handle_create(file, &obj->base, handle);
16290 }
16291
16292 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16293                                         struct drm_file *file,
16294                                         unsigned flags, unsigned color,
16295                                         struct drm_clip_rect *clips,
16296                                         unsigned num_clips)
16297 {
16298         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16299
16300         i915_gem_object_flush_if_display(obj);
16301         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16302
16303         return 0;
16304 }
16305
16306 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16307         .destroy = intel_user_framebuffer_destroy,
16308         .create_handle = intel_user_framebuffer_create_handle,
16309         .dirty = intel_user_framebuffer_dirty,
16310 };
16311
16312 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16313                                   struct drm_i915_gem_object *obj,
16314                                   struct drm_mode_fb_cmd2 *mode_cmd)
16315 {
16316         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16317         struct drm_framebuffer *fb = &intel_fb->base;
16318         u32 max_stride;
16319         unsigned int tiling, stride;
16320         int ret = -EINVAL;
16321         int i;
16322
16323         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16324         if (!intel_fb->frontbuffer)
16325                 return -ENOMEM;
16326
16327         i915_gem_object_lock(obj);
16328         tiling = i915_gem_object_get_tiling(obj);
16329         stride = i915_gem_object_get_stride(obj);
16330         i915_gem_object_unlock(obj);
16331
16332         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16333                 /*
16334                  * If there's a fence, enforce that
16335                  * the fb modifier and tiling mode match.
16336                  */
16337                 if (tiling != I915_TILING_NONE &&
16338                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16339                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
16340                         goto err;
16341                 }
16342         } else {
16343                 if (tiling == I915_TILING_X) {
16344                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16345                 } else if (tiling == I915_TILING_Y) {
16346                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
16347                         goto err;
16348                 }
16349         }
16350
16351         if (!drm_any_plane_has_format(&dev_priv->drm,
16352                                       mode_cmd->pixel_format,
16353                                       mode_cmd->modifier[0])) {
16354                 struct drm_format_name_buf format_name;
16355
16356                 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
16357                               drm_get_format_name(mode_cmd->pixel_format,
16358                                                   &format_name),
16359                               mode_cmd->modifier[0]);
16360                 goto err;
16361         }
16362
16363         /*
16364          * gen2/3 display engine uses the fence if present,
16365          * so the tiling mode must match the fb modifier exactly.
16366          */
16367         if (INTEL_GEN(dev_priv) < 4 &&
16368             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16369                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
16370                 goto err;
16371         }
16372
16373         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
16374                                          mode_cmd->modifier[0]);
16375         if (mode_cmd->pitches[0] > max_stride) {
16376                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
16377                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
16378                               "tiled" : "linear",
16379                               mode_cmd->pitches[0], max_stride);
16380                 goto err;
16381         }
16382
16383         /*
16384          * If there's a fence, enforce that
16385          * the fb pitch and fence stride match.
16386          */
16387         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
16388                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
16389                               mode_cmd->pitches[0], stride);
16390                 goto err;
16391         }
16392
16393         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16394         if (mode_cmd->offsets[0] != 0)
16395                 goto err;
16396
16397         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
16398
16399         for (i = 0; i < fb->format->num_planes; i++) {
16400                 u32 stride_alignment;
16401
16402                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
16403                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
16404                         goto err;
16405                 }
16406
16407                 stride_alignment = intel_fb_stride_alignment(fb, i);
16408
16409                 /*
16410                  * Display WA #0531: skl,bxt,kbl,glk
16411                  *
16412                  * Render decompression and plane width > 3840
16413                  * combined with horizontal panning requires the
16414                  * plane stride to be a multiple of 4. We'll just
16415                  * require the entire fb to accommodate that to avoid
16416                  * potential runtime errors at plane configuration time.
16417                  */
16418                 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
16419                     is_ccs_modifier(fb->modifier))
16420                         stride_alignment *= 4;
16421
16422                 if (fb->pitches[i] & (stride_alignment - 1)) {
16423                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
16424                                       i, fb->pitches[i], stride_alignment);
16425                         goto err;
16426                 }
16427
16428                 fb->obj[i] = &obj->base;
16429         }
16430
16431         ret = intel_fill_fb_info(dev_priv, fb);
16432         if (ret)
16433                 goto err;
16434
16435         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
16436         if (ret) {
16437                 DRM_ERROR("framebuffer init failed %d\n", ret);
16438                 goto err;
16439         }
16440
16441         return 0;
16442
16443 err:
16444         intel_frontbuffer_put(intel_fb->frontbuffer);
16445         return ret;
16446 }
16447
16448 static struct drm_framebuffer *
16449 intel_user_framebuffer_create(struct drm_device *dev,
16450                               struct drm_file *filp,
16451                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16452 {
16453         struct drm_framebuffer *fb;
16454         struct drm_i915_gem_object *obj;
16455         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16456
16457         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16458         if (!obj)
16459                 return ERR_PTR(-ENOENT);
16460
16461         fb = intel_framebuffer_create(obj, &mode_cmd);
16462         i915_gem_object_put(obj);
16463
16464         return fb;
16465 }
16466
16467 static void intel_atomic_state_free(struct drm_atomic_state *state)
16468 {
16469         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16470
16471         drm_atomic_state_default_release(state);
16472
16473         i915_sw_fence_fini(&intel_state->commit_ready);
16474
16475         kfree(state);
16476 }
16477
16478 static enum drm_mode_status
16479 intel_mode_valid(struct drm_device *dev,
16480                  const struct drm_display_mode *mode)
16481 {
16482         struct drm_i915_private *dev_priv = to_i915(dev);
16483         int hdisplay_max, htotal_max;
16484         int vdisplay_max, vtotal_max;
16485
16486         /*
16487          * Can't reject DBLSCAN here because Xorg ddxen can add piles
16488          * of DBLSCAN modes to the output's mode list when they detect
16489          * the scaling mode property on the connector. And they don't
16490          * ask the kernel to validate those modes in any way until
16491          * modeset time at which point the client gets a protocol error.
16492          * So in order to not upset those clients we silently ignore the
16493          * DBLSCAN flag on such connectors. For other connectors we will
16494          * reject modes with the DBLSCAN flag in encoder->compute_config().
16495          * And we always reject DBLSCAN modes in connector->mode_valid()
16496          * as we never want such modes on the connector's mode list.
16497          */
16498
16499         if (mode->vscan > 1)
16500                 return MODE_NO_VSCAN;
16501
16502         if (mode->flags & DRM_MODE_FLAG_HSKEW)
16503                 return MODE_H_ILLEGAL;
16504
16505         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
16506                            DRM_MODE_FLAG_NCSYNC |
16507                            DRM_MODE_FLAG_PCSYNC))
16508                 return MODE_HSYNC;
16509
16510         if (mode->flags & (DRM_MODE_FLAG_BCAST |
16511                            DRM_MODE_FLAG_PIXMUX |
16512                            DRM_MODE_FLAG_CLKDIV2))
16513                 return MODE_BAD;
16514
16515         /* Transcoder timing limits */
16516         if (INTEL_GEN(dev_priv) >= 11) {
16517                 hdisplay_max = 16384;
16518                 vdisplay_max = 8192;
16519                 htotal_max = 16384;
16520                 vtotal_max = 8192;
16521         } else if (INTEL_GEN(dev_priv) >= 9 ||
16522                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
16523                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
16524                 vdisplay_max = 4096;
16525                 htotal_max = 8192;
16526                 vtotal_max = 8192;
16527         } else if (INTEL_GEN(dev_priv) >= 3) {
16528                 hdisplay_max = 4096;
16529                 vdisplay_max = 4096;
16530                 htotal_max = 8192;
16531                 vtotal_max = 8192;
16532         } else {
16533                 hdisplay_max = 2048;
16534                 vdisplay_max = 2048;
16535                 htotal_max = 4096;
16536                 vtotal_max = 4096;
16537         }
16538
16539         if (mode->hdisplay > hdisplay_max ||
16540             mode->hsync_start > htotal_max ||
16541             mode->hsync_end > htotal_max ||
16542             mode->htotal > htotal_max)
16543                 return MODE_H_ILLEGAL;
16544
16545         if (mode->vdisplay > vdisplay_max ||
16546             mode->vsync_start > vtotal_max ||
16547             mode->vsync_end > vtotal_max ||
16548             mode->vtotal > vtotal_max)
16549                 return MODE_V_ILLEGAL;
16550
16551         if (INTEL_GEN(dev_priv) >= 5) {
16552                 if (mode->hdisplay < 64 ||
16553                     mode->htotal - mode->hdisplay < 32)
16554                         return MODE_H_ILLEGAL;
16555
16556                 if (mode->vtotal - mode->vdisplay < 5)
16557                         return MODE_V_ILLEGAL;
16558         } else {
16559                 if (mode->htotal - mode->hdisplay < 32)
16560                         return MODE_H_ILLEGAL;
16561
16562                 if (mode->vtotal - mode->vdisplay < 3)
16563                         return MODE_V_ILLEGAL;
16564         }
16565
16566         return MODE_OK;
16567 }
16568
16569 enum drm_mode_status
16570 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
16571                                 const struct drm_display_mode *mode)
16572 {
16573         int plane_width_max, plane_height_max;
16574
16575         /*
16576          * intel_mode_valid() should be
16577          * sufficient on older platforms.
16578          */
16579         if (INTEL_GEN(dev_priv) < 9)
16580                 return MODE_OK;
16581
16582         /*
16583          * Most people will probably want a fullscreen
16584          * plane so let's not advertize modes that are
16585          * too big for that.
16586          */
16587         if (INTEL_GEN(dev_priv) >= 11) {
16588                 plane_width_max = 5120;
16589                 plane_height_max = 4320;
16590         } else {
16591                 plane_width_max = 5120;
16592                 plane_height_max = 4096;
16593         }
16594
16595         if (mode->hdisplay > plane_width_max)
16596                 return MODE_H_ILLEGAL;
16597
16598         if (mode->vdisplay > plane_height_max)
16599                 return MODE_V_ILLEGAL;
16600
16601         return MODE_OK;
16602 }
16603
16604 static const struct drm_mode_config_funcs intel_mode_funcs = {
16605         .fb_create = intel_user_framebuffer_create,
16606         .get_format_info = intel_get_format_info,
16607         .output_poll_changed = intel_fbdev_output_poll_changed,
16608         .mode_valid = intel_mode_valid,
16609         .atomic_check = intel_atomic_check,
16610         .atomic_commit = intel_atomic_commit,
16611         .atomic_state_alloc = intel_atomic_state_alloc,
16612         .atomic_state_clear = intel_atomic_state_clear,
16613         .atomic_state_free = intel_atomic_state_free,
16614 };
16615
16616 /**
16617  * intel_init_display_hooks - initialize the display modesetting hooks
16618  * @dev_priv: device private
16619  */
16620 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16621 {
16622         intel_init_cdclk_hooks(dev_priv);
16623
16624         if (INTEL_GEN(dev_priv) >= 9) {
16625                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16626                 dev_priv->display.get_initial_plane_config =
16627                         skylake_get_initial_plane_config;
16628                 dev_priv->display.crtc_compute_clock =
16629                         haswell_crtc_compute_clock;
16630                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16631                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16632         } else if (HAS_DDI(dev_priv)) {
16633                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16634                 dev_priv->display.get_initial_plane_config =
16635                         i9xx_get_initial_plane_config;
16636                 dev_priv->display.crtc_compute_clock =
16637                         haswell_crtc_compute_clock;
16638                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16639                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16640         } else if (HAS_PCH_SPLIT(dev_priv)) {
16641                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16642                 dev_priv->display.get_initial_plane_config =
16643                         i9xx_get_initial_plane_config;
16644                 dev_priv->display.crtc_compute_clock =
16645                         ironlake_crtc_compute_clock;
16646                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16647                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16648         } else if (IS_CHERRYVIEW(dev_priv)) {
16649                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16650                 dev_priv->display.get_initial_plane_config =
16651                         i9xx_get_initial_plane_config;
16652                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16653                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16654                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16655         } else if (IS_VALLEYVIEW(dev_priv)) {
16656                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16657                 dev_priv->display.get_initial_plane_config =
16658                         i9xx_get_initial_plane_config;
16659                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16660                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16661                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16662         } else if (IS_G4X(dev_priv)) {
16663                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16664                 dev_priv->display.get_initial_plane_config =
16665                         i9xx_get_initial_plane_config;
16666                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16667                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16668                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16669         } else if (IS_PINEVIEW(dev_priv)) {
16670                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16671                 dev_priv->display.get_initial_plane_config =
16672                         i9xx_get_initial_plane_config;
16673                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16674                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16675                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16676         } else if (!IS_GEN(dev_priv, 2)) {
16677                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16678                 dev_priv->display.get_initial_plane_config =
16679                         i9xx_get_initial_plane_config;
16680                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16681                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16682                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16683         } else {
16684                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16685                 dev_priv->display.get_initial_plane_config =
16686                         i9xx_get_initial_plane_config;
16687                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16688                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16689                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16690         }
16691
16692         if (IS_GEN(dev_priv, 5)) {
16693                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16694         } else if (IS_GEN(dev_priv, 6)) {
16695                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16696         } else if (IS_IVYBRIDGE(dev_priv)) {
16697                 /* FIXME: detect B0+ stepping and use auto training */
16698                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16699         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16700                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16701         }
16702
16703         if (INTEL_GEN(dev_priv) >= 9)
16704                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
16705         else
16706                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
16707
16708 }
16709
16710 void intel_modeset_init_hw(struct drm_i915_private *i915)
16711 {
16712         intel_update_cdclk(i915);
16713         intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
16714         i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
16715 }
16716
16717 /*
16718  * Calculate what we think the watermarks should be for the state we've read
16719  * out of the hardware and then immediately program those watermarks so that
16720  * we ensure the hardware settings match our internal state.
16721  *
16722  * We can calculate what we think WM's should be by creating a duplicate of the
16723  * current state (which was constructed during hardware readout) and running it
16724  * through the atomic check code to calculate new watermark values in the
16725  * state object.
16726  */
16727 static void sanitize_watermarks(struct drm_device *dev)
16728 {
16729         struct drm_i915_private *dev_priv = to_i915(dev);
16730         struct drm_atomic_state *state;
16731         struct intel_atomic_state *intel_state;
16732         struct intel_crtc *crtc;
16733         struct intel_crtc_state *crtc_state;
16734         struct drm_modeset_acquire_ctx ctx;
16735         int ret;
16736         int i;
16737
16738         /* Only supported on platforms that use atomic watermark design */
16739         if (!dev_priv->display.optimize_watermarks)
16740                 return;
16741
16742         /*
16743          * We need to hold connection_mutex before calling duplicate_state so
16744          * that the connector loop is protected.
16745          */
16746         drm_modeset_acquire_init(&ctx, 0);
16747 retry:
16748         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16749         if (ret == -EDEADLK) {
16750                 drm_modeset_backoff(&ctx);
16751                 goto retry;
16752         } else if (WARN_ON(ret)) {
16753                 goto fail;
16754         }
16755
16756         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16757         if (WARN_ON(IS_ERR(state)))
16758                 goto fail;
16759
16760         intel_state = to_intel_atomic_state(state);
16761
16762         /*
16763          * Hardware readout is the only time we don't want to calculate
16764          * intermediate watermarks (since we don't trust the current
16765          * watermarks).
16766          */
16767         if (!HAS_GMCH(dev_priv))
16768                 intel_state->skip_intermediate_wm = true;
16769
16770         ret = intel_atomic_check(dev, state);
16771         if (ret) {
16772                 /*
16773                  * If we fail here, it means that the hardware appears to be
16774                  * programmed in a way that shouldn't be possible, given our
16775                  * understanding of watermark requirements.  This might mean a
16776                  * mistake in the hardware readout code or a mistake in the
16777                  * watermark calculations for a given platform.  Raise a WARN
16778                  * so that this is noticeable.
16779                  *
16780                  * If this actually happens, we'll have to just leave the
16781                  * BIOS-programmed watermarks untouched and hope for the best.
16782                  */
16783                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16784                 goto put_state;
16785         }
16786
16787         /* Write calculated watermark values back */
16788         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16789                 crtc_state->wm.need_postvbl_update = true;
16790                 dev_priv->display.optimize_watermarks(intel_state, crtc);
16791
16792                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16793         }
16794
16795 put_state:
16796         drm_atomic_state_put(state);
16797 fail:
16798         drm_modeset_drop_locks(&ctx);
16799         drm_modeset_acquire_fini(&ctx);
16800 }
16801
16802 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16803 {
16804         if (IS_GEN(dev_priv, 5)) {
16805                 u32 fdi_pll_clk =
16806                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16807
16808                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16809         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16810                 dev_priv->fdi_pll_freq = 270000;
16811         } else {
16812                 return;
16813         }
16814
16815         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16816 }
16817
16818 static int intel_initial_commit(struct drm_device *dev)
16819 {
16820         struct drm_atomic_state *state = NULL;
16821         struct drm_modeset_acquire_ctx ctx;
16822         struct intel_crtc *crtc;
16823         int ret = 0;
16824
16825         state = drm_atomic_state_alloc(dev);
16826         if (!state)
16827                 return -ENOMEM;
16828
16829         drm_modeset_acquire_init(&ctx, 0);
16830
16831 retry:
16832         state->acquire_ctx = &ctx;
16833
16834         for_each_intel_crtc(dev, crtc) {
16835                 struct intel_crtc_state *crtc_state =
16836                         intel_atomic_get_crtc_state(state, crtc);
16837
16838                 if (IS_ERR(crtc_state)) {
16839                         ret = PTR_ERR(crtc_state);
16840                         goto out;
16841                 }
16842
16843                 if (crtc_state->hw.active) {
16844                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
16845                         if (ret)
16846                                 goto out;
16847
16848                         /*
16849                          * FIXME hack to force a LUT update to avoid the
16850                          * plane update forcing the pipe gamma on without
16851                          * having a proper LUT loaded. Remove once we
16852                          * have readout for pipe gamma enable.
16853                          */
16854                         crtc_state->uapi.color_mgmt_changed = true;
16855                 }
16856         }
16857
16858         ret = drm_atomic_commit(state);
16859
16860 out:
16861         if (ret == -EDEADLK) {
16862                 drm_atomic_state_clear(state);
16863                 drm_modeset_backoff(&ctx);
16864                 goto retry;
16865         }
16866
16867         drm_atomic_state_put(state);
16868
16869         drm_modeset_drop_locks(&ctx);
16870         drm_modeset_acquire_fini(&ctx);
16871
16872         return ret;
16873 }
16874
16875 static void intel_mode_config_init(struct drm_i915_private *i915)
16876 {
16877         struct drm_mode_config *mode_config = &i915->drm.mode_config;
16878
16879         drm_mode_config_init(&i915->drm);
16880
16881         mode_config->min_width = 0;
16882         mode_config->min_height = 0;
16883
16884         mode_config->preferred_depth = 24;
16885         mode_config->prefer_shadow = 1;
16886
16887         mode_config->allow_fb_modifiers = true;
16888
16889         mode_config->funcs = &intel_mode_funcs;
16890
16891         /*
16892          * Maximum framebuffer dimensions, chosen to match
16893          * the maximum render engine surface size on gen4+.
16894          */
16895         if (INTEL_GEN(i915) >= 7) {
16896                 mode_config->max_width = 16384;
16897                 mode_config->max_height = 16384;
16898         } else if (INTEL_GEN(i915) >= 4) {
16899                 mode_config->max_width = 8192;
16900                 mode_config->max_height = 8192;
16901         } else if (IS_GEN(i915, 3)) {
16902                 mode_config->max_width = 4096;
16903                 mode_config->max_height = 4096;
16904         } else {
16905                 mode_config->max_width = 2048;
16906                 mode_config->max_height = 2048;
16907         }
16908
16909         if (IS_I845G(i915) || IS_I865G(i915)) {
16910                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
16911                 mode_config->cursor_height = 1023;
16912         } else if (IS_GEN(i915, 2)) {
16913                 mode_config->cursor_width = 64;
16914                 mode_config->cursor_height = 64;
16915         } else {
16916                 mode_config->cursor_width = 256;
16917                 mode_config->cursor_height = 256;
16918         }
16919 }
16920
16921 int intel_modeset_init(struct drm_i915_private *i915)
16922 {
16923         struct drm_device *dev = &i915->drm;
16924         enum pipe pipe;
16925         struct intel_crtc *crtc;
16926         int ret;
16927
16928         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16929         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16930                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16931
16932         intel_mode_config_init(i915);
16933
16934         ret = intel_bw_init(i915);
16935         if (ret)
16936                 return ret;
16937
16938         init_llist_head(&i915->atomic_helper.free_list);
16939         INIT_WORK(&i915->atomic_helper.free_work,
16940                   intel_atomic_helper_free_state_worker);
16941
16942         intel_init_quirks(i915);
16943
16944         intel_fbc_init(i915);
16945
16946         intel_init_pm(i915);
16947
16948         intel_panel_sanitize_ssc(i915);
16949
16950         intel_gmbus_setup(i915);
16951
16952         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16953                       INTEL_NUM_PIPES(i915),
16954                       INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
16955
16956         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
16957                 for_each_pipe(i915, pipe) {
16958                         ret = intel_crtc_init(i915, pipe);
16959                         if (ret) {
16960                                 drm_mode_config_cleanup(dev);
16961                                 return ret;
16962                         }
16963                 }
16964         }
16965
16966         intel_shared_dpll_init(dev);
16967         intel_update_fdi_pll_freq(i915);
16968
16969         intel_update_czclk(i915);
16970         intel_modeset_init_hw(i915);
16971
16972         intel_hdcp_component_init(i915);
16973
16974         if (i915->max_cdclk_freq == 0)
16975                 intel_update_max_cdclk(i915);
16976
16977         /* Just disable it once at startup */
16978         intel_vga_disable(i915);
16979         intel_setup_outputs(i915);
16980
16981         drm_modeset_lock_all(dev);
16982         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
16983         drm_modeset_unlock_all(dev);
16984
16985         for_each_intel_crtc(dev, crtc) {
16986                 struct intel_initial_plane_config plane_config = {};
16987
16988                 if (!crtc->active)
16989                         continue;
16990
16991                 /*
16992                  * Note that reserving the BIOS fb up front prevents us
16993                  * from stuffing other stolen allocations like the ring
16994                  * on top.  This prevents some ugliness at boot time, and
16995                  * can even allow for smooth boot transitions if the BIOS
16996                  * fb is large enough for the active pipe configuration.
16997                  */
16998                 i915->display.get_initial_plane_config(crtc, &plane_config);
16999
17000                 /*
17001                  * If the fb is shared between multiple heads, we'll
17002                  * just get the first one.
17003                  */
17004                 intel_find_initial_plane_obj(crtc, &plane_config);
17005         }
17006
17007         /*
17008          * Make sure hardware watermarks really match the state we read out.
17009          * Note that we need to do this after reconstructing the BIOS fb's
17010          * since the watermark calculation done here will use pstate->fb.
17011          */
17012         if (!HAS_GMCH(i915))
17013                 sanitize_watermarks(dev);
17014
17015         /*
17016          * Force all active planes to recompute their states. So that on
17017          * mode_setcrtc after probe, all the intel_plane_state variables
17018          * are already calculated and there is no assert_plane warnings
17019          * during bootup.
17020          */
17021         ret = intel_initial_commit(dev);
17022         if (ret)
17023                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
17024
17025         return 0;
17026 }
17027
17028 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17029 {
17030         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17031         /* 640x480@60Hz, ~25175 kHz */
17032         struct dpll clock = {
17033                 .m1 = 18,
17034                 .m2 = 7,
17035                 .p1 = 13,
17036                 .p2 = 4,
17037                 .n = 2,
17038         };
17039         u32 dpll, fp;
17040         int i;
17041
17042         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
17043
17044         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17045                       pipe_name(pipe), clock.vco, clock.dot);
17046
17047         fp = i9xx_dpll_compute_fp(&clock);
17048         dpll = DPLL_DVO_2X_MODE |
17049                 DPLL_VGA_MODE_DIS |
17050                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17051                 PLL_P2_DIVIDE_BY_4 |
17052                 PLL_REF_INPUT_DREFCLK |
17053                 DPLL_VCO_ENABLE;
17054
17055         I915_WRITE(FP0(pipe), fp);
17056         I915_WRITE(FP1(pipe), fp);
17057
17058         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17059         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17060         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17061         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17062         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17063         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17064         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17065
17066         /*
17067          * Apparently we need to have VGA mode enabled prior to changing
17068          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17069          * dividers, even though the register value does change.
17070          */
17071         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17072         I915_WRITE(DPLL(pipe), dpll);
17073
17074         /* Wait for the clocks to stabilize. */
17075         POSTING_READ(DPLL(pipe));
17076         udelay(150);
17077
17078         /* The pixel multiplier can only be updated once the
17079          * DPLL is enabled and the clocks are stable.
17080          *
17081          * So write it again.
17082          */
17083         I915_WRITE(DPLL(pipe), dpll);
17084
17085         /* We do this three times for luck */
17086         for (i = 0; i < 3 ; i++) {
17087                 I915_WRITE(DPLL(pipe), dpll);
17088                 POSTING_READ(DPLL(pipe));
17089                 udelay(150); /* wait for warmup */
17090         }
17091
17092         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17093         POSTING_READ(PIPECONF(pipe));
17094
17095         intel_wait_for_pipe_scanline_moving(crtc);
17096 }
17097
17098 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17099 {
17100         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17101
17102         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
17103                       pipe_name(pipe));
17104
17105         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
17106         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
17107         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
17108         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
17109         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
17110
17111         I915_WRITE(PIPECONF(pipe), 0);
17112         POSTING_READ(PIPECONF(pipe));
17113
17114         intel_wait_for_pipe_scanline_stopped(crtc);
17115
17116         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
17117         POSTING_READ(DPLL(pipe));
17118 }
17119
17120 static void
17121 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17122 {
17123         struct intel_crtc *crtc;
17124
17125         if (INTEL_GEN(dev_priv) >= 4)
17126                 return;
17127
17128         for_each_intel_crtc(&dev_priv->drm, crtc) {
17129                 struct intel_plane *plane =
17130                         to_intel_plane(crtc->base.primary);
17131                 struct intel_crtc *plane_crtc;
17132                 enum pipe pipe;
17133
17134                 if (!plane->get_hw_state(plane, &pipe))
17135                         continue;
17136
17137                 if (pipe == crtc->pipe)
17138                         continue;
17139
17140                 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17141                               plane->base.base.id, plane->base.name);
17142
17143                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17144                 intel_plane_disable_noatomic(plane_crtc, plane);
17145         }
17146 }
17147
17148 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17149 {
17150         struct drm_device *dev = crtc->base.dev;
17151         struct intel_encoder *encoder;
17152
17153         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17154                 return true;
17155
17156         return false;
17157 }
17158
17159 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17160 {
17161         struct drm_device *dev = encoder->base.dev;
17162         struct intel_connector *connector;
17163
17164         for_each_connector_on_encoder(dev, &encoder->base, connector)
17165                 return connector;
17166
17167         return NULL;
17168 }
17169
17170 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17171                               enum pipe pch_transcoder)
17172 {
17173         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17174                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17175 }
17176
17177 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
17178 {
17179         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
17180         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
17181         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17182
17183         if (INTEL_GEN(dev_priv) >= 9 ||
17184             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17185                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
17186                 u32 val;
17187
17188                 if (transcoder_is_dsi(cpu_transcoder))
17189                         return;
17190
17191                 val = I915_READ(reg);
17192                 val &= ~HSW_FRAME_START_DELAY_MASK;
17193                 val |= HSW_FRAME_START_DELAY(0);
17194                 I915_WRITE(reg, val);
17195         } else {
17196                 i915_reg_t reg = PIPECONF(cpu_transcoder);
17197                 u32 val;
17198
17199                 val = I915_READ(reg);
17200                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
17201                 val |= PIPECONF_FRAME_START_DELAY(0);
17202                 I915_WRITE(reg, val);
17203         }
17204
17205         if (!crtc_state->has_pch_encoder)
17206                 return;
17207
17208         if (HAS_PCH_IBX(dev_priv)) {
17209                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
17210                 u32 val;
17211
17212                 val = I915_READ(reg);
17213                 val &= ~TRANS_FRAME_START_DELAY_MASK;
17214                 val |= TRANS_FRAME_START_DELAY(0);
17215                 I915_WRITE(reg, val);
17216         } else {
17217                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
17218                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
17219                 u32 val;
17220
17221                 val = I915_READ(reg);
17222                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
17223                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
17224                 I915_WRITE(reg, val);
17225         }
17226 }
17227
17228 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17229                                 struct drm_modeset_acquire_ctx *ctx)
17230 {
17231         struct drm_device *dev = crtc->base.dev;
17232         struct drm_i915_private *dev_priv = to_i915(dev);
17233         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17234
17235         if (crtc_state->hw.active) {
17236                 struct intel_plane *plane;
17237
17238                 /* Clear any frame start delays used for debugging left by the BIOS */
17239                 intel_sanitize_frame_start_delay(crtc_state);
17240
17241                 /* Disable everything but the primary plane */
17242                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17243                         const struct intel_plane_state *plane_state =
17244                                 to_intel_plane_state(plane->base.state);
17245
17246                         if (plane_state->uapi.visible &&
17247                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17248                                 intel_plane_disable_noatomic(crtc, plane);
17249                 }
17250
17251                 /*
17252                  * Disable any background color set by the BIOS, but enable the
17253                  * gamma and CSC to match how we program our planes.
17254                  */
17255                 if (INTEL_GEN(dev_priv) >= 9)
17256                         I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
17257                                    SKL_BOTTOM_COLOR_GAMMA_ENABLE |
17258                                    SKL_BOTTOM_COLOR_CSC_ENABLE);
17259         }
17260
17261         /* Adjust the state of the output pipe according to whether we
17262          * have active connectors/encoders. */
17263         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
17264                 intel_crtc_disable_noatomic(crtc, ctx);
17265
17266         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
17267                 /*
17268                  * We start out with underrun reporting disabled to avoid races.
17269                  * For correct bookkeeping mark this on active crtcs.
17270                  *
17271                  * Also on gmch platforms we dont have any hardware bits to
17272                  * disable the underrun reporting. Which means we need to start
17273                  * out with underrun reporting disabled also on inactive pipes,
17274                  * since otherwise we'll complain about the garbage we read when
17275                  * e.g. coming up after runtime pm.
17276                  *
17277                  * No protection against concurrent access is required - at
17278                  * worst a fifo underrun happens which also sets this to false.
17279                  */
17280                 crtc->cpu_fifo_underrun_disabled = true;
17281                 /*
17282                  * We track the PCH trancoder underrun reporting state
17283                  * within the crtc. With crtc for pipe A housing the underrun
17284                  * reporting state for PCH transcoder A, crtc for pipe B housing
17285                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
17286                  * and marking underrun reporting as disabled for the non-existing
17287                  * PCH transcoders B and C would prevent enabling the south
17288                  * error interrupt (see cpt_can_enable_serr_int()).
17289                  */
17290                 if (has_pch_trancoder(dev_priv, crtc->pipe))
17291                         crtc->pch_fifo_underrun_disabled = true;
17292         }
17293 }
17294
17295 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
17296 {
17297         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
17298
17299         /*
17300          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
17301          * the hardware when a high res displays plugged in. DPLL P
17302          * divider is zero, and the pipe timings are bonkers. We'll
17303          * try to disable everything in that case.
17304          *
17305          * FIXME would be nice to be able to sanitize this state
17306          * without several WARNs, but for now let's take the easy
17307          * road.
17308          */
17309         return IS_GEN(dev_priv, 6) &&
17310                 crtc_state->hw.active &&
17311                 crtc_state->shared_dpll &&
17312                 crtc_state->port_clock == 0;
17313 }
17314
17315 static void intel_sanitize_encoder(struct intel_encoder *encoder)
17316 {
17317         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
17318         struct intel_connector *connector;
17319         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
17320         struct intel_crtc_state *crtc_state = crtc ?
17321                 to_intel_crtc_state(crtc->base.state) : NULL;
17322
17323         /* We need to check both for a crtc link (meaning that the
17324          * encoder is active and trying to read from a pipe) and the
17325          * pipe itself being active. */
17326         bool has_active_crtc = crtc_state &&
17327                 crtc_state->hw.active;
17328
17329         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
17330                 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
17331                               pipe_name(crtc->pipe));
17332                 has_active_crtc = false;
17333         }
17334
17335         connector = intel_encoder_find_connector(encoder);
17336         if (connector && !has_active_crtc) {
17337                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
17338                               encoder->base.base.id,
17339                               encoder->base.name);
17340
17341                 /* Connector is active, but has no active pipe. This is
17342                  * fallout from our resume register restoring. Disable
17343                  * the encoder manually again. */
17344                 if (crtc_state) {
17345                         struct drm_encoder *best_encoder;
17346
17347                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
17348                                       encoder->base.base.id,
17349                                       encoder->base.name);
17350
17351                         /* avoid oopsing in case the hooks consult best_encoder */
17352                         best_encoder = connector->base.state->best_encoder;
17353                         connector->base.state->best_encoder = &encoder->base;
17354
17355                         if (encoder->disable)
17356                                 encoder->disable(encoder, crtc_state,
17357                                                  connector->base.state);
17358                         if (encoder->post_disable)
17359                                 encoder->post_disable(encoder, crtc_state,
17360                                                       connector->base.state);
17361
17362                         connector->base.state->best_encoder = best_encoder;
17363                 }
17364                 encoder->base.crtc = NULL;
17365
17366                 /* Inconsistent output/port/pipe state happens presumably due to
17367                  * a bug in one of the get_hw_state functions. Or someplace else
17368                  * in our code, like the register restore mess on resume. Clamp
17369                  * things to off as a safer default. */
17370
17371                 connector->base.dpms = DRM_MODE_DPMS_OFF;
17372                 connector->base.encoder = NULL;
17373         }
17374
17375         /* notify opregion of the sanitized encoder state */
17376         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
17377
17378         if (INTEL_GEN(dev_priv) >= 11)
17379                 icl_sanitize_encoder_pll_mapping(encoder);
17380 }
17381
17382 /* FIXME read out full plane state for all planes */
17383 static void readout_plane_state(struct drm_i915_private *dev_priv)
17384 {
17385         struct intel_plane *plane;
17386         struct intel_crtc *crtc;
17387
17388         for_each_intel_plane(&dev_priv->drm, plane) {
17389                 struct intel_plane_state *plane_state =
17390                         to_intel_plane_state(plane->base.state);
17391                 struct intel_crtc_state *crtc_state;
17392                 enum pipe pipe = PIPE_A;
17393                 bool visible;
17394
17395                 visible = plane->get_hw_state(plane, &pipe);
17396
17397                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17398                 crtc_state = to_intel_crtc_state(crtc->base.state);
17399
17400                 intel_set_plane_visible(crtc_state, plane_state, visible);
17401
17402                 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
17403                               plane->base.base.id, plane->base.name,
17404                               enableddisabled(visible), pipe_name(pipe));
17405         }
17406
17407         for_each_intel_crtc(&dev_priv->drm, crtc) {
17408                 struct intel_crtc_state *crtc_state =
17409                         to_intel_crtc_state(crtc->base.state);
17410
17411                 fixup_active_planes(crtc_state);
17412         }
17413 }
17414
17415 static void intel_modeset_readout_hw_state(struct drm_device *dev)
17416 {
17417         struct drm_i915_private *dev_priv = to_i915(dev);
17418         enum pipe pipe;
17419         struct intel_crtc *crtc;
17420         struct intel_encoder *encoder;
17421         struct intel_connector *connector;
17422         struct drm_connector_list_iter conn_iter;
17423         int i;
17424
17425         dev_priv->active_pipes = 0;
17426
17427         for_each_intel_crtc(dev, crtc) {
17428                 struct intel_crtc_state *crtc_state =
17429                         to_intel_crtc_state(crtc->base.state);
17430
17431                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
17432                 intel_crtc_free_hw_state(crtc_state);
17433                 memset(crtc_state, 0, sizeof(*crtc_state));
17434                 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
17435
17436                 crtc_state->hw.active = crtc_state->hw.enable =
17437                         dev_priv->display.get_pipe_config(crtc, crtc_state);
17438
17439                 crtc->base.enabled = crtc_state->hw.enable;
17440                 crtc->active = crtc_state->hw.active;
17441
17442                 if (crtc_state->hw.active)
17443                         dev_priv->active_pipes |= BIT(crtc->pipe);
17444
17445                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17446                               crtc->base.base.id, crtc->base.name,
17447                               enableddisabled(crtc_state->hw.active));
17448         }
17449
17450         readout_plane_state(dev_priv);
17451
17452         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17453                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17454
17455                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
17456                                                         &pll->state.hw_state);
17457
17458                 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
17459                     pll->info->id == DPLL_ID_EHL_DPLL4) {
17460                         pll->wakeref = intel_display_power_get(dev_priv,
17461                                                                POWER_DOMAIN_DPLL_DC_OFF);
17462                 }
17463
17464                 pll->state.crtc_mask = 0;
17465                 for_each_intel_crtc(dev, crtc) {
17466                         struct intel_crtc_state *crtc_state =
17467                                 to_intel_crtc_state(crtc->base.state);
17468
17469                         if (crtc_state->hw.active &&
17470                             crtc_state->shared_dpll == pll)
17471                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17472                 }
17473                 pll->active_mask = pll->state.crtc_mask;
17474
17475                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17476                               pll->info->name, pll->state.crtc_mask, pll->on);
17477         }
17478
17479         for_each_intel_encoder(dev, encoder) {
17480                 pipe = 0;
17481
17482                 if (encoder->get_hw_state(encoder, &pipe)) {
17483                         struct intel_crtc_state *crtc_state;
17484
17485                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17486                         crtc_state = to_intel_crtc_state(crtc->base.state);
17487
17488                         encoder->base.crtc = &crtc->base;
17489                         encoder->get_config(encoder, crtc_state);
17490                 } else {
17491                         encoder->base.crtc = NULL;
17492                 }
17493
17494                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17495                               encoder->base.base.id, encoder->base.name,
17496                               enableddisabled(encoder->base.crtc),
17497                               pipe_name(pipe));
17498         }
17499
17500         drm_connector_list_iter_begin(dev, &conn_iter);
17501         for_each_intel_connector_iter(connector, &conn_iter) {
17502                 if (connector->get_hw_state(connector)) {
17503                         struct intel_crtc_state *crtc_state;
17504                         struct intel_crtc *crtc;
17505
17506                         connector->base.dpms = DRM_MODE_DPMS_ON;
17507
17508                         encoder = connector->encoder;
17509                         connector->base.encoder = &encoder->base;
17510
17511                         crtc = to_intel_crtc(encoder->base.crtc);
17512                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
17513
17514                         if (crtc_state && crtc_state->hw.active) {
17515                                 /*
17516                                  * This has to be done during hardware readout
17517                                  * because anything calling .crtc_disable may
17518                                  * rely on the connector_mask being accurate.
17519                                  */
17520                                 crtc_state->uapi.connector_mask |=
17521                                         drm_connector_mask(&connector->base);
17522                                 crtc_state->uapi.encoder_mask |=
17523                                         drm_encoder_mask(&encoder->base);
17524                         }
17525                 } else {
17526                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17527                         connector->base.encoder = NULL;
17528                 }
17529                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17530                               connector->base.base.id, connector->base.name,
17531                               enableddisabled(connector->base.encoder));
17532         }
17533         drm_connector_list_iter_end(&conn_iter);
17534
17535         for_each_intel_crtc(dev, crtc) {
17536                 struct intel_bw_state *bw_state =
17537                         to_intel_bw_state(dev_priv->bw_obj.state);
17538                 struct intel_crtc_state *crtc_state =
17539                         to_intel_crtc_state(crtc->base.state);
17540                 struct intel_plane *plane;
17541                 int min_cdclk = 0;
17542
17543                 if (crtc_state->hw.active) {
17544                         struct drm_display_mode *mode = &crtc_state->hw.mode;
17545
17546                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
17547                                                     crtc_state);
17548
17549                         *mode = crtc_state->hw.adjusted_mode;
17550                         mode->hdisplay = crtc_state->pipe_src_w;
17551                         mode->vdisplay = crtc_state->pipe_src_h;
17552
17553                         /*
17554                          * The initial mode needs to be set in order to keep
17555                          * the atomic core happy. It wants a valid mode if the
17556                          * crtc's enabled, so we do the above call.
17557                          *
17558                          * But we don't set all the derived state fully, hence
17559                          * set a flag to indicate that a full recalculation is
17560                          * needed on the next commit.
17561                          */
17562                         mode->private_flags = I915_MODE_FLAG_INHERITED;
17563
17564                         intel_crtc_compute_pixel_rate(crtc_state);
17565
17566                         intel_crtc_update_active_timings(crtc_state);
17567
17568                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
17569                 }
17570
17571                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
17572                         const struct intel_plane_state *plane_state =
17573                                 to_intel_plane_state(plane->base.state);
17574
17575                         /*
17576                          * FIXME don't have the fb yet, so can't
17577                          * use intel_plane_data_rate() :(
17578                          */
17579                         if (plane_state->uapi.visible)
17580                                 crtc_state->data_rate[plane->id] =
17581                                         4 * crtc_state->pixel_rate;
17582                         /*
17583                          * FIXME don't have the fb yet, so can't
17584                          * use plane->min_cdclk() :(
17585                          */
17586                         if (plane_state->uapi.visible && plane->min_cdclk) {
17587                                 if (crtc_state->double_wide ||
17588                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
17589                                         crtc_state->min_cdclk[plane->id] =
17590                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
17591                                 else
17592                                         crtc_state->min_cdclk[plane->id] =
17593                                                 crtc_state->pixel_rate;
17594                         }
17595                         DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n",
17596                                       plane->base.base.id, plane->base.name,
17597                                       crtc_state->min_cdclk[plane->id]);
17598                 }
17599
17600                 if (crtc_state->hw.active) {
17601                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
17602                         if (WARN_ON(min_cdclk < 0))
17603                                 min_cdclk = 0;
17604                 }
17605
17606                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
17607                 dev_priv->min_voltage_level[crtc->pipe] =
17608                         crtc_state->min_voltage_level;
17609
17610                 intel_bw_crtc_update(bw_state, crtc_state);
17611
17612                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17613         }
17614 }
17615
17616 static void
17617 get_encoder_power_domains(struct drm_i915_private *dev_priv)
17618 {
17619         struct intel_encoder *encoder;
17620
17621         for_each_intel_encoder(&dev_priv->drm, encoder) {
17622                 struct intel_crtc_state *crtc_state;
17623
17624                 if (!encoder->get_power_domains)
17625                         continue;
17626
17627                 /*
17628                  * MST-primary and inactive encoders don't have a crtc state
17629                  * and neither of these require any power domain references.
17630                  */
17631                 if (!encoder->base.crtc)
17632                         continue;
17633
17634                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
17635                 encoder->get_power_domains(encoder, crtc_state);
17636         }
17637 }
17638
17639 static void intel_early_display_was(struct drm_i915_private *dev_priv)
17640 {
17641         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
17642         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
17643                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
17644                            DARBF_GATING_DIS);
17645
17646         if (IS_HASWELL(dev_priv)) {
17647                 /*
17648                  * WaRsPkgCStateDisplayPMReq:hsw
17649                  * System hang if this isn't done before disabling all planes!
17650                  */
17651                 I915_WRITE(CHICKEN_PAR1_1,
17652                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
17653         }
17654 }
17655
17656 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
17657                                        enum port port, i915_reg_t hdmi_reg)
17658 {
17659         u32 val = I915_READ(hdmi_reg);
17660
17661         if (val & SDVO_ENABLE ||
17662             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
17663                 return;
17664
17665         DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
17666                       port_name(port));
17667
17668         val &= ~SDVO_PIPE_SEL_MASK;
17669         val |= SDVO_PIPE_SEL(PIPE_A);
17670
17671         I915_WRITE(hdmi_reg, val);
17672 }
17673
17674 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
17675                                      enum port port, i915_reg_t dp_reg)
17676 {
17677         u32 val = I915_READ(dp_reg);
17678
17679         if (val & DP_PORT_EN ||
17680             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
17681                 return;
17682
17683         DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
17684                       port_name(port));
17685
17686         val &= ~DP_PIPE_SEL_MASK;
17687         val |= DP_PIPE_SEL(PIPE_A);
17688
17689         I915_WRITE(dp_reg, val);
17690 }
17691
17692 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
17693 {
17694         /*
17695          * The BIOS may select transcoder B on some of the PCH
17696          * ports even it doesn't enable the port. This would trip
17697          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
17698          * Sanitize the transcoder select bits to prevent that. We
17699          * assume that the BIOS never actually enabled the port,
17700          * because if it did we'd actually have to toggle the port
17701          * on and back off to make the transcoder A select stick
17702          * (see. intel_dp_link_down(), intel_disable_hdmi(),
17703          * intel_disable_sdvo()).
17704          */
17705         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
17706         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
17707         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
17708
17709         /* PCH SDVOB multiplex with HDMIB */
17710         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
17711         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
17712         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
17713 }
17714
17715 /* Scan out the current hw modeset state,
17716  * and sanitizes it to the current state
17717  */
17718 static void
17719 intel_modeset_setup_hw_state(struct drm_device *dev,
17720                              struct drm_modeset_acquire_ctx *ctx)
17721 {
17722         struct drm_i915_private *dev_priv = to_i915(dev);
17723         struct intel_encoder *encoder;
17724         struct intel_crtc *crtc;
17725         intel_wakeref_t wakeref;
17726         int i;
17727
17728         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17729
17730         intel_early_display_was(dev_priv);
17731         intel_modeset_readout_hw_state(dev);
17732
17733         /* HW state is read out, now we need to sanitize this mess. */
17734
17735         /* Sanitize the TypeC port mode upfront, encoders depend on this */
17736         for_each_intel_encoder(dev, encoder) {
17737                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17738
17739                 /* We need to sanitize only the MST primary port. */
17740                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17741                     intel_phy_is_tc(dev_priv, phy))
17742                         intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17743         }
17744
17745         get_encoder_power_domains(dev_priv);
17746
17747         if (HAS_PCH_IBX(dev_priv))
17748                 ibx_sanitize_pch_ports(dev_priv);
17749
17750         /*
17751          * intel_sanitize_plane_mapping() may need to do vblank
17752          * waits, so we need vblank interrupts restored beforehand.
17753          */
17754         for_each_intel_crtc(&dev_priv->drm, crtc) {
17755                 struct intel_crtc_state *crtc_state =
17756                         to_intel_crtc_state(crtc->base.state);
17757
17758                 drm_crtc_vblank_reset(&crtc->base);
17759
17760                 if (crtc_state->hw.active)
17761                         intel_crtc_vblank_on(crtc_state);
17762         }
17763
17764         intel_sanitize_plane_mapping(dev_priv);
17765
17766         for_each_intel_encoder(dev, encoder)
17767                 intel_sanitize_encoder(encoder);
17768
17769         for_each_intel_crtc(&dev_priv->drm, crtc) {
17770                 struct intel_crtc_state *crtc_state =
17771                         crtc_state = to_intel_crtc_state(crtc->base.state);
17772
17773                 intel_sanitize_crtc(crtc, ctx);
17774                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17775         }
17776
17777         intel_modeset_update_connector_atomic_state(dev);
17778
17779         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17780                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17781
17782                 if (!pll->on || pll->active_mask)
17783                         continue;
17784
17785                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17786                               pll->info->name);
17787
17788                 pll->info->funcs->disable(dev_priv, pll);
17789                 pll->on = false;
17790         }
17791
17792         if (IS_G4X(dev_priv)) {
17793                 g4x_wm_get_hw_state(dev_priv);
17794                 g4x_wm_sanitize(dev_priv);
17795         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17796                 vlv_wm_get_hw_state(dev_priv);
17797                 vlv_wm_sanitize(dev_priv);
17798         } else if (INTEL_GEN(dev_priv) >= 9) {
17799                 skl_wm_get_hw_state(dev_priv);
17800         } else if (HAS_PCH_SPLIT(dev_priv)) {
17801                 ilk_wm_get_hw_state(dev_priv);
17802         }
17803
17804         for_each_intel_crtc(dev, crtc) {
17805                 struct intel_crtc_state *crtc_state =
17806                         to_intel_crtc_state(crtc->base.state);
17807                 u64 put_domains;
17808
17809                 put_domains = modeset_get_crtc_power_domains(crtc_state);
17810                 if (WARN_ON(put_domains))
17811                         modeset_put_power_domains(dev_priv, put_domains);
17812         }
17813
17814         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17815
17816         intel_fbc_init_pipe_state(dev_priv);
17817 }
17818
17819 void intel_display_resume(struct drm_device *dev)
17820 {
17821         struct drm_i915_private *dev_priv = to_i915(dev);
17822         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17823         struct drm_modeset_acquire_ctx ctx;
17824         int ret;
17825
17826         dev_priv->modeset_restore_state = NULL;
17827         if (state)
17828                 state->acquire_ctx = &ctx;
17829
17830         drm_modeset_acquire_init(&ctx, 0);
17831
17832         while (1) {
17833                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17834                 if (ret != -EDEADLK)
17835                         break;
17836
17837                 drm_modeset_backoff(&ctx);
17838         }
17839
17840         if (!ret)
17841                 ret = __intel_display_resume(dev, state, &ctx);
17842
17843         intel_enable_ipc(dev_priv);
17844         drm_modeset_drop_locks(&ctx);
17845         drm_modeset_acquire_fini(&ctx);
17846
17847         if (ret)
17848                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17849         if (state)
17850                 drm_atomic_state_put(state);
17851 }
17852
17853 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
17854 {
17855         struct intel_connector *connector;
17856         struct drm_connector_list_iter conn_iter;
17857
17858         /* Kill all the work that may have been queued by hpd. */
17859         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
17860         for_each_intel_connector_iter(connector, &conn_iter) {
17861                 if (connector->modeset_retry_work.func)
17862                         cancel_work_sync(&connector->modeset_retry_work);
17863                 if (connector->hdcp.shim) {
17864                         cancel_delayed_work_sync(&connector->hdcp.check_work);
17865                         cancel_work_sync(&connector->hdcp.prop_work);
17866                 }
17867         }
17868         drm_connector_list_iter_end(&conn_iter);
17869 }
17870
17871 void intel_modeset_driver_remove(struct drm_i915_private *i915)
17872 {
17873         flush_workqueue(i915->flip_wq);
17874         flush_workqueue(i915->modeset_wq);
17875
17876         flush_work(&i915->atomic_helper.free_work);
17877         WARN_ON(!llist_empty(&i915->atomic_helper.free_list));
17878
17879         /*
17880          * Interrupts and polling as the first thing to avoid creating havoc.
17881          * Too much stuff here (turning of connectors, ...) would
17882          * experience fancy races otherwise.
17883          */
17884         intel_irq_uninstall(i915);
17885
17886         /*
17887          * Due to the hpd irq storm handling the hotplug work can re-arm the
17888          * poll handlers. Hence disable polling after hpd handling is shut down.
17889          */
17890         intel_hpd_poll_fini(i915);
17891
17892         /*
17893          * MST topology needs to be suspended so we don't have any calls to
17894          * fbdev after it's finalized. MST will be destroyed later as part of
17895          * drm_mode_config_cleanup()
17896          */
17897         intel_dp_mst_suspend(i915);
17898
17899         /* poll work can call into fbdev, hence clean that up afterwards */
17900         intel_fbdev_fini(i915);
17901
17902         intel_unregister_dsm_handler();
17903
17904         intel_fbc_global_disable(i915);
17905
17906         /* flush any delayed tasks or pending work */
17907         flush_scheduled_work();
17908
17909         intel_hdcp_component_fini(i915);
17910
17911         drm_mode_config_cleanup(&i915->drm);
17912
17913         intel_overlay_cleanup(i915);
17914
17915         intel_gmbus_teardown(i915);
17916
17917         destroy_workqueue(i915->flip_wq);
17918         destroy_workqueue(i915->modeset_wq);
17919
17920         intel_fbc_cleanup_cfb(i915);
17921 }
17922
17923 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17924
17925 struct intel_display_error_state {
17926
17927         u32 power_well_driver;
17928
17929         struct intel_cursor_error_state {
17930                 u32 control;
17931                 u32 position;
17932                 u32 base;
17933                 u32 size;
17934         } cursor[I915_MAX_PIPES];
17935
17936         struct intel_pipe_error_state {
17937                 bool power_domain_on;
17938                 u32 source;
17939                 u32 stat;
17940         } pipe[I915_MAX_PIPES];
17941
17942         struct intel_plane_error_state {
17943                 u32 control;
17944                 u32 stride;
17945                 u32 size;
17946                 u32 pos;
17947                 u32 addr;
17948                 u32 surface;
17949                 u32 tile_offset;
17950         } plane[I915_MAX_PIPES];
17951
17952         struct intel_transcoder_error_state {
17953                 bool available;
17954                 bool power_domain_on;
17955                 enum transcoder cpu_transcoder;
17956
17957                 u32 conf;
17958
17959                 u32 htotal;
17960                 u32 hblank;
17961                 u32 hsync;
17962                 u32 vtotal;
17963                 u32 vblank;
17964                 u32 vsync;
17965         } transcoder[5];
17966 };
17967
17968 struct intel_display_error_state *
17969 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17970 {
17971         struct intel_display_error_state *error;
17972         int transcoders[] = {
17973                 TRANSCODER_A,
17974                 TRANSCODER_B,
17975                 TRANSCODER_C,
17976                 TRANSCODER_D,
17977                 TRANSCODER_EDP,
17978         };
17979         int i;
17980
17981         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
17982
17983         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
17984                 return NULL;
17985
17986         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17987         if (error == NULL)
17988                 return NULL;
17989
17990         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17991                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
17992
17993         for_each_pipe(dev_priv, i) {
17994                 error->pipe[i].power_domain_on =
17995                         __intel_display_power_is_enabled(dev_priv,
17996                                                          POWER_DOMAIN_PIPE(i));
17997                 if (!error->pipe[i].power_domain_on)
17998                         continue;
17999
18000                 error->cursor[i].control = I915_READ(CURCNTR(i));
18001                 error->cursor[i].position = I915_READ(CURPOS(i));
18002                 error->cursor[i].base = I915_READ(CURBASE(i));
18003
18004                 error->plane[i].control = I915_READ(DSPCNTR(i));
18005                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
18006                 if (INTEL_GEN(dev_priv) <= 3) {
18007                         error->plane[i].size = I915_READ(DSPSIZE(i));
18008                         error->plane[i].pos = I915_READ(DSPPOS(i));
18009                 }
18010                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18011                         error->plane[i].addr = I915_READ(DSPADDR(i));
18012                 if (INTEL_GEN(dev_priv) >= 4) {
18013                         error->plane[i].surface = I915_READ(DSPSURF(i));
18014                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
18015                 }
18016
18017                 error->pipe[i].source = I915_READ(PIPESRC(i));
18018
18019                 if (HAS_GMCH(dev_priv))
18020                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
18021         }
18022
18023         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18024                 enum transcoder cpu_transcoder = transcoders[i];
18025
18026                 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
18027                         continue;
18028
18029                 error->transcoder[i].available = true;
18030                 error->transcoder[i].power_domain_on =
18031                         __intel_display_power_is_enabled(dev_priv,
18032                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18033                 if (!error->transcoder[i].power_domain_on)
18034                         continue;
18035
18036                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18037
18038                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
18039                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
18040                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
18041                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
18042                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
18043                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
18044                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
18045         }
18046
18047         return error;
18048 }
18049
18050 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18051
18052 void
18053 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18054                                 struct intel_display_error_state *error)
18055 {
18056         struct drm_i915_private *dev_priv = m->i915;
18057         int i;
18058
18059         if (!error)
18060                 return;
18061
18062         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18063         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18064                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18065                            error->power_well_driver);
18066         for_each_pipe(dev_priv, i) {
18067                 err_printf(m, "Pipe [%d]:\n", i);
18068                 err_printf(m, "  Power: %s\n",
18069                            onoff(error->pipe[i].power_domain_on));
18070                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
18071                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
18072
18073                 err_printf(m, "Plane [%d]:\n", i);
18074                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
18075                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
18076                 if (INTEL_GEN(dev_priv) <= 3) {
18077                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
18078                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
18079                 }
18080                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18081                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
18082                 if (INTEL_GEN(dev_priv) >= 4) {
18083                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
18084                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
18085                 }
18086
18087                 err_printf(m, "Cursor [%d]:\n", i);
18088                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
18089                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
18090                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
18091         }
18092
18093         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18094                 if (!error->transcoder[i].available)
18095                         continue;
18096
18097                 err_printf(m, "CPU transcoder: %s\n",
18098                            transcoder_name(error->transcoder[i].cpu_transcoder));
18099                 err_printf(m, "  Power: %s\n",
18100                            onoff(error->transcoder[i].power_domain_on));
18101                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
18102                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
18103                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
18104                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
18105                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
18106                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
18107                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
18108         }
18109 }
18110
18111 #endif