2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_atomic_uapi.h>
38 #include <drm/drm_dp_helper.h>
39 #include <drm/drm_edid.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_plane_helper.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_rect.h>
44 #include <drm/i915_drm.h>
46 #include "display/intel_crt.h"
47 #include "display/intel_ddi.h"
48 #include "display/intel_dp.h"
49 #include "display/intel_dsi.h"
50 #include "display/intel_dvo.h"
51 #include "display/intel_gmbus.h"
52 #include "display/intel_hdmi.h"
53 #include "display/intel_lvds.h"
54 #include "display/intel_sdvo.h"
55 #include "display/intel_tv.h"
56 #include "display/intel_vdsc.h"
58 #include "gt/intel_rps.h"
61 #include "i915_trace.h"
62 #include "intel_acpi.h"
63 #include "intel_atomic.h"
64 #include "intel_atomic_plane.h"
66 #include "intel_cdclk.h"
67 #include "intel_color.h"
68 #include "intel_display_types.h"
69 #include "intel_dp_link_training.h"
70 #include "intel_fbc.h"
71 #include "intel_fbdev.h"
72 #include "intel_fifo_underrun.h"
73 #include "intel_frontbuffer.h"
74 #include "intel_hdcp.h"
75 #include "intel_hotplug.h"
76 #include "intel_overlay.h"
77 #include "intel_pipe_crc.h"
79 #include "intel_psr.h"
80 #include "intel_quirks.h"
81 #include "intel_sideband.h"
82 #include "intel_sprite.h"
84 #include "intel_vga.h"
86 /* Primary plane formats for gen <= 3 */
87 static const u32 i8xx_primary_formats[] = {
94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
95 static const u32 ivb_primary_formats[] = {
100 DRM_FORMAT_XRGB2101010,
101 DRM_FORMAT_XBGR2101010,
104 /* Primary plane formats for gen >= 4, except ivb */
105 static const u32 i965_primary_formats[] = {
110 DRM_FORMAT_XRGB2101010,
111 DRM_FORMAT_XBGR2101010,
112 DRM_FORMAT_XBGR16161616F,
115 /* Primary plane formats for vlv/chv */
116 static const u32 vlv_primary_formats[] = {
123 DRM_FORMAT_XRGB2101010,
124 DRM_FORMAT_XBGR2101010,
125 DRM_FORMAT_ARGB2101010,
126 DRM_FORMAT_ABGR2101010,
127 DRM_FORMAT_XBGR16161616F,
130 static const u64 i9xx_format_modifiers[] = {
131 I915_FORMAT_MOD_X_TILED,
132 DRM_FORMAT_MOD_LINEAR,
133 DRM_FORMAT_MOD_INVALID
137 static const u32 intel_cursor_formats[] = {
141 static const u64 cursor_format_modifiers[] = {
142 DRM_FORMAT_MOD_LINEAR,
143 DRM_FORMAT_MOD_INVALID
146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
147 struct intel_crtc_state *pipe_config);
148 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
149 struct intel_crtc_state *pipe_config);
151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
152 struct drm_i915_gem_object *obj,
153 struct drm_mode_fb_cmd2 *mode_cmd);
154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
157 const struct intel_link_m_n *m_n,
158 const struct intel_link_m_n *m2_n2);
159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
160 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
161 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
163 static void vlv_prepare_pll(struct intel_crtc *crtc,
164 const struct intel_crtc_state *pipe_config);
165 static void chv_prepare_pll(struct intel_crtc *crtc,
166 const struct intel_crtc_state *pipe_config);
167 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
168 struct intel_crtc_state *crtc_state);
169 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
170 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
171 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
173 struct drm_modeset_acquire_ctx *ctx);
174 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
179 } dot, vco, n, m, m1, m2, p, p1;
183 int p2_slow, p2_fast;
187 /* returns HPLL frequency in kHz */
188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
190 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
192 /* Obtain SKU information */
193 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
194 CCK_FUSE_HPLL_FREQ_MASK;
196 return vco_freq[hpll_freq] * 1000;
199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
200 const char *name, u32 reg, int ref_freq)
205 val = vlv_cck_read(dev_priv, reg);
206 divider = val & CCK_FREQUENCY_VALUES;
208 WARN((val & CCK_FREQUENCY_STATUS) !=
209 (divider << CCK_FREQUENCY_STATUS_SHIFT),
210 "%s change in progress\n", name);
212 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
216 const char *name, u32 reg)
220 vlv_cck_get(dev_priv);
222 if (dev_priv->hpll_freq == 0)
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
227 vlv_cck_put(dev_priv);
232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
234 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL);
240 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
243 static inline u32 /* units of 100MHz */
244 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
245 const struct intel_crtc_state *pipe_config)
247 if (HAS_DDI(dev_priv))
248 return pipe_config->port_clock; /* SPLL */
250 return dev_priv->fdi_pll_freq;
253 static const struct intel_limit intel_limits_i8xx_dac = {
254 .dot = { .min = 25000, .max = 350000 },
255 .vco = { .min = 908000, .max = 1512000 },
256 .n = { .min = 2, .max = 16 },
257 .m = { .min = 96, .max = 140 },
258 .m1 = { .min = 18, .max = 26 },
259 .m2 = { .min = 6, .max = 16 },
260 .p = { .min = 4, .max = 128 },
261 .p1 = { .min = 2, .max = 33 },
262 .p2 = { .dot_limit = 165000,
263 .p2_slow = 4, .p2_fast = 2 },
266 static const struct intel_limit intel_limits_i8xx_dvo = {
267 .dot = { .min = 25000, .max = 350000 },
268 .vco = { .min = 908000, .max = 1512000 },
269 .n = { .min = 2, .max = 16 },
270 .m = { .min = 96, .max = 140 },
271 .m1 = { .min = 18, .max = 26 },
272 .m2 = { .min = 6, .max = 16 },
273 .p = { .min = 4, .max = 128 },
274 .p1 = { .min = 2, .max = 33 },
275 .p2 = { .dot_limit = 165000,
276 .p2_slow = 4, .p2_fast = 4 },
279 static const struct intel_limit intel_limits_i8xx_lvds = {
280 .dot = { .min = 25000, .max = 350000 },
281 .vco = { .min = 908000, .max = 1512000 },
282 .n = { .min = 2, .max = 16 },
283 .m = { .min = 96, .max = 140 },
284 .m1 = { .min = 18, .max = 26 },
285 .m2 = { .min = 6, .max = 16 },
286 .p = { .min = 4, .max = 128 },
287 .p1 = { .min = 1, .max = 6 },
288 .p2 = { .dot_limit = 165000,
289 .p2_slow = 14, .p2_fast = 7 },
292 static const struct intel_limit intel_limits_i9xx_sdvo = {
293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1400000, .max = 2800000 },
295 .n = { .min = 1, .max = 6 },
296 .m = { .min = 70, .max = 120 },
297 .m1 = { .min = 8, .max = 18 },
298 .m2 = { .min = 3, .max = 7 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 200000,
302 .p2_slow = 10, .p2_fast = 5 },
305 static const struct intel_limit intel_limits_i9xx_lvds = {
306 .dot = { .min = 20000, .max = 400000 },
307 .vco = { .min = 1400000, .max = 2800000 },
308 .n = { .min = 1, .max = 6 },
309 .m = { .min = 70, .max = 120 },
310 .m1 = { .min = 8, .max = 18 },
311 .m2 = { .min = 3, .max = 7 },
312 .p = { .min = 7, .max = 98 },
313 .p1 = { .min = 1, .max = 8 },
314 .p2 = { .dot_limit = 112000,
315 .p2_slow = 14, .p2_fast = 7 },
319 static const struct intel_limit intel_limits_g4x_sdvo = {
320 .dot = { .min = 25000, .max = 270000 },
321 .vco = { .min = 1750000, .max = 3500000},
322 .n = { .min = 1, .max = 4 },
323 .m = { .min = 104, .max = 138 },
324 .m1 = { .min = 17, .max = 23 },
325 .m2 = { .min = 5, .max = 11 },
326 .p = { .min = 10, .max = 30 },
327 .p1 = { .min = 1, .max = 3},
328 .p2 = { .dot_limit = 270000,
334 static const struct intel_limit intel_limits_g4x_hdmi = {
335 .dot = { .min = 22000, .max = 400000 },
336 .vco = { .min = 1750000, .max = 3500000},
337 .n = { .min = 1, .max = 4 },
338 .m = { .min = 104, .max = 138 },
339 .m1 = { .min = 16, .max = 23 },
340 .m2 = { .min = 5, .max = 11 },
341 .p = { .min = 5, .max = 80 },
342 .p1 = { .min = 1, .max = 8},
343 .p2 = { .dot_limit = 165000,
344 .p2_slow = 10, .p2_fast = 5 },
347 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
348 .dot = { .min = 20000, .max = 115000 },
349 .vco = { .min = 1750000, .max = 3500000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 104, .max = 138 },
352 .m1 = { .min = 17, .max = 23 },
353 .m2 = { .min = 5, .max = 11 },
354 .p = { .min = 28, .max = 112 },
355 .p1 = { .min = 2, .max = 8 },
356 .p2 = { .dot_limit = 0,
357 .p2_slow = 14, .p2_fast = 14
361 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
362 .dot = { .min = 80000, .max = 224000 },
363 .vco = { .min = 1750000, .max = 3500000 },
364 .n = { .min = 1, .max = 3 },
365 .m = { .min = 104, .max = 138 },
366 .m1 = { .min = 17, .max = 23 },
367 .m2 = { .min = 5, .max = 11 },
368 .p = { .min = 14, .max = 42 },
369 .p1 = { .min = 2, .max = 6 },
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 7, .p2_fast = 7
375 static const struct intel_limit intel_limits_pineview_sdvo = {
376 .dot = { .min = 20000, .max = 400000},
377 .vco = { .min = 1700000, .max = 3500000 },
378 /* Pineview's Ncounter is a ring counter */
379 .n = { .min = 3, .max = 6 },
380 .m = { .min = 2, .max = 256 },
381 /* Pineview only has one combined m divider, which we treat as m2. */
382 .m1 = { .min = 0, .max = 0 },
383 .m2 = { .min = 0, .max = 254 },
384 .p = { .min = 5, .max = 80 },
385 .p1 = { .min = 1, .max = 8 },
386 .p2 = { .dot_limit = 200000,
387 .p2_slow = 10, .p2_fast = 5 },
390 static const struct intel_limit intel_limits_pineview_lvds = {
391 .dot = { .min = 20000, .max = 400000 },
392 .vco = { .min = 1700000, .max = 3500000 },
393 .n = { .min = 3, .max = 6 },
394 .m = { .min = 2, .max = 256 },
395 .m1 = { .min = 0, .max = 0 },
396 .m2 = { .min = 0, .max = 254 },
397 .p = { .min = 7, .max = 112 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 112000,
400 .p2_slow = 14, .p2_fast = 14 },
403 /* Ironlake / Sandybridge
405 * We calculate clock using (register_value + 2) for N/M1/M2, so here
406 * the range value for them is (actual_value - 2).
408 static const struct intel_limit intel_limits_ironlake_dac = {
409 .dot = { .min = 25000, .max = 350000 },
410 .vco = { .min = 1760000, .max = 3510000 },
411 .n = { .min = 1, .max = 5 },
412 .m = { .min = 79, .max = 127 },
413 .m1 = { .min = 12, .max = 22 },
414 .m2 = { .min = 5, .max = 9 },
415 .p = { .min = 5, .max = 80 },
416 .p1 = { .min = 1, .max = 8 },
417 .p2 = { .dot_limit = 225000,
418 .p2_slow = 10, .p2_fast = 5 },
421 static const struct intel_limit intel_limits_ironlake_single_lvds = {
422 .dot = { .min = 25000, .max = 350000 },
423 .vco = { .min = 1760000, .max = 3510000 },
424 .n = { .min = 1, .max = 3 },
425 .m = { .min = 79, .max = 118 },
426 .m1 = { .min = 12, .max = 22 },
427 .m2 = { .min = 5, .max = 9 },
428 .p = { .min = 28, .max = 112 },
429 .p1 = { .min = 2, .max = 8 },
430 .p2 = { .dot_limit = 225000,
431 .p2_slow = 14, .p2_fast = 14 },
434 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
435 .dot = { .min = 25000, .max = 350000 },
436 .vco = { .min = 1760000, .max = 3510000 },
437 .n = { .min = 1, .max = 3 },
438 .m = { .min = 79, .max = 127 },
439 .m1 = { .min = 12, .max = 22 },
440 .m2 = { .min = 5, .max = 9 },
441 .p = { .min = 14, .max = 56 },
442 .p1 = { .min = 2, .max = 8 },
443 .p2 = { .dot_limit = 225000,
444 .p2_slow = 7, .p2_fast = 7 },
447 /* LVDS 100mhz refclk limits. */
448 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
449 .dot = { .min = 25000, .max = 350000 },
450 .vco = { .min = 1760000, .max = 3510000 },
451 .n = { .min = 1, .max = 2 },
452 .m = { .min = 79, .max = 126 },
453 .m1 = { .min = 12, .max = 22 },
454 .m2 = { .min = 5, .max = 9 },
455 .p = { .min = 28, .max = 112 },
456 .p1 = { .min = 2, .max = 8 },
457 .p2 = { .dot_limit = 225000,
458 .p2_slow = 14, .p2_fast = 14 },
461 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
462 .dot = { .min = 25000, .max = 350000 },
463 .vco = { .min = 1760000, .max = 3510000 },
464 .n = { .min = 1, .max = 3 },
465 .m = { .min = 79, .max = 126 },
466 .m1 = { .min = 12, .max = 22 },
467 .m2 = { .min = 5, .max = 9 },
468 .p = { .min = 14, .max = 42 },
469 .p1 = { .min = 2, .max = 6 },
470 .p2 = { .dot_limit = 225000,
471 .p2_slow = 7, .p2_fast = 7 },
474 static const struct intel_limit intel_limits_vlv = {
476 * These are the data rate limits (measured in fast clocks)
477 * since those are the strictest limits we have. The fast
478 * clock and actual rate limits are more relaxed, so checking
479 * them would make no difference.
481 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
482 .vco = { .min = 4000000, .max = 6000000 },
483 .n = { .min = 1, .max = 7 },
484 .m1 = { .min = 2, .max = 3 },
485 .m2 = { .min = 11, .max = 156 },
486 .p1 = { .min = 2, .max = 3 },
487 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
490 static const struct intel_limit intel_limits_chv = {
492 * These are the data rate limits (measured in fast clocks)
493 * since those are the strictest limits we have. The fast
494 * clock and actual rate limits are more relaxed, so checking
495 * them would make no difference.
497 .dot = { .min = 25000 * 5, .max = 540000 * 5},
498 .vco = { .min = 4800000, .max = 6480000 },
499 .n = { .min = 1, .max = 1 },
500 .m1 = { .min = 2, .max = 2 },
501 .m2 = { .min = 24 << 22, .max = 175 << 22 },
502 .p1 = { .min = 2, .max = 4 },
503 .p2 = { .p2_slow = 1, .p2_fast = 14 },
506 static const struct intel_limit intel_limits_bxt = {
507 /* FIXME: find real dot limits */
508 .dot = { .min = 0, .max = INT_MAX },
509 .vco = { .min = 4800000, .max = 6700000 },
510 .n = { .min = 1, .max = 1 },
511 .m1 = { .min = 2, .max = 2 },
512 /* FIXME: find real m2 limits */
513 .m2 = { .min = 2 << 22, .max = 255 << 22 },
514 .p1 = { .min = 2, .max = 4 },
515 .p2 = { .p2_slow = 1, .p2_fast = 20 },
518 /* WA Display #0827: Gen9:all */
520 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
523 I915_WRITE(CLKGATE_DIS_PSL(pipe),
524 I915_READ(CLKGATE_DIS_PSL(pipe)) |
525 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
527 I915_WRITE(CLKGATE_DIS_PSL(pipe),
528 I915_READ(CLKGATE_DIS_PSL(pipe)) &
529 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
532 /* Wa_2006604312:icl */
534 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
538 I915_WRITE(CLKGATE_DIS_PSL(pipe),
539 I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
541 I915_WRITE(CLKGATE_DIS_PSL(pipe),
542 I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
546 needs_modeset(const struct intel_crtc_state *state)
548 return drm_atomic_crtc_needs_modeset(&state->uapi);
552 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
554 return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
555 crtc_state->sync_mode_slaves_mask);
559 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
561 return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
562 crtc_state->sync_mode_slaves_mask);
566 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
567 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
568 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
569 * The helpers' return value is the rate of the clock that is fed to the
570 * display engine's pipe which can be the above fast dot clock rate or a
571 * divided-down version of it.
573 /* m1 is reserved as 0 in Pineview, n is a ring counter */
574 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
576 clock->m = clock->m2 + 2;
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n == 0 || clock->p == 0))
580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
586 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
588 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
591 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
593 clock->m = i9xx_dpll_compute_m(clock);
594 clock->p = clock->p1 * clock->p2;
595 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
597 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
598 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
605 clock->m = clock->m1 * clock->m2;
606 clock->p = clock->p1 * clock->p2;
607 if (WARN_ON(clock->n == 0 || clock->p == 0))
609 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
610 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
612 return clock->dot / 5;
615 int chv_calc_dpll_params(int refclk, struct dpll *clock)
617 clock->m = clock->m1 * clock->m2;
618 clock->p = clock->p1 * clock->p2;
619 if (WARN_ON(clock->n == 0 || clock->p == 0))
621 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
623 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
625 return clock->dot / 5;
628 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
631 * Returns whether the given set of divisors are valid for a given refclk with
632 * the given connectors.
634 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
635 const struct intel_limit *limit,
636 const struct dpll *clock)
638 if (clock->n < limit->n.min || limit->n.max < clock->n)
639 INTELPllInvalid("n out of range\n");
640 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
641 INTELPllInvalid("p1 out of range\n");
642 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
643 INTELPllInvalid("m2 out of range\n");
644 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
645 INTELPllInvalid("m1 out of range\n");
647 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
648 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
649 if (clock->m1 <= clock->m2)
650 INTELPllInvalid("m1 <= m2\n");
652 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
653 !IS_GEN9_LP(dev_priv)) {
654 if (clock->p < limit->p.min || limit->p.max < clock->p)
655 INTELPllInvalid("p out of range\n");
656 if (clock->m < limit->m.min || limit->m.max < clock->m)
657 INTELPllInvalid("m out of range\n");
660 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
661 INTELPllInvalid("vco out of range\n");
662 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
663 * connector, etc., rather than just a single range.
665 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
666 INTELPllInvalid("dot out of range\n");
672 i9xx_select_p2_div(const struct intel_limit *limit,
673 const struct intel_crtc_state *crtc_state,
676 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
678 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
680 * For LVDS just rely on its current settings for dual-channel.
681 * We haven't figured out how to reliably set up different
682 * single/dual channel state, if we even can.
684 if (intel_is_dual_link_lvds(dev_priv))
685 return limit->p2.p2_fast;
687 return limit->p2.p2_slow;
689 if (target < limit->p2.dot_limit)
690 return limit->p2.p2_slow;
692 return limit->p2.p2_fast;
697 * Returns a set of divisors for the desired target clock with the given
698 * refclk, or FALSE. The returned values represent the clock equation:
699 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
701 * Target and reference clocks are specified in kHz.
703 * If match_clock is provided, then best_clock P divider must match the P
704 * divider from @match_clock used for LVDS downclocking.
707 i9xx_find_best_dpll(const struct intel_limit *limit,
708 struct intel_crtc_state *crtc_state,
709 int target, int refclk, struct dpll *match_clock,
710 struct dpll *best_clock)
712 struct drm_device *dev = crtc_state->uapi.crtc->dev;
716 memset(best_clock, 0, sizeof(*best_clock));
718 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
720 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
722 for (clock.m2 = limit->m2.min;
723 clock.m2 <= limit->m2.max; clock.m2++) {
724 if (clock.m2 >= clock.m1)
726 for (clock.n = limit->n.min;
727 clock.n <= limit->n.max; clock.n++) {
728 for (clock.p1 = limit->p1.min;
729 clock.p1 <= limit->p1.max; clock.p1++) {
732 i9xx_calc_dpll_params(refclk, &clock);
733 if (!intel_PLL_is_valid(to_i915(dev),
738 clock.p != match_clock->p)
741 this_err = abs(clock.dot - target);
742 if (this_err < err) {
751 return (err != target);
755 * Returns a set of divisors for the desired target clock with the given
756 * refclk, or FALSE. The returned values represent the clock equation:
757 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
759 * Target and reference clocks are specified in kHz.
761 * If match_clock is provided, then best_clock P divider must match the P
762 * divider from @match_clock used for LVDS downclocking.
765 pnv_find_best_dpll(const struct intel_limit *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, struct dpll *match_clock,
768 struct dpll *best_clock)
770 struct drm_device *dev = crtc_state->uapi.crtc->dev;
774 memset(best_clock, 0, sizeof(*best_clock));
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 for (clock.n = limit->n.min;
783 clock.n <= limit->n.max; clock.n++) {
784 for (clock.p1 = limit->p1.min;
785 clock.p1 <= limit->p1.max; clock.p1++) {
788 pnv_calc_dpll_params(refclk, &clock);
789 if (!intel_PLL_is_valid(to_i915(dev),
794 clock.p != match_clock->p)
797 this_err = abs(clock.dot - target);
798 if (this_err < err) {
807 return (err != target);
811 * Returns a set of divisors for the desired target clock with the given
812 * refclk, or FALSE. The returned values represent the clock equation:
813 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
815 * Target and reference clocks are specified in kHz.
817 * If match_clock is provided, then best_clock P divider must match the P
818 * divider from @match_clock used for LVDS downclocking.
821 g4x_find_best_dpll(const struct intel_limit *limit,
822 struct intel_crtc_state *crtc_state,
823 int target, int refclk, struct dpll *match_clock,
824 struct dpll *best_clock)
826 struct drm_device *dev = crtc_state->uapi.crtc->dev;
830 /* approximately equals target * 0.00585 */
831 int err_most = (target >> 8) + (target >> 9);
833 memset(best_clock, 0, sizeof(*best_clock));
835 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
837 max_n = limit->n.max;
838 /* based on hardware requirement, prefer smaller n to precision */
839 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
840 /* based on hardware requirement, prefere larger m1,m2 */
841 for (clock.m1 = limit->m1.max;
842 clock.m1 >= limit->m1.min; clock.m1--) {
843 for (clock.m2 = limit->m2.max;
844 clock.m2 >= limit->m2.min; clock.m2--) {
845 for (clock.p1 = limit->p1.max;
846 clock.p1 >= limit->p1.min; clock.p1--) {
849 i9xx_calc_dpll_params(refclk, &clock);
850 if (!intel_PLL_is_valid(to_i915(dev),
855 this_err = abs(clock.dot - target);
856 if (this_err < err_most) {
870 * Check if the calculated PLL configuration is more optimal compared to the
871 * best configuration and error found so far. Return the calculated error.
873 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
874 const struct dpll *calculated_clock,
875 const struct dpll *best_clock,
876 unsigned int best_error_ppm,
877 unsigned int *error_ppm)
880 * For CHV ignore the error and consider only the P value.
881 * Prefer a bigger P value based on HW requirements.
883 if (IS_CHERRYVIEW(to_i915(dev))) {
886 return calculated_clock->p > best_clock->p;
889 if (WARN_ON_ONCE(!target_freq))
892 *error_ppm = div_u64(1000000ULL *
893 abs(target_freq - calculated_clock->dot),
896 * Prefer a better P value over a better (smaller) error if the error
897 * is small. Ensure this preference for future configurations too by
898 * setting the error to 0.
900 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
906 return *error_ppm + 10 < best_error_ppm;
910 * Returns a set of divisors for the desired target clock with the given
911 * refclk, or FALSE. The returned values represent the clock equation:
912 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
915 vlv_find_best_dpll(const struct intel_limit *limit,
916 struct intel_crtc_state *crtc_state,
917 int target, int refclk, struct dpll *match_clock,
918 struct dpll *best_clock)
920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
921 struct drm_device *dev = crtc->base.dev;
923 unsigned int bestppm = 1000000;
924 /* min update 19.2 MHz */
925 int max_n = min(limit->n.max, refclk / 19200);
928 target *= 5; /* fast clock */
930 memset(best_clock, 0, sizeof(*best_clock));
932 /* based on hardware requirement, prefer smaller n to precision */
933 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
934 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
935 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
936 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
937 clock.p = clock.p1 * clock.p2;
938 /* based on hardware requirement, prefer bigger m1,m2 values */
939 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
942 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
945 vlv_calc_dpll_params(refclk, &clock);
947 if (!intel_PLL_is_valid(to_i915(dev),
952 if (!vlv_PLL_is_optimal(dev, target,
970 * Returns a set of divisors for the desired target clock with the given
971 * refclk, or FALSE. The returned values represent the clock equation:
972 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
975 chv_find_best_dpll(const struct intel_limit *limit,
976 struct intel_crtc_state *crtc_state,
977 int target, int refclk, struct dpll *match_clock,
978 struct dpll *best_clock)
980 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
981 struct drm_device *dev = crtc->base.dev;
982 unsigned int best_error_ppm;
987 memset(best_clock, 0, sizeof(*best_clock));
988 best_error_ppm = 1000000;
991 * Based on hardware doc, the n always set to 1, and m1 always
992 * set to 2. If requires to support 200Mhz refclk, we need to
993 * revisit this because n may not 1 anymore.
995 clock.n = 1, clock.m1 = 2;
996 target *= 5; /* fast clock */
998 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
999 for (clock.p2 = limit->p2.p2_fast;
1000 clock.p2 >= limit->p2.p2_slow;
1001 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1002 unsigned int error_ppm;
1004 clock.p = clock.p1 * clock.p2;
1006 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1009 if (m2 > INT_MAX/clock.m1)
1014 chv_calc_dpll_params(refclk, &clock);
1016 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1019 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1020 best_error_ppm, &error_ppm))
1023 *best_clock = clock;
1024 best_error_ppm = error_ppm;
1032 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1033 struct dpll *best_clock)
1035 int refclk = 100000;
1036 const struct intel_limit *limit = &intel_limits_bxt;
1038 return chv_find_best_dpll(limit, crtc_state,
1039 crtc_state->port_clock, refclk,
1043 bool intel_crtc_active(struct intel_crtc *crtc)
1045 /* Be paranoid as we can arrive here with only partial
1046 * state retrieved from the hardware during setup.
1048 * We can ditch the adjusted_mode.crtc_clock check as soon
1049 * as Haswell has gained clock readout/fastboot support.
1051 * We can ditch the crtc->primary->state->fb check as soon as we can
1052 * properly reconstruct framebuffers.
1054 * FIXME: The intel_crtc->active here should be switched to
1055 * crtc->state->active once we have proper CRTC states wired up
1058 return crtc->active && crtc->base.primary->state->fb &&
1059 crtc->config->hw.adjusted_mode.crtc_clock;
1062 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1065 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1067 return crtc->config->cpu_transcoder;
1070 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1073 i915_reg_t reg = PIPEDSL(pipe);
1077 if (IS_GEN(dev_priv, 2))
1078 line_mask = DSL_LINEMASK_GEN2;
1080 line_mask = DSL_LINEMASK_GEN3;
1082 line1 = I915_READ(reg) & line_mask;
1084 line2 = I915_READ(reg) & line_mask;
1086 return line1 != line2;
1089 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1091 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092 enum pipe pipe = crtc->pipe;
1094 /* Wait for the display line to settle/start moving */
1095 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1096 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1097 pipe_name(pipe), onoff(state));
1100 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1102 wait_for_pipe_scanline_moving(crtc, false);
1105 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1107 wait_for_pipe_scanline_moving(crtc, true);
1111 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1113 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1114 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1116 if (INTEL_GEN(dev_priv) >= 4) {
1117 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1118 i915_reg_t reg = PIPECONF(cpu_transcoder);
1120 /* Wait for the Pipe State to go off */
1121 if (intel_de_wait_for_clear(dev_priv, reg,
1122 I965_PIPECONF_ACTIVE, 100))
1123 WARN(1, "pipe_off wait timed out\n");
1125 intel_wait_for_pipe_scanline_stopped(crtc);
1129 /* Only for pre-ILK configs */
1130 void assert_pll(struct drm_i915_private *dev_priv,
1131 enum pipe pipe, bool state)
1136 val = I915_READ(DPLL(pipe));
1137 cur_state = !!(val & DPLL_VCO_ENABLE);
1138 I915_STATE_WARN(cur_state != state,
1139 "PLL state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1143 /* XXX: the dsi pll is shared between MIPI DSI ports */
1144 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1149 vlv_cck_get(dev_priv);
1150 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1151 vlv_cck_put(dev_priv);
1153 cur_state = val & DSI_PLL_VCO_EN;
1154 I915_STATE_WARN(cur_state != state,
1155 "DSI PLL state assertion failure (expected %s, current %s)\n",
1156 onoff(state), onoff(cur_state));
1159 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, bool state)
1163 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1166 if (HAS_DDI(dev_priv)) {
1167 /* DDI does not have a specific FDI_TX register */
1168 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1169 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1171 u32 val = I915_READ(FDI_TX_CTL(pipe));
1172 cur_state = !!(val & FDI_TX_ENABLE);
1174 I915_STATE_WARN(cur_state != state,
1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 onoff(state), onoff(cur_state));
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1181 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1187 val = I915_READ(FDI_RX_CTL(pipe));
1188 cur_state = !!(val & FDI_RX_ENABLE);
1189 I915_STATE_WARN(cur_state != state,
1190 "FDI RX state assertion failure (expected %s, current %s)\n",
1191 onoff(state), onoff(cur_state));
1193 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1194 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1196 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201 /* ILK FDI PLL is always enabled */
1202 if (IS_GEN(dev_priv, 5))
1205 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1206 if (HAS_DDI(dev_priv))
1209 val = I915_READ(FDI_TX_CTL(pipe));
1210 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1213 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1219 val = I915_READ(FDI_RX_CTL(pipe));
1220 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1221 I915_STATE_WARN(cur_state != state,
1222 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1223 onoff(state), onoff(cur_state));
1226 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1230 enum pipe panel_pipe = INVALID_PIPE;
1233 if (WARN_ON(HAS_DDI(dev_priv)))
1236 if (HAS_PCH_SPLIT(dev_priv)) {
1239 pp_reg = PP_CONTROL(0);
1240 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1243 case PANEL_PORT_SELECT_LVDS:
1244 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1246 case PANEL_PORT_SELECT_DPA:
1247 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1249 case PANEL_PORT_SELECT_DPC:
1250 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1252 case PANEL_PORT_SELECT_DPD:
1253 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1256 MISSING_CASE(port_sel);
1259 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1260 /* presumably write lock depends on pipe, not port select */
1261 pp_reg = PP_CONTROL(pipe);
1266 pp_reg = PP_CONTROL(0);
1267 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1269 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1270 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1273 val = I915_READ(pp_reg);
1274 if (!(val & PANEL_POWER_ON) ||
1275 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1278 I915_STATE_WARN(panel_pipe == pipe && locked,
1279 "panel assertion failure, pipe %c regs locked\n",
1283 void assert_pipe(struct drm_i915_private *dev_priv,
1284 enum pipe pipe, bool state)
1287 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1289 enum intel_display_power_domain power_domain;
1290 intel_wakeref_t wakeref;
1292 /* we keep both pipes enabled on 830 */
1293 if (IS_I830(dev_priv))
1296 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1297 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1299 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1300 cur_state = !!(val & PIPECONF_ENABLE);
1302 intel_display_power_put(dev_priv, power_domain, wakeref);
1307 I915_STATE_WARN(cur_state != state,
1308 "pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), onoff(state), onoff(cur_state));
1312 static void assert_plane(struct intel_plane *plane, bool state)
1317 cur_state = plane->get_hw_state(plane, &pipe);
1319 I915_STATE_WARN(cur_state != state,
1320 "%s assertion failure (expected %s, current %s)\n",
1321 plane->base.name, onoff(state), onoff(cur_state));
1324 #define assert_plane_enabled(p) assert_plane(p, true)
1325 #define assert_plane_disabled(p) assert_plane(p, false)
1327 static void assert_planes_disabled(struct intel_crtc *crtc)
1329 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1330 struct intel_plane *plane;
1332 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1333 assert_plane_disabled(plane);
1336 static void assert_vblank_disabled(struct drm_crtc *crtc)
1338 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1339 drm_crtc_vblank_put(crtc);
1342 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1348 val = I915_READ(PCH_TRANSCONF(pipe));
1349 enabled = !!(val & TRANS_ENABLE);
1350 I915_STATE_WARN(enabled,
1351 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1355 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe, enum port port,
1359 enum pipe port_pipe;
1362 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1364 I915_STATE_WARN(state && port_pipe == pipe,
1365 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1366 port_name(port), pipe_name(pipe));
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369 "IBX PCH DP %c still using transcoder B\n",
1373 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe, enum port port,
1375 i915_reg_t hdmi_reg)
1377 enum pipe port_pipe;
1380 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1382 I915_STATE_WARN(state && port_pipe == pipe,
1383 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1384 port_name(port), pipe_name(pipe));
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1387 "IBX PCH HDMI %c still using transcoder B\n",
1391 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe port_pipe;
1396 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1397 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1398 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1400 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1402 "PCH VGA enabled on transcoder %c, should be disabled\n",
1405 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1407 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1410 /* PCH SDVOB multiplex with HDMIB */
1411 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1412 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1413 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1416 static void _vlv_enable_pll(struct intel_crtc *crtc,
1417 const struct intel_crtc_state *pipe_config)
1419 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1420 enum pipe pipe = crtc->pipe;
1422 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1423 POSTING_READ(DPLL(pipe));
1426 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1427 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1430 static void vlv_enable_pll(struct intel_crtc *crtc,
1431 const struct intel_crtc_state *pipe_config)
1433 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1434 enum pipe pipe = crtc->pipe;
1436 assert_pipe_disabled(dev_priv, pipe);
1438 /* PLL is protected by panel, make sure we can write it */
1439 assert_panel_unlocked(dev_priv, pipe);
1441 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1442 _vlv_enable_pll(crtc, pipe_config);
1444 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1445 POSTING_READ(DPLL_MD(pipe));
1449 static void _chv_enable_pll(struct intel_crtc *crtc,
1450 const struct intel_crtc_state *pipe_config)
1452 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1453 enum pipe pipe = crtc->pipe;
1454 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1457 vlv_dpio_get(dev_priv);
1459 /* Enable back the 10bit clock to display controller */
1460 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1461 tmp |= DPIO_DCLKP_EN;
1462 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1464 vlv_dpio_put(dev_priv);
1467 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1472 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1474 /* Check PLL is locked */
1475 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1476 DRM_ERROR("PLL %d failed to lock\n", pipe);
1479 static void chv_enable_pll(struct intel_crtc *crtc,
1480 const struct intel_crtc_state *pipe_config)
1482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1483 enum pipe pipe = crtc->pipe;
1485 assert_pipe_disabled(dev_priv, pipe);
1487 /* PLL is protected by panel, make sure we can write it */
1488 assert_panel_unlocked(dev_priv, pipe);
1490 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1491 _chv_enable_pll(crtc, pipe_config);
1493 if (pipe != PIPE_A) {
1495 * WaPixelRepeatModeFixForC0:chv
1497 * DPLLCMD is AWOL. Use chicken bits to propagate
1498 * the value from DPLLBMD to either pipe B or C.
1500 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1501 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1502 I915_WRITE(CBR4_VLV, 0);
1503 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1506 * DPLLB VGA mode also seems to cause problems.
1507 * We should always have it disabled.
1509 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1511 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1512 POSTING_READ(DPLL_MD(pipe));
1516 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1518 if (IS_I830(dev_priv))
1521 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1524 static void i9xx_enable_pll(struct intel_crtc *crtc,
1525 const struct intel_crtc_state *crtc_state)
1527 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1528 i915_reg_t reg = DPLL(crtc->pipe);
1529 u32 dpll = crtc_state->dpll_hw_state.dpll;
1532 assert_pipe_disabled(dev_priv, crtc->pipe);
1534 /* PLL is protected by panel, make sure we can write it */
1535 if (i9xx_has_pps(dev_priv))
1536 assert_panel_unlocked(dev_priv, crtc->pipe);
1539 * Apparently we need to have VGA mode enabled prior to changing
1540 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1541 * dividers, even though the register value does change.
1543 I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1544 I915_WRITE(reg, dpll);
1546 /* Wait for the clocks to stabilize. */
1550 if (INTEL_GEN(dev_priv) >= 4) {
1551 I915_WRITE(DPLL_MD(crtc->pipe),
1552 crtc_state->dpll_hw_state.dpll_md);
1554 /* The pixel multiplier can only be updated once the
1555 * DPLL is enabled and the clocks are stable.
1557 * So write it again.
1559 I915_WRITE(reg, dpll);
1562 /* We do this three times for luck */
1563 for (i = 0; i < 3; i++) {
1564 I915_WRITE(reg, dpll);
1566 udelay(150); /* wait for warmup */
1570 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1572 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574 enum pipe pipe = crtc->pipe;
1576 /* Don't disable pipe or pipe PLLs if needed */
1577 if (IS_I830(dev_priv))
1580 /* Make sure the pipe isn't still relying on us */
1581 assert_pipe_disabled(dev_priv, pipe);
1583 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1584 POSTING_READ(DPLL(pipe));
1587 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1591 /* Make sure the pipe isn't still relying on us */
1592 assert_pipe_disabled(dev_priv, pipe);
1594 val = DPLL_INTEGRATED_REF_CLK_VLV |
1595 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1597 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1599 I915_WRITE(DPLL(pipe), val);
1600 POSTING_READ(DPLL(pipe));
1603 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1605 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1608 /* Make sure the pipe isn't still relying on us */
1609 assert_pipe_disabled(dev_priv, pipe);
1611 val = DPLL_SSC_REF_CLK_CHV |
1612 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1614 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1616 I915_WRITE(DPLL(pipe), val);
1617 POSTING_READ(DPLL(pipe));
1619 vlv_dpio_get(dev_priv);
1621 /* Disable 10bit clock to display controller */
1622 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1623 val &= ~DPIO_DCLKP_EN;
1624 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1626 vlv_dpio_put(dev_priv);
1629 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1630 struct intel_digital_port *dport,
1631 unsigned int expected_mask)
1634 i915_reg_t dpll_reg;
1636 switch (dport->base.port) {
1638 port_mask = DPLL_PORTB_READY_MASK;
1642 port_mask = DPLL_PORTC_READY_MASK;
1644 expected_mask <<= 4;
1647 port_mask = DPLL_PORTD_READY_MASK;
1648 dpll_reg = DPIO_PHY_STATUS;
1654 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1655 port_mask, expected_mask, 1000))
1656 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1657 dport->base.base.base.id, dport->base.base.name,
1658 I915_READ(dpll_reg) & port_mask, expected_mask);
1661 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1663 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1665 enum pipe pipe = crtc->pipe;
1667 u32 val, pipeconf_val;
1669 /* Make sure PCH DPLL is enabled */
1670 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1672 /* FDI must be feeding us bits for PCH ports */
1673 assert_fdi_tx_enabled(dev_priv, pipe);
1674 assert_fdi_rx_enabled(dev_priv, pipe);
1676 if (HAS_PCH_CPT(dev_priv)) {
1677 reg = TRANS_CHICKEN2(pipe);
1678 val = I915_READ(reg);
1680 * Workaround: Set the timing override bit
1681 * before enabling the pch transcoder.
1683 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1684 /* Configure frame start delay to match the CPU */
1685 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1686 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1687 I915_WRITE(reg, val);
1690 reg = PCH_TRANSCONF(pipe);
1691 val = I915_READ(reg);
1692 pipeconf_val = I915_READ(PIPECONF(pipe));
1694 if (HAS_PCH_IBX(dev_priv)) {
1695 /* Configure frame start delay to match the CPU */
1696 val &= ~TRANS_FRAME_START_DELAY_MASK;
1697 val |= TRANS_FRAME_START_DELAY(0);
1700 * Make the BPC in transcoder be consistent with
1701 * that in pipeconf reg. For HDMI we must use 8bpc
1702 * here for both 8bpc and 12bpc.
1704 val &= ~PIPECONF_BPC_MASK;
1705 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1706 val |= PIPECONF_8BPC;
1708 val |= pipeconf_val & PIPECONF_BPC_MASK;
1711 val &= ~TRANS_INTERLACE_MASK;
1712 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1713 if (HAS_PCH_IBX(dev_priv) &&
1714 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1715 val |= TRANS_LEGACY_INTERLACED_ILK;
1717 val |= TRANS_INTERLACED;
1719 val |= TRANS_PROGRESSIVE;
1722 I915_WRITE(reg, val | TRANS_ENABLE);
1723 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1724 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1727 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1728 enum transcoder cpu_transcoder)
1730 u32 val, pipeconf_val;
1732 /* FDI must be feeding us bits for PCH ports */
1733 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1734 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1736 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1737 /* Workaround: set timing override bit. */
1738 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1739 /* Configure frame start delay to match the CPU */
1740 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1741 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1742 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1745 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1747 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1748 PIPECONF_INTERLACED_ILK)
1749 val |= TRANS_INTERLACED;
1751 val |= TRANS_PROGRESSIVE;
1753 I915_WRITE(LPT_TRANSCONF, val);
1754 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1755 TRANS_STATE_ENABLE, 100))
1756 DRM_ERROR("Failed to enable PCH transcoder\n");
1759 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1765 /* FDI relies on the transcoder */
1766 assert_fdi_tx_disabled(dev_priv, pipe);
1767 assert_fdi_rx_disabled(dev_priv, pipe);
1769 /* Ports must be off as well */
1770 assert_pch_ports_disabled(dev_priv, pipe);
1772 reg = PCH_TRANSCONF(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_ENABLE;
1775 I915_WRITE(reg, val);
1776 /* wait for PCH transcoder off, transcoder state */
1777 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1778 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1780 if (HAS_PCH_CPT(dev_priv)) {
1781 /* Workaround: Clear the timing override chicken bit again. */
1782 reg = TRANS_CHICKEN2(pipe);
1783 val = I915_READ(reg);
1784 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1785 I915_WRITE(reg, val);
1789 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1793 val = I915_READ(LPT_TRANSCONF);
1794 val &= ~TRANS_ENABLE;
1795 I915_WRITE(LPT_TRANSCONF, val);
1796 /* wait for PCH transcoder off, transcoder state */
1797 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1798 TRANS_STATE_ENABLE, 50))
1799 DRM_ERROR("Failed to disable PCH transcoder\n");
1801 /* Workaround: clear timing override bit. */
1802 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1803 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1804 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1807 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1809 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1811 if (HAS_PCH_LPT(dev_priv))
1817 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1819 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1822 * On i965gm the hardware frame counter reads
1823 * zero when the TV encoder is enabled :(
1825 if (IS_I965GM(dev_priv) &&
1826 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1829 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1830 return 0xffffffff; /* full 32 bit counter */
1831 else if (INTEL_GEN(dev_priv) >= 3)
1832 return 0xffffff; /* only 24 bits of frame count */
1834 return 0; /* Gen2 doesn't have a hardware frame counter */
1837 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1839 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1841 assert_vblank_disabled(&crtc->base);
1842 drm_crtc_set_max_vblank_count(&crtc->base,
1843 intel_crtc_max_vblank_count(crtc_state));
1844 drm_crtc_vblank_on(&crtc->base);
1847 static void intel_crtc_vblank_off(struct intel_crtc *crtc)
1849 drm_crtc_vblank_off(&crtc->base);
1850 assert_vblank_disabled(&crtc->base);
1853 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1855 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1856 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1857 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1858 enum pipe pipe = crtc->pipe;
1862 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1864 assert_planes_disabled(crtc);
1867 * A pipe without a PLL won't actually be able to drive bits from
1868 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1871 if (HAS_GMCH(dev_priv)) {
1872 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1873 assert_dsi_pll_enabled(dev_priv);
1875 assert_pll_enabled(dev_priv, pipe);
1877 if (new_crtc_state->has_pch_encoder) {
1878 /* if driving the PCH, we need FDI enabled */
1879 assert_fdi_rx_pll_enabled(dev_priv,
1880 intel_crtc_pch_transcoder(crtc));
1881 assert_fdi_tx_pll_enabled(dev_priv,
1882 (enum pipe) cpu_transcoder);
1884 /* FIXME: assert CPU port conditions for SNB+ */
1887 trace_intel_pipe_enable(crtc);
1889 reg = PIPECONF(cpu_transcoder);
1890 val = I915_READ(reg);
1891 if (val & PIPECONF_ENABLE) {
1892 /* we keep both pipes enabled on 830 */
1893 WARN_ON(!IS_I830(dev_priv));
1897 I915_WRITE(reg, val | PIPECONF_ENABLE);
1901 * Until the pipe starts PIPEDSL reads will return a stale value,
1902 * which causes an apparent vblank timestamp jump when PIPEDSL
1903 * resets to its proper value. That also messes up the frame count
1904 * when it's derived from the timestamps. So let's wait for the
1905 * pipe to start properly before we call drm_crtc_vblank_on()
1907 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1908 intel_wait_for_pipe_scanline_moving(crtc);
1911 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1913 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1914 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1915 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1916 enum pipe pipe = crtc->pipe;
1920 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1923 * Make sure planes won't keep trying to pump pixels to us,
1924 * or we might hang the display.
1926 assert_planes_disabled(crtc);
1928 trace_intel_pipe_disable(crtc);
1930 reg = PIPECONF(cpu_transcoder);
1931 val = I915_READ(reg);
1932 if ((val & PIPECONF_ENABLE) == 0)
1936 * Double wide has implications for planes
1937 * so best keep it disabled when not needed.
1939 if (old_crtc_state->double_wide)
1940 val &= ~PIPECONF_DOUBLE_WIDE;
1942 /* Don't disable pipe or pipe PLLs if needed */
1943 if (!IS_I830(dev_priv))
1944 val &= ~PIPECONF_ENABLE;
1946 I915_WRITE(reg, val);
1947 if ((val & PIPECONF_ENABLE) == 0)
1948 intel_wait_for_pipe_off(old_crtc_state);
1951 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1953 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1957 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1959 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1960 unsigned int cpp = fb->format->cpp[color_plane];
1962 switch (fb->modifier) {
1963 case DRM_FORMAT_MOD_LINEAR:
1964 return intel_tile_size(dev_priv);
1965 case I915_FORMAT_MOD_X_TILED:
1966 if (IS_GEN(dev_priv, 2))
1970 case I915_FORMAT_MOD_Y_TILED_CCS:
1971 if (color_plane == 1)
1974 case I915_FORMAT_MOD_Y_TILED:
1975 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1979 case I915_FORMAT_MOD_Yf_TILED_CCS:
1980 if (color_plane == 1)
1983 case I915_FORMAT_MOD_Yf_TILED:
1999 MISSING_CASE(fb->modifier);
2005 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2007 return intel_tile_size(to_i915(fb->dev)) /
2008 intel_tile_width_bytes(fb, color_plane);
2011 /* Return the tile dimensions in pixel units */
2012 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2013 unsigned int *tile_width,
2014 unsigned int *tile_height)
2016 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2017 unsigned int cpp = fb->format->cpp[color_plane];
2019 *tile_width = tile_width_bytes / cpp;
2020 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2024 intel_fb_align_height(const struct drm_framebuffer *fb,
2025 int color_plane, unsigned int height)
2027 unsigned int tile_height = intel_tile_height(fb, color_plane);
2029 return ALIGN(height, tile_height);
2032 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2034 unsigned int size = 0;
2037 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2038 size += rot_info->plane[i].width * rot_info->plane[i].height;
2043 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2045 unsigned int size = 0;
2048 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2049 size += rem_info->plane[i].width * rem_info->plane[i].height;
2055 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2056 const struct drm_framebuffer *fb,
2057 unsigned int rotation)
2059 view->type = I915_GGTT_VIEW_NORMAL;
2060 if (drm_rotation_90_or_270(rotation)) {
2061 view->type = I915_GGTT_VIEW_ROTATED;
2062 view->rotated = to_intel_framebuffer(fb)->rot_info;
2066 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2068 if (IS_I830(dev_priv))
2070 else if (IS_I85X(dev_priv))
2072 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2078 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2080 if (INTEL_GEN(dev_priv) >= 9)
2082 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2083 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2085 else if (INTEL_GEN(dev_priv) >= 4)
2091 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2094 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2096 /* AUX_DIST needs only 4K alignment */
2097 if (color_plane == 1)
2100 switch (fb->modifier) {
2101 case DRM_FORMAT_MOD_LINEAR:
2102 return intel_linear_alignment(dev_priv);
2103 case I915_FORMAT_MOD_X_TILED:
2104 if (INTEL_GEN(dev_priv) >= 9)
2107 case I915_FORMAT_MOD_Y_TILED_CCS:
2108 case I915_FORMAT_MOD_Yf_TILED_CCS:
2109 case I915_FORMAT_MOD_Y_TILED:
2110 case I915_FORMAT_MOD_Yf_TILED:
2111 return 1 * 1024 * 1024;
2113 MISSING_CASE(fb->modifier);
2118 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2120 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2121 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2123 return INTEL_GEN(dev_priv) < 4 ||
2125 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2129 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2130 const struct i915_ggtt_view *view,
2132 unsigned long *out_flags)
2134 struct drm_device *dev = fb->dev;
2135 struct drm_i915_private *dev_priv = to_i915(dev);
2136 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2137 intel_wakeref_t wakeref;
2138 struct i915_vma *vma;
2139 unsigned int pinctl;
2142 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2143 return ERR_PTR(-EINVAL);
2145 alignment = intel_surf_alignment(fb, 0);
2147 /* Note that the w/a also requires 64 PTE of padding following the
2148 * bo. We currently fill all unused PTE with the shadow page and so
2149 * we should always have valid PTE following the scanout preventing
2152 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2153 alignment = 256 * 1024;
2156 * Global gtt pte registers are special registers which actually forward
2157 * writes to a chunk of system memory. Which means that there is no risk
2158 * that the register values disappear as soon as we call
2159 * intel_runtime_pm_put(), so it is correct to wrap only the
2160 * pin/unpin/fence and not more.
2162 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2163 i915_gem_object_lock(obj);
2165 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2169 /* Valleyview is definitely limited to scanning out the first
2170 * 512MiB. Lets presume this behaviour was inherited from the
2171 * g4x display engine and that all earlier gen are similarly
2172 * limited. Testing suggests that it is a little more
2173 * complicated than this. For example, Cherryview appears quite
2174 * happy to scanout from anywhere within its global aperture.
2176 if (HAS_GMCH(dev_priv))
2177 pinctl |= PIN_MAPPABLE;
2179 vma = i915_gem_object_pin_to_display_plane(obj,
2180 alignment, view, pinctl);
2184 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2187 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2188 * fence, whereas 965+ only requires a fence if using
2189 * framebuffer compression. For simplicity, we always, when
2190 * possible, install a fence as the cost is not that onerous.
2192 * If we fail to fence the tiled scanout, then either the
2193 * modeset will reject the change (which is highly unlikely as
2194 * the affected systems, all but one, do not have unmappable
2195 * space) or we will not be able to enable full powersaving
2196 * techniques (also likely not to apply due to various limits
2197 * FBC and the like impose on the size of the buffer, which
2198 * presumably we violated anyway with this unmappable buffer).
2199 * Anyway, it is presumably better to stumble onwards with
2200 * something and try to run the system in a "less than optimal"
2201 * mode that matches the user configuration.
2203 ret = i915_vma_pin_fence(vma);
2204 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2205 i915_gem_object_unpin_from_display_plane(vma);
2210 if (ret == 0 && vma->fence)
2211 *out_flags |= PLANE_HAS_FENCE;
2216 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2218 i915_gem_object_unlock(obj);
2219 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2223 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2225 i915_gem_object_lock(vma->obj);
2226 if (flags & PLANE_HAS_FENCE)
2227 i915_vma_unpin_fence(vma);
2228 i915_gem_object_unpin_from_display_plane(vma);
2229 i915_gem_object_unlock(vma->obj);
2234 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2235 unsigned int rotation)
2237 if (drm_rotation_90_or_270(rotation))
2238 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2240 return fb->pitches[color_plane];
2244 * Convert the x/y offsets into a linear offset.
2245 * Only valid with 0/180 degree rotation, which is fine since linear
2246 * offset is only used with linear buffers on pre-hsw and tiled buffers
2247 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2249 u32 intel_fb_xy_to_linear(int x, int y,
2250 const struct intel_plane_state *state,
2253 const struct drm_framebuffer *fb = state->hw.fb;
2254 unsigned int cpp = fb->format->cpp[color_plane];
2255 unsigned int pitch = state->color_plane[color_plane].stride;
2257 return y * pitch + x * cpp;
2261 * Add the x/y offsets derived from fb->offsets[] to the user
2262 * specified plane src x/y offsets. The resulting x/y offsets
2263 * specify the start of scanout from the beginning of the gtt mapping.
2265 void intel_add_fb_offsets(int *x, int *y,
2266 const struct intel_plane_state *state,
2270 *x += state->color_plane[color_plane].x;
2271 *y += state->color_plane[color_plane].y;
2274 static u32 intel_adjust_tile_offset(int *x, int *y,
2275 unsigned int tile_width,
2276 unsigned int tile_height,
2277 unsigned int tile_size,
2278 unsigned int pitch_tiles,
2282 unsigned int pitch_pixels = pitch_tiles * tile_width;
2285 WARN_ON(old_offset & (tile_size - 1));
2286 WARN_ON(new_offset & (tile_size - 1));
2287 WARN_ON(new_offset > old_offset);
2289 tiles = (old_offset - new_offset) / tile_size;
2291 *y += tiles / pitch_tiles * tile_height;
2292 *x += tiles % pitch_tiles * tile_width;
2294 /* minimize x in case it got needlessly big */
2295 *y += *x / pitch_pixels * tile_height;
2301 static bool is_surface_linear(u64 modifier, int color_plane)
2303 return modifier == DRM_FORMAT_MOD_LINEAR;
2306 static u32 intel_adjust_aligned_offset(int *x, int *y,
2307 const struct drm_framebuffer *fb,
2309 unsigned int rotation,
2311 u32 old_offset, u32 new_offset)
2313 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2314 unsigned int cpp = fb->format->cpp[color_plane];
2316 WARN_ON(new_offset > old_offset);
2318 if (!is_surface_linear(fb->modifier, color_plane)) {
2319 unsigned int tile_size, tile_width, tile_height;
2320 unsigned int pitch_tiles;
2322 tile_size = intel_tile_size(dev_priv);
2323 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2325 if (drm_rotation_90_or_270(rotation)) {
2326 pitch_tiles = pitch / tile_height;
2327 swap(tile_width, tile_height);
2329 pitch_tiles = pitch / (tile_width * cpp);
2332 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2333 tile_size, pitch_tiles,
2334 old_offset, new_offset);
2336 old_offset += *y * pitch + *x * cpp;
2338 *y = (old_offset - new_offset) / pitch;
2339 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2346 * Adjust the tile offset by moving the difference into
2349 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2350 const struct intel_plane_state *state,
2352 u32 old_offset, u32 new_offset)
2354 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2356 state->color_plane[color_plane].stride,
2357 old_offset, new_offset);
2361 * Computes the aligned offset to the base tile and adjusts
2362 * x, y. bytes per pixel is assumed to be a power-of-two.
2364 * In the 90/270 rotated case, x and y are assumed
2365 * to be already rotated to match the rotated GTT view, and
2366 * pitch is the tile_height aligned framebuffer height.
2368 * This function is used when computing the derived information
2369 * under intel_framebuffer, so using any of that information
2370 * here is not allowed. Anything under drm_framebuffer can be
2371 * used. This is why the user has to pass in the pitch since it
2372 * is specified in the rotated orientation.
2374 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2376 const struct drm_framebuffer *fb,
2379 unsigned int rotation,
2382 unsigned int cpp = fb->format->cpp[color_plane];
2383 u32 offset, offset_aligned;
2388 if (!is_surface_linear(fb->modifier, color_plane)) {
2389 unsigned int tile_size, tile_width, tile_height;
2390 unsigned int tile_rows, tiles, pitch_tiles;
2392 tile_size = intel_tile_size(dev_priv);
2393 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2395 if (drm_rotation_90_or_270(rotation)) {
2396 pitch_tiles = pitch / tile_height;
2397 swap(tile_width, tile_height);
2399 pitch_tiles = pitch / (tile_width * cpp);
2402 tile_rows = *y / tile_height;
2405 tiles = *x / tile_width;
2408 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2409 offset_aligned = offset & ~alignment;
2411 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2412 tile_size, pitch_tiles,
2413 offset, offset_aligned);
2415 offset = *y * pitch + *x * cpp;
2416 offset_aligned = offset & ~alignment;
2418 *y = (offset & alignment) / pitch;
2419 *x = ((offset & alignment) - *y * pitch) / cpp;
2422 return offset_aligned;
2425 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2426 const struct intel_plane_state *state,
2429 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2430 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2431 const struct drm_framebuffer *fb = state->hw.fb;
2432 unsigned int rotation = state->hw.rotation;
2433 int pitch = state->color_plane[color_plane].stride;
2436 if (intel_plane->id == PLANE_CURSOR)
2437 alignment = intel_cursor_alignment(dev_priv);
2439 alignment = intel_surf_alignment(fb, color_plane);
2441 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2442 pitch, rotation, alignment);
2445 /* Convert the fb->offset[] into x/y offsets */
2446 static int intel_fb_offset_to_xy(int *x, int *y,
2447 const struct drm_framebuffer *fb,
2450 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2451 unsigned int height;
2453 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2454 fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2455 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2456 fb->offsets[color_plane], color_plane);
2460 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2461 height = ALIGN(height, intel_tile_height(fb, color_plane));
2463 /* Catch potential overflows early */
2464 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2465 fb->offsets[color_plane])) {
2466 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2467 fb->offsets[color_plane], fb->pitches[color_plane],
2475 intel_adjust_aligned_offset(x, y,
2476 fb, color_plane, DRM_MODE_ROTATE_0,
2477 fb->pitches[color_plane],
2478 fb->offsets[color_plane], 0);
2483 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2485 switch (fb_modifier) {
2486 case I915_FORMAT_MOD_X_TILED:
2487 return I915_TILING_X;
2488 case I915_FORMAT_MOD_Y_TILED:
2489 case I915_FORMAT_MOD_Y_TILED_CCS:
2490 return I915_TILING_Y;
2492 return I915_TILING_NONE;
2497 * From the Sky Lake PRM:
2498 * "The Color Control Surface (CCS) contains the compression status of
2499 * the cache-line pairs. The compression state of the cache-line pair
2500 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2501 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2502 * cache-line-pairs. CCS is always Y tiled."
2504 * Since cache line pairs refers to horizontally adjacent cache lines,
2505 * each cache line in the CCS corresponds to an area of 32x16 cache
2506 * lines on the main surface. Since each pixel is 4 bytes, this gives
2507 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2510 static const struct drm_format_info ccs_formats[] = {
2511 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2512 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2513 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2514 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2515 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2516 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2517 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2518 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2521 static const struct drm_format_info *
2522 lookup_format_info(const struct drm_format_info formats[],
2523 int num_formats, u32 format)
2527 for (i = 0; i < num_formats; i++) {
2528 if (formats[i].format == format)
2535 static const struct drm_format_info *
2536 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2538 switch (cmd->modifier[0]) {
2539 case I915_FORMAT_MOD_Y_TILED_CCS:
2540 case I915_FORMAT_MOD_Yf_TILED_CCS:
2541 return lookup_format_info(ccs_formats,
2542 ARRAY_SIZE(ccs_formats),
2549 bool is_ccs_modifier(u64 modifier)
2551 return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2552 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2555 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2556 u32 pixel_format, u64 modifier)
2558 struct intel_crtc *crtc;
2559 struct intel_plane *plane;
2562 * We assume the primary plane for pipe A has
2563 * the highest stride limits of them all.
2565 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2569 plane = to_intel_plane(crtc->base.primary);
2571 return plane->max_stride(plane, pixel_format, modifier,
2576 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2577 u32 pixel_format, u64 modifier)
2580 * Arbitrary limit for gen4+ chosen to match the
2581 * render engine max stride.
2583 * The new CCS hash mode makes remapping impossible
2585 if (!is_ccs_modifier(modifier)) {
2586 if (INTEL_GEN(dev_priv) >= 7)
2588 else if (INTEL_GEN(dev_priv) >= 4)
2592 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2596 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2598 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2600 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2601 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2606 * To make remapping with linear generally feasible
2607 * we need the stride to be page aligned.
2609 if (fb->pitches[color_plane] > max_stride)
2610 return intel_tile_size(dev_priv);
2614 return intel_tile_width_bytes(fb, color_plane);
2618 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2620 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2621 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2622 const struct drm_framebuffer *fb = plane_state->hw.fb;
2625 /* We don't want to deal with remapping with cursors */
2626 if (plane->id == PLANE_CURSOR)
2630 * The display engine limits already match/exceed the
2631 * render engine limits, so not much point in remapping.
2632 * Would also need to deal with the fence POT alignment
2633 * and gen2 2KiB GTT tile size.
2635 if (INTEL_GEN(dev_priv) < 4)
2639 * The new CCS hash mode isn't compatible with remapping as
2640 * the virtual address of the pages affects the compressed data.
2642 if (is_ccs_modifier(fb->modifier))
2645 /* Linear needs a page aligned stride for remapping */
2646 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2647 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2649 for (i = 0; i < fb->format->num_planes; i++) {
2650 if (fb->pitches[i] & alignment)
2658 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2660 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2661 const struct drm_framebuffer *fb = plane_state->hw.fb;
2662 unsigned int rotation = plane_state->hw.rotation;
2663 u32 stride, max_stride;
2666 * No remapping for invisible planes since we don't have
2667 * an actual source viewport to remap.
2669 if (!plane_state->uapi.visible)
2672 if (!intel_plane_can_remap(plane_state))
2676 * FIXME: aux plane limits on gen9+ are
2677 * unclear in Bspec, for now no checking.
2679 stride = intel_fb_pitch(fb, 0, rotation);
2680 max_stride = plane->max_stride(plane, fb->format->format,
2681 fb->modifier, rotation);
2683 return stride > max_stride;
2687 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2688 struct drm_framebuffer *fb)
2690 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2691 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2692 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2693 u32 gtt_offset_rotated = 0;
2694 unsigned int max_size = 0;
2695 int i, num_planes = fb->format->num_planes;
2696 unsigned int tile_size = intel_tile_size(dev_priv);
2698 for (i = 0; i < num_planes; i++) {
2699 unsigned int width, height;
2700 unsigned int cpp, size;
2705 cpp = fb->format->cpp[i];
2706 width = drm_framebuffer_plane_width(fb->width, fb, i);
2707 height = drm_framebuffer_plane_height(fb->height, fb, i);
2709 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2711 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2716 if (is_ccs_modifier(fb->modifier) && i == 1) {
2717 int hsub = fb->format->hsub;
2718 int vsub = fb->format->vsub;
2719 int tile_width, tile_height;
2723 intel_tile_dims(fb, i, &tile_width, &tile_height);
2725 tile_height *= vsub;
2727 ccs_x = (x * hsub) % tile_width;
2728 ccs_y = (y * vsub) % tile_height;
2729 main_x = intel_fb->normal[0].x % tile_width;
2730 main_y = intel_fb->normal[0].y % tile_height;
2733 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2734 * x/y offsets must match between CCS and the main surface.
2736 if (main_x != ccs_x || main_y != ccs_y) {
2737 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2740 intel_fb->normal[0].x,
2741 intel_fb->normal[0].y,
2748 * The fence (if used) is aligned to the start of the object
2749 * so having the framebuffer wrap around across the edge of the
2750 * fenced region doesn't really work. We have no API to configure
2751 * the fence start offset within the object (nor could we probably
2752 * on gen2/3). So it's just easier if we just require that the
2753 * fb layout agrees with the fence layout. We already check that the
2754 * fb stride matches the fence stride elsewhere.
2756 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2757 (x + width) * cpp > fb->pitches[i]) {
2758 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2764 * First pixel of the framebuffer from
2765 * the start of the normal gtt mapping.
2767 intel_fb->normal[i].x = x;
2768 intel_fb->normal[i].y = y;
2770 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2774 offset /= tile_size;
2776 if (!is_surface_linear(fb->modifier, i)) {
2777 unsigned int tile_width, tile_height;
2778 unsigned int pitch_tiles;
2781 intel_tile_dims(fb, i, &tile_width, &tile_height);
2783 rot_info->plane[i].offset = offset;
2784 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2785 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2786 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2788 intel_fb->rotated[i].pitch =
2789 rot_info->plane[i].height * tile_height;
2791 /* how many tiles does this plane need */
2792 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2794 * If the plane isn't horizontally tile aligned,
2795 * we need one more tile.
2800 /* rotate the x/y offsets to match the GTT view */
2801 drm_rect_init(&r, x, y, width, height);
2803 rot_info->plane[i].width * tile_width,
2804 rot_info->plane[i].height * tile_height,
2805 DRM_MODE_ROTATE_270);
2809 /* rotate the tile dimensions to match the GTT view */
2810 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2811 swap(tile_width, tile_height);
2814 * We only keep the x/y offsets, so push all of the
2815 * gtt offset into the x/y offsets.
2817 intel_adjust_tile_offset(&x, &y,
2818 tile_width, tile_height,
2819 tile_size, pitch_tiles,
2820 gtt_offset_rotated * tile_size, 0);
2822 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2825 * First pixel of the framebuffer from
2826 * the start of the rotated gtt mapping.
2828 intel_fb->rotated[i].x = x;
2829 intel_fb->rotated[i].y = y;
2831 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2832 x * cpp, tile_size);
2835 /* how many tiles in total needed in the bo */
2836 max_size = max(max_size, offset + size);
2839 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2840 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2841 mul_u32_u32(max_size, tile_size), obj->base.size);
2849 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2851 struct drm_i915_private *dev_priv =
2852 to_i915(plane_state->uapi.plane->dev);
2853 struct drm_framebuffer *fb = plane_state->hw.fb;
2854 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2855 struct intel_rotation_info *info = &plane_state->view.rotated;
2856 unsigned int rotation = plane_state->hw.rotation;
2857 int i, num_planes = fb->format->num_planes;
2858 unsigned int tile_size = intel_tile_size(dev_priv);
2859 unsigned int src_x, src_y;
2860 unsigned int src_w, src_h;
2863 memset(&plane_state->view, 0, sizeof(plane_state->view));
2864 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2865 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2867 src_x = plane_state->uapi.src.x1 >> 16;
2868 src_y = plane_state->uapi.src.y1 >> 16;
2869 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2870 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2872 WARN_ON(is_ccs_modifier(fb->modifier));
2874 /* Make src coordinates relative to the viewport */
2875 drm_rect_translate(&plane_state->uapi.src,
2876 -(src_x << 16), -(src_y << 16));
2878 /* Rotate src coordinates to match rotated GTT view */
2879 if (drm_rotation_90_or_270(rotation))
2880 drm_rect_rotate(&plane_state->uapi.src,
2881 src_w << 16, src_h << 16,
2882 DRM_MODE_ROTATE_270);
2884 for (i = 0; i < num_planes; i++) {
2885 unsigned int hsub = i ? fb->format->hsub : 1;
2886 unsigned int vsub = i ? fb->format->vsub : 1;
2887 unsigned int cpp = fb->format->cpp[i];
2888 unsigned int tile_width, tile_height;
2889 unsigned int width, height;
2890 unsigned int pitch_tiles;
2894 intel_tile_dims(fb, i, &tile_width, &tile_height);
2898 width = src_w / hsub;
2899 height = src_h / vsub;
2902 * First pixel of the src viewport from the
2903 * start of the normal gtt mapping.
2905 x += intel_fb->normal[i].x;
2906 y += intel_fb->normal[i].y;
2908 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2909 fb, i, fb->pitches[i],
2910 DRM_MODE_ROTATE_0, tile_size);
2911 offset /= tile_size;
2913 info->plane[i].offset = offset;
2914 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2916 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2917 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2919 if (drm_rotation_90_or_270(rotation)) {
2922 /* rotate the x/y offsets to match the GTT view */
2923 drm_rect_init(&r, x, y, width, height);
2925 info->plane[i].width * tile_width,
2926 info->plane[i].height * tile_height,
2927 DRM_MODE_ROTATE_270);
2931 pitch_tiles = info->plane[i].height;
2932 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2934 /* rotate the tile dimensions to match the GTT view */
2935 swap(tile_width, tile_height);
2937 pitch_tiles = info->plane[i].width;
2938 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2942 * We only keep the x/y offsets, so push all of the
2943 * gtt offset into the x/y offsets.
2945 intel_adjust_tile_offset(&x, &y,
2946 tile_width, tile_height,
2947 tile_size, pitch_tiles,
2948 gtt_offset * tile_size, 0);
2950 gtt_offset += info->plane[i].width * info->plane[i].height;
2952 plane_state->color_plane[i].offset = 0;
2953 plane_state->color_plane[i].x = x;
2954 plane_state->color_plane[i].y = y;
2959 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2961 const struct intel_framebuffer *fb =
2962 to_intel_framebuffer(plane_state->hw.fb);
2963 unsigned int rotation = plane_state->hw.rotation;
2969 num_planes = fb->base.format->num_planes;
2971 if (intel_plane_needs_remap(plane_state)) {
2972 intel_plane_remap_gtt(plane_state);
2975 * Sometimes even remapping can't overcome
2976 * the stride limitations :( Can happen with
2977 * big plane sizes and suitably misaligned
2980 return intel_plane_check_stride(plane_state);
2983 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2985 for (i = 0; i < num_planes; i++) {
2986 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2987 plane_state->color_plane[i].offset = 0;
2989 if (drm_rotation_90_or_270(rotation)) {
2990 plane_state->color_plane[i].x = fb->rotated[i].x;
2991 plane_state->color_plane[i].y = fb->rotated[i].y;
2993 plane_state->color_plane[i].x = fb->normal[i].x;
2994 plane_state->color_plane[i].y = fb->normal[i].y;
2998 /* Rotate src coordinates to match rotated GTT view */
2999 if (drm_rotation_90_or_270(rotation))
3000 drm_rect_rotate(&plane_state->uapi.src,
3001 fb->base.width << 16, fb->base.height << 16,
3002 DRM_MODE_ROTATE_270);
3004 return intel_plane_check_stride(plane_state);
3007 static int i9xx_format_to_fourcc(int format)
3010 case DISPPLANE_8BPP:
3011 return DRM_FORMAT_C8;
3012 case DISPPLANE_BGRA555:
3013 return DRM_FORMAT_ARGB1555;
3014 case DISPPLANE_BGRX555:
3015 return DRM_FORMAT_XRGB1555;
3016 case DISPPLANE_BGRX565:
3017 return DRM_FORMAT_RGB565;
3019 case DISPPLANE_BGRX888:
3020 return DRM_FORMAT_XRGB8888;
3021 case DISPPLANE_RGBX888:
3022 return DRM_FORMAT_XBGR8888;
3023 case DISPPLANE_BGRA888:
3024 return DRM_FORMAT_ARGB8888;
3025 case DISPPLANE_RGBA888:
3026 return DRM_FORMAT_ABGR8888;
3027 case DISPPLANE_BGRX101010:
3028 return DRM_FORMAT_XRGB2101010;
3029 case DISPPLANE_RGBX101010:
3030 return DRM_FORMAT_XBGR2101010;
3031 case DISPPLANE_BGRA101010:
3032 return DRM_FORMAT_ARGB2101010;
3033 case DISPPLANE_RGBA101010:
3034 return DRM_FORMAT_ABGR2101010;
3035 case DISPPLANE_RGBX161616:
3036 return DRM_FORMAT_XBGR16161616F;
3040 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3043 case PLANE_CTL_FORMAT_RGB_565:
3044 return DRM_FORMAT_RGB565;
3045 case PLANE_CTL_FORMAT_NV12:
3046 return DRM_FORMAT_NV12;
3047 case PLANE_CTL_FORMAT_P010:
3048 return DRM_FORMAT_P010;
3049 case PLANE_CTL_FORMAT_P012:
3050 return DRM_FORMAT_P012;
3051 case PLANE_CTL_FORMAT_P016:
3052 return DRM_FORMAT_P016;
3053 case PLANE_CTL_FORMAT_Y210:
3054 return DRM_FORMAT_Y210;
3055 case PLANE_CTL_FORMAT_Y212:
3056 return DRM_FORMAT_Y212;
3057 case PLANE_CTL_FORMAT_Y216:
3058 return DRM_FORMAT_Y216;
3059 case PLANE_CTL_FORMAT_Y410:
3060 return DRM_FORMAT_XVYU2101010;
3061 case PLANE_CTL_FORMAT_Y412:
3062 return DRM_FORMAT_XVYU12_16161616;
3063 case PLANE_CTL_FORMAT_Y416:
3064 return DRM_FORMAT_XVYU16161616;
3066 case PLANE_CTL_FORMAT_XRGB_8888:
3069 return DRM_FORMAT_ABGR8888;
3071 return DRM_FORMAT_XBGR8888;
3074 return DRM_FORMAT_ARGB8888;
3076 return DRM_FORMAT_XRGB8888;
3078 case PLANE_CTL_FORMAT_XRGB_2101010:
3081 return DRM_FORMAT_ABGR2101010;
3083 return DRM_FORMAT_XBGR2101010;
3086 return DRM_FORMAT_ARGB2101010;
3088 return DRM_FORMAT_XRGB2101010;
3090 case PLANE_CTL_FORMAT_XRGB_16161616F:
3093 return DRM_FORMAT_ABGR16161616F;
3095 return DRM_FORMAT_XBGR16161616F;
3098 return DRM_FORMAT_ARGB16161616F;
3100 return DRM_FORMAT_XRGB16161616F;
3106 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3107 struct intel_initial_plane_config *plane_config)
3109 struct drm_device *dev = crtc->base.dev;
3110 struct drm_i915_private *dev_priv = to_i915(dev);
3111 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3112 struct drm_framebuffer *fb = &plane_config->fb->base;
3113 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3114 u32 size_aligned = round_up(plane_config->base + plane_config->size,
3116 struct drm_i915_gem_object *obj;
3119 size_aligned -= base_aligned;
3121 if (plane_config->size == 0)
3124 /* If the FB is too big, just don't use it since fbdev is not very
3125 * important and we should probably use that space with FBC or other
3127 if (size_aligned * 2 > dev_priv->stolen_usable_size)
3130 switch (fb->modifier) {
3131 case DRM_FORMAT_MOD_LINEAR:
3132 case I915_FORMAT_MOD_X_TILED:
3133 case I915_FORMAT_MOD_Y_TILED:
3136 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3141 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3148 switch (plane_config->tiling) {
3149 case I915_TILING_NONE:
3153 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3156 MISSING_CASE(plane_config->tiling);
3160 mode_cmd.pixel_format = fb->format->format;
3161 mode_cmd.width = fb->width;
3162 mode_cmd.height = fb->height;
3163 mode_cmd.pitches[0] = fb->pitches[0];
3164 mode_cmd.modifier[0] = fb->modifier;
3165 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3167 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3168 DRM_DEBUG_KMS("intel fb init failed\n");
3173 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3176 i915_gem_object_put(obj);
3181 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3182 struct intel_plane_state *plane_state,
3185 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3187 plane_state->uapi.visible = visible;
3190 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3192 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3195 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3197 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3198 struct drm_plane *plane;
3201 * Active_planes aliases if multiple "primary" or cursor planes
3202 * have been used on the same (or wrong) pipe. plane_mask uses
3203 * unique ids, hence we can use that to reconstruct active_planes.
3205 crtc_state->active_planes = 0;
3207 drm_for_each_plane_mask(plane, &dev_priv->drm,
3208 crtc_state->uapi.plane_mask)
3209 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3212 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3213 struct intel_plane *plane)
3215 struct intel_crtc_state *crtc_state =
3216 to_intel_crtc_state(crtc->base.state);
3217 struct intel_plane_state *plane_state =
3218 to_intel_plane_state(plane->base.state);
3220 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3221 plane->base.base.id, plane->base.name,
3222 crtc->base.base.id, crtc->base.name);
3224 intel_set_plane_visible(crtc_state, plane_state, false);
3225 fixup_active_planes(crtc_state);
3226 crtc_state->data_rate[plane->id] = 0;
3227 crtc_state->min_cdclk[plane->id] = 0;
3229 if (plane->id == PLANE_PRIMARY)
3230 intel_pre_disable_primary_noatomic(&crtc->base);
3232 intel_disable_plane(plane, crtc_state);
3235 static struct intel_frontbuffer *
3236 to_intel_frontbuffer(struct drm_framebuffer *fb)
3238 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3242 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3243 struct intel_initial_plane_config *plane_config)
3245 struct drm_device *dev = intel_crtc->base.dev;
3246 struct drm_i915_private *dev_priv = to_i915(dev);
3248 struct drm_plane *primary = intel_crtc->base.primary;
3249 struct drm_plane_state *plane_state = primary->state;
3250 struct intel_plane *intel_plane = to_intel_plane(primary);
3251 struct intel_plane_state *intel_state =
3252 to_intel_plane_state(plane_state);
3253 struct drm_framebuffer *fb;
3255 if (!plane_config->fb)
3258 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3259 fb = &plane_config->fb->base;
3263 kfree(plane_config->fb);
3266 * Failed to alloc the obj, check to see if we should share
3267 * an fb with another CRTC instead
3269 for_each_crtc(dev, c) {
3270 struct intel_plane_state *state;
3272 if (c == &intel_crtc->base)
3275 if (!to_intel_crtc(c)->active)
3278 state = to_intel_plane_state(c->primary->state);
3282 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3284 drm_framebuffer_get(fb);
3290 * We've failed to reconstruct the BIOS FB. Current display state
3291 * indicates that the primary plane is visible, but has a NULL FB,
3292 * which will lead to problems later if we don't fix it up. The
3293 * simplest solution is to just disable the primary plane now and
3294 * pretend the BIOS never had it enabled.
3296 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3301 intel_state->hw.rotation = plane_config->rotation;
3302 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3303 intel_state->hw.rotation);
3304 intel_state->color_plane[0].stride =
3305 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3308 intel_pin_and_fence_fb_obj(fb,
3310 intel_plane_uses_fence(intel_state),
3311 &intel_state->flags);
3312 if (IS_ERR(intel_state->vma)) {
3313 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3314 intel_crtc->pipe, PTR_ERR(intel_state->vma));
3316 intel_state->vma = NULL;
3317 drm_framebuffer_put(fb);
3321 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3323 plane_state->src_x = 0;
3324 plane_state->src_y = 0;
3325 plane_state->src_w = fb->width << 16;
3326 plane_state->src_h = fb->height << 16;
3328 plane_state->crtc_x = 0;
3329 plane_state->crtc_y = 0;
3330 plane_state->crtc_w = fb->width;
3331 plane_state->crtc_h = fb->height;
3333 intel_state->uapi.src = drm_plane_state_src(plane_state);
3334 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3336 if (plane_config->tiling)
3337 dev_priv->preserve_bios_swizzle = true;
3339 plane_state->fb = fb;
3340 plane_state->crtc = &intel_crtc->base;
3341 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3343 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3344 &to_intel_frontbuffer(fb)->bits);
3347 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3349 unsigned int rotation)
3351 int cpp = fb->format->cpp[color_plane];
3353 switch (fb->modifier) {
3354 case DRM_FORMAT_MOD_LINEAR:
3355 case I915_FORMAT_MOD_X_TILED:
3357 * Validated limit is 4k, but has 5k should
3358 * work apart from the following features:
3359 * - Ytile (already limited to 4k)
3360 * - FP16 (already limited to 4k)
3361 * - render compression (already limited to 4k)
3362 * - KVMR sprite and cursor (don't care)
3363 * - horizontal panning (TODO verify this)
3364 * - pipe and plane scaling (TODO verify this)
3370 case I915_FORMAT_MOD_Y_TILED_CCS:
3371 case I915_FORMAT_MOD_Yf_TILED_CCS:
3372 /* FIXME AUX plane? */
3373 case I915_FORMAT_MOD_Y_TILED:
3374 case I915_FORMAT_MOD_Yf_TILED:
3380 MISSING_CASE(fb->modifier);
3385 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3387 unsigned int rotation)
3389 int cpp = fb->format->cpp[color_plane];
3391 switch (fb->modifier) {
3392 case DRM_FORMAT_MOD_LINEAR:
3393 case I915_FORMAT_MOD_X_TILED:
3398 case I915_FORMAT_MOD_Y_TILED_CCS:
3399 case I915_FORMAT_MOD_Yf_TILED_CCS:
3400 /* FIXME AUX plane? */
3401 case I915_FORMAT_MOD_Y_TILED:
3402 case I915_FORMAT_MOD_Yf_TILED:
3408 MISSING_CASE(fb->modifier);
3413 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3415 unsigned int rotation)
3420 static int skl_max_plane_height(void)
3425 static int icl_max_plane_height(void)
3430 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3431 int main_x, int main_y, u32 main_offset)
3433 const struct drm_framebuffer *fb = plane_state->hw.fb;
3434 int hsub = fb->format->hsub;
3435 int vsub = fb->format->vsub;
3436 int aux_x = plane_state->color_plane[1].x;
3437 int aux_y = plane_state->color_plane[1].y;
3438 u32 aux_offset = plane_state->color_plane[1].offset;
3439 u32 alignment = intel_surf_alignment(fb, 1);
3441 while (aux_offset >= main_offset && aux_y <= main_y) {
3444 if (aux_x == main_x && aux_y == main_y)
3447 if (aux_offset == 0)
3452 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3453 aux_offset, aux_offset - alignment);
3454 aux_x = x * hsub + aux_x % hsub;
3455 aux_y = y * vsub + aux_y % vsub;
3458 if (aux_x != main_x || aux_y != main_y)
3461 plane_state->color_plane[1].offset = aux_offset;
3462 plane_state->color_plane[1].x = aux_x;
3463 plane_state->color_plane[1].y = aux_y;
3468 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3470 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3471 const struct drm_framebuffer *fb = plane_state->hw.fb;
3472 unsigned int rotation = plane_state->hw.rotation;
3473 int x = plane_state->uapi.src.x1 >> 16;
3474 int y = plane_state->uapi.src.y1 >> 16;
3475 int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3476 int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3479 u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3481 if (INTEL_GEN(dev_priv) >= 11)
3482 max_width = icl_max_plane_width(fb, 0, rotation);
3483 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3484 max_width = glk_max_plane_width(fb, 0, rotation);
3486 max_width = skl_max_plane_width(fb, 0, rotation);
3488 if (INTEL_GEN(dev_priv) >= 11)
3489 max_height = icl_max_plane_height();
3491 max_height = skl_max_plane_height();
3493 if (w > max_width || h > max_height) {
3494 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3495 w, h, max_width, max_height);
3499 intel_add_fb_offsets(&x, &y, plane_state, 0);
3500 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3501 alignment = intel_surf_alignment(fb, 0);
3504 * AUX surface offset is specified as the distance from the
3505 * main surface offset, and it must be non-negative. Make
3506 * sure that is what we will get.
3508 if (offset > aux_offset)
3509 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3510 offset, aux_offset & ~(alignment - 1));
3513 * When using an X-tiled surface, the plane blows up
3514 * if the x offset + width exceed the stride.
3516 * TODO: linear and Y-tiled seem fine, Yf untested,
3518 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3519 int cpp = fb->format->cpp[0];
3521 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3523 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3527 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3528 offset, offset - alignment);
3533 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3534 * they match with the main surface x/y offsets.
3536 if (is_ccs_modifier(fb->modifier)) {
3537 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3541 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3542 offset, offset - alignment);
3545 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3546 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3551 plane_state->color_plane[0].offset = offset;
3552 plane_state->color_plane[0].x = x;
3553 plane_state->color_plane[0].y = y;
3556 * Put the final coordinates back so that the src
3557 * coordinate checks will see the right values.
3559 drm_rect_translate_to(&plane_state->uapi.src,
3565 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3567 const struct drm_framebuffer *fb = plane_state->hw.fb;
3568 unsigned int rotation = plane_state->hw.rotation;
3569 int max_width = skl_max_plane_width(fb, 1, rotation);
3570 int max_height = 4096;
3571 int x = plane_state->uapi.src.x1 >> 17;
3572 int y = plane_state->uapi.src.y1 >> 17;
3573 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3574 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3577 intel_add_fb_offsets(&x, &y, plane_state, 1);
3578 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3580 /* FIXME not quite sure how/if these apply to the chroma plane */
3581 if (w > max_width || h > max_height) {
3582 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3583 w, h, max_width, max_height);
3587 plane_state->color_plane[1].offset = offset;
3588 plane_state->color_plane[1].x = x;
3589 plane_state->color_plane[1].y = y;
3594 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3596 const struct drm_framebuffer *fb = plane_state->hw.fb;
3597 int src_x = plane_state->uapi.src.x1 >> 16;
3598 int src_y = plane_state->uapi.src.y1 >> 16;
3599 int hsub = fb->format->hsub;
3600 int vsub = fb->format->vsub;
3601 int x = src_x / hsub;
3602 int y = src_y / vsub;
3605 intel_add_fb_offsets(&x, &y, plane_state, 1);
3606 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3608 plane_state->color_plane[1].offset = offset;
3609 plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3610 plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3615 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3617 const struct drm_framebuffer *fb = plane_state->hw.fb;
3620 ret = intel_plane_compute_gtt(plane_state);
3624 if (!plane_state->uapi.visible)
3628 * Handle the AUX surface first since
3629 * the main surface setup depends on it.
3631 if (drm_format_info_is_yuv_semiplanar(fb->format)) {
3632 ret = skl_check_nv12_aux_surface(plane_state);
3635 } else if (is_ccs_modifier(fb->modifier)) {
3636 ret = skl_check_ccs_aux_surface(plane_state);
3640 plane_state->color_plane[1].offset = ~0xfff;
3641 plane_state->color_plane[1].x = 0;
3642 plane_state->color_plane[1].y = 0;
3645 ret = skl_check_main_surface(plane_state);
3652 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
3653 const struct intel_plane_state *plane_state,
3654 unsigned int *num, unsigned int *den)
3656 const struct drm_framebuffer *fb = plane_state->hw.fb;
3657 unsigned int cpp = fb->format->cpp[0];
3660 * g4x bspec says 64bpp pixel rate can't exceed 80%
3661 * of cdclk when the sprite plane is enabled on the
3662 * same pipe. ilk/snb bspec says 64bpp pixel rate is
3663 * never allowed to exceed 80% of cdclk. Let's just go
3664 * with the ilk/snb limit always.
3675 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
3676 const struct intel_plane_state *plane_state)
3678 unsigned int pixel_rate;
3679 unsigned int num, den;
3682 * Note that crtc_state->pixel_rate accounts for both
3683 * horizontal and vertical panel fitter downscaling factors.
3684 * Pre-HSW bspec tells us to only consider the horizontal
3685 * downscaling factor here. We ignore that and just consider
3686 * both for simplicity.
3688 pixel_rate = crtc_state->pixel_rate;
3690 i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
3692 /* two pixels per clock with double wide pipe */
3693 if (crtc_state->double_wide)
3696 return DIV_ROUND_UP(pixel_rate * num, den);
3700 i9xx_plane_max_stride(struct intel_plane *plane,
3701 u32 pixel_format, u64 modifier,
3702 unsigned int rotation)
3704 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3706 if (!HAS_GMCH(dev_priv)) {
3708 } else if (INTEL_GEN(dev_priv) >= 4) {
3709 if (modifier == I915_FORMAT_MOD_X_TILED)
3713 } else if (INTEL_GEN(dev_priv) >= 3) {
3714 if (modifier == I915_FORMAT_MOD_X_TILED)
3719 if (plane->i9xx_plane == PLANE_C)
3726 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3728 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3729 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3732 if (crtc_state->gamma_enable)
3733 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3735 if (crtc_state->csc_enable)
3736 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3738 if (INTEL_GEN(dev_priv) < 5)
3739 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3744 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3745 const struct intel_plane_state *plane_state)
3747 struct drm_i915_private *dev_priv =
3748 to_i915(plane_state->uapi.plane->dev);
3749 const struct drm_framebuffer *fb = plane_state->hw.fb;
3750 unsigned int rotation = plane_state->hw.rotation;
3753 dspcntr = DISPLAY_PLANE_ENABLE;
3755 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3756 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3757 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3759 switch (fb->format->format) {
3761 dspcntr |= DISPPLANE_8BPP;
3763 case DRM_FORMAT_XRGB1555:
3764 dspcntr |= DISPPLANE_BGRX555;
3766 case DRM_FORMAT_ARGB1555:
3767 dspcntr |= DISPPLANE_BGRA555;
3769 case DRM_FORMAT_RGB565:
3770 dspcntr |= DISPPLANE_BGRX565;
3772 case DRM_FORMAT_XRGB8888:
3773 dspcntr |= DISPPLANE_BGRX888;
3775 case DRM_FORMAT_XBGR8888:
3776 dspcntr |= DISPPLANE_RGBX888;
3778 case DRM_FORMAT_ARGB8888:
3779 dspcntr |= DISPPLANE_BGRA888;
3781 case DRM_FORMAT_ABGR8888:
3782 dspcntr |= DISPPLANE_RGBA888;
3784 case DRM_FORMAT_XRGB2101010:
3785 dspcntr |= DISPPLANE_BGRX101010;
3787 case DRM_FORMAT_XBGR2101010:
3788 dspcntr |= DISPPLANE_RGBX101010;
3790 case DRM_FORMAT_ARGB2101010:
3791 dspcntr |= DISPPLANE_BGRA101010;
3793 case DRM_FORMAT_ABGR2101010:
3794 dspcntr |= DISPPLANE_RGBA101010;
3796 case DRM_FORMAT_XBGR16161616F:
3797 dspcntr |= DISPPLANE_RGBX161616;
3800 MISSING_CASE(fb->format->format);
3804 if (INTEL_GEN(dev_priv) >= 4 &&
3805 fb->modifier == I915_FORMAT_MOD_X_TILED)
3806 dspcntr |= DISPPLANE_TILED;
3808 if (rotation & DRM_MODE_ROTATE_180)
3809 dspcntr |= DISPPLANE_ROTATE_180;
3811 if (rotation & DRM_MODE_REFLECT_X)
3812 dspcntr |= DISPPLANE_MIRROR;
3817 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3819 struct drm_i915_private *dev_priv =
3820 to_i915(plane_state->uapi.plane->dev);
3821 const struct drm_framebuffer *fb = plane_state->hw.fb;
3822 int src_x, src_y, src_w;
3826 ret = intel_plane_compute_gtt(plane_state);
3830 if (!plane_state->uapi.visible)
3833 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3834 src_x = plane_state->uapi.src.x1 >> 16;
3835 src_y = plane_state->uapi.src.y1 >> 16;
3837 /* Undocumented hardware limit on i965/g4x/vlv/chv */
3838 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
3841 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3843 if (INTEL_GEN(dev_priv) >= 4)
3844 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3850 * Put the final coordinates back so that the src
3851 * coordinate checks will see the right values.
3853 drm_rect_translate_to(&plane_state->uapi.src,
3854 src_x << 16, src_y << 16);
3856 /* HSW/BDW do this automagically in hardware */
3857 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3858 unsigned int rotation = plane_state->hw.rotation;
3859 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3860 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3862 if (rotation & DRM_MODE_ROTATE_180) {
3865 } else if (rotation & DRM_MODE_REFLECT_X) {
3870 plane_state->color_plane[0].offset = offset;
3871 plane_state->color_plane[0].x = src_x;
3872 plane_state->color_plane[0].y = src_y;
3877 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3879 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3880 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3882 if (IS_CHERRYVIEW(dev_priv))
3883 return i9xx_plane == PLANE_B;
3884 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3886 else if (IS_GEN(dev_priv, 4))
3887 return i9xx_plane == PLANE_C;
3889 return i9xx_plane == PLANE_B ||
3890 i9xx_plane == PLANE_C;
3894 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3895 struct intel_plane_state *plane_state)
3897 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3900 ret = chv_plane_check_rotation(plane_state);
3904 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
3906 DRM_PLANE_HELPER_NO_SCALING,
3907 DRM_PLANE_HELPER_NO_SCALING,
3908 i9xx_plane_has_windowing(plane),
3913 ret = i9xx_check_plane_surface(plane_state);
3917 if (!plane_state->uapi.visible)
3920 ret = intel_plane_check_src_coordinates(plane_state);
3924 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3929 static void i9xx_update_plane(struct intel_plane *plane,
3930 const struct intel_crtc_state *crtc_state,
3931 const struct intel_plane_state *plane_state)
3933 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3934 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3936 int x = plane_state->color_plane[0].x;
3937 int y = plane_state->color_plane[0].y;
3938 int crtc_x = plane_state->uapi.dst.x1;
3939 int crtc_y = plane_state->uapi.dst.y1;
3940 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
3941 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
3942 unsigned long irqflags;
3946 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3948 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3950 if (INTEL_GEN(dev_priv) >= 4)
3951 dspaddr_offset = plane_state->color_plane[0].offset;
3953 dspaddr_offset = linear_offset;
3955 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3957 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3959 if (INTEL_GEN(dev_priv) < 4) {
3961 * PLANE_A doesn't actually have a full window
3962 * generator but let's assume we still need to
3963 * program whatever is there.
3965 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3966 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3967 ((crtc_h - 1) << 16) | (crtc_w - 1));
3968 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3969 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3970 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3971 ((crtc_h - 1) << 16) | (crtc_w - 1));
3972 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3975 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3976 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3977 } else if (INTEL_GEN(dev_priv) >= 4) {
3978 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3979 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3983 * The control register self-arms if the plane was previously
3984 * disabled. Try to make the plane enable atomic by writing
3985 * the control register just before the surface register.
3987 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3988 if (INTEL_GEN(dev_priv) >= 4)
3989 I915_WRITE_FW(DSPSURF(i9xx_plane),
3990 intel_plane_ggtt_offset(plane_state) +
3993 I915_WRITE_FW(DSPADDR(i9xx_plane),
3994 intel_plane_ggtt_offset(plane_state) +
3997 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4000 static void i9xx_disable_plane(struct intel_plane *plane,
4001 const struct intel_crtc_state *crtc_state)
4003 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4004 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4005 unsigned long irqflags;
4009 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4010 * enable on ilk+ affect the pipe bottom color as
4011 * well, so we must configure them even if the plane
4014 * On pre-g4x there is no way to gamma correct the
4015 * pipe bottom color but we'll keep on doing this
4016 * anyway so that the crtc state readout works correctly.
4018 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4020 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4022 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
4023 if (INTEL_GEN(dev_priv) >= 4)
4024 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
4026 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
4028 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4031 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4034 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4035 enum intel_display_power_domain power_domain;
4036 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4037 intel_wakeref_t wakeref;
4042 * Not 100% correct for planes that can move between pipes,
4043 * but that's only the case for gen2-4 which don't have any
4044 * display power wells.
4046 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4047 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4051 val = I915_READ(DSPCNTR(i9xx_plane));
4053 ret = val & DISPLAY_PLANE_ENABLE;
4055 if (INTEL_GEN(dev_priv) >= 5)
4056 *pipe = plane->pipe;
4058 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4059 DISPPLANE_SEL_PIPE_SHIFT;
4061 intel_display_power_put(dev_priv, power_domain, wakeref);
4066 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4068 struct drm_device *dev = intel_crtc->base.dev;
4069 struct drm_i915_private *dev_priv = to_i915(dev);
4071 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4072 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4073 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4077 * This function detaches (aka. unbinds) unused scalers in hardware
4079 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4082 const struct intel_crtc_scaler_state *scaler_state =
4083 &crtc_state->scaler_state;
4086 /* loop through and disable scalers that aren't in use */
4087 for (i = 0; i < intel_crtc->num_scalers; i++) {
4088 if (!scaler_state->scalers[i].in_use)
4089 skl_detach_scaler(intel_crtc, i);
4093 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4094 int color_plane, unsigned int rotation)
4097 * The stride is either expressed as a multiple of 64 bytes chunks for
4098 * linear buffers or in number of tiles for tiled buffers.
4100 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
4102 else if (drm_rotation_90_or_270(rotation))
4103 return intel_tile_height(fb, color_plane);
4105 return intel_tile_width_bytes(fb, color_plane);
4108 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4111 const struct drm_framebuffer *fb = plane_state->hw.fb;
4112 unsigned int rotation = plane_state->hw.rotation;
4113 u32 stride = plane_state->color_plane[color_plane].stride;
4115 if (color_plane >= fb->format->num_planes)
4118 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4121 static u32 skl_plane_ctl_format(u32 pixel_format)
4123 switch (pixel_format) {
4125 return PLANE_CTL_FORMAT_INDEXED;
4126 case DRM_FORMAT_RGB565:
4127 return PLANE_CTL_FORMAT_RGB_565;
4128 case DRM_FORMAT_XBGR8888:
4129 case DRM_FORMAT_ABGR8888:
4130 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4131 case DRM_FORMAT_XRGB8888:
4132 case DRM_FORMAT_ARGB8888:
4133 return PLANE_CTL_FORMAT_XRGB_8888;
4134 case DRM_FORMAT_XBGR2101010:
4135 case DRM_FORMAT_ABGR2101010:
4136 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4137 case DRM_FORMAT_XRGB2101010:
4138 case DRM_FORMAT_ARGB2101010:
4139 return PLANE_CTL_FORMAT_XRGB_2101010;
4140 case DRM_FORMAT_XBGR16161616F:
4141 case DRM_FORMAT_ABGR16161616F:
4142 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4143 case DRM_FORMAT_XRGB16161616F:
4144 case DRM_FORMAT_ARGB16161616F:
4145 return PLANE_CTL_FORMAT_XRGB_16161616F;
4146 case DRM_FORMAT_YUYV:
4147 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4148 case DRM_FORMAT_YVYU:
4149 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4150 case DRM_FORMAT_UYVY:
4151 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4152 case DRM_FORMAT_VYUY:
4153 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4154 case DRM_FORMAT_NV12:
4155 return PLANE_CTL_FORMAT_NV12;
4156 case DRM_FORMAT_P010:
4157 return PLANE_CTL_FORMAT_P010;
4158 case DRM_FORMAT_P012:
4159 return PLANE_CTL_FORMAT_P012;
4160 case DRM_FORMAT_P016:
4161 return PLANE_CTL_FORMAT_P016;
4162 case DRM_FORMAT_Y210:
4163 return PLANE_CTL_FORMAT_Y210;
4164 case DRM_FORMAT_Y212:
4165 return PLANE_CTL_FORMAT_Y212;
4166 case DRM_FORMAT_Y216:
4167 return PLANE_CTL_FORMAT_Y216;
4168 case DRM_FORMAT_XVYU2101010:
4169 return PLANE_CTL_FORMAT_Y410;
4170 case DRM_FORMAT_XVYU12_16161616:
4171 return PLANE_CTL_FORMAT_Y412;
4172 case DRM_FORMAT_XVYU16161616:
4173 return PLANE_CTL_FORMAT_Y416;
4175 MISSING_CASE(pixel_format);
4181 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4183 if (!plane_state->hw.fb->format->has_alpha)
4184 return PLANE_CTL_ALPHA_DISABLE;
4186 switch (plane_state->hw.pixel_blend_mode) {
4187 case DRM_MODE_BLEND_PIXEL_NONE:
4188 return PLANE_CTL_ALPHA_DISABLE;
4189 case DRM_MODE_BLEND_PREMULTI:
4190 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4191 case DRM_MODE_BLEND_COVERAGE:
4192 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4194 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4195 return PLANE_CTL_ALPHA_DISABLE;
4199 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4201 if (!plane_state->hw.fb->format->has_alpha)
4202 return PLANE_COLOR_ALPHA_DISABLE;
4204 switch (plane_state->hw.pixel_blend_mode) {
4205 case DRM_MODE_BLEND_PIXEL_NONE:
4206 return PLANE_COLOR_ALPHA_DISABLE;
4207 case DRM_MODE_BLEND_PREMULTI:
4208 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4209 case DRM_MODE_BLEND_COVERAGE:
4210 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4212 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4213 return PLANE_COLOR_ALPHA_DISABLE;
4217 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4219 switch (fb_modifier) {
4220 case DRM_FORMAT_MOD_LINEAR:
4222 case I915_FORMAT_MOD_X_TILED:
4223 return PLANE_CTL_TILED_X;
4224 case I915_FORMAT_MOD_Y_TILED:
4225 return PLANE_CTL_TILED_Y;
4226 case I915_FORMAT_MOD_Y_TILED_CCS:
4227 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4228 case I915_FORMAT_MOD_Yf_TILED:
4229 return PLANE_CTL_TILED_YF;
4230 case I915_FORMAT_MOD_Yf_TILED_CCS:
4231 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4233 MISSING_CASE(fb_modifier);
4239 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4242 case DRM_MODE_ROTATE_0:
4245 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4246 * while i915 HW rotation is clockwise, thats why this swapping.
4248 case DRM_MODE_ROTATE_90:
4249 return PLANE_CTL_ROTATE_270;
4250 case DRM_MODE_ROTATE_180:
4251 return PLANE_CTL_ROTATE_180;
4252 case DRM_MODE_ROTATE_270:
4253 return PLANE_CTL_ROTATE_90;
4255 MISSING_CASE(rotate);
4261 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4266 case DRM_MODE_REFLECT_X:
4267 return PLANE_CTL_FLIP_HORIZONTAL;
4268 case DRM_MODE_REFLECT_Y:
4270 MISSING_CASE(reflect);
4276 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4278 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4281 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4284 if (crtc_state->gamma_enable)
4285 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4287 if (crtc_state->csc_enable)
4288 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4294 const struct intel_plane_state *plane_state)
4296 struct drm_i915_private *dev_priv =
4297 to_i915(plane_state->uapi.plane->dev);
4298 const struct drm_framebuffer *fb = plane_state->hw.fb;
4299 unsigned int rotation = plane_state->hw.rotation;
4300 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4303 plane_ctl = PLANE_CTL_ENABLE;
4305 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4306 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4307 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4309 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4310 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4312 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4313 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4316 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4317 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4318 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4320 if (INTEL_GEN(dev_priv) >= 10)
4321 plane_ctl |= cnl_plane_ctl_flip(rotation &
4322 DRM_MODE_REFLECT_MASK);
4324 if (key->flags & I915_SET_COLORKEY_DESTINATION)
4325 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4326 else if (key->flags & I915_SET_COLORKEY_SOURCE)
4327 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4332 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4334 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4335 u32 plane_color_ctl = 0;
4337 if (INTEL_GEN(dev_priv) >= 11)
4338 return plane_color_ctl;
4340 if (crtc_state->gamma_enable)
4341 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4343 if (crtc_state->csc_enable)
4344 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4346 return plane_color_ctl;
4349 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4350 const struct intel_plane_state *plane_state)
4352 struct drm_i915_private *dev_priv =
4353 to_i915(plane_state->uapi.plane->dev);
4354 const struct drm_framebuffer *fb = plane_state->hw.fb;
4355 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4356 u32 plane_color_ctl = 0;
4358 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4359 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4361 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4362 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4363 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4365 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4367 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4368 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4369 } else if (fb->format->is_yuv) {
4370 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4373 return plane_color_ctl;
4377 __intel_display_resume(struct drm_device *dev,
4378 struct drm_atomic_state *state,
4379 struct drm_modeset_acquire_ctx *ctx)
4381 struct drm_crtc_state *crtc_state;
4382 struct drm_crtc *crtc;
4385 intel_modeset_setup_hw_state(dev, ctx);
4386 intel_vga_redisable(to_i915(dev));
4392 * We've duplicated the state, pointers to the old state are invalid.
4394 * Don't attempt to use the old state until we commit the duplicated state.
4396 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4398 * Force recalculation even if we restore
4399 * current state. With fast modeset this may not result
4400 * in a modeset when the state is compatible.
4402 crtc_state->mode_changed = true;
4405 /* ignore any reset values/BIOS leftovers in the WM registers */
4406 if (!HAS_GMCH(to_i915(dev)))
4407 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4409 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4411 WARN_ON(ret == -EDEADLK);
4415 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4417 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4418 intel_has_gpu_reset(&dev_priv->gt));
4421 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4423 struct drm_device *dev = &dev_priv->drm;
4424 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4425 struct drm_atomic_state *state;
4428 /* reset doesn't touch the display */
4429 if (!i915_modparams.force_reset_modeset_test &&
4430 !gpu_reset_clobbers_display(dev_priv))
4433 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4434 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4435 smp_mb__after_atomic();
4436 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4438 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4439 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4440 intel_gt_set_wedged(&dev_priv->gt);
4444 * Need mode_config.mutex so that we don't
4445 * trample ongoing ->detect() and whatnot.
4447 mutex_lock(&dev->mode_config.mutex);
4448 drm_modeset_acquire_init(ctx, 0);
4450 ret = drm_modeset_lock_all_ctx(dev, ctx);
4451 if (ret != -EDEADLK)
4454 drm_modeset_backoff(ctx);
4457 * Disabling the crtcs gracefully seems nicer. Also the
4458 * g33 docs say we should at least disable all the planes.
4460 state = drm_atomic_helper_duplicate_state(dev, ctx);
4461 if (IS_ERR(state)) {
4462 ret = PTR_ERR(state);
4463 DRM_ERROR("Duplicating state failed with %i\n", ret);
4467 ret = drm_atomic_helper_disable_all(dev, ctx);
4469 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4470 drm_atomic_state_put(state);
4474 dev_priv->modeset_restore_state = state;
4475 state->acquire_ctx = ctx;
4478 void intel_finish_reset(struct drm_i915_private *dev_priv)
4480 struct drm_device *dev = &dev_priv->drm;
4481 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4482 struct drm_atomic_state *state;
4485 /* reset doesn't touch the display */
4486 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4489 state = fetch_and_zero(&dev_priv->modeset_restore_state);
4493 /* reset doesn't touch the display */
4494 if (!gpu_reset_clobbers_display(dev_priv)) {
4495 /* for testing only restore the display */
4496 ret = __intel_display_resume(dev, state, ctx);
4498 DRM_ERROR("Restoring old state failed with %i\n", ret);
4501 * The display has been reset as well,
4502 * so need a full re-initialization.
4504 intel_pps_unlock_regs_wa(dev_priv);
4505 intel_modeset_init_hw(dev_priv);
4506 intel_init_clock_gating(dev_priv);
4508 spin_lock_irq(&dev_priv->irq_lock);
4509 if (dev_priv->display.hpd_irq_setup)
4510 dev_priv->display.hpd_irq_setup(dev_priv);
4511 spin_unlock_irq(&dev_priv->irq_lock);
4513 ret = __intel_display_resume(dev, state, ctx);
4515 DRM_ERROR("Restoring old state failed with %i\n", ret);
4517 intel_hpd_init(dev_priv);
4520 drm_atomic_state_put(state);
4522 drm_modeset_drop_locks(ctx);
4523 drm_modeset_acquire_fini(ctx);
4524 mutex_unlock(&dev->mode_config.mutex);
4526 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4529 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4531 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4532 enum pipe pipe = crtc->pipe;
4535 tmp = I915_READ(PIPE_CHICKEN(pipe));
4538 * Display WA #1153: icl
4539 * enable hardware to bypass the alpha math
4540 * and rounding for per-pixel values 00 and 0xff
4542 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4544 * Display WA # 1605353570: icl
4545 * Set the pixel rounding bit to 1 for allowing
4546 * passthrough of Frame buffer pixels unmodified
4549 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4550 I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4553 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
4555 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4556 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4557 u32 trans_ddi_func_ctl2_val;
4561 * Configure the master select and enable Transcoder Port Sync for
4562 * Slave CRTCs transcoder.
4564 if (crtc_state->master_transcoder == INVALID_TRANSCODER)
4567 if (crtc_state->master_transcoder == TRANSCODER_EDP)
4570 master_select = crtc_state->master_transcoder + 1;
4572 /* Set the master select bits for Tranascoder Port Sync */
4573 trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
4574 PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
4575 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
4576 /* Enable Transcoder Port Sync */
4577 trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
4579 I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
4580 trans_ddi_func_ctl2_val);
4583 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
4585 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4586 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4588 u32 trans_ddi_func_ctl2_val;
4590 if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
4593 DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
4594 transcoder_name(old_crtc_state->cpu_transcoder));
4596 reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
4597 trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
4598 PORT_SYNC_MODE_MASTER_SELECT_MASK);
4599 I915_WRITE(reg, trans_ddi_func_ctl2_val);
4602 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4604 struct drm_device *dev = crtc->base.dev;
4605 struct drm_i915_private *dev_priv = to_i915(dev);
4606 enum pipe pipe = crtc->pipe;
4610 /* enable normal train */
4611 reg = FDI_TX_CTL(pipe);
4612 temp = I915_READ(reg);
4613 if (IS_IVYBRIDGE(dev_priv)) {
4614 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4615 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4617 temp &= ~FDI_LINK_TRAIN_NONE;
4618 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4620 I915_WRITE(reg, temp);
4622 reg = FDI_RX_CTL(pipe);
4623 temp = I915_READ(reg);
4624 if (HAS_PCH_CPT(dev_priv)) {
4625 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4626 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4628 temp &= ~FDI_LINK_TRAIN_NONE;
4629 temp |= FDI_LINK_TRAIN_NONE;
4631 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4633 /* wait one idle pattern time */
4637 /* IVB wants error correction enabled */
4638 if (IS_IVYBRIDGE(dev_priv))
4639 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4640 FDI_FE_ERRC_ENABLE);
4643 /* The FDI link training functions for ILK/Ibexpeak. */
4644 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4645 const struct intel_crtc_state *crtc_state)
4647 struct drm_device *dev = crtc->base.dev;
4648 struct drm_i915_private *dev_priv = to_i915(dev);
4649 enum pipe pipe = crtc->pipe;
4653 /* FDI needs bits from pipe first */
4654 assert_pipe_enabled(dev_priv, pipe);
4656 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4658 reg = FDI_RX_IMR(pipe);
4659 temp = I915_READ(reg);
4660 temp &= ~FDI_RX_SYMBOL_LOCK;
4661 temp &= ~FDI_RX_BIT_LOCK;
4662 I915_WRITE(reg, temp);
4666 /* enable CPU FDI TX and PCH FDI RX */
4667 reg = FDI_TX_CTL(pipe);
4668 temp = I915_READ(reg);
4669 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4670 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4671 temp &= ~FDI_LINK_TRAIN_NONE;
4672 temp |= FDI_LINK_TRAIN_PATTERN_1;
4673 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4675 reg = FDI_RX_CTL(pipe);
4676 temp = I915_READ(reg);
4677 temp &= ~FDI_LINK_TRAIN_NONE;
4678 temp |= FDI_LINK_TRAIN_PATTERN_1;
4679 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4684 /* Ironlake workaround, enable clock pointer after FDI enable*/
4685 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4686 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4687 FDI_RX_PHASE_SYNC_POINTER_EN);
4689 reg = FDI_RX_IIR(pipe);
4690 for (tries = 0; tries < 5; tries++) {
4691 temp = I915_READ(reg);
4692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4694 if ((temp & FDI_RX_BIT_LOCK)) {
4695 DRM_DEBUG_KMS("FDI train 1 done.\n");
4696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4701 DRM_ERROR("FDI train 1 fail!\n");
4704 reg = FDI_TX_CTL(pipe);
4705 temp = I915_READ(reg);
4706 temp &= ~FDI_LINK_TRAIN_NONE;
4707 temp |= FDI_LINK_TRAIN_PATTERN_2;
4708 I915_WRITE(reg, temp);
4710 reg = FDI_RX_CTL(pipe);
4711 temp = I915_READ(reg);
4712 temp &= ~FDI_LINK_TRAIN_NONE;
4713 temp |= FDI_LINK_TRAIN_PATTERN_2;
4714 I915_WRITE(reg, temp);
4719 reg = FDI_RX_IIR(pipe);
4720 for (tries = 0; tries < 5; tries++) {
4721 temp = I915_READ(reg);
4722 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4724 if (temp & FDI_RX_SYMBOL_LOCK) {
4725 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4726 DRM_DEBUG_KMS("FDI train 2 done.\n");
4731 DRM_ERROR("FDI train 2 fail!\n");
4733 DRM_DEBUG_KMS("FDI train done\n");
4737 static const int snb_b_fdi_train_param[] = {
4738 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4739 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4740 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4741 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4744 /* The FDI link training functions for SNB/Cougarpoint. */
4745 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4746 const struct intel_crtc_state *crtc_state)
4748 struct drm_device *dev = crtc->base.dev;
4749 struct drm_i915_private *dev_priv = to_i915(dev);
4750 enum pipe pipe = crtc->pipe;
4754 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4756 reg = FDI_RX_IMR(pipe);
4757 temp = I915_READ(reg);
4758 temp &= ~FDI_RX_SYMBOL_LOCK;
4759 temp &= ~FDI_RX_BIT_LOCK;
4760 I915_WRITE(reg, temp);
4765 /* enable CPU FDI TX and PCH FDI RX */
4766 reg = FDI_TX_CTL(pipe);
4767 temp = I915_READ(reg);
4768 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4769 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4770 temp &= ~FDI_LINK_TRAIN_NONE;
4771 temp |= FDI_LINK_TRAIN_PATTERN_1;
4772 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4774 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4775 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4777 I915_WRITE(FDI_RX_MISC(pipe),
4778 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4780 reg = FDI_RX_CTL(pipe);
4781 temp = I915_READ(reg);
4782 if (HAS_PCH_CPT(dev_priv)) {
4783 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4784 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4786 temp &= ~FDI_LINK_TRAIN_NONE;
4787 temp |= FDI_LINK_TRAIN_PATTERN_1;
4789 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4794 for (i = 0; i < 4; i++) {
4795 reg = FDI_TX_CTL(pipe);
4796 temp = I915_READ(reg);
4797 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4798 temp |= snb_b_fdi_train_param[i];
4799 I915_WRITE(reg, temp);
4804 for (retry = 0; retry < 5; retry++) {
4805 reg = FDI_RX_IIR(pipe);
4806 temp = I915_READ(reg);
4807 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4808 if (temp & FDI_RX_BIT_LOCK) {
4809 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4810 DRM_DEBUG_KMS("FDI train 1 done.\n");
4819 DRM_ERROR("FDI train 1 fail!\n");
4822 reg = FDI_TX_CTL(pipe);
4823 temp = I915_READ(reg);
4824 temp &= ~FDI_LINK_TRAIN_NONE;
4825 temp |= FDI_LINK_TRAIN_PATTERN_2;
4826 if (IS_GEN(dev_priv, 6)) {
4827 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4829 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4831 I915_WRITE(reg, temp);
4833 reg = FDI_RX_CTL(pipe);
4834 temp = I915_READ(reg);
4835 if (HAS_PCH_CPT(dev_priv)) {
4836 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4837 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4839 temp &= ~FDI_LINK_TRAIN_NONE;
4840 temp |= FDI_LINK_TRAIN_PATTERN_2;
4842 I915_WRITE(reg, temp);
4847 for (i = 0; i < 4; i++) {
4848 reg = FDI_TX_CTL(pipe);
4849 temp = I915_READ(reg);
4850 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4851 temp |= snb_b_fdi_train_param[i];
4852 I915_WRITE(reg, temp);
4857 for (retry = 0; retry < 5; retry++) {
4858 reg = FDI_RX_IIR(pipe);
4859 temp = I915_READ(reg);
4860 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4861 if (temp & FDI_RX_SYMBOL_LOCK) {
4862 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4863 DRM_DEBUG_KMS("FDI train 2 done.\n");
4872 DRM_ERROR("FDI train 2 fail!\n");
4874 DRM_DEBUG_KMS("FDI train done.\n");
4877 /* Manual link training for Ivy Bridge A0 parts */
4878 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4879 const struct intel_crtc_state *crtc_state)
4881 struct drm_device *dev = crtc->base.dev;
4882 struct drm_i915_private *dev_priv = to_i915(dev);
4883 enum pipe pipe = crtc->pipe;
4887 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4889 reg = FDI_RX_IMR(pipe);
4890 temp = I915_READ(reg);
4891 temp &= ~FDI_RX_SYMBOL_LOCK;
4892 temp &= ~FDI_RX_BIT_LOCK;
4893 I915_WRITE(reg, temp);
4898 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4899 I915_READ(FDI_RX_IIR(pipe)));
4901 /* Try each vswing and preemphasis setting twice before moving on */
4902 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4903 /* disable first in case we need to retry */
4904 reg = FDI_TX_CTL(pipe);
4905 temp = I915_READ(reg);
4906 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4907 temp &= ~FDI_TX_ENABLE;
4908 I915_WRITE(reg, temp);
4910 reg = FDI_RX_CTL(pipe);
4911 temp = I915_READ(reg);
4912 temp &= ~FDI_LINK_TRAIN_AUTO;
4913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4914 temp &= ~FDI_RX_ENABLE;
4915 I915_WRITE(reg, temp);
4917 /* enable CPU FDI TX and PCH FDI RX */
4918 reg = FDI_TX_CTL(pipe);
4919 temp = I915_READ(reg);
4920 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4921 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4922 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4923 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4924 temp |= snb_b_fdi_train_param[j/2];
4925 temp |= FDI_COMPOSITE_SYNC;
4926 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4928 I915_WRITE(FDI_RX_MISC(pipe),
4929 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4931 reg = FDI_RX_CTL(pipe);
4932 temp = I915_READ(reg);
4933 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4934 temp |= FDI_COMPOSITE_SYNC;
4935 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4938 udelay(1); /* should be 0.5us */
4940 for (i = 0; i < 4; i++) {
4941 reg = FDI_RX_IIR(pipe);
4942 temp = I915_READ(reg);
4943 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4945 if (temp & FDI_RX_BIT_LOCK ||
4946 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4947 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4948 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4952 udelay(1); /* should be 0.5us */
4955 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4960 reg = FDI_TX_CTL(pipe);
4961 temp = I915_READ(reg);
4962 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4963 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4964 I915_WRITE(reg, temp);
4966 reg = FDI_RX_CTL(pipe);
4967 temp = I915_READ(reg);
4968 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4969 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4970 I915_WRITE(reg, temp);
4973 udelay(2); /* should be 1.5us */
4975 for (i = 0; i < 4; i++) {
4976 reg = FDI_RX_IIR(pipe);
4977 temp = I915_READ(reg);
4978 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4980 if (temp & FDI_RX_SYMBOL_LOCK ||
4981 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4982 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4983 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4987 udelay(2); /* should be 1.5us */
4990 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4994 DRM_DEBUG_KMS("FDI train done.\n");
4997 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5000 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5001 enum pipe pipe = intel_crtc->pipe;
5005 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5006 reg = FDI_RX_CTL(pipe);
5007 temp = I915_READ(reg);
5008 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5009 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5010 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5011 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
5016 /* Switch from Rawclk to PCDclk */
5017 temp = I915_READ(reg);
5018 I915_WRITE(reg, temp | FDI_PCDCLK);
5023 /* Enable CPU FDI TX PLL, always on for Ironlake */
5024 reg = FDI_TX_CTL(pipe);
5025 temp = I915_READ(reg);
5026 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5027 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5034 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
5036 struct drm_device *dev = intel_crtc->base.dev;
5037 struct drm_i915_private *dev_priv = to_i915(dev);
5038 enum pipe pipe = intel_crtc->pipe;
5042 /* Switch from PCDclk to Rawclk */
5043 reg = FDI_RX_CTL(pipe);
5044 temp = I915_READ(reg);
5045 I915_WRITE(reg, temp & ~FDI_PCDCLK);
5047 /* Disable CPU FDI TX PLL */
5048 reg = FDI_TX_CTL(pipe);
5049 temp = I915_READ(reg);
5050 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
5055 reg = FDI_RX_CTL(pipe);
5056 temp = I915_READ(reg);
5057 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
5059 /* Wait for the clocks to turn off. */
5064 static void ironlake_fdi_disable(struct intel_crtc *crtc)
5066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5067 enum pipe pipe = crtc->pipe;
5071 /* disable CPU FDI tx and PCH FDI rx */
5072 reg = FDI_TX_CTL(pipe);
5073 temp = I915_READ(reg);
5074 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
5077 reg = FDI_RX_CTL(pipe);
5078 temp = I915_READ(reg);
5079 temp &= ~(0x7 << 16);
5080 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5081 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
5086 /* Ironlake workaround, disable clock pointer after downing FDI */
5087 if (HAS_PCH_IBX(dev_priv))
5088 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
5090 /* still set train pattern 1 */
5091 reg = FDI_TX_CTL(pipe);
5092 temp = I915_READ(reg);
5093 temp &= ~FDI_LINK_TRAIN_NONE;
5094 temp |= FDI_LINK_TRAIN_PATTERN_1;
5095 I915_WRITE(reg, temp);
5097 reg = FDI_RX_CTL(pipe);
5098 temp = I915_READ(reg);
5099 if (HAS_PCH_CPT(dev_priv)) {
5100 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5101 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5103 temp &= ~FDI_LINK_TRAIN_NONE;
5104 temp |= FDI_LINK_TRAIN_PATTERN_1;
5106 /* BPC in FDI rx is consistent with that in PIPECONF */
5107 temp &= ~(0x07 << 16);
5108 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5109 I915_WRITE(reg, temp);
5115 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5117 struct drm_crtc *crtc;
5120 drm_for_each_crtc(crtc, &dev_priv->drm) {
5121 struct drm_crtc_commit *commit;
5122 spin_lock(&crtc->commit_lock);
5123 commit = list_first_entry_or_null(&crtc->commit_list,
5124 struct drm_crtc_commit, commit_entry);
5125 cleanup_done = commit ?
5126 try_wait_for_completion(&commit->cleanup_done) : true;
5127 spin_unlock(&crtc->commit_lock);
5132 drm_crtc_wait_one_vblank(crtc);
5140 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5144 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
5146 mutex_lock(&dev_priv->sb_lock);
5148 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5149 temp |= SBI_SSCCTL_DISABLE;
5150 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5152 mutex_unlock(&dev_priv->sb_lock);
5155 /* Program iCLKIP clock to the desired frequency */
5156 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5158 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5159 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5160 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5161 u32 divsel, phaseinc, auxdiv, phasedir = 0;
5164 lpt_disable_iclkip(dev_priv);
5166 /* The iCLK virtual clock root frequency is in MHz,
5167 * but the adjusted_mode->crtc_clock in in KHz. To get the
5168 * divisors, it is necessary to divide one by another, so we
5169 * convert the virtual clock precision to KHz here for higher
5172 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5173 u32 iclk_virtual_root_freq = 172800 * 1000;
5174 u32 iclk_pi_range = 64;
5175 u32 desired_divisor;
5177 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5179 divsel = (desired_divisor / iclk_pi_range) - 2;
5180 phaseinc = desired_divisor % iclk_pi_range;
5183 * Near 20MHz is a corner case which is
5184 * out of range for the 7-bit divisor
5190 /* This should not happen with any sane values */
5191 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5192 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5193 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5194 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5196 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5203 mutex_lock(&dev_priv->sb_lock);
5205 /* Program SSCDIVINTPHASE6 */
5206 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5207 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5208 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5209 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5210 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5211 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5212 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5213 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5215 /* Program SSCAUXDIV */
5216 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5217 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5218 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5219 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5221 /* Enable modulator and associated divider */
5222 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5223 temp &= ~SBI_SSCCTL_DISABLE;
5224 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5226 mutex_unlock(&dev_priv->sb_lock);
5228 /* Wait for initialization time */
5231 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5234 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5236 u32 divsel, phaseinc, auxdiv;
5237 u32 iclk_virtual_root_freq = 172800 * 1000;
5238 u32 iclk_pi_range = 64;
5239 u32 desired_divisor;
5242 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5245 mutex_lock(&dev_priv->sb_lock);
5247 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5248 if (temp & SBI_SSCCTL_DISABLE) {
5249 mutex_unlock(&dev_priv->sb_lock);
5253 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5254 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5255 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5256 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5257 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5259 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5260 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5261 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5263 mutex_unlock(&dev_priv->sb_lock);
5265 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5267 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5268 desired_divisor << auxdiv);
5271 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5272 enum pipe pch_transcoder)
5274 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5275 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5276 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5278 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5279 I915_READ(HTOTAL(cpu_transcoder)));
5280 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5281 I915_READ(HBLANK(cpu_transcoder)));
5282 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5283 I915_READ(HSYNC(cpu_transcoder)));
5285 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5286 I915_READ(VTOTAL(cpu_transcoder)));
5287 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5288 I915_READ(VBLANK(cpu_transcoder)));
5289 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5290 I915_READ(VSYNC(cpu_transcoder)));
5291 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5292 I915_READ(VSYNCSHIFT(cpu_transcoder)));
5295 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5299 temp = I915_READ(SOUTH_CHICKEN1);
5300 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5303 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5304 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5306 temp &= ~FDI_BC_BIFURCATION_SELECT;
5308 temp |= FDI_BC_BIFURCATION_SELECT;
5310 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5311 I915_WRITE(SOUTH_CHICKEN1, temp);
5312 POSTING_READ(SOUTH_CHICKEN1);
5315 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5317 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5318 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5320 switch (crtc->pipe) {
5324 if (crtc_state->fdi_lanes > 2)
5325 cpt_set_fdi_bc_bifurcation(dev_priv, false);
5327 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5331 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5340 * Finds the encoder associated with the given CRTC. This can only be
5341 * used when we know that the CRTC isn't feeding multiple encoders!
5343 static struct intel_encoder *
5344 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5345 const struct intel_crtc_state *crtc_state)
5347 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5348 const struct drm_connector_state *connector_state;
5349 const struct drm_connector *connector;
5350 struct intel_encoder *encoder = NULL;
5351 int num_encoders = 0;
5354 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5355 if (connector_state->crtc != &crtc->base)
5358 encoder = to_intel_encoder(connector_state->best_encoder);
5362 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5363 num_encoders, pipe_name(crtc->pipe));
5369 * Enable PCH resources required for PCH ports:
5371 * - FDI training & RX/TX
5372 * - update transcoder timings
5373 * - DP transcoding bits
5376 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5377 const struct intel_crtc_state *crtc_state)
5379 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5380 struct drm_device *dev = crtc->base.dev;
5381 struct drm_i915_private *dev_priv = to_i915(dev);
5382 enum pipe pipe = crtc->pipe;
5385 assert_pch_transcoder_disabled(dev_priv, pipe);
5387 if (IS_IVYBRIDGE(dev_priv))
5388 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5390 /* Write the TU size bits before fdi link training, so that error
5391 * detection works. */
5392 I915_WRITE(FDI_RX_TUSIZE1(pipe),
5393 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5395 /* For PCH output, training FDI link */
5396 dev_priv->display.fdi_link_train(crtc, crtc_state);
5398 /* We need to program the right clock selection before writing the pixel
5399 * mutliplier into the DPLL. */
5400 if (HAS_PCH_CPT(dev_priv)) {
5403 temp = I915_READ(PCH_DPLL_SEL);
5404 temp |= TRANS_DPLL_ENABLE(pipe);
5405 sel = TRANS_DPLLB_SEL(pipe);
5406 if (crtc_state->shared_dpll ==
5407 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5411 I915_WRITE(PCH_DPLL_SEL, temp);
5414 /* XXX: pch pll's can be enabled any time before we enable the PCH
5415 * transcoder, and we actually should do this to not upset any PCH
5416 * transcoder that already use the clock when we share it.
5418 * Note that enable_shared_dpll tries to do the right thing, but
5419 * get_shared_dpll unconditionally resets the pll - we need that to have
5420 * the right LVDS enable sequence. */
5421 intel_enable_shared_dpll(crtc_state);
5423 /* set transcoder timing, panel must allow it */
5424 assert_panel_unlocked(dev_priv, pipe);
5425 ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5427 intel_fdi_normal_train(crtc);
5429 /* For PCH DP, enable TRANS_DP_CTL */
5430 if (HAS_PCH_CPT(dev_priv) &&
5431 intel_crtc_has_dp_encoder(crtc_state)) {
5432 const struct drm_display_mode *adjusted_mode =
5433 &crtc_state->hw.adjusted_mode;
5434 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5435 i915_reg_t reg = TRANS_DP_CTL(pipe);
5438 temp = I915_READ(reg);
5439 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5440 TRANS_DP_SYNC_MASK |
5442 temp |= TRANS_DP_OUTPUT_ENABLE;
5443 temp |= bpc << 9; /* same format but at 11:9 */
5445 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5446 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5447 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5448 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5450 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5451 WARN_ON(port < PORT_B || port > PORT_D);
5452 temp |= TRANS_DP_PORT_SEL(port);
5454 I915_WRITE(reg, temp);
5457 ironlake_enable_pch_transcoder(crtc_state);
5460 static void lpt_pch_enable(const struct intel_atomic_state *state,
5461 const struct intel_crtc_state *crtc_state)
5463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5465 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5467 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5469 lpt_program_iclkip(crtc_state);
5471 /* Set transcoder timing. */
5472 ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5474 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5477 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5480 i915_reg_t dslreg = PIPEDSL(pipe);
5483 temp = I915_READ(dslreg);
5485 if (wait_for(I915_READ(dslreg) != temp, 5)) {
5486 if (wait_for(I915_READ(dslreg) != temp, 5))
5487 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5492 * The hardware phase 0.0 refers to the center of the pixel.
5493 * We want to start from the top/left edge which is phase
5494 * -0.5. That matches how the hardware calculates the scaling
5495 * factors (from top-left of the first pixel to bottom-right
5496 * of the last pixel, as opposed to the pixel centers).
5498 * For 4:2:0 subsampled chroma planes we obviously have to
5499 * adjust that so that the chroma sample position lands in
5502 * Note that for packed YCbCr 4:2:2 formats there is no way to
5503 * control chroma siting. The hardware simply replicates the
5504 * chroma samples for both of the luma samples, and thus we don't
5505 * actually get the expected MPEG2 chroma siting convention :(
5506 * The same behaviour is observed on pre-SKL platforms as well.
5508 * Theory behind the formula (note that we ignore sub-pixel
5509 * source coordinates):
5510 * s = source sample position
5511 * d = destination sample position
5516 * | | 1.5 (initial phase)
5524 * | -0.375 (initial phase)
5531 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5533 int phase = -0x8000;
5537 phase += (sub - 1) * 0x8000 / sub;
5539 phase += scale / (2 * sub);
5542 * Hardware initial phase limited to [-0.5:1.5].
5543 * Since the max hardware scale factor is 3.0, we
5544 * should never actually excdeed 1.0 here.
5546 WARN_ON(phase < -0x8000 || phase > 0x18000);
5549 phase = 0x10000 + phase;
5551 trip = PS_PHASE_TRIP;
5553 return ((phase >> 2) & PS_PHASE_MASK) | trip;
5556 #define SKL_MIN_SRC_W 8
5557 #define SKL_MAX_SRC_W 4096
5558 #define SKL_MIN_SRC_H 8
5559 #define SKL_MAX_SRC_H 4096
5560 #define SKL_MIN_DST_W 8
5561 #define SKL_MAX_DST_W 4096
5562 #define SKL_MIN_DST_H 8
5563 #define SKL_MAX_DST_H 4096
5564 #define ICL_MAX_SRC_W 5120
5565 #define ICL_MAX_SRC_H 4096
5566 #define ICL_MAX_DST_W 5120
5567 #define ICL_MAX_DST_H 4096
5568 #define SKL_MIN_YUV_420_SRC_W 16
5569 #define SKL_MIN_YUV_420_SRC_H 16
5572 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5573 unsigned int scaler_user, int *scaler_id,
5574 int src_w, int src_h, int dst_w, int dst_h,
5575 const struct drm_format_info *format, bool need_scaler)
5577 struct intel_crtc_scaler_state *scaler_state =
5578 &crtc_state->scaler_state;
5579 struct intel_crtc *intel_crtc =
5580 to_intel_crtc(crtc_state->uapi.crtc);
5581 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5582 const struct drm_display_mode *adjusted_mode =
5583 &crtc_state->hw.adjusted_mode;
5586 * Src coordinates are already rotated by 270 degrees for
5587 * the 90/270 degree plane rotation cases (to match the
5588 * GTT mapping), hence no need to account for rotation here.
5590 if (src_w != dst_w || src_h != dst_h)
5594 * Scaling/fitting not supported in IF-ID mode in GEN9+
5595 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5596 * Once NV12 is enabled, handle it here while allocating scaler
5599 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
5600 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5601 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5606 * if plane is being disabled or scaler is no more required or force detach
5607 * - free scaler binded to this plane/crtc
5608 * - in order to do this, update crtc->scaler_usage
5610 * Here scaler state in crtc_state is set free so that
5611 * scaler can be assigned to other user. Actual register
5612 * update to free the scaler is done in plane/panel-fit programming.
5613 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5615 if (force_detach || !need_scaler) {
5616 if (*scaler_id >= 0) {
5617 scaler_state->scaler_users &= ~(1 << scaler_user);
5618 scaler_state->scalers[*scaler_id].in_use = 0;
5620 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5621 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5622 intel_crtc->pipe, scaler_user, *scaler_id,
5623 scaler_state->scaler_users);
5629 if (format && drm_format_info_is_yuv_semiplanar(format) &&
5630 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5631 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5636 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5637 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5638 (INTEL_GEN(dev_priv) >= 11 &&
5639 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5640 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5641 (INTEL_GEN(dev_priv) < 11 &&
5642 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5643 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5644 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5645 "size is out of scaler range\n",
5646 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5650 /* mark this plane as a scaler user in crtc_state */
5651 scaler_state->scaler_users |= (1 << scaler_user);
5652 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5653 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5654 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5655 scaler_state->scaler_users);
5661 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5663 * @state: crtc's scaler state
5666 * 0 - scaler_usage updated successfully
5667 * error - requested scaling cannot be supported or other error condition
5669 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5671 const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
5672 bool need_scaler = false;
5674 if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5677 return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
5678 &state->scaler_state.scaler_id,
5679 state->pipe_src_w, state->pipe_src_h,
5680 adjusted_mode->crtc_hdisplay,
5681 adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5685 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5686 * @crtc_state: crtc's scaler state
5687 * @plane_state: atomic plane state to update
5690 * 0 - scaler_usage updated successfully
5691 * error - requested scaling cannot be supported or other error condition
5693 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5694 struct intel_plane_state *plane_state)
5696 struct intel_plane *intel_plane =
5697 to_intel_plane(plane_state->uapi.plane);
5698 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5699 struct drm_framebuffer *fb = plane_state->hw.fb;
5701 bool force_detach = !fb || !plane_state->uapi.visible;
5702 bool need_scaler = false;
5704 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5705 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5706 fb && drm_format_info_is_yuv_semiplanar(fb->format))
5709 ret = skl_update_scaler(crtc_state, force_detach,
5710 drm_plane_index(&intel_plane->base),
5711 &plane_state->scaler_id,
5712 drm_rect_width(&plane_state->uapi.src) >> 16,
5713 drm_rect_height(&plane_state->uapi.src) >> 16,
5714 drm_rect_width(&plane_state->uapi.dst),
5715 drm_rect_height(&plane_state->uapi.dst),
5716 fb ? fb->format : NULL, need_scaler);
5718 if (ret || plane_state->scaler_id < 0)
5721 /* check colorkey */
5722 if (plane_state->ckey.flags) {
5723 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5724 intel_plane->base.base.id,
5725 intel_plane->base.name);
5729 /* Check src format */
5730 switch (fb->format->format) {
5731 case DRM_FORMAT_RGB565:
5732 case DRM_FORMAT_XBGR8888:
5733 case DRM_FORMAT_XRGB8888:
5734 case DRM_FORMAT_ABGR8888:
5735 case DRM_FORMAT_ARGB8888:
5736 case DRM_FORMAT_XRGB2101010:
5737 case DRM_FORMAT_XBGR2101010:
5738 case DRM_FORMAT_ARGB2101010:
5739 case DRM_FORMAT_ABGR2101010:
5740 case DRM_FORMAT_YUYV:
5741 case DRM_FORMAT_YVYU:
5742 case DRM_FORMAT_UYVY:
5743 case DRM_FORMAT_VYUY:
5744 case DRM_FORMAT_NV12:
5745 case DRM_FORMAT_P010:
5746 case DRM_FORMAT_P012:
5747 case DRM_FORMAT_P016:
5748 case DRM_FORMAT_Y210:
5749 case DRM_FORMAT_Y212:
5750 case DRM_FORMAT_Y216:
5751 case DRM_FORMAT_XVYU2101010:
5752 case DRM_FORMAT_XVYU12_16161616:
5753 case DRM_FORMAT_XVYU16161616:
5755 case DRM_FORMAT_XBGR16161616F:
5756 case DRM_FORMAT_ABGR16161616F:
5757 case DRM_FORMAT_XRGB16161616F:
5758 case DRM_FORMAT_ARGB16161616F:
5759 if (INTEL_GEN(dev_priv) >= 11)
5763 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5764 intel_plane->base.base.id, intel_plane->base.name,
5765 fb->base.id, fb->format->format);
5772 static void skylake_scaler_disable(struct intel_crtc *crtc)
5776 for (i = 0; i < crtc->num_scalers; i++)
5777 skl_detach_scaler(crtc, i);
5780 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5782 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5783 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5784 enum pipe pipe = crtc->pipe;
5785 const struct intel_crtc_scaler_state *scaler_state =
5786 &crtc_state->scaler_state;
5788 if (crtc_state->pch_pfit.enabled) {
5789 u16 uv_rgb_hphase, uv_rgb_vphase;
5790 int pfit_w, pfit_h, hscale, vscale;
5793 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5796 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5797 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5799 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5800 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5802 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5803 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5805 id = scaler_state->scaler_id;
5806 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5807 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5808 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5809 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5810 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5811 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5812 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5813 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5817 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5819 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5821 enum pipe pipe = crtc->pipe;
5823 if (crtc_state->pch_pfit.enabled) {
5824 /* Force use of hard-coded filter coefficients
5825 * as some pre-programmed values are broken,
5828 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5829 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5830 PF_PIPE_SEL_IVB(pipe));
5832 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5833 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5834 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5838 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5841 struct drm_device *dev = crtc->base.dev;
5842 struct drm_i915_private *dev_priv = to_i915(dev);
5844 if (!crtc_state->ips_enabled)
5848 * We can only enable IPS after we enable a plane and wait for a vblank
5849 * This function is called from post_plane_update, which is run after
5852 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5854 if (IS_BROADWELL(dev_priv)) {
5855 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5856 IPS_ENABLE | IPS_PCODE_CONTROL));
5857 /* Quoting Art Runyan: "its not safe to expect any particular
5858 * value in IPS_CTL bit 31 after enabling IPS through the
5859 * mailbox." Moreover, the mailbox may return a bogus state,
5860 * so we need to just enable it and continue on.
5863 I915_WRITE(IPS_CTL, IPS_ENABLE);
5864 /* The bit only becomes 1 in the next vblank, so this wait here
5865 * is essentially intel_wait_for_vblank. If we don't have this
5866 * and don't wait for vblanks until the end of crtc_enable, then
5867 * the HW state readout code will complain that the expected
5868 * IPS_CTL value is not the one we read. */
5869 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5870 DRM_ERROR("Timed out waiting for IPS enable\n");
5874 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5876 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5877 struct drm_device *dev = crtc->base.dev;
5878 struct drm_i915_private *dev_priv = to_i915(dev);
5880 if (!crtc_state->ips_enabled)
5883 if (IS_BROADWELL(dev_priv)) {
5884 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5886 * Wait for PCODE to finish disabling IPS. The BSpec specified
5887 * 42ms timeout value leads to occasional timeouts so use 100ms
5890 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5891 DRM_ERROR("Timed out waiting for IPS disable\n");
5893 I915_WRITE(IPS_CTL, 0);
5894 POSTING_READ(IPS_CTL);
5897 /* We need to wait for a vblank before we can disable the plane. */
5898 intel_wait_for_vblank(dev_priv, crtc->pipe);
5901 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5903 if (intel_crtc->overlay)
5904 (void) intel_overlay_switch_off(intel_crtc->overlay);
5906 /* Let userspace switch the overlay on again. In most cases userspace
5907 * has to recompute where to put it anyway.
5912 * intel_post_enable_primary - Perform operations after enabling primary plane
5913 * @crtc: the CRTC whose primary plane was just enabled
5914 * @new_crtc_state: the enabling state
5916 * Performs potentially sleeping operations that must be done after the primary
5917 * plane is enabled, such as updating FBC and IPS. Note that this may be
5918 * called due to an explicit primary plane update, or due to an implicit
5919 * re-enable that is caused when a sprite plane is updated to no longer
5920 * completely hide the primary plane.
5923 intel_post_enable_primary(struct drm_crtc *crtc,
5924 const struct intel_crtc_state *new_crtc_state)
5926 struct drm_device *dev = crtc->dev;
5927 struct drm_i915_private *dev_priv = to_i915(dev);
5928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5929 enum pipe pipe = intel_crtc->pipe;
5932 * Gen2 reports pipe underruns whenever all planes are disabled.
5933 * So don't enable underrun reporting before at least some planes
5935 * FIXME: Need to fix the logic to work when we turn off all planes
5936 * but leave the pipe running.
5938 if (IS_GEN(dev_priv, 2))
5939 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5941 /* Underruns don't always raise interrupts, so check manually. */
5942 intel_check_cpu_fifo_underruns(dev_priv);
5943 intel_check_pch_fifo_underruns(dev_priv);
5946 /* FIXME get rid of this and use pre_plane_update */
5948 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5950 struct drm_device *dev = crtc->dev;
5951 struct drm_i915_private *dev_priv = to_i915(dev);
5952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5953 enum pipe pipe = intel_crtc->pipe;
5956 * Gen2 reports pipe underruns whenever all planes are disabled.
5957 * So disable underrun reporting before all the planes get disabled.
5959 if (IS_GEN(dev_priv, 2))
5960 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5962 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5965 * Vblank time updates from the shadow to live plane control register
5966 * are blocked if the memory self-refresh mode is active at that
5967 * moment. So to make sure the plane gets truly disabled, disable
5968 * first the self-refresh mode. The self-refresh enable bit in turn
5969 * will be checked/applied by the HW only at the next frame start
5970 * event which is after the vblank start event, so we need to have a
5971 * wait-for-vblank between disabling the plane and the pipe.
5973 if (HAS_GMCH(dev_priv) &&
5974 intel_set_memory_cxsr(dev_priv, false))
5975 intel_wait_for_vblank(dev_priv, pipe);
5978 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5979 const struct intel_crtc_state *new_crtc_state)
5981 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5982 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5984 if (!old_crtc_state->ips_enabled)
5987 if (needs_modeset(new_crtc_state))
5991 * Workaround : Do not read or write the pipe palette/gamma data while
5992 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5994 * Disable IPS before we program the LUT.
5996 if (IS_HASWELL(dev_priv) &&
5997 (new_crtc_state->uapi.color_mgmt_changed ||
5998 new_crtc_state->update_pipe) &&
5999 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6002 return !new_crtc_state->ips_enabled;
6005 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6006 const struct intel_crtc_state *new_crtc_state)
6008 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6011 if (!new_crtc_state->ips_enabled)
6014 if (needs_modeset(new_crtc_state))
6018 * Workaround : Do not read or write the pipe palette/gamma data while
6019 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6021 * Re-enable IPS after the LUT has been programmed.
6023 if (IS_HASWELL(dev_priv) &&
6024 (new_crtc_state->uapi.color_mgmt_changed ||
6025 new_crtc_state->update_pipe) &&
6026 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6030 * We can't read out IPS on broadwell, assume the worst and
6031 * forcibly enable IPS on the first fastset.
6033 if (new_crtc_state->update_pipe &&
6034 old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
6037 return !old_crtc_state->ips_enabled;
6040 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6042 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6044 if (!crtc_state->nv12_planes)
6047 /* WA Display #0827: Gen9:all */
6048 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6054 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6056 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6058 /* Wa_2006604312:icl */
6059 if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
6065 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
6067 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6068 struct drm_device *dev = crtc->base.dev;
6069 struct drm_i915_private *dev_priv = to_i915(dev);
6070 struct drm_atomic_state *state = old_crtc_state->uapi.state;
6071 struct intel_crtc_state *pipe_config =
6072 intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
6074 struct drm_plane *primary = crtc->base.primary;
6075 struct drm_plane_state *old_primary_state =
6076 drm_atomic_get_old_plane_state(state, primary);
6078 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
6080 if (pipe_config->update_wm_post && pipe_config->hw.active)
6081 intel_update_watermarks(crtc);
6083 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
6084 hsw_enable_ips(pipe_config);
6086 if (old_primary_state) {
6087 struct drm_plane_state *new_primary_state =
6088 drm_atomic_get_new_plane_state(state, primary);
6090 intel_fbc_post_update(crtc);
6092 if (new_primary_state->visible &&
6093 (needs_modeset(pipe_config) ||
6094 !old_primary_state->visible))
6095 intel_post_enable_primary(&crtc->base, pipe_config);
6098 if (needs_nv12_wa(old_crtc_state) &&
6099 !needs_nv12_wa(pipe_config))
6100 skl_wa_827(dev_priv, crtc->pipe, false);
6102 if (needs_scalerclk_wa(old_crtc_state) &&
6103 !needs_scalerclk_wa(pipe_config))
6104 icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
6107 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
6108 struct intel_crtc_state *pipe_config)
6110 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6111 struct drm_device *dev = crtc->base.dev;
6112 struct drm_i915_private *dev_priv = to_i915(dev);
6113 struct drm_atomic_state *state = old_crtc_state->uapi.state;
6114 struct drm_plane *primary = crtc->base.primary;
6115 struct drm_plane_state *old_primary_state =
6116 drm_atomic_get_old_plane_state(state, primary);
6117 bool modeset = needs_modeset(pipe_config);
6118 struct intel_atomic_state *intel_state =
6119 to_intel_atomic_state(state);
6121 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
6122 hsw_disable_ips(old_crtc_state);
6124 if (old_primary_state) {
6125 struct intel_plane_state *new_primary_state =
6126 intel_atomic_get_new_plane_state(intel_state,
6127 to_intel_plane(primary));
6129 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
6131 * Gen2 reports pipe underruns whenever all planes are disabled.
6132 * So disable underrun reporting before all the planes get disabled.
6134 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
6135 (modeset || !new_primary_state->uapi.visible))
6136 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
6139 /* Display WA 827 */
6140 if (!needs_nv12_wa(old_crtc_state) &&
6141 needs_nv12_wa(pipe_config))
6142 skl_wa_827(dev_priv, crtc->pipe, true);
6144 /* Wa_2006604312:icl */
6145 if (!needs_scalerclk_wa(old_crtc_state) &&
6146 needs_scalerclk_wa(pipe_config))
6147 icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
6150 * Vblank time updates from the shadow to live plane control register
6151 * are blocked if the memory self-refresh mode is active at that
6152 * moment. So to make sure the plane gets truly disabled, disable
6153 * first the self-refresh mode. The self-refresh enable bit in turn
6154 * will be checked/applied by the HW only at the next frame start
6155 * event which is after the vblank start event, so we need to have a
6156 * wait-for-vblank between disabling the plane and the pipe.
6158 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6159 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6160 intel_wait_for_vblank(dev_priv, crtc->pipe);
6163 * IVB workaround: must disable low power watermarks for at least
6164 * one frame before enabling scaling. LP watermarks can be re-enabled
6165 * when scaling is disabled.
6167 * WaCxSRDisabledForSpriteScaling:ivb
6169 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
6170 old_crtc_state->hw.active)
6171 intel_wait_for_vblank(dev_priv, crtc->pipe);
6174 * If we're doing a modeset, we're done. No need to do any pre-vblank
6175 * watermark programming here.
6177 if (needs_modeset(pipe_config))
6181 * For platforms that support atomic watermarks, program the
6182 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
6183 * will be the intermediate values that are safe for both pre- and
6184 * post- vblank; when vblank happens, the 'active' values will be set
6185 * to the final 'target' values and we'll do this again to get the
6186 * optimal watermarks. For gen9+ platforms, the values we program here
6187 * will be the final target values which will get automatically latched
6188 * at vblank time; no further programming will be necessary.
6190 * If a platform hasn't been transitioned to atomic watermarks yet,
6191 * we'll continue to update watermarks the old way, if flags tell
6194 if (dev_priv->display.initial_watermarks)
6195 dev_priv->display.initial_watermarks(intel_state, crtc);
6196 else if (pipe_config->update_wm_pre)
6197 intel_update_watermarks(crtc);
6200 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6201 struct intel_crtc *crtc)
6203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6204 const struct intel_crtc_state *new_crtc_state =
6205 intel_atomic_get_new_crtc_state(state, crtc);
6206 unsigned int update_mask = new_crtc_state->update_planes;
6207 const struct intel_plane_state *old_plane_state;
6208 struct intel_plane *plane;
6209 unsigned fb_bits = 0;
6212 intel_crtc_dpms_overlay_disable(crtc);
6214 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6215 if (crtc->pipe != plane->pipe ||
6216 !(update_mask & BIT(plane->id)))
6219 intel_disable_plane(plane, new_crtc_state);
6221 if (old_plane_state->uapi.visible)
6222 fb_bits |= plane->frontbuffer_bit;
6225 intel_frontbuffer_flip(dev_priv, fb_bits);
6229 * intel_connector_primary_encoder - get the primary encoder for a connector
6230 * @connector: connector for which to return the encoder
6232 * Returns the primary encoder for a connector. There is a 1:1 mapping from
6233 * all connectors to their encoder, except for DP-MST connectors which have
6234 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6235 * pointed to by as many DP-MST connectors as there are pipes.
6237 static struct intel_encoder *
6238 intel_connector_primary_encoder(struct intel_connector *connector)
6240 struct intel_encoder *encoder;
6242 if (connector->mst_port)
6243 return &dp_to_dig_port(connector->mst_port)->base;
6245 encoder = intel_attached_encoder(&connector->base);
6252 intel_connector_needs_modeset(struct intel_atomic_state *state,
6253 const struct drm_connector_state *old_conn_state,
6254 const struct drm_connector_state *new_conn_state)
6256 struct intel_crtc *old_crtc = old_conn_state->crtc ?
6257 to_intel_crtc(old_conn_state->crtc) : NULL;
6258 struct intel_crtc *new_crtc = new_conn_state->crtc ?
6259 to_intel_crtc(new_conn_state->crtc) : NULL;
6261 return new_crtc != old_crtc ||
6263 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6266 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6268 struct drm_connector_state *old_conn_state;
6269 struct drm_connector_state *new_conn_state;
6270 struct drm_connector *conn;
6273 for_each_oldnew_connector_in_state(&state->base, conn,
6274 old_conn_state, new_conn_state, i) {
6275 struct intel_encoder *encoder;
6276 struct intel_crtc *crtc;
6278 if (!intel_connector_needs_modeset(state,
6283 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6284 if (!encoder->update_prepare)
6287 crtc = new_conn_state->crtc ?
6288 to_intel_crtc(new_conn_state->crtc) : NULL;
6289 encoder->update_prepare(state, encoder, crtc);
6293 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6295 struct drm_connector_state *old_conn_state;
6296 struct drm_connector_state *new_conn_state;
6297 struct drm_connector *conn;
6300 for_each_oldnew_connector_in_state(&state->base, conn,
6301 old_conn_state, new_conn_state, i) {
6302 struct intel_encoder *encoder;
6303 struct intel_crtc *crtc;
6305 if (!intel_connector_needs_modeset(state,
6310 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6311 if (!encoder->update_complete)
6314 crtc = new_conn_state->crtc ?
6315 to_intel_crtc(new_conn_state->crtc) : NULL;
6316 encoder->update_complete(state, encoder, crtc);
6320 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6321 struct intel_crtc *crtc)
6323 const struct intel_crtc_state *crtc_state =
6324 intel_atomic_get_new_crtc_state(state, crtc);
6325 const struct drm_connector_state *conn_state;
6326 struct drm_connector *conn;
6329 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6330 struct intel_encoder *encoder =
6331 to_intel_encoder(conn_state->best_encoder);
6333 if (conn_state->crtc != &crtc->base)
6336 if (encoder->pre_pll_enable)
6337 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6341 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6342 struct intel_crtc *crtc)
6344 const struct intel_crtc_state *crtc_state =
6345 intel_atomic_get_new_crtc_state(state, crtc);
6346 const struct drm_connector_state *conn_state;
6347 struct drm_connector *conn;
6350 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6351 struct intel_encoder *encoder =
6352 to_intel_encoder(conn_state->best_encoder);
6354 if (conn_state->crtc != &crtc->base)
6357 if (encoder->pre_enable)
6358 encoder->pre_enable(encoder, crtc_state, conn_state);
6362 static void intel_encoders_enable(struct intel_atomic_state *state,
6363 struct intel_crtc *crtc)
6365 const struct intel_crtc_state *crtc_state =
6366 intel_atomic_get_new_crtc_state(state, crtc);
6367 const struct drm_connector_state *conn_state;
6368 struct drm_connector *conn;
6371 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6372 struct intel_encoder *encoder =
6373 to_intel_encoder(conn_state->best_encoder);
6375 if (conn_state->crtc != &crtc->base)
6378 if (encoder->enable)
6379 encoder->enable(encoder, crtc_state, conn_state);
6380 intel_opregion_notify_encoder(encoder, true);
6384 static void intel_encoders_disable(struct intel_atomic_state *state,
6385 struct intel_crtc *crtc)
6387 const struct intel_crtc_state *old_crtc_state =
6388 intel_atomic_get_old_crtc_state(state, crtc);
6389 const struct drm_connector_state *old_conn_state;
6390 struct drm_connector *conn;
6393 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6394 struct intel_encoder *encoder =
6395 to_intel_encoder(old_conn_state->best_encoder);
6397 if (old_conn_state->crtc != &crtc->base)
6400 intel_opregion_notify_encoder(encoder, false);
6401 if (encoder->disable)
6402 encoder->disable(encoder, old_crtc_state, old_conn_state);
6406 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6407 struct intel_crtc *crtc)
6409 const struct intel_crtc_state *old_crtc_state =
6410 intel_atomic_get_old_crtc_state(state, crtc);
6411 const struct drm_connector_state *old_conn_state;
6412 struct drm_connector *conn;
6415 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6416 struct intel_encoder *encoder =
6417 to_intel_encoder(old_conn_state->best_encoder);
6419 if (old_conn_state->crtc != &crtc->base)
6422 if (encoder->post_disable)
6423 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6427 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6428 struct intel_crtc *crtc)
6430 const struct intel_crtc_state *old_crtc_state =
6431 intel_atomic_get_old_crtc_state(state, crtc);
6432 const struct drm_connector_state *old_conn_state;
6433 struct drm_connector *conn;
6436 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6437 struct intel_encoder *encoder =
6438 to_intel_encoder(old_conn_state->best_encoder);
6440 if (old_conn_state->crtc != &crtc->base)
6443 if (encoder->post_pll_disable)
6444 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6448 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6449 struct intel_crtc *crtc)
6451 const struct intel_crtc_state *crtc_state =
6452 intel_atomic_get_new_crtc_state(state, crtc);
6453 const struct drm_connector_state *conn_state;
6454 struct drm_connector *conn;
6457 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6458 struct intel_encoder *encoder =
6459 to_intel_encoder(conn_state->best_encoder);
6461 if (conn_state->crtc != &crtc->base)
6464 if (encoder->update_pipe)
6465 encoder->update_pipe(encoder, crtc_state, conn_state);
6469 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6472 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6474 plane->disable_plane(plane, crtc_state);
6477 static void ironlake_crtc_enable(struct intel_atomic_state *state,
6478 struct intel_crtc *crtc)
6480 const struct intel_crtc_state *new_crtc_state =
6481 intel_atomic_get_new_crtc_state(state, crtc);
6482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6483 enum pipe pipe = crtc->pipe;
6485 if (WARN_ON(crtc->active))
6489 * Sometimes spurious CPU pipe underruns happen during FDI
6490 * training, at least with VGA+HDMI cloning. Suppress them.
6492 * On ILK we get an occasional spurious CPU pipe underruns
6493 * between eDP port A enable and vdd enable. Also PCH port
6494 * enable seems to result in the occasional CPU pipe underrun.
6496 * Spurious PCH underruns also occur during PCH enabling.
6498 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6499 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6501 if (new_crtc_state->has_pch_encoder)
6502 intel_prepare_shared_dpll(new_crtc_state);
6504 if (intel_crtc_has_dp_encoder(new_crtc_state))
6505 intel_dp_set_m_n(new_crtc_state, M1_N1);
6507 intel_set_pipe_timings(new_crtc_state);
6508 intel_set_pipe_src_size(new_crtc_state);
6510 if (new_crtc_state->has_pch_encoder)
6511 intel_cpu_transcoder_set_m_n(new_crtc_state,
6512 &new_crtc_state->fdi_m_n, NULL);
6514 ironlake_set_pipeconf(new_crtc_state);
6516 crtc->active = true;
6518 intel_encoders_pre_enable(state, crtc);
6520 if (new_crtc_state->has_pch_encoder) {
6521 /* Note: FDI PLL enabling _must_ be done before we enable the
6522 * cpu pipes, hence this is separate from all the other fdi/pch
6524 ironlake_fdi_pll_enable(new_crtc_state);
6526 assert_fdi_tx_disabled(dev_priv, pipe);
6527 assert_fdi_rx_disabled(dev_priv, pipe);
6530 ironlake_pfit_enable(new_crtc_state);
6533 * On ILK+ LUT must be loaded before the pipe is running but with
6536 intel_color_load_luts(new_crtc_state);
6537 intel_color_commit(new_crtc_state);
6538 /* update DSPCNTR to configure gamma for pipe bottom color */
6539 intel_disable_primary_plane(new_crtc_state);
6541 if (dev_priv->display.initial_watermarks)
6542 dev_priv->display.initial_watermarks(state, crtc);
6543 intel_enable_pipe(new_crtc_state);
6545 if (new_crtc_state->has_pch_encoder)
6546 ironlake_pch_enable(state, new_crtc_state);
6548 intel_crtc_vblank_on(new_crtc_state);
6550 intel_encoders_enable(state, crtc);
6552 if (HAS_PCH_CPT(dev_priv))
6553 cpt_verify_modeset(dev_priv, pipe);
6556 * Must wait for vblank to avoid spurious PCH FIFO underruns.
6557 * And a second vblank wait is needed at least on ILK with
6558 * some interlaced HDMI modes. Let's do the double wait always
6559 * in case there are more corner cases we don't know about.
6561 if (new_crtc_state->has_pch_encoder) {
6562 intel_wait_for_vblank(dev_priv, pipe);
6563 intel_wait_for_vblank(dev_priv, pipe);
6565 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6566 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6569 /* IPS only exists on ULT machines and is tied to pipe A. */
6570 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6572 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6575 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6576 enum pipe pipe, bool apply)
6578 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6579 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6586 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6589 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6592 enum pipe pipe = crtc->pipe;
6595 val = MBUS_DBOX_A_CREDIT(2);
6597 if (INTEL_GEN(dev_priv) >= 12) {
6598 val |= MBUS_DBOX_BW_CREDIT(2);
6599 val |= MBUS_DBOX_B_CREDIT(12);
6601 val |= MBUS_DBOX_BW_CREDIT(1);
6602 val |= MBUS_DBOX_B_CREDIT(8);
6605 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6608 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
6610 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6611 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6612 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
6615 val = I915_READ(reg);
6616 val &= ~HSW_FRAME_START_DELAY_MASK;
6617 val |= HSW_FRAME_START_DELAY(0);
6618 I915_WRITE(reg, val);
6621 static void haswell_crtc_enable(struct intel_atomic_state *state,
6622 struct intel_crtc *crtc)
6624 const struct intel_crtc_state *new_crtc_state =
6625 intel_atomic_get_new_crtc_state(state, crtc);
6626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6627 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
6628 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
6629 bool psl_clkgate_wa;
6631 if (WARN_ON(crtc->active))
6634 intel_encoders_pre_pll_enable(state, crtc);
6636 if (new_crtc_state->shared_dpll)
6637 intel_enable_shared_dpll(new_crtc_state);
6639 intel_encoders_pre_enable(state, crtc);
6641 if (intel_crtc_has_dp_encoder(new_crtc_state))
6642 intel_dp_set_m_n(new_crtc_state, M1_N1);
6644 if (!transcoder_is_dsi(cpu_transcoder))
6645 intel_set_pipe_timings(new_crtc_state);
6647 if (INTEL_GEN(dev_priv) >= 11)
6648 icl_enable_trans_port_sync(new_crtc_state);
6650 intel_set_pipe_src_size(new_crtc_state);
6652 if (cpu_transcoder != TRANSCODER_EDP &&
6653 !transcoder_is_dsi(cpu_transcoder))
6654 I915_WRITE(PIPE_MULT(cpu_transcoder),
6655 new_crtc_state->pixel_multiplier - 1);
6657 if (new_crtc_state->has_pch_encoder)
6658 intel_cpu_transcoder_set_m_n(new_crtc_state,
6659 &new_crtc_state->fdi_m_n, NULL);
6661 if (!transcoder_is_dsi(cpu_transcoder)) {
6662 hsw_set_frame_start_delay(new_crtc_state);
6663 haswell_set_pipeconf(new_crtc_state);
6666 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6667 bdw_set_pipemisc(new_crtc_state);
6669 crtc->active = true;
6671 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6672 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6673 new_crtc_state->pch_pfit.enabled;
6675 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6677 if (INTEL_GEN(dev_priv) >= 9)
6678 skylake_pfit_enable(new_crtc_state);
6680 ironlake_pfit_enable(new_crtc_state);
6683 * On ILK+ LUT must be loaded before the pipe is running but with
6686 intel_color_load_luts(new_crtc_state);
6687 intel_color_commit(new_crtc_state);
6688 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6689 if (INTEL_GEN(dev_priv) < 9)
6690 intel_disable_primary_plane(new_crtc_state);
6692 if (INTEL_GEN(dev_priv) >= 11)
6693 icl_set_pipe_chicken(crtc);
6695 if (!transcoder_is_dsi(cpu_transcoder))
6696 intel_ddi_enable_transcoder_func(new_crtc_state);
6698 if (dev_priv->display.initial_watermarks)
6699 dev_priv->display.initial_watermarks(state, crtc);
6701 if (INTEL_GEN(dev_priv) >= 11)
6702 icl_pipe_mbus_enable(crtc);
6704 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6705 if (!transcoder_is_dsi(cpu_transcoder))
6706 intel_enable_pipe(new_crtc_state);
6708 if (new_crtc_state->has_pch_encoder)
6709 lpt_pch_enable(state, new_crtc_state);
6711 intel_crtc_vblank_on(new_crtc_state);
6713 intel_encoders_enable(state, crtc);
6715 if (psl_clkgate_wa) {
6716 intel_wait_for_vblank(dev_priv, pipe);
6717 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6720 /* If we change the relative order between pipe/planes enabling, we need
6721 * to change the workaround. */
6722 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
6723 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6724 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6725 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6729 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6731 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6732 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6733 enum pipe pipe = crtc->pipe;
6735 /* To avoid upsetting the power well on haswell only disable the pfit if
6736 * it's in use. The hw state code will make sure we get this right. */
6737 if (old_crtc_state->pch_pfit.enabled) {
6738 I915_WRITE(PF_CTL(pipe), 0);
6739 I915_WRITE(PF_WIN_POS(pipe), 0);
6740 I915_WRITE(PF_WIN_SZ(pipe), 0);
6744 static void ironlake_crtc_disable(struct intel_atomic_state *state,
6745 struct intel_crtc *crtc)
6747 const struct intel_crtc_state *old_crtc_state =
6748 intel_atomic_get_old_crtc_state(state, crtc);
6749 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6750 enum pipe pipe = crtc->pipe;
6753 * Sometimes spurious CPU pipe underruns happen when the
6754 * pipe is already disabled, but FDI RX/TX is still enabled.
6755 * Happens at least with VGA+HDMI cloning. Suppress them.
6757 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6758 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6760 intel_encoders_disable(state, crtc);
6762 intel_crtc_vblank_off(crtc);
6764 intel_disable_pipe(old_crtc_state);
6766 ironlake_pfit_disable(old_crtc_state);
6768 if (old_crtc_state->has_pch_encoder)
6769 ironlake_fdi_disable(crtc);
6771 intel_encoders_post_disable(state, crtc);
6773 if (old_crtc_state->has_pch_encoder) {
6774 ironlake_disable_pch_transcoder(dev_priv, pipe);
6776 if (HAS_PCH_CPT(dev_priv)) {
6780 /* disable TRANS_DP_CTL */
6781 reg = TRANS_DP_CTL(pipe);
6782 temp = I915_READ(reg);
6783 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6784 TRANS_DP_PORT_SEL_MASK);
6785 temp |= TRANS_DP_PORT_SEL_NONE;
6786 I915_WRITE(reg, temp);
6788 /* disable DPLL_SEL */
6789 temp = I915_READ(PCH_DPLL_SEL);
6790 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6791 I915_WRITE(PCH_DPLL_SEL, temp);
6794 ironlake_fdi_pll_disable(crtc);
6797 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6798 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6801 static void haswell_crtc_disable(struct intel_atomic_state *state,
6802 struct intel_crtc *crtc)
6804 const struct intel_crtc_state *old_crtc_state =
6805 intel_atomic_get_old_crtc_state(state, crtc);
6806 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6807 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6809 intel_encoders_disable(state, crtc);
6811 intel_crtc_vblank_off(crtc);
6813 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6814 if (!transcoder_is_dsi(cpu_transcoder))
6815 intel_disable_pipe(old_crtc_state);
6817 if (INTEL_GEN(dev_priv) >= 11)
6818 icl_disable_transcoder_port_sync(old_crtc_state);
6820 if (!transcoder_is_dsi(cpu_transcoder))
6821 intel_ddi_disable_transcoder_func(old_crtc_state);
6823 intel_dsc_disable(old_crtc_state);
6825 if (INTEL_GEN(dev_priv) >= 9)
6826 skylake_scaler_disable(crtc);
6828 ironlake_pfit_disable(old_crtc_state);
6830 intel_encoders_post_disable(state, crtc);
6832 intel_encoders_post_pll_disable(state, crtc);
6835 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6837 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6838 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6840 if (!crtc_state->gmch_pfit.control)
6844 * The panel fitter should only be adjusted whilst the pipe is disabled,
6845 * according to register description and PRM.
6847 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6848 assert_pipe_disabled(dev_priv, crtc->pipe);
6850 I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6851 I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6853 /* Border color in case we don't scale up to the full screen. Black by
6854 * default, change to something else for debugging. */
6855 I915_WRITE(BCLRPAT(crtc->pipe), 0);
6858 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6860 if (phy == PHY_NONE)
6863 if (IS_ELKHARTLAKE(dev_priv))
6864 return phy <= PHY_C;
6866 if (INTEL_GEN(dev_priv) >= 11)
6867 return phy <= PHY_B;
6872 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6874 if (INTEL_GEN(dev_priv) >= 12)
6875 return phy >= PHY_D && phy <= PHY_I;
6877 if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6878 return phy >= PHY_C && phy <= PHY_F;
6883 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6885 if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6888 return (enum phy)port;
6891 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6893 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6894 return PORT_TC_NONE;
6896 if (INTEL_GEN(dev_priv) >= 12)
6897 return port - PORT_D;
6899 return port - PORT_C;
6902 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6906 return POWER_DOMAIN_PORT_DDI_A_LANES;
6908 return POWER_DOMAIN_PORT_DDI_B_LANES;
6910 return POWER_DOMAIN_PORT_DDI_C_LANES;
6912 return POWER_DOMAIN_PORT_DDI_D_LANES;
6914 return POWER_DOMAIN_PORT_DDI_E_LANES;
6916 return POWER_DOMAIN_PORT_DDI_F_LANES;
6918 return POWER_DOMAIN_PORT_DDI_G_LANES;
6921 return POWER_DOMAIN_PORT_OTHER;
6925 enum intel_display_power_domain
6926 intel_aux_power_domain(struct intel_digital_port *dig_port)
6928 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6929 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6931 if (intel_phy_is_tc(dev_priv, phy) &&
6932 dig_port->tc_mode == TC_PORT_TBT_ALT) {
6933 switch (dig_port->aux_ch) {
6935 return POWER_DOMAIN_AUX_C_TBT;
6937 return POWER_DOMAIN_AUX_D_TBT;
6939 return POWER_DOMAIN_AUX_E_TBT;
6941 return POWER_DOMAIN_AUX_F_TBT;
6943 return POWER_DOMAIN_AUX_G_TBT;
6945 MISSING_CASE(dig_port->aux_ch);
6946 return POWER_DOMAIN_AUX_C_TBT;
6950 switch (dig_port->aux_ch) {
6952 return POWER_DOMAIN_AUX_A;
6954 return POWER_DOMAIN_AUX_B;
6956 return POWER_DOMAIN_AUX_C;
6958 return POWER_DOMAIN_AUX_D;
6960 return POWER_DOMAIN_AUX_E;
6962 return POWER_DOMAIN_AUX_F;
6964 return POWER_DOMAIN_AUX_G;
6966 MISSING_CASE(dig_port->aux_ch);
6967 return POWER_DOMAIN_AUX_A;
6971 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6973 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6974 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6975 struct drm_encoder *encoder;
6976 enum pipe pipe = crtc->pipe;
6978 enum transcoder transcoder = crtc_state->cpu_transcoder;
6980 if (!crtc_state->hw.active)
6983 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6984 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6985 if (crtc_state->pch_pfit.enabled ||
6986 crtc_state->pch_pfit.force_thru)
6987 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6989 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6990 crtc_state->uapi.encoder_mask) {
6991 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6993 mask |= BIT_ULL(intel_encoder->power_domain);
6996 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6997 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6999 if (crtc_state->shared_dpll)
7000 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7006 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7010 enum intel_display_power_domain domain;
7011 u64 domains, new_domains, old_domains;
7013 old_domains = crtc->enabled_power_domains;
7014 crtc->enabled_power_domains = new_domains =
7015 get_crtc_power_domains(crtc_state);
7017 domains = new_domains & ~old_domains;
7019 for_each_power_domain(domain, domains)
7020 intel_display_power_get(dev_priv, domain);
7022 return old_domains & ~new_domains;
7025 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7028 enum intel_display_power_domain domain;
7030 for_each_power_domain(domain, domains)
7031 intel_display_power_put_unchecked(dev_priv, domain);
7034 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7035 struct intel_crtc *crtc)
7037 const struct intel_crtc_state *new_crtc_state =
7038 intel_atomic_get_new_crtc_state(state, crtc);
7039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7040 enum pipe pipe = crtc->pipe;
7042 if (WARN_ON(crtc->active))
7045 if (intel_crtc_has_dp_encoder(new_crtc_state))
7046 intel_dp_set_m_n(new_crtc_state, M1_N1);
7048 intel_set_pipe_timings(new_crtc_state);
7049 intel_set_pipe_src_size(new_crtc_state);
7051 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7052 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7053 I915_WRITE(CHV_CANVAS(pipe), 0);
7056 i9xx_set_pipeconf(new_crtc_state);
7058 crtc->active = true;
7060 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7062 intel_encoders_pre_pll_enable(state, crtc);
7064 if (IS_CHERRYVIEW(dev_priv)) {
7065 chv_prepare_pll(crtc, new_crtc_state);
7066 chv_enable_pll(crtc, new_crtc_state);
7068 vlv_prepare_pll(crtc, new_crtc_state);
7069 vlv_enable_pll(crtc, new_crtc_state);
7072 intel_encoders_pre_enable(state, crtc);
7074 i9xx_pfit_enable(new_crtc_state);
7076 intel_color_load_luts(new_crtc_state);
7077 intel_color_commit(new_crtc_state);
7078 /* update DSPCNTR to configure gamma for pipe bottom color */
7079 intel_disable_primary_plane(new_crtc_state);
7081 dev_priv->display.initial_watermarks(state, crtc);
7082 intel_enable_pipe(new_crtc_state);
7084 intel_crtc_vblank_on(new_crtc_state);
7086 intel_encoders_enable(state, crtc);
7089 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7091 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7092 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7094 I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
7095 I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
7098 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7099 struct intel_crtc *crtc)
7101 const struct intel_crtc_state *new_crtc_state =
7102 intel_atomic_get_new_crtc_state(state, crtc);
7103 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7104 enum pipe pipe = crtc->pipe;
7106 if (WARN_ON(crtc->active))
7109 i9xx_set_pll_dividers(new_crtc_state);
7111 if (intel_crtc_has_dp_encoder(new_crtc_state))
7112 intel_dp_set_m_n(new_crtc_state, M1_N1);
7114 intel_set_pipe_timings(new_crtc_state);
7115 intel_set_pipe_src_size(new_crtc_state);
7117 i9xx_set_pipeconf(new_crtc_state);
7119 crtc->active = true;
7121 if (!IS_GEN(dev_priv, 2))
7122 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7124 intel_encoders_pre_enable(state, crtc);
7126 i9xx_enable_pll(crtc, new_crtc_state);
7128 i9xx_pfit_enable(new_crtc_state);
7130 intel_color_load_luts(new_crtc_state);
7131 intel_color_commit(new_crtc_state);
7132 /* update DSPCNTR to configure gamma for pipe bottom color */
7133 intel_disable_primary_plane(new_crtc_state);
7135 if (dev_priv->display.initial_watermarks)
7136 dev_priv->display.initial_watermarks(state, crtc);
7138 intel_update_watermarks(crtc);
7139 intel_enable_pipe(new_crtc_state);
7141 intel_crtc_vblank_on(new_crtc_state);
7143 intel_encoders_enable(state, crtc);
7146 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7148 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7149 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7151 if (!old_crtc_state->gmch_pfit.control)
7154 assert_pipe_disabled(dev_priv, crtc->pipe);
7156 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
7157 I915_READ(PFIT_CONTROL));
7158 I915_WRITE(PFIT_CONTROL, 0);
7161 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7162 struct intel_crtc *crtc)
7164 struct intel_crtc_state *old_crtc_state =
7165 intel_atomic_get_old_crtc_state(state, crtc);
7166 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7167 enum pipe pipe = crtc->pipe;
7170 * On gen2 planes are double buffered but the pipe isn't, so we must
7171 * wait for planes to fully turn off before disabling the pipe.
7173 if (IS_GEN(dev_priv, 2))
7174 intel_wait_for_vblank(dev_priv, pipe);
7176 intel_encoders_disable(state, crtc);
7178 intel_crtc_vblank_off(crtc);
7180 intel_disable_pipe(old_crtc_state);
7182 i9xx_pfit_disable(old_crtc_state);
7184 intel_encoders_post_disable(state, crtc);
7186 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7187 if (IS_CHERRYVIEW(dev_priv))
7188 chv_disable_pll(dev_priv, pipe);
7189 else if (IS_VALLEYVIEW(dev_priv))
7190 vlv_disable_pll(dev_priv, pipe);
7192 i9xx_disable_pll(old_crtc_state);
7195 intel_encoders_post_pll_disable(state, crtc);
7197 if (!IS_GEN(dev_priv, 2))
7198 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7200 if (!dev_priv->display.initial_watermarks)
7201 intel_update_watermarks(crtc);
7203 /* clock the pipe down to 640x480@60 to potentially save power */
7204 if (IS_I830(dev_priv))
7205 i830_enable_pipe(dev_priv, pipe);
7208 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7209 struct drm_modeset_acquire_ctx *ctx)
7211 struct intel_encoder *encoder;
7212 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7213 struct intel_bw_state *bw_state =
7214 to_intel_bw_state(dev_priv->bw_obj.state);
7215 struct intel_crtc_state *crtc_state =
7216 to_intel_crtc_state(crtc->base.state);
7217 enum intel_display_power_domain domain;
7218 struct intel_plane *plane;
7219 struct drm_atomic_state *state;
7220 struct intel_crtc_state *temp_crtc_state;
7221 enum pipe pipe = crtc->pipe;
7225 if (!crtc_state->hw.active)
7228 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7229 const struct intel_plane_state *plane_state =
7230 to_intel_plane_state(plane->base.state);
7232 if (plane_state->uapi.visible)
7233 intel_plane_disable_noatomic(crtc, plane);
7236 state = drm_atomic_state_alloc(&dev_priv->drm);
7238 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7239 crtc->base.base.id, crtc->base.name);
7243 state->acquire_ctx = ctx;
7245 /* Everything's already locked, -EDEADLK can't happen. */
7246 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7247 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7249 WARN_ON(IS_ERR(temp_crtc_state) || ret);
7251 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7253 drm_atomic_state_put(state);
7255 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7256 crtc->base.base.id, crtc->base.name);
7258 crtc->active = false;
7259 crtc->base.enabled = false;
7261 WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7262 crtc_state->uapi.active = false;
7263 crtc_state->uapi.connector_mask = 0;
7264 crtc_state->uapi.encoder_mask = 0;
7265 intel_crtc_free_hw_state(crtc_state);
7266 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7268 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7269 encoder->base.crtc = NULL;
7271 intel_fbc_disable(crtc);
7272 intel_update_watermarks(crtc);
7273 intel_disable_shared_dpll(crtc_state);
7275 domains = crtc->enabled_power_domains;
7276 for_each_power_domain(domain, domains)
7277 intel_display_power_put_unchecked(dev_priv, domain);
7278 crtc->enabled_power_domains = 0;
7280 dev_priv->active_pipes &= ~BIT(pipe);
7281 dev_priv->min_cdclk[pipe] = 0;
7282 dev_priv->min_voltage_level[pipe] = 0;
7284 bw_state->data_rate[pipe] = 0;
7285 bw_state->num_active_planes[pipe] = 0;
7289 * turn all crtc's off, but do not adjust state
7290 * This has to be paired with a call to intel_modeset_setup_hw_state.
7292 int intel_display_suspend(struct drm_device *dev)
7294 struct drm_i915_private *dev_priv = to_i915(dev);
7295 struct drm_atomic_state *state;
7298 state = drm_atomic_helper_suspend(dev);
7299 ret = PTR_ERR_OR_ZERO(state);
7301 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7303 dev_priv->modeset_restore_state = state;
7307 void intel_encoder_destroy(struct drm_encoder *encoder)
7309 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7311 drm_encoder_cleanup(encoder);
7312 kfree(intel_encoder);
7315 /* Cross check the actual hw state with our own modeset state tracking (and it's
7316 * internal consistency). */
7317 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7318 struct drm_connector_state *conn_state)
7320 struct intel_connector *connector = to_intel_connector(conn_state->connector);
7322 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7323 connector->base.base.id,
7324 connector->base.name);
7326 if (connector->get_hw_state(connector)) {
7327 struct intel_encoder *encoder = connector->encoder;
7329 I915_STATE_WARN(!crtc_state,
7330 "connector enabled without attached crtc\n");
7335 I915_STATE_WARN(!crtc_state->hw.active,
7336 "connector is active, but attached crtc isn't\n");
7338 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7341 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7342 "atomic encoder doesn't match attached encoder\n");
7344 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7345 "attached encoder crtc differs from connector crtc\n");
7347 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7348 "attached crtc is active, but connector isn't\n");
7349 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7350 "best encoder set without crtc!\n");
7354 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7356 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7357 return crtc_state->fdi_lanes;
7362 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7363 struct intel_crtc_state *pipe_config)
7365 struct drm_i915_private *dev_priv = to_i915(dev);
7366 struct drm_atomic_state *state = pipe_config->uapi.state;
7367 struct intel_crtc *other_crtc;
7368 struct intel_crtc_state *other_crtc_state;
7370 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7371 pipe_name(pipe), pipe_config->fdi_lanes);
7372 if (pipe_config->fdi_lanes > 4) {
7373 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7374 pipe_name(pipe), pipe_config->fdi_lanes);
7378 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7379 if (pipe_config->fdi_lanes > 2) {
7380 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7381 pipe_config->fdi_lanes);
7388 if (INTEL_NUM_PIPES(dev_priv) == 2)
7391 /* Ivybridge 3 pipe is really complicated */
7396 if (pipe_config->fdi_lanes <= 2)
7399 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7401 intel_atomic_get_crtc_state(state, other_crtc);
7402 if (IS_ERR(other_crtc_state))
7403 return PTR_ERR(other_crtc_state);
7405 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7406 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7407 pipe_name(pipe), pipe_config->fdi_lanes);
7412 if (pipe_config->fdi_lanes > 2) {
7413 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7414 pipe_name(pipe), pipe_config->fdi_lanes);
7418 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7420 intel_atomic_get_crtc_state(state, other_crtc);
7421 if (IS_ERR(other_crtc_state))
7422 return PTR_ERR(other_crtc_state);
7424 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7425 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7435 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7436 struct intel_crtc_state *pipe_config)
7438 struct drm_device *dev = intel_crtc->base.dev;
7439 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7440 int lane, link_bw, fdi_dotclock, ret;
7441 bool needs_recompute = false;
7444 /* FDI is a binary signal running at ~2.7GHz, encoding
7445 * each output octet as 10 bits. The actual frequency
7446 * is stored as a divider into a 100MHz clock, and the
7447 * mode pixel clock is stored in units of 1KHz.
7448 * Hence the bw of each lane in terms of the mode signal
7451 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7453 fdi_dotclock = adjusted_mode->crtc_clock;
7455 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7456 pipe_config->pipe_bpp);
7458 pipe_config->fdi_lanes = lane;
7460 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7461 link_bw, &pipe_config->fdi_m_n, false, false);
7463 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7464 if (ret == -EDEADLK)
7467 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7468 pipe_config->pipe_bpp -= 2*3;
7469 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7470 pipe_config->pipe_bpp);
7471 needs_recompute = true;
7472 pipe_config->bw_constrained = true;
7477 if (needs_recompute)
7483 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7485 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7488 /* IPS only exists on ULT machines and is tied to pipe A. */
7489 if (!hsw_crtc_supports_ips(crtc))
7492 if (!i915_modparams.enable_ips)
7495 if (crtc_state->pipe_bpp > 24)
7499 * We compare against max which means we must take
7500 * the increased cdclk requirement into account when
7501 * calculating the new cdclk.
7503 * Should measure whether using a lower cdclk w/o IPS
7505 if (IS_BROADWELL(dev_priv) &&
7506 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7512 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7514 struct drm_i915_private *dev_priv =
7515 to_i915(crtc_state->uapi.crtc->dev);
7516 struct intel_atomic_state *intel_state =
7517 to_intel_atomic_state(crtc_state->uapi.state);
7519 if (!hsw_crtc_state_ips_capable(crtc_state))
7523 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7524 * enabled and disabled dynamically based on package C states,
7525 * user space can't make reliable use of the CRCs, so let's just
7526 * completely disable it.
7528 if (crtc_state->crc_enabled)
7531 /* IPS should be fine as long as at least one plane is enabled. */
7532 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7535 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7536 if (IS_BROADWELL(dev_priv) &&
7537 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7543 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7545 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7547 /* GDG double wide on either pipe, otherwise pipe A only */
7548 return INTEL_GEN(dev_priv) < 4 &&
7549 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7552 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7556 pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7559 * We only use IF-ID interlacing. If we ever use
7560 * PF-ID we'll need to adjust the pixel_rate here.
7563 if (pipe_config->pch_pfit.enabled) {
7564 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7565 u32 pfit_size = pipe_config->pch_pfit.size;
7567 pipe_w = pipe_config->pipe_src_w;
7568 pipe_h = pipe_config->pipe_src_h;
7570 pfit_w = (pfit_size >> 16) & 0xFFFF;
7571 pfit_h = pfit_size & 0xFFFF;
7572 if (pipe_w < pfit_w)
7574 if (pipe_h < pfit_h)
7577 if (WARN_ON(!pfit_w || !pfit_h))
7580 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7587 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7589 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7591 if (HAS_GMCH(dev_priv))
7592 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7593 crtc_state->pixel_rate =
7594 crtc_state->hw.adjusted_mode.crtc_clock;
7596 crtc_state->pixel_rate =
7597 ilk_pipe_pixel_rate(crtc_state);
7600 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7601 struct intel_crtc_state *pipe_config)
7603 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7604 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7605 int clock_limit = dev_priv->max_dotclk_freq;
7607 if (INTEL_GEN(dev_priv) < 4) {
7608 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7611 * Enable double wide mode when the dot clock
7612 * is > 90% of the (display) core speed.
7614 if (intel_crtc_supports_double_wide(crtc) &&
7615 adjusted_mode->crtc_clock > clock_limit) {
7616 clock_limit = dev_priv->max_dotclk_freq;
7617 pipe_config->double_wide = true;
7621 if (adjusted_mode->crtc_clock > clock_limit) {
7622 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7623 adjusted_mode->crtc_clock, clock_limit,
7624 yesno(pipe_config->double_wide));
7628 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7629 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7630 pipe_config->hw.ctm) {
7632 * There is only one pipe CSC unit per pipe, and we need that
7633 * for output conversion from RGB->YCBCR. So if CTM is already
7634 * applied we can't support YCBCR420 output.
7636 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7641 * Pipe horizontal size must be even in:
7643 * - LVDS dual channel mode
7644 * - Double wide pipe
7646 if (pipe_config->pipe_src_w & 1) {
7647 if (pipe_config->double_wide) {
7648 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7652 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7653 intel_is_dual_link_lvds(dev_priv)) {
7654 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7659 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7660 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7662 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7663 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7666 intel_crtc_compute_pixel_rate(pipe_config);
7668 if (pipe_config->has_pch_encoder)
7669 return ironlake_fdi_compute_config(crtc, pipe_config);
7675 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7677 while (*num > DATA_LINK_M_N_MASK ||
7678 *den > DATA_LINK_M_N_MASK) {
7684 static void compute_m_n(unsigned int m, unsigned int n,
7685 u32 *ret_m, u32 *ret_n,
7689 * Several DP dongles in particular seem to be fussy about
7690 * too large link M/N values. Give N value as 0x8000 that
7691 * should be acceptable by specific devices. 0x8000 is the
7692 * specified fixed N value for asynchronous clock mode,
7693 * which the devices expect also in synchronous clock mode.
7698 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7700 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7701 intel_reduce_m_n_ratio(ret_m, ret_n);
7705 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7706 int pixel_clock, int link_clock,
7707 struct intel_link_m_n *m_n,
7708 bool constant_n, bool fec_enable)
7710 u32 data_clock = bits_per_pixel * pixel_clock;
7713 data_clock = intel_dp_mode_to_fec_clock(data_clock);
7716 compute_m_n(data_clock,
7717 link_clock * nlanes * 8,
7718 &m_n->gmch_m, &m_n->gmch_n,
7721 compute_m_n(pixel_clock, link_clock,
7722 &m_n->link_m, &m_n->link_n,
7726 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
7729 * There may be no VBT; and if the BIOS enabled SSC we can
7730 * just keep using it to avoid unnecessary flicker. Whereas if the
7731 * BIOS isn't using it, don't assume it will work even if the VBT
7732 * indicates as much.
7734 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7735 bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) &
7738 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
7739 DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n",
7740 enableddisabled(bios_lvds_use_ssc),
7741 enableddisabled(dev_priv->vbt.lvds_use_ssc));
7742 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
7747 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7749 if (i915_modparams.panel_use_ssc >= 0)
7750 return i915_modparams.panel_use_ssc != 0;
7751 return dev_priv->vbt.lvds_use_ssc
7752 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7755 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7757 return (1 << dpll->n) << 16 | dpll->m2;
7760 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7762 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7765 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7766 struct intel_crtc_state *crtc_state,
7767 struct dpll *reduced_clock)
7769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7772 if (IS_PINEVIEW(dev_priv)) {
7773 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7775 fp2 = pnv_dpll_compute_fp(reduced_clock);
7777 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7779 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7782 crtc_state->dpll_hw_state.fp0 = fp;
7784 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7786 crtc_state->dpll_hw_state.fp1 = fp2;
7788 crtc_state->dpll_hw_state.fp1 = fp;
7792 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7798 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7799 * and set it to a reasonable value instead.
7801 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7802 reg_val &= 0xffffff00;
7803 reg_val |= 0x00000030;
7804 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7806 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7807 reg_val &= 0x00ffffff;
7808 reg_val |= 0x8c000000;
7809 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7811 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7812 reg_val &= 0xffffff00;
7813 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7815 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7816 reg_val &= 0x00ffffff;
7817 reg_val |= 0xb0000000;
7818 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7821 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7822 const struct intel_link_m_n *m_n)
7824 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7825 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7826 enum pipe pipe = crtc->pipe;
7828 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7829 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7830 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7831 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7834 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7835 enum transcoder transcoder)
7837 if (IS_HASWELL(dev_priv))
7838 return transcoder == TRANSCODER_EDP;
7841 * Strictly speaking some registers are available before
7842 * gen7, but we only support DRRS on gen7+
7844 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7847 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7848 const struct intel_link_m_n *m_n,
7849 const struct intel_link_m_n *m2_n2)
7851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7852 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7853 enum pipe pipe = crtc->pipe;
7854 enum transcoder transcoder = crtc_state->cpu_transcoder;
7856 if (INTEL_GEN(dev_priv) >= 5) {
7857 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7858 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7859 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7860 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7862 * M2_N2 registers are set only if DRRS is supported
7863 * (to make sure the registers are not unnecessarily accessed).
7865 if (m2_n2 && crtc_state->has_drrs &&
7866 transcoder_has_m2_n2(dev_priv, transcoder)) {
7867 I915_WRITE(PIPE_DATA_M2(transcoder),
7868 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7869 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7870 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7871 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7874 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7875 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7876 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7877 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7881 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7883 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7886 dp_m_n = &crtc_state->dp_m_n;
7887 dp_m2_n2 = &crtc_state->dp_m2_n2;
7888 } else if (m_n == M2_N2) {
7891 * M2_N2 registers are not supported. Hence m2_n2 divider value
7892 * needs to be programmed into M1_N1.
7894 dp_m_n = &crtc_state->dp_m2_n2;
7896 DRM_ERROR("Unsupported divider value\n");
7900 if (crtc_state->has_pch_encoder)
7901 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7903 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7906 static void vlv_compute_dpll(struct intel_crtc *crtc,
7907 struct intel_crtc_state *pipe_config)
7909 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7910 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7911 if (crtc->pipe != PIPE_A)
7912 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7914 /* DPLL not used with DSI, but still need the rest set up */
7915 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7916 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7917 DPLL_EXT_BUFFER_ENABLE_VLV;
7919 pipe_config->dpll_hw_state.dpll_md =
7920 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7923 static void chv_compute_dpll(struct intel_crtc *crtc,
7924 struct intel_crtc_state *pipe_config)
7926 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7927 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7928 if (crtc->pipe != PIPE_A)
7929 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7931 /* DPLL not used with DSI, but still need the rest set up */
7932 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7933 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7935 pipe_config->dpll_hw_state.dpll_md =
7936 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7939 static void vlv_prepare_pll(struct intel_crtc *crtc,
7940 const struct intel_crtc_state *pipe_config)
7942 struct drm_device *dev = crtc->base.dev;
7943 struct drm_i915_private *dev_priv = to_i915(dev);
7944 enum pipe pipe = crtc->pipe;
7946 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7947 u32 coreclk, reg_val;
7950 I915_WRITE(DPLL(pipe),
7951 pipe_config->dpll_hw_state.dpll &
7952 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7954 /* No need to actually set up the DPLL with DSI */
7955 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7958 vlv_dpio_get(dev_priv);
7960 bestn = pipe_config->dpll.n;
7961 bestm1 = pipe_config->dpll.m1;
7962 bestm2 = pipe_config->dpll.m2;
7963 bestp1 = pipe_config->dpll.p1;
7964 bestp2 = pipe_config->dpll.p2;
7966 /* See eDP HDMI DPIO driver vbios notes doc */
7968 /* PLL B needs special handling */
7970 vlv_pllb_recal_opamp(dev_priv, pipe);
7972 /* Set up Tx target for periodic Rcomp update */
7973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7975 /* Disable target IRef on PLL */
7976 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7977 reg_val &= 0x00ffffff;
7978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7980 /* Disable fast lock */
7981 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7983 /* Set idtafcrecal before PLL is enabled */
7984 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7985 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7986 mdiv |= ((bestn << DPIO_N_SHIFT));
7987 mdiv |= (1 << DPIO_K_SHIFT);
7990 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7991 * but we don't support that).
7992 * Note: don't use the DAC post divider as it seems unstable.
7994 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7995 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7997 mdiv |= DPIO_ENABLE_CALIBRATION;
7998 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8000 /* Set HBR and RBR LPF coefficients */
8001 if (pipe_config->port_clock == 162000 ||
8002 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8003 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8004 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8007 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8010 if (intel_crtc_has_dp_encoder(pipe_config)) {
8011 /* Use SSC source */
8013 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8016 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8018 } else { /* HDMI or VGA */
8019 /* Use bend source */
8021 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8024 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8028 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8029 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8030 if (intel_crtc_has_dp_encoder(pipe_config))
8031 coreclk |= 0x01000000;
8032 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8034 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8036 vlv_dpio_put(dev_priv);
8039 static void chv_prepare_pll(struct intel_crtc *crtc,
8040 const struct intel_crtc_state *pipe_config)
8042 struct drm_device *dev = crtc->base.dev;
8043 struct drm_i915_private *dev_priv = to_i915(dev);
8044 enum pipe pipe = crtc->pipe;
8045 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8046 u32 loopfilter, tribuf_calcntr;
8047 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8051 /* Enable Refclk and SSC */
8052 I915_WRITE(DPLL(pipe),
8053 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8055 /* No need to actually set up the DPLL with DSI */
8056 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8059 bestn = pipe_config->dpll.n;
8060 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8061 bestm1 = pipe_config->dpll.m1;
8062 bestm2 = pipe_config->dpll.m2 >> 22;
8063 bestp1 = pipe_config->dpll.p1;
8064 bestp2 = pipe_config->dpll.p2;
8065 vco = pipe_config->dpll.vco;
8069 vlv_dpio_get(dev_priv);
8071 /* p1 and p2 divider */
8072 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8073 5 << DPIO_CHV_S1_DIV_SHIFT |
8074 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8075 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8076 1 << DPIO_CHV_K_DIV_SHIFT);
8078 /* Feedback post-divider - m2 */
8079 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8081 /* Feedback refclk divider - n and m1 */
8082 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8083 DPIO_CHV_M1_DIV_BY_2 |
8084 1 << DPIO_CHV_N_DIV_SHIFT);
8086 /* M2 fraction division */
8087 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8089 /* M2 fraction division enable */
8090 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8091 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8092 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8094 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8095 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8097 /* Program digital lock detect threshold */
8098 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8099 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8100 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8101 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8103 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8104 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8107 if (vco == 5400000) {
8108 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8109 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8110 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8111 tribuf_calcntr = 0x9;
8112 } else if (vco <= 6200000) {
8113 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8114 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8115 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8116 tribuf_calcntr = 0x9;
8117 } else if (vco <= 6480000) {
8118 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8119 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8120 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8121 tribuf_calcntr = 0x8;
8123 /* Not supported. Apply the same limits as in the max case */
8124 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8125 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8126 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8129 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8131 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8132 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8133 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8134 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8137 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8138 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8141 vlv_dpio_put(dev_priv);
8145 * vlv_force_pll_on - forcibly enable just the PLL
8146 * @dev_priv: i915 private structure
8147 * @pipe: pipe PLL to enable
8148 * @dpll: PLL configuration
8150 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8151 * in cases where we need the PLL enabled even when @pipe is not going to
8154 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8155 const struct dpll *dpll)
8157 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8158 struct intel_crtc_state *pipe_config;
8160 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8164 pipe_config->uapi.crtc = &crtc->base;
8165 pipe_config->pixel_multiplier = 1;
8166 pipe_config->dpll = *dpll;
8168 if (IS_CHERRYVIEW(dev_priv)) {
8169 chv_compute_dpll(crtc, pipe_config);
8170 chv_prepare_pll(crtc, pipe_config);
8171 chv_enable_pll(crtc, pipe_config);
8173 vlv_compute_dpll(crtc, pipe_config);
8174 vlv_prepare_pll(crtc, pipe_config);
8175 vlv_enable_pll(crtc, pipe_config);
8184 * vlv_force_pll_off - forcibly disable just the PLL
8185 * @dev_priv: i915 private structure
8186 * @pipe: pipe PLL to disable
8188 * Disable the PLL for @pipe. To be used in cases where we need
8189 * the PLL enabled even when @pipe is not going to be enabled.
8191 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8193 if (IS_CHERRYVIEW(dev_priv))
8194 chv_disable_pll(dev_priv, pipe);
8196 vlv_disable_pll(dev_priv, pipe);
8199 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8200 struct intel_crtc_state *crtc_state,
8201 struct dpll *reduced_clock)
8203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8205 struct dpll *clock = &crtc_state->dpll;
8207 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8209 dpll = DPLL_VGA_MODE_DIS;
8211 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8212 dpll |= DPLLB_MODE_LVDS;
8214 dpll |= DPLLB_MODE_DAC_SERIAL;
8216 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8217 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8218 dpll |= (crtc_state->pixel_multiplier - 1)
8219 << SDVO_MULTIPLIER_SHIFT_HIRES;
8222 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8223 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8224 dpll |= DPLL_SDVO_HIGH_SPEED;
8226 if (intel_crtc_has_dp_encoder(crtc_state))
8227 dpll |= DPLL_SDVO_HIGH_SPEED;
8229 /* compute bitmask from p1 value */
8230 if (IS_PINEVIEW(dev_priv))
8231 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8233 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8234 if (IS_G4X(dev_priv) && reduced_clock)
8235 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8237 switch (clock->p2) {
8239 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8242 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8245 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8248 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8251 if (INTEL_GEN(dev_priv) >= 4)
8252 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8254 if (crtc_state->sdvo_tv_clock)
8255 dpll |= PLL_REF_INPUT_TVCLKINBC;
8256 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8257 intel_panel_use_ssc(dev_priv))
8258 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8260 dpll |= PLL_REF_INPUT_DREFCLK;
8262 dpll |= DPLL_VCO_ENABLE;
8263 crtc_state->dpll_hw_state.dpll = dpll;
8265 if (INTEL_GEN(dev_priv) >= 4) {
8266 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8267 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8268 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8272 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8273 struct intel_crtc_state *crtc_state,
8274 struct dpll *reduced_clock)
8276 struct drm_device *dev = crtc->base.dev;
8277 struct drm_i915_private *dev_priv = to_i915(dev);
8279 struct dpll *clock = &crtc_state->dpll;
8281 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8283 dpll = DPLL_VGA_MODE_DIS;
8285 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8286 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8289 dpll |= PLL_P1_DIVIDE_BY_TWO;
8291 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8293 dpll |= PLL_P2_DIVIDE_BY_4;
8298 * "[Almador Errata}: For the correct operation of the muxed DVO pins
8299 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8300 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8301 * Enable) must be set to “1” in both the DPLL A Control Register
8302 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8304 * For simplicity We simply keep both bits always enabled in
8305 * both DPLLS. The spec says we should disable the DVO 2X clock
8306 * when not needed, but this seems to work fine in practice.
8308 if (IS_I830(dev_priv) ||
8309 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8310 dpll |= DPLL_DVO_2X_MODE;
8312 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8313 intel_panel_use_ssc(dev_priv))
8314 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8316 dpll |= PLL_REF_INPUT_DREFCLK;
8318 dpll |= DPLL_VCO_ENABLE;
8319 crtc_state->dpll_hw_state.dpll = dpll;
8322 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8324 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8325 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8326 enum pipe pipe = crtc->pipe;
8327 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8328 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8329 u32 crtc_vtotal, crtc_vblank_end;
8332 /* We need to be careful not to changed the adjusted mode, for otherwise
8333 * the hw state checker will get angry at the mismatch. */
8334 crtc_vtotal = adjusted_mode->crtc_vtotal;
8335 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8337 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8338 /* the chip adds 2 halflines automatically */
8340 crtc_vblank_end -= 1;
8342 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8343 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8345 vsyncshift = adjusted_mode->crtc_hsync_start -
8346 adjusted_mode->crtc_htotal / 2;
8348 vsyncshift += adjusted_mode->crtc_htotal;
8351 if (INTEL_GEN(dev_priv) > 3)
8352 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8354 I915_WRITE(HTOTAL(cpu_transcoder),
8355 (adjusted_mode->crtc_hdisplay - 1) |
8356 ((adjusted_mode->crtc_htotal - 1) << 16));
8357 I915_WRITE(HBLANK(cpu_transcoder),
8358 (adjusted_mode->crtc_hblank_start - 1) |
8359 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8360 I915_WRITE(HSYNC(cpu_transcoder),
8361 (adjusted_mode->crtc_hsync_start - 1) |
8362 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8364 I915_WRITE(VTOTAL(cpu_transcoder),
8365 (adjusted_mode->crtc_vdisplay - 1) |
8366 ((crtc_vtotal - 1) << 16));
8367 I915_WRITE(VBLANK(cpu_transcoder),
8368 (adjusted_mode->crtc_vblank_start - 1) |
8369 ((crtc_vblank_end - 1) << 16));
8370 I915_WRITE(VSYNC(cpu_transcoder),
8371 (adjusted_mode->crtc_vsync_start - 1) |
8372 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8374 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8375 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8376 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8378 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8379 (pipe == PIPE_B || pipe == PIPE_C))
8380 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8384 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8386 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8387 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8388 enum pipe pipe = crtc->pipe;
8390 /* pipesrc controls the size that is scaled from, which should
8391 * always be the user's requested size.
8393 I915_WRITE(PIPESRC(pipe),
8394 ((crtc_state->pipe_src_w - 1) << 16) |
8395 (crtc_state->pipe_src_h - 1));
8398 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8400 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8401 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8403 if (IS_GEN(dev_priv, 2))
8406 if (INTEL_GEN(dev_priv) >= 9 ||
8407 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8408 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8410 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8413 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8414 struct intel_crtc_state *pipe_config)
8416 struct drm_device *dev = crtc->base.dev;
8417 struct drm_i915_private *dev_priv = to_i915(dev);
8418 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8421 tmp = I915_READ(HTOTAL(cpu_transcoder));
8422 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8423 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8425 if (!transcoder_is_dsi(cpu_transcoder)) {
8426 tmp = I915_READ(HBLANK(cpu_transcoder));
8427 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8429 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8430 ((tmp >> 16) & 0xffff) + 1;
8432 tmp = I915_READ(HSYNC(cpu_transcoder));
8433 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8434 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8436 tmp = I915_READ(VTOTAL(cpu_transcoder));
8437 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8438 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8440 if (!transcoder_is_dsi(cpu_transcoder)) {
8441 tmp = I915_READ(VBLANK(cpu_transcoder));
8442 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8444 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8445 ((tmp >> 16) & 0xffff) + 1;
8447 tmp = I915_READ(VSYNC(cpu_transcoder));
8448 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8449 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8451 if (intel_pipe_is_interlaced(pipe_config)) {
8452 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8453 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8454 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8458 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8459 struct intel_crtc_state *pipe_config)
8461 struct drm_device *dev = crtc->base.dev;
8462 struct drm_i915_private *dev_priv = to_i915(dev);
8465 tmp = I915_READ(PIPESRC(crtc->pipe));
8466 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8467 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8469 pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8470 pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8473 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8474 struct intel_crtc_state *pipe_config)
8476 mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8477 mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8478 mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8479 mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8481 mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8482 mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8483 mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8484 mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8486 mode->flags = pipe_config->hw.adjusted_mode.flags;
8487 mode->type = DRM_MODE_TYPE_DRIVER;
8489 mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8491 mode->hsync = drm_mode_hsync(mode);
8492 mode->vrefresh = drm_mode_vrefresh(mode);
8493 drm_mode_set_name(mode);
8496 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8498 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8499 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8504 /* we keep both pipes enabled on 830 */
8505 if (IS_I830(dev_priv))
8506 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8508 if (crtc_state->double_wide)
8509 pipeconf |= PIPECONF_DOUBLE_WIDE;
8511 /* only g4x and later have fancy bpc/dither controls */
8512 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8513 IS_CHERRYVIEW(dev_priv)) {
8514 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8515 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8516 pipeconf |= PIPECONF_DITHER_EN |
8517 PIPECONF_DITHER_TYPE_SP;
8519 switch (crtc_state->pipe_bpp) {
8521 pipeconf |= PIPECONF_6BPC;
8524 pipeconf |= PIPECONF_8BPC;
8527 pipeconf |= PIPECONF_10BPC;
8530 /* Case prevented by intel_choose_pipe_bpp_dither. */
8535 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8536 if (INTEL_GEN(dev_priv) < 4 ||
8537 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8538 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8540 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8542 pipeconf |= PIPECONF_PROGRESSIVE;
8545 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8546 crtc_state->limited_color_range)
8547 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8549 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8551 pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8553 I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8554 POSTING_READ(PIPECONF(crtc->pipe));
8557 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8558 struct intel_crtc_state *crtc_state)
8560 struct drm_device *dev = crtc->base.dev;
8561 struct drm_i915_private *dev_priv = to_i915(dev);
8562 const struct intel_limit *limit;
8565 memset(&crtc_state->dpll_hw_state, 0,
8566 sizeof(crtc_state->dpll_hw_state));
8568 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8569 if (intel_panel_use_ssc(dev_priv)) {
8570 refclk = dev_priv->vbt.lvds_ssc_freq;
8571 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8574 limit = &intel_limits_i8xx_lvds;
8575 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8576 limit = &intel_limits_i8xx_dvo;
8578 limit = &intel_limits_i8xx_dac;
8581 if (!crtc_state->clock_set &&
8582 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8583 refclk, NULL, &crtc_state->dpll)) {
8584 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8588 i8xx_compute_dpll(crtc, crtc_state, NULL);
8593 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8594 struct intel_crtc_state *crtc_state)
8596 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8597 const struct intel_limit *limit;
8600 memset(&crtc_state->dpll_hw_state, 0,
8601 sizeof(crtc_state->dpll_hw_state));
8603 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8604 if (intel_panel_use_ssc(dev_priv)) {
8605 refclk = dev_priv->vbt.lvds_ssc_freq;
8606 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8609 if (intel_is_dual_link_lvds(dev_priv))
8610 limit = &intel_limits_g4x_dual_channel_lvds;
8612 limit = &intel_limits_g4x_single_channel_lvds;
8613 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8614 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8615 limit = &intel_limits_g4x_hdmi;
8616 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8617 limit = &intel_limits_g4x_sdvo;
8619 /* The option is for other outputs */
8620 limit = &intel_limits_i9xx_sdvo;
8623 if (!crtc_state->clock_set &&
8624 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8625 refclk, NULL, &crtc_state->dpll)) {
8626 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8630 i9xx_compute_dpll(crtc, crtc_state, NULL);
8635 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8636 struct intel_crtc_state *crtc_state)
8638 struct drm_device *dev = crtc->base.dev;
8639 struct drm_i915_private *dev_priv = to_i915(dev);
8640 const struct intel_limit *limit;
8643 memset(&crtc_state->dpll_hw_state, 0,
8644 sizeof(crtc_state->dpll_hw_state));
8646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8647 if (intel_panel_use_ssc(dev_priv)) {
8648 refclk = dev_priv->vbt.lvds_ssc_freq;
8649 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8652 limit = &intel_limits_pineview_lvds;
8654 limit = &intel_limits_pineview_sdvo;
8657 if (!crtc_state->clock_set &&
8658 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8659 refclk, NULL, &crtc_state->dpll)) {
8660 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8664 i9xx_compute_dpll(crtc, crtc_state, NULL);
8669 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8670 struct intel_crtc_state *crtc_state)
8672 struct drm_device *dev = crtc->base.dev;
8673 struct drm_i915_private *dev_priv = to_i915(dev);
8674 const struct intel_limit *limit;
8677 memset(&crtc_state->dpll_hw_state, 0,
8678 sizeof(crtc_state->dpll_hw_state));
8680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8681 if (intel_panel_use_ssc(dev_priv)) {
8682 refclk = dev_priv->vbt.lvds_ssc_freq;
8683 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8686 limit = &intel_limits_i9xx_lvds;
8688 limit = &intel_limits_i9xx_sdvo;
8691 if (!crtc_state->clock_set &&
8692 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8693 refclk, NULL, &crtc_state->dpll)) {
8694 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8698 i9xx_compute_dpll(crtc, crtc_state, NULL);
8703 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8704 struct intel_crtc_state *crtc_state)
8706 int refclk = 100000;
8707 const struct intel_limit *limit = &intel_limits_chv;
8709 memset(&crtc_state->dpll_hw_state, 0,
8710 sizeof(crtc_state->dpll_hw_state));
8712 if (!crtc_state->clock_set &&
8713 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8714 refclk, NULL, &crtc_state->dpll)) {
8715 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8719 chv_compute_dpll(crtc, crtc_state);
8724 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8725 struct intel_crtc_state *crtc_state)
8727 int refclk = 100000;
8728 const struct intel_limit *limit = &intel_limits_vlv;
8730 memset(&crtc_state->dpll_hw_state, 0,
8731 sizeof(crtc_state->dpll_hw_state));
8733 if (!crtc_state->clock_set &&
8734 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8735 refclk, NULL, &crtc_state->dpll)) {
8736 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8740 vlv_compute_dpll(crtc, crtc_state);
8745 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8747 if (IS_I830(dev_priv))
8750 return INTEL_GEN(dev_priv) >= 4 ||
8751 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8754 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8755 struct intel_crtc_state *pipe_config)
8757 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8760 if (!i9xx_has_pfit(dev_priv))
8763 tmp = I915_READ(PFIT_CONTROL);
8764 if (!(tmp & PFIT_ENABLE))
8767 /* Check whether the pfit is attached to our pipe. */
8768 if (INTEL_GEN(dev_priv) < 4) {
8769 if (crtc->pipe != PIPE_B)
8772 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8776 pipe_config->gmch_pfit.control = tmp;
8777 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8780 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8781 struct intel_crtc_state *pipe_config)
8783 struct drm_device *dev = crtc->base.dev;
8784 struct drm_i915_private *dev_priv = to_i915(dev);
8785 enum pipe pipe = crtc->pipe;
8788 int refclk = 100000;
8790 /* In case of DSI, DPLL will not be used */
8791 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8794 vlv_dpio_get(dev_priv);
8795 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8796 vlv_dpio_put(dev_priv);
8798 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8799 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8800 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8801 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8802 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8804 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8808 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8809 struct intel_initial_plane_config *plane_config)
8811 struct drm_device *dev = crtc->base.dev;
8812 struct drm_i915_private *dev_priv = to_i915(dev);
8813 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8814 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8816 u32 val, base, offset;
8817 int fourcc, pixel_format;
8818 unsigned int aligned_height;
8819 struct drm_framebuffer *fb;
8820 struct intel_framebuffer *intel_fb;
8822 if (!plane->get_hw_state(plane, &pipe))
8825 WARN_ON(pipe != crtc->pipe);
8827 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8829 DRM_DEBUG_KMS("failed to alloc fb\n");
8833 fb = &intel_fb->base;
8837 val = I915_READ(DSPCNTR(i9xx_plane));
8839 if (INTEL_GEN(dev_priv) >= 4) {
8840 if (val & DISPPLANE_TILED) {
8841 plane_config->tiling = I915_TILING_X;
8842 fb->modifier = I915_FORMAT_MOD_X_TILED;
8845 if (val & DISPPLANE_ROTATE_180)
8846 plane_config->rotation = DRM_MODE_ROTATE_180;
8849 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8850 val & DISPPLANE_MIRROR)
8851 plane_config->rotation |= DRM_MODE_REFLECT_X;
8853 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8854 fourcc = i9xx_format_to_fourcc(pixel_format);
8855 fb->format = drm_format_info(fourcc);
8857 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8858 offset = I915_READ(DSPOFFSET(i9xx_plane));
8859 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8860 } else if (INTEL_GEN(dev_priv) >= 4) {
8861 if (plane_config->tiling)
8862 offset = I915_READ(DSPTILEOFF(i9xx_plane));
8864 offset = I915_READ(DSPLINOFF(i9xx_plane));
8865 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8867 base = I915_READ(DSPADDR(i9xx_plane));
8869 plane_config->base = base;
8871 val = I915_READ(PIPESRC(pipe));
8872 fb->width = ((val >> 16) & 0xfff) + 1;
8873 fb->height = ((val >> 0) & 0xfff) + 1;
8875 val = I915_READ(DSPSTRIDE(i9xx_plane));
8876 fb->pitches[0] = val & 0xffffffc0;
8878 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8880 plane_config->size = fb->pitches[0] * aligned_height;
8882 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8883 crtc->base.name, plane->base.name, fb->width, fb->height,
8884 fb->format->cpp[0] * 8, base, fb->pitches[0],
8885 plane_config->size);
8887 plane_config->fb = intel_fb;
8890 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8891 struct intel_crtc_state *pipe_config)
8893 struct drm_device *dev = crtc->base.dev;
8894 struct drm_i915_private *dev_priv = to_i915(dev);
8895 enum pipe pipe = crtc->pipe;
8896 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8898 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8899 int refclk = 100000;
8901 /* In case of DSI, DPLL will not be used */
8902 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8905 vlv_dpio_get(dev_priv);
8906 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8907 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8908 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8909 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8910 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8911 vlv_dpio_put(dev_priv);
8913 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8914 clock.m2 = (pll_dw0 & 0xff) << 22;
8915 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8916 clock.m2 |= pll_dw2 & 0x3fffff;
8917 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8918 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8919 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8921 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8924 static enum intel_output_format
8925 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
8927 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8930 tmp = I915_READ(PIPEMISC(crtc->pipe));
8932 if (tmp & PIPEMISC_YUV420_ENABLE) {
8933 /* We support 4:2:0 in full blend mode only */
8934 WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
8936 return INTEL_OUTPUT_FORMAT_YCBCR420;
8937 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8938 return INTEL_OUTPUT_FORMAT_YCBCR444;
8940 return INTEL_OUTPUT_FORMAT_RGB;
8944 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8946 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8947 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8948 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8949 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8952 tmp = I915_READ(DSPCNTR(i9xx_plane));
8954 if (tmp & DISPPLANE_GAMMA_ENABLE)
8955 crtc_state->gamma_enable = true;
8957 if (!HAS_GMCH(dev_priv) &&
8958 tmp & DISPPLANE_PIPE_CSC_ENABLE)
8959 crtc_state->csc_enable = true;
8962 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8963 struct intel_crtc_state *pipe_config)
8965 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8966 enum intel_display_power_domain power_domain;
8967 intel_wakeref_t wakeref;
8971 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8972 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8976 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8977 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8978 pipe_config->shared_dpll = NULL;
8979 pipe_config->master_transcoder = INVALID_TRANSCODER;
8983 tmp = I915_READ(PIPECONF(crtc->pipe));
8984 if (!(tmp & PIPECONF_ENABLE))
8987 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8988 IS_CHERRYVIEW(dev_priv)) {
8989 switch (tmp & PIPECONF_BPC_MASK) {
8991 pipe_config->pipe_bpp = 18;
8994 pipe_config->pipe_bpp = 24;
8996 case PIPECONF_10BPC:
8997 pipe_config->pipe_bpp = 30;
9004 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9005 (tmp & PIPECONF_COLOR_RANGE_SELECT))
9006 pipe_config->limited_color_range = true;
9008 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9009 PIPECONF_GAMMA_MODE_SHIFT;
9011 if (IS_CHERRYVIEW(dev_priv))
9012 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
9014 i9xx_get_pipe_color_config(pipe_config);
9015 intel_color_get_config(pipe_config);
9017 if (INTEL_GEN(dev_priv) < 4)
9018 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9020 intel_get_pipe_timings(crtc, pipe_config);
9021 intel_get_pipe_src_size(crtc, pipe_config);
9023 i9xx_get_pfit_config(crtc, pipe_config);
9025 if (INTEL_GEN(dev_priv) >= 4) {
9026 /* No way to read it out on pipes B and C */
9027 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9028 tmp = dev_priv->chv_dpll_md[crtc->pipe];
9030 tmp = I915_READ(DPLL_MD(crtc->pipe));
9031 pipe_config->pixel_multiplier =
9032 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9033 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9034 pipe_config->dpll_hw_state.dpll_md = tmp;
9035 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9036 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9037 tmp = I915_READ(DPLL(crtc->pipe));
9038 pipe_config->pixel_multiplier =
9039 ((tmp & SDVO_MULTIPLIER_MASK)
9040 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9042 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9043 * port and will be fixed up in the encoder->get_config
9045 pipe_config->pixel_multiplier = 1;
9047 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
9048 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9049 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
9050 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
9052 /* Mask out read-only status bits. */
9053 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9054 DPLL_PORTC_READY_MASK |
9055 DPLL_PORTB_READY_MASK);
9058 if (IS_CHERRYVIEW(dev_priv))
9059 chv_crtc_clock_get(crtc, pipe_config);
9060 else if (IS_VALLEYVIEW(dev_priv))
9061 vlv_crtc_clock_get(crtc, pipe_config);
9063 i9xx_crtc_clock_get(crtc, pipe_config);
9066 * Normally the dotclock is filled in by the encoder .get_config()
9067 * but in case the pipe is enabled w/o any ports we need a sane
9070 pipe_config->hw.adjusted_mode.crtc_clock =
9071 pipe_config->port_clock / pipe_config->pixel_multiplier;
9076 intel_display_power_put(dev_priv, power_domain, wakeref);
9081 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
9083 struct intel_encoder *encoder;
9086 bool has_lvds = false;
9087 bool has_cpu_edp = false;
9088 bool has_panel = false;
9089 bool has_ck505 = false;
9090 bool can_ssc = false;
9091 bool using_ssc_source = false;
9093 /* We need to take the global config into account */
9094 for_each_intel_encoder(&dev_priv->drm, encoder) {
9095 switch (encoder->type) {
9096 case INTEL_OUTPUT_LVDS:
9100 case INTEL_OUTPUT_EDP:
9102 if (encoder->port == PORT_A)
9110 if (HAS_PCH_IBX(dev_priv)) {
9111 has_ck505 = dev_priv->vbt.display_clock_mode;
9112 can_ssc = has_ck505;
9118 /* Check if any DPLLs are using the SSC source */
9119 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9120 u32 temp = I915_READ(PCH_DPLL(i));
9122 if (!(temp & DPLL_VCO_ENABLE))
9125 if ((temp & PLL_REF_INPUT_MASK) ==
9126 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9127 using_ssc_source = true;
9132 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9133 has_panel, has_lvds, has_ck505, using_ssc_source);
9135 /* Ironlake: try to setup display ref clock before DPLL
9136 * enabling. This is only under driver's control after
9137 * PCH B stepping, previous chipset stepping should be
9138 * ignoring this setting.
9140 val = I915_READ(PCH_DREF_CONTROL);
9142 /* As we must carefully and slowly disable/enable each source in turn,
9143 * compute the final state we want first and check if we need to
9144 * make any changes at all.
9147 final &= ~DREF_NONSPREAD_SOURCE_MASK;
9149 final |= DREF_NONSPREAD_CK505_ENABLE;
9151 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9153 final &= ~DREF_SSC_SOURCE_MASK;
9154 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9155 final &= ~DREF_SSC1_ENABLE;
9158 final |= DREF_SSC_SOURCE_ENABLE;
9160 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9161 final |= DREF_SSC1_ENABLE;
9164 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9165 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9167 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9169 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9170 } else if (using_ssc_source) {
9171 final |= DREF_SSC_SOURCE_ENABLE;
9172 final |= DREF_SSC1_ENABLE;
9178 /* Always enable nonspread source */
9179 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9182 val |= DREF_NONSPREAD_CK505_ENABLE;
9184 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9187 val &= ~DREF_SSC_SOURCE_MASK;
9188 val |= DREF_SSC_SOURCE_ENABLE;
9190 /* SSC must be turned on before enabling the CPU output */
9191 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9192 DRM_DEBUG_KMS("Using SSC on panel\n");
9193 val |= DREF_SSC1_ENABLE;
9195 val &= ~DREF_SSC1_ENABLE;
9197 /* Get SSC going before enabling the outputs */
9198 I915_WRITE(PCH_DREF_CONTROL, val);
9199 POSTING_READ(PCH_DREF_CONTROL);
9202 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9204 /* Enable CPU source on CPU attached eDP */
9206 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9207 DRM_DEBUG_KMS("Using SSC on eDP\n");
9208 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9210 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9212 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9214 I915_WRITE(PCH_DREF_CONTROL, val);
9215 POSTING_READ(PCH_DREF_CONTROL);
9218 DRM_DEBUG_KMS("Disabling CPU source output\n");
9220 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9222 /* Turn off CPU output */
9223 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9225 I915_WRITE(PCH_DREF_CONTROL, val);
9226 POSTING_READ(PCH_DREF_CONTROL);
9229 if (!using_ssc_source) {
9230 DRM_DEBUG_KMS("Disabling SSC source\n");
9232 /* Turn off the SSC source */
9233 val &= ~DREF_SSC_SOURCE_MASK;
9234 val |= DREF_SSC_SOURCE_DISABLE;
9237 val &= ~DREF_SSC1_ENABLE;
9239 I915_WRITE(PCH_DREF_CONTROL, val);
9240 POSTING_READ(PCH_DREF_CONTROL);
9245 BUG_ON(val != final);
9248 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9252 tmp = I915_READ(SOUTH_CHICKEN2);
9253 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9254 I915_WRITE(SOUTH_CHICKEN2, tmp);
9256 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9257 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9258 DRM_ERROR("FDI mPHY reset assert timeout\n");
9260 tmp = I915_READ(SOUTH_CHICKEN2);
9261 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9262 I915_WRITE(SOUTH_CHICKEN2, tmp);
9264 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9265 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9266 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9269 /* WaMPhyProgramming:hsw */
9270 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9274 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9275 tmp &= ~(0xFF << 24);
9276 tmp |= (0x12 << 24);
9277 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9279 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9281 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9283 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9285 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9287 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9288 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9289 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9291 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9292 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9293 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9295 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9298 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9300 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9303 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9305 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9308 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9310 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9313 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9315 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9316 tmp &= ~(0xFF << 16);
9317 tmp |= (0x1C << 16);
9318 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9320 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9321 tmp &= ~(0xFF << 16);
9322 tmp |= (0x1C << 16);
9323 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9325 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9327 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9329 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9331 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9333 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9334 tmp &= ~(0xF << 28);
9336 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9338 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9339 tmp &= ~(0xF << 28);
9341 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9344 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9345 * Programming" based on the parameters passed:
9346 * - Sequence to enable CLKOUT_DP
9347 * - Sequence to enable CLKOUT_DP without spread
9348 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9350 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9351 bool with_spread, bool with_fdi)
9355 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9357 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9358 with_fdi, "LP PCH doesn't have FDI\n"))
9361 mutex_lock(&dev_priv->sb_lock);
9363 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9364 tmp &= ~SBI_SSCCTL_DISABLE;
9365 tmp |= SBI_SSCCTL_PATHALT;
9366 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9371 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9372 tmp &= ~SBI_SSCCTL_PATHALT;
9373 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9376 lpt_reset_fdi_mphy(dev_priv);
9377 lpt_program_fdi_mphy(dev_priv);
9381 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9382 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9383 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9384 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9386 mutex_unlock(&dev_priv->sb_lock);
9389 /* Sequence to disable CLKOUT_DP */
9390 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9394 mutex_lock(&dev_priv->sb_lock);
9396 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9397 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9398 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9399 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9401 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9402 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9403 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9404 tmp |= SBI_SSCCTL_PATHALT;
9405 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9408 tmp |= SBI_SSCCTL_DISABLE;
9409 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9412 mutex_unlock(&dev_priv->sb_lock);
9415 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9417 static const u16 sscdivintphase[] = {
9418 [BEND_IDX( 50)] = 0x3B23,
9419 [BEND_IDX( 45)] = 0x3B23,
9420 [BEND_IDX( 40)] = 0x3C23,
9421 [BEND_IDX( 35)] = 0x3C23,
9422 [BEND_IDX( 30)] = 0x3D23,
9423 [BEND_IDX( 25)] = 0x3D23,
9424 [BEND_IDX( 20)] = 0x3E23,
9425 [BEND_IDX( 15)] = 0x3E23,
9426 [BEND_IDX( 10)] = 0x3F23,
9427 [BEND_IDX( 5)] = 0x3F23,
9428 [BEND_IDX( 0)] = 0x0025,
9429 [BEND_IDX( -5)] = 0x0025,
9430 [BEND_IDX(-10)] = 0x0125,
9431 [BEND_IDX(-15)] = 0x0125,
9432 [BEND_IDX(-20)] = 0x0225,
9433 [BEND_IDX(-25)] = 0x0225,
9434 [BEND_IDX(-30)] = 0x0325,
9435 [BEND_IDX(-35)] = 0x0325,
9436 [BEND_IDX(-40)] = 0x0425,
9437 [BEND_IDX(-45)] = 0x0425,
9438 [BEND_IDX(-50)] = 0x0525,
9443 * steps -50 to 50 inclusive, in steps of 5
9444 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9445 * change in clock period = -(steps / 10) * 5.787 ps
9447 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9450 int idx = BEND_IDX(steps);
9452 if (WARN_ON(steps % 5 != 0))
9455 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9458 mutex_lock(&dev_priv->sb_lock);
9460 if (steps % 10 != 0)
9464 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9466 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9468 tmp |= sscdivintphase[idx];
9469 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9471 mutex_unlock(&dev_priv->sb_lock);
9476 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9478 u32 fuse_strap = I915_READ(FUSE_STRAP);
9479 u32 ctl = I915_READ(SPLL_CTL);
9481 if ((ctl & SPLL_PLL_ENABLE) == 0)
9484 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9485 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9488 if (IS_BROADWELL(dev_priv) &&
9489 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9495 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9496 enum intel_dpll_id id)
9498 u32 fuse_strap = I915_READ(FUSE_STRAP);
9499 u32 ctl = I915_READ(WRPLL_CTL(id));
9501 if ((ctl & WRPLL_PLL_ENABLE) == 0)
9504 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9507 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9508 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9509 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9515 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9517 struct intel_encoder *encoder;
9518 bool has_fdi = false;
9520 for_each_intel_encoder(&dev_priv->drm, encoder) {
9521 switch (encoder->type) {
9522 case INTEL_OUTPUT_ANALOG:
9531 * The BIOS may have decided to use the PCH SSC
9532 * reference so we must not disable it until the
9533 * relevant PLLs have stopped relying on it. We'll
9534 * just leave the PCH SSC reference enabled in case
9535 * any active PLL is using it. It will get disabled
9536 * after runtime suspend if we don't have FDI.
9538 * TODO: Move the whole reference clock handling
9539 * to the modeset sequence proper so that we can
9540 * actually enable/disable/reconfigure these things
9541 * safely. To do that we need to introduce a real
9542 * clock hierarchy. That would also allow us to do
9543 * clock bending finally.
9545 dev_priv->pch_ssc_use = 0;
9547 if (spll_uses_pch_ssc(dev_priv)) {
9548 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9549 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9552 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9553 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9554 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9557 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9558 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9559 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9562 if (dev_priv->pch_ssc_use)
9566 lpt_bend_clkout_dp(dev_priv, 0);
9567 lpt_enable_clkout_dp(dev_priv, true, true);
9569 lpt_disable_clkout_dp(dev_priv);
9574 * Initialize reference clocks when the driver loads
9576 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9578 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9579 ironlake_init_pch_refclk(dev_priv);
9580 else if (HAS_PCH_LPT(dev_priv))
9581 lpt_init_pch_refclk(dev_priv);
9584 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9586 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9587 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9588 enum pipe pipe = crtc->pipe;
9593 switch (crtc_state->pipe_bpp) {
9595 val |= PIPECONF_6BPC;
9598 val |= PIPECONF_8BPC;
9601 val |= PIPECONF_10BPC;
9604 val |= PIPECONF_12BPC;
9607 /* Case prevented by intel_choose_pipe_bpp_dither. */
9611 if (crtc_state->dither)
9612 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9614 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9615 val |= PIPECONF_INTERLACED_ILK;
9617 val |= PIPECONF_PROGRESSIVE;
9620 * This would end up with an odd purple hue over
9621 * the entire display. Make sure we don't do it.
9623 WARN_ON(crtc_state->limited_color_range &&
9624 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
9626 if (crtc_state->limited_color_range)
9627 val |= PIPECONF_COLOR_RANGE_SELECT;
9629 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9630 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
9632 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9634 val |= PIPECONF_FRAME_START_DELAY(0);
9636 I915_WRITE(PIPECONF(pipe), val);
9637 POSTING_READ(PIPECONF(pipe));
9640 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9643 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9644 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9647 if (IS_HASWELL(dev_priv) && crtc_state->dither)
9648 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9650 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9651 val |= PIPECONF_INTERLACED_ILK;
9653 val |= PIPECONF_PROGRESSIVE;
9655 if (IS_HASWELL(dev_priv) &&
9656 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9657 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
9659 I915_WRITE(PIPECONF(cpu_transcoder), val);
9660 POSTING_READ(PIPECONF(cpu_transcoder));
9663 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9665 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9666 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9669 switch (crtc_state->pipe_bpp) {
9671 val |= PIPEMISC_DITHER_6_BPC;
9674 val |= PIPEMISC_DITHER_8_BPC;
9677 val |= PIPEMISC_DITHER_10_BPC;
9680 val |= PIPEMISC_DITHER_12_BPC;
9683 MISSING_CASE(crtc_state->pipe_bpp);
9687 if (crtc_state->dither)
9688 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9690 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9691 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9692 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9694 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9695 val |= PIPEMISC_YUV420_ENABLE |
9696 PIPEMISC_YUV420_MODE_FULL_BLEND;
9698 if (INTEL_GEN(dev_priv) >= 11 &&
9699 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9700 BIT(PLANE_CURSOR))) == 0)
9701 val |= PIPEMISC_HDR_MODE_PRECISION;
9703 I915_WRITE(PIPEMISC(crtc->pipe), val);
9706 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9708 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9711 tmp = I915_READ(PIPEMISC(crtc->pipe));
9713 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9714 case PIPEMISC_DITHER_6_BPC:
9716 case PIPEMISC_DITHER_8_BPC:
9718 case PIPEMISC_DITHER_10_BPC:
9720 case PIPEMISC_DITHER_12_BPC:
9728 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9731 * Account for spread spectrum to avoid
9732 * oversubscribing the link. Max center spread
9733 * is 2.5%; use 5% for safety's sake.
9735 u32 bps = target_clock * bpp * 21 / 20;
9736 return DIV_ROUND_UP(bps, link_bw * 8);
9739 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9741 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9744 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9745 struct intel_crtc_state *crtc_state,
9746 struct dpll *reduced_clock)
9748 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9752 /* Enable autotuning of the PLL clock (if permissible) */
9754 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9755 if ((intel_panel_use_ssc(dev_priv) &&
9756 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9757 (HAS_PCH_IBX(dev_priv) &&
9758 intel_is_dual_link_lvds(dev_priv)))
9760 } else if (crtc_state->sdvo_tv_clock) {
9764 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9766 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9769 if (reduced_clock) {
9770 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9772 if (reduced_clock->m < factor * reduced_clock->n)
9780 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9781 dpll |= DPLLB_MODE_LVDS;
9783 dpll |= DPLLB_MODE_DAC_SERIAL;
9785 dpll |= (crtc_state->pixel_multiplier - 1)
9786 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9788 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9789 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9790 dpll |= DPLL_SDVO_HIGH_SPEED;
9792 if (intel_crtc_has_dp_encoder(crtc_state))
9793 dpll |= DPLL_SDVO_HIGH_SPEED;
9796 * The high speed IO clock is only really required for
9797 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9798 * possible to share the DPLL between CRT and HDMI. Enabling
9799 * the clock needlessly does no real harm, except use up a
9800 * bit of power potentially.
9802 * We'll limit this to IVB with 3 pipes, since it has only two
9803 * DPLLs and so DPLL sharing is the only way to get three pipes
9804 * driving PCH ports at the same time. On SNB we could do this,
9805 * and potentially avoid enabling the second DPLL, but it's not
9806 * clear if it''s a win or loss power wise. No point in doing
9807 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9809 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
9810 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9811 dpll |= DPLL_SDVO_HIGH_SPEED;
9813 /* compute bitmask from p1 value */
9814 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9816 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9818 switch (crtc_state->dpll.p2) {
9820 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9823 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9826 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9829 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9833 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9834 intel_panel_use_ssc(dev_priv))
9835 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9837 dpll |= PLL_REF_INPUT_DREFCLK;
9839 dpll |= DPLL_VCO_ENABLE;
9841 crtc_state->dpll_hw_state.dpll = dpll;
9842 crtc_state->dpll_hw_state.fp0 = fp;
9843 crtc_state->dpll_hw_state.fp1 = fp2;
9846 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9847 struct intel_crtc_state *crtc_state)
9849 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9850 struct intel_atomic_state *state =
9851 to_intel_atomic_state(crtc_state->uapi.state);
9852 const struct intel_limit *limit;
9853 int refclk = 120000;
9855 memset(&crtc_state->dpll_hw_state, 0,
9856 sizeof(crtc_state->dpll_hw_state));
9858 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9859 if (!crtc_state->has_pch_encoder)
9862 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9863 if (intel_panel_use_ssc(dev_priv)) {
9864 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9865 dev_priv->vbt.lvds_ssc_freq);
9866 refclk = dev_priv->vbt.lvds_ssc_freq;
9869 if (intel_is_dual_link_lvds(dev_priv)) {
9870 if (refclk == 100000)
9871 limit = &intel_limits_ironlake_dual_lvds_100m;
9873 limit = &intel_limits_ironlake_dual_lvds;
9875 if (refclk == 100000)
9876 limit = &intel_limits_ironlake_single_lvds_100m;
9878 limit = &intel_limits_ironlake_single_lvds;
9881 limit = &intel_limits_ironlake_dac;
9884 if (!crtc_state->clock_set &&
9885 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9886 refclk, NULL, &crtc_state->dpll)) {
9887 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9891 ironlake_compute_dpll(crtc, crtc_state, NULL);
9893 if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9894 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9895 pipe_name(crtc->pipe));
9902 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9903 struct intel_link_m_n *m_n)
9905 struct drm_device *dev = crtc->base.dev;
9906 struct drm_i915_private *dev_priv = to_i915(dev);
9907 enum pipe pipe = crtc->pipe;
9909 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9910 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9911 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9913 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9914 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9915 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9918 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9919 enum transcoder transcoder,
9920 struct intel_link_m_n *m_n,
9921 struct intel_link_m_n *m2_n2)
9923 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9924 enum pipe pipe = crtc->pipe;
9926 if (INTEL_GEN(dev_priv) >= 5) {
9927 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9928 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9929 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9931 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9932 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9933 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9935 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9936 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9937 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9938 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9940 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9941 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9942 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9945 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9946 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9947 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9949 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9950 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9951 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9955 void intel_dp_get_m_n(struct intel_crtc *crtc,
9956 struct intel_crtc_state *pipe_config)
9958 if (pipe_config->has_pch_encoder)
9959 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9961 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9962 &pipe_config->dp_m_n,
9963 &pipe_config->dp_m2_n2);
9966 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9967 struct intel_crtc_state *pipe_config)
9969 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9970 &pipe_config->fdi_m_n, NULL);
9973 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9974 struct intel_crtc_state *pipe_config)
9976 struct drm_device *dev = crtc->base.dev;
9977 struct drm_i915_private *dev_priv = to_i915(dev);
9978 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9983 /* find scaler attached to this pipe */
9984 for (i = 0; i < crtc->num_scalers; i++) {
9985 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9986 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9988 pipe_config->pch_pfit.enabled = true;
9989 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9990 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9991 scaler_state->scalers[i].in_use = true;
9996 scaler_state->scaler_id = id;
9998 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10000 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10005 skylake_get_initial_plane_config(struct intel_crtc *crtc,
10006 struct intel_initial_plane_config *plane_config)
10008 struct drm_device *dev = crtc->base.dev;
10009 struct drm_i915_private *dev_priv = to_i915(dev);
10010 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10011 enum plane_id plane_id = plane->id;
10013 u32 val, base, offset, stride_mult, tiling, alpha;
10014 int fourcc, pixel_format;
10015 unsigned int aligned_height;
10016 struct drm_framebuffer *fb;
10017 struct intel_framebuffer *intel_fb;
10019 if (!plane->get_hw_state(plane, &pipe))
10022 WARN_ON(pipe != crtc->pipe);
10024 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10026 DRM_DEBUG_KMS("failed to alloc fb\n");
10030 fb = &intel_fb->base;
10034 val = I915_READ(PLANE_CTL(pipe, plane_id));
10036 if (INTEL_GEN(dev_priv) >= 11)
10037 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10039 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10041 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10042 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
10043 alpha &= PLANE_COLOR_ALPHA_MASK;
10045 alpha = val & PLANE_CTL_ALPHA_MASK;
10048 fourcc = skl_format_to_fourcc(pixel_format,
10049 val & PLANE_CTL_ORDER_RGBX, alpha);
10050 fb->format = drm_format_info(fourcc);
10052 tiling = val & PLANE_CTL_TILED_MASK;
10054 case PLANE_CTL_TILED_LINEAR:
10055 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10057 case PLANE_CTL_TILED_X:
10058 plane_config->tiling = I915_TILING_X;
10059 fb->modifier = I915_FORMAT_MOD_X_TILED;
10061 case PLANE_CTL_TILED_Y:
10062 plane_config->tiling = I915_TILING_Y;
10063 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10064 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
10066 fb->modifier = I915_FORMAT_MOD_Y_TILED;
10068 case PLANE_CTL_TILED_YF:
10069 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10070 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10072 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10075 MISSING_CASE(tiling);
10080 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10081 * while i915 HW rotation is clockwise, thats why this swapping.
10083 switch (val & PLANE_CTL_ROTATE_MASK) {
10084 case PLANE_CTL_ROTATE_0:
10085 plane_config->rotation = DRM_MODE_ROTATE_0;
10087 case PLANE_CTL_ROTATE_90:
10088 plane_config->rotation = DRM_MODE_ROTATE_270;
10090 case PLANE_CTL_ROTATE_180:
10091 plane_config->rotation = DRM_MODE_ROTATE_180;
10093 case PLANE_CTL_ROTATE_270:
10094 plane_config->rotation = DRM_MODE_ROTATE_90;
10098 if (INTEL_GEN(dev_priv) >= 10 &&
10099 val & PLANE_CTL_FLIP_HORIZONTAL)
10100 plane_config->rotation |= DRM_MODE_REFLECT_X;
10102 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10103 plane_config->base = base;
10105 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
10107 val = I915_READ(PLANE_SIZE(pipe, plane_id));
10108 fb->height = ((val >> 16) & 0xffff) + 1;
10109 fb->width = ((val >> 0) & 0xffff) + 1;
10111 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
10112 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10113 fb->pitches[0] = (val & 0x3ff) * stride_mult;
10115 aligned_height = intel_fb_align_height(fb, 0, fb->height);
10117 plane_config->size = fb->pitches[0] * aligned_height;
10119 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10120 crtc->base.name, plane->base.name, fb->width, fb->height,
10121 fb->format->cpp[0] * 8, base, fb->pitches[0],
10122 plane_config->size);
10124 plane_config->fb = intel_fb;
10131 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
10132 struct intel_crtc_state *pipe_config)
10134 struct drm_device *dev = crtc->base.dev;
10135 struct drm_i915_private *dev_priv = to_i915(dev);
10138 tmp = I915_READ(PF_CTL(crtc->pipe));
10140 if (tmp & PF_ENABLE) {
10141 pipe_config->pch_pfit.enabled = true;
10142 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
10143 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
10145 /* We currently do not free assignements of panel fitters on
10146 * ivb/hsw (since we don't use the higher upscaling modes which
10147 * differentiates them) so just WARN about this case for now. */
10148 if (IS_GEN(dev_priv, 7)) {
10149 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
10150 PF_PIPE_SEL_IVB(crtc->pipe));
10155 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
10156 struct intel_crtc_state *pipe_config)
10158 struct drm_device *dev = crtc->base.dev;
10159 struct drm_i915_private *dev_priv = to_i915(dev);
10160 enum intel_display_power_domain power_domain;
10161 intel_wakeref_t wakeref;
10165 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10166 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10170 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10171 pipe_config->shared_dpll = NULL;
10172 pipe_config->master_transcoder = INVALID_TRANSCODER;
10175 tmp = I915_READ(PIPECONF(crtc->pipe));
10176 if (!(tmp & PIPECONF_ENABLE))
10179 switch (tmp & PIPECONF_BPC_MASK) {
10180 case PIPECONF_6BPC:
10181 pipe_config->pipe_bpp = 18;
10183 case PIPECONF_8BPC:
10184 pipe_config->pipe_bpp = 24;
10186 case PIPECONF_10BPC:
10187 pipe_config->pipe_bpp = 30;
10189 case PIPECONF_12BPC:
10190 pipe_config->pipe_bpp = 36;
10196 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10197 pipe_config->limited_color_range = true;
10199 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10200 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10201 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10202 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10205 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10209 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10210 PIPECONF_GAMMA_MODE_SHIFT;
10212 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10214 i9xx_get_pipe_color_config(pipe_config);
10215 intel_color_get_config(pipe_config);
10217 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10218 struct intel_shared_dpll *pll;
10219 enum intel_dpll_id pll_id;
10221 pipe_config->has_pch_encoder = true;
10223 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
10224 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10225 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10227 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10229 if (HAS_PCH_IBX(dev_priv)) {
10231 * The pipe->pch transcoder and pch transcoder->pll
10232 * mapping is fixed.
10234 pll_id = (enum intel_dpll_id) crtc->pipe;
10236 tmp = I915_READ(PCH_DPLL_SEL);
10237 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10238 pll_id = DPLL_ID_PCH_PLL_B;
10240 pll_id= DPLL_ID_PCH_PLL_A;
10243 pipe_config->shared_dpll =
10244 intel_get_shared_dpll_by_id(dev_priv, pll_id);
10245 pll = pipe_config->shared_dpll;
10247 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10248 &pipe_config->dpll_hw_state));
10250 tmp = pipe_config->dpll_hw_state.dpll;
10251 pipe_config->pixel_multiplier =
10252 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10253 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10255 ironlake_pch_clock_get(crtc, pipe_config);
10257 pipe_config->pixel_multiplier = 1;
10260 intel_get_pipe_timings(crtc, pipe_config);
10261 intel_get_pipe_src_size(crtc, pipe_config);
10263 ironlake_get_pfit_config(crtc, pipe_config);
10268 intel_display_power_put(dev_priv, power_domain, wakeref);
10272 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10273 struct intel_crtc_state *crtc_state)
10275 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10276 struct intel_atomic_state *state =
10277 to_intel_atomic_state(crtc_state->uapi.state);
10279 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10280 INTEL_GEN(dev_priv) >= 11) {
10281 struct intel_encoder *encoder =
10282 intel_get_crtc_new_encoder(state, crtc_state);
10284 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10285 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10286 pipe_name(crtc->pipe));
10294 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10296 struct intel_crtc_state *pipe_config)
10298 enum intel_dpll_id id;
10301 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10302 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10304 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10307 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10310 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10312 struct intel_crtc_state *pipe_config)
10314 enum phy phy = intel_port_to_phy(dev_priv, port);
10315 enum icl_port_dpll_id port_dpll_id;
10316 enum intel_dpll_id id;
10319 if (intel_phy_is_combo(dev_priv, phy)) {
10320 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10321 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10322 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10323 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10324 } else if (intel_phy_is_tc(dev_priv, phy)) {
10325 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10327 if (clk_sel == DDI_CLK_SEL_MG) {
10328 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10330 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10332 WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10333 id = DPLL_ID_ICL_TBTPLL;
10334 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10337 WARN(1, "Invalid port %x\n", port);
10341 pipe_config->icl_port_dplls[port_dpll_id].pll =
10342 intel_get_shared_dpll_by_id(dev_priv, id);
10344 icl_set_active_port_dpll(pipe_config, port_dpll_id);
10347 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10349 struct intel_crtc_state *pipe_config)
10351 enum intel_dpll_id id;
10355 id = DPLL_ID_SKL_DPLL0;
10358 id = DPLL_ID_SKL_DPLL1;
10361 id = DPLL_ID_SKL_DPLL2;
10364 DRM_ERROR("Incorrect port type\n");
10368 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10371 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10373 struct intel_crtc_state *pipe_config)
10375 enum intel_dpll_id id;
10378 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10379 id = temp >> (port * 3 + 1);
10381 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10384 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10387 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10389 struct intel_crtc_state *pipe_config)
10391 enum intel_dpll_id id;
10392 u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10394 switch (ddi_pll_sel) {
10395 case PORT_CLK_SEL_WRPLL1:
10396 id = DPLL_ID_WRPLL1;
10398 case PORT_CLK_SEL_WRPLL2:
10399 id = DPLL_ID_WRPLL2;
10401 case PORT_CLK_SEL_SPLL:
10404 case PORT_CLK_SEL_LCPLL_810:
10405 id = DPLL_ID_LCPLL_810;
10407 case PORT_CLK_SEL_LCPLL_1350:
10408 id = DPLL_ID_LCPLL_1350;
10410 case PORT_CLK_SEL_LCPLL_2700:
10411 id = DPLL_ID_LCPLL_2700;
10414 MISSING_CASE(ddi_pll_sel);
10416 case PORT_CLK_SEL_NONE:
10420 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10423 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10424 struct intel_crtc_state *pipe_config,
10425 u64 *power_domain_mask,
10426 intel_wakeref_t *wakerefs)
10428 struct drm_device *dev = crtc->base.dev;
10429 struct drm_i915_private *dev_priv = to_i915(dev);
10430 enum intel_display_power_domain power_domain;
10431 unsigned long panel_transcoder_mask = 0;
10432 unsigned long enabled_panel_transcoders = 0;
10433 enum transcoder panel_transcoder;
10434 intel_wakeref_t wf;
10437 if (INTEL_GEN(dev_priv) >= 11)
10438 panel_transcoder_mask |=
10439 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10441 if (HAS_TRANSCODER_EDP(dev_priv))
10442 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10445 * The pipe->transcoder mapping is fixed with the exception of the eDP
10446 * and DSI transcoders handled below.
10448 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10451 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10452 * consistency and less surprising code; it's in always on power).
10454 for_each_set_bit(panel_transcoder,
10455 &panel_transcoder_mask,
10456 ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10457 bool force_thru = false;
10458 enum pipe trans_pipe;
10460 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10461 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10465 * Log all enabled ones, only use the first one.
10467 * FIXME: This won't work for two separate DSI displays.
10469 enabled_panel_transcoders |= BIT(panel_transcoder);
10470 if (enabled_panel_transcoders != BIT(panel_transcoder))
10473 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10475 WARN(1, "unknown pipe linked to transcoder %s\n",
10476 transcoder_name(panel_transcoder));
10478 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10481 case TRANS_DDI_EDP_INPUT_A_ON:
10482 trans_pipe = PIPE_A;
10484 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10485 trans_pipe = PIPE_B;
10487 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10488 trans_pipe = PIPE_C;
10492 if (trans_pipe == crtc->pipe) {
10493 pipe_config->cpu_transcoder = panel_transcoder;
10494 pipe_config->pch_pfit.force_thru = force_thru;
10499 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10501 WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10502 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10504 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10505 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10507 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10511 wakerefs[power_domain] = wf;
10512 *power_domain_mask |= BIT_ULL(power_domain);
10514 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10516 return tmp & PIPECONF_ENABLE;
10519 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10520 struct intel_crtc_state *pipe_config,
10521 u64 *power_domain_mask,
10522 intel_wakeref_t *wakerefs)
10524 struct drm_device *dev = crtc->base.dev;
10525 struct drm_i915_private *dev_priv = to_i915(dev);
10526 enum intel_display_power_domain power_domain;
10527 enum transcoder cpu_transcoder;
10528 intel_wakeref_t wf;
10532 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10533 if (port == PORT_A)
10534 cpu_transcoder = TRANSCODER_DSI_A;
10536 cpu_transcoder = TRANSCODER_DSI_C;
10538 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10539 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10541 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10545 wakerefs[power_domain] = wf;
10546 *power_domain_mask |= BIT_ULL(power_domain);
10549 * The PLL needs to be enabled with a valid divider
10550 * configuration, otherwise accessing DSI registers will hang
10551 * the machine. See BSpec North Display Engine
10552 * registers/MIPI[BXT]. We can break out here early, since we
10553 * need the same DSI PLL to be enabled for both DSI ports.
10555 if (!bxt_dsi_pll_is_enabled(dev_priv))
10558 /* XXX: this works for video mode only */
10559 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10560 if (!(tmp & DPI_ENABLE))
10563 tmp = I915_READ(MIPI_CTRL(port));
10564 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10567 pipe_config->cpu_transcoder = cpu_transcoder;
10571 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10574 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10575 struct intel_crtc_state *pipe_config)
10577 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10578 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
10579 struct intel_shared_dpll *pll;
10583 if (transcoder_is_dsi(cpu_transcoder)) {
10584 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
10587 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
10588 if (INTEL_GEN(dev_priv) >= 12)
10589 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10591 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10594 if (INTEL_GEN(dev_priv) >= 11)
10595 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10596 else if (IS_CANNONLAKE(dev_priv))
10597 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10598 else if (IS_GEN9_BC(dev_priv))
10599 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10600 else if (IS_GEN9_LP(dev_priv))
10601 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10603 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10605 pll = pipe_config->shared_dpll;
10607 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10608 &pipe_config->dpll_hw_state));
10612 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10613 * DDI E. So just check whether this pipe is wired to DDI E and whether
10614 * the PCH transcoder is on.
10616 if (INTEL_GEN(dev_priv) < 9 &&
10617 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10618 pipe_config->has_pch_encoder = true;
10620 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10621 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10622 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10624 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10628 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
10629 enum transcoder cpu_transcoder)
10631 u32 trans_port_sync, master_select;
10633 trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
10635 if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
10636 return INVALID_TRANSCODER;
10638 master_select = trans_port_sync &
10639 PORT_SYNC_MODE_MASTER_SELECT_MASK;
10640 if (master_select == 0)
10641 return TRANSCODER_EDP;
10643 return master_select - 1;
10646 static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
10648 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
10650 enum transcoder cpu_transcoder;
10652 crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
10653 crtc_state->cpu_transcoder);
10655 transcoders = BIT(TRANSCODER_A) |
10656 BIT(TRANSCODER_B) |
10657 BIT(TRANSCODER_C) |
10659 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
10660 enum intel_display_power_domain power_domain;
10661 intel_wakeref_t trans_wakeref;
10663 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10664 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
10667 if (!trans_wakeref)
10670 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
10671 crtc_state->cpu_transcoder)
10672 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
10674 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
10677 WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
10678 crtc_state->sync_mode_slaves_mask);
10681 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10682 struct intel_crtc_state *pipe_config)
10684 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10685 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10686 enum intel_display_power_domain power_domain;
10687 u64 power_domain_mask;
10690 intel_crtc_init_scalers(crtc, pipe_config);
10692 pipe_config->master_transcoder = INVALID_TRANSCODER;
10694 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10695 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10699 wakerefs[power_domain] = wf;
10700 power_domain_mask = BIT_ULL(power_domain);
10702 pipe_config->shared_dpll = NULL;
10704 active = hsw_get_transcoder_state(crtc, pipe_config,
10705 &power_domain_mask, wakerefs);
10707 if (IS_GEN9_LP(dev_priv) &&
10708 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10709 &power_domain_mask, wakerefs)) {
10717 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10718 INTEL_GEN(dev_priv) >= 11) {
10719 haswell_get_ddi_port_state(crtc, pipe_config);
10720 intel_get_pipe_timings(crtc, pipe_config);
10723 intel_get_pipe_src_size(crtc, pipe_config);
10725 if (IS_HASWELL(dev_priv)) {
10726 u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10728 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
10729 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10731 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10733 pipe_config->output_format =
10734 bdw_get_pipemisc_output_format(crtc);
10737 * Currently there is no interface defined to
10738 * check user preference between RGB/YCBCR444
10739 * or YCBCR420. So the only possible case for
10740 * YCBCR444 usage is driving YCBCR420 output
10741 * with LSPCON, when pipe is configured for
10742 * YCBCR444 output and LSPCON takes care of
10745 pipe_config->lspcon_downsampling =
10746 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
10749 pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10751 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10753 if (INTEL_GEN(dev_priv) >= 9) {
10754 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10756 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10757 pipe_config->gamma_enable = true;
10759 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10760 pipe_config->csc_enable = true;
10762 i9xx_get_pipe_color_config(pipe_config);
10765 intel_color_get_config(pipe_config);
10767 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10768 WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10770 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10772 wakerefs[power_domain] = wf;
10773 power_domain_mask |= BIT_ULL(power_domain);
10775 if (INTEL_GEN(dev_priv) >= 9)
10776 skylake_get_pfit_config(crtc, pipe_config);
10778 ironlake_get_pfit_config(crtc, pipe_config);
10781 if (hsw_crtc_supports_ips(crtc)) {
10782 if (IS_HASWELL(dev_priv))
10783 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10786 * We cannot readout IPS state on broadwell, set to
10787 * true so we can set it to a defined state on first
10790 pipe_config->ips_enabled = true;
10794 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10795 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10796 pipe_config->pixel_multiplier =
10797 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10799 pipe_config->pixel_multiplier = 1;
10802 if (INTEL_GEN(dev_priv) >= 11 &&
10803 !transcoder_is_dsi(pipe_config->cpu_transcoder))
10804 icelake_get_trans_port_sync_config(pipe_config);
10807 for_each_power_domain(power_domain, power_domain_mask)
10808 intel_display_power_put(dev_priv,
10809 power_domain, wakerefs[power_domain]);
10814 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10816 struct drm_i915_private *dev_priv =
10817 to_i915(plane_state->uapi.plane->dev);
10818 const struct drm_framebuffer *fb = plane_state->hw.fb;
10819 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10822 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10823 base = obj->phys_handle->busaddr;
10825 base = intel_plane_ggtt_offset(plane_state);
10827 return base + plane_state->color_plane[0].offset;
10830 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10832 int x = plane_state->uapi.dst.x1;
10833 int y = plane_state->uapi.dst.y1;
10837 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10840 pos |= x << CURSOR_X_SHIFT;
10843 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10846 pos |= y << CURSOR_Y_SHIFT;
10851 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10853 const struct drm_mode_config *config =
10854 &plane_state->uapi.plane->dev->mode_config;
10855 int width = drm_rect_width(&plane_state->uapi.dst);
10856 int height = drm_rect_height(&plane_state->uapi.dst);
10858 return width > 0 && width <= config->cursor_width &&
10859 height > 0 && height <= config->cursor_height;
10862 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10864 struct drm_i915_private *dev_priv =
10865 to_i915(plane_state->uapi.plane->dev);
10866 unsigned int rotation = plane_state->hw.rotation;
10871 ret = intel_plane_compute_gtt(plane_state);
10875 if (!plane_state->uapi.visible)
10878 src_x = plane_state->uapi.src.x1 >> 16;
10879 src_y = plane_state->uapi.src.y1 >> 16;
10881 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10882 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10885 if (src_x != 0 || src_y != 0) {
10886 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10891 * Put the final coordinates back so that the src
10892 * coordinate checks will see the right values.
10894 drm_rect_translate_to(&plane_state->uapi.src,
10895 src_x << 16, src_y << 16);
10897 /* ILK+ do this automagically in hardware */
10898 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
10899 const struct drm_framebuffer *fb = plane_state->hw.fb;
10900 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
10901 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
10903 offset += (src_h * src_w - 1) * fb->format->cpp[0];
10906 plane_state->color_plane[0].offset = offset;
10907 plane_state->color_plane[0].x = src_x;
10908 plane_state->color_plane[0].y = src_y;
10913 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10914 struct intel_plane_state *plane_state)
10916 const struct drm_framebuffer *fb = plane_state->hw.fb;
10919 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10920 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10924 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
10926 DRM_PLANE_HELPER_NO_SCALING,
10927 DRM_PLANE_HELPER_NO_SCALING,
10932 /* Use the unclipped src/dst rectangles, which we program to hw */
10933 plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
10934 plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
10936 ret = intel_cursor_check_surface(plane_state);
10940 if (!plane_state->uapi.visible)
10943 ret = intel_plane_check_src_coordinates(plane_state);
10950 static unsigned int
10951 i845_cursor_max_stride(struct intel_plane *plane,
10952 u32 pixel_format, u64 modifier,
10953 unsigned int rotation)
10958 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10962 if (crtc_state->gamma_enable)
10963 cntl |= CURSOR_GAMMA_ENABLE;
10968 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10969 const struct intel_plane_state *plane_state)
10971 return CURSOR_ENABLE |
10972 CURSOR_FORMAT_ARGB |
10973 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10976 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10978 int width = drm_rect_width(&plane_state->uapi.dst);
10981 * 845g/865g are only limited by the width of their cursors,
10982 * the height is arbitrary up to the precision of the register.
10984 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10987 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10988 struct intel_plane_state *plane_state)
10990 const struct drm_framebuffer *fb = plane_state->hw.fb;
10993 ret = intel_check_cursor(crtc_state, plane_state);
10997 /* if we want to turn off the cursor ignore width and height */
11001 /* Check for which cursor types we support */
11002 if (!i845_cursor_size_ok(plane_state)) {
11003 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11004 drm_rect_width(&plane_state->uapi.dst),
11005 drm_rect_height(&plane_state->uapi.dst));
11009 WARN_ON(plane_state->uapi.visible &&
11010 plane_state->color_plane[0].stride != fb->pitches[0]);
11012 switch (fb->pitches[0]) {
11019 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
11024 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11029 static void i845_update_cursor(struct intel_plane *plane,
11030 const struct intel_crtc_state *crtc_state,
11031 const struct intel_plane_state *plane_state)
11033 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11034 u32 cntl = 0, base = 0, pos = 0, size = 0;
11035 unsigned long irqflags;
11037 if (plane_state && plane_state->uapi.visible) {
11038 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11039 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11041 cntl = plane_state->ctl |
11042 i845_cursor_ctl_crtc(crtc_state);
11044 size = (height << 12) | width;
11046 base = intel_cursor_base(plane_state);
11047 pos = intel_cursor_position(plane_state);
11050 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11052 /* On these chipsets we can only modify the base/size/stride
11053 * whilst the cursor is disabled.
11055 if (plane->cursor.base != base ||
11056 plane->cursor.size != size ||
11057 plane->cursor.cntl != cntl) {
11058 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
11059 I915_WRITE_FW(CURBASE(PIPE_A), base);
11060 I915_WRITE_FW(CURSIZE, size);
11061 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11062 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
11064 plane->cursor.base = base;
11065 plane->cursor.size = size;
11066 plane->cursor.cntl = cntl;
11068 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11071 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11074 static void i845_disable_cursor(struct intel_plane *plane,
11075 const struct intel_crtc_state *crtc_state)
11077 i845_update_cursor(plane, crtc_state, NULL);
11080 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11083 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11084 enum intel_display_power_domain power_domain;
11085 intel_wakeref_t wakeref;
11088 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11089 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11093 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11097 intel_display_power_put(dev_priv, power_domain, wakeref);
11102 static unsigned int
11103 i9xx_cursor_max_stride(struct intel_plane *plane,
11104 u32 pixel_format, u64 modifier,
11105 unsigned int rotation)
11107 return plane->base.dev->mode_config.cursor_width * 4;
11110 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11112 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11113 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11116 if (INTEL_GEN(dev_priv) >= 11)
11119 if (crtc_state->gamma_enable)
11120 cntl = MCURSOR_GAMMA_ENABLE;
11122 if (crtc_state->csc_enable)
11123 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11125 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11126 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11131 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11132 const struct intel_plane_state *plane_state)
11134 struct drm_i915_private *dev_priv =
11135 to_i915(plane_state->uapi.plane->dev);
11138 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11139 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11141 switch (drm_rect_width(&plane_state->uapi.dst)) {
11143 cntl |= MCURSOR_MODE_64_ARGB_AX;
11146 cntl |= MCURSOR_MODE_128_ARGB_AX;
11149 cntl |= MCURSOR_MODE_256_ARGB_AX;
11152 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11156 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11157 cntl |= MCURSOR_ROTATE_180;
11162 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11164 struct drm_i915_private *dev_priv =
11165 to_i915(plane_state->uapi.plane->dev);
11166 int width = drm_rect_width(&plane_state->uapi.dst);
11167 int height = drm_rect_height(&plane_state->uapi.dst);
11169 if (!intel_cursor_size_ok(plane_state))
11172 /* Cursor width is limited to a few power-of-two sizes */
11183 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11184 * height from 8 lines up to the cursor width, when the
11185 * cursor is not rotated. Everything else requires square
11188 if (HAS_CUR_FBC(dev_priv) &&
11189 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11190 if (height < 8 || height > width)
11193 if (height != width)
11200 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11201 struct intel_plane_state *plane_state)
11203 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11204 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11205 const struct drm_framebuffer *fb = plane_state->hw.fb;
11206 enum pipe pipe = plane->pipe;
11209 ret = intel_check_cursor(crtc_state, plane_state);
11213 /* if we want to turn off the cursor ignore width and height */
11217 /* Check for which cursor types we support */
11218 if (!i9xx_cursor_size_ok(plane_state)) {
11219 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11220 drm_rect_width(&plane_state->uapi.dst),
11221 drm_rect_height(&plane_state->uapi.dst));
11225 WARN_ON(plane_state->uapi.visible &&
11226 plane_state->color_plane[0].stride != fb->pitches[0]);
11228 if (fb->pitches[0] !=
11229 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11230 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
11232 drm_rect_width(&plane_state->uapi.dst));
11237 * There's something wrong with the cursor on CHV pipe C.
11238 * If it straddles the left edge of the screen then
11239 * moving it away from the edge or disabling it often
11240 * results in a pipe underrun, and often that can lead to
11241 * dead pipe (constant underrun reported, and it scans
11242 * out just a solid color). To recover from that, the
11243 * display power well must be turned off and on again.
11244 * Refuse the put the cursor into that compromised position.
11246 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11247 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11248 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11252 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11257 static void i9xx_update_cursor(struct intel_plane *plane,
11258 const struct intel_crtc_state *crtc_state,
11259 const struct intel_plane_state *plane_state)
11261 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11262 enum pipe pipe = plane->pipe;
11263 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11264 unsigned long irqflags;
11266 if (plane_state && plane_state->uapi.visible) {
11267 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11268 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11270 cntl = plane_state->ctl |
11271 i9xx_cursor_ctl_crtc(crtc_state);
11273 if (width != height)
11274 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11276 base = intel_cursor_base(plane_state);
11277 pos = intel_cursor_position(plane_state);
11280 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11283 * On some platforms writing CURCNTR first will also
11284 * cause CURPOS to be armed by the CURBASE write.
11285 * Without the CURCNTR write the CURPOS write would
11286 * arm itself. Thus we always update CURCNTR before
11289 * On other platforms CURPOS always requires the
11290 * CURBASE write to arm the update. Additonally
11291 * a write to any of the cursor register will cancel
11292 * an already armed cursor update. Thus leaving out
11293 * the CURBASE write after CURPOS could lead to a
11294 * cursor that doesn't appear to move, or even change
11295 * shape. Thus we always write CURBASE.
11297 * The other registers are armed by by the CURBASE write
11298 * except when the plane is getting enabled at which time
11299 * the CURCNTR write arms the update.
11302 if (INTEL_GEN(dev_priv) >= 9)
11303 skl_write_cursor_wm(plane, crtc_state);
11305 if (plane->cursor.base != base ||
11306 plane->cursor.size != fbc_ctl ||
11307 plane->cursor.cntl != cntl) {
11308 if (HAS_CUR_FBC(dev_priv))
11309 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
11310 I915_WRITE_FW(CURCNTR(pipe), cntl);
11311 I915_WRITE_FW(CURPOS(pipe), pos);
11312 I915_WRITE_FW(CURBASE(pipe), base);
11314 plane->cursor.base = base;
11315 plane->cursor.size = fbc_ctl;
11316 plane->cursor.cntl = cntl;
11318 I915_WRITE_FW(CURPOS(pipe), pos);
11319 I915_WRITE_FW(CURBASE(pipe), base);
11322 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11325 static void i9xx_disable_cursor(struct intel_plane *plane,
11326 const struct intel_crtc_state *crtc_state)
11328 i9xx_update_cursor(plane, crtc_state, NULL);
11331 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11334 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11335 enum intel_display_power_domain power_domain;
11336 intel_wakeref_t wakeref;
11341 * Not 100% correct for planes that can move between pipes,
11342 * but that's only the case for gen2-3 which don't have any
11343 * display power wells.
11345 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11346 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11350 val = I915_READ(CURCNTR(plane->pipe));
11352 ret = val & MCURSOR_MODE;
11354 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11355 *pipe = plane->pipe;
11357 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11358 MCURSOR_PIPE_SELECT_SHIFT;
11360 intel_display_power_put(dev_priv, power_domain, wakeref);
11365 /* VESA 640x480x72Hz mode to set on the pipe */
11366 static const struct drm_display_mode load_detect_mode = {
11367 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11368 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11371 struct drm_framebuffer *
11372 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11373 struct drm_mode_fb_cmd2 *mode_cmd)
11375 struct intel_framebuffer *intel_fb;
11378 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11380 return ERR_PTR(-ENOMEM);
11382 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11386 return &intel_fb->base;
11390 return ERR_PTR(ret);
11393 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11394 struct drm_crtc *crtc)
11396 struct drm_plane *plane;
11397 struct drm_plane_state *plane_state;
11400 ret = drm_atomic_add_affected_planes(state, crtc);
11404 for_each_new_plane_in_state(state, plane, plane_state, i) {
11405 if (plane_state->crtc != crtc)
11408 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11412 drm_atomic_set_fb_for_plane(plane_state, NULL);
11418 int intel_get_load_detect_pipe(struct drm_connector *connector,
11419 struct intel_load_detect_pipe *old,
11420 struct drm_modeset_acquire_ctx *ctx)
11422 struct intel_crtc *intel_crtc;
11423 struct intel_encoder *intel_encoder =
11424 intel_attached_encoder(connector);
11425 struct drm_crtc *possible_crtc;
11426 struct drm_encoder *encoder = &intel_encoder->base;
11427 struct drm_crtc *crtc = NULL;
11428 struct drm_device *dev = encoder->dev;
11429 struct drm_i915_private *dev_priv = to_i915(dev);
11430 struct drm_mode_config *config = &dev->mode_config;
11431 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11432 struct drm_connector_state *connector_state;
11433 struct intel_crtc_state *crtc_state;
11436 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11437 connector->base.id, connector->name,
11438 encoder->base.id, encoder->name);
11440 old->restore_state = NULL;
11442 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11445 * Algorithm gets a little messy:
11447 * - if the connector already has an assigned crtc, use it (but make
11448 * sure it's on first)
11450 * - try to find the first unused crtc that can drive this connector,
11451 * and use that if we find one
11454 /* See if we already have a CRTC for this connector */
11455 if (connector->state->crtc) {
11456 crtc = connector->state->crtc;
11458 ret = drm_modeset_lock(&crtc->mutex, ctx);
11462 /* Make sure the crtc and connector are running */
11466 /* Find an unused one (if possible) */
11467 for_each_crtc(dev, possible_crtc) {
11469 if (!(encoder->possible_crtcs & (1 << i)))
11472 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11476 if (possible_crtc->state->enable) {
11477 drm_modeset_unlock(&possible_crtc->mutex);
11481 crtc = possible_crtc;
11486 * If we didn't find an unused CRTC, don't use any.
11489 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11495 intel_crtc = to_intel_crtc(crtc);
11497 state = drm_atomic_state_alloc(dev);
11498 restore_state = drm_atomic_state_alloc(dev);
11499 if (!state || !restore_state) {
11504 state->acquire_ctx = ctx;
11505 restore_state->acquire_ctx = ctx;
11507 connector_state = drm_atomic_get_connector_state(state, connector);
11508 if (IS_ERR(connector_state)) {
11509 ret = PTR_ERR(connector_state);
11513 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11517 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11518 if (IS_ERR(crtc_state)) {
11519 ret = PTR_ERR(crtc_state);
11523 crtc_state->uapi.active = true;
11525 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11526 &load_detect_mode);
11530 ret = intel_modeset_disable_planes(state, crtc);
11534 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11536 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11538 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11540 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11544 ret = drm_atomic_commit(state);
11546 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11550 old->restore_state = restore_state;
11551 drm_atomic_state_put(state);
11553 /* let the connector get through one full cycle before testing */
11554 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11559 drm_atomic_state_put(state);
11562 if (restore_state) {
11563 drm_atomic_state_put(restore_state);
11564 restore_state = NULL;
11567 if (ret == -EDEADLK)
11573 void intel_release_load_detect_pipe(struct drm_connector *connector,
11574 struct intel_load_detect_pipe *old,
11575 struct drm_modeset_acquire_ctx *ctx)
11577 struct intel_encoder *intel_encoder =
11578 intel_attached_encoder(connector);
11579 struct drm_encoder *encoder = &intel_encoder->base;
11580 struct drm_atomic_state *state = old->restore_state;
11583 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11584 connector->base.id, connector->name,
11585 encoder->base.id, encoder->name);
11590 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11592 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11593 drm_atomic_state_put(state);
11596 static int i9xx_pll_refclk(struct drm_device *dev,
11597 const struct intel_crtc_state *pipe_config)
11599 struct drm_i915_private *dev_priv = to_i915(dev);
11600 u32 dpll = pipe_config->dpll_hw_state.dpll;
11602 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11603 return dev_priv->vbt.lvds_ssc_freq;
11604 else if (HAS_PCH_SPLIT(dev_priv))
11606 else if (!IS_GEN(dev_priv, 2))
11612 /* Returns the clock of the currently programmed mode of the given pipe. */
11613 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11614 struct intel_crtc_state *pipe_config)
11616 struct drm_device *dev = crtc->base.dev;
11617 struct drm_i915_private *dev_priv = to_i915(dev);
11618 enum pipe pipe = crtc->pipe;
11619 u32 dpll = pipe_config->dpll_hw_state.dpll;
11623 int refclk = i9xx_pll_refclk(dev, pipe_config);
11625 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11626 fp = pipe_config->dpll_hw_state.fp0;
11628 fp = pipe_config->dpll_hw_state.fp1;
11630 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11631 if (IS_PINEVIEW(dev_priv)) {
11632 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11633 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11635 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11636 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11639 if (!IS_GEN(dev_priv, 2)) {
11640 if (IS_PINEVIEW(dev_priv))
11641 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11642 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11644 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11645 DPLL_FPA01_P1_POST_DIV_SHIFT);
11647 switch (dpll & DPLL_MODE_MASK) {
11648 case DPLLB_MODE_DAC_SERIAL:
11649 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11652 case DPLLB_MODE_LVDS:
11653 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11657 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11658 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11662 if (IS_PINEVIEW(dev_priv))
11663 port_clock = pnv_calc_dpll_params(refclk, &clock);
11665 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11667 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11668 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11671 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11672 DPLL_FPA01_P1_POST_DIV_SHIFT);
11674 if (lvds & LVDS_CLKB_POWER_UP)
11679 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11682 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11683 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11685 if (dpll & PLL_P2_DIVIDE_BY_4)
11691 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11695 * This value includes pixel_multiplier. We will use
11696 * port_clock to compute adjusted_mode.crtc_clock in the
11697 * encoder's get_config() function.
11699 pipe_config->port_clock = port_clock;
11702 int intel_dotclock_calculate(int link_freq,
11703 const struct intel_link_m_n *m_n)
11706 * The calculation for the data clock is:
11707 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11708 * But we want to avoid losing precison if possible, so:
11709 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11711 * and the link clock is simpler:
11712 * link_clock = (m * link_clock) / n
11718 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11721 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11722 struct intel_crtc_state *pipe_config)
11724 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11726 /* read out port_clock from the DPLL */
11727 i9xx_crtc_clock_get(crtc, pipe_config);
11730 * In case there is an active pipe without active ports,
11731 * we may need some idea for the dotclock anyway.
11732 * Calculate one based on the FDI configuration.
11734 pipe_config->hw.adjusted_mode.crtc_clock =
11735 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11736 &pipe_config->fdi_m_n);
11739 /* Returns the currently programmed mode of the given encoder. */
11740 struct drm_display_mode *
11741 intel_encoder_current_mode(struct intel_encoder *encoder)
11743 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11744 struct intel_crtc_state *crtc_state;
11745 struct drm_display_mode *mode;
11746 struct intel_crtc *crtc;
11749 if (!encoder->get_hw_state(encoder, &pipe))
11752 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11754 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11758 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11764 crtc_state->uapi.crtc = &crtc->base;
11766 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11772 encoder->get_config(encoder, crtc_state);
11774 intel_mode_from_pipe_config(mode, crtc_state);
11781 static void intel_crtc_destroy(struct drm_crtc *crtc)
11783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11785 drm_crtc_cleanup(crtc);
11790 * intel_wm_need_update - Check whether watermarks need updating
11791 * @cur: current plane state
11792 * @new: new plane state
11794 * Check current plane state versus the new one to determine whether
11795 * watermarks need to be recalculated.
11797 * Returns true or false.
11799 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11800 struct intel_plane_state *new)
11802 /* Update watermarks on tiling or size changes. */
11803 if (new->uapi.visible != cur->uapi.visible)
11806 if (!cur->hw.fb || !new->hw.fb)
11809 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
11810 cur->hw.rotation != new->hw.rotation ||
11811 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
11812 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
11813 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
11814 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
11820 static bool needs_scaling(const struct intel_plane_state *state)
11822 int src_w = drm_rect_width(&state->uapi.src) >> 16;
11823 int src_h = drm_rect_height(&state->uapi.src) >> 16;
11824 int dst_w = drm_rect_width(&state->uapi.dst);
11825 int dst_h = drm_rect_height(&state->uapi.dst);
11827 return (src_w != dst_w || src_h != dst_h);
11830 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11831 struct intel_crtc_state *crtc_state,
11832 const struct intel_plane_state *old_plane_state,
11833 struct intel_plane_state *plane_state)
11835 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11836 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11837 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11838 bool mode_changed = needs_modeset(crtc_state);
11839 bool was_crtc_enabled = old_crtc_state->hw.active;
11840 bool is_crtc_enabled = crtc_state->hw.active;
11841 bool turn_off, turn_on, visible, was_visible;
11844 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11845 ret = skl_update_scaler_plane(crtc_state, plane_state);
11850 was_visible = old_plane_state->uapi.visible;
11851 visible = plane_state->uapi.visible;
11853 if (!was_crtc_enabled && WARN_ON(was_visible))
11854 was_visible = false;
11857 * Visibility is calculated as if the crtc was on, but
11858 * after scaler setup everything depends on it being off
11859 * when the crtc isn't active.
11861 * FIXME this is wrong for watermarks. Watermarks should also
11862 * be computed as if the pipe would be active. Perhaps move
11863 * per-plane wm computation to the .check_plane() hook, and
11864 * only combine the results from all planes in the current place?
11866 if (!is_crtc_enabled) {
11867 plane_state->uapi.visible = visible = false;
11868 crtc_state->active_planes &= ~BIT(plane->id);
11869 crtc_state->data_rate[plane->id] = 0;
11870 crtc_state->min_cdclk[plane->id] = 0;
11873 if (!was_visible && !visible)
11876 turn_off = was_visible && (!visible || mode_changed);
11877 turn_on = visible && (!was_visible || mode_changed);
11879 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11880 crtc->base.base.id, crtc->base.name,
11881 plane->base.base.id, plane->base.name,
11882 was_visible, visible,
11883 turn_off, turn_on, mode_changed);
11886 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11887 crtc_state->update_wm_pre = true;
11889 /* must disable cxsr around plane enable/disable */
11890 if (plane->id != PLANE_CURSOR)
11891 crtc_state->disable_cxsr = true;
11892 } else if (turn_off) {
11893 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11894 crtc_state->update_wm_post = true;
11896 /* must disable cxsr around plane enable/disable */
11897 if (plane->id != PLANE_CURSOR)
11898 crtc_state->disable_cxsr = true;
11899 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11900 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11901 /* FIXME bollocks */
11902 crtc_state->update_wm_pre = true;
11903 crtc_state->update_wm_post = true;
11907 if (visible || was_visible)
11908 crtc_state->fb_bits |= plane->frontbuffer_bit;
11911 * ILK/SNB DVSACNTR/Sprite Enable
11912 * IVB SPR_CTL/Sprite Enable
11913 * "When in Self Refresh Big FIFO mode, a write to enable the
11914 * plane will be internally buffered and delayed while Big FIFO
11915 * mode is exiting."
11917 * Which means that enabling the sprite can take an extra frame
11918 * when we start in big FIFO mode (LP1+). Thus we need to drop
11919 * down to LP0 and wait for vblank in order to make sure the
11920 * sprite gets enabled on the next vblank after the register write.
11921 * Doing otherwise would risk enabling the sprite one frame after
11922 * we've already signalled flip completion. We can resume LP1+
11923 * once the sprite has been enabled.
11926 * WaCxSRDisabledForSpriteScaling:ivb
11927 * IVB SPR_SCALE/Scaling Enable
11928 * "Low Power watermarks must be disabled for at least one
11929 * frame before enabling sprite scaling, and kept disabled
11930 * until sprite scaling is disabled."
11932 * ILK/SNB DVSASCALE/Scaling Enable
11933 * "When in Self Refresh Big FIFO mode, scaling enable will be
11934 * masked off while Big FIFO mode is exiting."
11936 * Despite the w/a only being listed for IVB we assume that
11937 * the ILK/SNB note has similar ramifications, hence we apply
11938 * the w/a on all three platforms.
11940 * With experimental results seems this is needed also for primary
11941 * plane, not only sprite plane.
11943 if (plane->id != PLANE_CURSOR &&
11944 (IS_GEN_RANGE(dev_priv, 5, 6) ||
11945 IS_IVYBRIDGE(dev_priv)) &&
11946 (turn_on || (!needs_scaling(old_plane_state) &&
11947 needs_scaling(plane_state))))
11948 crtc_state->disable_lp_wm = true;
11953 static bool encoders_cloneable(const struct intel_encoder *a,
11954 const struct intel_encoder *b)
11956 /* masks could be asymmetric, so check both ways */
11957 return a == b || (a->cloneable & (1 << b->type) &&
11958 b->cloneable & (1 << a->type));
11961 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11962 struct intel_crtc *crtc,
11963 struct intel_encoder *encoder)
11965 struct intel_encoder *source_encoder;
11966 struct drm_connector *connector;
11967 struct drm_connector_state *connector_state;
11970 for_each_new_connector_in_state(state, connector, connector_state, i) {
11971 if (connector_state->crtc != &crtc->base)
11975 to_intel_encoder(connector_state->best_encoder);
11976 if (!encoders_cloneable(encoder, source_encoder))
11983 static int icl_add_linked_planes(struct intel_atomic_state *state)
11985 struct intel_plane *plane, *linked;
11986 struct intel_plane_state *plane_state, *linked_plane_state;
11989 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11990 linked = plane_state->planar_linked_plane;
11995 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11996 if (IS_ERR(linked_plane_state))
11997 return PTR_ERR(linked_plane_state);
11999 WARN_ON(linked_plane_state->planar_linked_plane != plane);
12000 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
12006 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12010 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12011 struct intel_plane *plane, *linked;
12012 struct intel_plane_state *plane_state;
12015 if (INTEL_GEN(dev_priv) < 11)
12019 * Destroy all old plane links and make the slave plane invisible
12020 * in the crtc_state->active_planes mask.
12022 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12023 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12026 plane_state->planar_linked_plane = NULL;
12027 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12028 crtc_state->active_planes &= ~BIT(plane->id);
12029 crtc_state->update_planes |= BIT(plane->id);
12032 plane_state->planar_slave = false;
12035 if (!crtc_state->nv12_planes)
12038 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12039 struct intel_plane_state *linked_state = NULL;
12041 if (plane->pipe != crtc->pipe ||
12042 !(crtc_state->nv12_planes & BIT(plane->id)))
12045 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12046 if (!icl_is_nv12_y_plane(linked->id))
12049 if (crtc_state->active_planes & BIT(linked->id))
12052 linked_state = intel_atomic_get_plane_state(state, linked);
12053 if (IS_ERR(linked_state))
12054 return PTR_ERR(linked_state);
12059 if (!linked_state) {
12060 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
12061 hweight8(crtc_state->nv12_planes));
12066 plane_state->planar_linked_plane = linked;
12068 linked_state->planar_slave = true;
12069 linked_state->planar_linked_plane = plane;
12070 crtc_state->active_planes |= BIT(linked->id);
12071 crtc_state->update_planes |= BIT(linked->id);
12072 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
12074 /* Copy parameters to slave plane */
12075 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12076 linked_state->color_ctl = plane_state->color_ctl;
12077 linked_state->color_plane[0] = plane_state->color_plane[0];
12079 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12080 linked_state->uapi.src = plane_state->uapi.src;
12081 linked_state->uapi.dst = plane_state->uapi.dst;
12083 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12084 if (linked->id == PLANE_SPRITE5)
12085 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12086 else if (linked->id == PLANE_SPRITE4)
12087 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12089 MISSING_CASE(linked->id);
12096 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12098 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12099 struct intel_atomic_state *state =
12100 to_intel_atomic_state(new_crtc_state->uapi.state);
12101 const struct intel_crtc_state *old_crtc_state =
12102 intel_atomic_get_old_crtc_state(state, crtc);
12104 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12107 static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
12109 struct drm_crtc *crtc = crtc_state->uapi.crtc;
12110 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12111 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12112 struct drm_connector *master_connector, *connector;
12113 struct drm_connector_state *connector_state;
12114 struct drm_connector_list_iter conn_iter;
12115 struct drm_crtc *master_crtc = NULL;
12116 struct drm_crtc_state *master_crtc_state;
12117 struct intel_crtc_state *master_pipe_config;
12118 int i, tile_group_id;
12120 if (INTEL_GEN(dev_priv) < 11)
12124 * In case of tiled displays there could be one or more slaves but there is
12125 * only one master. Lets make the CRTC used by the connector corresponding
12126 * to the last horizonal and last vertical tile a master/genlock CRTC.
12127 * All the other CRTCs corresponding to other tiles of the same Tile group
12128 * are the slave CRTCs and hold a pointer to their genlock CRTC.
12130 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
12131 if (connector_state->crtc != crtc)
12133 if (!connector->has_tile)
12135 if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
12136 crtc_state->hw.mode.vdisplay != connector->tile_v_size)
12138 if (connector->tile_h_loc == connector->num_h_tile - 1 &&
12139 connector->tile_v_loc == connector->num_v_tile - 1)
12141 crtc_state->sync_mode_slaves_mask = 0;
12142 tile_group_id = connector->tile_group->id;
12143 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
12144 drm_for_each_connector_iter(master_connector, &conn_iter) {
12145 struct drm_connector_state *master_conn_state = NULL;
12147 if (!master_connector->has_tile)
12149 if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
12150 master_connector->tile_v_loc != master_connector->num_v_tile - 1)
12152 if (master_connector->tile_group->id != tile_group_id)
12155 master_conn_state = drm_atomic_get_connector_state(&state->base,
12157 if (IS_ERR(master_conn_state)) {
12158 drm_connector_list_iter_end(&conn_iter);
12159 return PTR_ERR(master_conn_state);
12161 if (master_conn_state->crtc) {
12162 master_crtc = master_conn_state->crtc;
12166 drm_connector_list_iter_end(&conn_iter);
12168 if (!master_crtc) {
12169 DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
12170 connector_state->crtc->base.id);
12174 master_crtc_state = drm_atomic_get_crtc_state(&state->base,
12176 if (IS_ERR(master_crtc_state))
12177 return PTR_ERR(master_crtc_state);
12179 master_pipe_config = to_intel_crtc_state(master_crtc_state);
12180 crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
12181 master_pipe_config->sync_mode_slaves_mask |=
12182 BIT(crtc_state->cpu_transcoder);
12183 DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
12184 transcoder_name(crtc_state->master_transcoder),
12185 crtc_state->uapi.crtc->base.id,
12186 master_pipe_config->sync_mode_slaves_mask);
12192 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12193 struct intel_crtc *crtc)
12195 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12196 struct intel_crtc_state *crtc_state =
12197 intel_atomic_get_new_crtc_state(state, crtc);
12198 bool mode_changed = needs_modeset(crtc_state);
12201 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12202 mode_changed && !crtc_state->hw.active)
12203 crtc_state->update_wm_post = true;
12205 if (mode_changed && crtc_state->hw.enable &&
12206 dev_priv->display.crtc_compute_clock &&
12207 !WARN_ON(crtc_state->shared_dpll)) {
12208 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12214 * May need to update pipe gamma enable bits
12215 * when C8 planes are getting enabled/disabled.
12217 if (c8_planes_changed(crtc_state))
12218 crtc_state->uapi.color_mgmt_changed = true;
12220 if (mode_changed || crtc_state->update_pipe ||
12221 crtc_state->uapi.color_mgmt_changed) {
12222 ret = intel_color_check(crtc_state);
12228 if (dev_priv->display.compute_pipe_wm) {
12229 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12231 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12236 if (dev_priv->display.compute_intermediate_wm) {
12237 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12241 * Calculate 'intermediate' watermarks that satisfy both the
12242 * old state and the new state. We can program these
12245 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12247 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12252 if (INTEL_GEN(dev_priv) >= 9) {
12253 if (mode_changed || crtc_state->update_pipe)
12254 ret = skl_update_scaler_crtc(crtc_state);
12256 ret = intel_atomic_setup_scalers(dev_priv, crtc,
12260 if (HAS_IPS(dev_priv))
12261 crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
12266 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12268 struct intel_connector *connector;
12269 struct drm_connector_list_iter conn_iter;
12271 drm_connector_list_iter_begin(dev, &conn_iter);
12272 for_each_intel_connector_iter(connector, &conn_iter) {
12273 if (connector->base.state->crtc)
12274 drm_connector_put(&connector->base);
12276 if (connector->base.encoder) {
12277 connector->base.state->best_encoder =
12278 connector->base.encoder;
12279 connector->base.state->crtc =
12280 connector->base.encoder->crtc;
12282 drm_connector_get(&connector->base);
12284 connector->base.state->best_encoder = NULL;
12285 connector->base.state->crtc = NULL;
12288 drm_connector_list_iter_end(&conn_iter);
12292 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12293 struct intel_crtc_state *pipe_config)
12295 struct drm_connector *connector = conn_state->connector;
12296 const struct drm_display_info *info = &connector->display_info;
12299 switch (conn_state->max_bpc) {
12316 if (bpp < pipe_config->pipe_bpp) {
12317 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12318 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12319 connector->base.id, connector->name,
12320 bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
12321 pipe_config->pipe_bpp);
12323 pipe_config->pipe_bpp = bpp;
12330 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12331 struct intel_crtc_state *pipe_config)
12333 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12334 struct drm_atomic_state *state = pipe_config->uapi.state;
12335 struct drm_connector *connector;
12336 struct drm_connector_state *connector_state;
12339 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12340 IS_CHERRYVIEW(dev_priv)))
12342 else if (INTEL_GEN(dev_priv) >= 5)
12347 pipe_config->pipe_bpp = bpp;
12349 /* Clamp display bpp to connector max bpp */
12350 for_each_new_connector_in_state(state, connector, connector_state, i) {
12353 if (connector_state->crtc != &crtc->base)
12356 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12364 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12366 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12367 "type: 0x%x flags: 0x%x\n",
12369 mode->crtc_hdisplay, mode->crtc_hsync_start,
12370 mode->crtc_hsync_end, mode->crtc_htotal,
12371 mode->crtc_vdisplay, mode->crtc_vsync_start,
12372 mode->crtc_vsync_end, mode->crtc_vtotal,
12373 mode->type, mode->flags);
12377 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12378 const char *id, unsigned int lane_count,
12379 const struct intel_link_m_n *m_n)
12381 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12383 m_n->gmch_m, m_n->gmch_n,
12384 m_n->link_m, m_n->link_n, m_n->tu);
12388 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12389 const union hdmi_infoframe *frame)
12391 if ((drm_debug & DRM_UT_KMS) == 0)
12394 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12397 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12399 static const char * const output_type_str[] = {
12400 OUTPUT_TYPE(UNUSED),
12401 OUTPUT_TYPE(ANALOG),
12405 OUTPUT_TYPE(TVOUT),
12411 OUTPUT_TYPE(DP_MST),
12416 static void snprintf_output_types(char *buf, size_t len,
12417 unsigned int output_types)
12424 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12427 if ((output_types & BIT(i)) == 0)
12430 r = snprintf(str, len, "%s%s",
12431 str != buf ? "," : "", output_type_str[i]);
12437 output_types &= ~BIT(i);
12440 WARN_ON_ONCE(output_types != 0);
12443 static const char * const output_format_str[] = {
12444 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12445 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12446 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12447 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12450 static const char *output_formats(enum intel_output_format format)
12452 if (format >= ARRAY_SIZE(output_format_str))
12453 format = INTEL_OUTPUT_FORMAT_INVALID;
12454 return output_format_str[format];
12457 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12459 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12460 const struct drm_framebuffer *fb = plane_state->hw.fb;
12461 struct drm_format_name_buf format_name;
12464 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12465 plane->base.base.id, plane->base.name,
12466 yesno(plane_state->uapi.visible));
12470 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12471 plane->base.base.id, plane->base.name,
12472 fb->base.id, fb->width, fb->height,
12473 drm_get_format_name(fb->format->format, &format_name),
12474 yesno(plane_state->uapi.visible));
12475 DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12476 plane_state->hw.rotation, plane_state->scaler_id);
12477 if (plane_state->uapi.visible)
12478 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12479 DRM_RECT_FP_ARG(&plane_state->uapi.src),
12480 DRM_RECT_ARG(&plane_state->uapi.dst));
12483 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12484 struct intel_atomic_state *state,
12485 const char *context)
12487 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12489 const struct intel_plane_state *plane_state;
12490 struct intel_plane *plane;
12494 DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12495 crtc->base.base.id, crtc->base.name,
12496 yesno(pipe_config->hw.enable), context);
12498 if (!pipe_config->hw.enable)
12501 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12502 DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12503 yesno(pipe_config->hw.active),
12504 buf, pipe_config->output_types,
12505 output_formats(pipe_config->output_format));
12507 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12508 transcoder_name(pipe_config->cpu_transcoder),
12509 pipe_config->pipe_bpp, pipe_config->dither);
12511 if (pipe_config->has_pch_encoder)
12512 intel_dump_m_n_config(pipe_config, "fdi",
12513 pipe_config->fdi_lanes,
12514 &pipe_config->fdi_m_n);
12516 if (intel_crtc_has_dp_encoder(pipe_config)) {
12517 intel_dump_m_n_config(pipe_config, "dp m_n",
12518 pipe_config->lane_count, &pipe_config->dp_m_n);
12519 if (pipe_config->has_drrs)
12520 intel_dump_m_n_config(pipe_config, "dp m2_n2",
12521 pipe_config->lane_count,
12522 &pipe_config->dp_m2_n2);
12525 DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12526 pipe_config->has_audio, pipe_config->has_infoframe,
12527 pipe_config->infoframes.enable);
12529 if (pipe_config->infoframes.enable &
12530 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12531 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12532 if (pipe_config->infoframes.enable &
12533 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12534 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12535 if (pipe_config->infoframes.enable &
12536 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12537 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12538 if (pipe_config->infoframes.enable &
12539 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12540 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12542 DRM_DEBUG_KMS("requested mode:\n");
12543 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
12544 DRM_DEBUG_KMS("adjusted mode:\n");
12545 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
12546 intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
12547 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12548 pipe_config->port_clock,
12549 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12550 pipe_config->pixel_rate);
12552 if (INTEL_GEN(dev_priv) >= 9)
12553 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12555 pipe_config->scaler_state.scaler_users,
12556 pipe_config->scaler_state.scaler_id);
12558 if (HAS_GMCH(dev_priv))
12559 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12560 pipe_config->gmch_pfit.control,
12561 pipe_config->gmch_pfit.pgm_ratios,
12562 pipe_config->gmch_pfit.lvds_border_bits);
12564 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12565 pipe_config->pch_pfit.pos,
12566 pipe_config->pch_pfit.size,
12567 enableddisabled(pipe_config->pch_pfit.enabled),
12568 yesno(pipe_config->pch_pfit.force_thru));
12570 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12571 pipe_config->ips_enabled, pipe_config->double_wide);
12573 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12575 if (IS_CHERRYVIEW(dev_priv))
12576 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12577 pipe_config->cgm_mode, pipe_config->gamma_mode,
12578 pipe_config->gamma_enable, pipe_config->csc_enable);
12580 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12581 pipe_config->csc_mode, pipe_config->gamma_mode,
12582 pipe_config->gamma_enable, pipe_config->csc_enable);
12588 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12589 if (plane->pipe == crtc->pipe)
12590 intel_dump_plane_state(plane_state);
12594 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12596 struct drm_device *dev = state->base.dev;
12597 struct drm_connector *connector;
12598 struct drm_connector_list_iter conn_iter;
12599 unsigned int used_ports = 0;
12600 unsigned int used_mst_ports = 0;
12604 * We're going to peek into connector->state,
12605 * hence connection_mutex must be held.
12607 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
12610 * Walk the connector list instead of the encoder
12611 * list to detect the problem on ddi platforms
12612 * where there's just one encoder per digital port.
12614 drm_connector_list_iter_begin(dev, &conn_iter);
12615 drm_for_each_connector_iter(connector, &conn_iter) {
12616 struct drm_connector_state *connector_state;
12617 struct intel_encoder *encoder;
12620 drm_atomic_get_new_connector_state(&state->base,
12622 if (!connector_state)
12623 connector_state = connector->state;
12625 if (!connector_state->best_encoder)
12628 encoder = to_intel_encoder(connector_state->best_encoder);
12630 WARN_ON(!connector_state->crtc);
12632 switch (encoder->type) {
12633 unsigned int port_mask;
12634 case INTEL_OUTPUT_DDI:
12635 if (WARN_ON(!HAS_DDI(to_i915(dev))))
12637 /* else, fall through */
12638 case INTEL_OUTPUT_DP:
12639 case INTEL_OUTPUT_HDMI:
12640 case INTEL_OUTPUT_EDP:
12641 port_mask = 1 << encoder->port;
12643 /* the same port mustn't appear more than once */
12644 if (used_ports & port_mask)
12647 used_ports |= port_mask;
12649 case INTEL_OUTPUT_DP_MST:
12651 1 << encoder->port;
12657 drm_connector_list_iter_end(&conn_iter);
12659 /* can't mix MST and SST/HDMI on the same port */
12660 if (used_ports & used_mst_ports)
12667 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
12669 intel_crtc_copy_color_blobs(crtc_state);
12673 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
12675 crtc_state->hw.enable = crtc_state->uapi.enable;
12676 crtc_state->hw.active = crtc_state->uapi.active;
12677 crtc_state->hw.mode = crtc_state->uapi.mode;
12678 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
12679 intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
12682 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
12684 crtc_state->uapi.enable = crtc_state->hw.enable;
12685 crtc_state->uapi.active = crtc_state->hw.active;
12686 WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
12688 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
12690 /* copy color blobs to uapi */
12691 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
12692 crtc_state->hw.degamma_lut);
12693 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
12694 crtc_state->hw.gamma_lut);
12695 drm_property_replace_blob(&crtc_state->uapi.ctm,
12696 crtc_state->hw.ctm);
12700 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
12702 struct drm_i915_private *dev_priv =
12703 to_i915(crtc_state->uapi.crtc->dev);
12704 struct intel_crtc_state *saved_state;
12706 saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12710 /* free the old crtc_state->hw members */
12711 intel_crtc_free_hw_state(crtc_state);
12713 /* FIXME: before the switch to atomic started, a new pipe_config was
12714 * kzalloc'd. Code that depends on any field being zero should be
12715 * fixed, so that the crtc_state can be safely duplicated. For now,
12716 * only fields that are know to not cause problems are preserved. */
12718 saved_state->uapi = crtc_state->uapi;
12719 saved_state->scaler_state = crtc_state->scaler_state;
12720 saved_state->shared_dpll = crtc_state->shared_dpll;
12721 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12722 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12723 sizeof(saved_state->icl_port_dplls));
12724 saved_state->crc_enabled = crtc_state->crc_enabled;
12725 if (IS_G4X(dev_priv) ||
12726 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12727 saved_state->wm = crtc_state->wm;
12729 * Save the slave bitmask which gets filled for master crtc state during
12730 * slave atomic check call.
12732 if (is_trans_port_sync_master(crtc_state))
12733 saved_state->sync_mode_slaves_mask =
12734 crtc_state->sync_mode_slaves_mask;
12736 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
12737 kfree(saved_state);
12739 intel_crtc_copy_uapi_to_hw_state(crtc_state);
12745 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12747 struct drm_crtc *crtc = pipe_config->uapi.crtc;
12748 struct drm_atomic_state *state = pipe_config->uapi.state;
12749 struct intel_encoder *encoder;
12750 struct drm_connector *connector;
12751 struct drm_connector_state *connector_state;
12756 pipe_config->cpu_transcoder =
12757 (enum transcoder) to_intel_crtc(crtc)->pipe;
12760 * Sanitize sync polarity flags based on requested ones. If neither
12761 * positive or negative polarity is requested, treat this as meaning
12762 * negative polarity.
12764 if (!(pipe_config->hw.adjusted_mode.flags &
12765 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12766 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12768 if (!(pipe_config->hw.adjusted_mode.flags &
12769 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12770 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12772 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12777 base_bpp = pipe_config->pipe_bpp;
12780 * Determine the real pipe dimensions. Note that stereo modes can
12781 * increase the actual pipe size due to the frame doubling and
12782 * insertion of additional space for blanks between the frame. This
12783 * is stored in the crtc timings. We use the requested mode to do this
12784 * computation to clearly distinguish it from the adjusted mode, which
12785 * can be changed by the connectors in the below retry loop.
12787 drm_mode_get_hv_timing(&pipe_config->hw.mode,
12788 &pipe_config->pipe_src_w,
12789 &pipe_config->pipe_src_h);
12791 for_each_new_connector_in_state(state, connector, connector_state, i) {
12792 if (connector_state->crtc != crtc)
12795 encoder = to_intel_encoder(connector_state->best_encoder);
12797 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12798 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12803 * Determine output_types before calling the .compute_config()
12804 * hooks so that the hooks can use this information safely.
12806 if (encoder->compute_output_type)
12807 pipe_config->output_types |=
12808 BIT(encoder->compute_output_type(encoder, pipe_config,
12811 pipe_config->output_types |= BIT(encoder->type);
12815 /* Ensure the port clock defaults are reset when retrying. */
12816 pipe_config->port_clock = 0;
12817 pipe_config->pixel_multiplier = 1;
12819 /* Fill in default crtc timings, allow encoders to overwrite them. */
12820 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
12821 CRTC_STEREO_DOUBLE);
12823 /* Set the crtc_state defaults for trans_port_sync */
12824 pipe_config->master_transcoder = INVALID_TRANSCODER;
12825 ret = icl_add_sync_mode_crtcs(pipe_config);
12827 DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
12832 /* Pass our mode to the connectors and the CRTC to give them a chance to
12833 * adjust it according to limitations or connector properties, and also
12834 * a chance to reject the mode entirely.
12836 for_each_new_connector_in_state(state, connector, connector_state, i) {
12837 if (connector_state->crtc != crtc)
12840 encoder = to_intel_encoder(connector_state->best_encoder);
12841 ret = encoder->compute_config(encoder, pipe_config,
12844 if (ret != -EDEADLK)
12845 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12851 /* Set default port clock if not overwritten by the encoder. Needs to be
12852 * done afterwards in case the encoder adjusts the mode. */
12853 if (!pipe_config->port_clock)
12854 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
12855 * pipe_config->pixel_multiplier;
12857 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12858 if (ret == -EDEADLK)
12861 DRM_DEBUG_KMS("CRTC fixup failed\n");
12865 if (ret == RETRY) {
12866 if (WARN(!retry, "loop in pipe configuration computation\n"))
12869 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12871 goto encoder_retry;
12874 /* Dithering seems to not pass-through bits correctly when it should, so
12875 * only enable it on 6bpc panels and when its not a compliance
12876 * test requesting 6bpc video pattern.
12878 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12879 !pipe_config->dither_force_disable;
12880 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12881 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12884 * Make drm_calc_timestamping_constants in
12885 * drm_atomic_helper_update_legacy_modeset_state() happy
12887 pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
12892 bool intel_fuzzy_clock_check(int clock1, int clock2)
12896 if (clock1 == clock2)
12899 if (!clock1 || !clock2)
12902 diff = abs(clock1 - clock2);
12904 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12911 intel_compare_m_n(unsigned int m, unsigned int n,
12912 unsigned int m2, unsigned int n2,
12915 if (m == m2 && n == n2)
12918 if (exact || !m || !n || !m2 || !n2)
12921 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12928 } else if (n < n2) {
12938 return intel_fuzzy_clock_check(m, m2);
12942 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12943 const struct intel_link_m_n *m2_n2,
12946 return m_n->tu == m2_n2->tu &&
12947 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12948 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12949 intel_compare_m_n(m_n->link_m, m_n->link_n,
12950 m2_n2->link_m, m2_n2->link_n, exact);
12954 intel_compare_infoframe(const union hdmi_infoframe *a,
12955 const union hdmi_infoframe *b)
12957 return memcmp(a, b, sizeof(*a)) == 0;
12961 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12962 bool fastset, const char *name,
12963 const union hdmi_infoframe *a,
12964 const union hdmi_infoframe *b)
12967 if ((drm_debug & DRM_UT_KMS) == 0)
12970 DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name);
12971 DRM_DEBUG_KMS("expected:\n");
12972 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12973 DRM_DEBUG_KMS("found:\n");
12974 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12976 DRM_ERROR("mismatch in %s infoframe\n", name);
12977 DRM_ERROR("expected:\n");
12978 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12979 DRM_ERROR("found:\n");
12980 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12984 static void __printf(4, 5)
12985 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
12986 const char *name, const char *format, ...)
12988 struct va_format vaf;
12991 va_start(args, format);
12996 DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
12997 crtc->base.base.id, crtc->base.name, name, &vaf);
12999 DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
13000 crtc->base.base.id, crtc->base.name, name, &vaf);
13005 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13007 if (i915_modparams.fastboot != -1)
13008 return i915_modparams.fastboot;
13010 /* Enable fastboot by default on Skylake and newer */
13011 if (INTEL_GEN(dev_priv) >= 9)
13014 /* Enable fastboot by default on VLV and CHV */
13015 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13018 /* Disabled by default on all others */
13023 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13024 const struct intel_crtc_state *pipe_config,
13027 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13028 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13031 bool fixup_inherited = fastset &&
13032 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
13033 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
13035 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13036 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
13040 #define PIPE_CONF_CHECK_X(name) do { \
13041 if (current_config->name != pipe_config->name) { \
13042 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13043 "(expected 0x%08x, found 0x%08x)", \
13044 current_config->name, \
13045 pipe_config->name); \
13050 #define PIPE_CONF_CHECK_I(name) do { \
13051 if (current_config->name != pipe_config->name) { \
13052 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13053 "(expected %i, found %i)", \
13054 current_config->name, \
13055 pipe_config->name); \
13060 #define PIPE_CONF_CHECK_BOOL(name) do { \
13061 if (current_config->name != pipe_config->name) { \
13062 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13063 "(expected %s, found %s)", \
13064 yesno(current_config->name), \
13065 yesno(pipe_config->name)); \
13071 * Checks state where we only read out the enabling, but not the entire
13072 * state itself (like full infoframes or ELD for audio). These states
13073 * require a full modeset on bootup to fix up.
13075 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13076 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13077 PIPE_CONF_CHECK_BOOL(name); \
13079 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13080 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13081 yesno(current_config->name), \
13082 yesno(pipe_config->name)); \
13087 #define PIPE_CONF_CHECK_P(name) do { \
13088 if (current_config->name != pipe_config->name) { \
13089 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13090 "(expected %p, found %p)", \
13091 current_config->name, \
13092 pipe_config->name); \
13097 #define PIPE_CONF_CHECK_M_N(name) do { \
13098 if (!intel_compare_link_m_n(¤t_config->name, \
13099 &pipe_config->name,\
13101 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13102 "(expected tu %i gmch %i/%i link %i/%i, " \
13103 "found tu %i, gmch %i/%i link %i/%i)", \
13104 current_config->name.tu, \
13105 current_config->name.gmch_m, \
13106 current_config->name.gmch_n, \
13107 current_config->name.link_m, \
13108 current_config->name.link_n, \
13109 pipe_config->name.tu, \
13110 pipe_config->name.gmch_m, \
13111 pipe_config->name.gmch_n, \
13112 pipe_config->name.link_m, \
13113 pipe_config->name.link_n); \
13118 /* This is required for BDW+ where there is only one set of registers for
13119 * switching between high and low RR.
13120 * This macro can be used whenever a comparison has to be made between one
13121 * hw state and multiple sw state variables.
13123 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13124 if (!intel_compare_link_m_n(¤t_config->name, \
13125 &pipe_config->name, !fastset) && \
13126 !intel_compare_link_m_n(¤t_config->alt_name, \
13127 &pipe_config->name, !fastset)) { \
13128 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13129 "(expected tu %i gmch %i/%i link %i/%i, " \
13130 "or tu %i gmch %i/%i link %i/%i, " \
13131 "found tu %i, gmch %i/%i link %i/%i)", \
13132 current_config->name.tu, \
13133 current_config->name.gmch_m, \
13134 current_config->name.gmch_n, \
13135 current_config->name.link_m, \
13136 current_config->name.link_n, \
13137 current_config->alt_name.tu, \
13138 current_config->alt_name.gmch_m, \
13139 current_config->alt_name.gmch_n, \
13140 current_config->alt_name.link_m, \
13141 current_config->alt_name.link_n, \
13142 pipe_config->name.tu, \
13143 pipe_config->name.gmch_m, \
13144 pipe_config->name.gmch_n, \
13145 pipe_config->name.link_m, \
13146 pipe_config->name.link_n); \
13151 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13152 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13153 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13154 "(%x) (expected %i, found %i)", \
13156 current_config->name & (mask), \
13157 pipe_config->name & (mask)); \
13162 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13163 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13164 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13165 "(expected %i, found %i)", \
13166 current_config->name, \
13167 pipe_config->name); \
13172 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13173 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
13174 &pipe_config->infoframes.name)) { \
13175 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13176 ¤t_config->infoframes.name, \
13177 &pipe_config->infoframes.name); \
13182 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13183 if (current_config->name1 != pipe_config->name1) { \
13184 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13185 "(expected %i, found %i, won't compare lut values)", \
13186 current_config->name1, \
13187 pipe_config->name1); \
13190 if (!intel_color_lut_equal(current_config->name2, \
13191 pipe_config->name2, pipe_config->name1, \
13192 bit_precision)) { \
13193 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13194 "hw_state doesn't match sw_state"); \
13200 #define PIPE_CONF_QUIRK(quirk) \
13201 ((current_config->quirks | pipe_config->quirks) & (quirk))
13203 PIPE_CONF_CHECK_I(cpu_transcoder);
13205 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13206 PIPE_CONF_CHECK_I(fdi_lanes);
13207 PIPE_CONF_CHECK_M_N(fdi_m_n);
13209 PIPE_CONF_CHECK_I(lane_count);
13210 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13212 if (INTEL_GEN(dev_priv) < 8) {
13213 PIPE_CONF_CHECK_M_N(dp_m_n);
13215 if (current_config->has_drrs)
13216 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13218 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13220 PIPE_CONF_CHECK_X(output_types);
13222 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13223 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13224 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13225 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13226 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13227 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13229 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13230 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13231 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13232 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13233 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13234 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13236 PIPE_CONF_CHECK_I(pixel_multiplier);
13237 PIPE_CONF_CHECK_I(output_format);
13238 PIPE_CONF_CHECK_I(dc3co_exitline);
13239 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13240 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13241 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13242 PIPE_CONF_CHECK_BOOL(limited_color_range);
13244 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13245 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13246 PIPE_CONF_CHECK_BOOL(has_infoframe);
13247 PIPE_CONF_CHECK_BOOL(fec_enable);
13249 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13251 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13252 DRM_MODE_FLAG_INTERLACE);
13254 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13255 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13256 DRM_MODE_FLAG_PHSYNC);
13257 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13258 DRM_MODE_FLAG_NHSYNC);
13259 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13260 DRM_MODE_FLAG_PVSYNC);
13261 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13262 DRM_MODE_FLAG_NVSYNC);
13265 PIPE_CONF_CHECK_X(gmch_pfit.control);
13266 /* pfit ratios are autocomputed by the hw on gen4+ */
13267 if (INTEL_GEN(dev_priv) < 4)
13268 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13269 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13272 * Changing the EDP transcoder input mux
13273 * (A_ONOFF vs. A_ON) requires a full modeset.
13275 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13278 PIPE_CONF_CHECK_I(pipe_src_w);
13279 PIPE_CONF_CHECK_I(pipe_src_h);
13281 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13282 if (current_config->pch_pfit.enabled) {
13283 PIPE_CONF_CHECK_X(pch_pfit.pos);
13284 PIPE_CONF_CHECK_X(pch_pfit.size);
13287 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13288 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13290 PIPE_CONF_CHECK_X(gamma_mode);
13291 if (IS_CHERRYVIEW(dev_priv))
13292 PIPE_CONF_CHECK_X(cgm_mode);
13294 PIPE_CONF_CHECK_X(csc_mode);
13295 PIPE_CONF_CHECK_BOOL(gamma_enable);
13296 PIPE_CONF_CHECK_BOOL(csc_enable);
13298 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13300 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13304 PIPE_CONF_CHECK_BOOL(double_wide);
13306 PIPE_CONF_CHECK_P(shared_dpll);
13307 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13308 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13309 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13310 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13311 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13312 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13313 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13314 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13315 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13316 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13317 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13318 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13319 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13320 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13321 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13322 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13323 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13324 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13325 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13326 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13327 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13328 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13329 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13330 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13331 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13332 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13333 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13334 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13335 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13336 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13337 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13339 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13340 PIPE_CONF_CHECK_X(dsi_pll.div);
13342 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13343 PIPE_CONF_CHECK_I(pipe_bpp);
13345 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13346 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13348 PIPE_CONF_CHECK_I(min_voltage_level);
13350 PIPE_CONF_CHECK_X(infoframes.enable);
13351 PIPE_CONF_CHECK_X(infoframes.gcp);
13352 PIPE_CONF_CHECK_INFOFRAME(avi);
13353 PIPE_CONF_CHECK_INFOFRAME(spd);
13354 PIPE_CONF_CHECK_INFOFRAME(hdmi);
13355 PIPE_CONF_CHECK_INFOFRAME(drm);
13357 PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
13358 PIPE_CONF_CHECK_I(master_transcoder);
13360 #undef PIPE_CONF_CHECK_X
13361 #undef PIPE_CONF_CHECK_I
13362 #undef PIPE_CONF_CHECK_BOOL
13363 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13364 #undef PIPE_CONF_CHECK_P
13365 #undef PIPE_CONF_CHECK_FLAGS
13366 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13367 #undef PIPE_CONF_CHECK_COLOR_LUT
13368 #undef PIPE_CONF_QUIRK
13373 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13374 const struct intel_crtc_state *pipe_config)
13376 if (pipe_config->has_pch_encoder) {
13377 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13378 &pipe_config->fdi_m_n);
13379 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13382 * FDI already provided one idea for the dotclock.
13383 * Yell if the encoder disagrees.
13385 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13386 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13387 fdi_dotclock, dotclock);
13391 static void verify_wm_state(struct intel_crtc *crtc,
13392 struct intel_crtc_state *new_crtc_state)
13394 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13395 struct skl_hw_state {
13396 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13397 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13398 struct skl_ddb_allocation ddb;
13399 struct skl_pipe_wm wm;
13401 struct skl_ddb_allocation *sw_ddb;
13402 struct skl_pipe_wm *sw_wm;
13403 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13404 const enum pipe pipe = crtc->pipe;
13405 int plane, level, max_level = ilk_wm_max_level(dev_priv);
13407 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13410 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13414 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13415 sw_wm = &new_crtc_state->wm.skl.optimal;
13417 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13419 skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13420 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13422 if (INTEL_GEN(dev_priv) >= 11 &&
13423 hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13424 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
13425 sw_ddb->enabled_slices,
13426 hw->ddb.enabled_slices);
13429 for_each_universal_plane(dev_priv, pipe, plane) {
13430 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13432 hw_plane_wm = &hw->wm.planes[plane];
13433 sw_plane_wm = &sw_wm->planes[plane];
13436 for (level = 0; level <= max_level; level++) {
13437 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13438 &sw_plane_wm->wm[level]))
13441 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13442 pipe_name(pipe), plane + 1, level,
13443 sw_plane_wm->wm[level].plane_en,
13444 sw_plane_wm->wm[level].plane_res_b,
13445 sw_plane_wm->wm[level].plane_res_l,
13446 hw_plane_wm->wm[level].plane_en,
13447 hw_plane_wm->wm[level].plane_res_b,
13448 hw_plane_wm->wm[level].plane_res_l);
13451 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13452 &sw_plane_wm->trans_wm)) {
13453 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13454 pipe_name(pipe), plane + 1,
13455 sw_plane_wm->trans_wm.plane_en,
13456 sw_plane_wm->trans_wm.plane_res_b,
13457 sw_plane_wm->trans_wm.plane_res_l,
13458 hw_plane_wm->trans_wm.plane_en,
13459 hw_plane_wm->trans_wm.plane_res_b,
13460 hw_plane_wm->trans_wm.plane_res_l);
13464 hw_ddb_entry = &hw->ddb_y[plane];
13465 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13467 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13468 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13469 pipe_name(pipe), plane + 1,
13470 sw_ddb_entry->start, sw_ddb_entry->end,
13471 hw_ddb_entry->start, hw_ddb_entry->end);
13477 * If the cursor plane isn't active, we may not have updated it's ddb
13478 * allocation. In that case since the ddb allocation will be updated
13479 * once the plane becomes visible, we can skip this check
13482 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13484 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13485 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13488 for (level = 0; level <= max_level; level++) {
13489 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13490 &sw_plane_wm->wm[level]))
13493 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13494 pipe_name(pipe), level,
13495 sw_plane_wm->wm[level].plane_en,
13496 sw_plane_wm->wm[level].plane_res_b,
13497 sw_plane_wm->wm[level].plane_res_l,
13498 hw_plane_wm->wm[level].plane_en,
13499 hw_plane_wm->wm[level].plane_res_b,
13500 hw_plane_wm->wm[level].plane_res_l);
13503 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13504 &sw_plane_wm->trans_wm)) {
13505 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13507 sw_plane_wm->trans_wm.plane_en,
13508 sw_plane_wm->trans_wm.plane_res_b,
13509 sw_plane_wm->trans_wm.plane_res_l,
13510 hw_plane_wm->trans_wm.plane_en,
13511 hw_plane_wm->trans_wm.plane_res_b,
13512 hw_plane_wm->trans_wm.plane_res_l);
13516 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13517 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13519 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13520 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13522 sw_ddb_entry->start, sw_ddb_entry->end,
13523 hw_ddb_entry->start, hw_ddb_entry->end);
13531 verify_connector_state(struct intel_atomic_state *state,
13532 struct intel_crtc *crtc)
13534 struct drm_connector *connector;
13535 struct drm_connector_state *new_conn_state;
13538 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13539 struct drm_encoder *encoder = connector->encoder;
13540 struct intel_crtc_state *crtc_state = NULL;
13542 if (new_conn_state->crtc != &crtc->base)
13546 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13548 intel_connector_verify_state(crtc_state, new_conn_state);
13550 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13551 "connector's atomic encoder doesn't match legacy encoder\n");
13556 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13558 struct intel_encoder *encoder;
13559 struct drm_connector *connector;
13560 struct drm_connector_state *old_conn_state, *new_conn_state;
13563 for_each_intel_encoder(&dev_priv->drm, encoder) {
13564 bool enabled = false, found = false;
13567 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13568 encoder->base.base.id,
13569 encoder->base.name);
13571 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13572 new_conn_state, i) {
13573 if (old_conn_state->best_encoder == &encoder->base)
13576 if (new_conn_state->best_encoder != &encoder->base)
13578 found = enabled = true;
13580 I915_STATE_WARN(new_conn_state->crtc !=
13581 encoder->base.crtc,
13582 "connector's crtc doesn't match encoder crtc\n");
13588 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13589 "encoder's enabled state mismatch "
13590 "(expected %i, found %i)\n",
13591 !!encoder->base.crtc, enabled);
13593 if (!encoder->base.crtc) {
13596 active = encoder->get_hw_state(encoder, &pipe);
13597 I915_STATE_WARN(active,
13598 "encoder detached but still enabled on pipe %c.\n",
13605 verify_crtc_state(struct intel_crtc *crtc,
13606 struct intel_crtc_state *old_crtc_state,
13607 struct intel_crtc_state *new_crtc_state)
13609 struct drm_device *dev = crtc->base.dev;
13610 struct drm_i915_private *dev_priv = to_i915(dev);
13611 struct intel_encoder *encoder;
13612 struct intel_crtc_state *pipe_config;
13613 struct drm_atomic_state *state;
13616 state = old_crtc_state->uapi.state;
13617 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
13618 intel_crtc_free_hw_state(old_crtc_state);
13620 pipe_config = old_crtc_state;
13621 memset(pipe_config, 0, sizeof(*pipe_config));
13622 pipe_config->uapi.crtc = &crtc->base;
13623 pipe_config->uapi.state = state;
13625 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13627 active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13629 /* we keep both pipes enabled on 830 */
13630 if (IS_I830(dev_priv))
13631 active = new_crtc_state->hw.active;
13633 I915_STATE_WARN(new_crtc_state->hw.active != active,
13634 "crtc active state doesn't match with hw state "
13635 "(expected %i, found %i)\n",
13636 new_crtc_state->hw.active, active);
13638 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
13639 "transitional active state does not match atomic hw state "
13640 "(expected %i, found %i)\n",
13641 new_crtc_state->hw.active, crtc->active);
13643 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13646 active = encoder->get_hw_state(encoder, &pipe);
13647 I915_STATE_WARN(active != new_crtc_state->hw.active,
13648 "[ENCODER:%i] active %i with crtc active %i\n",
13649 encoder->base.base.id, active,
13650 new_crtc_state->hw.active);
13652 I915_STATE_WARN(active && crtc->pipe != pipe,
13653 "Encoder connected to wrong pipe %c\n",
13657 encoder->get_config(encoder, pipe_config);
13660 intel_crtc_compute_pixel_rate(pipe_config);
13662 if (!new_crtc_state->hw.active)
13665 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13667 if (!intel_pipe_config_compare(new_crtc_state,
13668 pipe_config, false)) {
13669 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13670 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13671 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13676 intel_verify_planes(struct intel_atomic_state *state)
13678 struct intel_plane *plane;
13679 const struct intel_plane_state *plane_state;
13682 for_each_new_intel_plane_in_state(state, plane,
13684 assert_plane(plane, plane_state->planar_slave ||
13685 plane_state->uapi.visible);
13689 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13690 struct intel_shared_dpll *pll,
13691 struct intel_crtc *crtc,
13692 struct intel_crtc_state *new_crtc_state)
13694 struct intel_dpll_hw_state dpll_hw_state;
13695 unsigned int crtc_mask;
13698 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13700 DRM_DEBUG_KMS("%s\n", pll->info->name);
13702 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13704 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13705 I915_STATE_WARN(!pll->on && pll->active_mask,
13706 "pll in active use but not on in sw tracking\n");
13707 I915_STATE_WARN(pll->on && !pll->active_mask,
13708 "pll is on but not used by any active crtc\n");
13709 I915_STATE_WARN(pll->on != active,
13710 "pll on state mismatch (expected %i, found %i)\n",
13715 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13716 "more active pll users than references: %x vs %x\n",
13717 pll->active_mask, pll->state.crtc_mask);
13722 crtc_mask = drm_crtc_mask(&crtc->base);
13724 if (new_crtc_state->hw.active)
13725 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13726 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13727 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13729 I915_STATE_WARN(pll->active_mask & crtc_mask,
13730 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13731 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13733 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13734 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13735 crtc_mask, pll->state.crtc_mask);
13737 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13739 sizeof(dpll_hw_state)),
13740 "pll hw state mismatch\n");
13744 verify_shared_dpll_state(struct intel_crtc *crtc,
13745 struct intel_crtc_state *old_crtc_state,
13746 struct intel_crtc_state *new_crtc_state)
13748 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13750 if (new_crtc_state->shared_dpll)
13751 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13753 if (old_crtc_state->shared_dpll &&
13754 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13755 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13756 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13758 I915_STATE_WARN(pll->active_mask & crtc_mask,
13759 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13760 pipe_name(drm_crtc_index(&crtc->base)));
13761 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13762 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13763 pipe_name(drm_crtc_index(&crtc->base)));
13768 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13769 struct intel_atomic_state *state,
13770 struct intel_crtc_state *old_crtc_state,
13771 struct intel_crtc_state *new_crtc_state)
13773 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13776 verify_wm_state(crtc, new_crtc_state);
13777 verify_connector_state(state, crtc);
13778 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13779 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13783 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13787 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13788 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13792 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13793 struct intel_atomic_state *state)
13795 verify_encoder_state(dev_priv, state);
13796 verify_connector_state(state, NULL);
13797 verify_disabled_dpll_state(dev_priv);
13801 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
13803 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13804 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13805 const struct drm_display_mode *adjusted_mode =
13806 &crtc_state->hw.adjusted_mode;
13808 drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
13811 * The scanline counter increments at the leading edge of hsync.
13813 * On most platforms it starts counting from vtotal-1 on the
13814 * first active line. That means the scanline counter value is
13815 * always one less than what we would expect. Ie. just after
13816 * start of vblank, which also occurs at start of hsync (on the
13817 * last active line), the scanline counter will read vblank_start-1.
13819 * On gen2 the scanline counter starts counting from 1 instead
13820 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13821 * to keep the value positive), instead of adding one.
13823 * On HSW+ the behaviour of the scanline counter depends on the output
13824 * type. For DP ports it behaves like most other platforms, but on HDMI
13825 * there's an extra 1 line difference. So we need to add two instead of
13826 * one to the value.
13828 * On VLV/CHV DSI the scanline counter would appear to increment
13829 * approx. 1/3 of a scanline before start of vblank. Unfortunately
13830 * that means we can't tell whether we're in vblank or not while
13831 * we're on that particular line. We must still set scanline_offset
13832 * to 1 so that the vblank timestamps come out correct when we query
13833 * the scanline counter from within the vblank interrupt handler.
13834 * However if queried just before the start of vblank we'll get an
13835 * answer that's slightly in the future.
13837 if (IS_GEN(dev_priv, 2)) {
13840 vtotal = adjusted_mode->crtc_vtotal;
13841 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13844 crtc->scanline_offset = vtotal - 1;
13845 } else if (HAS_DDI(dev_priv) &&
13846 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13847 crtc->scanline_offset = 2;
13849 crtc->scanline_offset = 1;
13853 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13855 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13856 struct intel_crtc_state *new_crtc_state;
13857 struct intel_crtc *crtc;
13860 if (!dev_priv->display.crtc_compute_clock)
13863 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13864 if (!needs_modeset(new_crtc_state))
13867 intel_release_shared_dplls(state, crtc);
13872 * This implements the workaround described in the "notes" section of the mode
13873 * set sequence documentation. When going from no pipes or single pipe to
13874 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13875 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13877 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13879 struct intel_crtc_state *crtc_state;
13880 struct intel_crtc *crtc;
13881 struct intel_crtc_state *first_crtc_state = NULL;
13882 struct intel_crtc_state *other_crtc_state = NULL;
13883 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13886 /* look at all crtc's that are going to be enabled in during modeset */
13887 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13888 if (!crtc_state->hw.active ||
13889 !needs_modeset(crtc_state))
13892 if (first_crtc_state) {
13893 other_crtc_state = crtc_state;
13896 first_crtc_state = crtc_state;
13897 first_pipe = crtc->pipe;
13901 /* No workaround needed? */
13902 if (!first_crtc_state)
13905 /* w/a possibly needed, check how many crtc's are already enabled. */
13906 for_each_intel_crtc(state->base.dev, crtc) {
13907 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13908 if (IS_ERR(crtc_state))
13909 return PTR_ERR(crtc_state);
13911 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13913 if (!crtc_state->hw.active ||
13914 needs_modeset(crtc_state))
13917 /* 2 or more enabled crtcs means no need for w/a */
13918 if (enabled_pipe != INVALID_PIPE)
13921 enabled_pipe = crtc->pipe;
13924 if (enabled_pipe != INVALID_PIPE)
13925 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13926 else if (other_crtc_state)
13927 other_crtc_state->hsw_workaround_pipe = first_pipe;
13932 static int intel_modeset_checks(struct intel_atomic_state *state)
13934 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13935 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13936 struct intel_crtc *crtc;
13939 /* keep the current setting */
13940 if (!state->cdclk.force_min_cdclk_changed)
13941 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13943 state->modeset = true;
13944 state->active_pipes = dev_priv->active_pipes;
13945 state->cdclk.logical = dev_priv->cdclk.logical;
13946 state->cdclk.actual = dev_priv->cdclk.actual;
13948 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13949 new_crtc_state, i) {
13950 if (new_crtc_state->hw.active)
13951 state->active_pipes |= BIT(crtc->pipe);
13953 state->active_pipes &= ~BIT(crtc->pipe);
13955 if (old_crtc_state->hw.active != new_crtc_state->hw.active)
13956 state->active_pipe_changes |= BIT(crtc->pipe);
13959 if (state->active_pipe_changes) {
13960 ret = intel_atomic_lock_global_state(state);
13965 ret = intel_modeset_calc_cdclk(state);
13969 intel_modeset_clear_plls(state);
13971 if (IS_HASWELL(dev_priv))
13972 return haswell_mode_set_planes_workaround(state);
13978 * Handle calculation of various watermark data at the end of the atomic check
13979 * phase. The code here should be run after the per-crtc and per-plane 'check'
13980 * handlers to ensure that all derived state has been updated.
13982 static int calc_watermark_data(struct intel_atomic_state *state)
13984 struct drm_device *dev = state->base.dev;
13985 struct drm_i915_private *dev_priv = to_i915(dev);
13987 /* Is there platform-specific watermark information to calculate? */
13988 if (dev_priv->display.compute_global_watermarks)
13989 return dev_priv->display.compute_global_watermarks(state);
13994 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13995 struct intel_crtc_state *new_crtc_state)
13997 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14000 new_crtc_state->uapi.mode_changed = false;
14001 new_crtc_state->update_pipe = true;
14004 * If we're not doing the full modeset we want to
14005 * keep the current M/N values as they may be
14006 * sufficiently different to the computed values
14007 * to cause problems.
14009 * FIXME: should really copy more fuzzy state here
14011 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14012 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14013 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14014 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14017 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14018 struct intel_crtc *crtc,
14021 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14022 struct intel_plane *plane;
14024 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14025 struct intel_plane_state *plane_state;
14027 if ((plane_ids_mask & BIT(plane->id)) == 0)
14030 plane_state = intel_atomic_get_plane_state(state, plane);
14031 if (IS_ERR(plane_state))
14032 return PTR_ERR(plane_state);
14038 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14040 /* See {hsw,vlv,ivb}_plane_ratio() */
14041 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14042 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14043 IS_IVYBRIDGE(dev_priv);
14046 static int intel_atomic_check_planes(struct intel_atomic_state *state,
14047 bool *need_modeset)
14049 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14050 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14051 struct intel_plane_state *plane_state;
14052 struct intel_plane *plane;
14053 struct intel_crtc *crtc;
14056 ret = icl_add_linked_planes(state);
14060 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14061 ret = intel_plane_atomic_check(state, plane);
14063 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
14064 plane->base.base.id, plane->base.name);
14069 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14070 new_crtc_state, i) {
14071 u8 old_active_planes, new_active_planes;
14073 ret = icl_check_nv12_planes(new_crtc_state);
14078 * On some platforms the number of active planes affects
14079 * the planes' minimum cdclk calculation. Add such planes
14080 * to the state before we compute the minimum cdclk.
14082 if (!active_planes_affects_min_cdclk(dev_priv))
14085 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14086 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14088 if (hweight8(old_active_planes) == hweight8(new_active_planes))
14091 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14097 * active_planes bitmask has been updated, and potentially
14098 * affected planes are part of the state. We can now
14099 * compute the minimum cdclk for each plane.
14101 for_each_new_intel_plane_in_state(state, plane, plane_state, i)
14102 *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
14107 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14109 struct intel_crtc_state *crtc_state;
14110 struct intel_crtc *crtc;
14113 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14114 int ret = intel_crtc_atomic_check(state, crtc);
14116 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
14117 crtc->base.base.id, crtc->base.name);
14126 * intel_atomic_check - validate state object
14128 * @_state: state to validate
14130 static int intel_atomic_check(struct drm_device *dev,
14131 struct drm_atomic_state *_state)
14133 struct drm_i915_private *dev_priv = to_i915(dev);
14134 struct intel_atomic_state *state = to_intel_atomic_state(_state);
14135 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14136 struct intel_crtc *crtc;
14138 bool any_ms = false;
14140 /* Catch I915_MODE_FLAG_INHERITED */
14141 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14142 new_crtc_state, i) {
14143 if (new_crtc_state->hw.mode.private_flags !=
14144 old_crtc_state->hw.mode.private_flags)
14145 new_crtc_state->uapi.mode_changed = true;
14148 ret = drm_atomic_helper_check_modeset(dev, &state->base);
14152 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14153 new_crtc_state, i) {
14154 if (!needs_modeset(new_crtc_state)) {
14156 intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14161 if (!new_crtc_state->uapi.enable) {
14162 intel_crtc_copy_uapi_to_hw_state(new_crtc_state);
14168 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14172 ret = intel_modeset_pipe_config(new_crtc_state);
14176 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14178 if (needs_modeset(new_crtc_state))
14182 if (any_ms && !check_digital_port_conflicts(state)) {
14183 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14188 ret = drm_dp_mst_atomic_check(&state->base);
14192 any_ms |= state->cdclk.force_min_cdclk_changed;
14194 ret = intel_atomic_check_planes(state, &any_ms);
14199 ret = intel_modeset_checks(state);
14203 state->cdclk.logical = dev_priv->cdclk.logical;
14206 ret = intel_atomic_check_crtcs(state);
14210 intel_fbc_choose_crtc(dev_priv, state);
14211 ret = calc_watermark_data(state);
14215 ret = intel_bw_atomic_check(state);
14219 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14220 new_crtc_state, i) {
14221 if (!needs_modeset(new_crtc_state) &&
14222 !new_crtc_state->update_pipe)
14225 intel_dump_pipe_config(new_crtc_state, state,
14226 needs_modeset(new_crtc_state) ?
14227 "[modeset]" : "[fastset]");
14233 if (ret == -EDEADLK)
14237 * FIXME would probably be nice to know which crtc specifically
14238 * caused the failure, in cases where we can pinpoint it.
14240 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14242 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14247 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14249 return drm_atomic_helper_prepare_planes(state->base.dev,
14253 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14255 struct drm_device *dev = crtc->base.dev;
14256 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14258 if (!vblank->max_vblank_count)
14259 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14261 return crtc->base.funcs->get_vblank_counter(&crtc->base);
14264 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14265 struct intel_crtc_state *crtc_state)
14267 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14269 if (!IS_GEN(dev_priv, 2))
14270 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14272 if (crtc_state->has_pch_encoder) {
14273 enum pipe pch_transcoder =
14274 intel_crtc_pch_transcoder(crtc);
14276 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14280 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14281 const struct intel_crtc_state *new_crtc_state)
14283 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14284 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14287 * Update pipe size and adjust fitter if needed: the reason for this is
14288 * that in compute_mode_changes we check the native mode (not the pfit
14289 * mode) to see if we can flip rather than do a full mode set. In the
14290 * fastboot case, we'll flip, but if we don't update the pipesrc and
14291 * pfit state, we'll end up with a big fb scanned out into the wrong
14294 intel_set_pipe_src_size(new_crtc_state);
14296 /* on skylake this is done by detaching scalers */
14297 if (INTEL_GEN(dev_priv) >= 9) {
14298 skl_detach_scalers(new_crtc_state);
14300 if (new_crtc_state->pch_pfit.enabled)
14301 skylake_pfit_enable(new_crtc_state);
14302 } else if (HAS_PCH_SPLIT(dev_priv)) {
14303 if (new_crtc_state->pch_pfit.enabled)
14304 ironlake_pfit_enable(new_crtc_state);
14305 else if (old_crtc_state->pch_pfit.enabled)
14306 ironlake_pfit_disable(old_crtc_state);
14309 if (INTEL_GEN(dev_priv) >= 11)
14310 icl_set_pipe_chicken(crtc);
14313 static void commit_pipe_config(struct intel_atomic_state *state,
14314 struct intel_crtc_state *old_crtc_state,
14315 struct intel_crtc_state *new_crtc_state)
14317 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14318 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14319 bool modeset = needs_modeset(new_crtc_state);
14322 * During modesets pipe configuration was programmed as the
14323 * CRTC was enabled.
14326 if (new_crtc_state->uapi.color_mgmt_changed ||
14327 new_crtc_state->update_pipe)
14328 intel_color_commit(new_crtc_state);
14330 if (INTEL_GEN(dev_priv) >= 9)
14331 skl_detach_scalers(new_crtc_state);
14333 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14334 bdw_set_pipemisc(new_crtc_state);
14336 if (new_crtc_state->update_pipe)
14337 intel_pipe_fastset(old_crtc_state, new_crtc_state);
14340 if (dev_priv->display.atomic_update_watermarks)
14341 dev_priv->display.atomic_update_watermarks(state, crtc);
14344 static void intel_update_crtc(struct intel_crtc *crtc,
14345 struct intel_atomic_state *state,
14346 struct intel_crtc_state *old_crtc_state,
14347 struct intel_crtc_state *new_crtc_state)
14349 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14350 bool modeset = needs_modeset(new_crtc_state);
14351 struct intel_plane_state *new_plane_state =
14352 intel_atomic_get_new_plane_state(state,
14353 to_intel_plane(crtc->base.primary));
14356 intel_crtc_update_active_timings(new_crtc_state);
14358 dev_priv->display.crtc_enable(state, crtc);
14360 /* vblanks work again, re-enable pipe CRC. */
14361 intel_crtc_enable_pipe_crc(crtc);
14363 if (new_crtc_state->preload_luts &&
14364 (new_crtc_state->uapi.color_mgmt_changed ||
14365 new_crtc_state->update_pipe))
14366 intel_color_load_luts(new_crtc_state);
14368 intel_pre_plane_update(old_crtc_state, new_crtc_state);
14370 if (new_crtc_state->update_pipe)
14371 intel_encoders_update_pipe(state, crtc);
14374 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14375 intel_fbc_disable(crtc);
14376 else if (new_plane_state)
14377 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14379 /* Perform vblank evasion around commit operation */
14380 intel_pipe_update_start(new_crtc_state);
14382 commit_pipe_config(state, old_crtc_state, new_crtc_state);
14384 if (INTEL_GEN(dev_priv) >= 9)
14385 skl_update_planes_on_crtc(state, crtc);
14387 i9xx_update_planes_on_crtc(state, crtc);
14389 intel_pipe_update_end(new_crtc_state);
14392 * We usually enable FIFO underrun interrupts as part of the
14393 * CRTC enable sequence during modesets. But when we inherit a
14394 * valid pipe configuration from the BIOS we need to take care
14395 * of enabling them on the CRTC's first fastset.
14397 if (new_crtc_state->update_pipe && !modeset &&
14398 old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14399 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14402 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
14404 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
14405 enum transcoder slave_transcoder;
14407 WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
14409 slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
14410 return intel_get_crtc_for_pipe(dev_priv,
14411 (enum pipe)slave_transcoder);
14414 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
14415 struct intel_crtc_state *old_crtc_state,
14416 struct intel_crtc_state *new_crtc_state,
14417 struct intel_crtc *crtc)
14419 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14421 intel_crtc_disable_planes(state, crtc);
14424 * We need to disable pipe CRC before disabling the pipe,
14425 * or we race against vblank off.
14427 intel_crtc_disable_pipe_crc(crtc);
14429 dev_priv->display.crtc_disable(state, crtc);
14430 crtc->active = false;
14431 intel_fbc_disable(crtc);
14432 intel_disable_shared_dpll(old_crtc_state);
14435 * Underruns don't always raise interrupts,
14436 * so check manually.
14438 intel_check_cpu_fifo_underruns(dev_priv);
14439 intel_check_pch_fifo_underruns(dev_priv);
14441 /* FIXME unify this for all platforms */
14442 if (!new_crtc_state->hw.active &&
14443 !HAS_GMCH(dev_priv) &&
14444 dev_priv->display.initial_watermarks)
14445 dev_priv->display.initial_watermarks(state, crtc);
14448 static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
14449 struct intel_crtc *crtc,
14450 struct intel_crtc_state *old_crtc_state,
14451 struct intel_crtc_state *new_crtc_state)
14453 struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14454 struct intel_crtc_state *new_slave_crtc_state =
14455 intel_atomic_get_new_crtc_state(state, slave_crtc);
14456 struct intel_crtc_state *old_slave_crtc_state =
14457 intel_atomic_get_old_crtc_state(state, slave_crtc);
14459 WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14460 !old_slave_crtc_state);
14462 /* Disable Slave first */
14463 intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
14464 if (old_slave_crtc_state->hw.active)
14465 intel_old_crtc_state_disables(state,
14466 old_slave_crtc_state,
14467 new_slave_crtc_state,
14470 /* Disable Master */
14471 intel_pre_plane_update(old_crtc_state, new_crtc_state);
14472 if (old_crtc_state->hw.active)
14473 intel_old_crtc_state_disables(state,
14479 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
14481 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14482 struct intel_crtc *crtc;
14486 * Disable CRTC/pipes in reverse order because some features(MST in
14487 * TGL+) requires master and slave relationship between pipes, so it
14488 * should always pick the lowest pipe as master as it will be enabled
14489 * first and disable in the reverse order so the master will be the
14490 * last one to be disabled.
14492 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
14493 new_crtc_state, i) {
14494 if (!needs_modeset(new_crtc_state))
14497 /* In case of Transcoder port Sync master slave CRTCs can be
14498 * assigned in any order and we need to make sure that
14499 * slave CRTCs are disabled first and then master CRTC since
14500 * Slave vblanks are masked till Master Vblanks.
14502 if (is_trans_port_sync_mode(old_crtc_state)) {
14503 if (is_trans_port_sync_master(old_crtc_state))
14504 intel_trans_port_sync_modeset_disables(state,
14511 intel_pre_plane_update(old_crtc_state, new_crtc_state);
14513 if (old_crtc_state->hw.active)
14514 intel_old_crtc_state_disables(state,
14522 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
14524 struct intel_crtc *crtc;
14525 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14528 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14529 if (!new_crtc_state->hw.active)
14532 intel_update_crtc(crtc, state, old_crtc_state,
14537 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
14538 struct intel_atomic_state *state,
14539 struct intel_crtc_state *new_crtc_state)
14541 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14543 intel_crtc_update_active_timings(new_crtc_state);
14544 dev_priv->display.crtc_enable(state, crtc);
14545 intel_crtc_enable_pipe_crc(crtc);
14548 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
14549 struct intel_atomic_state *state)
14551 struct drm_connector *uninitialized_var(conn);
14552 struct drm_connector_state *conn_state;
14553 struct intel_dp *intel_dp;
14556 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
14557 if (conn_state->crtc == &crtc->base)
14560 intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
14561 intel_dp_stop_link_train(intel_dp);
14564 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
14565 struct intel_atomic_state *state)
14567 struct intel_crtc_state *new_crtc_state =
14568 intel_atomic_get_new_crtc_state(state, crtc);
14569 struct intel_crtc_state *old_crtc_state =
14570 intel_atomic_get_old_crtc_state(state, crtc);
14571 struct intel_plane_state *new_plane_state =
14572 intel_atomic_get_new_plane_state(state,
14573 to_intel_plane(crtc->base.primary));
14574 bool modeset = needs_modeset(new_crtc_state);
14576 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14577 intel_fbc_disable(crtc);
14578 else if (new_plane_state)
14579 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14581 /* Perform vblank evasion around commit operation */
14582 intel_pipe_update_start(new_crtc_state);
14583 commit_pipe_config(state, old_crtc_state, new_crtc_state);
14584 skl_update_planes_on_crtc(state, crtc);
14585 intel_pipe_update_end(new_crtc_state);
14588 * We usually enable FIFO underrun interrupts as part of the
14589 * CRTC enable sequence during modesets. But when we inherit a
14590 * valid pipe configuration from the BIOS we need to take care
14591 * of enabling them on the CRTC's first fastset.
14593 if (new_crtc_state->update_pipe && !modeset &&
14594 old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14595 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14598 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
14599 struct intel_atomic_state *state,
14600 struct intel_crtc_state *old_crtc_state,
14601 struct intel_crtc_state *new_crtc_state)
14603 struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14604 struct intel_crtc_state *new_slave_crtc_state =
14605 intel_atomic_get_new_crtc_state(state, slave_crtc);
14606 struct intel_crtc_state *old_slave_crtc_state =
14607 intel_atomic_get_old_crtc_state(state, slave_crtc);
14609 WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14610 !old_slave_crtc_state);
14612 DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
14613 crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
14614 slave_crtc->base.name);
14616 /* Enable seq for slave with with DP_TP_CTL left Idle until the
14619 intel_crtc_enable_trans_port_sync(slave_crtc,
14621 new_slave_crtc_state);
14623 /* Enable seq for master with with DP_TP_CTL left Idle */
14624 intel_crtc_enable_trans_port_sync(crtc,
14628 /* Set Slave's DP_TP_CTL to Normal */
14629 intel_set_dp_tp_ctl_normal(slave_crtc,
14632 /* Set Master's DP_TP_CTL To Normal */
14633 usleep_range(200, 400);
14634 intel_set_dp_tp_ctl_normal(crtc,
14637 /* Now do the post crtc enable for all master and slaves */
14638 intel_post_crtc_enable_updates(slave_crtc,
14640 intel_post_crtc_enable_updates(crtc,
14644 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
14646 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14647 struct intel_crtc *crtc;
14648 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14649 unsigned int updated = 0;
14652 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
14653 u8 required_slices = state->wm_results.ddb.enabled_slices;
14654 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
14656 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
14657 /* ignore allocations for crtc's that have been turned off. */
14658 if (new_crtc_state->hw.active)
14659 entries[i] = old_crtc_state->wm.skl.ddb;
14661 /* If 2nd DBuf slice required, enable it here */
14662 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
14663 icl_dbuf_slices_update(dev_priv, required_slices);
14666 * Whenever the number of active pipes changes, we need to make sure we
14667 * update the pipes in the right order so that their ddb allocations
14668 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14669 * cause pipe underruns and other bad stuff.
14674 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14675 enum pipe pipe = crtc->pipe;
14676 bool vbl_wait = false;
14677 bool modeset = needs_modeset(new_crtc_state);
14679 if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
14682 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
14684 INTEL_NUM_PIPES(dev_priv), i))
14687 updated |= BIT(pipe);
14688 entries[i] = new_crtc_state->wm.skl.ddb;
14691 * If this is an already active pipe, it's DDB changed,
14692 * and this isn't the last pipe that needs updating
14693 * then we need to wait for a vblank to pass for the
14694 * new ddb allocation to take effect.
14696 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
14697 &old_crtc_state->wm.skl.ddb) &&
14699 state->wm_results.dirty_pipes != updated)
14702 if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
14703 if (is_trans_port_sync_master(new_crtc_state))
14704 intel_update_trans_port_sync_crtcs(crtc,
14711 intel_update_crtc(crtc, state, old_crtc_state,
14716 intel_wait_for_vblank(dev_priv, pipe);
14720 } while (progress);
14722 /* If 2nd DBuf slice is no more required disable it */
14723 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
14724 icl_dbuf_slices_update(dev_priv, required_slices);
14727 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14729 struct intel_atomic_state *state, *next;
14730 struct llist_node *freed;
14732 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14733 llist_for_each_entry_safe(state, next, freed, freed)
14734 drm_atomic_state_put(&state->base);
14737 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14739 struct drm_i915_private *dev_priv =
14740 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14742 intel_atomic_helper_free_state(dev_priv);
14745 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
14747 struct wait_queue_entry wait_fence, wait_reset;
14748 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
14750 init_wait_entry(&wait_fence, 0);
14751 init_wait_entry(&wait_reset, 0);
14753 prepare_to_wait(&intel_state->commit_ready.wait,
14754 &wait_fence, TASK_UNINTERRUPTIBLE);
14755 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14756 I915_RESET_MODESET),
14757 &wait_reset, TASK_UNINTERRUPTIBLE);
14760 if (i915_sw_fence_done(&intel_state->commit_ready) ||
14761 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
14766 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
14767 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14768 I915_RESET_MODESET),
14772 static void intel_atomic_cleanup_work(struct work_struct *work)
14774 struct drm_atomic_state *state =
14775 container_of(work, struct drm_atomic_state, commit_work);
14776 struct drm_i915_private *i915 = to_i915(state->dev);
14778 drm_atomic_helper_cleanup_planes(&i915->drm, state);
14779 drm_atomic_helper_commit_cleanup_done(state);
14780 drm_atomic_state_put(state);
14782 intel_atomic_helper_free_state(i915);
14785 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
14787 struct drm_device *dev = state->base.dev;
14788 struct drm_i915_private *dev_priv = to_i915(dev);
14789 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14790 struct intel_crtc *crtc;
14791 u64 put_domains[I915_MAX_PIPES] = {};
14792 intel_wakeref_t wakeref = 0;
14795 intel_atomic_commit_fence_wait(state);
14797 drm_atomic_helper_wait_for_dependencies(&state->base);
14799 if (state->modeset)
14800 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14802 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14803 new_crtc_state, i) {
14804 if (needs_modeset(new_crtc_state) ||
14805 new_crtc_state->update_pipe) {
14807 put_domains[crtc->pipe] =
14808 modeset_get_crtc_power_domains(new_crtc_state);
14812 intel_commit_modeset_disables(state);
14814 /* FIXME: Eventually get rid of our crtc->config pointer */
14815 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14816 crtc->config = new_crtc_state;
14818 if (state->modeset) {
14819 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14821 intel_set_cdclk_pre_plane_update(dev_priv,
14822 &state->cdclk.actual,
14823 &dev_priv->cdclk.actual,
14824 state->cdclk.pipe);
14827 * SKL workaround: bspec recommends we disable the SAGV when we
14828 * have more then one pipe enabled
14830 if (!intel_can_enable_sagv(state))
14831 intel_disable_sagv(dev_priv);
14833 intel_modeset_verify_disabled(dev_priv, state);
14836 /* Complete the events for pipes that have now been disabled */
14837 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14838 bool modeset = needs_modeset(new_crtc_state);
14840 /* Complete events for now disable pipes here. */
14841 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
14842 spin_lock_irq(&dev->event_lock);
14843 drm_crtc_send_vblank_event(&crtc->base,
14844 new_crtc_state->uapi.event);
14845 spin_unlock_irq(&dev->event_lock);
14847 new_crtc_state->uapi.event = NULL;
14851 if (state->modeset)
14852 intel_encoders_update_prepare(state);
14854 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14855 dev_priv->display.commit_modeset_enables(state);
14857 if (state->modeset) {
14858 intel_encoders_update_complete(state);
14860 intel_set_cdclk_post_plane_update(dev_priv,
14861 &state->cdclk.actual,
14862 &dev_priv->cdclk.actual,
14863 state->cdclk.pipe);
14866 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14867 * already, but still need the state for the delayed optimization. To
14869 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14870 * - schedule that vblank worker _before_ calling hw_done
14871 * - at the start of commit_tail, cancel it _synchrously
14872 * - switch over to the vblank wait helper in the core after that since
14873 * we don't need out special handling any more.
14875 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14877 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14878 if (new_crtc_state->hw.active &&
14879 !needs_modeset(new_crtc_state) &&
14880 !new_crtc_state->preload_luts &&
14881 (new_crtc_state->uapi.color_mgmt_changed ||
14882 new_crtc_state->update_pipe))
14883 intel_color_load_luts(new_crtc_state);
14887 * Now that the vblank has passed, we can go ahead and program the
14888 * optimal watermarks on platforms that need two-step watermark
14891 * TODO: Move this (and other cleanup) to an async worker eventually.
14893 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14894 if (dev_priv->display.optimize_watermarks)
14895 dev_priv->display.optimize_watermarks(state, crtc);
14898 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14899 intel_post_plane_update(old_crtc_state);
14901 if (put_domains[i])
14902 modeset_put_power_domains(dev_priv, put_domains[i]);
14904 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14907 if (state->modeset)
14908 intel_verify_planes(state);
14910 if (state->modeset && intel_can_enable_sagv(state))
14911 intel_enable_sagv(dev_priv);
14913 drm_atomic_helper_commit_hw_done(&state->base);
14915 if (state->modeset) {
14916 /* As one of the primary mmio accessors, KMS has a high
14917 * likelihood of triggering bugs in unclaimed access. After we
14918 * finish modesetting, see if an error has been flagged, and if
14919 * so enable debugging for the next modeset - and hope we catch
14922 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14923 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14925 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14928 * Defer the cleanup of the old state to a separate worker to not
14929 * impede the current task (userspace for blocking modesets) that
14930 * are executed inline. For out-of-line asynchronous modesets/flips,
14931 * deferring to a new worker seems overkill, but we would place a
14932 * schedule point (cond_resched()) here anyway to keep latencies
14935 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14936 queue_work(system_highpri_wq, &state->base.commit_work);
14939 static void intel_atomic_commit_work(struct work_struct *work)
14941 struct intel_atomic_state *state =
14942 container_of(work, struct intel_atomic_state, base.commit_work);
14944 intel_atomic_commit_tail(state);
14947 static int __i915_sw_fence_call
14948 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14949 enum i915_sw_fence_notify notify)
14951 struct intel_atomic_state *state =
14952 container_of(fence, struct intel_atomic_state, commit_ready);
14955 case FENCE_COMPLETE:
14956 /* we do blocking waits in the worker, nothing to do here */
14960 struct intel_atomic_helper *helper =
14961 &to_i915(state->base.dev)->atomic_helper;
14963 if (llist_add(&state->freed, &helper->free_list))
14964 schedule_work(&helper->free_work);
14969 return NOTIFY_DONE;
14972 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14974 struct intel_plane_state *old_plane_state, *new_plane_state;
14975 struct intel_plane *plane;
14978 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14979 new_plane_state, i)
14980 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
14981 to_intel_frontbuffer(new_plane_state->hw.fb),
14982 plane->frontbuffer_bit);
14985 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
14987 struct intel_crtc *crtc;
14989 for_each_intel_crtc(&dev_priv->drm, crtc)
14990 drm_modeset_lock_assert_held(&crtc->base.mutex);
14993 static int intel_atomic_commit(struct drm_device *dev,
14994 struct drm_atomic_state *_state,
14997 struct intel_atomic_state *state = to_intel_atomic_state(_state);
14998 struct drm_i915_private *dev_priv = to_i915(dev);
15001 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15003 drm_atomic_state_get(&state->base);
15004 i915_sw_fence_init(&state->commit_ready,
15005 intel_atomic_commit_ready);
15008 * The intel_legacy_cursor_update() fast path takes care
15009 * of avoiding the vblank waits for simple cursor
15010 * movement and flips. For cursor on/off and size changes,
15011 * we want to perform the vblank waits so that watermark
15012 * updates happen during the correct frames. Gen9+ have
15013 * double buffered watermarks and so shouldn't need this.
15015 * Unset state->legacy_cursor_update before the call to
15016 * drm_atomic_helper_setup_commit() because otherwise
15017 * drm_atomic_helper_wait_for_flip_done() is a noop and
15018 * we get FIFO underruns because we didn't wait
15021 * FIXME doing watermarks and fb cleanup from a vblank worker
15022 * (assuming we had any) would solve these problems.
15024 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15025 struct intel_crtc_state *new_crtc_state;
15026 struct intel_crtc *crtc;
15029 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15030 if (new_crtc_state->wm.need_postvbl_update ||
15031 new_crtc_state->update_wm_post)
15032 state->base.legacy_cursor_update = false;
15035 ret = intel_atomic_prepare_commit(state);
15037 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
15038 i915_sw_fence_commit(&state->commit_ready);
15039 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15043 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15045 ret = drm_atomic_helper_swap_state(&state->base, true);
15048 i915_sw_fence_commit(&state->commit_ready);
15050 drm_atomic_helper_cleanup_planes(dev, &state->base);
15051 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15054 dev_priv->wm.distrust_bios_wm = false;
15055 intel_shared_dpll_swap_state(state);
15056 intel_atomic_track_fbs(state);
15058 if (state->global_state_changed) {
15059 assert_global_state_locked(dev_priv);
15061 memcpy(dev_priv->min_cdclk, state->min_cdclk,
15062 sizeof(state->min_cdclk));
15063 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
15064 sizeof(state->min_voltage_level));
15065 dev_priv->active_pipes = state->active_pipes;
15066 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
15068 intel_cdclk_swap_state(state);
15071 drm_atomic_state_get(&state->base);
15072 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15074 i915_sw_fence_commit(&state->commit_ready);
15075 if (nonblock && state->modeset) {
15076 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15077 } else if (nonblock) {
15078 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15080 if (state->modeset)
15081 flush_workqueue(dev_priv->modeset_wq);
15082 intel_atomic_commit_tail(state);
15088 struct wait_rps_boost {
15089 struct wait_queue_entry wait;
15091 struct drm_crtc *crtc;
15092 struct i915_request *request;
15095 static int do_rps_boost(struct wait_queue_entry *_wait,
15096 unsigned mode, int sync, void *key)
15098 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15099 struct i915_request *rq = wait->request;
15102 * If we missed the vblank, but the request is already running it
15103 * is reasonable to assume that it will complete before the next
15104 * vblank without our intervention, so leave RPS alone.
15106 if (!i915_request_started(rq))
15107 intel_rps_boost(rq);
15108 i915_request_put(rq);
15110 drm_crtc_vblank_put(wait->crtc);
15112 list_del(&wait->wait.entry);
15117 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15118 struct dma_fence *fence)
15120 struct wait_rps_boost *wait;
15122 if (!dma_fence_is_i915(fence))
15125 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15128 if (drm_crtc_vblank_get(crtc))
15131 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15133 drm_crtc_vblank_put(crtc);
15137 wait->request = to_request(dma_fence_get(fence));
15140 wait->wait.func = do_rps_boost;
15141 wait->wait.flags = 0;
15143 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15146 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15148 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15149 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15150 struct drm_framebuffer *fb = plane_state->hw.fb;
15151 struct i915_vma *vma;
15153 if (plane->id == PLANE_CURSOR &&
15154 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15155 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15156 const int align = intel_cursor_alignment(dev_priv);
15159 err = i915_gem_object_attach_phys(obj, align);
15164 vma = intel_pin_and_fence_fb_obj(fb,
15165 &plane_state->view,
15166 intel_plane_uses_fence(plane_state),
15167 &plane_state->flags);
15169 return PTR_ERR(vma);
15171 plane_state->vma = vma;
15176 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15178 struct i915_vma *vma;
15180 vma = fetch_and_zero(&old_plane_state->vma);
15182 intel_unpin_fb_vma(vma, old_plane_state->flags);
15185 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15187 struct i915_sched_attr attr = {
15188 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15191 i915_gem_object_wait_priority(obj, 0, &attr);
15195 * intel_prepare_plane_fb - Prepare fb for usage on plane
15196 * @plane: drm plane to prepare for
15197 * @_new_plane_state: the plane state being prepared
15199 * Prepares a framebuffer for usage on a display plane. Generally this
15200 * involves pinning the underlying object and updating the frontbuffer tracking
15201 * bits. Some older platforms need special physical address handling for
15204 * Returns 0 on success, negative error code on failure.
15207 intel_prepare_plane_fb(struct drm_plane *plane,
15208 struct drm_plane_state *_new_plane_state)
15210 struct intel_plane_state *new_plane_state =
15211 to_intel_plane_state(_new_plane_state);
15212 struct intel_atomic_state *intel_state =
15213 to_intel_atomic_state(new_plane_state->uapi.state);
15214 struct drm_i915_private *dev_priv = to_i915(plane->dev);
15215 struct drm_framebuffer *fb = new_plane_state->hw.fb;
15216 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15217 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
15221 struct intel_crtc_state *crtc_state =
15222 intel_atomic_get_new_crtc_state(intel_state,
15223 to_intel_crtc(plane->state->crtc));
15225 /* Big Hammer, we also need to ensure that any pending
15226 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15227 * current scanout is retired before unpinning the old
15228 * framebuffer. Note that we rely on userspace rendering
15229 * into the buffer attached to the pipe they are waiting
15230 * on. If not, userspace generates a GPU hang with IPEHR
15231 * point to the MI_WAIT_FOR_EVENT.
15233 * This should only fail upon a hung GPU, in which case we
15234 * can safely continue.
15236 if (needs_modeset(crtc_state)) {
15237 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15238 old_obj->base.resv, NULL,
15246 if (new_plane_state->uapi.fence) { /* explicit fencing */
15247 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
15248 new_plane_state->uapi.fence,
15249 I915_FENCE_TIMEOUT,
15258 ret = i915_gem_object_pin_pages(obj);
15262 ret = intel_plane_pin_fb(new_plane_state);
15264 i915_gem_object_unpin_pages(obj);
15268 fb_obj_bump_render_priority(obj);
15269 intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
15271 if (!new_plane_state->uapi.fence) { /* implicit fencing */
15272 struct dma_fence *fence;
15274 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15275 obj->base.resv, NULL,
15276 false, I915_FENCE_TIMEOUT,
15281 fence = dma_resv_get_excl_rcu(obj->base.resv);
15283 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15285 dma_fence_put(fence);
15288 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15289 new_plane_state->uapi.fence);
15293 * We declare pageflips to be interactive and so merit a small bias
15294 * towards upclocking to deliver the frame on time. By only changing
15295 * the RPS thresholds to sample more regularly and aim for higher
15296 * clocks we can hopefully deliver low power workloads (like kodi)
15297 * that are not quite steady state without resorting to forcing
15298 * maximum clocks following a vblank miss (see do_rps_boost()).
15300 if (!intel_state->rps_interactive) {
15301 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15302 intel_state->rps_interactive = true;
15309 * intel_cleanup_plane_fb - Cleans up an fb after plane use
15310 * @plane: drm plane to clean up for
15311 * @_old_plane_state: the state from the previous modeset
15313 * Cleans up a framebuffer that has just been removed from a plane.
15316 intel_cleanup_plane_fb(struct drm_plane *plane,
15317 struct drm_plane_state *_old_plane_state)
15319 struct intel_plane_state *old_plane_state =
15320 to_intel_plane_state(_old_plane_state);
15321 struct intel_atomic_state *intel_state =
15322 to_intel_atomic_state(old_plane_state->uapi.state);
15323 struct drm_i915_private *dev_priv = to_i915(plane->dev);
15325 if (intel_state->rps_interactive) {
15326 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15327 intel_state->rps_interactive = false;
15330 /* Should only be called after a successful intel_prepare_plane_fb()! */
15331 intel_plane_unpin_fb(old_plane_state);
15335 * intel_plane_destroy - destroy a plane
15336 * @plane: plane to destroy
15338 * Common destruction function for all types of planes (primary, cursor,
15341 void intel_plane_destroy(struct drm_plane *plane)
15343 drm_plane_cleanup(plane);
15344 kfree(to_intel_plane(plane));
15347 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15348 u32 format, u64 modifier)
15350 switch (modifier) {
15351 case DRM_FORMAT_MOD_LINEAR:
15352 case I915_FORMAT_MOD_X_TILED:
15359 case DRM_FORMAT_C8:
15360 case DRM_FORMAT_RGB565:
15361 case DRM_FORMAT_XRGB1555:
15362 case DRM_FORMAT_XRGB8888:
15363 return modifier == DRM_FORMAT_MOD_LINEAR ||
15364 modifier == I915_FORMAT_MOD_X_TILED;
15370 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15371 u32 format, u64 modifier)
15373 switch (modifier) {
15374 case DRM_FORMAT_MOD_LINEAR:
15375 case I915_FORMAT_MOD_X_TILED:
15382 case DRM_FORMAT_C8:
15383 case DRM_FORMAT_RGB565:
15384 case DRM_FORMAT_XRGB8888:
15385 case DRM_FORMAT_XBGR8888:
15386 case DRM_FORMAT_ARGB8888:
15387 case DRM_FORMAT_ABGR8888:
15388 case DRM_FORMAT_XRGB2101010:
15389 case DRM_FORMAT_XBGR2101010:
15390 case DRM_FORMAT_ARGB2101010:
15391 case DRM_FORMAT_ABGR2101010:
15392 case DRM_FORMAT_XBGR16161616F:
15393 return modifier == DRM_FORMAT_MOD_LINEAR ||
15394 modifier == I915_FORMAT_MOD_X_TILED;
15400 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15401 u32 format, u64 modifier)
15403 return modifier == DRM_FORMAT_MOD_LINEAR &&
15404 format == DRM_FORMAT_ARGB8888;
15407 static const struct drm_plane_funcs i965_plane_funcs = {
15408 .update_plane = drm_atomic_helper_update_plane,
15409 .disable_plane = drm_atomic_helper_disable_plane,
15410 .destroy = intel_plane_destroy,
15411 .atomic_duplicate_state = intel_plane_duplicate_state,
15412 .atomic_destroy_state = intel_plane_destroy_state,
15413 .format_mod_supported = i965_plane_format_mod_supported,
15416 static const struct drm_plane_funcs i8xx_plane_funcs = {
15417 .update_plane = drm_atomic_helper_update_plane,
15418 .disable_plane = drm_atomic_helper_disable_plane,
15419 .destroy = intel_plane_destroy,
15420 .atomic_duplicate_state = intel_plane_duplicate_state,
15421 .atomic_destroy_state = intel_plane_destroy_state,
15422 .format_mod_supported = i8xx_plane_format_mod_supported,
15426 intel_legacy_cursor_update(struct drm_plane *_plane,
15427 struct drm_crtc *_crtc,
15428 struct drm_framebuffer *fb,
15429 int crtc_x, int crtc_y,
15430 unsigned int crtc_w, unsigned int crtc_h,
15431 u32 src_x, u32 src_y,
15432 u32 src_w, u32 src_h,
15433 struct drm_modeset_acquire_ctx *ctx)
15435 struct intel_plane *plane = to_intel_plane(_plane);
15436 struct intel_crtc *crtc = to_intel_crtc(_crtc);
15437 struct intel_plane_state *old_plane_state =
15438 to_intel_plane_state(plane->base.state);
15439 struct intel_plane_state *new_plane_state;
15440 struct intel_crtc_state *crtc_state =
15441 to_intel_crtc_state(crtc->base.state);
15442 struct intel_crtc_state *new_crtc_state;
15446 * When crtc is inactive or there is a modeset pending,
15447 * wait for it to complete in the slowpath
15449 if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
15450 crtc_state->update_pipe)
15454 * Don't do an async update if there is an outstanding commit modifying
15455 * the plane. This prevents our async update's changes from getting
15456 * overridden by a previous synchronous update's state.
15458 if (old_plane_state->uapi.commit &&
15459 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
15463 * If any parameters change that may affect watermarks,
15464 * take the slowpath. Only changing fb or position should be
15467 if (old_plane_state->uapi.crtc != &crtc->base ||
15468 old_plane_state->uapi.src_w != src_w ||
15469 old_plane_state->uapi.src_h != src_h ||
15470 old_plane_state->uapi.crtc_w != crtc_w ||
15471 old_plane_state->uapi.crtc_h != crtc_h ||
15472 !old_plane_state->uapi.fb != !fb)
15475 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
15476 if (!new_plane_state)
15479 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
15480 if (!new_crtc_state) {
15485 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
15487 new_plane_state->uapi.src_x = src_x;
15488 new_plane_state->uapi.src_y = src_y;
15489 new_plane_state->uapi.src_w = src_w;
15490 new_plane_state->uapi.src_h = src_h;
15491 new_plane_state->uapi.crtc_x = crtc_x;
15492 new_plane_state->uapi.crtc_y = crtc_y;
15493 new_plane_state->uapi.crtc_w = crtc_w;
15494 new_plane_state->uapi.crtc_h = crtc_h;
15496 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
15497 old_plane_state, new_plane_state);
15501 ret = intel_plane_pin_fb(new_plane_state);
15505 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
15507 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15508 to_intel_frontbuffer(new_plane_state->hw.fb),
15509 plane->frontbuffer_bit);
15511 /* Swap plane state */
15512 plane->base.state = &new_plane_state->uapi;
15515 * We cannot swap crtc_state as it may be in use by an atomic commit or
15516 * page flip that's running simultaneously. If we swap crtc_state and
15517 * destroy the old state, we will cause a use-after-free there.
15519 * Only update active_planes, which is needed for our internal
15520 * bookkeeping. Either value will do the right thing when updating
15521 * planes atomically. If the cursor was part of the atomic update then
15522 * we would have taken the slowpath.
15524 crtc_state->active_planes = new_crtc_state->active_planes;
15526 if (new_plane_state->uapi.visible)
15527 intel_update_plane(plane, crtc_state, new_plane_state);
15529 intel_disable_plane(plane, crtc_state);
15531 intel_plane_unpin_fb(old_plane_state);
15534 if (new_crtc_state)
15535 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
15537 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
15539 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
15543 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
15544 crtc_x, crtc_y, crtc_w, crtc_h,
15545 src_x, src_y, src_w, src_h, ctx);
15548 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15549 .update_plane = intel_legacy_cursor_update,
15550 .disable_plane = drm_atomic_helper_disable_plane,
15551 .destroy = intel_plane_destroy,
15552 .atomic_duplicate_state = intel_plane_duplicate_state,
15553 .atomic_destroy_state = intel_plane_destroy_state,
15554 .format_mod_supported = intel_cursor_format_mod_supported,
15557 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
15558 enum i9xx_plane_id i9xx_plane)
15560 if (!HAS_FBC(dev_priv))
15563 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15564 return i9xx_plane == PLANE_A; /* tied to pipe A */
15565 else if (IS_IVYBRIDGE(dev_priv))
15566 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
15567 i9xx_plane == PLANE_C;
15568 else if (INTEL_GEN(dev_priv) >= 4)
15569 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
15571 return i9xx_plane == PLANE_A;
15574 static struct intel_plane *
15575 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15577 struct intel_plane *plane;
15578 const struct drm_plane_funcs *plane_funcs;
15579 unsigned int supported_rotations;
15580 unsigned int possible_crtcs;
15581 const u32 *formats;
15585 if (INTEL_GEN(dev_priv) >= 9)
15586 return skl_universal_plane_create(dev_priv, pipe,
15589 plane = intel_plane_alloc();
15593 plane->pipe = pipe;
15595 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15596 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15598 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15599 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
15601 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
15602 plane->id = PLANE_PRIMARY;
15603 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
15605 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
15606 if (plane->has_fbc) {
15607 struct intel_fbc *fbc = &dev_priv->fbc;
15609 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
15612 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15613 formats = vlv_primary_formats;
15614 num_formats = ARRAY_SIZE(vlv_primary_formats);
15615 } else if (INTEL_GEN(dev_priv) >= 4) {
15617 * WaFP16GammaEnabling:ivb
15618 * "Workaround : When using the 64-bit format, the plane
15619 * output on each color channel has one quarter amplitude.
15620 * It can be brought up to full amplitude by using pipe
15621 * gamma correction or pipe color space conversion to
15622 * multiply the plane output by four."
15624 * There is no dedicated plane gamma for the primary plane,
15625 * and using the pipe gamma/csc could conflict with other
15626 * planes, so we choose not to expose fp16 on IVB primary
15627 * planes. HSW primary planes no longer have this problem.
15629 if (IS_IVYBRIDGE(dev_priv)) {
15630 formats = ivb_primary_formats;
15631 num_formats = ARRAY_SIZE(ivb_primary_formats);
15633 formats = i965_primary_formats;
15634 num_formats = ARRAY_SIZE(i965_primary_formats);
15637 formats = i8xx_primary_formats;
15638 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15641 if (INTEL_GEN(dev_priv) >= 4)
15642 plane_funcs = &i965_plane_funcs;
15644 plane_funcs = &i8xx_plane_funcs;
15646 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15647 plane->min_cdclk = vlv_plane_min_cdclk;
15648 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15649 plane->min_cdclk = hsw_plane_min_cdclk;
15650 else if (IS_IVYBRIDGE(dev_priv))
15651 plane->min_cdclk = ivb_plane_min_cdclk;
15653 plane->min_cdclk = i9xx_plane_min_cdclk;
15655 plane->max_stride = i9xx_plane_max_stride;
15656 plane->update_plane = i9xx_update_plane;
15657 plane->disable_plane = i9xx_disable_plane;
15658 plane->get_hw_state = i9xx_plane_get_hw_state;
15659 plane->check_plane = i9xx_plane_check;
15661 possible_crtcs = BIT(pipe);
15663 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15664 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15665 possible_crtcs, plane_funcs,
15666 formats, num_formats,
15667 i9xx_format_modifiers,
15668 DRM_PLANE_TYPE_PRIMARY,
15669 "primary %c", pipe_name(pipe));
15671 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15672 possible_crtcs, plane_funcs,
15673 formats, num_formats,
15674 i9xx_format_modifiers,
15675 DRM_PLANE_TYPE_PRIMARY,
15677 plane_name(plane->i9xx_plane));
15681 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15682 supported_rotations =
15683 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
15684 DRM_MODE_REFLECT_X;
15685 } else if (INTEL_GEN(dev_priv) >= 4) {
15686 supported_rotations =
15687 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
15689 supported_rotations = DRM_MODE_ROTATE_0;
15692 if (INTEL_GEN(dev_priv) >= 4)
15693 drm_plane_create_rotation_property(&plane->base,
15695 supported_rotations);
15698 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
15700 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
15705 intel_plane_free(plane);
15707 return ERR_PTR(ret);
15710 static struct intel_plane *
15711 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
15714 unsigned int possible_crtcs;
15715 struct intel_plane *cursor;
15718 cursor = intel_plane_alloc();
15719 if (IS_ERR(cursor))
15722 cursor->pipe = pipe;
15723 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15724 cursor->id = PLANE_CURSOR;
15725 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15727 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15728 cursor->max_stride = i845_cursor_max_stride;
15729 cursor->update_plane = i845_update_cursor;
15730 cursor->disable_plane = i845_disable_cursor;
15731 cursor->get_hw_state = i845_cursor_get_hw_state;
15732 cursor->check_plane = i845_check_cursor;
15734 cursor->max_stride = i9xx_cursor_max_stride;
15735 cursor->update_plane = i9xx_update_cursor;
15736 cursor->disable_plane = i9xx_disable_cursor;
15737 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15738 cursor->check_plane = i9xx_check_cursor;
15741 cursor->cursor.base = ~0;
15742 cursor->cursor.cntl = ~0;
15744 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15745 cursor->cursor.size = ~0;
15747 possible_crtcs = BIT(pipe);
15749 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15750 possible_crtcs, &intel_cursor_plane_funcs,
15751 intel_cursor_formats,
15752 ARRAY_SIZE(intel_cursor_formats),
15753 cursor_format_modifiers,
15754 DRM_PLANE_TYPE_CURSOR,
15755 "cursor %c", pipe_name(pipe));
15759 if (INTEL_GEN(dev_priv) >= 4)
15760 drm_plane_create_rotation_property(&cursor->base,
15762 DRM_MODE_ROTATE_0 |
15763 DRM_MODE_ROTATE_180);
15765 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15766 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15768 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15773 intel_plane_free(cursor);
15775 return ERR_PTR(ret);
15778 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15779 struct intel_crtc_state *crtc_state)
15781 struct intel_crtc_scaler_state *scaler_state =
15782 &crtc_state->scaler_state;
15783 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15786 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
15787 if (!crtc->num_scalers)
15790 for (i = 0; i < crtc->num_scalers; i++) {
15791 struct intel_scaler *scaler = &scaler_state->scalers[i];
15793 scaler->in_use = 0;
15797 scaler_state->scaler_id = -1;
15800 #define INTEL_CRTC_FUNCS \
15801 .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15802 .set_config = drm_atomic_helper_set_config, \
15803 .destroy = intel_crtc_destroy, \
15804 .page_flip = drm_atomic_helper_page_flip, \
15805 .atomic_duplicate_state = intel_crtc_duplicate_state, \
15806 .atomic_destroy_state = intel_crtc_destroy_state, \
15807 .set_crc_source = intel_crtc_set_crc_source, \
15808 .verify_crc_source = intel_crtc_verify_crc_source, \
15809 .get_crc_sources = intel_crtc_get_crc_sources
15811 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15814 .get_vblank_counter = g4x_get_vblank_counter,
15815 .enable_vblank = bdw_enable_vblank,
15816 .disable_vblank = bdw_disable_vblank,
15819 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15822 .get_vblank_counter = g4x_get_vblank_counter,
15823 .enable_vblank = ilk_enable_vblank,
15824 .disable_vblank = ilk_disable_vblank,
15827 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15830 .get_vblank_counter = g4x_get_vblank_counter,
15831 .enable_vblank = i965_enable_vblank,
15832 .disable_vblank = i965_disable_vblank,
15835 static const struct drm_crtc_funcs i965_crtc_funcs = {
15838 .get_vblank_counter = i915_get_vblank_counter,
15839 .enable_vblank = i965_enable_vblank,
15840 .disable_vblank = i965_disable_vblank,
15843 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
15846 .get_vblank_counter = i915_get_vblank_counter,
15847 .enable_vblank = i915gm_enable_vblank,
15848 .disable_vblank = i915gm_disable_vblank,
15851 static const struct drm_crtc_funcs i915_crtc_funcs = {
15854 .get_vblank_counter = i915_get_vblank_counter,
15855 .enable_vblank = i8xx_enable_vblank,
15856 .disable_vblank = i8xx_disable_vblank,
15859 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15862 /* no hw vblank counter */
15863 .enable_vblank = i8xx_enable_vblank,
15864 .disable_vblank = i8xx_disable_vblank,
15867 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15869 const struct drm_crtc_funcs *funcs;
15870 struct intel_crtc *intel_crtc;
15871 struct intel_crtc_state *crtc_state = NULL;
15872 struct intel_plane *primary = NULL;
15873 struct intel_plane *cursor = NULL;
15876 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15880 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15885 __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
15886 intel_crtc->config = crtc_state;
15888 primary = intel_primary_plane_create(dev_priv, pipe);
15889 if (IS_ERR(primary)) {
15890 ret = PTR_ERR(primary);
15893 intel_crtc->plane_ids_mask |= BIT(primary->id);
15895 for_each_sprite(dev_priv, pipe, sprite) {
15896 struct intel_plane *plane;
15898 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15899 if (IS_ERR(plane)) {
15900 ret = PTR_ERR(plane);
15903 intel_crtc->plane_ids_mask |= BIT(plane->id);
15906 cursor = intel_cursor_plane_create(dev_priv, pipe);
15907 if (IS_ERR(cursor)) {
15908 ret = PTR_ERR(cursor);
15911 intel_crtc->plane_ids_mask |= BIT(cursor->id);
15913 if (HAS_GMCH(dev_priv)) {
15914 if (IS_CHERRYVIEW(dev_priv) ||
15915 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15916 funcs = &g4x_crtc_funcs;
15917 else if (IS_GEN(dev_priv, 4))
15918 funcs = &i965_crtc_funcs;
15919 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
15920 funcs = &i915gm_crtc_funcs;
15921 else if (IS_GEN(dev_priv, 3))
15922 funcs = &i915_crtc_funcs;
15924 funcs = &i8xx_crtc_funcs;
15926 if (INTEL_GEN(dev_priv) >= 8)
15927 funcs = &bdw_crtc_funcs;
15929 funcs = &ilk_crtc_funcs;
15932 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15933 &primary->base, &cursor->base,
15934 funcs, "pipe %c", pipe_name(pipe));
15938 intel_crtc->pipe = pipe;
15940 /* initialize shared scalers */
15941 intel_crtc_init_scalers(intel_crtc, crtc_state);
15943 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15944 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15945 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
15947 if (INTEL_GEN(dev_priv) < 9) {
15948 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15950 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15951 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15952 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
15955 intel_color_init(intel_crtc);
15957 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15963 * drm_mode_config_cleanup() will free up any
15964 * crtcs/planes already initialized.
15972 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15973 struct drm_file *file)
15975 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15976 struct drm_crtc *drmmode_crtc;
15977 struct intel_crtc *crtc;
15979 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15983 crtc = to_intel_crtc(drmmode_crtc);
15984 pipe_from_crtc_id->pipe = crtc->pipe;
15989 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
15991 struct drm_device *dev = encoder->base.dev;
15992 struct intel_encoder *source_encoder;
15993 u32 possible_clones = 0;
15995 for_each_intel_encoder(dev, source_encoder) {
15996 if (encoders_cloneable(encoder, source_encoder))
15997 possible_clones |= drm_encoder_mask(&source_encoder->base);
16000 return possible_clones;
16003 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
16005 struct drm_device *dev = encoder->base.dev;
16006 struct intel_crtc *crtc;
16007 u32 possible_crtcs = 0;
16009 for_each_intel_crtc(dev, crtc) {
16010 if (encoder->pipe_mask & BIT(crtc->pipe))
16011 possible_crtcs |= drm_crtc_mask(&crtc->base);
16014 return possible_crtcs;
16017 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16019 if (!IS_MOBILE(dev_priv))
16022 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
16025 if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
16031 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16033 if (INTEL_GEN(dev_priv) >= 9)
16036 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16039 if (HAS_PCH_LPT_H(dev_priv) &&
16040 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16043 /* DDI E can't be used if DDI A requires 4 lanes */
16044 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16047 if (!dev_priv->vbt.int_crt_support)
16053 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16058 if (HAS_DDI(dev_priv))
16061 * This w/a is needed at least on CPT/PPT, but to be sure apply it
16062 * everywhere where registers can be write protected.
16064 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16069 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16070 u32 val = I915_READ(PP_CONTROL(pps_idx));
16072 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16073 I915_WRITE(PP_CONTROL(pps_idx), val);
16077 static void intel_pps_init(struct drm_i915_private *dev_priv)
16079 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16080 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16081 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16082 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16084 dev_priv->pps_mmio_base = PPS_BASE;
16086 intel_pps_unlock_regs_wa(dev_priv);
16089 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16091 struct intel_encoder *encoder;
16092 bool dpd_is_edp = false;
16094 intel_pps_init(dev_priv);
16096 if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16099 if (INTEL_GEN(dev_priv) >= 12) {
16100 intel_ddi_init(dev_priv, PORT_A);
16101 intel_ddi_init(dev_priv, PORT_B);
16102 intel_ddi_init(dev_priv, PORT_D);
16103 intel_ddi_init(dev_priv, PORT_E);
16104 intel_ddi_init(dev_priv, PORT_F);
16105 intel_ddi_init(dev_priv, PORT_G);
16106 intel_ddi_init(dev_priv, PORT_H);
16107 intel_ddi_init(dev_priv, PORT_I);
16108 icl_dsi_init(dev_priv);
16109 } else if (IS_ELKHARTLAKE(dev_priv)) {
16110 intel_ddi_init(dev_priv, PORT_A);
16111 intel_ddi_init(dev_priv, PORT_B);
16112 intel_ddi_init(dev_priv, PORT_C);
16113 intel_ddi_init(dev_priv, PORT_D);
16114 icl_dsi_init(dev_priv);
16115 } else if (IS_GEN(dev_priv, 11)) {
16116 intel_ddi_init(dev_priv, PORT_A);
16117 intel_ddi_init(dev_priv, PORT_B);
16118 intel_ddi_init(dev_priv, PORT_C);
16119 intel_ddi_init(dev_priv, PORT_D);
16120 intel_ddi_init(dev_priv, PORT_E);
16122 * On some ICL SKUs port F is not present. No strap bits for
16123 * this, so rely on VBT.
16124 * Work around broken VBTs on SKUs known to have no port F.
16126 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16127 intel_bios_is_port_present(dev_priv, PORT_F))
16128 intel_ddi_init(dev_priv, PORT_F);
16130 icl_dsi_init(dev_priv);
16131 } else if (IS_GEN9_LP(dev_priv)) {
16133 * FIXME: Broxton doesn't support port detection via the
16134 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16135 * detect the ports.
16137 intel_ddi_init(dev_priv, PORT_A);
16138 intel_ddi_init(dev_priv, PORT_B);
16139 intel_ddi_init(dev_priv, PORT_C);
16141 vlv_dsi_init(dev_priv);
16142 } else if (HAS_DDI(dev_priv)) {
16145 if (intel_ddi_crt_present(dev_priv))
16146 intel_crt_init(dev_priv);
16149 * Haswell uses DDI functions to detect digital outputs.
16150 * On SKL pre-D0 the strap isn't connected, so we assume
16153 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16154 /* WaIgnoreDDIAStrap: skl */
16155 if (found || IS_GEN9_BC(dev_priv))
16156 intel_ddi_init(dev_priv, PORT_A);
16158 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16160 found = I915_READ(SFUSE_STRAP);
16162 if (found & SFUSE_STRAP_DDIB_DETECTED)
16163 intel_ddi_init(dev_priv, PORT_B);
16164 if (found & SFUSE_STRAP_DDIC_DETECTED)
16165 intel_ddi_init(dev_priv, PORT_C);
16166 if (found & SFUSE_STRAP_DDID_DETECTED)
16167 intel_ddi_init(dev_priv, PORT_D);
16168 if (found & SFUSE_STRAP_DDIF_DETECTED)
16169 intel_ddi_init(dev_priv, PORT_F);
16171 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16173 if (IS_GEN9_BC(dev_priv) &&
16174 intel_bios_is_port_present(dev_priv, PORT_E))
16175 intel_ddi_init(dev_priv, PORT_E);
16177 } else if (HAS_PCH_SPLIT(dev_priv)) {
16181 * intel_edp_init_connector() depends on this completing first,
16182 * to prevent the registration of both eDP and LVDS and the
16183 * incorrect sharing of the PPS.
16185 intel_lvds_init(dev_priv);
16186 intel_crt_init(dev_priv);
16188 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16190 if (ilk_has_edp_a(dev_priv))
16191 intel_dp_init(dev_priv, DP_A, PORT_A);
16193 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
16194 /* PCH SDVOB multiplex with HDMIB */
16195 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16197 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16198 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
16199 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16202 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
16203 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16205 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
16206 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16208 if (I915_READ(PCH_DP_C) & DP_DETECTED)
16209 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16211 if (I915_READ(PCH_DP_D) & DP_DETECTED)
16212 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16213 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16214 bool has_edp, has_port;
16216 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16217 intel_crt_init(dev_priv);
16220 * The DP_DETECTED bit is the latched state of the DDC
16221 * SDA pin at boot. However since eDP doesn't require DDC
16222 * (no way to plug in a DP->HDMI dongle) the DDC pins for
16223 * eDP ports may have been muxed to an alternate function.
16224 * Thus we can't rely on the DP_DETECTED bit alone to detect
16225 * eDP ports. Consult the VBT as well as DP_DETECTED to
16226 * detect eDP ports.
16228 * Sadly the straps seem to be missing sometimes even for HDMI
16229 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16230 * and VBT for the presence of the port. Additionally we can't
16231 * trust the port type the VBT declares as we've seen at least
16232 * HDMI ports that the VBT claim are DP or eDP.
16234 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16235 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16236 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
16237 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16238 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16239 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16241 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16242 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16243 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
16244 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16245 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16246 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16248 if (IS_CHERRYVIEW(dev_priv)) {
16250 * eDP not supported on port D,
16251 * so no need to worry about it
16253 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16254 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
16255 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16256 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
16257 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16260 vlv_dsi_init(dev_priv);
16261 } else if (IS_PINEVIEW(dev_priv)) {
16262 intel_lvds_init(dev_priv);
16263 intel_crt_init(dev_priv);
16264 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16265 bool found = false;
16267 if (IS_MOBILE(dev_priv))
16268 intel_lvds_init(dev_priv);
16270 intel_crt_init(dev_priv);
16272 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16273 DRM_DEBUG_KMS("probing SDVOB\n");
16274 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16275 if (!found && IS_G4X(dev_priv)) {
16276 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
16277 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16280 if (!found && IS_G4X(dev_priv))
16281 intel_dp_init(dev_priv, DP_B, PORT_B);
16284 /* Before G4X SDVOC doesn't have its own detect register */
16286 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16287 DRM_DEBUG_KMS("probing SDVOC\n");
16288 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16291 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
16293 if (IS_G4X(dev_priv)) {
16294 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
16295 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16297 if (IS_G4X(dev_priv))
16298 intel_dp_init(dev_priv, DP_C, PORT_C);
16301 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
16302 intel_dp_init(dev_priv, DP_D, PORT_D);
16304 if (SUPPORTS_TV(dev_priv))
16305 intel_tv_init(dev_priv);
16306 } else if (IS_GEN(dev_priv, 2)) {
16307 if (IS_I85X(dev_priv))
16308 intel_lvds_init(dev_priv);
16310 intel_crt_init(dev_priv);
16311 intel_dvo_init(dev_priv);
16314 intel_psr_init(dev_priv);
16316 for_each_intel_encoder(&dev_priv->drm, encoder) {
16317 encoder->base.possible_crtcs =
16318 intel_encoder_possible_crtcs(encoder);
16319 encoder->base.possible_clones =
16320 intel_encoder_possible_clones(encoder);
16323 intel_init_pch_refclk(dev_priv);
16325 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16328 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16330 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16332 drm_framebuffer_cleanup(fb);
16333 intel_frontbuffer_put(intel_fb->frontbuffer);
16338 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16339 struct drm_file *file,
16340 unsigned int *handle)
16342 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16344 if (obj->userptr.mm) {
16345 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
16349 return drm_gem_handle_create(file, &obj->base, handle);
16352 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16353 struct drm_file *file,
16354 unsigned flags, unsigned color,
16355 struct drm_clip_rect *clips,
16356 unsigned num_clips)
16358 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16360 i915_gem_object_flush_if_display(obj);
16361 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16366 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16367 .destroy = intel_user_framebuffer_destroy,
16368 .create_handle = intel_user_framebuffer_create_handle,
16369 .dirty = intel_user_framebuffer_dirty,
16372 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16373 struct drm_i915_gem_object *obj,
16374 struct drm_mode_fb_cmd2 *mode_cmd)
16376 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16377 struct drm_framebuffer *fb = &intel_fb->base;
16379 unsigned int tiling, stride;
16383 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16384 if (!intel_fb->frontbuffer)
16387 i915_gem_object_lock(obj);
16388 tiling = i915_gem_object_get_tiling(obj);
16389 stride = i915_gem_object_get_stride(obj);
16390 i915_gem_object_unlock(obj);
16392 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16394 * If there's a fence, enforce that
16395 * the fb modifier and tiling mode match.
16397 if (tiling != I915_TILING_NONE &&
16398 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16399 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
16403 if (tiling == I915_TILING_X) {
16404 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16405 } else if (tiling == I915_TILING_Y) {
16406 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
16411 if (!drm_any_plane_has_format(&dev_priv->drm,
16412 mode_cmd->pixel_format,
16413 mode_cmd->modifier[0])) {
16414 struct drm_format_name_buf format_name;
16416 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
16417 drm_get_format_name(mode_cmd->pixel_format,
16419 mode_cmd->modifier[0]);
16424 * gen2/3 display engine uses the fence if present,
16425 * so the tiling mode must match the fb modifier exactly.
16427 if (INTEL_GEN(dev_priv) < 4 &&
16428 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16429 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
16433 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
16434 mode_cmd->modifier[0]);
16435 if (mode_cmd->pitches[0] > max_stride) {
16436 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
16437 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
16438 "tiled" : "linear",
16439 mode_cmd->pitches[0], max_stride);
16444 * If there's a fence, enforce that
16445 * the fb pitch and fence stride match.
16447 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
16448 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
16449 mode_cmd->pitches[0], stride);
16453 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16454 if (mode_cmd->offsets[0] != 0)
16457 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
16459 for (i = 0; i < fb->format->num_planes; i++) {
16460 u32 stride_alignment;
16462 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
16463 DRM_DEBUG_KMS("bad plane %d handle\n", i);
16467 stride_alignment = intel_fb_stride_alignment(fb, i);
16470 * Display WA #0531: skl,bxt,kbl,glk
16472 * Render decompression and plane width > 3840
16473 * combined with horizontal panning requires the
16474 * plane stride to be a multiple of 4. We'll just
16475 * require the entire fb to accommodate that to avoid
16476 * potential runtime errors at plane configuration time.
16478 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
16479 is_ccs_modifier(fb->modifier))
16480 stride_alignment *= 4;
16482 if (fb->pitches[i] & (stride_alignment - 1)) {
16483 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
16484 i, fb->pitches[i], stride_alignment);
16488 fb->obj[i] = &obj->base;
16491 ret = intel_fill_fb_info(dev_priv, fb);
16495 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
16497 DRM_ERROR("framebuffer init failed %d\n", ret);
16504 intel_frontbuffer_put(intel_fb->frontbuffer);
16508 static struct drm_framebuffer *
16509 intel_user_framebuffer_create(struct drm_device *dev,
16510 struct drm_file *filp,
16511 const struct drm_mode_fb_cmd2 *user_mode_cmd)
16513 struct drm_framebuffer *fb;
16514 struct drm_i915_gem_object *obj;
16515 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16517 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16519 return ERR_PTR(-ENOENT);
16521 fb = intel_framebuffer_create(obj, &mode_cmd);
16522 i915_gem_object_put(obj);
16527 static void intel_atomic_state_free(struct drm_atomic_state *state)
16529 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16531 drm_atomic_state_default_release(state);
16533 i915_sw_fence_fini(&intel_state->commit_ready);
16538 static enum drm_mode_status
16539 intel_mode_valid(struct drm_device *dev,
16540 const struct drm_display_mode *mode)
16542 struct drm_i915_private *dev_priv = to_i915(dev);
16543 int hdisplay_max, htotal_max;
16544 int vdisplay_max, vtotal_max;
16547 * Can't reject DBLSCAN here because Xorg ddxen can add piles
16548 * of DBLSCAN modes to the output's mode list when they detect
16549 * the scaling mode property on the connector. And they don't
16550 * ask the kernel to validate those modes in any way until
16551 * modeset time at which point the client gets a protocol error.
16552 * So in order to not upset those clients we silently ignore the
16553 * DBLSCAN flag on such connectors. For other connectors we will
16554 * reject modes with the DBLSCAN flag in encoder->compute_config().
16555 * And we always reject DBLSCAN modes in connector->mode_valid()
16556 * as we never want such modes on the connector's mode list.
16559 if (mode->vscan > 1)
16560 return MODE_NO_VSCAN;
16562 if (mode->flags & DRM_MODE_FLAG_HSKEW)
16563 return MODE_H_ILLEGAL;
16565 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
16566 DRM_MODE_FLAG_NCSYNC |
16567 DRM_MODE_FLAG_PCSYNC))
16570 if (mode->flags & (DRM_MODE_FLAG_BCAST |
16571 DRM_MODE_FLAG_PIXMUX |
16572 DRM_MODE_FLAG_CLKDIV2))
16575 /* Transcoder timing limits */
16576 if (INTEL_GEN(dev_priv) >= 11) {
16577 hdisplay_max = 16384;
16578 vdisplay_max = 8192;
16579 htotal_max = 16384;
16581 } else if (INTEL_GEN(dev_priv) >= 9 ||
16582 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
16583 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
16584 vdisplay_max = 4096;
16587 } else if (INTEL_GEN(dev_priv) >= 3) {
16588 hdisplay_max = 4096;
16589 vdisplay_max = 4096;
16593 hdisplay_max = 2048;
16594 vdisplay_max = 2048;
16599 if (mode->hdisplay > hdisplay_max ||
16600 mode->hsync_start > htotal_max ||
16601 mode->hsync_end > htotal_max ||
16602 mode->htotal > htotal_max)
16603 return MODE_H_ILLEGAL;
16605 if (mode->vdisplay > vdisplay_max ||
16606 mode->vsync_start > vtotal_max ||
16607 mode->vsync_end > vtotal_max ||
16608 mode->vtotal > vtotal_max)
16609 return MODE_V_ILLEGAL;
16611 if (INTEL_GEN(dev_priv) >= 5) {
16612 if (mode->hdisplay < 64 ||
16613 mode->htotal - mode->hdisplay < 32)
16614 return MODE_H_ILLEGAL;
16616 if (mode->vtotal - mode->vdisplay < 5)
16617 return MODE_V_ILLEGAL;
16619 if (mode->htotal - mode->hdisplay < 32)
16620 return MODE_H_ILLEGAL;
16622 if (mode->vtotal - mode->vdisplay < 3)
16623 return MODE_V_ILLEGAL;
16629 enum drm_mode_status
16630 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
16631 const struct drm_display_mode *mode)
16633 int plane_width_max, plane_height_max;
16636 * intel_mode_valid() should be
16637 * sufficient on older platforms.
16639 if (INTEL_GEN(dev_priv) < 9)
16643 * Most people will probably want a fullscreen
16644 * plane so let's not advertize modes that are
16645 * too big for that.
16647 if (INTEL_GEN(dev_priv) >= 11) {
16648 plane_width_max = 5120;
16649 plane_height_max = 4320;
16651 plane_width_max = 5120;
16652 plane_height_max = 4096;
16655 if (mode->hdisplay > plane_width_max)
16656 return MODE_H_ILLEGAL;
16658 if (mode->vdisplay > plane_height_max)
16659 return MODE_V_ILLEGAL;
16664 static const struct drm_mode_config_funcs intel_mode_funcs = {
16665 .fb_create = intel_user_framebuffer_create,
16666 .get_format_info = intel_get_format_info,
16667 .output_poll_changed = intel_fbdev_output_poll_changed,
16668 .mode_valid = intel_mode_valid,
16669 .atomic_check = intel_atomic_check,
16670 .atomic_commit = intel_atomic_commit,
16671 .atomic_state_alloc = intel_atomic_state_alloc,
16672 .atomic_state_clear = intel_atomic_state_clear,
16673 .atomic_state_free = intel_atomic_state_free,
16677 * intel_init_display_hooks - initialize the display modesetting hooks
16678 * @dev_priv: device private
16680 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16682 intel_init_cdclk_hooks(dev_priv);
16684 if (INTEL_GEN(dev_priv) >= 9) {
16685 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16686 dev_priv->display.get_initial_plane_config =
16687 skylake_get_initial_plane_config;
16688 dev_priv->display.crtc_compute_clock =
16689 haswell_crtc_compute_clock;
16690 dev_priv->display.crtc_enable = haswell_crtc_enable;
16691 dev_priv->display.crtc_disable = haswell_crtc_disable;
16692 } else if (HAS_DDI(dev_priv)) {
16693 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16694 dev_priv->display.get_initial_plane_config =
16695 i9xx_get_initial_plane_config;
16696 dev_priv->display.crtc_compute_clock =
16697 haswell_crtc_compute_clock;
16698 dev_priv->display.crtc_enable = haswell_crtc_enable;
16699 dev_priv->display.crtc_disable = haswell_crtc_disable;
16700 } else if (HAS_PCH_SPLIT(dev_priv)) {
16701 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16702 dev_priv->display.get_initial_plane_config =
16703 i9xx_get_initial_plane_config;
16704 dev_priv->display.crtc_compute_clock =
16705 ironlake_crtc_compute_clock;
16706 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16707 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16708 } else if (IS_CHERRYVIEW(dev_priv)) {
16709 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16710 dev_priv->display.get_initial_plane_config =
16711 i9xx_get_initial_plane_config;
16712 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16713 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16714 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16715 } else if (IS_VALLEYVIEW(dev_priv)) {
16716 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16717 dev_priv->display.get_initial_plane_config =
16718 i9xx_get_initial_plane_config;
16719 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16720 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16721 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16722 } else if (IS_G4X(dev_priv)) {
16723 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16724 dev_priv->display.get_initial_plane_config =
16725 i9xx_get_initial_plane_config;
16726 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16727 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16728 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16729 } else if (IS_PINEVIEW(dev_priv)) {
16730 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16731 dev_priv->display.get_initial_plane_config =
16732 i9xx_get_initial_plane_config;
16733 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16734 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16735 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16736 } else if (!IS_GEN(dev_priv, 2)) {
16737 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16738 dev_priv->display.get_initial_plane_config =
16739 i9xx_get_initial_plane_config;
16740 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16741 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16742 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16744 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16745 dev_priv->display.get_initial_plane_config =
16746 i9xx_get_initial_plane_config;
16747 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16748 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16749 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16752 if (IS_GEN(dev_priv, 5)) {
16753 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16754 } else if (IS_GEN(dev_priv, 6)) {
16755 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16756 } else if (IS_IVYBRIDGE(dev_priv)) {
16757 /* FIXME: detect B0+ stepping and use auto training */
16758 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16759 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16760 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16763 if (INTEL_GEN(dev_priv) >= 9)
16764 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
16766 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
16770 void intel_modeset_init_hw(struct drm_i915_private *i915)
16772 intel_update_cdclk(i915);
16773 intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
16774 i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
16778 * Calculate what we think the watermarks should be for the state we've read
16779 * out of the hardware and then immediately program those watermarks so that
16780 * we ensure the hardware settings match our internal state.
16782 * We can calculate what we think WM's should be by creating a duplicate of the
16783 * current state (which was constructed during hardware readout) and running it
16784 * through the atomic check code to calculate new watermark values in the
16787 static void sanitize_watermarks(struct drm_device *dev)
16789 struct drm_i915_private *dev_priv = to_i915(dev);
16790 struct drm_atomic_state *state;
16791 struct intel_atomic_state *intel_state;
16792 struct intel_crtc *crtc;
16793 struct intel_crtc_state *crtc_state;
16794 struct drm_modeset_acquire_ctx ctx;
16798 /* Only supported on platforms that use atomic watermark design */
16799 if (!dev_priv->display.optimize_watermarks)
16803 * We need to hold connection_mutex before calling duplicate_state so
16804 * that the connector loop is protected.
16806 drm_modeset_acquire_init(&ctx, 0);
16808 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16809 if (ret == -EDEADLK) {
16810 drm_modeset_backoff(&ctx);
16812 } else if (WARN_ON(ret)) {
16816 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16817 if (WARN_ON(IS_ERR(state)))
16820 intel_state = to_intel_atomic_state(state);
16823 * Hardware readout is the only time we don't want to calculate
16824 * intermediate watermarks (since we don't trust the current
16827 if (!HAS_GMCH(dev_priv))
16828 intel_state->skip_intermediate_wm = true;
16830 ret = intel_atomic_check(dev, state);
16833 * If we fail here, it means that the hardware appears to be
16834 * programmed in a way that shouldn't be possible, given our
16835 * understanding of watermark requirements. This might mean a
16836 * mistake in the hardware readout code or a mistake in the
16837 * watermark calculations for a given platform. Raise a WARN
16838 * so that this is noticeable.
16840 * If this actually happens, we'll have to just leave the
16841 * BIOS-programmed watermarks untouched and hope for the best.
16843 WARN(true, "Could not determine valid watermarks for inherited state\n");
16847 /* Write calculated watermark values back */
16848 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16849 crtc_state->wm.need_postvbl_update = true;
16850 dev_priv->display.optimize_watermarks(intel_state, crtc);
16852 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16856 drm_atomic_state_put(state);
16858 drm_modeset_drop_locks(&ctx);
16859 drm_modeset_acquire_fini(&ctx);
16862 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16864 if (IS_GEN(dev_priv, 5)) {
16866 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16868 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16869 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16870 dev_priv->fdi_pll_freq = 270000;
16875 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16878 static int intel_initial_commit(struct drm_device *dev)
16880 struct drm_atomic_state *state = NULL;
16881 struct drm_modeset_acquire_ctx ctx;
16882 struct intel_crtc *crtc;
16885 state = drm_atomic_state_alloc(dev);
16889 drm_modeset_acquire_init(&ctx, 0);
16892 state->acquire_ctx = &ctx;
16894 for_each_intel_crtc(dev, crtc) {
16895 struct intel_crtc_state *crtc_state =
16896 intel_atomic_get_crtc_state(state, crtc);
16898 if (IS_ERR(crtc_state)) {
16899 ret = PTR_ERR(crtc_state);
16903 if (crtc_state->hw.active) {
16904 ret = drm_atomic_add_affected_planes(state, &crtc->base);
16909 * FIXME hack to force a LUT update to avoid the
16910 * plane update forcing the pipe gamma on without
16911 * having a proper LUT loaded. Remove once we
16912 * have readout for pipe gamma enable.
16914 crtc_state->uapi.color_mgmt_changed = true;
16918 ret = drm_atomic_commit(state);
16921 if (ret == -EDEADLK) {
16922 drm_atomic_state_clear(state);
16923 drm_modeset_backoff(&ctx);
16927 drm_atomic_state_put(state);
16929 drm_modeset_drop_locks(&ctx);
16930 drm_modeset_acquire_fini(&ctx);
16935 static void intel_mode_config_init(struct drm_i915_private *i915)
16937 struct drm_mode_config *mode_config = &i915->drm.mode_config;
16939 drm_mode_config_init(&i915->drm);
16941 mode_config->min_width = 0;
16942 mode_config->min_height = 0;
16944 mode_config->preferred_depth = 24;
16945 mode_config->prefer_shadow = 1;
16947 mode_config->allow_fb_modifiers = true;
16949 mode_config->funcs = &intel_mode_funcs;
16952 * Maximum framebuffer dimensions, chosen to match
16953 * the maximum render engine surface size on gen4+.
16955 if (INTEL_GEN(i915) >= 7) {
16956 mode_config->max_width = 16384;
16957 mode_config->max_height = 16384;
16958 } else if (INTEL_GEN(i915) >= 4) {
16959 mode_config->max_width = 8192;
16960 mode_config->max_height = 8192;
16961 } else if (IS_GEN(i915, 3)) {
16962 mode_config->max_width = 4096;
16963 mode_config->max_height = 4096;
16965 mode_config->max_width = 2048;
16966 mode_config->max_height = 2048;
16969 if (IS_I845G(i915) || IS_I865G(i915)) {
16970 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
16971 mode_config->cursor_height = 1023;
16972 } else if (IS_GEN(i915, 2)) {
16973 mode_config->cursor_width = 64;
16974 mode_config->cursor_height = 64;
16976 mode_config->cursor_width = 256;
16977 mode_config->cursor_height = 256;
16981 int intel_modeset_init(struct drm_i915_private *i915)
16983 struct drm_device *dev = &i915->drm;
16985 struct intel_crtc *crtc;
16988 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16989 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16990 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16992 intel_mode_config_init(i915);
16994 ret = intel_bw_init(i915);
16998 init_llist_head(&i915->atomic_helper.free_list);
16999 INIT_WORK(&i915->atomic_helper.free_work,
17000 intel_atomic_helper_free_state_worker);
17002 intel_init_quirks(i915);
17004 intel_fbc_init(i915);
17006 intel_init_pm(i915);
17008 intel_panel_sanitize_ssc(i915);
17010 intel_gmbus_setup(i915);
17012 DRM_DEBUG_KMS("%d display pipe%s available.\n",
17013 INTEL_NUM_PIPES(i915),
17014 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17016 if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
17017 for_each_pipe(i915, pipe) {
17018 ret = intel_crtc_init(i915, pipe);
17020 drm_mode_config_cleanup(dev);
17026 intel_shared_dpll_init(dev);
17027 intel_update_fdi_pll_freq(i915);
17029 intel_update_czclk(i915);
17030 intel_modeset_init_hw(i915);
17032 intel_hdcp_component_init(i915);
17034 if (i915->max_cdclk_freq == 0)
17035 intel_update_max_cdclk(i915);
17037 /* Just disable it once at startup */
17038 intel_vga_disable(i915);
17039 intel_setup_outputs(i915);
17041 drm_modeset_lock_all(dev);
17042 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17043 drm_modeset_unlock_all(dev);
17045 for_each_intel_crtc(dev, crtc) {
17046 struct intel_initial_plane_config plane_config = {};
17052 * Note that reserving the BIOS fb up front prevents us
17053 * from stuffing other stolen allocations like the ring
17054 * on top. This prevents some ugliness at boot time, and
17055 * can even allow for smooth boot transitions if the BIOS
17056 * fb is large enough for the active pipe configuration.
17058 i915->display.get_initial_plane_config(crtc, &plane_config);
17061 * If the fb is shared between multiple heads, we'll
17062 * just get the first one.
17064 intel_find_initial_plane_obj(crtc, &plane_config);
17068 * Make sure hardware watermarks really match the state we read out.
17069 * Note that we need to do this after reconstructing the BIOS fb's
17070 * since the watermark calculation done here will use pstate->fb.
17072 if (!HAS_GMCH(i915))
17073 sanitize_watermarks(dev);
17076 * Force all active planes to recompute their states. So that on
17077 * mode_setcrtc after probe, all the intel_plane_state variables
17078 * are already calculated and there is no assert_plane warnings
17081 ret = intel_initial_commit(dev);
17083 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
17088 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17090 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17091 /* 640x480@60Hz, ~25175 kHz */
17092 struct dpll clock = {
17102 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
17104 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17105 pipe_name(pipe), clock.vco, clock.dot);
17107 fp = i9xx_dpll_compute_fp(&clock);
17108 dpll = DPLL_DVO_2X_MODE |
17109 DPLL_VGA_MODE_DIS |
17110 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17111 PLL_P2_DIVIDE_BY_4 |
17112 PLL_REF_INPUT_DREFCLK |
17115 I915_WRITE(FP0(pipe), fp);
17116 I915_WRITE(FP1(pipe), fp);
17118 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17119 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17120 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17121 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17122 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17123 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17124 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17127 * Apparently we need to have VGA mode enabled prior to changing
17128 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17129 * dividers, even though the register value does change.
17131 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17132 I915_WRITE(DPLL(pipe), dpll);
17134 /* Wait for the clocks to stabilize. */
17135 POSTING_READ(DPLL(pipe));
17138 /* The pixel multiplier can only be updated once the
17139 * DPLL is enabled and the clocks are stable.
17141 * So write it again.
17143 I915_WRITE(DPLL(pipe), dpll);
17145 /* We do this three times for luck */
17146 for (i = 0; i < 3 ; i++) {
17147 I915_WRITE(DPLL(pipe), dpll);
17148 POSTING_READ(DPLL(pipe));
17149 udelay(150); /* wait for warmup */
17152 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17153 POSTING_READ(PIPECONF(pipe));
17155 intel_wait_for_pipe_scanline_moving(crtc);
17158 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17160 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17162 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
17165 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
17166 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
17167 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
17168 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
17169 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
17171 I915_WRITE(PIPECONF(pipe), 0);
17172 POSTING_READ(PIPECONF(pipe));
17174 intel_wait_for_pipe_scanline_stopped(crtc);
17176 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
17177 POSTING_READ(DPLL(pipe));
17181 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17183 struct intel_crtc *crtc;
17185 if (INTEL_GEN(dev_priv) >= 4)
17188 for_each_intel_crtc(&dev_priv->drm, crtc) {
17189 struct intel_plane *plane =
17190 to_intel_plane(crtc->base.primary);
17191 struct intel_crtc *plane_crtc;
17194 if (!plane->get_hw_state(plane, &pipe))
17197 if (pipe == crtc->pipe)
17200 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17201 plane->base.base.id, plane->base.name);
17203 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17204 intel_plane_disable_noatomic(plane_crtc, plane);
17208 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17210 struct drm_device *dev = crtc->base.dev;
17211 struct intel_encoder *encoder;
17213 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17219 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17221 struct drm_device *dev = encoder->base.dev;
17222 struct intel_connector *connector;
17224 for_each_connector_on_encoder(dev, &encoder->base, connector)
17230 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17231 enum pipe pch_transcoder)
17233 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17234 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17237 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
17239 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
17240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
17241 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17243 if (INTEL_GEN(dev_priv) >= 9 ||
17244 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17245 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
17248 if (transcoder_is_dsi(cpu_transcoder))
17251 val = I915_READ(reg);
17252 val &= ~HSW_FRAME_START_DELAY_MASK;
17253 val |= HSW_FRAME_START_DELAY(0);
17254 I915_WRITE(reg, val);
17256 i915_reg_t reg = PIPECONF(cpu_transcoder);
17259 val = I915_READ(reg);
17260 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
17261 val |= PIPECONF_FRAME_START_DELAY(0);
17262 I915_WRITE(reg, val);
17265 if (!crtc_state->has_pch_encoder)
17268 if (HAS_PCH_IBX(dev_priv)) {
17269 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
17272 val = I915_READ(reg);
17273 val &= ~TRANS_FRAME_START_DELAY_MASK;
17274 val |= TRANS_FRAME_START_DELAY(0);
17275 I915_WRITE(reg, val);
17277 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
17278 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
17281 val = I915_READ(reg);
17282 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
17283 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
17284 I915_WRITE(reg, val);
17288 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17289 struct drm_modeset_acquire_ctx *ctx)
17291 struct drm_device *dev = crtc->base.dev;
17292 struct drm_i915_private *dev_priv = to_i915(dev);
17293 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17295 if (crtc_state->hw.active) {
17296 struct intel_plane *plane;
17298 /* Clear any frame start delays used for debugging left by the BIOS */
17299 intel_sanitize_frame_start_delay(crtc_state);
17301 /* Disable everything but the primary plane */
17302 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17303 const struct intel_plane_state *plane_state =
17304 to_intel_plane_state(plane->base.state);
17306 if (plane_state->uapi.visible &&
17307 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17308 intel_plane_disable_noatomic(crtc, plane);
17312 * Disable any background color set by the BIOS, but enable the
17313 * gamma and CSC to match how we program our planes.
17315 if (INTEL_GEN(dev_priv) >= 9)
17316 I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
17317 SKL_BOTTOM_COLOR_GAMMA_ENABLE |
17318 SKL_BOTTOM_COLOR_CSC_ENABLE);
17321 /* Adjust the state of the output pipe according to whether we
17322 * have active connectors/encoders. */
17323 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
17324 intel_crtc_disable_noatomic(crtc, ctx);
17326 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
17328 * We start out with underrun reporting disabled to avoid races.
17329 * For correct bookkeeping mark this on active crtcs.
17331 * Also on gmch platforms we dont have any hardware bits to
17332 * disable the underrun reporting. Which means we need to start
17333 * out with underrun reporting disabled also on inactive pipes,
17334 * since otherwise we'll complain about the garbage we read when
17335 * e.g. coming up after runtime pm.
17337 * No protection against concurrent access is required - at
17338 * worst a fifo underrun happens which also sets this to false.
17340 crtc->cpu_fifo_underrun_disabled = true;
17342 * We track the PCH trancoder underrun reporting state
17343 * within the crtc. With crtc for pipe A housing the underrun
17344 * reporting state for PCH transcoder A, crtc for pipe B housing
17345 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
17346 * and marking underrun reporting as disabled for the non-existing
17347 * PCH transcoders B and C would prevent enabling the south
17348 * error interrupt (see cpt_can_enable_serr_int()).
17350 if (has_pch_trancoder(dev_priv, crtc->pipe))
17351 crtc->pch_fifo_underrun_disabled = true;
17355 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
17357 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
17360 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
17361 * the hardware when a high res displays plugged in. DPLL P
17362 * divider is zero, and the pipe timings are bonkers. We'll
17363 * try to disable everything in that case.
17365 * FIXME would be nice to be able to sanitize this state
17366 * without several WARNs, but for now let's take the easy
17369 return IS_GEN(dev_priv, 6) &&
17370 crtc_state->hw.active &&
17371 crtc_state->shared_dpll &&
17372 crtc_state->port_clock == 0;
17375 static void intel_sanitize_encoder(struct intel_encoder *encoder)
17377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
17378 struct intel_connector *connector;
17379 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
17380 struct intel_crtc_state *crtc_state = crtc ?
17381 to_intel_crtc_state(crtc->base.state) : NULL;
17383 /* We need to check both for a crtc link (meaning that the
17384 * encoder is active and trying to read from a pipe) and the
17385 * pipe itself being active. */
17386 bool has_active_crtc = crtc_state &&
17387 crtc_state->hw.active;
17389 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
17390 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
17391 pipe_name(crtc->pipe));
17392 has_active_crtc = false;
17395 connector = intel_encoder_find_connector(encoder);
17396 if (connector && !has_active_crtc) {
17397 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
17398 encoder->base.base.id,
17399 encoder->base.name);
17401 /* Connector is active, but has no active pipe. This is
17402 * fallout from our resume register restoring. Disable
17403 * the encoder manually again. */
17405 struct drm_encoder *best_encoder;
17407 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
17408 encoder->base.base.id,
17409 encoder->base.name);
17411 /* avoid oopsing in case the hooks consult best_encoder */
17412 best_encoder = connector->base.state->best_encoder;
17413 connector->base.state->best_encoder = &encoder->base;
17415 if (encoder->disable)
17416 encoder->disable(encoder, crtc_state,
17417 connector->base.state);
17418 if (encoder->post_disable)
17419 encoder->post_disable(encoder, crtc_state,
17420 connector->base.state);
17422 connector->base.state->best_encoder = best_encoder;
17424 encoder->base.crtc = NULL;
17426 /* Inconsistent output/port/pipe state happens presumably due to
17427 * a bug in one of the get_hw_state functions. Or someplace else
17428 * in our code, like the register restore mess on resume. Clamp
17429 * things to off as a safer default. */
17431 connector->base.dpms = DRM_MODE_DPMS_OFF;
17432 connector->base.encoder = NULL;
17435 /* notify opregion of the sanitized encoder state */
17436 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
17438 if (INTEL_GEN(dev_priv) >= 11)
17439 icl_sanitize_encoder_pll_mapping(encoder);
17442 /* FIXME read out full plane state for all planes */
17443 static void readout_plane_state(struct drm_i915_private *dev_priv)
17445 struct intel_plane *plane;
17446 struct intel_crtc *crtc;
17448 for_each_intel_plane(&dev_priv->drm, plane) {
17449 struct intel_plane_state *plane_state =
17450 to_intel_plane_state(plane->base.state);
17451 struct intel_crtc_state *crtc_state;
17452 enum pipe pipe = PIPE_A;
17455 visible = plane->get_hw_state(plane, &pipe);
17457 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17458 crtc_state = to_intel_crtc_state(crtc->base.state);
17460 intel_set_plane_visible(crtc_state, plane_state, visible);
17462 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
17463 plane->base.base.id, plane->base.name,
17464 enableddisabled(visible), pipe_name(pipe));
17467 for_each_intel_crtc(&dev_priv->drm, crtc) {
17468 struct intel_crtc_state *crtc_state =
17469 to_intel_crtc_state(crtc->base.state);
17471 fixup_active_planes(crtc_state);
17475 static void intel_modeset_readout_hw_state(struct drm_device *dev)
17477 struct drm_i915_private *dev_priv = to_i915(dev);
17479 struct intel_crtc *crtc;
17480 struct intel_encoder *encoder;
17481 struct intel_connector *connector;
17482 struct drm_connector_list_iter conn_iter;
17485 dev_priv->active_pipes = 0;
17487 for_each_intel_crtc(dev, crtc) {
17488 struct intel_crtc_state *crtc_state =
17489 to_intel_crtc_state(crtc->base.state);
17491 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
17492 intel_crtc_free_hw_state(crtc_state);
17493 memset(crtc_state, 0, sizeof(*crtc_state));
17494 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
17496 crtc_state->hw.active = crtc_state->hw.enable =
17497 dev_priv->display.get_pipe_config(crtc, crtc_state);
17499 crtc->base.enabled = crtc_state->hw.enable;
17500 crtc->active = crtc_state->hw.active;
17502 if (crtc_state->hw.active)
17503 dev_priv->active_pipes |= BIT(crtc->pipe);
17505 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17506 crtc->base.base.id, crtc->base.name,
17507 enableddisabled(crtc_state->hw.active));
17510 readout_plane_state(dev_priv);
17512 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17513 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17515 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
17516 &pll->state.hw_state);
17518 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
17519 pll->info->id == DPLL_ID_EHL_DPLL4) {
17520 pll->wakeref = intel_display_power_get(dev_priv,
17521 POWER_DOMAIN_DPLL_DC_OFF);
17524 pll->state.crtc_mask = 0;
17525 for_each_intel_crtc(dev, crtc) {
17526 struct intel_crtc_state *crtc_state =
17527 to_intel_crtc_state(crtc->base.state);
17529 if (crtc_state->hw.active &&
17530 crtc_state->shared_dpll == pll)
17531 pll->state.crtc_mask |= 1 << crtc->pipe;
17533 pll->active_mask = pll->state.crtc_mask;
17535 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17536 pll->info->name, pll->state.crtc_mask, pll->on);
17539 for_each_intel_encoder(dev, encoder) {
17542 if (encoder->get_hw_state(encoder, &pipe)) {
17543 struct intel_crtc_state *crtc_state;
17545 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17546 crtc_state = to_intel_crtc_state(crtc->base.state);
17548 encoder->base.crtc = &crtc->base;
17549 encoder->get_config(encoder, crtc_state);
17551 encoder->base.crtc = NULL;
17554 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17555 encoder->base.base.id, encoder->base.name,
17556 enableddisabled(encoder->base.crtc),
17560 drm_connector_list_iter_begin(dev, &conn_iter);
17561 for_each_intel_connector_iter(connector, &conn_iter) {
17562 if (connector->get_hw_state(connector)) {
17563 struct intel_crtc_state *crtc_state;
17564 struct intel_crtc *crtc;
17566 connector->base.dpms = DRM_MODE_DPMS_ON;
17568 encoder = connector->encoder;
17569 connector->base.encoder = &encoder->base;
17571 crtc = to_intel_crtc(encoder->base.crtc);
17572 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
17574 if (crtc_state && crtc_state->hw.active) {
17576 * This has to be done during hardware readout
17577 * because anything calling .crtc_disable may
17578 * rely on the connector_mask being accurate.
17580 crtc_state->uapi.connector_mask |=
17581 drm_connector_mask(&connector->base);
17582 crtc_state->uapi.encoder_mask |=
17583 drm_encoder_mask(&encoder->base);
17586 connector->base.dpms = DRM_MODE_DPMS_OFF;
17587 connector->base.encoder = NULL;
17589 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17590 connector->base.base.id, connector->base.name,
17591 enableddisabled(connector->base.encoder));
17593 drm_connector_list_iter_end(&conn_iter);
17595 for_each_intel_crtc(dev, crtc) {
17596 struct intel_bw_state *bw_state =
17597 to_intel_bw_state(dev_priv->bw_obj.state);
17598 struct intel_crtc_state *crtc_state =
17599 to_intel_crtc_state(crtc->base.state);
17600 struct intel_plane *plane;
17603 if (crtc_state->hw.active) {
17604 struct drm_display_mode *mode = &crtc_state->hw.mode;
17606 intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
17609 *mode = crtc_state->hw.adjusted_mode;
17610 mode->hdisplay = crtc_state->pipe_src_w;
17611 mode->vdisplay = crtc_state->pipe_src_h;
17614 * The initial mode needs to be set in order to keep
17615 * the atomic core happy. It wants a valid mode if the
17616 * crtc's enabled, so we do the above call.
17618 * But we don't set all the derived state fully, hence
17619 * set a flag to indicate that a full recalculation is
17620 * needed on the next commit.
17622 mode->private_flags = I915_MODE_FLAG_INHERITED;
17624 intel_crtc_compute_pixel_rate(crtc_state);
17626 intel_crtc_update_active_timings(crtc_state);
17628 intel_crtc_copy_hw_to_uapi_state(crtc_state);
17631 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
17632 const struct intel_plane_state *plane_state =
17633 to_intel_plane_state(plane->base.state);
17636 * FIXME don't have the fb yet, so can't
17637 * use intel_plane_data_rate() :(
17639 if (plane_state->uapi.visible)
17640 crtc_state->data_rate[plane->id] =
17641 4 * crtc_state->pixel_rate;
17643 * FIXME don't have the fb yet, so can't
17644 * use plane->min_cdclk() :(
17646 if (plane_state->uapi.visible && plane->min_cdclk) {
17647 if (crtc_state->double_wide ||
17648 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
17649 crtc_state->min_cdclk[plane->id] =
17650 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
17652 crtc_state->min_cdclk[plane->id] =
17653 crtc_state->pixel_rate;
17655 DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n",
17656 plane->base.base.id, plane->base.name,
17657 crtc_state->min_cdclk[plane->id]);
17660 if (crtc_state->hw.active) {
17661 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
17662 if (WARN_ON(min_cdclk < 0))
17666 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
17667 dev_priv->min_voltage_level[crtc->pipe] =
17668 crtc_state->min_voltage_level;
17670 intel_bw_crtc_update(bw_state, crtc_state);
17672 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17677 get_encoder_power_domains(struct drm_i915_private *dev_priv)
17679 struct intel_encoder *encoder;
17681 for_each_intel_encoder(&dev_priv->drm, encoder) {
17682 struct intel_crtc_state *crtc_state;
17684 if (!encoder->get_power_domains)
17688 * MST-primary and inactive encoders don't have a crtc state
17689 * and neither of these require any power domain references.
17691 if (!encoder->base.crtc)
17694 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
17695 encoder->get_power_domains(encoder, crtc_state);
17699 static void intel_early_display_was(struct drm_i915_private *dev_priv)
17701 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
17702 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
17703 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
17706 if (IS_HASWELL(dev_priv)) {
17708 * WaRsPkgCStateDisplayPMReq:hsw
17709 * System hang if this isn't done before disabling all planes!
17711 I915_WRITE(CHICKEN_PAR1_1,
17712 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
17716 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
17717 enum port port, i915_reg_t hdmi_reg)
17719 u32 val = I915_READ(hdmi_reg);
17721 if (val & SDVO_ENABLE ||
17722 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
17725 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
17728 val &= ~SDVO_PIPE_SEL_MASK;
17729 val |= SDVO_PIPE_SEL(PIPE_A);
17731 I915_WRITE(hdmi_reg, val);
17734 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
17735 enum port port, i915_reg_t dp_reg)
17737 u32 val = I915_READ(dp_reg);
17739 if (val & DP_PORT_EN ||
17740 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
17743 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
17746 val &= ~DP_PIPE_SEL_MASK;
17747 val |= DP_PIPE_SEL(PIPE_A);
17749 I915_WRITE(dp_reg, val);
17752 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
17755 * The BIOS may select transcoder B on some of the PCH
17756 * ports even it doesn't enable the port. This would trip
17757 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
17758 * Sanitize the transcoder select bits to prevent that. We
17759 * assume that the BIOS never actually enabled the port,
17760 * because if it did we'd actually have to toggle the port
17761 * on and back off to make the transcoder A select stick
17762 * (see. intel_dp_link_down(), intel_disable_hdmi(),
17763 * intel_disable_sdvo()).
17765 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
17766 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
17767 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
17769 /* PCH SDVOB multiplex with HDMIB */
17770 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
17771 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
17772 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
17775 /* Scan out the current hw modeset state,
17776 * and sanitizes it to the current state
17779 intel_modeset_setup_hw_state(struct drm_device *dev,
17780 struct drm_modeset_acquire_ctx *ctx)
17782 struct drm_i915_private *dev_priv = to_i915(dev);
17783 struct intel_encoder *encoder;
17784 struct intel_crtc *crtc;
17785 intel_wakeref_t wakeref;
17788 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17790 intel_early_display_was(dev_priv);
17791 intel_modeset_readout_hw_state(dev);
17793 /* HW state is read out, now we need to sanitize this mess. */
17795 /* Sanitize the TypeC port mode upfront, encoders depend on this */
17796 for_each_intel_encoder(dev, encoder) {
17797 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17799 /* We need to sanitize only the MST primary port. */
17800 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17801 intel_phy_is_tc(dev_priv, phy))
17802 intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17805 get_encoder_power_domains(dev_priv);
17807 if (HAS_PCH_IBX(dev_priv))
17808 ibx_sanitize_pch_ports(dev_priv);
17811 * intel_sanitize_plane_mapping() may need to do vblank
17812 * waits, so we need vblank interrupts restored beforehand.
17814 for_each_intel_crtc(&dev_priv->drm, crtc) {
17815 struct intel_crtc_state *crtc_state =
17816 to_intel_crtc_state(crtc->base.state);
17818 drm_crtc_vblank_reset(&crtc->base);
17820 if (crtc_state->hw.active)
17821 intel_crtc_vblank_on(crtc_state);
17824 intel_sanitize_plane_mapping(dev_priv);
17826 for_each_intel_encoder(dev, encoder)
17827 intel_sanitize_encoder(encoder);
17829 for_each_intel_crtc(&dev_priv->drm, crtc) {
17830 struct intel_crtc_state *crtc_state =
17831 crtc_state = to_intel_crtc_state(crtc->base.state);
17833 intel_sanitize_crtc(crtc, ctx);
17834 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17837 intel_modeset_update_connector_atomic_state(dev);
17839 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17840 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17842 if (!pll->on || pll->active_mask)
17845 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17848 pll->info->funcs->disable(dev_priv, pll);
17852 if (IS_G4X(dev_priv)) {
17853 g4x_wm_get_hw_state(dev_priv);
17854 g4x_wm_sanitize(dev_priv);
17855 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17856 vlv_wm_get_hw_state(dev_priv);
17857 vlv_wm_sanitize(dev_priv);
17858 } else if (INTEL_GEN(dev_priv) >= 9) {
17859 skl_wm_get_hw_state(dev_priv);
17860 } else if (HAS_PCH_SPLIT(dev_priv)) {
17861 ilk_wm_get_hw_state(dev_priv);
17864 for_each_intel_crtc(dev, crtc) {
17865 struct intel_crtc_state *crtc_state =
17866 to_intel_crtc_state(crtc->base.state);
17869 put_domains = modeset_get_crtc_power_domains(crtc_state);
17870 if (WARN_ON(put_domains))
17871 modeset_put_power_domains(dev_priv, put_domains);
17874 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17876 intel_fbc_init_pipe_state(dev_priv);
17879 void intel_display_resume(struct drm_device *dev)
17881 struct drm_i915_private *dev_priv = to_i915(dev);
17882 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17883 struct drm_modeset_acquire_ctx ctx;
17886 dev_priv->modeset_restore_state = NULL;
17888 state->acquire_ctx = &ctx;
17890 drm_modeset_acquire_init(&ctx, 0);
17893 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17894 if (ret != -EDEADLK)
17897 drm_modeset_backoff(&ctx);
17901 ret = __intel_display_resume(dev, state, &ctx);
17903 intel_enable_ipc(dev_priv);
17904 drm_modeset_drop_locks(&ctx);
17905 drm_modeset_acquire_fini(&ctx);
17908 DRM_ERROR("Restoring old state failed with %i\n", ret);
17910 drm_atomic_state_put(state);
17913 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
17915 struct intel_connector *connector;
17916 struct drm_connector_list_iter conn_iter;
17918 /* Kill all the work that may have been queued by hpd. */
17919 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
17920 for_each_intel_connector_iter(connector, &conn_iter) {
17921 if (connector->modeset_retry_work.func)
17922 cancel_work_sync(&connector->modeset_retry_work);
17923 if (connector->hdcp.shim) {
17924 cancel_delayed_work_sync(&connector->hdcp.check_work);
17925 cancel_work_sync(&connector->hdcp.prop_work);
17928 drm_connector_list_iter_end(&conn_iter);
17931 void intel_modeset_driver_remove(struct drm_i915_private *i915)
17933 flush_workqueue(i915->flip_wq);
17934 flush_workqueue(i915->modeset_wq);
17936 flush_work(&i915->atomic_helper.free_work);
17937 WARN_ON(!llist_empty(&i915->atomic_helper.free_list));
17940 * Interrupts and polling as the first thing to avoid creating havoc.
17941 * Too much stuff here (turning of connectors, ...) would
17942 * experience fancy races otherwise.
17944 intel_irq_uninstall(i915);
17947 * Due to the hpd irq storm handling the hotplug work can re-arm the
17948 * poll handlers. Hence disable polling after hpd handling is shut down.
17950 intel_hpd_poll_fini(i915);
17953 * MST topology needs to be suspended so we don't have any calls to
17954 * fbdev after it's finalized. MST will be destroyed later as part of
17955 * drm_mode_config_cleanup()
17957 intel_dp_mst_suspend(i915);
17959 /* poll work can call into fbdev, hence clean that up afterwards */
17960 intel_fbdev_fini(i915);
17962 intel_unregister_dsm_handler();
17964 intel_fbc_global_disable(i915);
17966 /* flush any delayed tasks or pending work */
17967 flush_scheduled_work();
17969 intel_hdcp_component_fini(i915);
17971 drm_mode_config_cleanup(&i915->drm);
17973 intel_overlay_cleanup(i915);
17975 intel_gmbus_teardown(i915);
17977 destroy_workqueue(i915->flip_wq);
17978 destroy_workqueue(i915->modeset_wq);
17980 intel_fbc_cleanup_cfb(i915);
17983 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17985 struct intel_display_error_state {
17987 u32 power_well_driver;
17989 struct intel_cursor_error_state {
17994 } cursor[I915_MAX_PIPES];
17996 struct intel_pipe_error_state {
17997 bool power_domain_on;
18000 } pipe[I915_MAX_PIPES];
18002 struct intel_plane_error_state {
18010 } plane[I915_MAX_PIPES];
18012 struct intel_transcoder_error_state {
18014 bool power_domain_on;
18015 enum transcoder cpu_transcoder;
18028 struct intel_display_error_state *
18029 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
18031 struct intel_display_error_state *error;
18032 int transcoders[] = {
18041 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
18043 if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
18046 error = kzalloc(sizeof(*error), GFP_ATOMIC);
18050 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18051 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
18053 for_each_pipe(dev_priv, i) {
18054 error->pipe[i].power_domain_on =
18055 __intel_display_power_is_enabled(dev_priv,
18056 POWER_DOMAIN_PIPE(i));
18057 if (!error->pipe[i].power_domain_on)
18060 error->cursor[i].control = I915_READ(CURCNTR(i));
18061 error->cursor[i].position = I915_READ(CURPOS(i));
18062 error->cursor[i].base = I915_READ(CURBASE(i));
18064 error->plane[i].control = I915_READ(DSPCNTR(i));
18065 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
18066 if (INTEL_GEN(dev_priv) <= 3) {
18067 error->plane[i].size = I915_READ(DSPSIZE(i));
18068 error->plane[i].pos = I915_READ(DSPPOS(i));
18070 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18071 error->plane[i].addr = I915_READ(DSPADDR(i));
18072 if (INTEL_GEN(dev_priv) >= 4) {
18073 error->plane[i].surface = I915_READ(DSPSURF(i));
18074 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
18077 error->pipe[i].source = I915_READ(PIPESRC(i));
18079 if (HAS_GMCH(dev_priv))
18080 error->pipe[i].stat = I915_READ(PIPESTAT(i));
18083 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18084 enum transcoder cpu_transcoder = transcoders[i];
18086 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
18089 error->transcoder[i].available = true;
18090 error->transcoder[i].power_domain_on =
18091 __intel_display_power_is_enabled(dev_priv,
18092 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18093 if (!error->transcoder[i].power_domain_on)
18096 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18098 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
18099 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
18100 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
18101 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
18102 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
18103 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
18104 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
18110 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18113 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18114 struct intel_display_error_state *error)
18116 struct drm_i915_private *dev_priv = m->i915;
18122 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18123 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18124 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18125 error->power_well_driver);
18126 for_each_pipe(dev_priv, i) {
18127 err_printf(m, "Pipe [%d]:\n", i);
18128 err_printf(m, " Power: %s\n",
18129 onoff(error->pipe[i].power_domain_on));
18130 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
18131 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
18133 err_printf(m, "Plane [%d]:\n", i);
18134 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
18135 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
18136 if (INTEL_GEN(dev_priv) <= 3) {
18137 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
18138 err_printf(m, " POS: %08x\n", error->plane[i].pos);
18140 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18141 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
18142 if (INTEL_GEN(dev_priv) >= 4) {
18143 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
18144 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
18147 err_printf(m, "Cursor [%d]:\n", i);
18148 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
18149 err_printf(m, " POS: %08x\n", error->cursor[i].position);
18150 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
18153 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18154 if (!error->transcoder[i].available)
18157 err_printf(m, "CPU transcoder: %s\n",
18158 transcoder_name(error->transcoder[i].cpu_transcoder));
18159 err_printf(m, " Power: %s\n",
18160 onoff(error->transcoder[i].power_domain_on));
18161 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
18162 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
18163 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
18164 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
18165 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
18166 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
18167 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);