drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <drm/i915_drm.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_fbc.h"
  70 #include "intel_fbdev.h"
  71 #include "intel_fifo_underrun.h"
  72 #include "intel_frontbuffer.h"
  73 #include "intel_hdcp.h"
  74 #include "intel_hotplug.h"
  75 #include "intel_overlay.h"
  76 #include "intel_pipe_crc.h"
  77 #include "intel_pm.h"
  78 #include "intel_psr.h"
  79 #include "intel_quirks.h"
  80 #include "intel_sideband.h"
  81 #include "intel_sprite.h"
  82 #include "intel_tc.h"
  83 #include "intel_vga.h"
  84
  85 /* Primary plane formats for gen <= 3 */
  86 static const u32 i8xx_primary_formats[] = {
  87         DRM_FORMAT_C8,
  88         DRM_FORMAT_RGB565,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_XRGB8888,
  91 };
  92
  93 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  94 static const u32 ivb_primary_formats[] = {
  95         DRM_FORMAT_C8,
  96         DRM_FORMAT_RGB565,
  97         DRM_FORMAT_XRGB8888,
  98         DRM_FORMAT_XBGR8888,
  99         DRM_FORMAT_XRGB2101010,
 100         DRM_FORMAT_XBGR2101010,
 101 };
 102
 103 /* Primary plane formats for gen >= 4, except ivb */
 104 static const u32 i965_primary_formats[] = {
 105         DRM_FORMAT_C8,
 106         DRM_FORMAT_RGB565,
 107         DRM_FORMAT_XRGB8888,
 108         DRM_FORMAT_XBGR8888,
 109         DRM_FORMAT_XRGB2101010,
 110         DRM_FORMAT_XBGR2101010,
 111         DRM_FORMAT_XBGR16161616F,
 112 };
 113
 114 static const u64 i9xx_format_modifiers[] = {
 115         I915_FORMAT_MOD_X_TILED,
 116         DRM_FORMAT_MOD_LINEAR,
 117         DRM_FORMAT_MOD_INVALID
 118 };
 119
 120 /* Cursor formats */
 121 static const u32 intel_cursor_formats[] = {
 122         DRM_FORMAT_ARGB8888,
 123 };
 124
 125 static const u64 cursor_format_modifiers[] = {
 126         DRM_FORMAT_MOD_LINEAR,
 127         DRM_FORMAT_MOD_INVALID
 128 };
 129
 130 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 131                                 struct intel_crtc_state *pipe_config);
 132 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 133                                    struct intel_crtc_state *pipe_config);
 134
 135 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 136                                   struct drm_i915_gem_object *obj,
 137                                   struct drm_mode_fb_cmd2 *mode_cmd);
 138 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 139 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 140 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 141                                          const struct intel_link_m_n *m_n,
 142                                          const struct intel_link_m_n *m2_n2);
 143 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 144 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 145 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
 146 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 147 static void vlv_prepare_pll(struct intel_crtc *crtc,
 148                             const struct intel_crtc_state *pipe_config);
 149 static void chv_prepare_pll(struct intel_crtc *crtc,
 150                             const struct intel_crtc_state *pipe_config);
 151 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 152                                     struct intel_crtc_state *crtc_state);
 153 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
 154 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 155 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 156 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 157                                          struct drm_modeset_acquire_ctx *ctx);
 158 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 159
 160 struct intel_limit {
 161         struct {
 162                 int min, max;
 163         } dot, vco, n, m, m1, m2, p, p1;
 164
 165         struct {
 166                 int dot_limit;
 167                 int p2_slow, p2_fast;
 168         } p2;
 169 };
 170
 171 /* returns HPLL frequency in kHz */
 172 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 173 {
 174         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 175
 176         /* Obtain SKU information */
 177         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 178                 CCK_FUSE_HPLL_FREQ_MASK;
 179
 180         return vco_freq[hpll_freq] * 1000;
 181 }
 182
 183 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 184                       const char *name, u32 reg, int ref_freq)
 185 {
 186         u32 val;
 187         int divider;
 188
 189         val = vlv_cck_read(dev_priv, reg);
 190         divider = val & CCK_FREQUENCY_VALUES;
 191
 192         WARN((val & CCK_FREQUENCY_STATUS) !=
 193              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 194              "%s change in progress\n", name);
 195
 196         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 197 }
 198
 199 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 200                            const char *name, u32 reg)
 201 {
 202         int hpll;
 203
 204         vlv_cck_get(dev_priv);
 205
 206         if (dev_priv->hpll_freq == 0)
 207                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 208
 209         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 210
 211         vlv_cck_put(dev_priv);
 212
 213         return hpll;
 214 }
 215
 216 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 217 {
 218         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 219                 return;
 220
 221         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 222                                                       CCK_CZ_CLOCK_CONTROL);
 223
 224         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 225 }
 226
 227 static inline u32 /* units of 100MHz */
 228 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 229                     const struct intel_crtc_state *pipe_config)
 230 {
 231         if (HAS_DDI(dev_priv))
 232                 return pipe_config->port_clock; /* SPLL */
 233         else
 234                 return dev_priv->fdi_pll_freq;
 235 }
 236
 237 static const struct intel_limit intel_limits_i8xx_dac = {
 238         .dot = { .min = 25000, .max = 350000 },
 239         .vco = { .min = 908000, .max = 1512000 },
 240         .n = { .min = 2, .max = 16 },
 241         .m = { .min = 96, .max = 140 },
 242         .m1 = { .min = 18, .max = 26 },
 243         .m2 = { .min = 6, .max = 16 },
 244         .p = { .min = 4, .max = 128 },
 245         .p1 = { .min = 2, .max = 33 },
 246         .p2 = { .dot_limit = 165000,
 247                 .p2_slow = 4, .p2_fast = 2 },
 248 };
 249
 250 static const struct intel_limit intel_limits_i8xx_dvo = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 908000, .max = 1512000 },
 253         .n = { .min = 2, .max = 16 },
 254         .m = { .min = 96, .max = 140 },
 255         .m1 = { .min = 18, .max = 26 },
 256         .m2 = { .min = 6, .max = 16 },
 257         .p = { .min = 4, .max = 128 },
 258         .p1 = { .min = 2, .max = 33 },
 259         .p2 = { .dot_limit = 165000,
 260                 .p2_slow = 4, .p2_fast = 4 },
 261 };
 262
 263 static const struct intel_limit intel_limits_i8xx_lvds = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 1, .max = 6 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 14, .p2_fast = 7 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i9xx_sdvo = {
 277         .dot = { .min = 20000, .max = 400000 },
 278         .vco = { .min = 1400000, .max = 2800000 },
 279         .n = { .min = 1, .max = 6 },
 280         .m = { .min = 70, .max = 120 },
 281         .m1 = { .min = 8, .max = 18 },
 282         .m2 = { .min = 3, .max = 7 },
 283         .p = { .min = 5, .max = 80 },
 284         .p1 = { .min = 1, .max = 8 },
 285         .p2 = { .dot_limit = 200000,
 286                 .p2_slow = 10, .p2_fast = 5 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i9xx_lvds = {
 290         .dot = { .min = 20000, .max = 400000 },
 291         .vco = { .min = 1400000, .max = 2800000 },
 292         .n = { .min = 1, .max = 6 },
 293         .m = { .min = 70, .max = 120 },
 294         .m1 = { .min = 8, .max = 18 },
 295         .m2 = { .min = 3, .max = 7 },
 296         .p = { .min = 7, .max = 98 },
 297         .p1 = { .min = 1, .max = 8 },
 298         .p2 = { .dot_limit = 112000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302
 303 static const struct intel_limit intel_limits_g4x_sdvo = {
 304         .dot = { .min = 25000, .max = 270000 },
 305         .vco = { .min = 1750000, .max = 3500000},
 306         .n = { .min = 1, .max = 4 },
 307         .m = { .min = 104, .max = 138 },
 308         .m1 = { .min = 17, .max = 23 },
 309         .m2 = { .min = 5, .max = 11 },
 310         .p = { .min = 10, .max = 30 },
 311         .p1 = { .min = 1, .max = 3},
 312         .p2 = { .dot_limit = 270000,
 313                 .p2_slow = 10,
 314                 .p2_fast = 10
 315         },
 316 };
 317
 318 static const struct intel_limit intel_limits_g4x_hdmi = {
 319         .dot = { .min = 22000, .max = 400000 },
 320         .vco = { .min = 1750000, .max = 3500000},
 321         .n = { .min = 1, .max = 4 },
 322         .m = { .min = 104, .max = 138 },
 323         .m1 = { .min = 16, .max = 23 },
 324         .m2 = { .min = 5, .max = 11 },
 325         .p = { .min = 5, .max = 80 },
 326         .p1 = { .min = 1, .max = 8},
 327         .p2 = { .dot_limit = 165000,
 328                 .p2_slow = 10, .p2_fast = 5 },
 329 };
 330
 331 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 332         .dot = { .min = 20000, .max = 115000 },
 333         .vco = { .min = 1750000, .max = 3500000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 104, .max = 138 },
 336         .m1 = { .min = 17, .max = 23 },
 337         .m2 = { .min = 5, .max = 11 },
 338         .p = { .min = 28, .max = 112 },
 339         .p1 = { .min = 2, .max = 8 },
 340         .p2 = { .dot_limit = 0,
 341                 .p2_slow = 14, .p2_fast = 14
 342         },
 343 };
 344
 345 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 346         .dot = { .min = 80000, .max = 224000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 14, .max = 42 },
 353         .p1 = { .min = 2, .max = 6 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 7, .p2_fast = 7
 356         },
 357 };
 358
 359 static const struct intel_limit intel_limits_pineview_sdvo = {
 360         .dot = { .min = 20000, .max = 400000},
 361         .vco = { .min = 1700000, .max = 3500000 },
 362         /* Pineview's Ncounter is a ring counter */
 363         .n = { .min = 3, .max = 6 },
 364         .m = { .min = 2, .max = 256 },
 365         /* Pineview only has one combined m divider, which we treat as m2. */
 366         .m1 = { .min = 0, .max = 0 },
 367         .m2 = { .min = 0, .max = 254 },
 368         .p = { .min = 5, .max = 80 },
 369         .p1 = { .min = 1, .max = 8 },
 370         .p2 = { .dot_limit = 200000,
 371                 .p2_slow = 10, .p2_fast = 5 },
 372 };
 373
 374 static const struct intel_limit intel_limits_pineview_lvds = {
 375         .dot = { .min = 20000, .max = 400000 },
 376         .vco = { .min = 1700000, .max = 3500000 },
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         .m1 = { .min = 0, .max = 0 },
 380         .m2 = { .min = 0, .max = 254 },
 381         .p = { .min = 7, .max = 112 },
 382         .p1 = { .min = 1, .max = 8 },
 383         .p2 = { .dot_limit = 112000,
 384                 .p2_slow = 14, .p2_fast = 14 },
 385 };
 386
 387 /* Ironlake / Sandybridge
 388  *
 389  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 390  * the range value for them is (actual_value - 2).
 391  */
 392 static const struct intel_limit intel_limits_ironlake_dac = {
 393         .dot = { .min = 25000, .max = 350000 },
 394         .vco = { .min = 1760000, .max = 3510000 },
 395         .n = { .min = 1, .max = 5 },
 396         .m = { .min = 79, .max = 127 },
 397         .m1 = { .min = 12, .max = 22 },
 398         .m2 = { .min = 5, .max = 9 },
 399         .p = { .min = 5, .max = 80 },
 400         .p1 = { .min = 1, .max = 8 },
 401         .p2 = { .dot_limit = 225000,
 402                 .p2_slow = 10, .p2_fast = 5 },
 403 };
 404
 405 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 406         .dot = { .min = 25000, .max = 350000 },
 407         .vco = { .min = 1760000, .max = 3510000 },
 408         .n = { .min = 1, .max = 3 },
 409         .m = { .min = 79, .max = 118 },
 410         .m1 = { .min = 12, .max = 22 },
 411         .m2 = { .min = 5, .max = 9 },
 412         .p = { .min = 28, .max = 112 },
 413         .p1 = { .min = 2, .max = 8 },
 414         .p2 = { .dot_limit = 225000,
 415                 .p2_slow = 14, .p2_fast = 14 },
 416 };
 417
 418 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 3 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 14, .max = 56 },
 426         .p1 = { .min = 2, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 7, .p2_fast = 7 },
 429 };
 430
 431 /* LVDS 100mhz refclk limits. */
 432 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 2 },
 436         .m = { .min = 79, .max = 126 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 28, .max = 112 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 14, .p2_fast = 14 },
 443 };
 444
 445 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 446         .dot = { .min = 25000, .max = 350000 },
 447         .vco = { .min = 1760000, .max = 3510000 },
 448         .n = { .min = 1, .max = 3 },
 449         .m = { .min = 79, .max = 126 },
 450         .m1 = { .min = 12, .max = 22 },
 451         .m2 = { .min = 5, .max = 9 },
 452         .p = { .min = 14, .max = 42 },
 453         .p1 = { .min = 2, .max = 6 },
 454         .p2 = { .dot_limit = 225000,
 455                 .p2_slow = 7, .p2_fast = 7 },
 456 };
 457
 458 static const struct intel_limit intel_limits_vlv = {
 459          /*
 460           * These are the data rate limits (measured in fast clocks)
 461           * since those are the strictest limits we have. The fast
 462           * clock and actual rate limits are more relaxed, so checking
 463           * them would make no difference.
 464           */
 465         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 466         .vco = { .min = 4000000, .max = 6000000 },
 467         .n = { .min = 1, .max = 7 },
 468         .m1 = { .min = 2, .max = 3 },
 469         .m2 = { .min = 11, .max = 156 },
 470         .p1 = { .min = 2, .max = 3 },
 471         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 472 };
 473
 474 static const struct intel_limit intel_limits_chv = {
 475         /*
 476          * These are the data rate limits (measured in fast clocks)
 477          * since those are the strictest limits we have.  The fast
 478          * clock and actual rate limits are more relaxed, so checking
 479          * them would make no difference.
 480          */
 481         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 482         .vco = { .min = 4800000, .max = 6480000 },
 483         .n = { .min = 1, .max = 1 },
 484         .m1 = { .min = 2, .max = 2 },
 485         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 486         .p1 = { .min = 2, .max = 4 },
 487         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 488 };
 489
 490 static const struct intel_limit intel_limits_bxt = {
 491         /* FIXME: find real dot limits */
 492         .dot = { .min = 0, .max = INT_MAX },
 493         .vco = { .min = 4800000, .max = 6700000 },
 494         .n = { .min = 1, .max = 1 },
 495         .m1 = { .min = 2, .max = 2 },
 496         /* FIXME: find real m2 limits */
 497         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 498         .p1 = { .min = 2, .max = 4 },
 499         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 500 };
 501
 502 /* WA Display #0827: Gen9:all */
 503 static void
 504 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 505 {
 506         if (enable)
 507                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 508                            I915_READ(CLKGATE_DIS_PSL(pipe)) |
 509                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 510         else
 511                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 512                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 513                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 514 }
 515
 516 /* Wa_2006604312:icl */
 517 static void
 518 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 519                        bool enable)
 520 {
 521         if (enable)
 522                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 523                            I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 524         else
 525                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 526                            I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 527 }
 528
 529 static bool
 530 needs_modeset(const struct intel_crtc_state *state)
 531 {
 532         return drm_atomic_crtc_needs_modeset(&state->uapi);
 533 }
 534
 535 bool
 536 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 537 {
 538         return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
 539                 crtc_state->sync_mode_slaves_mask);
 540 }
 541
 542 static bool
 543 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 544 {
 545         return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
 546                 crtc_state->sync_mode_slaves_mask);
 547 }
 548
 549 /*
 550  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 551  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 552  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 553  * The helpers' return value is the rate of the clock that is fed to the
 554  * display engine's pipe which can be the above fast dot clock rate or a
 555  * divided-down version of it.
 556  */
 557 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 558 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 559 {
 560         clock->m = clock->m2 + 2;
 561         clock->p = clock->p1 * clock->p2;
 562         if (WARN_ON(clock->n == 0 || clock->p == 0))
 563                 return 0;
 564         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 565         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 566
 567         return clock->dot;
 568 }
 569
 570 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 571 {
 572         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 573 }
 574
 575 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 576 {
 577         clock->m = i9xx_dpll_compute_m(clock);
 578         clock->p = clock->p1 * clock->p2;
 579         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 580                 return 0;
 581         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 582         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 583
 584         return clock->dot;
 585 }
 586
 587 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 588 {
 589         clock->m = clock->m1 * clock->m2;
 590         clock->p = clock->p1 * clock->p2;
 591         if (WARN_ON(clock->n == 0 || clock->p == 0))
 592                 return 0;
 593         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 594         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 595
 596         return clock->dot / 5;
 597 }
 598
 599 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 600 {
 601         clock->m = clock->m1 * clock->m2;
 602         clock->p = clock->p1 * clock->p2;
 603         if (WARN_ON(clock->n == 0 || clock->p == 0))
 604                 return 0;
 605         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 606                                            clock->n << 22);
 607         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 608
 609         return clock->dot / 5;
 610 }
 611
 612 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 613
 614 /*
 615  * Returns whether the given set of divisors are valid for a given refclk with
 616  * the given connectors.
 617  */
 618 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 619                                const struct intel_limit *limit,
 620                                const struct dpll *clock)
 621 {
 622         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 623                 INTELPllInvalid("n out of range\n");
 624         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 625                 INTELPllInvalid("p1 out of range\n");
 626         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 627                 INTELPllInvalid("m2 out of range\n");
 628         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 629                 INTELPllInvalid("m1 out of range\n");
 630
 631         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 632             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 633                 if (clock->m1 <= clock->m2)
 634                         INTELPllInvalid("m1 <= m2\n");
 635
 636         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 637             !IS_GEN9_LP(dev_priv)) {
 638                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 639                         INTELPllInvalid("p out of range\n");
 640                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 641                         INTELPllInvalid("m out of range\n");
 642         }
 643
 644         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 645                 INTELPllInvalid("vco out of range\n");
 646         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 647          * connector, etc., rather than just a single range.
 648          */
 649         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 650                 INTELPllInvalid("dot out of range\n");
 651
 652         return true;
 653 }
 654
 655 static int
 656 i9xx_select_p2_div(const struct intel_limit *limit,
 657                    const struct intel_crtc_state *crtc_state,
 658                    int target)
 659 {
 660         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 661
 662         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 663                 /*
 664                  * For LVDS just rely on its current settings for dual-channel.
 665                  * We haven't figured out how to reliably set up different
 666                  * single/dual channel state, if we even can.
 667                  */
 668                 if (intel_is_dual_link_lvds(dev_priv))
 669                         return limit->p2.p2_fast;
 670                 else
 671                         return limit->p2.p2_slow;
 672         } else {
 673                 if (target < limit->p2.dot_limit)
 674                         return limit->p2.p2_slow;
 675                 else
 676                         return limit->p2.p2_fast;
 677         }
 678 }
 679
 680 /*
 681  * Returns a set of divisors for the desired target clock with the given
 682  * refclk, or FALSE.  The returned values represent the clock equation:
 683  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 684  *
 685  * Target and reference clocks are specified in kHz.
 686  *
 687  * If match_clock is provided, then best_clock P divider must match the P
 688  * divider from @match_clock used for LVDS downclocking.
 689  */
 690 static bool
 691 i9xx_find_best_dpll(const struct intel_limit *limit,
 692                     struct intel_crtc_state *crtc_state,
 693                     int target, int refclk, struct dpll *match_clock,
 694                     struct dpll *best_clock)
 695 {
 696         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 697         struct dpll clock;
 698         int err = target;
 699
 700         memset(best_clock, 0, sizeof(*best_clock));
 701
 702         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 703
 704         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 705              clock.m1++) {
 706                 for (clock.m2 = limit->m2.min;
 707                      clock.m2 <= limit->m2.max; clock.m2++) {
 708                         if (clock.m2 >= clock.m1)
 709                                 break;
 710                         for (clock.n = limit->n.min;
 711                              clock.n <= limit->n.max; clock.n++) {
 712                                 for (clock.p1 = limit->p1.min;
 713                                         clock.p1 <= limit->p1.max; clock.p1++) {
 714                                         int this_err;
 715
 716                                         i9xx_calc_dpll_params(refclk, &clock);
 717                                         if (!intel_PLL_is_valid(to_i915(dev),
 718                                                                 limit,
 719                                                                 &clock))
 720                                                 continue;
 721                                         if (match_clock &&
 722                                             clock.p != match_clock->p)
 723                                                 continue;
 724
 725                                         this_err = abs(clock.dot - target);
 726                                         if (this_err < err) {
 727                                                 *best_clock = clock;
 728                                                 err = this_err;
 729                                         }
 730                                 }
 731                         }
 732                 }
 733         }
 734
 735         return (err != target);
 736 }
 737
 738 /*
 739  * Returns a set of divisors for the desired target clock with the given
 740  * refclk, or FALSE.  The returned values represent the clock equation:
 741  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 742  *
 743  * Target and reference clocks are specified in kHz.
 744  *
 745  * If match_clock is provided, then best_clock P divider must match the P
 746  * divider from @match_clock used for LVDS downclocking.
 747  */
 748 static bool
 749 pnv_find_best_dpll(const struct intel_limit *limit,
 750                    struct intel_crtc_state *crtc_state,
 751                    int target, int refclk, struct dpll *match_clock,
 752                    struct dpll *best_clock)
 753 {
 754         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 755         struct dpll clock;
 756         int err = target;
 757
 758         memset(best_clock, 0, sizeof(*best_clock));
 759
 760         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 761
 762         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 763              clock.m1++) {
 764                 for (clock.m2 = limit->m2.min;
 765                      clock.m2 <= limit->m2.max; clock.m2++) {
 766                         for (clock.n = limit->n.min;
 767                              clock.n <= limit->n.max; clock.n++) {
 768                                 for (clock.p1 = limit->p1.min;
 769                                         clock.p1 <= limit->p1.max; clock.p1++) {
 770                                         int this_err;
 771
 772                                         pnv_calc_dpll_params(refclk, &clock);
 773                                         if (!intel_PLL_is_valid(to_i915(dev),
 774                                                                 limit,
 775                                                                 &clock))
 776                                                 continue;
 777                                         if (match_clock &&
 778                                             clock.p != match_clock->p)
 779                                                 continue;
 780
 781                                         this_err = abs(clock.dot - target);
 782                                         if (this_err < err) {
 783                                                 *best_clock = clock;
 784                                                 err = this_err;
 785                                         }
 786                                 }
 787                         }
 788                 }
 789         }
 790
 791         return (err != target);
 792 }
 793
 794 /*
 795  * Returns a set of divisors for the desired target clock with the given
 796  * refclk, or FALSE.  The returned values represent the clock equation:
 797  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 798  *
 799  * Target and reference clocks are specified in kHz.
 800  *
 801  * If match_clock is provided, then best_clock P divider must match the P
 802  * divider from @match_clock used for LVDS downclocking.
 803  */
 804 static bool
 805 g4x_find_best_dpll(const struct intel_limit *limit,
 806                    struct intel_crtc_state *crtc_state,
 807                    int target, int refclk, struct dpll *match_clock,
 808                    struct dpll *best_clock)
 809 {
 810         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 811         struct dpll clock;
 812         int max_n;
 813         bool found = false;
 814         /* approximately equals target * 0.00585 */
 815         int err_most = (target >> 8) + (target >> 9);
 816
 817         memset(best_clock, 0, sizeof(*best_clock));
 818
 819         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 820
 821         max_n = limit->n.max;
 822         /* based on hardware requirement, prefer smaller n to precision */
 823         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 824                 /* based on hardware requirement, prefere larger m1,m2 */
 825                 for (clock.m1 = limit->m1.max;
 826                      clock.m1 >= limit->m1.min; clock.m1--) {
 827                         for (clock.m2 = limit->m2.max;
 828                              clock.m2 >= limit->m2.min; clock.m2--) {
 829                                 for (clock.p1 = limit->p1.max;
 830                                      clock.p1 >= limit->p1.min; clock.p1--) {
 831                                         int this_err;
 832
 833                                         i9xx_calc_dpll_params(refclk, &clock);
 834                                         if (!intel_PLL_is_valid(to_i915(dev),
 835                                                                 limit,
 836                                                                 &clock))
 837                                                 continue;
 838
 839                                         this_err = abs(clock.dot - target);
 840                                         if (this_err < err_most) {
 841                                                 *best_clock = clock;
 842                                                 err_most = this_err;
 843                                                 max_n = clock.n;
 844                                                 found = true;
 845                                         }
 846                                 }
 847                         }
 848                 }
 849         }
 850         return found;
 851 }
 852
 853 /*
 854  * Check if the calculated PLL configuration is more optimal compared to the
 855  * best configuration and error found so far. Return the calculated error.
 856  */
 857 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 858                                const struct dpll *calculated_clock,
 859                                const struct dpll *best_clock,
 860                                unsigned int best_error_ppm,
 861                                unsigned int *error_ppm)
 862 {
 863         /*
 864          * For CHV ignore the error and consider only the P value.
 865          * Prefer a bigger P value based on HW requirements.
 866          */
 867         if (IS_CHERRYVIEW(to_i915(dev))) {
 868                 *error_ppm = 0;
 869
 870                 return calculated_clock->p > best_clock->p;
 871         }
 872
 873         if (WARN_ON_ONCE(!target_freq))
 874                 return false;
 875
 876         *error_ppm = div_u64(1000000ULL *
 877                                 abs(target_freq - calculated_clock->dot),
 878                              target_freq);
 879         /*
 880          * Prefer a better P value over a better (smaller) error if the error
 881          * is small. Ensure this preference for future configurations too by
 882          * setting the error to 0.
 883          */
 884         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 885                 *error_ppm = 0;
 886
 887                 return true;
 888         }
 889
 890         return *error_ppm + 10 < best_error_ppm;
 891 }
 892
 893 /*
 894  * Returns a set of divisors for the desired target clock with the given
 895  * refclk, or FALSE.  The returned values represent the clock equation:
 896  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 897  */
 898 static bool
 899 vlv_find_best_dpll(const struct intel_limit *limit,
 900                    struct intel_crtc_state *crtc_state,
 901                    int target, int refclk, struct dpll *match_clock,
 902                    struct dpll *best_clock)
 903 {
 904         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 905         struct drm_device *dev = crtc->base.dev;
 906         struct dpll clock;
 907         unsigned int bestppm = 1000000;
 908         /* min update 19.2 MHz */
 909         int max_n = min(limit->n.max, refclk / 19200);
 910         bool found = false;
 911
 912         target *= 5; /* fast clock */
 913
 914         memset(best_clock, 0, sizeof(*best_clock));
 915
 916         /* based on hardware requirement, prefer smaller n to precision */
 917         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 918                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 919                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 920                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 921                                 clock.p = clock.p1 * clock.p2;
 922                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 923                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 924                                         unsigned int ppm;
 925
 926                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 927                                                                      refclk * clock.m1);
 928
 929                                         vlv_calc_dpll_params(refclk, &clock);
 930
 931                                         if (!intel_PLL_is_valid(to_i915(dev),
 932                                                                 limit,
 933                                                                 &clock))
 934                                                 continue;
 935
 936                                         if (!vlv_PLL_is_optimal(dev, target,
 937                                                                 &clock,
 938                                                                 best_clock,
 939                                                                 bestppm, &ppm))
 940                                                 continue;
 941
 942                                         *best_clock = clock;
 943                                         bestppm = ppm;
 944                                         found = true;
 945                                 }
 946                         }
 947                 }
 948         }
 949
 950         return found;
 951 }
 952
 953 /*
 954  * Returns a set of divisors for the desired target clock with the given
 955  * refclk, or FALSE.  The returned values represent the clock equation:
 956  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 957  */
 958 static bool
 959 chv_find_best_dpll(const struct intel_limit *limit,
 960                    struct intel_crtc_state *crtc_state,
 961                    int target, int refclk, struct dpll *match_clock,
 962                    struct dpll *best_clock)
 963 {
 964         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 965         struct drm_device *dev = crtc->base.dev;
 966         unsigned int best_error_ppm;
 967         struct dpll clock;
 968         u64 m2;
 969         int found = false;
 970
 971         memset(best_clock, 0, sizeof(*best_clock));
 972         best_error_ppm = 1000000;
 973
 974         /*
 975          * Based on hardware doc, the n always set to 1, and m1 always
 976          * set to 2.  If requires to support 200Mhz refclk, we need to
 977          * revisit this because n may not 1 anymore.
 978          */
 979         clock.n = 1, clock.m1 = 2;
 980         target *= 5;    /* fast clock */
 981
 982         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 983                 for (clock.p2 = limit->p2.p2_fast;
 984                                 clock.p2 >= limit->p2.p2_slow;
 985                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 986                         unsigned int error_ppm;
 987
 988                         clock.p = clock.p1 * clock.p2;
 989
 990                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
 991                                                    refclk * clock.m1);
 992
 993                         if (m2 > INT_MAX/clock.m1)
 994                                 continue;
 995
 996                         clock.m2 = m2;
 997
 998                         chv_calc_dpll_params(refclk, &clock);
 999
1000                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1001                                 continue;
1002
1003                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1004                                                 best_error_ppm, &error_ppm))
1005                                 continue;
1006
1007                         *best_clock = clock;
1008                         best_error_ppm = error_ppm;
1009                         found = true;
1010                 }
1011         }
1012
1013         return found;
1014 }
1015
1016 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1017                         struct dpll *best_clock)
1018 {
1019         int refclk = 100000;
1020         const struct intel_limit *limit = &intel_limits_bxt;
1021
1022         return chv_find_best_dpll(limit, crtc_state,
1023                                   crtc_state->port_clock, refclk,
1024                                   NULL, best_clock);
1025 }
1026
1027 bool intel_crtc_active(struct intel_crtc *crtc)
1028 {
1029         /* Be paranoid as we can arrive here with only partial
1030          * state retrieved from the hardware during setup.
1031          *
1032          * We can ditch the adjusted_mode.crtc_clock check as soon
1033          * as Haswell has gained clock readout/fastboot support.
1034          *
1035          * We can ditch the crtc->primary->state->fb check as soon as we can
1036          * properly reconstruct framebuffers.
1037          *
1038          * FIXME: The intel_crtc->active here should be switched to
1039          * crtc->state->active once we have proper CRTC states wired up
1040          * for atomic.
1041          */
1042         return crtc->active && crtc->base.primary->state->fb &&
1043                 crtc->config->hw.adjusted_mode.crtc_clock;
1044 }
1045
1046 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1047                                              enum pipe pipe)
1048 {
1049         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1050
1051         return crtc->config->cpu_transcoder;
1052 }
1053
1054 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1055                                     enum pipe pipe)
1056 {
1057         i915_reg_t reg = PIPEDSL(pipe);
1058         u32 line1, line2;
1059         u32 line_mask;
1060
1061         if (IS_GEN(dev_priv, 2))
1062                 line_mask = DSL_LINEMASK_GEN2;
1063         else
1064                 line_mask = DSL_LINEMASK_GEN3;
1065
1066         line1 = I915_READ(reg) & line_mask;
1067         msleep(5);
1068         line2 = I915_READ(reg) & line_mask;
1069
1070         return line1 != line2;
1071 }
1072
1073 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1074 {
1075         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1076         enum pipe pipe = crtc->pipe;
1077
1078         /* Wait for the display line to settle/start moving */
1079         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1080                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1081                           pipe_name(pipe), onoff(state));
1082 }
1083
1084 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1085 {
1086         wait_for_pipe_scanline_moving(crtc, false);
1087 }
1088
1089 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1090 {
1091         wait_for_pipe_scanline_moving(crtc, true);
1092 }
1093
1094 static void
1095 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1096 {
1097         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1098         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1099
1100         if (INTEL_GEN(dev_priv) >= 4) {
1101                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1102                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1103
1104                 /* Wait for the Pipe State to go off */
1105                 if (intel_de_wait_for_clear(dev_priv, reg,
1106                                             I965_PIPECONF_ACTIVE, 100))
1107                         WARN(1, "pipe_off wait timed out\n");
1108         } else {
1109                 intel_wait_for_pipe_scanline_stopped(crtc);
1110         }
1111 }
1112
1113 /* Only for pre-ILK configs */
1114 void assert_pll(struct drm_i915_private *dev_priv,
1115                 enum pipe pipe, bool state)
1116 {
1117         u32 val;
1118         bool cur_state;
1119
1120         val = I915_READ(DPLL(pipe));
1121         cur_state = !!(val & DPLL_VCO_ENABLE);
1122         I915_STATE_WARN(cur_state != state,
1123              "PLL state assertion failure (expected %s, current %s)\n",
1124                         onoff(state), onoff(cur_state));
1125 }
1126
1127 /* XXX: the dsi pll is shared between MIPI DSI ports */
1128 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1129 {
1130         u32 val;
1131         bool cur_state;
1132
1133         vlv_cck_get(dev_priv);
1134         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1135         vlv_cck_put(dev_priv);
1136
1137         cur_state = val & DSI_PLL_VCO_EN;
1138         I915_STATE_WARN(cur_state != state,
1139              "DSI PLL state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142
1143 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1144                           enum pipe pipe, bool state)
1145 {
1146         bool cur_state;
1147         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1148                                                                       pipe);
1149
1150         if (HAS_DDI(dev_priv)) {
1151                 /* DDI does not have a specific FDI_TX register */
1152                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1153                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1154         } else {
1155                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1156                 cur_state = !!(val & FDI_TX_ENABLE);
1157         }
1158         I915_STATE_WARN(cur_state != state,
1159              "FDI TX state assertion failure (expected %s, current %s)\n",
1160                         onoff(state), onoff(cur_state));
1161 }
1162 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1163 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1164
1165 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1166                           enum pipe pipe, bool state)
1167 {
1168         u32 val;
1169         bool cur_state;
1170
1171         val = I915_READ(FDI_RX_CTL(pipe));
1172         cur_state = !!(val & FDI_RX_ENABLE);
1173         I915_STATE_WARN(cur_state != state,
1174              "FDI RX state assertion failure (expected %s, current %s)\n",
1175                         onoff(state), onoff(cur_state));
1176 }
1177 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1178 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1179
1180 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1181                                       enum pipe pipe)
1182 {
1183         u32 val;
1184
1185         /* ILK FDI PLL is always enabled */
1186         if (IS_GEN(dev_priv, 5))
1187                 return;
1188
1189         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1190         if (HAS_DDI(dev_priv))
1191                 return;
1192
1193         val = I915_READ(FDI_TX_CTL(pipe));
1194         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1195 }
1196
1197 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1198                        enum pipe pipe, bool state)
1199 {
1200         u32 val;
1201         bool cur_state;
1202
1203         val = I915_READ(FDI_RX_CTL(pipe));
1204         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1205         I915_STATE_WARN(cur_state != state,
1206              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1207                         onoff(state), onoff(cur_state));
1208 }
1209
1210 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1211 {
1212         i915_reg_t pp_reg;
1213         u32 val;
1214         enum pipe panel_pipe = INVALID_PIPE;
1215         bool locked = true;
1216
1217         if (WARN_ON(HAS_DDI(dev_priv)))
1218                 return;
1219
1220         if (HAS_PCH_SPLIT(dev_priv)) {
1221                 u32 port_sel;
1222
1223                 pp_reg = PP_CONTROL(0);
1224                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1225
1226                 switch (port_sel) {
1227                 case PANEL_PORT_SELECT_LVDS:
1228                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1229                         break;
1230                 case PANEL_PORT_SELECT_DPA:
1231                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1232                         break;
1233                 case PANEL_PORT_SELECT_DPC:
1234                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1235                         break;
1236                 case PANEL_PORT_SELECT_DPD:
1237                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1238                         break;
1239                 default:
1240                         MISSING_CASE(port_sel);
1241                         break;
1242                 }
1243         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1244                 /* presumably write lock depends on pipe, not port select */
1245                 pp_reg = PP_CONTROL(pipe);
1246                 panel_pipe = pipe;
1247         } else {
1248                 u32 port_sel;
1249
1250                 pp_reg = PP_CONTROL(0);
1251                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1252
1253                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1254                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1255         }
1256
1257         val = I915_READ(pp_reg);
1258         if (!(val & PANEL_POWER_ON) ||
1259             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1260                 locked = false;
1261
1262         I915_STATE_WARN(panel_pipe == pipe && locked,
1263              "panel assertion failure, pipe %c regs locked\n",
1264              pipe_name(pipe));
1265 }
1266
1267 void assert_pipe(struct drm_i915_private *dev_priv,
1268                  enum pipe pipe, bool state)
1269 {
1270         bool cur_state;
1271         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1272                                                                       pipe);
1273         enum intel_display_power_domain power_domain;
1274         intel_wakeref_t wakeref;
1275
1276         /* we keep both pipes enabled on 830 */
1277         if (IS_I830(dev_priv))
1278                 state = true;
1279
1280         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1281         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1282         if (wakeref) {
1283                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1284                 cur_state = !!(val & PIPECONF_ENABLE);
1285
1286                 intel_display_power_put(dev_priv, power_domain, wakeref);
1287         } else {
1288                 cur_state = false;
1289         }
1290
1291         I915_STATE_WARN(cur_state != state,
1292              "pipe %c assertion failure (expected %s, current %s)\n",
1293                         pipe_name(pipe), onoff(state), onoff(cur_state));
1294 }
1295
1296 static void assert_plane(struct intel_plane *plane, bool state)
1297 {
1298         enum pipe pipe;
1299         bool cur_state;
1300
1301         cur_state = plane->get_hw_state(plane, &pipe);
1302
1303         I915_STATE_WARN(cur_state != state,
1304                         "%s assertion failure (expected %s, current %s)\n",
1305                         plane->base.name, onoff(state), onoff(cur_state));
1306 }
1307
1308 #define assert_plane_enabled(p) assert_plane(p, true)
1309 #define assert_plane_disabled(p) assert_plane(p, false)
1310
1311 static void assert_planes_disabled(struct intel_crtc *crtc)
1312 {
1313         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1314         struct intel_plane *plane;
1315
1316         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1317                 assert_plane_disabled(plane);
1318 }
1319
1320 static void assert_vblank_disabled(struct drm_crtc *crtc)
1321 {
1322         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1323                 drm_crtc_vblank_put(crtc);
1324 }
1325
1326 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1327                                     enum pipe pipe)
1328 {
1329         u32 val;
1330         bool enabled;
1331
1332         val = I915_READ(PCH_TRANSCONF(pipe));
1333         enabled = !!(val & TRANS_ENABLE);
1334         I915_STATE_WARN(enabled,
1335              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1336              pipe_name(pipe));
1337 }
1338
1339 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1340                                    enum pipe pipe, enum port port,
1341                                    i915_reg_t dp_reg)
1342 {
1343         enum pipe port_pipe;
1344         bool state;
1345
1346         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1347
1348         I915_STATE_WARN(state && port_pipe == pipe,
1349                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1350                         port_name(port), pipe_name(pipe));
1351
1352         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1353                         "IBX PCH DP %c still using transcoder B\n",
1354                         port_name(port));
1355 }
1356
1357 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1358                                      enum pipe pipe, enum port port,
1359                                      i915_reg_t hdmi_reg)
1360 {
1361         enum pipe port_pipe;
1362         bool state;
1363
1364         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1365
1366         I915_STATE_WARN(state && port_pipe == pipe,
1367                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1368                         port_name(port), pipe_name(pipe));
1369
1370         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1371                         "IBX PCH HDMI %c still using transcoder B\n",
1372                         port_name(port));
1373 }
1374
1375 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1376                                       enum pipe pipe)
1377 {
1378         enum pipe port_pipe;
1379
1380         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1381         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1382         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1383
1384         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1385                         port_pipe == pipe,
1386                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1387                         pipe_name(pipe));
1388
1389         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1390                         port_pipe == pipe,
1391                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1392                         pipe_name(pipe));
1393
1394         /* PCH SDVOB multiplex with HDMIB */
1395         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1396         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1397         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1398 }
1399
1400 static void _vlv_enable_pll(struct intel_crtc *crtc,
1401                             const struct intel_crtc_state *pipe_config)
1402 {
1403         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1404         enum pipe pipe = crtc->pipe;
1405
1406         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1407         POSTING_READ(DPLL(pipe));
1408         udelay(150);
1409
1410         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1411                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1412 }
1413
1414 static void vlv_enable_pll(struct intel_crtc *crtc,
1415                            const struct intel_crtc_state *pipe_config)
1416 {
1417         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1418         enum pipe pipe = crtc->pipe;
1419
1420         assert_pipe_disabled(dev_priv, pipe);
1421
1422         /* PLL is protected by panel, make sure we can write it */
1423         assert_panel_unlocked(dev_priv, pipe);
1424
1425         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1426                 _vlv_enable_pll(crtc, pipe_config);
1427
1428         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1429         POSTING_READ(DPLL_MD(pipe));
1430 }
1431
1432
1433 static void _chv_enable_pll(struct intel_crtc *crtc,
1434                             const struct intel_crtc_state *pipe_config)
1435 {
1436         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1437         enum pipe pipe = crtc->pipe;
1438         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1439         u32 tmp;
1440
1441         vlv_dpio_get(dev_priv);
1442
1443         /* Enable back the 10bit clock to display controller */
1444         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1445         tmp |= DPIO_DCLKP_EN;
1446         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1447
1448         vlv_dpio_put(dev_priv);
1449
1450         /*
1451          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1452          */
1453         udelay(1);
1454
1455         /* Enable PLL */
1456         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457
1458         /* Check PLL is locked */
1459         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1460                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1461 }
1462
1463 static void chv_enable_pll(struct intel_crtc *crtc,
1464                            const struct intel_crtc_state *pipe_config)
1465 {
1466         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1467         enum pipe pipe = crtc->pipe;
1468
1469         assert_pipe_disabled(dev_priv, pipe);
1470
1471         /* PLL is protected by panel, make sure we can write it */
1472         assert_panel_unlocked(dev_priv, pipe);
1473
1474         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1475                 _chv_enable_pll(crtc, pipe_config);
1476
1477         if (pipe != PIPE_A) {
1478                 /*
1479                  * WaPixelRepeatModeFixForC0:chv
1480                  *
1481                  * DPLLCMD is AWOL. Use chicken bits to propagate
1482                  * the value from DPLLBMD to either pipe B or C.
1483                  */
1484                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1485                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1486                 I915_WRITE(CBR4_VLV, 0);
1487                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1488
1489                 /*
1490                  * DPLLB VGA mode also seems to cause problems.
1491                  * We should always have it disabled.
1492                  */
1493                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1494         } else {
1495                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1496                 POSTING_READ(DPLL_MD(pipe));
1497         }
1498 }
1499
1500 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1501 {
1502         if (IS_I830(dev_priv))
1503                 return false;
1504
1505         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1506 }
1507
1508 static void i9xx_enable_pll(struct intel_crtc *crtc,
1509                             const struct intel_crtc_state *crtc_state)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1512         i915_reg_t reg = DPLL(crtc->pipe);
1513         u32 dpll = crtc_state->dpll_hw_state.dpll;
1514         int i;
1515
1516         assert_pipe_disabled(dev_priv, crtc->pipe);
1517
1518         /* PLL is protected by panel, make sure we can write it */
1519         if (i9xx_has_pps(dev_priv))
1520                 assert_panel_unlocked(dev_priv, crtc->pipe);
1521
1522         /*
1523          * Apparently we need to have VGA mode enabled prior to changing
1524          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1525          * dividers, even though the register value does change.
1526          */
1527         I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1528         I915_WRITE(reg, dpll);
1529
1530         /* Wait for the clocks to stabilize. */
1531         POSTING_READ(reg);
1532         udelay(150);
1533
1534         if (INTEL_GEN(dev_priv) >= 4) {
1535                 I915_WRITE(DPLL_MD(crtc->pipe),
1536                            crtc_state->dpll_hw_state.dpll_md);
1537         } else {
1538                 /* The pixel multiplier can only be updated once the
1539                  * DPLL is enabled and the clocks are stable.
1540                  *
1541                  * So write it again.
1542                  */
1543                 I915_WRITE(reg, dpll);
1544         }
1545
1546         /* We do this three times for luck */
1547         for (i = 0; i < 3; i++) {
1548                 I915_WRITE(reg, dpll);
1549                 POSTING_READ(reg);
1550                 udelay(150); /* wait for warmup */
1551         }
1552 }
1553
1554 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1555 {
1556         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1558         enum pipe pipe = crtc->pipe;
1559
1560         /* Don't disable pipe or pipe PLLs if needed */
1561         if (IS_I830(dev_priv))
1562                 return;
1563
1564         /* Make sure the pipe isn't still relying on us */
1565         assert_pipe_disabled(dev_priv, pipe);
1566
1567         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1568         POSTING_READ(DPLL(pipe));
1569 }
1570
1571 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1572 {
1573         u32 val;
1574
1575         /* Make sure the pipe isn't still relying on us */
1576         assert_pipe_disabled(dev_priv, pipe);
1577
1578         val = DPLL_INTEGRATED_REF_CLK_VLV |
1579                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1580         if (pipe != PIPE_A)
1581                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1582
1583         I915_WRITE(DPLL(pipe), val);
1584         POSTING_READ(DPLL(pipe));
1585 }
1586
1587 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1588 {
1589         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1590         u32 val;
1591
1592         /* Make sure the pipe isn't still relying on us */
1593         assert_pipe_disabled(dev_priv, pipe);
1594
1595         val = DPLL_SSC_REF_CLK_CHV |
1596                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1597         if (pipe != PIPE_A)
1598                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1599
1600         I915_WRITE(DPLL(pipe), val);
1601         POSTING_READ(DPLL(pipe));
1602
1603         vlv_dpio_get(dev_priv);
1604
1605         /* Disable 10bit clock to display controller */
1606         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1607         val &= ~DPIO_DCLKP_EN;
1608         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1609
1610         vlv_dpio_put(dev_priv);
1611 }
1612
1613 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1614                          struct intel_digital_port *dport,
1615                          unsigned int expected_mask)
1616 {
1617         u32 port_mask;
1618         i915_reg_t dpll_reg;
1619
1620         switch (dport->base.port) {
1621         case PORT_B:
1622                 port_mask = DPLL_PORTB_READY_MASK;
1623                 dpll_reg = DPLL(0);
1624                 break;
1625         case PORT_C:
1626                 port_mask = DPLL_PORTC_READY_MASK;
1627                 dpll_reg = DPLL(0);
1628                 expected_mask <<= 4;
1629                 break;
1630         case PORT_D:
1631                 port_mask = DPLL_PORTD_READY_MASK;
1632                 dpll_reg = DPIO_PHY_STATUS;
1633                 break;
1634         default:
1635                 BUG();
1636         }
1637
1638         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1639                                        port_mask, expected_mask, 1000))
1640                 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1641                      dport->base.base.base.id, dport->base.base.name,
1642                      I915_READ(dpll_reg) & port_mask, expected_mask);
1643 }
1644
1645 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1646 {
1647         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1648         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1649         enum pipe pipe = crtc->pipe;
1650         i915_reg_t reg;
1651         u32 val, pipeconf_val;
1652
1653         /* Make sure PCH DPLL is enabled */
1654         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1655
1656         /* FDI must be feeding us bits for PCH ports */
1657         assert_fdi_tx_enabled(dev_priv, pipe);
1658         assert_fdi_rx_enabled(dev_priv, pipe);
1659
1660         if (HAS_PCH_CPT(dev_priv)) {
1661                 /* Workaround: Set the timing override bit before enabling the
1662                  * pch transcoder. */
1663                 reg = TRANS_CHICKEN2(pipe);
1664                 val = I915_READ(reg);
1665                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1666                 I915_WRITE(reg, val);
1667         }
1668
1669         reg = PCH_TRANSCONF(pipe);
1670         val = I915_READ(reg);
1671         pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673         if (HAS_PCH_IBX(dev_priv)) {
1674                 /*
1675                  * Make the BPC in transcoder be consistent with
1676                  * that in pipeconf reg. For HDMI we must use 8bpc
1677                  * here for both 8bpc and 12bpc.
1678                  */
1679                 val &= ~PIPECONF_BPC_MASK;
1680                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1681                         val |= PIPECONF_8BPC;
1682                 else
1683                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1684         }
1685
1686         val &= ~TRANS_INTERLACE_MASK;
1687         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1688                 if (HAS_PCH_IBX(dev_priv) &&
1689                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1690                         val |= TRANS_LEGACY_INTERLACED_ILK;
1691                 else
1692                         val |= TRANS_INTERLACED;
1693         } else {
1694                 val |= TRANS_PROGRESSIVE;
1695         }
1696
1697         I915_WRITE(reg, val | TRANS_ENABLE);
1698         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1699                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1700 }
1701
1702 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1703                                       enum transcoder cpu_transcoder)
1704 {
1705         u32 val, pipeconf_val;
1706
1707         /* FDI must be feeding us bits for PCH ports */
1708         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1709         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1710
1711         /* Workaround: set timing override bit. */
1712         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1713         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1714         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1715
1716         val = TRANS_ENABLE;
1717         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1718
1719         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1720             PIPECONF_INTERLACED_ILK)
1721                 val |= TRANS_INTERLACED;
1722         else
1723                 val |= TRANS_PROGRESSIVE;
1724
1725         I915_WRITE(LPT_TRANSCONF, val);
1726         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1727                                   TRANS_STATE_ENABLE, 100))
1728                 DRM_ERROR("Failed to enable PCH transcoder\n");
1729 }
1730
1731 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1732                                             enum pipe pipe)
1733 {
1734         i915_reg_t reg;
1735         u32 val;
1736
1737         /* FDI relies on the transcoder */
1738         assert_fdi_tx_disabled(dev_priv, pipe);
1739         assert_fdi_rx_disabled(dev_priv, pipe);
1740
1741         /* Ports must be off as well */
1742         assert_pch_ports_disabled(dev_priv, pipe);
1743
1744         reg = PCH_TRANSCONF(pipe);
1745         val = I915_READ(reg);
1746         val &= ~TRANS_ENABLE;
1747         I915_WRITE(reg, val);
1748         /* wait for PCH transcoder off, transcoder state */
1749         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1750                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1751
1752         if (HAS_PCH_CPT(dev_priv)) {
1753                 /* Workaround: Clear the timing override chicken bit again. */
1754                 reg = TRANS_CHICKEN2(pipe);
1755                 val = I915_READ(reg);
1756                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1757                 I915_WRITE(reg, val);
1758         }
1759 }
1760
1761 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1762 {
1763         u32 val;
1764
1765         val = I915_READ(LPT_TRANSCONF);
1766         val &= ~TRANS_ENABLE;
1767         I915_WRITE(LPT_TRANSCONF, val);
1768         /* wait for PCH transcoder off, transcoder state */
1769         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1770                                     TRANS_STATE_ENABLE, 50))
1771                 DRM_ERROR("Failed to disable PCH transcoder\n");
1772
1773         /* Workaround: clear timing override bit. */
1774         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1775         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1777 }
1778
1779 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1780 {
1781         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1782
1783         if (HAS_PCH_LPT(dev_priv))
1784                 return PIPE_A;
1785         else
1786                 return crtc->pipe;
1787 }
1788
1789 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1790 {
1791         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1792
1793         /*
1794          * On i965gm the hardware frame counter reads
1795          * zero when the TV encoder is enabled :(
1796          */
1797         if (IS_I965GM(dev_priv) &&
1798             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1799                 return 0;
1800
1801         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1802                 return 0xffffffff; /* full 32 bit counter */
1803         else if (INTEL_GEN(dev_priv) >= 3)
1804                 return 0xffffff; /* only 24 bits of frame count */
1805         else
1806                 return 0; /* Gen2 doesn't have a hardware frame counter */
1807 }
1808
1809 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1810 {
1811         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1812
1813         drm_crtc_set_max_vblank_count(&crtc->base,
1814                                       intel_crtc_max_vblank_count(crtc_state));
1815         drm_crtc_vblank_on(&crtc->base);
1816 }
1817
1818 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1819 {
1820         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1821         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1822         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1823         enum pipe pipe = crtc->pipe;
1824         i915_reg_t reg;
1825         u32 val;
1826
1827         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1828
1829         assert_planes_disabled(crtc);
1830
1831         /*
1832          * A pipe without a PLL won't actually be able to drive bits from
1833          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1834          * need the check.
1835          */
1836         if (HAS_GMCH(dev_priv)) {
1837                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1838                         assert_dsi_pll_enabled(dev_priv);
1839                 else
1840                         assert_pll_enabled(dev_priv, pipe);
1841         } else {
1842                 if (new_crtc_state->has_pch_encoder) {
1843                         /* if driving the PCH, we need FDI enabled */
1844                         assert_fdi_rx_pll_enabled(dev_priv,
1845                                                   intel_crtc_pch_transcoder(crtc));
1846                         assert_fdi_tx_pll_enabled(dev_priv,
1847                                                   (enum pipe) cpu_transcoder);
1848                 }
1849                 /* FIXME: assert CPU port conditions for SNB+ */
1850         }
1851
1852         trace_intel_pipe_enable(crtc);
1853
1854         reg = PIPECONF(cpu_transcoder);
1855         val = I915_READ(reg);
1856         if (val & PIPECONF_ENABLE) {
1857                 /* we keep both pipes enabled on 830 */
1858                 WARN_ON(!IS_I830(dev_priv));
1859                 return;
1860         }
1861
1862         I915_WRITE(reg, val | PIPECONF_ENABLE);
1863         POSTING_READ(reg);
1864
1865         /*
1866          * Until the pipe starts PIPEDSL reads will return a stale value,
1867          * which causes an apparent vblank timestamp jump when PIPEDSL
1868          * resets to its proper value. That also messes up the frame count
1869          * when it's derived from the timestamps. So let's wait for the
1870          * pipe to start properly before we call drm_crtc_vblank_on()
1871          */
1872         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1873                 intel_wait_for_pipe_scanline_moving(crtc);
1874 }
1875
1876 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1877 {
1878         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1879         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1880         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1881         enum pipe pipe = crtc->pipe;
1882         i915_reg_t reg;
1883         u32 val;
1884
1885         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1886
1887         /*
1888          * Make sure planes won't keep trying to pump pixels to us,
1889          * or we might hang the display.
1890          */
1891         assert_planes_disabled(crtc);
1892
1893         trace_intel_pipe_disable(crtc);
1894
1895         reg = PIPECONF(cpu_transcoder);
1896         val = I915_READ(reg);
1897         if ((val & PIPECONF_ENABLE) == 0)
1898                 return;
1899
1900         /*
1901          * Double wide has implications for planes
1902          * so best keep it disabled when not needed.
1903          */
1904         if (old_crtc_state->double_wide)
1905                 val &= ~PIPECONF_DOUBLE_WIDE;
1906
1907         /* Don't disable pipe or pipe PLLs if needed */
1908         if (!IS_I830(dev_priv))
1909                 val &= ~PIPECONF_ENABLE;
1910
1911         I915_WRITE(reg, val);
1912         if ((val & PIPECONF_ENABLE) == 0)
1913                 intel_wait_for_pipe_off(old_crtc_state);
1914 }
1915
1916 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1917 {
1918         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1919 }
1920
1921 static unsigned int
1922 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1923 {
1924         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1925         unsigned int cpp = fb->format->cpp[color_plane];
1926
1927         switch (fb->modifier) {
1928         case DRM_FORMAT_MOD_LINEAR:
1929                 return intel_tile_size(dev_priv);
1930         case I915_FORMAT_MOD_X_TILED:
1931                 if (IS_GEN(dev_priv, 2))
1932                         return 128;
1933                 else
1934                         return 512;
1935         case I915_FORMAT_MOD_Y_TILED_CCS:
1936                 if (color_plane == 1)
1937                         return 128;
1938                 /* fall through */
1939         case I915_FORMAT_MOD_Y_TILED:
1940                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1941                         return 128;
1942                 else
1943                         return 512;
1944         case I915_FORMAT_MOD_Yf_TILED_CCS:
1945                 if (color_plane == 1)
1946                         return 128;
1947                 /* fall through */
1948         case I915_FORMAT_MOD_Yf_TILED:
1949                 switch (cpp) {
1950                 case 1:
1951                         return 64;
1952                 case 2:
1953                 case 4:
1954                         return 128;
1955                 case 8:
1956                 case 16:
1957                         return 256;
1958                 default:
1959                         MISSING_CASE(cpp);
1960                         return cpp;
1961                 }
1962                 break;
1963         default:
1964                 MISSING_CASE(fb->modifier);
1965                 return cpp;
1966         }
1967 }
1968
1969 static unsigned int
1970 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1971 {
1972         return intel_tile_size(to_i915(fb->dev)) /
1973                 intel_tile_width_bytes(fb, color_plane);
1974 }
1975
1976 /* Return the tile dimensions in pixel units */
1977 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1978                             unsigned int *tile_width,
1979                             unsigned int *tile_height)
1980 {
1981         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1982         unsigned int cpp = fb->format->cpp[color_plane];
1983
1984         *tile_width = tile_width_bytes / cpp;
1985         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1986 }
1987
1988 unsigned int
1989 intel_fb_align_height(const struct drm_framebuffer *fb,
1990                       int color_plane, unsigned int height)
1991 {
1992         unsigned int tile_height = intel_tile_height(fb, color_plane);
1993
1994         return ALIGN(height, tile_height);
1995 }
1996
1997 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1998 {
1999         unsigned int size = 0;
2000         int i;
2001
2002         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2003                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2004
2005         return size;
2006 }
2007
2008 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2009 {
2010         unsigned int size = 0;
2011         int i;
2012
2013         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2014                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2015
2016         return size;
2017 }
2018
2019 static void
2020 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2021                         const struct drm_framebuffer *fb,
2022                         unsigned int rotation)
2023 {
2024         view->type = I915_GGTT_VIEW_NORMAL;
2025         if (drm_rotation_90_or_270(rotation)) {
2026                 view->type = I915_GGTT_VIEW_ROTATED;
2027                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2028         }
2029 }
2030
2031 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2032 {
2033         if (IS_I830(dev_priv))
2034                 return 16 * 1024;
2035         else if (IS_I85X(dev_priv))
2036                 return 256;
2037         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2038                 return 32;
2039         else
2040                 return 4 * 1024;
2041 }
2042
2043 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2044 {
2045         if (INTEL_GEN(dev_priv) >= 9)
2046                 return 256 * 1024;
2047         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2048                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2049                 return 128 * 1024;
2050         else if (INTEL_GEN(dev_priv) >= 4)
2051                 return 4 * 1024;
2052         else
2053                 return 0;
2054 }
2055
2056 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2057                                          int color_plane)
2058 {
2059         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2060
2061         /* AUX_DIST needs only 4K alignment */
2062         if (color_plane == 1)
2063                 return 4096;
2064
2065         switch (fb->modifier) {
2066         case DRM_FORMAT_MOD_LINEAR:
2067                 return intel_linear_alignment(dev_priv);
2068         case I915_FORMAT_MOD_X_TILED:
2069                 if (INTEL_GEN(dev_priv) >= 9)
2070                         return 256 * 1024;
2071                 return 0;
2072         case I915_FORMAT_MOD_Y_TILED_CCS:
2073         case I915_FORMAT_MOD_Yf_TILED_CCS:
2074         case I915_FORMAT_MOD_Y_TILED:
2075         case I915_FORMAT_MOD_Yf_TILED:
2076                 return 1 * 1024 * 1024;
2077         default:
2078                 MISSING_CASE(fb->modifier);
2079                 return 0;
2080         }
2081 }
2082
2083 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2084 {
2085         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2086         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2087
2088         return INTEL_GEN(dev_priv) < 4 ||
2089                 (plane->has_fbc &&
2090                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2091 }
2092
2093 struct i915_vma *
2094 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2095                            const struct i915_ggtt_view *view,
2096                            bool uses_fence,
2097                            unsigned long *out_flags)
2098 {
2099         struct drm_device *dev = fb->dev;
2100         struct drm_i915_private *dev_priv = to_i915(dev);
2101         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2102         intel_wakeref_t wakeref;
2103         struct i915_vma *vma;
2104         unsigned int pinctl;
2105         u32 alignment;
2106
2107         if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2108                 return ERR_PTR(-EINVAL);
2109
2110         alignment = intel_surf_alignment(fb, 0);
2111
2112         /* Note that the w/a also requires 64 PTE of padding following the
2113          * bo. We currently fill all unused PTE with the shadow page and so
2114          * we should always have valid PTE following the scanout preventing
2115          * the VT-d warning.
2116          */
2117         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2118                 alignment = 256 * 1024;
2119
2120         /*
2121          * Global gtt pte registers are special registers which actually forward
2122          * writes to a chunk of system memory. Which means that there is no risk
2123          * that the register values disappear as soon as we call
2124          * intel_runtime_pm_put(), so it is correct to wrap only the
2125          * pin/unpin/fence and not more.
2126          */
2127         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2128         i915_gem_object_lock(obj);
2129
2130         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2131
2132         pinctl = 0;
2133
2134         /* Valleyview is definitely limited to scanning out the first
2135          * 512MiB. Lets presume this behaviour was inherited from the
2136          * g4x display engine and that all earlier gen are similarly
2137          * limited. Testing suggests that it is a little more
2138          * complicated than this. For example, Cherryview appears quite
2139          * happy to scanout from anywhere within its global aperture.
2140          */
2141         if (HAS_GMCH(dev_priv))
2142                 pinctl |= PIN_MAPPABLE;
2143
2144         vma = i915_gem_object_pin_to_display_plane(obj,
2145                                                    alignment, view, pinctl);
2146         if (IS_ERR(vma))
2147                 goto err;
2148
2149         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2150                 int ret;
2151
2152                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2153                  * fence, whereas 965+ only requires a fence if using
2154                  * framebuffer compression.  For simplicity, we always, when
2155                  * possible, install a fence as the cost is not that onerous.
2156                  *
2157                  * If we fail to fence the tiled scanout, then either the
2158                  * modeset will reject the change (which is highly unlikely as
2159                  * the affected systems, all but one, do not have unmappable
2160                  * space) or we will not be able to enable full powersaving
2161                  * techniques (also likely not to apply due to various limits
2162                  * FBC and the like impose on the size of the buffer, which
2163                  * presumably we violated anyway with this unmappable buffer).
2164                  * Anyway, it is presumably better to stumble onwards with
2165                  * something and try to run the system in a "less than optimal"
2166                  * mode that matches the user configuration.
2167                  */
2168                 ret = i915_vma_pin_fence(vma);
2169                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2170                         i915_gem_object_unpin_from_display_plane(vma);
2171                         vma = ERR_PTR(ret);
2172                         goto err;
2173                 }
2174
2175                 if (ret == 0 && vma->fence)
2176                         *out_flags |= PLANE_HAS_FENCE;
2177         }
2178
2179         i915_vma_get(vma);
2180 err:
2181         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2182
2183         i915_gem_object_unlock(obj);
2184         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2185         return vma;
2186 }
2187
2188 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2189 {
2190         i915_gem_object_lock(vma->obj);
2191         if (flags & PLANE_HAS_FENCE)
2192                 i915_vma_unpin_fence(vma);
2193         i915_gem_object_unpin_from_display_plane(vma);
2194         i915_gem_object_unlock(vma->obj);
2195
2196         i915_vma_put(vma);
2197 }
2198
2199 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2200                           unsigned int rotation)
2201 {
2202         if (drm_rotation_90_or_270(rotation))
2203                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2204         else
2205                 return fb->pitches[color_plane];
2206 }
2207
2208 /*
2209  * Convert the x/y offsets into a linear offset.
2210  * Only valid with 0/180 degree rotation, which is fine since linear
2211  * offset is only used with linear buffers on pre-hsw and tiled buffers
2212  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2213  */
2214 u32 intel_fb_xy_to_linear(int x, int y,
2215                           const struct intel_plane_state *state,
2216                           int color_plane)
2217 {
2218         const struct drm_framebuffer *fb = state->hw.fb;
2219         unsigned int cpp = fb->format->cpp[color_plane];
2220         unsigned int pitch = state->color_plane[color_plane].stride;
2221
2222         return y * pitch + x * cpp;
2223 }
2224
2225 /*
2226  * Add the x/y offsets derived from fb->offsets[] to the user
2227  * specified plane src x/y offsets. The resulting x/y offsets
2228  * specify the start of scanout from the beginning of the gtt mapping.
2229  */
2230 void intel_add_fb_offsets(int *x, int *y,
2231                           const struct intel_plane_state *state,
2232                           int color_plane)
2233
2234 {
2235         *x += state->color_plane[color_plane].x;
2236         *y += state->color_plane[color_plane].y;
2237 }
2238
2239 static u32 intel_adjust_tile_offset(int *x, int *y,
2240                                     unsigned int tile_width,
2241                                     unsigned int tile_height,
2242                                     unsigned int tile_size,
2243                                     unsigned int pitch_tiles,
2244                                     u32 old_offset,
2245                                     u32 new_offset)
2246 {
2247         unsigned int pitch_pixels = pitch_tiles * tile_width;
2248         unsigned int tiles;
2249
2250         WARN_ON(old_offset & (tile_size - 1));
2251         WARN_ON(new_offset & (tile_size - 1));
2252         WARN_ON(new_offset > old_offset);
2253
2254         tiles = (old_offset - new_offset) / tile_size;
2255
2256         *y += tiles / pitch_tiles * tile_height;
2257         *x += tiles % pitch_tiles * tile_width;
2258
2259         /* minimize x in case it got needlessly big */
2260         *y += *x / pitch_pixels * tile_height;
2261         *x %= pitch_pixels;
2262
2263         return new_offset;
2264 }
2265
2266 static bool is_surface_linear(u64 modifier, int color_plane)
2267 {
2268         return modifier == DRM_FORMAT_MOD_LINEAR;
2269 }
2270
2271 static u32 intel_adjust_aligned_offset(int *x, int *y,
2272                                        const struct drm_framebuffer *fb,
2273                                        int color_plane,
2274                                        unsigned int rotation,
2275                                        unsigned int pitch,
2276                                        u32 old_offset, u32 new_offset)
2277 {
2278         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2279         unsigned int cpp = fb->format->cpp[color_plane];
2280
2281         WARN_ON(new_offset > old_offset);
2282
2283         if (!is_surface_linear(fb->modifier, color_plane)) {
2284                 unsigned int tile_size, tile_width, tile_height;
2285                 unsigned int pitch_tiles;
2286
2287                 tile_size = intel_tile_size(dev_priv);
2288                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2289
2290                 if (drm_rotation_90_or_270(rotation)) {
2291                         pitch_tiles = pitch / tile_height;
2292                         swap(tile_width, tile_height);
2293                 } else {
2294                         pitch_tiles = pitch / (tile_width * cpp);
2295                 }
2296
2297                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2298                                          tile_size, pitch_tiles,
2299                                          old_offset, new_offset);
2300         } else {
2301                 old_offset += *y * pitch + *x * cpp;
2302
2303                 *y = (old_offset - new_offset) / pitch;
2304                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2305         }
2306
2307         return new_offset;
2308 }
2309
2310 /*
2311  * Adjust the tile offset by moving the difference into
2312  * the x/y offsets.
2313  */
2314 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2315                                              const struct intel_plane_state *state,
2316                                              int color_plane,
2317                                              u32 old_offset, u32 new_offset)
2318 {
2319         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2320                                            state->hw.rotation,
2321                                            state->color_plane[color_plane].stride,
2322                                            old_offset, new_offset);
2323 }
2324
2325 /*
2326  * Computes the aligned offset to the base tile and adjusts
2327  * x, y. bytes per pixel is assumed to be a power-of-two.
2328  *
2329  * In the 90/270 rotated case, x and y are assumed
2330  * to be already rotated to match the rotated GTT view, and
2331  * pitch is the tile_height aligned framebuffer height.
2332  *
2333  * This function is used when computing the derived information
2334  * under intel_framebuffer, so using any of that information
2335  * here is not allowed. Anything under drm_framebuffer can be
2336  * used. This is why the user has to pass in the pitch since it
2337  * is specified in the rotated orientation.
2338  */
2339 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2340                                         int *x, int *y,
2341                                         const struct drm_framebuffer *fb,
2342                                         int color_plane,
2343                                         unsigned int pitch,
2344                                         unsigned int rotation,
2345                                         u32 alignment)
2346 {
2347         unsigned int cpp = fb->format->cpp[color_plane];
2348         u32 offset, offset_aligned;
2349
2350         if (alignment)
2351                 alignment--;
2352
2353         if (!is_surface_linear(fb->modifier, color_plane)) {
2354                 unsigned int tile_size, tile_width, tile_height;
2355                 unsigned int tile_rows, tiles, pitch_tiles;
2356
2357                 tile_size = intel_tile_size(dev_priv);
2358                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2359
2360                 if (drm_rotation_90_or_270(rotation)) {
2361                         pitch_tiles = pitch / tile_height;
2362                         swap(tile_width, tile_height);
2363                 } else {
2364                         pitch_tiles = pitch / (tile_width * cpp);
2365                 }
2366
2367                 tile_rows = *y / tile_height;
2368                 *y %= tile_height;
2369
2370                 tiles = *x / tile_width;
2371                 *x %= tile_width;
2372
2373                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2374                 offset_aligned = offset & ~alignment;
2375
2376                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2377                                          tile_size, pitch_tiles,
2378                                          offset, offset_aligned);
2379         } else {
2380                 offset = *y * pitch + *x * cpp;
2381                 offset_aligned = offset & ~alignment;
2382
2383                 *y = (offset & alignment) / pitch;
2384                 *x = ((offset & alignment) - *y * pitch) / cpp;
2385         }
2386
2387         return offset_aligned;
2388 }
2389
2390 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2391                                               const struct intel_plane_state *state,
2392                                               int color_plane)
2393 {
2394         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2395         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2396         const struct drm_framebuffer *fb = state->hw.fb;
2397         unsigned int rotation = state->hw.rotation;
2398         int pitch = state->color_plane[color_plane].stride;
2399         u32 alignment;
2400
2401         if (intel_plane->id == PLANE_CURSOR)
2402                 alignment = intel_cursor_alignment(dev_priv);
2403         else
2404                 alignment = intel_surf_alignment(fb, color_plane);
2405
2406         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2407                                             pitch, rotation, alignment);
2408 }
2409
2410 /* Convert the fb->offset[] into x/y offsets */
2411 static int intel_fb_offset_to_xy(int *x, int *y,
2412                                  const struct drm_framebuffer *fb,
2413                                  int color_plane)
2414 {
2415         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2416         unsigned int height;
2417
2418         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2419             fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2420                 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2421                               fb->offsets[color_plane], color_plane);
2422                 return -EINVAL;
2423         }
2424
2425         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2426         height = ALIGN(height, intel_tile_height(fb, color_plane));
2427
2428         /* Catch potential overflows early */
2429         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2430                             fb->offsets[color_plane])) {
2431                 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2432                               fb->offsets[color_plane], fb->pitches[color_plane],
2433                               color_plane);
2434                 return -ERANGE;
2435         }
2436
2437         *x = 0;
2438         *y = 0;
2439
2440         intel_adjust_aligned_offset(x, y,
2441                                     fb, color_plane, DRM_MODE_ROTATE_0,
2442                                     fb->pitches[color_plane],
2443                                     fb->offsets[color_plane], 0);
2444
2445         return 0;
2446 }
2447
2448 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2449 {
2450         switch (fb_modifier) {
2451         case I915_FORMAT_MOD_X_TILED:
2452                 return I915_TILING_X;
2453         case I915_FORMAT_MOD_Y_TILED:
2454         case I915_FORMAT_MOD_Y_TILED_CCS:
2455                 return I915_TILING_Y;
2456         default:
2457                 return I915_TILING_NONE;
2458         }
2459 }
2460
2461 /*
2462  * From the Sky Lake PRM:
2463  * "The Color Control Surface (CCS) contains the compression status of
2464  *  the cache-line pairs. The compression state of the cache-line pair
2465  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2466  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2467  *  cache-line-pairs. CCS is always Y tiled."
2468  *
2469  * Since cache line pairs refers to horizontally adjacent cache lines,
2470  * each cache line in the CCS corresponds to an area of 32x16 cache
2471  * lines on the main surface. Since each pixel is 4 bytes, this gives
2472  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2473  * main surface.
2474  */
2475 static const struct drm_format_info ccs_formats[] = {
2476         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2477           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2478         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2479           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2480         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2481           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2482         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2483           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2484 };
2485
2486 static const struct drm_format_info *
2487 lookup_format_info(const struct drm_format_info formats[],
2488                    int num_formats, u32 format)
2489 {
2490         int i;
2491
2492         for (i = 0; i < num_formats; i++) {
2493                 if (formats[i].format == format)
2494                         return &formats[i];
2495         }
2496
2497         return NULL;
2498 }
2499
2500 static const struct drm_format_info *
2501 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2502 {
2503         switch (cmd->modifier[0]) {
2504         case I915_FORMAT_MOD_Y_TILED_CCS:
2505         case I915_FORMAT_MOD_Yf_TILED_CCS:
2506                 return lookup_format_info(ccs_formats,
2507                                           ARRAY_SIZE(ccs_formats),
2508                                           cmd->pixel_format);
2509         default:
2510                 return NULL;
2511         }
2512 }
2513
2514 bool is_ccs_modifier(u64 modifier)
2515 {
2516         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2517                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2518 }
2519
2520 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2521                               u32 pixel_format, u64 modifier)
2522 {
2523         struct intel_crtc *crtc;
2524         struct intel_plane *plane;
2525
2526         /*
2527          * We assume the primary plane for pipe A has
2528          * the highest stride limits of them all.
2529          */
2530         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2531         plane = to_intel_plane(crtc->base.primary);
2532
2533         return plane->max_stride(plane, pixel_format, modifier,
2534                                  DRM_MODE_ROTATE_0);
2535 }
2536
2537 static
2538 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2539                         u32 pixel_format, u64 modifier)
2540 {
2541         /*
2542          * Arbitrary limit for gen4+ chosen to match the
2543          * render engine max stride.
2544          *
2545          * The new CCS hash mode makes remapping impossible
2546          */
2547         if (!is_ccs_modifier(modifier)) {
2548                 if (INTEL_GEN(dev_priv) >= 7)
2549                         return 256*1024;
2550                 else if (INTEL_GEN(dev_priv) >= 4)
2551                         return 128*1024;
2552         }
2553
2554         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2555 }
2556
2557 static u32
2558 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2559 {
2560         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2561
2562         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2563                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2564                                                            fb->format->format,
2565                                                            fb->modifier);
2566
2567                 /*
2568                  * To make remapping with linear generally feasible
2569                  * we need the stride to be page aligned.
2570                  */
2571                 if (fb->pitches[color_plane] > max_stride)
2572                         return intel_tile_size(dev_priv);
2573                 else
2574                         return 64;
2575         } else {
2576                 return intel_tile_width_bytes(fb, color_plane);
2577         }
2578 }
2579
2580 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2581 {
2582         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2583         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2584         const struct drm_framebuffer *fb = plane_state->hw.fb;
2585         int i;
2586
2587         /* We don't want to deal with remapping with cursors */
2588         if (plane->id == PLANE_CURSOR)
2589                 return false;
2590
2591         /*
2592          * The display engine limits already match/exceed the
2593          * render engine limits, so not much point in remapping.
2594          * Would also need to deal with the fence POT alignment
2595          * and gen2 2KiB GTT tile size.
2596          */
2597         if (INTEL_GEN(dev_priv) < 4)
2598                 return false;
2599
2600         /*
2601          * The new CCS hash mode isn't compatible with remapping as
2602          * the virtual address of the pages affects the compressed data.
2603          */
2604         if (is_ccs_modifier(fb->modifier))
2605                 return false;
2606
2607         /* Linear needs a page aligned stride for remapping */
2608         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2609                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2610
2611                 for (i = 0; i < fb->format->num_planes; i++) {
2612                         if (fb->pitches[i] & alignment)
2613                                 return false;
2614                 }
2615         }
2616
2617         return true;
2618 }
2619
2620 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2621 {
2622         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2623         const struct drm_framebuffer *fb = plane_state->hw.fb;
2624         unsigned int rotation = plane_state->hw.rotation;
2625         u32 stride, max_stride;
2626
2627         /*
2628          * No remapping for invisible planes since we don't have
2629          * an actual source viewport to remap.
2630          */
2631         if (!plane_state->uapi.visible)
2632                 return false;
2633
2634         if (!intel_plane_can_remap(plane_state))
2635                 return false;
2636
2637         /*
2638          * FIXME: aux plane limits on gen9+ are
2639          * unclear in Bspec, for now no checking.
2640          */
2641         stride = intel_fb_pitch(fb, 0, rotation);
2642         max_stride = plane->max_stride(plane, fb->format->format,
2643                                        fb->modifier, rotation);
2644
2645         return stride > max_stride;
2646 }
2647
2648 static int
2649 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2650                    struct drm_framebuffer *fb)
2651 {
2652         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2653         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2654         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2655         u32 gtt_offset_rotated = 0;
2656         unsigned int max_size = 0;
2657         int i, num_planes = fb->format->num_planes;
2658         unsigned int tile_size = intel_tile_size(dev_priv);
2659
2660         for (i = 0; i < num_planes; i++) {
2661                 unsigned int width, height;
2662                 unsigned int cpp, size;
2663                 u32 offset;
2664                 int x, y;
2665                 int ret;
2666
2667                 cpp = fb->format->cpp[i];
2668                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2669                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2670
2671                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2672                 if (ret) {
2673                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2674                                       i, fb->offsets[i]);
2675                         return ret;
2676                 }
2677
2678                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2679                         int hsub = fb->format->hsub;
2680                         int vsub = fb->format->vsub;
2681                         int tile_width, tile_height;
2682                         int main_x, main_y;
2683                         int ccs_x, ccs_y;
2684
2685                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2686                         tile_width *= hsub;
2687                         tile_height *= vsub;
2688
2689                         ccs_x = (x * hsub) % tile_width;
2690                         ccs_y = (y * vsub) % tile_height;
2691                         main_x = intel_fb->normal[0].x % tile_width;
2692                         main_y = intel_fb->normal[0].y % tile_height;
2693
2694                         /*
2695                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2696                          * x/y offsets must match between CCS and the main surface.
2697                          */
2698                         if (main_x != ccs_x || main_y != ccs_y) {
2699                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2700                                               main_x, main_y,
2701                                               ccs_x, ccs_y,
2702                                               intel_fb->normal[0].x,
2703                                               intel_fb->normal[0].y,
2704                                               x, y);
2705                                 return -EINVAL;
2706                         }
2707                 }
2708
2709                 /*
2710                  * The fence (if used) is aligned to the start of the object
2711                  * so having the framebuffer wrap around across the edge of the
2712                  * fenced region doesn't really work. We have no API to configure
2713                  * the fence start offset within the object (nor could we probably
2714                  * on gen2/3). So it's just easier if we just require that the
2715                  * fb layout agrees with the fence layout. We already check that the
2716                  * fb stride matches the fence stride elsewhere.
2717                  */
2718                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2719                     (x + width) * cpp > fb->pitches[i]) {
2720                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2721                                       i, fb->offsets[i]);
2722                         return -EINVAL;
2723                 }
2724
2725                 /*
2726                  * First pixel of the framebuffer from
2727                  * the start of the normal gtt mapping.
2728                  */
2729                 intel_fb->normal[i].x = x;
2730                 intel_fb->normal[i].y = y;
2731
2732                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2733                                                       fb->pitches[i],
2734                                                       DRM_MODE_ROTATE_0,
2735                                                       tile_size);
2736                 offset /= tile_size;
2737
2738                 if (!is_surface_linear(fb->modifier, i)) {
2739                         unsigned int tile_width, tile_height;
2740                         unsigned int pitch_tiles;
2741                         struct drm_rect r;
2742
2743                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2744
2745                         rot_info->plane[i].offset = offset;
2746                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2747                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2748                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2749
2750                         intel_fb->rotated[i].pitch =
2751                                 rot_info->plane[i].height * tile_height;
2752
2753                         /* how many tiles does this plane need */
2754                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2755                         /*
2756                          * If the plane isn't horizontally tile aligned,
2757                          * we need one more tile.
2758                          */
2759                         if (x != 0)
2760                                 size++;
2761
2762                         /* rotate the x/y offsets to match the GTT view */
2763                         drm_rect_init(&r, x, y, width, height);
2764                         drm_rect_rotate(&r,
2765                                         rot_info->plane[i].width * tile_width,
2766                                         rot_info->plane[i].height * tile_height,
2767                                         DRM_MODE_ROTATE_270);
2768                         x = r.x1;
2769                         y = r.y1;
2770
2771                         /* rotate the tile dimensions to match the GTT view */
2772                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2773                         swap(tile_width, tile_height);
2774
2775                         /*
2776                          * We only keep the x/y offsets, so push all of the
2777                          * gtt offset into the x/y offsets.
2778                          */
2779                         intel_adjust_tile_offset(&x, &y,
2780                                                  tile_width, tile_height,
2781                                                  tile_size, pitch_tiles,
2782                                                  gtt_offset_rotated * tile_size, 0);
2783
2784                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2785
2786                         /*
2787                          * First pixel of the framebuffer from
2788                          * the start of the rotated gtt mapping.
2789                          */
2790                         intel_fb->rotated[i].x = x;
2791                         intel_fb->rotated[i].y = y;
2792                 } else {
2793                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2794                                             x * cpp, tile_size);
2795                 }
2796
2797                 /* how many tiles in total needed in the bo */
2798                 max_size = max(max_size, offset + size);
2799         }
2800
2801         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2802                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2803                               mul_u32_u32(max_size, tile_size), obj->base.size);
2804                 return -EINVAL;
2805         }
2806
2807         return 0;
2808 }
2809
2810 static void
2811 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2812 {
2813         struct drm_i915_private *dev_priv =
2814                 to_i915(plane_state->uapi.plane->dev);
2815         struct drm_framebuffer *fb = plane_state->hw.fb;
2816         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2817         struct intel_rotation_info *info = &plane_state->view.rotated;
2818         unsigned int rotation = plane_state->hw.rotation;
2819         int i, num_planes = fb->format->num_planes;
2820         unsigned int tile_size = intel_tile_size(dev_priv);
2821         unsigned int src_x, src_y;
2822         unsigned int src_w, src_h;
2823         u32 gtt_offset = 0;
2824
2825         memset(&plane_state->view, 0, sizeof(plane_state->view));
2826         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2827                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2828
2829         src_x = plane_state->uapi.src.x1 >> 16;
2830         src_y = plane_state->uapi.src.y1 >> 16;
2831         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2832         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2833
2834         WARN_ON(is_ccs_modifier(fb->modifier));
2835
2836         /* Make src coordinates relative to the viewport */
2837         drm_rect_translate(&plane_state->uapi.src,
2838                            -(src_x << 16), -(src_y << 16));
2839
2840         /* Rotate src coordinates to match rotated GTT view */
2841         if (drm_rotation_90_or_270(rotation))
2842                 drm_rect_rotate(&plane_state->uapi.src,
2843                                 src_w << 16, src_h << 16,
2844                                 DRM_MODE_ROTATE_270);
2845
2846         for (i = 0; i < num_planes; i++) {
2847                 unsigned int hsub = i ? fb->format->hsub : 1;
2848                 unsigned int vsub = i ? fb->format->vsub : 1;
2849                 unsigned int cpp = fb->format->cpp[i];
2850                 unsigned int tile_width, tile_height;
2851                 unsigned int width, height;
2852                 unsigned int pitch_tiles;
2853                 unsigned int x, y;
2854                 u32 offset;
2855
2856                 intel_tile_dims(fb, i, &tile_width, &tile_height);
2857
2858                 x = src_x / hsub;
2859                 y = src_y / vsub;
2860                 width = src_w / hsub;
2861                 height = src_h / vsub;
2862
2863                 /*
2864                  * First pixel of the src viewport from the
2865                  * start of the normal gtt mapping.
2866                  */
2867                 x += intel_fb->normal[i].x;
2868                 y += intel_fb->normal[i].y;
2869
2870                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2871                                                       fb, i, fb->pitches[i],
2872                                                       DRM_MODE_ROTATE_0, tile_size);
2873                 offset /= tile_size;
2874
2875                 info->plane[i].offset = offset;
2876                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2877                                                      tile_width * cpp);
2878                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2879                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2880
2881                 if (drm_rotation_90_or_270(rotation)) {
2882                         struct drm_rect r;
2883
2884                         /* rotate the x/y offsets to match the GTT view */
2885                         drm_rect_init(&r, x, y, width, height);
2886                         drm_rect_rotate(&r,
2887                                         info->plane[i].width * tile_width,
2888                                         info->plane[i].height * tile_height,
2889                                         DRM_MODE_ROTATE_270);
2890                         x = r.x1;
2891                         y = r.y1;
2892
2893                         pitch_tiles = info->plane[i].height;
2894                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2895
2896                         /* rotate the tile dimensions to match the GTT view */
2897                         swap(tile_width, tile_height);
2898                 } else {
2899                         pitch_tiles = info->plane[i].width;
2900                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2901                 }
2902
2903                 /*
2904                  * We only keep the x/y offsets, so push all of the
2905                  * gtt offset into the x/y offsets.
2906                  */
2907                 intel_adjust_tile_offset(&x, &y,
2908                                          tile_width, tile_height,
2909                                          tile_size, pitch_tiles,
2910                                          gtt_offset * tile_size, 0);
2911
2912                 gtt_offset += info->plane[i].width * info->plane[i].height;
2913
2914                 plane_state->color_plane[i].offset = 0;
2915                 plane_state->color_plane[i].x = x;
2916                 plane_state->color_plane[i].y = y;
2917         }
2918 }
2919
2920 static int
2921 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2922 {
2923         const struct intel_framebuffer *fb =
2924                 to_intel_framebuffer(plane_state->hw.fb);
2925         unsigned int rotation = plane_state->hw.rotation;
2926         int i, num_planes;
2927
2928         if (!fb)
2929                 return 0;
2930
2931         num_planes = fb->base.format->num_planes;
2932
2933         if (intel_plane_needs_remap(plane_state)) {
2934                 intel_plane_remap_gtt(plane_state);
2935
2936                 /*
2937                  * Sometimes even remapping can't overcome
2938                  * the stride limitations :( Can happen with
2939                  * big plane sizes and suitably misaligned
2940                  * offsets.
2941                  */
2942                 return intel_plane_check_stride(plane_state);
2943         }
2944
2945         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2946
2947         for (i = 0; i < num_planes; i++) {
2948                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2949                 plane_state->color_plane[i].offset = 0;
2950
2951                 if (drm_rotation_90_or_270(rotation)) {
2952                         plane_state->color_plane[i].x = fb->rotated[i].x;
2953                         plane_state->color_plane[i].y = fb->rotated[i].y;
2954                 } else {
2955                         plane_state->color_plane[i].x = fb->normal[i].x;
2956                         plane_state->color_plane[i].y = fb->normal[i].y;
2957                 }
2958         }
2959
2960         /* Rotate src coordinates to match rotated GTT view */
2961         if (drm_rotation_90_or_270(rotation))
2962                 drm_rect_rotate(&plane_state->uapi.src,
2963                                 fb->base.width << 16, fb->base.height << 16,
2964                                 DRM_MODE_ROTATE_270);
2965
2966         return intel_plane_check_stride(plane_state);
2967 }
2968
2969 static int i9xx_format_to_fourcc(int format)
2970 {
2971         switch (format) {
2972         case DISPPLANE_8BPP:
2973                 return DRM_FORMAT_C8;
2974         case DISPPLANE_BGRX555:
2975                 return DRM_FORMAT_XRGB1555;
2976         case DISPPLANE_BGRX565:
2977                 return DRM_FORMAT_RGB565;
2978         default:
2979         case DISPPLANE_BGRX888:
2980                 return DRM_FORMAT_XRGB8888;
2981         case DISPPLANE_RGBX888:
2982                 return DRM_FORMAT_XBGR8888;
2983         case DISPPLANE_BGRX101010:
2984                 return DRM_FORMAT_XRGB2101010;
2985         case DISPPLANE_RGBX101010:
2986                 return DRM_FORMAT_XBGR2101010;
2987         case DISPPLANE_RGBX161616:
2988                 return DRM_FORMAT_XBGR16161616F;
2989         }
2990 }
2991
2992 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2993 {
2994         switch (format) {
2995         case PLANE_CTL_FORMAT_RGB_565:
2996                 return DRM_FORMAT_RGB565;
2997         case PLANE_CTL_FORMAT_NV12:
2998                 return DRM_FORMAT_NV12;
2999         case PLANE_CTL_FORMAT_P010:
3000                 return DRM_FORMAT_P010;
3001         case PLANE_CTL_FORMAT_P012:
3002                 return DRM_FORMAT_P012;
3003         case PLANE_CTL_FORMAT_P016:
3004                 return DRM_FORMAT_P016;
3005         case PLANE_CTL_FORMAT_Y210:
3006                 return DRM_FORMAT_Y210;
3007         case PLANE_CTL_FORMAT_Y212:
3008                 return DRM_FORMAT_Y212;
3009         case PLANE_CTL_FORMAT_Y216:
3010                 return DRM_FORMAT_Y216;
3011         case PLANE_CTL_FORMAT_Y410:
3012                 return DRM_FORMAT_XVYU2101010;
3013         case PLANE_CTL_FORMAT_Y412:
3014                 return DRM_FORMAT_XVYU12_16161616;
3015         case PLANE_CTL_FORMAT_Y416:
3016                 return DRM_FORMAT_XVYU16161616;
3017         default:
3018         case PLANE_CTL_FORMAT_XRGB_8888:
3019                 if (rgb_order) {
3020                         if (alpha)
3021                                 return DRM_FORMAT_ABGR8888;
3022                         else
3023                                 return DRM_FORMAT_XBGR8888;
3024                 } else {
3025                         if (alpha)
3026                                 return DRM_FORMAT_ARGB8888;
3027                         else
3028                                 return DRM_FORMAT_XRGB8888;
3029                 }
3030         case PLANE_CTL_FORMAT_XRGB_2101010:
3031                 if (rgb_order)
3032                         return DRM_FORMAT_XBGR2101010;
3033                 else
3034                         return DRM_FORMAT_XRGB2101010;
3035         case PLANE_CTL_FORMAT_XRGB_16161616F:
3036                 if (rgb_order) {
3037                         if (alpha)
3038                                 return DRM_FORMAT_ABGR16161616F;
3039                         else
3040                                 return DRM_FORMAT_XBGR16161616F;
3041                 } else {
3042                         if (alpha)
3043                                 return DRM_FORMAT_ARGB16161616F;
3044                         else
3045                                 return DRM_FORMAT_XRGB16161616F;
3046                 }
3047         }
3048 }
3049
3050 static bool
3051 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3052                               struct intel_initial_plane_config *plane_config)
3053 {
3054         struct drm_device *dev = crtc->base.dev;
3055         struct drm_i915_private *dev_priv = to_i915(dev);
3056         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3057         struct drm_framebuffer *fb = &plane_config->fb->base;
3058         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3059         u32 size_aligned = round_up(plane_config->base + plane_config->size,
3060                                     PAGE_SIZE);
3061         struct drm_i915_gem_object *obj;
3062         bool ret = false;
3063
3064         size_aligned -= base_aligned;
3065
3066         if (plane_config->size == 0)
3067                 return false;
3068
3069         /* If the FB is too big, just don't use it since fbdev is not very
3070          * important and we should probably use that space with FBC or other
3071          * features. */
3072         if (size_aligned * 2 > dev_priv->stolen_usable_size)
3073                 return false;
3074
3075         switch (fb->modifier) {
3076         case DRM_FORMAT_MOD_LINEAR:
3077         case I915_FORMAT_MOD_X_TILED:
3078         case I915_FORMAT_MOD_Y_TILED:
3079                 break;
3080         default:
3081                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3082                                  fb->modifier);
3083                 return false;
3084         }
3085
3086         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3087                                                              base_aligned,
3088                                                              base_aligned,
3089                                                              size_aligned);
3090         if (IS_ERR(obj))
3091                 return false;
3092
3093         switch (plane_config->tiling) {
3094         case I915_TILING_NONE:
3095                 break;
3096         case I915_TILING_X:
3097         case I915_TILING_Y:
3098                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3099                 break;
3100         default:
3101                 MISSING_CASE(plane_config->tiling);
3102                 goto out;
3103         }
3104
3105         mode_cmd.pixel_format = fb->format->format;
3106         mode_cmd.width = fb->width;
3107         mode_cmd.height = fb->height;
3108         mode_cmd.pitches[0] = fb->pitches[0];
3109         mode_cmd.modifier[0] = fb->modifier;
3110         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3111
3112         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3113                 DRM_DEBUG_KMS("intel fb init failed\n");
3114                 goto out;
3115         }
3116
3117
3118         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3119         ret = true;
3120 out:
3121         i915_gem_object_put(obj);
3122         return ret;
3123 }
3124
3125 static void
3126 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3127                         struct intel_plane_state *plane_state,
3128                         bool visible)
3129 {
3130         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3131
3132         plane_state->uapi.visible = visible;
3133
3134         if (visible)
3135                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3136         else
3137                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3138 }
3139
3140 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3141 {
3142         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3143         struct drm_plane *plane;
3144
3145         /*
3146          * Active_planes aliases if multiple "primary" or cursor planes
3147          * have been used on the same (or wrong) pipe. plane_mask uses
3148          * unique ids, hence we can use that to reconstruct active_planes.
3149          */
3150         crtc_state->active_planes = 0;
3151
3152         drm_for_each_plane_mask(plane, &dev_priv->drm,
3153                                 crtc_state->uapi.plane_mask)
3154                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3155 }
3156
3157 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3158                                          struct intel_plane *plane)
3159 {
3160         struct intel_crtc_state *crtc_state =
3161                 to_intel_crtc_state(crtc->base.state);
3162         struct intel_plane_state *plane_state =
3163                 to_intel_plane_state(plane->base.state);
3164
3165         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3166                       plane->base.base.id, plane->base.name,
3167                       crtc->base.base.id, crtc->base.name);
3168
3169         intel_set_plane_visible(crtc_state, plane_state, false);
3170         fixup_active_planes(crtc_state);
3171         crtc_state->data_rate[plane->id] = 0;
3172         crtc_state->min_cdclk[plane->id] = 0;
3173
3174         if (plane->id == PLANE_PRIMARY)
3175                 intel_pre_disable_primary_noatomic(&crtc->base);
3176
3177         intel_disable_plane(plane, crtc_state);
3178 }
3179
3180 static struct intel_frontbuffer *
3181 to_intel_frontbuffer(struct drm_framebuffer *fb)
3182 {
3183         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3184 }
3185
3186 static void
3187 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3188                              struct intel_initial_plane_config *plane_config)
3189 {
3190         struct drm_device *dev = intel_crtc->base.dev;
3191         struct drm_i915_private *dev_priv = to_i915(dev);
3192         struct drm_crtc *c;
3193         struct drm_plane *primary = intel_crtc->base.primary;
3194         struct drm_plane_state *plane_state = primary->state;
3195         struct intel_plane *intel_plane = to_intel_plane(primary);
3196         struct intel_plane_state *intel_state =
3197                 to_intel_plane_state(plane_state);
3198         struct drm_framebuffer *fb;
3199
3200         if (!plane_config->fb)
3201                 return;
3202
3203         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3204                 fb = &plane_config->fb->base;
3205                 goto valid_fb;
3206         }
3207
3208         kfree(plane_config->fb);
3209
3210         /*
3211          * Failed to alloc the obj, check to see if we should share
3212          * an fb with another CRTC instead
3213          */
3214         for_each_crtc(dev, c) {
3215                 struct intel_plane_state *state;
3216
3217                 if (c == &intel_crtc->base)
3218                         continue;
3219
3220                 if (!to_intel_crtc(c)->active)
3221                         continue;
3222
3223                 state = to_intel_plane_state(c->primary->state);
3224                 if (!state->vma)
3225                         continue;
3226
3227                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3228                         fb = state->hw.fb;
3229                         drm_framebuffer_get(fb);
3230                         goto valid_fb;
3231                 }
3232         }
3233
3234         /*
3235          * We've failed to reconstruct the BIOS FB.  Current display state
3236          * indicates that the primary plane is visible, but has a NULL FB,
3237          * which will lead to problems later if we don't fix it up.  The
3238          * simplest solution is to just disable the primary plane now and
3239          * pretend the BIOS never had it enabled.
3240          */
3241         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3242
3243         return;
3244
3245 valid_fb:
3246         intel_state->hw.rotation = plane_config->rotation;
3247         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3248                                 intel_state->hw.rotation);
3249         intel_state->color_plane[0].stride =
3250                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3251
3252         intel_state->vma =
3253                 intel_pin_and_fence_fb_obj(fb,
3254                                            &intel_state->view,
3255                                            intel_plane_uses_fence(intel_state),
3256                                            &intel_state->flags);
3257         if (IS_ERR(intel_state->vma)) {
3258                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3259                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
3260
3261                 intel_state->vma = NULL;
3262                 drm_framebuffer_put(fb);
3263                 return;
3264         }
3265
3266         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3267
3268         plane_state->src_x = 0;
3269         plane_state->src_y = 0;
3270         plane_state->src_w = fb->width << 16;
3271         plane_state->src_h = fb->height << 16;
3272
3273         plane_state->crtc_x = 0;
3274         plane_state->crtc_y = 0;
3275         plane_state->crtc_w = fb->width;
3276         plane_state->crtc_h = fb->height;
3277
3278         intel_state->uapi.src = drm_plane_state_src(plane_state);
3279         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3280
3281         if (plane_config->tiling)
3282                 dev_priv->preserve_bios_swizzle = true;
3283
3284         plane_state->fb = fb;
3285         plane_state->crtc = &intel_crtc->base;
3286
3287         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3288                   &to_intel_frontbuffer(fb)->bits);
3289 }
3290
3291 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3292                                int color_plane,
3293                                unsigned int rotation)
3294 {
3295         int cpp = fb->format->cpp[color_plane];
3296
3297         switch (fb->modifier) {
3298         case DRM_FORMAT_MOD_LINEAR:
3299         case I915_FORMAT_MOD_X_TILED:
3300                 /*
3301                  * Validated limit is 4k, but has 5k should
3302                  * work apart from the following features:
3303                  * - Ytile (already limited to 4k)
3304                  * - FP16 (already limited to 4k)
3305                  * - render compression (already limited to 4k)
3306                  * - KVMR sprite and cursor (don't care)
3307                  * - horizontal panning (TODO verify this)
3308                  * - pipe and plane scaling (TODO verify this)
3309                  */
3310                 if (cpp == 8)
3311                         return 4096;
3312                 else
3313                         return 5120;
3314         case I915_FORMAT_MOD_Y_TILED_CCS:
3315         case I915_FORMAT_MOD_Yf_TILED_CCS:
3316                 /* FIXME AUX plane? */
3317         case I915_FORMAT_MOD_Y_TILED:
3318         case I915_FORMAT_MOD_Yf_TILED:
3319                 if (cpp == 8)
3320                         return 2048;
3321                 else
3322                         return 4096;
3323         default:
3324                 MISSING_CASE(fb->modifier);
3325                 return 2048;
3326         }
3327 }
3328
3329 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3330                                int color_plane,
3331                                unsigned int rotation)
3332 {
3333         int cpp = fb->format->cpp[color_plane];
3334
3335         switch (fb->modifier) {
3336         case DRM_FORMAT_MOD_LINEAR:
3337         case I915_FORMAT_MOD_X_TILED:
3338                 if (cpp == 8)
3339                         return 4096;
3340                 else
3341                         return 5120;
3342         case I915_FORMAT_MOD_Y_TILED_CCS:
3343         case I915_FORMAT_MOD_Yf_TILED_CCS:
3344                 /* FIXME AUX plane? */
3345         case I915_FORMAT_MOD_Y_TILED:
3346         case I915_FORMAT_MOD_Yf_TILED:
3347                 if (cpp == 8)
3348                         return 2048;
3349                 else
3350                         return 5120;
3351         default:
3352                 MISSING_CASE(fb->modifier);
3353                 return 2048;
3354         }
3355 }
3356
3357 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3358                                int color_plane,
3359                                unsigned int rotation)
3360 {
3361         return 5120;
3362 }
3363
3364 static int skl_max_plane_height(void)
3365 {
3366         return 4096;
3367 }
3368
3369 static int icl_max_plane_height(void)
3370 {
3371         return 4320;
3372 }
3373
3374 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3375                                            int main_x, int main_y, u32 main_offset)
3376 {
3377         const struct drm_framebuffer *fb = plane_state->hw.fb;
3378         int hsub = fb->format->hsub;
3379         int vsub = fb->format->vsub;
3380         int aux_x = plane_state->color_plane[1].x;
3381         int aux_y = plane_state->color_plane[1].y;
3382         u32 aux_offset = plane_state->color_plane[1].offset;
3383         u32 alignment = intel_surf_alignment(fb, 1);
3384
3385         while (aux_offset >= main_offset && aux_y <= main_y) {
3386                 int x, y;
3387
3388                 if (aux_x == main_x && aux_y == main_y)
3389                         break;
3390
3391                 if (aux_offset == 0)
3392                         break;
3393
3394                 x = aux_x / hsub;
3395                 y = aux_y / vsub;
3396                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3397                                                                aux_offset, aux_offset - alignment);
3398                 aux_x = x * hsub + aux_x % hsub;
3399                 aux_y = y * vsub + aux_y % vsub;
3400         }
3401
3402         if (aux_x != main_x || aux_y != main_y)
3403                 return false;
3404
3405         plane_state->color_plane[1].offset = aux_offset;
3406         plane_state->color_plane[1].x = aux_x;
3407         plane_state->color_plane[1].y = aux_y;
3408
3409         return true;
3410 }
3411
3412 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3413 {
3414         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3415         const struct drm_framebuffer *fb = plane_state->hw.fb;
3416         unsigned int rotation = plane_state->hw.rotation;
3417         int x = plane_state->uapi.src.x1 >> 16;
3418         int y = plane_state->uapi.src.y1 >> 16;
3419         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3420         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3421         int max_width;
3422         int max_height;
3423         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3424
3425         if (INTEL_GEN(dev_priv) >= 11)
3426                 max_width = icl_max_plane_width(fb, 0, rotation);
3427         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3428                 max_width = glk_max_plane_width(fb, 0, rotation);
3429         else
3430                 max_width = skl_max_plane_width(fb, 0, rotation);
3431
3432         if (INTEL_GEN(dev_priv) >= 11)
3433                 max_height = icl_max_plane_height();
3434         else
3435                 max_height = skl_max_plane_height();
3436
3437         if (w > max_width || h > max_height) {
3438                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3439                               w, h, max_width, max_height);
3440                 return -EINVAL;
3441         }
3442
3443         intel_add_fb_offsets(&x, &y, plane_state, 0);
3444         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3445         alignment = intel_surf_alignment(fb, 0);
3446
3447         /*
3448          * AUX surface offset is specified as the distance from the
3449          * main surface offset, and it must be non-negative. Make
3450          * sure that is what we will get.
3451          */
3452         if (offset > aux_offset)
3453                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3454                                                            offset, aux_offset & ~(alignment - 1));
3455
3456         /*
3457          * When using an X-tiled surface, the plane blows up
3458          * if the x offset + width exceed the stride.
3459          *
3460          * TODO: linear and Y-tiled seem fine, Yf untested,
3461          */
3462         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3463                 int cpp = fb->format->cpp[0];
3464
3465                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3466                         if (offset == 0) {
3467                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3468                                 return -EINVAL;
3469                         }
3470
3471                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3472                                                                    offset, offset - alignment);
3473                 }
3474         }
3475
3476         /*
3477          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3478          * they match with the main surface x/y offsets.
3479          */
3480         if (is_ccs_modifier(fb->modifier)) {
3481                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3482                         if (offset == 0)
3483                                 break;
3484
3485                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3486                                                                    offset, offset - alignment);
3487                 }
3488
3489                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3490                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3491                         return -EINVAL;
3492                 }
3493         }
3494
3495         plane_state->color_plane[0].offset = offset;
3496         plane_state->color_plane[0].x = x;
3497         plane_state->color_plane[0].y = y;
3498
3499         /*
3500          * Put the final coordinates back so that the src
3501          * coordinate checks will see the right values.
3502          */
3503         drm_rect_translate_to(&plane_state->uapi.src,
3504                               x << 16, y << 16);
3505
3506         return 0;
3507 }
3508
3509 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3510 {
3511         const struct drm_framebuffer *fb = plane_state->hw.fb;
3512         unsigned int rotation = plane_state->hw.rotation;
3513         int max_width = skl_max_plane_width(fb, 1, rotation);
3514         int max_height = 4096;
3515         int x = plane_state->uapi.src.x1 >> 17;
3516         int y = plane_state->uapi.src.y1 >> 17;
3517         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3518         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3519         u32 offset;
3520
3521         intel_add_fb_offsets(&x, &y, plane_state, 1);
3522         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3523
3524         /* FIXME not quite sure how/if these apply to the chroma plane */
3525         if (w > max_width || h > max_height) {
3526                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3527                               w, h, max_width, max_height);
3528                 return -EINVAL;
3529         }
3530
3531         plane_state->color_plane[1].offset = offset;
3532         plane_state->color_plane[1].x = x;
3533         plane_state->color_plane[1].y = y;
3534
3535         return 0;
3536 }
3537
3538 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3539 {
3540         const struct drm_framebuffer *fb = plane_state->hw.fb;
3541         int src_x = plane_state->uapi.src.x1 >> 16;
3542         int src_y = plane_state->uapi.src.y1 >> 16;
3543         int hsub = fb->format->hsub;
3544         int vsub = fb->format->vsub;
3545         int x = src_x / hsub;
3546         int y = src_y / vsub;
3547         u32 offset;
3548
3549         intel_add_fb_offsets(&x, &y, plane_state, 1);
3550         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3551
3552         plane_state->color_plane[1].offset = offset;
3553         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3554         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3555
3556         return 0;
3557 }
3558
3559 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3560 {
3561         const struct drm_framebuffer *fb = plane_state->hw.fb;
3562         int ret;
3563
3564         ret = intel_plane_compute_gtt(plane_state);
3565         if (ret)
3566                 return ret;
3567
3568         if (!plane_state->uapi.visible)
3569                 return 0;
3570
3571         /*
3572          * Handle the AUX surface first since
3573          * the main surface setup depends on it.
3574          */
3575         if (drm_format_info_is_yuv_semiplanar(fb->format)) {
3576                 ret = skl_check_nv12_aux_surface(plane_state);
3577                 if (ret)
3578                         return ret;
3579         } else if (is_ccs_modifier(fb->modifier)) {
3580                 ret = skl_check_ccs_aux_surface(plane_state);
3581                 if (ret)
3582                         return ret;
3583         } else {
3584                 plane_state->color_plane[1].offset = ~0xfff;
3585                 plane_state->color_plane[1].x = 0;
3586                 plane_state->color_plane[1].y = 0;
3587         }
3588
3589         ret = skl_check_main_surface(plane_state);
3590         if (ret)
3591                 return ret;
3592
3593         return 0;
3594 }
3595
3596 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
3597                              const struct intel_plane_state *plane_state,
3598                              unsigned int *num, unsigned int *den)
3599 {
3600         const struct drm_framebuffer *fb = plane_state->hw.fb;
3601         unsigned int cpp = fb->format->cpp[0];
3602
3603         /*
3604          * g4x bspec says 64bpp pixel rate can't exceed 80%
3605          * of cdclk when the sprite plane is enabled on the
3606          * same pipe. ilk/snb bspec says 64bpp pixel rate is
3607          * never allowed to exceed 80% of cdclk. Let's just go
3608          * with the ilk/snb limit always.
3609          */
3610         if (cpp == 8) {
3611                 *num = 10;
3612                 *den = 8;
3613         } else {
3614                 *num = 1;
3615                 *den = 1;
3616         }
3617 }
3618
3619 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
3620                                 const struct intel_plane_state *plane_state)
3621 {
3622         unsigned int pixel_rate;
3623         unsigned int num, den;
3624
3625         /*
3626          * Note that crtc_state->pixel_rate accounts for both
3627          * horizontal and vertical panel fitter downscaling factors.
3628          * Pre-HSW bspec tells us to only consider the horizontal
3629          * downscaling factor here. We ignore that and just consider
3630          * both for simplicity.
3631          */
3632         pixel_rate = crtc_state->pixel_rate;
3633
3634         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
3635
3636         /* two pixels per clock with double wide pipe */
3637         if (crtc_state->double_wide)
3638                 den *= 2;
3639
3640         return DIV_ROUND_UP(pixel_rate * num, den);
3641 }
3642
3643 unsigned int
3644 i9xx_plane_max_stride(struct intel_plane *plane,
3645                       u32 pixel_format, u64 modifier,
3646                       unsigned int rotation)
3647 {
3648         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3649
3650         if (!HAS_GMCH(dev_priv)) {
3651                 return 32*1024;
3652         } else if (INTEL_GEN(dev_priv) >= 4) {
3653                 if (modifier == I915_FORMAT_MOD_X_TILED)
3654                         return 16*1024;
3655                 else
3656                         return 32*1024;
3657         } else if (INTEL_GEN(dev_priv) >= 3) {
3658                 if (modifier == I915_FORMAT_MOD_X_TILED)
3659                         return 8*1024;
3660                 else
3661                         return 16*1024;
3662         } else {
3663                 if (plane->i9xx_plane == PLANE_C)
3664                         return 4*1024;
3665                 else
3666                         return 8*1024;
3667         }
3668 }
3669
3670 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3671 {
3672         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3673         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3674         u32 dspcntr = 0;
3675
3676         if (crtc_state->gamma_enable)
3677                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3678
3679         if (crtc_state->csc_enable)
3680                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3681
3682         if (INTEL_GEN(dev_priv) < 5)
3683                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3684
3685         return dspcntr;
3686 }
3687
3688 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3689                           const struct intel_plane_state *plane_state)
3690 {
3691         struct drm_i915_private *dev_priv =
3692                 to_i915(plane_state->uapi.plane->dev);
3693         const struct drm_framebuffer *fb = plane_state->hw.fb;
3694         unsigned int rotation = plane_state->hw.rotation;
3695         u32 dspcntr;
3696
3697         dspcntr = DISPLAY_PLANE_ENABLE;
3698
3699         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3700             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3701                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3702
3703         switch (fb->format->format) {
3704         case DRM_FORMAT_C8:
3705                 dspcntr |= DISPPLANE_8BPP;
3706                 break;
3707         case DRM_FORMAT_XRGB1555:
3708                 dspcntr |= DISPPLANE_BGRX555;
3709                 break;
3710         case DRM_FORMAT_RGB565:
3711                 dspcntr |= DISPPLANE_BGRX565;
3712                 break;
3713         case DRM_FORMAT_XRGB8888:
3714                 dspcntr |= DISPPLANE_BGRX888;
3715                 break;
3716         case DRM_FORMAT_XBGR8888:
3717                 dspcntr |= DISPPLANE_RGBX888;
3718                 break;
3719         case DRM_FORMAT_XRGB2101010:
3720                 dspcntr |= DISPPLANE_BGRX101010;
3721                 break;
3722         case DRM_FORMAT_XBGR2101010:
3723                 dspcntr |= DISPPLANE_RGBX101010;
3724                 break;
3725         case DRM_FORMAT_XBGR16161616F:
3726                 dspcntr |= DISPPLANE_RGBX161616;
3727                 break;
3728         default:
3729                 MISSING_CASE(fb->format->format);
3730                 return 0;
3731         }
3732
3733         if (INTEL_GEN(dev_priv) >= 4 &&
3734             fb->modifier == I915_FORMAT_MOD_X_TILED)
3735                 dspcntr |= DISPPLANE_TILED;
3736
3737         if (rotation & DRM_MODE_ROTATE_180)
3738                 dspcntr |= DISPPLANE_ROTATE_180;
3739
3740         if (rotation & DRM_MODE_REFLECT_X)
3741                 dspcntr |= DISPPLANE_MIRROR;
3742
3743         return dspcntr;
3744 }
3745
3746 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3747 {
3748         struct drm_i915_private *dev_priv =
3749                 to_i915(plane_state->uapi.plane->dev);
3750         const struct drm_framebuffer *fb = plane_state->hw.fb;
3751         int src_x, src_y, src_w;
3752         u32 offset;
3753         int ret;
3754
3755         ret = intel_plane_compute_gtt(plane_state);
3756         if (ret)
3757                 return ret;
3758
3759         if (!plane_state->uapi.visible)
3760                 return 0;
3761
3762         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3763         src_x = plane_state->uapi.src.x1 >> 16;
3764         src_y = plane_state->uapi.src.y1 >> 16;
3765
3766         /* Undocumented hardware limit on i965/g4x/vlv/chv */
3767         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
3768                 return -EINVAL;
3769
3770         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3771
3772         if (INTEL_GEN(dev_priv) >= 4)
3773                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3774                                                             plane_state, 0);
3775         else
3776                 offset = 0;
3777
3778         /*
3779          * Put the final coordinates back so that the src
3780          * coordinate checks will see the right values.
3781          */
3782         drm_rect_translate_to(&plane_state->uapi.src,
3783                               src_x << 16, src_y << 16);
3784
3785         /* HSW/BDW do this automagically in hardware */
3786         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3787                 unsigned int rotation = plane_state->hw.rotation;
3788                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3789                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3790
3791                 if (rotation & DRM_MODE_ROTATE_180) {
3792                         src_x += src_w - 1;
3793                         src_y += src_h - 1;
3794                 } else if (rotation & DRM_MODE_REFLECT_X) {
3795                         src_x += src_w - 1;
3796                 }
3797         }
3798
3799         plane_state->color_plane[0].offset = offset;
3800         plane_state->color_plane[0].x = src_x;
3801         plane_state->color_plane[0].y = src_y;
3802
3803         return 0;
3804 }
3805
3806 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3807 {
3808         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3809         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3810
3811         if (IS_CHERRYVIEW(dev_priv))
3812                 return i9xx_plane == PLANE_B;
3813         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3814                 return false;
3815         else if (IS_GEN(dev_priv, 4))
3816                 return i9xx_plane == PLANE_C;
3817         else
3818                 return i9xx_plane == PLANE_B ||
3819                         i9xx_plane == PLANE_C;
3820 }
3821
3822 static int
3823 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3824                  struct intel_plane_state *plane_state)
3825 {
3826         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3827         int ret;
3828
3829         ret = chv_plane_check_rotation(plane_state);
3830         if (ret)
3831                 return ret;
3832
3833         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
3834                                                   &crtc_state->uapi,
3835                                                   DRM_PLANE_HELPER_NO_SCALING,
3836                                                   DRM_PLANE_HELPER_NO_SCALING,
3837                                                   i9xx_plane_has_windowing(plane),
3838                                                   true);
3839         if (ret)
3840                 return ret;
3841
3842         ret = i9xx_check_plane_surface(plane_state);
3843         if (ret)
3844                 return ret;
3845
3846         if (!plane_state->uapi.visible)
3847                 return 0;
3848
3849         ret = intel_plane_check_src_coordinates(plane_state);
3850         if (ret)
3851                 return ret;
3852
3853         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3854
3855         return 0;
3856 }
3857
3858 static void i9xx_update_plane(struct intel_plane *plane,
3859                               const struct intel_crtc_state *crtc_state,
3860                               const struct intel_plane_state *plane_state)
3861 {
3862         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3863         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3864         u32 linear_offset;
3865         int x = plane_state->color_plane[0].x;
3866         int y = plane_state->color_plane[0].y;
3867         int crtc_x = plane_state->uapi.dst.x1;
3868         int crtc_y = plane_state->uapi.dst.y1;
3869         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
3870         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
3871         unsigned long irqflags;
3872         u32 dspaddr_offset;
3873         u32 dspcntr;
3874
3875         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3876
3877         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3878
3879         if (INTEL_GEN(dev_priv) >= 4)
3880                 dspaddr_offset = plane_state->color_plane[0].offset;
3881         else
3882                 dspaddr_offset = linear_offset;
3883
3884         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3885
3886         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3887
3888         if (INTEL_GEN(dev_priv) < 4) {
3889                 /*
3890                  * PLANE_A doesn't actually have a full window
3891                  * generator but let's assume we still need to
3892                  * program whatever is there.
3893                  */
3894                 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3895                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3896                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3897         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3898                 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3899                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3900                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3901                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3902         }
3903
3904         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3905                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3906         } else if (INTEL_GEN(dev_priv) >= 4) {
3907                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3908                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3909         }
3910
3911         /*
3912          * The control register self-arms if the plane was previously
3913          * disabled. Try to make the plane enable atomic by writing
3914          * the control register just before the surface register.
3915          */
3916         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3917         if (INTEL_GEN(dev_priv) >= 4)
3918                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3919                               intel_plane_ggtt_offset(plane_state) +
3920                               dspaddr_offset);
3921         else
3922                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3923                               intel_plane_ggtt_offset(plane_state) +
3924                               dspaddr_offset);
3925
3926         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3927 }
3928
3929 static void i9xx_disable_plane(struct intel_plane *plane,
3930                                const struct intel_crtc_state *crtc_state)
3931 {
3932         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3933         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3934         unsigned long irqflags;
3935         u32 dspcntr;
3936
3937         /*
3938          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3939          * enable on ilk+ affect the pipe bottom color as
3940          * well, so we must configure them even if the plane
3941          * is disabled.
3942          *
3943          * On pre-g4x there is no way to gamma correct the
3944          * pipe bottom color but we'll keep on doing this
3945          * anyway so that the crtc state readout works correctly.
3946          */
3947         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
3948
3949         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3950
3951         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3952         if (INTEL_GEN(dev_priv) >= 4)
3953                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3954         else
3955                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3956
3957         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3958 }
3959
3960 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3961                                     enum pipe *pipe)
3962 {
3963         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3964         enum intel_display_power_domain power_domain;
3965         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3966         intel_wakeref_t wakeref;
3967         bool ret;
3968         u32 val;
3969
3970         /*
3971          * Not 100% correct for planes that can move between pipes,
3972          * but that's only the case for gen2-4 which don't have any
3973          * display power wells.
3974          */
3975         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3976         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3977         if (!wakeref)
3978                 return false;
3979
3980         val = I915_READ(DSPCNTR(i9xx_plane));
3981
3982         ret = val & DISPLAY_PLANE_ENABLE;
3983
3984         if (INTEL_GEN(dev_priv) >= 5)
3985                 *pipe = plane->pipe;
3986         else
3987                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3988                         DISPPLANE_SEL_PIPE_SHIFT;
3989
3990         intel_display_power_put(dev_priv, power_domain, wakeref);
3991
3992         return ret;
3993 }
3994
3995 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3996 {
3997         struct drm_device *dev = intel_crtc->base.dev;
3998         struct drm_i915_private *dev_priv = to_i915(dev);
3999
4000         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4001         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4002         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4003 }
4004
4005 /*
4006  * This function detaches (aka. unbinds) unused scalers in hardware
4007  */
4008 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4009 {
4010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4011         const struct intel_crtc_scaler_state *scaler_state =
4012                 &crtc_state->scaler_state;
4013         int i;
4014
4015         /* loop through and disable scalers that aren't in use */
4016         for (i = 0; i < intel_crtc->num_scalers; i++) {
4017                 if (!scaler_state->scalers[i].in_use)
4018                         skl_detach_scaler(intel_crtc, i);
4019         }
4020 }
4021
4022 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4023                                           int color_plane, unsigned int rotation)
4024 {
4025         /*
4026          * The stride is either expressed as a multiple of 64 bytes chunks for
4027          * linear buffers or in number of tiles for tiled buffers.
4028          */
4029         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
4030                 return 64;
4031         else if (drm_rotation_90_or_270(rotation))
4032                 return intel_tile_height(fb, color_plane);
4033         else
4034                 return intel_tile_width_bytes(fb, color_plane);
4035 }
4036
4037 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4038                      int color_plane)
4039 {
4040         const struct drm_framebuffer *fb = plane_state->hw.fb;
4041         unsigned int rotation = plane_state->hw.rotation;
4042         u32 stride = plane_state->color_plane[color_plane].stride;
4043
4044         if (color_plane >= fb->format->num_planes)
4045                 return 0;
4046
4047         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4048 }
4049
4050 static u32 skl_plane_ctl_format(u32 pixel_format)
4051 {
4052         switch (pixel_format) {
4053         case DRM_FORMAT_C8:
4054                 return PLANE_CTL_FORMAT_INDEXED;
4055         case DRM_FORMAT_RGB565:
4056                 return PLANE_CTL_FORMAT_RGB_565;
4057         case DRM_FORMAT_XBGR8888:
4058         case DRM_FORMAT_ABGR8888:
4059                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4060         case DRM_FORMAT_XRGB8888:
4061         case DRM_FORMAT_ARGB8888:
4062                 return PLANE_CTL_FORMAT_XRGB_8888;
4063         case DRM_FORMAT_XBGR2101010:
4064                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4065         case DRM_FORMAT_XRGB2101010:
4066                 return PLANE_CTL_FORMAT_XRGB_2101010;
4067         case DRM_FORMAT_XBGR16161616F:
4068         case DRM_FORMAT_ABGR16161616F:
4069                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4070         case DRM_FORMAT_XRGB16161616F:
4071         case DRM_FORMAT_ARGB16161616F:
4072                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4073         case DRM_FORMAT_YUYV:
4074                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4075         case DRM_FORMAT_YVYU:
4076                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4077         case DRM_FORMAT_UYVY:
4078                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4079         case DRM_FORMAT_VYUY:
4080                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4081         case DRM_FORMAT_NV12:
4082                 return PLANE_CTL_FORMAT_NV12;
4083         case DRM_FORMAT_P010:
4084                 return PLANE_CTL_FORMAT_P010;
4085         case DRM_FORMAT_P012:
4086                 return PLANE_CTL_FORMAT_P012;
4087         case DRM_FORMAT_P016:
4088                 return PLANE_CTL_FORMAT_P016;
4089         case DRM_FORMAT_Y210:
4090                 return PLANE_CTL_FORMAT_Y210;
4091         case DRM_FORMAT_Y212:
4092                 return PLANE_CTL_FORMAT_Y212;
4093         case DRM_FORMAT_Y216:
4094                 return PLANE_CTL_FORMAT_Y216;
4095         case DRM_FORMAT_XVYU2101010:
4096                 return PLANE_CTL_FORMAT_Y410;
4097         case DRM_FORMAT_XVYU12_16161616:
4098                 return PLANE_CTL_FORMAT_Y412;
4099         case DRM_FORMAT_XVYU16161616:
4100                 return PLANE_CTL_FORMAT_Y416;
4101         default:
4102                 MISSING_CASE(pixel_format);
4103         }
4104
4105         return 0;
4106 }
4107
4108 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4109 {
4110         if (!plane_state->hw.fb->format->has_alpha)
4111                 return PLANE_CTL_ALPHA_DISABLE;
4112
4113         switch (plane_state->hw.pixel_blend_mode) {
4114         case DRM_MODE_BLEND_PIXEL_NONE:
4115                 return PLANE_CTL_ALPHA_DISABLE;
4116         case DRM_MODE_BLEND_PREMULTI:
4117                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4118         case DRM_MODE_BLEND_COVERAGE:
4119                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4120         default:
4121                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4122                 return PLANE_CTL_ALPHA_DISABLE;
4123         }
4124 }
4125
4126 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4127 {
4128         if (!plane_state->hw.fb->format->has_alpha)
4129                 return PLANE_COLOR_ALPHA_DISABLE;
4130
4131         switch (plane_state->hw.pixel_blend_mode) {
4132         case DRM_MODE_BLEND_PIXEL_NONE:
4133                 return PLANE_COLOR_ALPHA_DISABLE;
4134         case DRM_MODE_BLEND_PREMULTI:
4135                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4136         case DRM_MODE_BLEND_COVERAGE:
4137                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4138         default:
4139                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4140                 return PLANE_COLOR_ALPHA_DISABLE;
4141         }
4142 }
4143
4144 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4145 {
4146         switch (fb_modifier) {
4147         case DRM_FORMAT_MOD_LINEAR:
4148                 break;
4149         case I915_FORMAT_MOD_X_TILED:
4150                 return PLANE_CTL_TILED_X;
4151         case I915_FORMAT_MOD_Y_TILED:
4152                 return PLANE_CTL_TILED_Y;
4153         case I915_FORMAT_MOD_Y_TILED_CCS:
4154                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4155         case I915_FORMAT_MOD_Yf_TILED:
4156                 return PLANE_CTL_TILED_YF;
4157         case I915_FORMAT_MOD_Yf_TILED_CCS:
4158                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4159         default:
4160                 MISSING_CASE(fb_modifier);
4161         }
4162
4163         return 0;
4164 }
4165
4166 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4167 {
4168         switch (rotate) {
4169         case DRM_MODE_ROTATE_0:
4170                 break;
4171         /*
4172          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4173          * while i915 HW rotation is clockwise, thats why this swapping.
4174          */
4175         case DRM_MODE_ROTATE_90:
4176                 return PLANE_CTL_ROTATE_270;
4177         case DRM_MODE_ROTATE_180:
4178                 return PLANE_CTL_ROTATE_180;
4179         case DRM_MODE_ROTATE_270:
4180                 return PLANE_CTL_ROTATE_90;
4181         default:
4182                 MISSING_CASE(rotate);
4183         }
4184
4185         return 0;
4186 }
4187
4188 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4189 {
4190         switch (reflect) {
4191         case 0:
4192                 break;
4193         case DRM_MODE_REFLECT_X:
4194                 return PLANE_CTL_FLIP_HORIZONTAL;
4195         case DRM_MODE_REFLECT_Y:
4196         default:
4197                 MISSING_CASE(reflect);
4198         }
4199
4200         return 0;
4201 }
4202
4203 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4204 {
4205         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4206         u32 plane_ctl = 0;
4207
4208         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4209                 return plane_ctl;
4210
4211         if (crtc_state->gamma_enable)
4212                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4213
4214         if (crtc_state->csc_enable)
4215                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4216
4217         return plane_ctl;
4218 }
4219
4220 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4221                   const struct intel_plane_state *plane_state)
4222 {
4223         struct drm_i915_private *dev_priv =
4224                 to_i915(plane_state->uapi.plane->dev);
4225         const struct drm_framebuffer *fb = plane_state->hw.fb;
4226         unsigned int rotation = plane_state->hw.rotation;
4227         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4228         u32 plane_ctl;
4229
4230         plane_ctl = PLANE_CTL_ENABLE;
4231
4232         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4233                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4234                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4235
4236                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4237                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4238
4239                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4240                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4241         }
4242
4243         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4244         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4245         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4246
4247         if (INTEL_GEN(dev_priv) >= 10)
4248                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4249                                                 DRM_MODE_REFLECT_MASK);
4250
4251         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4252                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4253         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4254                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4255
4256         return plane_ctl;
4257 }
4258
4259 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4260 {
4261         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4262         u32 plane_color_ctl = 0;
4263
4264         if (INTEL_GEN(dev_priv) >= 11)
4265                 return plane_color_ctl;
4266
4267         if (crtc_state->gamma_enable)
4268                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4269
4270         if (crtc_state->csc_enable)
4271                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4272
4273         return plane_color_ctl;
4274 }
4275
4276 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4277                         const struct intel_plane_state *plane_state)
4278 {
4279         struct drm_i915_private *dev_priv =
4280                 to_i915(plane_state->uapi.plane->dev);
4281         const struct drm_framebuffer *fb = plane_state->hw.fb;
4282         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4283         u32 plane_color_ctl = 0;
4284
4285         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4286         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4287
4288         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4289                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4290                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4291                 else
4292                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4293
4294                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4295                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4296         } else if (fb->format->is_yuv) {
4297                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4298         }
4299
4300         return plane_color_ctl;
4301 }
4302
4303 static int
4304 __intel_display_resume(struct drm_device *dev,
4305                        struct drm_atomic_state *state,
4306                        struct drm_modeset_acquire_ctx *ctx)
4307 {
4308         struct drm_crtc_state *crtc_state;
4309         struct drm_crtc *crtc;
4310         int i, ret;
4311
4312         intel_modeset_setup_hw_state(dev, ctx);
4313         intel_vga_redisable(to_i915(dev));
4314
4315         if (!state)
4316                 return 0;
4317
4318         /*
4319          * We've duplicated the state, pointers to the old state are invalid.
4320          *
4321          * Don't attempt to use the old state until we commit the duplicated state.
4322          */
4323         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4324                 /*
4325                  * Force recalculation even if we restore
4326                  * current state. With fast modeset this may not result
4327                  * in a modeset when the state is compatible.
4328                  */
4329                 crtc_state->mode_changed = true;
4330         }
4331
4332         /* ignore any reset values/BIOS leftovers in the WM registers */
4333         if (!HAS_GMCH(to_i915(dev)))
4334                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4335
4336         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4337
4338         WARN_ON(ret == -EDEADLK);
4339         return ret;
4340 }
4341
4342 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4343 {
4344         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4345                 intel_has_gpu_reset(&dev_priv->gt));
4346 }
4347
4348 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4349 {
4350         struct drm_device *dev = &dev_priv->drm;
4351         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4352         struct drm_atomic_state *state;
4353         int ret;
4354
4355         /* reset doesn't touch the display */
4356         if (!i915_modparams.force_reset_modeset_test &&
4357             !gpu_reset_clobbers_display(dev_priv))
4358                 return;
4359
4360         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4361         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4362         smp_mb__after_atomic();
4363         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4364
4365         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4366                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4367                 intel_gt_set_wedged(&dev_priv->gt);
4368         }
4369
4370         /*
4371          * Need mode_config.mutex so that we don't
4372          * trample ongoing ->detect() and whatnot.
4373          */
4374         mutex_lock(&dev->mode_config.mutex);
4375         drm_modeset_acquire_init(ctx, 0);
4376         while (1) {
4377                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4378                 if (ret != -EDEADLK)
4379                         break;
4380
4381                 drm_modeset_backoff(ctx);
4382         }
4383         /*
4384          * Disabling the crtcs gracefully seems nicer. Also the
4385          * g33 docs say we should at least disable all the planes.
4386          */
4387         state = drm_atomic_helper_duplicate_state(dev, ctx);
4388         if (IS_ERR(state)) {
4389                 ret = PTR_ERR(state);
4390                 DRM_ERROR("Duplicating state failed with %i\n", ret);
4391                 return;
4392         }
4393
4394         ret = drm_atomic_helper_disable_all(dev, ctx);
4395         if (ret) {
4396                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4397                 drm_atomic_state_put(state);
4398                 return;
4399         }
4400
4401         dev_priv->modeset_restore_state = state;
4402         state->acquire_ctx = ctx;
4403 }
4404
4405 void intel_finish_reset(struct drm_i915_private *dev_priv)
4406 {
4407         struct drm_device *dev = &dev_priv->drm;
4408         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4409         struct drm_atomic_state *state;
4410         int ret;
4411
4412         /* reset doesn't touch the display */
4413         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4414                 return;
4415
4416         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4417         if (!state)
4418                 goto unlock;
4419
4420         /* reset doesn't touch the display */
4421         if (!gpu_reset_clobbers_display(dev_priv)) {
4422                 /* for testing only restore the display */
4423                 ret = __intel_display_resume(dev, state, ctx);
4424                 if (ret)
4425                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4426         } else {
4427                 /*
4428                  * The display has been reset as well,
4429                  * so need a full re-initialization.
4430                  */
4431                 intel_pps_unlock_regs_wa(dev_priv);
4432                 intel_modeset_init_hw(dev_priv);
4433                 intel_init_clock_gating(dev_priv);
4434
4435                 spin_lock_irq(&dev_priv->irq_lock);
4436                 if (dev_priv->display.hpd_irq_setup)
4437                         dev_priv->display.hpd_irq_setup(dev_priv);
4438                 spin_unlock_irq(&dev_priv->irq_lock);
4439
4440                 ret = __intel_display_resume(dev, state, ctx);
4441                 if (ret)
4442                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4443
4444                 intel_hpd_init(dev_priv);
4445         }
4446
4447         drm_atomic_state_put(state);
4448 unlock:
4449         drm_modeset_drop_locks(ctx);
4450         drm_modeset_acquire_fini(ctx);
4451         mutex_unlock(&dev->mode_config.mutex);
4452
4453         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4454 }
4455
4456 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4457 {
4458         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4459         enum pipe pipe = crtc->pipe;
4460         u32 tmp;
4461
4462         tmp = I915_READ(PIPE_CHICKEN(pipe));
4463
4464         /*
4465          * Display WA #1153: icl
4466          * enable hardware to bypass the alpha math
4467          * and rounding for per-pixel values 00 and 0xff
4468          */
4469         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4470         /*
4471          * Display WA # 1605353570: icl
4472          * Set the pixel rounding bit to 1 for allowing
4473          * passthrough of Frame buffer pixels unmodified
4474          * across pipe
4475          */
4476         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4477         I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4478 }
4479
4480 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
4481 {
4482         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4483         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4484         u32 trans_ddi_func_ctl2_val;
4485         u8 master_select;
4486
4487         /*
4488          * Configure the master select and enable Transcoder Port Sync for
4489          * Slave CRTCs transcoder.
4490          */
4491         if (crtc_state->master_transcoder == INVALID_TRANSCODER)
4492                 return;
4493
4494         if (crtc_state->master_transcoder == TRANSCODER_EDP)
4495                 master_select = 0;
4496         else
4497                 master_select = crtc_state->master_transcoder + 1;
4498
4499         /* Set the master select bits for Tranascoder Port Sync */
4500         trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
4501                                    PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
4502                 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
4503         /* Enable Transcoder Port Sync */
4504         trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
4505
4506         I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
4507                    trans_ddi_func_ctl2_val);
4508 }
4509
4510 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
4511 {
4512         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4514         i915_reg_t reg;
4515         u32 trans_ddi_func_ctl2_val;
4516
4517         if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
4518                 return;
4519
4520         DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
4521                       transcoder_name(old_crtc_state->cpu_transcoder));
4522
4523         reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
4524         trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
4525                                     PORT_SYNC_MODE_MASTER_SELECT_MASK);
4526         I915_WRITE(reg, trans_ddi_func_ctl2_val);
4527 }
4528
4529 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4530 {
4531         struct drm_device *dev = crtc->base.dev;
4532         struct drm_i915_private *dev_priv = to_i915(dev);
4533         enum pipe pipe = crtc->pipe;
4534         i915_reg_t reg;
4535         u32 temp;
4536
4537         /* enable normal train */
4538         reg = FDI_TX_CTL(pipe);
4539         temp = I915_READ(reg);
4540         if (IS_IVYBRIDGE(dev_priv)) {
4541                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4542                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4543         } else {
4544                 temp &= ~FDI_LINK_TRAIN_NONE;
4545                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4546         }
4547         I915_WRITE(reg, temp);
4548
4549         reg = FDI_RX_CTL(pipe);
4550         temp = I915_READ(reg);
4551         if (HAS_PCH_CPT(dev_priv)) {
4552                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4553                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4554         } else {
4555                 temp &= ~FDI_LINK_TRAIN_NONE;
4556                 temp |= FDI_LINK_TRAIN_NONE;
4557         }
4558         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4559
4560         /* wait one idle pattern time */
4561         POSTING_READ(reg);
4562         udelay(1000);
4563
4564         /* IVB wants error correction enabled */
4565         if (IS_IVYBRIDGE(dev_priv))
4566                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4567                            FDI_FE_ERRC_ENABLE);
4568 }
4569
4570 /* The FDI link training functions for ILK/Ibexpeak. */
4571 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4572                                     const struct intel_crtc_state *crtc_state)
4573 {
4574         struct drm_device *dev = crtc->base.dev;
4575         struct drm_i915_private *dev_priv = to_i915(dev);
4576         enum pipe pipe = crtc->pipe;
4577         i915_reg_t reg;
4578         u32 temp, tries;
4579
4580         /* FDI needs bits from pipe first */
4581         assert_pipe_enabled(dev_priv, pipe);
4582
4583         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4584            for train result */
4585         reg = FDI_RX_IMR(pipe);
4586         temp = I915_READ(reg);
4587         temp &= ~FDI_RX_SYMBOL_LOCK;
4588         temp &= ~FDI_RX_BIT_LOCK;
4589         I915_WRITE(reg, temp);
4590         I915_READ(reg);
4591         udelay(150);
4592
4593         /* enable CPU FDI TX and PCH FDI RX */
4594         reg = FDI_TX_CTL(pipe);
4595         temp = I915_READ(reg);
4596         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4597         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4598         temp &= ~FDI_LINK_TRAIN_NONE;
4599         temp |= FDI_LINK_TRAIN_PATTERN_1;
4600         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4601
4602         reg = FDI_RX_CTL(pipe);
4603         temp = I915_READ(reg);
4604         temp &= ~FDI_LINK_TRAIN_NONE;
4605         temp |= FDI_LINK_TRAIN_PATTERN_1;
4606         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4607
4608         POSTING_READ(reg);
4609         udelay(150);
4610
4611         /* Ironlake workaround, enable clock pointer after FDI enable*/
4612         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4613         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4614                    FDI_RX_PHASE_SYNC_POINTER_EN);
4615
4616         reg = FDI_RX_IIR(pipe);
4617         for (tries = 0; tries < 5; tries++) {
4618                 temp = I915_READ(reg);
4619                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4620
4621                 if ((temp & FDI_RX_BIT_LOCK)) {
4622                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4623                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4624                         break;
4625                 }
4626         }
4627         if (tries == 5)
4628                 DRM_ERROR("FDI train 1 fail!\n");
4629
4630         /* Train 2 */
4631         reg = FDI_TX_CTL(pipe);
4632         temp = I915_READ(reg);
4633         temp &= ~FDI_LINK_TRAIN_NONE;
4634         temp |= FDI_LINK_TRAIN_PATTERN_2;
4635         I915_WRITE(reg, temp);
4636
4637         reg = FDI_RX_CTL(pipe);
4638         temp = I915_READ(reg);
4639         temp &= ~FDI_LINK_TRAIN_NONE;
4640         temp |= FDI_LINK_TRAIN_PATTERN_2;
4641         I915_WRITE(reg, temp);
4642
4643         POSTING_READ(reg);
4644         udelay(150);
4645
4646         reg = FDI_RX_IIR(pipe);
4647         for (tries = 0; tries < 5; tries++) {
4648                 temp = I915_READ(reg);
4649                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4650
4651                 if (temp & FDI_RX_SYMBOL_LOCK) {
4652                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4653                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4654                         break;
4655                 }
4656         }
4657         if (tries == 5)
4658                 DRM_ERROR("FDI train 2 fail!\n");
4659
4660         DRM_DEBUG_KMS("FDI train done\n");
4661
4662 }
4663
4664 static const int snb_b_fdi_train_param[] = {
4665         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4666         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4667         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4668         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4669 };
4670
4671 /* The FDI link training functions for SNB/Cougarpoint. */
4672 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4673                                 const struct intel_crtc_state *crtc_state)
4674 {
4675         struct drm_device *dev = crtc->base.dev;
4676         struct drm_i915_private *dev_priv = to_i915(dev);
4677         enum pipe pipe = crtc->pipe;
4678         i915_reg_t reg;
4679         u32 temp, i, retry;
4680
4681         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4682            for train result */
4683         reg = FDI_RX_IMR(pipe);
4684         temp = I915_READ(reg);
4685         temp &= ~FDI_RX_SYMBOL_LOCK;
4686         temp &= ~FDI_RX_BIT_LOCK;
4687         I915_WRITE(reg, temp);
4688
4689         POSTING_READ(reg);
4690         udelay(150);
4691
4692         /* enable CPU FDI TX and PCH FDI RX */
4693         reg = FDI_TX_CTL(pipe);
4694         temp = I915_READ(reg);
4695         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4696         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4697         temp &= ~FDI_LINK_TRAIN_NONE;
4698         temp |= FDI_LINK_TRAIN_PATTERN_1;
4699         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4700         /* SNB-B */
4701         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4702         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4703
4704         I915_WRITE(FDI_RX_MISC(pipe),
4705                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4706
4707         reg = FDI_RX_CTL(pipe);
4708         temp = I915_READ(reg);
4709         if (HAS_PCH_CPT(dev_priv)) {
4710                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4711                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4712         } else {
4713                 temp &= ~FDI_LINK_TRAIN_NONE;
4714                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4715         }
4716         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4717
4718         POSTING_READ(reg);
4719         udelay(150);
4720
4721         for (i = 0; i < 4; i++) {
4722                 reg = FDI_TX_CTL(pipe);
4723                 temp = I915_READ(reg);
4724                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4725                 temp |= snb_b_fdi_train_param[i];
4726                 I915_WRITE(reg, temp);
4727
4728                 POSTING_READ(reg);
4729                 udelay(500);
4730
4731                 for (retry = 0; retry < 5; retry++) {
4732                         reg = FDI_RX_IIR(pipe);
4733                         temp = I915_READ(reg);
4734                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4735                         if (temp & FDI_RX_BIT_LOCK) {
4736                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4737                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4738                                 break;
4739                         }
4740                         udelay(50);
4741                 }
4742                 if (retry < 5)
4743                         break;
4744         }
4745         if (i == 4)
4746                 DRM_ERROR("FDI train 1 fail!\n");
4747
4748         /* Train 2 */
4749         reg = FDI_TX_CTL(pipe);
4750         temp = I915_READ(reg);
4751         temp &= ~FDI_LINK_TRAIN_NONE;
4752         temp |= FDI_LINK_TRAIN_PATTERN_2;
4753         if (IS_GEN(dev_priv, 6)) {
4754                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4755                 /* SNB-B */
4756                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4757         }
4758         I915_WRITE(reg, temp);
4759
4760         reg = FDI_RX_CTL(pipe);
4761         temp = I915_READ(reg);
4762         if (HAS_PCH_CPT(dev_priv)) {
4763                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4764                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4765         } else {
4766                 temp &= ~FDI_LINK_TRAIN_NONE;
4767                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4768         }
4769         I915_WRITE(reg, temp);
4770
4771         POSTING_READ(reg);
4772         udelay(150);
4773
4774         for (i = 0; i < 4; i++) {
4775                 reg = FDI_TX_CTL(pipe);
4776                 temp = I915_READ(reg);
4777                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4778                 temp |= snb_b_fdi_train_param[i];
4779                 I915_WRITE(reg, temp);
4780
4781                 POSTING_READ(reg);
4782                 udelay(500);
4783
4784                 for (retry = 0; retry < 5; retry++) {
4785                         reg = FDI_RX_IIR(pipe);
4786                         temp = I915_READ(reg);
4787                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4788                         if (temp & FDI_RX_SYMBOL_LOCK) {
4789                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4790                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4791                                 break;
4792                         }
4793                         udelay(50);
4794                 }
4795                 if (retry < 5)
4796                         break;
4797         }
4798         if (i == 4)
4799                 DRM_ERROR("FDI train 2 fail!\n");
4800
4801         DRM_DEBUG_KMS("FDI train done.\n");
4802 }
4803
4804 /* Manual link training for Ivy Bridge A0 parts */
4805 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4806                                       const struct intel_crtc_state *crtc_state)
4807 {
4808         struct drm_device *dev = crtc->base.dev;
4809         struct drm_i915_private *dev_priv = to_i915(dev);
4810         enum pipe pipe = crtc->pipe;
4811         i915_reg_t reg;
4812         u32 temp, i, j;
4813
4814         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4815            for train result */
4816         reg = FDI_RX_IMR(pipe);
4817         temp = I915_READ(reg);
4818         temp &= ~FDI_RX_SYMBOL_LOCK;
4819         temp &= ~FDI_RX_BIT_LOCK;
4820         I915_WRITE(reg, temp);
4821
4822         POSTING_READ(reg);
4823         udelay(150);
4824
4825         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4826                       I915_READ(FDI_RX_IIR(pipe)));
4827
4828         /* Try each vswing and preemphasis setting twice before moving on */
4829         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4830                 /* disable first in case we need to retry */
4831                 reg = FDI_TX_CTL(pipe);
4832                 temp = I915_READ(reg);
4833                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4834                 temp &= ~FDI_TX_ENABLE;
4835                 I915_WRITE(reg, temp);
4836
4837                 reg = FDI_RX_CTL(pipe);
4838                 temp = I915_READ(reg);
4839                 temp &= ~FDI_LINK_TRAIN_AUTO;
4840                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4841                 temp &= ~FDI_RX_ENABLE;
4842                 I915_WRITE(reg, temp);
4843
4844                 /* enable CPU FDI TX and PCH FDI RX */
4845                 reg = FDI_TX_CTL(pipe);
4846                 temp = I915_READ(reg);
4847                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4848                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4849                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4850                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4851                 temp |= snb_b_fdi_train_param[j/2];
4852                 temp |= FDI_COMPOSITE_SYNC;
4853                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4854
4855                 I915_WRITE(FDI_RX_MISC(pipe),
4856                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4857
4858                 reg = FDI_RX_CTL(pipe);
4859                 temp = I915_READ(reg);
4860                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4861                 temp |= FDI_COMPOSITE_SYNC;
4862                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4863
4864                 POSTING_READ(reg);
4865                 udelay(1); /* should be 0.5us */
4866
4867                 for (i = 0; i < 4; i++) {
4868                         reg = FDI_RX_IIR(pipe);
4869                         temp = I915_READ(reg);
4870                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4871
4872                         if (temp & FDI_RX_BIT_LOCK ||
4873                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4874                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4875                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4876                                               i);
4877                                 break;
4878                         }
4879                         udelay(1); /* should be 0.5us */
4880                 }
4881                 if (i == 4) {
4882                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4883                         continue;
4884                 }
4885
4886                 /* Train 2 */
4887                 reg = FDI_TX_CTL(pipe);
4888                 temp = I915_READ(reg);
4889                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4890                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4891                 I915_WRITE(reg, temp);
4892
4893                 reg = FDI_RX_CTL(pipe);
4894                 temp = I915_READ(reg);
4895                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4896                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4897                 I915_WRITE(reg, temp);
4898
4899                 POSTING_READ(reg);
4900                 udelay(2); /* should be 1.5us */
4901
4902                 for (i = 0; i < 4; i++) {
4903                         reg = FDI_RX_IIR(pipe);
4904                         temp = I915_READ(reg);
4905                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4906
4907                         if (temp & FDI_RX_SYMBOL_LOCK ||
4908                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4909                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4910                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4911                                               i);
4912                                 goto train_done;
4913                         }
4914                         udelay(2); /* should be 1.5us */
4915                 }
4916                 if (i == 4)
4917                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4918         }
4919
4920 train_done:
4921         DRM_DEBUG_KMS("FDI train done.\n");
4922 }
4923
4924 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4925 {
4926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4927         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4928         enum pipe pipe = intel_crtc->pipe;
4929         i915_reg_t reg;
4930         u32 temp;
4931
4932         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4933         reg = FDI_RX_CTL(pipe);
4934         temp = I915_READ(reg);
4935         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4936         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4937         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4938         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4939
4940         POSTING_READ(reg);
4941         udelay(200);
4942
4943         /* Switch from Rawclk to PCDclk */
4944         temp = I915_READ(reg);
4945         I915_WRITE(reg, temp | FDI_PCDCLK);
4946
4947         POSTING_READ(reg);
4948         udelay(200);
4949
4950         /* Enable CPU FDI TX PLL, always on for Ironlake */
4951         reg = FDI_TX_CTL(pipe);
4952         temp = I915_READ(reg);
4953         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4954                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4955
4956                 POSTING_READ(reg);
4957                 udelay(100);
4958         }
4959 }
4960
4961 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4962 {
4963         struct drm_device *dev = intel_crtc->base.dev;
4964         struct drm_i915_private *dev_priv = to_i915(dev);
4965         enum pipe pipe = intel_crtc->pipe;
4966         i915_reg_t reg;
4967         u32 temp;
4968
4969         /* Switch from PCDclk to Rawclk */
4970         reg = FDI_RX_CTL(pipe);
4971         temp = I915_READ(reg);
4972         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4973
4974         /* Disable CPU FDI TX PLL */
4975         reg = FDI_TX_CTL(pipe);
4976         temp = I915_READ(reg);
4977         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4978
4979         POSTING_READ(reg);
4980         udelay(100);
4981
4982         reg = FDI_RX_CTL(pipe);
4983         temp = I915_READ(reg);
4984         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4985
4986         /* Wait for the clocks to turn off. */
4987         POSTING_READ(reg);
4988         udelay(100);
4989 }
4990
4991 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4992 {
4993         struct drm_device *dev = crtc->dev;
4994         struct drm_i915_private *dev_priv = to_i915(dev);
4995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4996         enum pipe pipe = intel_crtc->pipe;
4997         i915_reg_t reg;
4998         u32 temp;
4999
5000         /* disable CPU FDI tx and PCH FDI rx */
5001         reg = FDI_TX_CTL(pipe);
5002         temp = I915_READ(reg);
5003         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
5004         POSTING_READ(reg);
5005
5006         reg = FDI_RX_CTL(pipe);
5007         temp = I915_READ(reg);
5008         temp &= ~(0x7 << 16);
5009         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5010         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
5011
5012         POSTING_READ(reg);
5013         udelay(100);
5014
5015         /* Ironlake workaround, disable clock pointer after downing FDI */
5016         if (HAS_PCH_IBX(dev_priv))
5017                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
5018
5019         /* still set train pattern 1 */
5020         reg = FDI_TX_CTL(pipe);
5021         temp = I915_READ(reg);
5022         temp &= ~FDI_LINK_TRAIN_NONE;
5023         temp |= FDI_LINK_TRAIN_PATTERN_1;
5024         I915_WRITE(reg, temp);
5025
5026         reg = FDI_RX_CTL(pipe);
5027         temp = I915_READ(reg);
5028         if (HAS_PCH_CPT(dev_priv)) {
5029                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5030                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5031         } else {
5032                 temp &= ~FDI_LINK_TRAIN_NONE;
5033                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5034         }
5035         /* BPC in FDI rx is consistent with that in PIPECONF */
5036         temp &= ~(0x07 << 16);
5037         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5038         I915_WRITE(reg, temp);
5039
5040         POSTING_READ(reg);
5041         udelay(100);
5042 }
5043
5044 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5045 {
5046         struct drm_crtc *crtc;
5047         bool cleanup_done;
5048
5049         drm_for_each_crtc(crtc, &dev_priv->drm) {
5050                 struct drm_crtc_commit *commit;
5051                 spin_lock(&crtc->commit_lock);
5052                 commit = list_first_entry_or_null(&crtc->commit_list,
5053                                                   struct drm_crtc_commit, commit_entry);
5054                 cleanup_done = commit ?
5055                         try_wait_for_completion(&commit->cleanup_done) : true;
5056                 spin_unlock(&crtc->commit_lock);
5057
5058                 if (cleanup_done)
5059                         continue;
5060
5061                 drm_crtc_wait_one_vblank(crtc);
5062
5063                 return true;
5064         }
5065
5066         return false;
5067 }
5068
5069 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5070 {
5071         u32 temp;
5072
5073         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
5074
5075         mutex_lock(&dev_priv->sb_lock);
5076
5077         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5078         temp |= SBI_SSCCTL_DISABLE;
5079         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5080
5081         mutex_unlock(&dev_priv->sb_lock);
5082 }
5083
5084 /* Program iCLKIP clock to the desired frequency */
5085 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5086 {
5087         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5088         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5089         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5090         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5091         u32 temp;
5092
5093         lpt_disable_iclkip(dev_priv);
5094
5095         /* The iCLK virtual clock root frequency is in MHz,
5096          * but the adjusted_mode->crtc_clock in in KHz. To get the
5097          * divisors, it is necessary to divide one by another, so we
5098          * convert the virtual clock precision to KHz here for higher
5099          * precision.
5100          */
5101         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5102                 u32 iclk_virtual_root_freq = 172800 * 1000;
5103                 u32 iclk_pi_range = 64;
5104                 u32 desired_divisor;
5105
5106                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5107                                                     clock << auxdiv);
5108                 divsel = (desired_divisor / iclk_pi_range) - 2;
5109                 phaseinc = desired_divisor % iclk_pi_range;
5110
5111                 /*
5112                  * Near 20MHz is a corner case which is
5113                  * out of range for the 7-bit divisor
5114                  */
5115                 if (divsel <= 0x7f)
5116                         break;
5117         }
5118
5119         /* This should not happen with any sane values */
5120         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5121                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5122         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5123                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5124
5125         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5126                         clock,
5127                         auxdiv,
5128                         divsel,
5129                         phasedir,
5130                         phaseinc);
5131
5132         mutex_lock(&dev_priv->sb_lock);
5133
5134         /* Program SSCDIVINTPHASE6 */
5135         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5136         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5137         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5138         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5139         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5140         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5141         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5142         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5143
5144         /* Program SSCAUXDIV */
5145         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5146         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5147         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5148         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5149
5150         /* Enable modulator and associated divider */
5151         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5152         temp &= ~SBI_SSCCTL_DISABLE;
5153         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5154
5155         mutex_unlock(&dev_priv->sb_lock);
5156
5157         /* Wait for initialization time */
5158         udelay(24);
5159
5160         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5161 }
5162
5163 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5164 {
5165         u32 divsel, phaseinc, auxdiv;
5166         u32 iclk_virtual_root_freq = 172800 * 1000;
5167         u32 iclk_pi_range = 64;
5168         u32 desired_divisor;
5169         u32 temp;
5170
5171         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5172                 return 0;
5173
5174         mutex_lock(&dev_priv->sb_lock);
5175
5176         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5177         if (temp & SBI_SSCCTL_DISABLE) {
5178                 mutex_unlock(&dev_priv->sb_lock);
5179                 return 0;
5180         }
5181
5182         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5183         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5184                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5185         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5186                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5187
5188         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5189         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5190                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5191
5192         mutex_unlock(&dev_priv->sb_lock);
5193
5194         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5195
5196         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5197                                  desired_divisor << auxdiv);
5198 }
5199
5200 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5201                                                 enum pipe pch_transcoder)
5202 {
5203         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5204         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5205         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5206
5207         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5208                    I915_READ(HTOTAL(cpu_transcoder)));
5209         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5210                    I915_READ(HBLANK(cpu_transcoder)));
5211         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5212                    I915_READ(HSYNC(cpu_transcoder)));
5213
5214         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5215                    I915_READ(VTOTAL(cpu_transcoder)));
5216         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5217                    I915_READ(VBLANK(cpu_transcoder)));
5218         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5219                    I915_READ(VSYNC(cpu_transcoder)));
5220         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5221                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
5222 }
5223
5224 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5225 {
5226         u32 temp;
5227
5228         temp = I915_READ(SOUTH_CHICKEN1);
5229         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5230                 return;
5231
5232         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5233         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5234
5235         temp &= ~FDI_BC_BIFURCATION_SELECT;
5236         if (enable)
5237                 temp |= FDI_BC_BIFURCATION_SELECT;
5238
5239         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5240         I915_WRITE(SOUTH_CHICKEN1, temp);
5241         POSTING_READ(SOUTH_CHICKEN1);
5242 }
5243
5244 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5245 {
5246         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5247         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5248
5249         switch (crtc->pipe) {
5250         case PIPE_A:
5251                 break;
5252         case PIPE_B:
5253                 if (crtc_state->fdi_lanes > 2)
5254                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5255                 else
5256                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5257
5258                 break;
5259         case PIPE_C:
5260                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5261
5262                 break;
5263         default:
5264                 BUG();
5265         }
5266 }
5267
5268 /*
5269  * Finds the encoder associated with the given CRTC. This can only be
5270  * used when we know that the CRTC isn't feeding multiple encoders!
5271  */
5272 static struct intel_encoder *
5273 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5274                            const struct intel_crtc_state *crtc_state)
5275 {
5276         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5277         const struct drm_connector_state *connector_state;
5278         const struct drm_connector *connector;
5279         struct intel_encoder *encoder = NULL;
5280         int num_encoders = 0;
5281         int i;
5282
5283         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5284                 if (connector_state->crtc != &crtc->base)
5285                         continue;
5286
5287                 encoder = to_intel_encoder(connector_state->best_encoder);
5288                 num_encoders++;
5289         }
5290
5291         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5292              num_encoders, pipe_name(crtc->pipe));
5293
5294         return encoder;
5295 }
5296
5297 /*
5298  * Enable PCH resources required for PCH ports:
5299  *   - PCH PLLs
5300  *   - FDI training & RX/TX
5301  *   - update transcoder timings
5302  *   - DP transcoding bits
5303  *   - transcoder
5304  */
5305 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5306                                 const struct intel_crtc_state *crtc_state)
5307 {
5308         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5309         struct drm_device *dev = crtc->base.dev;
5310         struct drm_i915_private *dev_priv = to_i915(dev);
5311         enum pipe pipe = crtc->pipe;
5312         u32 temp;
5313
5314         assert_pch_transcoder_disabled(dev_priv, pipe);
5315
5316         if (IS_IVYBRIDGE(dev_priv))
5317                 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5318
5319         /* Write the TU size bits before fdi link training, so that error
5320          * detection works. */
5321         I915_WRITE(FDI_RX_TUSIZE1(pipe),
5322                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5323
5324         /* For PCH output, training FDI link */
5325         dev_priv->display.fdi_link_train(crtc, crtc_state);
5326
5327         /* We need to program the right clock selection before writing the pixel
5328          * mutliplier into the DPLL. */
5329         if (HAS_PCH_CPT(dev_priv)) {
5330                 u32 sel;
5331
5332                 temp = I915_READ(PCH_DPLL_SEL);
5333                 temp |= TRANS_DPLL_ENABLE(pipe);
5334                 sel = TRANS_DPLLB_SEL(pipe);
5335                 if (crtc_state->shared_dpll ==
5336                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5337                         temp |= sel;
5338                 else
5339                         temp &= ~sel;
5340                 I915_WRITE(PCH_DPLL_SEL, temp);
5341         }
5342
5343         /* XXX: pch pll's can be enabled any time before we enable the PCH
5344          * transcoder, and we actually should do this to not upset any PCH
5345          * transcoder that already use the clock when we share it.
5346          *
5347          * Note that enable_shared_dpll tries to do the right thing, but
5348          * get_shared_dpll unconditionally resets the pll - we need that to have
5349          * the right LVDS enable sequence. */
5350         intel_enable_shared_dpll(crtc_state);
5351
5352         /* set transcoder timing, panel must allow it */
5353         assert_panel_unlocked(dev_priv, pipe);
5354         ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5355
5356         intel_fdi_normal_train(crtc);
5357
5358         /* For PCH DP, enable TRANS_DP_CTL */
5359         if (HAS_PCH_CPT(dev_priv) &&
5360             intel_crtc_has_dp_encoder(crtc_state)) {
5361                 const struct drm_display_mode *adjusted_mode =
5362                         &crtc_state->hw.adjusted_mode;
5363                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5364                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5365                 enum port port;
5366
5367                 temp = I915_READ(reg);
5368                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5369                           TRANS_DP_SYNC_MASK |
5370                           TRANS_DP_BPC_MASK);
5371                 temp |= TRANS_DP_OUTPUT_ENABLE;
5372                 temp |= bpc << 9; /* same format but at 11:9 */
5373
5374                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5375                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5376                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5377                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5378
5379                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5380                 WARN_ON(port < PORT_B || port > PORT_D);
5381                 temp |= TRANS_DP_PORT_SEL(port);
5382
5383                 I915_WRITE(reg, temp);
5384         }
5385
5386         ironlake_enable_pch_transcoder(crtc_state);
5387 }
5388
5389 static void lpt_pch_enable(const struct intel_atomic_state *state,
5390                            const struct intel_crtc_state *crtc_state)
5391 {
5392         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5393         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5394         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5395
5396         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5397
5398         lpt_program_iclkip(crtc_state);
5399
5400         /* Set transcoder timing. */
5401         ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5402
5403         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5404 }
5405
5406 static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
5407 {
5408         struct drm_i915_private *dev_priv = to_i915(dev);
5409         i915_reg_t dslreg = PIPEDSL(pipe);
5410         u32 temp;
5411
5412         temp = I915_READ(dslreg);
5413         udelay(500);
5414         if (wait_for(I915_READ(dslreg) != temp, 5)) {
5415                 if (wait_for(I915_READ(dslreg) != temp, 5))
5416                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5417         }
5418 }
5419
5420 /*
5421  * The hardware phase 0.0 refers to the center of the pixel.
5422  * We want to start from the top/left edge which is phase
5423  * -0.5. That matches how the hardware calculates the scaling
5424  * factors (from top-left of the first pixel to bottom-right
5425  * of the last pixel, as opposed to the pixel centers).
5426  *
5427  * For 4:2:0 subsampled chroma planes we obviously have to
5428  * adjust that so that the chroma sample position lands in
5429  * the right spot.
5430  *
5431  * Note that for packed YCbCr 4:2:2 formats there is no way to
5432  * control chroma siting. The hardware simply replicates the
5433  * chroma samples for both of the luma samples, and thus we don't
5434  * actually get the expected MPEG2 chroma siting convention :(
5435  * The same behaviour is observed on pre-SKL platforms as well.
5436  *
5437  * Theory behind the formula (note that we ignore sub-pixel
5438  * source coordinates):
5439  * s = source sample position
5440  * d = destination sample position
5441  *
5442  * Downscaling 4:1:
5443  * -0.5
5444  * | 0.0
5445  * | |     1.5 (initial phase)
5446  * | |     |
5447  * v v     v
5448  * | s | s | s | s |
5449  * |       d       |
5450  *
5451  * Upscaling 1:4:
5452  * -0.5
5453  * | -0.375 (initial phase)
5454  * | |     0.0
5455  * | |     |
5456  * v v     v
5457  * |       s       |
5458  * | d | d | d | d |
5459  */
5460 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5461 {
5462         int phase = -0x8000;
5463         u16 trip = 0;
5464
5465         if (chroma_cosited)
5466                 phase += (sub - 1) * 0x8000 / sub;
5467
5468         phase += scale / (2 * sub);
5469
5470         /*
5471          * Hardware initial phase limited to [-0.5:1.5].
5472          * Since the max hardware scale factor is 3.0, we
5473          * should never actually excdeed 1.0 here.
5474          */
5475         WARN_ON(phase < -0x8000 || phase > 0x18000);
5476
5477         if (phase < 0)
5478                 phase = 0x10000 + phase;
5479         else
5480                 trip = PS_PHASE_TRIP;
5481
5482         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5483 }
5484
5485 #define SKL_MIN_SRC_W 8
5486 #define SKL_MAX_SRC_W 4096
5487 #define SKL_MIN_SRC_H 8
5488 #define SKL_MAX_SRC_H 4096
5489 #define SKL_MIN_DST_W 8
5490 #define SKL_MAX_DST_W 4096
5491 #define SKL_MIN_DST_H 8
5492 #define SKL_MAX_DST_H 4096
5493 #define ICL_MAX_SRC_W 5120
5494 #define ICL_MAX_SRC_H 4096
5495 #define ICL_MAX_DST_W 5120
5496 #define ICL_MAX_DST_H 4096
5497 #define SKL_MIN_YUV_420_SRC_W 16
5498 #define SKL_MIN_YUV_420_SRC_H 16
5499
5500 static int
5501 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5502                   unsigned int scaler_user, int *scaler_id,
5503                   int src_w, int src_h, int dst_w, int dst_h,
5504                   const struct drm_format_info *format, bool need_scaler)
5505 {
5506         struct intel_crtc_scaler_state *scaler_state =
5507                 &crtc_state->scaler_state;
5508         struct intel_crtc *intel_crtc =
5509                 to_intel_crtc(crtc_state->uapi.crtc);
5510         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5511         const struct drm_display_mode *adjusted_mode =
5512                 &crtc_state->hw.adjusted_mode;
5513
5514         /*
5515          * Src coordinates are already rotated by 270 degrees for
5516          * the 90/270 degree plane rotation cases (to match the
5517          * GTT mapping), hence no need to account for rotation here.
5518          */
5519         if (src_w != dst_w || src_h != dst_h)
5520                 need_scaler = true;
5521
5522         /*
5523          * Scaling/fitting not supported in IF-ID mode in GEN9+
5524          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5525          * Once NV12 is enabled, handle it here while allocating scaler
5526          * for NV12.
5527          */
5528         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
5529             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5530                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5531                 return -EINVAL;
5532         }
5533
5534         /*
5535          * if plane is being disabled or scaler is no more required or force detach
5536          *  - free scaler binded to this plane/crtc
5537          *  - in order to do this, update crtc->scaler_usage
5538          *
5539          * Here scaler state in crtc_state is set free so that
5540          * scaler can be assigned to other user. Actual register
5541          * update to free the scaler is done in plane/panel-fit programming.
5542          * For this purpose crtc/plane_state->scaler_id isn't reset here.
5543          */
5544         if (force_detach || !need_scaler) {
5545                 if (*scaler_id >= 0) {
5546                         scaler_state->scaler_users &= ~(1 << scaler_user);
5547                         scaler_state->scalers[*scaler_id].in_use = 0;
5548
5549                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5550                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5551                                 intel_crtc->pipe, scaler_user, *scaler_id,
5552                                 scaler_state->scaler_users);
5553                         *scaler_id = -1;
5554                 }
5555                 return 0;
5556         }
5557
5558         if (format && drm_format_info_is_yuv_semiplanar(format) &&
5559             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5560                 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5561                 return -EINVAL;
5562         }
5563
5564         /* range checks */
5565         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5566             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5567             (INTEL_GEN(dev_priv) >= 11 &&
5568              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5569               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5570             (INTEL_GEN(dev_priv) < 11 &&
5571              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5572               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5573                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5574                         "size is out of scaler range\n",
5575                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5576                 return -EINVAL;
5577         }
5578
5579         /* mark this plane as a scaler user in crtc_state */
5580         scaler_state->scaler_users |= (1 << scaler_user);
5581         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5582                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5583                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5584                 scaler_state->scaler_users);
5585
5586         return 0;
5587 }
5588
5589 /**
5590  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5591  *
5592  * @state: crtc's scaler state
5593  *
5594  * Return
5595  *     0 - scaler_usage updated successfully
5596  *    error - requested scaling cannot be supported or other error condition
5597  */
5598 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5599 {
5600         const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
5601         bool need_scaler = false;
5602
5603         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5604                 need_scaler = true;
5605
5606         return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
5607                                  &state->scaler_state.scaler_id,
5608                                  state->pipe_src_w, state->pipe_src_h,
5609                                  adjusted_mode->crtc_hdisplay,
5610                                  adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5611 }
5612
5613 /**
5614  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5615  * @crtc_state: crtc's scaler state
5616  * @plane_state: atomic plane state to update
5617  *
5618  * Return
5619  *     0 - scaler_usage updated successfully
5620  *    error - requested scaling cannot be supported or other error condition
5621  */
5622 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5623                                    struct intel_plane_state *plane_state)
5624 {
5625         struct intel_plane *intel_plane =
5626                 to_intel_plane(plane_state->uapi.plane);
5627         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5628         struct drm_framebuffer *fb = plane_state->hw.fb;
5629         int ret;
5630         bool force_detach = !fb || !plane_state->uapi.visible;
5631         bool need_scaler = false;
5632
5633         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5634         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5635             fb && drm_format_info_is_yuv_semiplanar(fb->format))
5636                 need_scaler = true;
5637
5638         ret = skl_update_scaler(crtc_state, force_detach,
5639                                 drm_plane_index(&intel_plane->base),
5640                                 &plane_state->scaler_id,
5641                                 drm_rect_width(&plane_state->uapi.src) >> 16,
5642                                 drm_rect_height(&plane_state->uapi.src) >> 16,
5643                                 drm_rect_width(&plane_state->uapi.dst),
5644                                 drm_rect_height(&plane_state->uapi.dst),
5645                                 fb ? fb->format : NULL, need_scaler);
5646
5647         if (ret || plane_state->scaler_id < 0)
5648                 return ret;
5649
5650         /* check colorkey */
5651         if (plane_state->ckey.flags) {
5652                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5653                               intel_plane->base.base.id,
5654                               intel_plane->base.name);
5655                 return -EINVAL;
5656         }
5657
5658         /* Check src format */
5659         switch (fb->format->format) {
5660         case DRM_FORMAT_RGB565:
5661         case DRM_FORMAT_XBGR8888:
5662         case DRM_FORMAT_XRGB8888:
5663         case DRM_FORMAT_ABGR8888:
5664         case DRM_FORMAT_ARGB8888:
5665         case DRM_FORMAT_XRGB2101010:
5666         case DRM_FORMAT_XBGR2101010:
5667         case DRM_FORMAT_YUYV:
5668         case DRM_FORMAT_YVYU:
5669         case DRM_FORMAT_UYVY:
5670         case DRM_FORMAT_VYUY:
5671         case DRM_FORMAT_NV12:
5672         case DRM_FORMAT_P010:
5673         case DRM_FORMAT_P012:
5674         case DRM_FORMAT_P016:
5675         case DRM_FORMAT_Y210:
5676         case DRM_FORMAT_Y212:
5677         case DRM_FORMAT_Y216:
5678         case DRM_FORMAT_XVYU2101010:
5679         case DRM_FORMAT_XVYU12_16161616:
5680         case DRM_FORMAT_XVYU16161616:
5681                 break;
5682         case DRM_FORMAT_XBGR16161616F:
5683         case DRM_FORMAT_ABGR16161616F:
5684         case DRM_FORMAT_XRGB16161616F:
5685         case DRM_FORMAT_ARGB16161616F:
5686                 if (INTEL_GEN(dev_priv) >= 11)
5687                         break;
5688                 /* fall through */
5689         default:
5690                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5691                               intel_plane->base.base.id, intel_plane->base.name,
5692                               fb->base.id, fb->format->format);
5693                 return -EINVAL;
5694         }
5695
5696         return 0;
5697 }
5698
5699 static void skylake_scaler_disable(struct intel_crtc *crtc)
5700 {
5701         int i;
5702
5703         for (i = 0; i < crtc->num_scalers; i++)
5704                 skl_detach_scaler(crtc, i);
5705 }
5706
5707 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5708 {
5709         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5710         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5711         enum pipe pipe = crtc->pipe;
5712         const struct intel_crtc_scaler_state *scaler_state =
5713                 &crtc_state->scaler_state;
5714
5715         if (crtc_state->pch_pfit.enabled) {
5716                 u16 uv_rgb_hphase, uv_rgb_vphase;
5717                 int pfit_w, pfit_h, hscale, vscale;
5718                 int id;
5719
5720                 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5721                         return;
5722
5723                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5724                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5725
5726                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5727                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5728
5729                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5730                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5731
5732                 id = scaler_state->scaler_id;
5733                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5734                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5735                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5736                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5737                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5738                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5739                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5740                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5741         }
5742 }
5743
5744 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5745 {
5746         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5747         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5748         enum pipe pipe = crtc->pipe;
5749
5750         if (crtc_state->pch_pfit.enabled) {
5751                 /* Force use of hard-coded filter coefficients
5752                  * as some pre-programmed values are broken,
5753                  * e.g. x201.
5754                  */
5755                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5756                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5757                                                  PF_PIPE_SEL_IVB(pipe));
5758                 else
5759                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5760                 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5761                 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5762         }
5763 }
5764
5765 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5766 {
5767         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5768         struct drm_device *dev = crtc->base.dev;
5769         struct drm_i915_private *dev_priv = to_i915(dev);
5770
5771         if (!crtc_state->ips_enabled)
5772                 return;
5773
5774         /*
5775          * We can only enable IPS after we enable a plane and wait for a vblank
5776          * This function is called from post_plane_update, which is run after
5777          * a vblank wait.
5778          */
5779         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5780
5781         if (IS_BROADWELL(dev_priv)) {
5782                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5783                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5784                 /* Quoting Art Runyan: "its not safe to expect any particular
5785                  * value in IPS_CTL bit 31 after enabling IPS through the
5786                  * mailbox." Moreover, the mailbox may return a bogus state,
5787                  * so we need to just enable it and continue on.
5788                  */
5789         } else {
5790                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5791                 /* The bit only becomes 1 in the next vblank, so this wait here
5792                  * is essentially intel_wait_for_vblank. If we don't have this
5793                  * and don't wait for vblanks until the end of crtc_enable, then
5794                  * the HW state readout code will complain that the expected
5795                  * IPS_CTL value is not the one we read. */
5796                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5797                         DRM_ERROR("Timed out waiting for IPS enable\n");
5798         }
5799 }
5800
5801 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5802 {
5803         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5804         struct drm_device *dev = crtc->base.dev;
5805         struct drm_i915_private *dev_priv = to_i915(dev);
5806
5807         if (!crtc_state->ips_enabled)
5808                 return;
5809
5810         if (IS_BROADWELL(dev_priv)) {
5811                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5812                 /*
5813                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5814                  * 42ms timeout value leads to occasional timeouts so use 100ms
5815                  * instead.
5816                  */
5817                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5818                         DRM_ERROR("Timed out waiting for IPS disable\n");
5819         } else {
5820                 I915_WRITE(IPS_CTL, 0);
5821                 POSTING_READ(IPS_CTL);
5822         }
5823
5824         /* We need to wait for a vblank before we can disable the plane. */
5825         intel_wait_for_vblank(dev_priv, crtc->pipe);
5826 }
5827
5828 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5829 {
5830         if (intel_crtc->overlay)
5831                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5832
5833         /* Let userspace switch the overlay on again. In most cases userspace
5834          * has to recompute where to put it anyway.
5835          */
5836 }
5837
5838 /**
5839  * intel_post_enable_primary - Perform operations after enabling primary plane
5840  * @crtc: the CRTC whose primary plane was just enabled
5841  * @new_crtc_state: the enabling state
5842  *
5843  * Performs potentially sleeping operations that must be done after the primary
5844  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5845  * called due to an explicit primary plane update, or due to an implicit
5846  * re-enable that is caused when a sprite plane is updated to no longer
5847  * completely hide the primary plane.
5848  */
5849 static void
5850 intel_post_enable_primary(struct drm_crtc *crtc,
5851                           const struct intel_crtc_state *new_crtc_state)
5852 {
5853         struct drm_device *dev = crtc->dev;
5854         struct drm_i915_private *dev_priv = to_i915(dev);
5855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5856         enum pipe pipe = intel_crtc->pipe;
5857
5858         /*
5859          * Gen2 reports pipe underruns whenever all planes are disabled.
5860          * So don't enable underrun reporting before at least some planes
5861          * are enabled.
5862          * FIXME: Need to fix the logic to work when we turn off all planes
5863          * but leave the pipe running.
5864          */
5865         if (IS_GEN(dev_priv, 2))
5866                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5867
5868         /* Underruns don't always raise interrupts, so check manually. */
5869         intel_check_cpu_fifo_underruns(dev_priv);
5870         intel_check_pch_fifo_underruns(dev_priv);
5871 }
5872
5873 /* FIXME get rid of this and use pre_plane_update */
5874 static void
5875 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5876 {
5877         struct drm_device *dev = crtc->dev;
5878         struct drm_i915_private *dev_priv = to_i915(dev);
5879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5880         enum pipe pipe = intel_crtc->pipe;
5881
5882         /*
5883          * Gen2 reports pipe underruns whenever all planes are disabled.
5884          * So disable underrun reporting before all the planes get disabled.
5885          */
5886         if (IS_GEN(dev_priv, 2))
5887                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5888
5889         hsw_disable_ips(to_intel_crtc_state(crtc->state));
5890
5891         /*
5892          * Vblank time updates from the shadow to live plane control register
5893          * are blocked if the memory self-refresh mode is active at that
5894          * moment. So to make sure the plane gets truly disabled, disable
5895          * first the self-refresh mode. The self-refresh enable bit in turn
5896          * will be checked/applied by the HW only at the next frame start
5897          * event which is after the vblank start event, so we need to have a
5898          * wait-for-vblank between disabling the plane and the pipe.
5899          */
5900         if (HAS_GMCH(dev_priv) &&
5901             intel_set_memory_cxsr(dev_priv, false))
5902                 intel_wait_for_vblank(dev_priv, pipe);
5903 }
5904
5905 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5906                                        const struct intel_crtc_state *new_crtc_state)
5907 {
5908         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5909         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5910
5911         if (!old_crtc_state->ips_enabled)
5912                 return false;
5913
5914         if (needs_modeset(new_crtc_state))
5915                 return true;
5916
5917         /*
5918          * Workaround : Do not read or write the pipe palette/gamma data while
5919          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5920          *
5921          * Disable IPS before we program the LUT.
5922          */
5923         if (IS_HASWELL(dev_priv) &&
5924             (new_crtc_state->uapi.color_mgmt_changed ||
5925              new_crtc_state->update_pipe) &&
5926             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5927                 return true;
5928
5929         return !new_crtc_state->ips_enabled;
5930 }
5931
5932 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5933                                        const struct intel_crtc_state *new_crtc_state)
5934 {
5935         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5936         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5937
5938         if (!new_crtc_state->ips_enabled)
5939                 return false;
5940
5941         if (needs_modeset(new_crtc_state))
5942                 return true;
5943
5944         /*
5945          * Workaround : Do not read or write the pipe palette/gamma data while
5946          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5947          *
5948          * Re-enable IPS after the LUT has been programmed.
5949          */
5950         if (IS_HASWELL(dev_priv) &&
5951             (new_crtc_state->uapi.color_mgmt_changed ||
5952              new_crtc_state->update_pipe) &&
5953             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5954                 return true;
5955
5956         /*
5957          * We can't read out IPS on broadwell, assume the worst and
5958          * forcibly enable IPS on the first fastset.
5959          */
5960         if (new_crtc_state->update_pipe &&
5961             old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5962                 return true;
5963
5964         return !old_crtc_state->ips_enabled;
5965 }
5966
5967 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5968                           const struct intel_crtc_state *crtc_state)
5969 {
5970         if (!crtc_state->nv12_planes)
5971                 return false;
5972
5973         /* WA Display #0827: Gen9:all */
5974         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5975                 return true;
5976
5977         return false;
5978 }
5979
5980 static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
5981                                const struct intel_crtc_state *crtc_state)
5982 {
5983         /* Wa_2006604312:icl */
5984         if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
5985                 return true;
5986
5987         return false;
5988 }
5989
5990 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5991 {
5992         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
5993         struct drm_device *dev = crtc->base.dev;
5994         struct drm_i915_private *dev_priv = to_i915(dev);
5995         struct drm_atomic_state *state = old_crtc_state->uapi.state;
5996         struct intel_crtc_state *pipe_config =
5997                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
5998                                                 crtc);
5999         struct drm_plane *primary = crtc->base.primary;
6000         struct drm_plane_state *old_primary_state =
6001                 drm_atomic_get_old_plane_state(state, primary);
6002
6003         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
6004
6005         if (pipe_config->update_wm_post && pipe_config->hw.active)
6006                 intel_update_watermarks(crtc);
6007
6008         if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
6009                 hsw_enable_ips(pipe_config);
6010
6011         if (old_primary_state) {
6012                 struct drm_plane_state *new_primary_state =
6013                         drm_atomic_get_new_plane_state(state, primary);
6014
6015                 intel_fbc_post_update(crtc);
6016
6017                 if (new_primary_state->visible &&
6018                     (needs_modeset(pipe_config) ||
6019                      !old_primary_state->visible))
6020                         intel_post_enable_primary(&crtc->base, pipe_config);
6021         }
6022
6023         if (needs_nv12_wa(dev_priv, old_crtc_state) &&
6024             !needs_nv12_wa(dev_priv, pipe_config))
6025                 skl_wa_827(dev_priv, crtc->pipe, false);
6026
6027         if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
6028             !needs_scalerclk_wa(dev_priv, pipe_config))
6029                 icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
6030 }
6031
6032 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
6033                                    struct intel_crtc_state *pipe_config)
6034 {
6035         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6036         struct drm_device *dev = crtc->base.dev;
6037         struct drm_i915_private *dev_priv = to_i915(dev);
6038         struct drm_atomic_state *state = old_crtc_state->uapi.state;
6039         struct drm_plane *primary = crtc->base.primary;
6040         struct drm_plane_state *old_primary_state =
6041                 drm_atomic_get_old_plane_state(state, primary);
6042         bool modeset = needs_modeset(pipe_config);
6043         struct intel_atomic_state *intel_state =
6044                 to_intel_atomic_state(state);
6045
6046         if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
6047                 hsw_disable_ips(old_crtc_state);
6048
6049         if (old_primary_state) {
6050                 struct intel_plane_state *new_primary_state =
6051                         intel_atomic_get_new_plane_state(intel_state,
6052                                                          to_intel_plane(primary));
6053
6054                 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
6055                 /*
6056                  * Gen2 reports pipe underruns whenever all planes are disabled.
6057                  * So disable underrun reporting before all the planes get disabled.
6058                  */
6059                 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
6060                     (modeset || !new_primary_state->uapi.visible))
6061                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
6062         }
6063
6064         /* Display WA 827 */
6065         if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
6066             needs_nv12_wa(dev_priv, pipe_config))
6067                 skl_wa_827(dev_priv, crtc->pipe, true);
6068
6069         /* Wa_2006604312:icl */
6070         if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
6071             needs_scalerclk_wa(dev_priv, pipe_config))
6072                 icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
6073
6074         /*
6075          * Vblank time updates from the shadow to live plane control register
6076          * are blocked if the memory self-refresh mode is active at that
6077          * moment. So to make sure the plane gets truly disabled, disable
6078          * first the self-refresh mode. The self-refresh enable bit in turn
6079          * will be checked/applied by the HW only at the next frame start
6080          * event which is after the vblank start event, so we need to have a
6081          * wait-for-vblank between disabling the plane and the pipe.
6082          */
6083         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6084             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6085                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6086
6087         /*
6088          * IVB workaround: must disable low power watermarks for at least
6089          * one frame before enabling scaling.  LP watermarks can be re-enabled
6090          * when scaling is disabled.
6091          *
6092          * WaCxSRDisabledForSpriteScaling:ivb
6093          */
6094         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
6095             old_crtc_state->hw.active)
6096                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6097
6098         /*
6099          * If we're doing a modeset, we're done.  No need to do any pre-vblank
6100          * watermark programming here.
6101          */
6102         if (needs_modeset(pipe_config))
6103                 return;
6104
6105         /*
6106          * For platforms that support atomic watermarks, program the
6107          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6108          * will be the intermediate values that are safe for both pre- and
6109          * post- vblank; when vblank happens, the 'active' values will be set
6110          * to the final 'target' values and we'll do this again to get the
6111          * optimal watermarks.  For gen9+ platforms, the values we program here
6112          * will be the final target values which will get automatically latched
6113          * at vblank time; no further programming will be necessary.
6114          *
6115          * If a platform hasn't been transitioned to atomic watermarks yet,
6116          * we'll continue to update watermarks the old way, if flags tell
6117          * us to.
6118          */
6119         if (dev_priv->display.initial_watermarks != NULL)
6120                 dev_priv->display.initial_watermarks(intel_state,
6121                                                      pipe_config);
6122         else if (pipe_config->update_wm_pre)
6123                 intel_update_watermarks(crtc);
6124 }
6125
6126 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6127                                       struct intel_crtc *crtc)
6128 {
6129         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6130         const struct intel_crtc_state *new_crtc_state =
6131                 intel_atomic_get_new_crtc_state(state, crtc);
6132         unsigned int update_mask = new_crtc_state->update_planes;
6133         const struct intel_plane_state *old_plane_state;
6134         struct intel_plane *plane;
6135         unsigned fb_bits = 0;
6136         int i;
6137
6138         intel_crtc_dpms_overlay_disable(crtc);
6139
6140         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6141                 if (crtc->pipe != plane->pipe ||
6142                     !(update_mask & BIT(plane->id)))
6143                         continue;
6144
6145                 intel_disable_plane(plane, new_crtc_state);
6146
6147                 if (old_plane_state->uapi.visible)
6148                         fb_bits |= plane->frontbuffer_bit;
6149         }
6150
6151         intel_frontbuffer_flip(dev_priv, fb_bits);
6152 }
6153
6154 /*
6155  * intel_connector_primary_encoder - get the primary encoder for a connector
6156  * @connector: connector for which to return the encoder
6157  *
6158  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6159  * all connectors to their encoder, except for DP-MST connectors which have
6160  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6161  * pointed to by as many DP-MST connectors as there are pipes.
6162  */
6163 static struct intel_encoder *
6164 intel_connector_primary_encoder(struct intel_connector *connector)
6165 {
6166         struct intel_encoder *encoder;
6167
6168         if (connector->mst_port)
6169                 return &dp_to_dig_port(connector->mst_port)->base;
6170
6171         encoder = intel_attached_encoder(&connector->base);
6172         WARN_ON(!encoder);
6173
6174         return encoder;
6175 }
6176
6177 static bool
6178 intel_connector_needs_modeset(struct intel_atomic_state *state,
6179                               const struct drm_connector_state *old_conn_state,
6180                               const struct drm_connector_state *new_conn_state)
6181 {
6182         struct intel_crtc *old_crtc = old_conn_state->crtc ?
6183                                       to_intel_crtc(old_conn_state->crtc) : NULL;
6184         struct intel_crtc *new_crtc = new_conn_state->crtc ?
6185                                       to_intel_crtc(new_conn_state->crtc) : NULL;
6186
6187         return new_crtc != old_crtc ||
6188                (new_crtc &&
6189                 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6190 }
6191
6192 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6193 {
6194         struct drm_connector_state *old_conn_state;
6195         struct drm_connector_state *new_conn_state;
6196         struct drm_connector *conn;
6197         int i;
6198
6199         for_each_oldnew_connector_in_state(&state->base, conn,
6200                                            old_conn_state, new_conn_state, i) {
6201                 struct intel_encoder *encoder;
6202                 struct intel_crtc *crtc;
6203
6204                 if (!intel_connector_needs_modeset(state,
6205                                                    old_conn_state,
6206                                                    new_conn_state))
6207                         continue;
6208
6209                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6210                 if (!encoder->update_prepare)
6211                         continue;
6212
6213                 crtc = new_conn_state->crtc ?
6214                         to_intel_crtc(new_conn_state->crtc) : NULL;
6215                 encoder->update_prepare(state, encoder, crtc);
6216         }
6217 }
6218
6219 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6220 {
6221         struct drm_connector_state *old_conn_state;
6222         struct drm_connector_state *new_conn_state;
6223         struct drm_connector *conn;
6224         int i;
6225
6226         for_each_oldnew_connector_in_state(&state->base, conn,
6227                                            old_conn_state, new_conn_state, i) {
6228                 struct intel_encoder *encoder;
6229                 struct intel_crtc *crtc;
6230
6231                 if (!intel_connector_needs_modeset(state,
6232                                                    old_conn_state,
6233                                                    new_conn_state))
6234                         continue;
6235
6236                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6237                 if (!encoder->update_complete)
6238                         continue;
6239
6240                 crtc = new_conn_state->crtc ?
6241                         to_intel_crtc(new_conn_state->crtc) : NULL;
6242                 encoder->update_complete(state, encoder, crtc);
6243         }
6244 }
6245
6246 static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
6247                                           struct intel_crtc_state *crtc_state,
6248                                           struct intel_atomic_state *state)
6249 {
6250         struct drm_connector_state *conn_state;
6251         struct drm_connector *conn;
6252         int i;
6253
6254         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6255                 struct intel_encoder *encoder =
6256                         to_intel_encoder(conn_state->best_encoder);
6257
6258                 if (conn_state->crtc != &crtc->base)
6259                         continue;
6260
6261                 if (encoder->pre_pll_enable)
6262                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6263         }
6264 }
6265
6266 static void intel_encoders_pre_enable(struct intel_crtc *crtc,
6267                                       struct intel_crtc_state *crtc_state,
6268                                       struct intel_atomic_state *state)
6269 {
6270         struct drm_connector_state *conn_state;
6271         struct drm_connector *conn;
6272         int i;
6273
6274         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6275                 struct intel_encoder *encoder =
6276                         to_intel_encoder(conn_state->best_encoder);
6277
6278                 if (conn_state->crtc != &crtc->base)
6279                         continue;
6280
6281                 if (encoder->pre_enable)
6282                         encoder->pre_enable(encoder, crtc_state, conn_state);
6283         }
6284 }
6285
6286 static void intel_encoders_enable(struct intel_crtc *crtc,
6287                                   struct intel_crtc_state *crtc_state,
6288                                   struct intel_atomic_state *state)
6289 {
6290         struct drm_connector_state *conn_state;
6291         struct drm_connector *conn;
6292         int i;
6293
6294         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6295                 struct intel_encoder *encoder =
6296                         to_intel_encoder(conn_state->best_encoder);
6297
6298                 if (conn_state->crtc != &crtc->base)
6299                         continue;
6300
6301                 if (encoder->enable)
6302                         encoder->enable(encoder, crtc_state, conn_state);
6303                 intel_opregion_notify_encoder(encoder, true);
6304         }
6305 }
6306
6307 static void intel_encoders_disable(struct intel_crtc *crtc,
6308                                    struct intel_crtc_state *old_crtc_state,
6309                                    struct intel_atomic_state *state)
6310 {
6311         struct drm_connector_state *old_conn_state;
6312         struct drm_connector *conn;
6313         int i;
6314
6315         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6316                 struct intel_encoder *encoder =
6317                         to_intel_encoder(old_conn_state->best_encoder);
6318
6319                 if (old_conn_state->crtc != &crtc->base)
6320                         continue;
6321
6322                 intel_opregion_notify_encoder(encoder, false);
6323                 if (encoder->disable)
6324                         encoder->disable(encoder, old_crtc_state, old_conn_state);
6325         }
6326 }
6327
6328 static void intel_encoders_post_disable(struct intel_crtc *crtc,
6329                                         struct intel_crtc_state *old_crtc_state,
6330                                         struct intel_atomic_state *state)
6331 {
6332         struct drm_connector_state *old_conn_state;
6333         struct drm_connector *conn;
6334         int i;
6335
6336         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6337                 struct intel_encoder *encoder =
6338                         to_intel_encoder(old_conn_state->best_encoder);
6339
6340                 if (old_conn_state->crtc != &crtc->base)
6341                         continue;
6342
6343                 if (encoder->post_disable)
6344                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6345         }
6346 }
6347
6348 static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
6349                                             struct intel_crtc_state *old_crtc_state,
6350                                             struct intel_atomic_state *state)
6351 {
6352         struct drm_connector_state *old_conn_state;
6353         struct drm_connector *conn;
6354         int i;
6355
6356         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6357                 struct intel_encoder *encoder =
6358                         to_intel_encoder(old_conn_state->best_encoder);
6359
6360                 if (old_conn_state->crtc != &crtc->base)
6361                         continue;
6362
6363                 if (encoder->post_pll_disable)
6364                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6365         }
6366 }
6367
6368 static void intel_encoders_update_pipe(struct intel_crtc *crtc,
6369                                        struct intel_crtc_state *crtc_state,
6370                                        struct intel_atomic_state *state)
6371 {
6372         struct drm_connector_state *conn_state;
6373         struct drm_connector *conn;
6374         int i;
6375
6376         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6377                 struct intel_encoder *encoder =
6378                         to_intel_encoder(conn_state->best_encoder);
6379
6380                 if (conn_state->crtc != &crtc->base)
6381                         continue;
6382
6383                 if (encoder->update_pipe)
6384                         encoder->update_pipe(encoder, crtc_state, conn_state);
6385         }
6386 }
6387
6388 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6389 {
6390         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6391         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6392
6393         plane->disable_plane(plane, crtc_state);
6394 }
6395
6396 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
6397                                  struct intel_atomic_state *state)
6398 {
6399         struct drm_crtc *crtc = pipe_config->uapi.crtc;
6400         struct drm_device *dev = crtc->dev;
6401         struct drm_i915_private *dev_priv = to_i915(dev);
6402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6403         enum pipe pipe = intel_crtc->pipe;
6404
6405         if (WARN_ON(intel_crtc->active))
6406                 return;
6407
6408         /*
6409          * Sometimes spurious CPU pipe underruns happen during FDI
6410          * training, at least with VGA+HDMI cloning. Suppress them.
6411          *
6412          * On ILK we get an occasional spurious CPU pipe underruns
6413          * between eDP port A enable and vdd enable. Also PCH port
6414          * enable seems to result in the occasional CPU pipe underrun.
6415          *
6416          * Spurious PCH underruns also occur during PCH enabling.
6417          */
6418         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6419         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6420
6421         if (pipe_config->has_pch_encoder)
6422                 intel_prepare_shared_dpll(pipe_config);
6423
6424         if (intel_crtc_has_dp_encoder(pipe_config))
6425                 intel_dp_set_m_n(pipe_config, M1_N1);
6426
6427         intel_set_pipe_timings(pipe_config);
6428         intel_set_pipe_src_size(pipe_config);
6429
6430         if (pipe_config->has_pch_encoder) {
6431                 intel_cpu_transcoder_set_m_n(pipe_config,
6432                                              &pipe_config->fdi_m_n, NULL);
6433         }
6434
6435         ironlake_set_pipeconf(pipe_config);
6436
6437         intel_crtc->active = true;
6438
6439         intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6440
6441         if (pipe_config->has_pch_encoder) {
6442                 /* Note: FDI PLL enabling _must_ be done before we enable the
6443                  * cpu pipes, hence this is separate from all the other fdi/pch
6444                  * enabling. */
6445                 ironlake_fdi_pll_enable(pipe_config);
6446         } else {
6447                 assert_fdi_tx_disabled(dev_priv, pipe);
6448                 assert_fdi_rx_disabled(dev_priv, pipe);
6449         }
6450
6451         ironlake_pfit_enable(pipe_config);
6452
6453         /*
6454          * On ILK+ LUT must be loaded before the pipe is running but with
6455          * clocks enabled
6456          */
6457         intel_color_load_luts(pipe_config);
6458         intel_color_commit(pipe_config);
6459         /* update DSPCNTR to configure gamma for pipe bottom color */
6460         intel_disable_primary_plane(pipe_config);
6461
6462         if (dev_priv->display.initial_watermarks != NULL)
6463                 dev_priv->display.initial_watermarks(state, pipe_config);
6464         intel_enable_pipe(pipe_config);
6465
6466         if (pipe_config->has_pch_encoder)
6467                 ironlake_pch_enable(state, pipe_config);
6468
6469         assert_vblank_disabled(crtc);
6470         intel_crtc_vblank_on(pipe_config);
6471
6472         intel_encoders_enable(intel_crtc, pipe_config, state);
6473
6474         if (HAS_PCH_CPT(dev_priv))
6475                 cpt_verify_modeset(dev, intel_crtc->pipe);
6476
6477         /*
6478          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6479          * And a second vblank wait is needed at least on ILK with
6480          * some interlaced HDMI modes. Let's do the double wait always
6481          * in case there are more corner cases we don't know about.
6482          */
6483         if (pipe_config->has_pch_encoder) {
6484                 intel_wait_for_vblank(dev_priv, pipe);
6485                 intel_wait_for_vblank(dev_priv, pipe);
6486         }
6487         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6488         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6489 }
6490
6491 /* IPS only exists on ULT machines and is tied to pipe A. */
6492 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6493 {
6494         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6495 }
6496
6497 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6498                                             enum pipe pipe, bool apply)
6499 {
6500         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6501         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6502
6503         if (apply)
6504                 val |= mask;
6505         else
6506                 val &= ~mask;
6507
6508         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6509 }
6510
6511 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6512 {
6513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6514         enum pipe pipe = crtc->pipe;
6515         u32 val;
6516
6517         val = MBUS_DBOX_A_CREDIT(2);
6518
6519         if (INTEL_GEN(dev_priv) >= 12) {
6520                 val |= MBUS_DBOX_BW_CREDIT(2);
6521                 val |= MBUS_DBOX_B_CREDIT(12);
6522         } else {
6523                 val |= MBUS_DBOX_BW_CREDIT(1);
6524                 val |= MBUS_DBOX_B_CREDIT(8);
6525         }
6526
6527         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6528 }
6529
6530 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
6531                                 struct intel_atomic_state *state)
6532 {
6533         struct drm_crtc *crtc = pipe_config->uapi.crtc;
6534         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6536         enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
6537         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6538         bool psl_clkgate_wa;
6539
6540         if (WARN_ON(intel_crtc->active))
6541                 return;
6542
6543         intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
6544
6545         if (pipe_config->shared_dpll)
6546                 intel_enable_shared_dpll(pipe_config);
6547
6548         intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6549
6550         if (intel_crtc_has_dp_encoder(pipe_config))
6551                 intel_dp_set_m_n(pipe_config, M1_N1);
6552
6553         if (!transcoder_is_dsi(cpu_transcoder))
6554                 intel_set_pipe_timings(pipe_config);
6555
6556         if (INTEL_GEN(dev_priv) >= 11)
6557                 icl_enable_trans_port_sync(pipe_config);
6558
6559         intel_set_pipe_src_size(pipe_config);
6560
6561         if (cpu_transcoder != TRANSCODER_EDP &&
6562             !transcoder_is_dsi(cpu_transcoder)) {
6563                 I915_WRITE(PIPE_MULT(cpu_transcoder),
6564                            pipe_config->pixel_multiplier - 1);
6565         }
6566
6567         if (pipe_config->has_pch_encoder) {
6568                 intel_cpu_transcoder_set_m_n(pipe_config,
6569                                              &pipe_config->fdi_m_n, NULL);
6570         }
6571
6572         if (!transcoder_is_dsi(cpu_transcoder))
6573                 haswell_set_pipeconf(pipe_config);
6574
6575         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6576                 bdw_set_pipemisc(pipe_config);
6577
6578         intel_crtc->active = true;
6579
6580         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6581         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6582                          pipe_config->pch_pfit.enabled;
6583         if (psl_clkgate_wa)
6584                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6585
6586         if (INTEL_GEN(dev_priv) >= 9)
6587                 skylake_pfit_enable(pipe_config);
6588         else
6589                 ironlake_pfit_enable(pipe_config);
6590
6591         /*
6592          * On ILK+ LUT must be loaded before the pipe is running but with
6593          * clocks enabled
6594          */
6595         intel_color_load_luts(pipe_config);
6596         intel_color_commit(pipe_config);
6597         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6598         if (INTEL_GEN(dev_priv) < 9)
6599                 intel_disable_primary_plane(pipe_config);
6600
6601         if (INTEL_GEN(dev_priv) >= 11)
6602                 icl_set_pipe_chicken(intel_crtc);
6603
6604         if (!transcoder_is_dsi(cpu_transcoder))
6605                 intel_ddi_enable_transcoder_func(pipe_config);
6606
6607         if (dev_priv->display.initial_watermarks != NULL)
6608                 dev_priv->display.initial_watermarks(state, pipe_config);
6609
6610         if (INTEL_GEN(dev_priv) >= 11)
6611                 icl_pipe_mbus_enable(intel_crtc);
6612
6613         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6614         if (!transcoder_is_dsi(cpu_transcoder))
6615                 intel_enable_pipe(pipe_config);
6616
6617         if (pipe_config->has_pch_encoder)
6618                 lpt_pch_enable(state, pipe_config);
6619
6620         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
6621                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
6622
6623         assert_vblank_disabled(crtc);
6624         intel_crtc_vblank_on(pipe_config);
6625
6626         intel_encoders_enable(intel_crtc, pipe_config, state);
6627
6628         if (psl_clkgate_wa) {
6629                 intel_wait_for_vblank(dev_priv, pipe);
6630                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6631         }
6632
6633         /* If we change the relative order between pipe/planes enabling, we need
6634          * to change the workaround. */
6635         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
6636         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6637                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6638                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6639         }
6640 }
6641
6642 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6643 {
6644         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6645         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6646         enum pipe pipe = crtc->pipe;
6647
6648         /* To avoid upsetting the power well on haswell only disable the pfit if
6649          * it's in use. The hw state code will make sure we get this right. */
6650         if (old_crtc_state->pch_pfit.enabled) {
6651                 I915_WRITE(PF_CTL(pipe), 0);
6652                 I915_WRITE(PF_WIN_POS(pipe), 0);
6653                 I915_WRITE(PF_WIN_SZ(pipe), 0);
6654         }
6655 }
6656
6657 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6658                                   struct intel_atomic_state *state)
6659 {
6660         struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
6661         struct drm_device *dev = crtc->dev;
6662         struct drm_i915_private *dev_priv = to_i915(dev);
6663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6664         enum pipe pipe = intel_crtc->pipe;
6665
6666         /*
6667          * Sometimes spurious CPU pipe underruns happen when the
6668          * pipe is already disabled, but FDI RX/TX is still enabled.
6669          * Happens at least with VGA+HDMI cloning. Suppress them.
6670          */
6671         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6672         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6673
6674         intel_encoders_disable(intel_crtc, old_crtc_state, state);
6675
6676         drm_crtc_vblank_off(crtc);
6677         assert_vblank_disabled(crtc);
6678
6679         intel_disable_pipe(old_crtc_state);
6680
6681         ironlake_pfit_disable(old_crtc_state);
6682
6683         if (old_crtc_state->has_pch_encoder)
6684                 ironlake_fdi_disable(crtc);
6685
6686         intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6687
6688         if (old_crtc_state->has_pch_encoder) {
6689                 ironlake_disable_pch_transcoder(dev_priv, pipe);
6690
6691                 if (HAS_PCH_CPT(dev_priv)) {
6692                         i915_reg_t reg;
6693                         u32 temp;
6694
6695                         /* disable TRANS_DP_CTL */
6696                         reg = TRANS_DP_CTL(pipe);
6697                         temp = I915_READ(reg);
6698                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6699                                   TRANS_DP_PORT_SEL_MASK);
6700                         temp |= TRANS_DP_PORT_SEL_NONE;
6701                         I915_WRITE(reg, temp);
6702
6703                         /* disable DPLL_SEL */
6704                         temp = I915_READ(PCH_DPLL_SEL);
6705                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6706                         I915_WRITE(PCH_DPLL_SEL, temp);
6707                 }
6708
6709                 ironlake_fdi_pll_disable(intel_crtc);
6710         }
6711
6712         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6713         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6714 }
6715
6716 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6717                                  struct intel_atomic_state *state)
6718 {
6719         struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
6720         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6722         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6723
6724         intel_encoders_disable(intel_crtc, old_crtc_state, state);
6725
6726         drm_crtc_vblank_off(crtc);
6727         assert_vblank_disabled(crtc);
6728
6729         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6730         if (!transcoder_is_dsi(cpu_transcoder))
6731                 intel_disable_pipe(old_crtc_state);
6732
6733         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
6734                 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
6735
6736         if (INTEL_GEN(dev_priv) >= 11)
6737                 icl_disable_transcoder_port_sync(old_crtc_state);
6738
6739         if (!transcoder_is_dsi(cpu_transcoder))
6740                 intel_ddi_disable_transcoder_func(old_crtc_state);
6741
6742         intel_dsc_disable(old_crtc_state);
6743
6744         if (INTEL_GEN(dev_priv) >= 9)
6745                 skylake_scaler_disable(intel_crtc);
6746         else
6747                 ironlake_pfit_disable(old_crtc_state);
6748
6749         intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6750
6751         intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
6752 }
6753
6754 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6755 {
6756         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6757         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6758
6759         if (!crtc_state->gmch_pfit.control)
6760                 return;
6761
6762         /*
6763          * The panel fitter should only be adjusted whilst the pipe is disabled,
6764          * according to register description and PRM.
6765          */
6766         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6767         assert_pipe_disabled(dev_priv, crtc->pipe);
6768
6769         I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6770         I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6771
6772         /* Border color in case we don't scale up to the full screen. Black by
6773          * default, change to something else for debugging. */
6774         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6775 }
6776
6777 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6778 {
6779         if (phy == PHY_NONE)
6780                 return false;
6781
6782         if (IS_ELKHARTLAKE(dev_priv))
6783                 return phy <= PHY_C;
6784
6785         if (INTEL_GEN(dev_priv) >= 11)
6786                 return phy <= PHY_B;
6787
6788         return false;
6789 }
6790
6791 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6792 {
6793         if (INTEL_GEN(dev_priv) >= 12)
6794                 return phy >= PHY_D && phy <= PHY_I;
6795
6796         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6797                 return phy >= PHY_C && phy <= PHY_F;
6798
6799         return false;
6800 }
6801
6802 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6803 {
6804         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6805                 return PHY_A;
6806
6807         return (enum phy)port;
6808 }
6809
6810 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6811 {
6812         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6813                 return PORT_TC_NONE;
6814
6815         if (INTEL_GEN(dev_priv) >= 12)
6816                 return port - PORT_D;
6817
6818         return port - PORT_C;
6819 }
6820
6821 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6822 {
6823         switch (port) {
6824         case PORT_A:
6825                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6826         case PORT_B:
6827                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6828         case PORT_C:
6829                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6830         case PORT_D:
6831                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6832         case PORT_E:
6833                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6834         case PORT_F:
6835                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6836         case PORT_G:
6837                 return POWER_DOMAIN_PORT_DDI_G_LANES;
6838         default:
6839                 MISSING_CASE(port);
6840                 return POWER_DOMAIN_PORT_OTHER;
6841         }
6842 }
6843
6844 enum intel_display_power_domain
6845 intel_aux_power_domain(struct intel_digital_port *dig_port)
6846 {
6847         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6848         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6849
6850         if (intel_phy_is_tc(dev_priv, phy) &&
6851             dig_port->tc_mode == TC_PORT_TBT_ALT) {
6852                 switch (dig_port->aux_ch) {
6853                 case AUX_CH_C:
6854                         return POWER_DOMAIN_AUX_C_TBT;
6855                 case AUX_CH_D:
6856                         return POWER_DOMAIN_AUX_D_TBT;
6857                 case AUX_CH_E:
6858                         return POWER_DOMAIN_AUX_E_TBT;
6859                 case AUX_CH_F:
6860                         return POWER_DOMAIN_AUX_F_TBT;
6861                 case AUX_CH_G:
6862                         return POWER_DOMAIN_AUX_G_TBT;
6863                 default:
6864                         MISSING_CASE(dig_port->aux_ch);
6865                         return POWER_DOMAIN_AUX_C_TBT;
6866                 }
6867         }
6868
6869         switch (dig_port->aux_ch) {
6870         case AUX_CH_A:
6871                 return POWER_DOMAIN_AUX_A;
6872         case AUX_CH_B:
6873                 return POWER_DOMAIN_AUX_B;
6874         case AUX_CH_C:
6875                 return POWER_DOMAIN_AUX_C;
6876         case AUX_CH_D:
6877                 return POWER_DOMAIN_AUX_D;
6878         case AUX_CH_E:
6879                 return POWER_DOMAIN_AUX_E;
6880         case AUX_CH_F:
6881                 return POWER_DOMAIN_AUX_F;
6882         case AUX_CH_G:
6883                 return POWER_DOMAIN_AUX_G;
6884         default:
6885                 MISSING_CASE(dig_port->aux_ch);
6886                 return POWER_DOMAIN_AUX_A;
6887         }
6888 }
6889
6890 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6891 {
6892         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6893         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6894         struct drm_encoder *encoder;
6895         enum pipe pipe = crtc->pipe;
6896         u64 mask;
6897         enum transcoder transcoder = crtc_state->cpu_transcoder;
6898
6899         if (!crtc_state->hw.active)
6900                 return 0;
6901
6902         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6903         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6904         if (crtc_state->pch_pfit.enabled ||
6905             crtc_state->pch_pfit.force_thru)
6906                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6907
6908         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6909                                   crtc_state->uapi.encoder_mask) {
6910                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6911
6912                 mask |= BIT_ULL(intel_encoder->power_domain);
6913         }
6914
6915         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6916                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6917
6918         if (crtc_state->shared_dpll)
6919                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6920
6921         return mask;
6922 }
6923
6924 static u64
6925 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6926 {
6927         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6928         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6929         enum intel_display_power_domain domain;
6930         u64 domains, new_domains, old_domains;
6931
6932         old_domains = crtc->enabled_power_domains;
6933         crtc->enabled_power_domains = new_domains =
6934                 get_crtc_power_domains(crtc_state);
6935
6936         domains = new_domains & ~old_domains;
6937
6938         for_each_power_domain(domain, domains)
6939                 intel_display_power_get(dev_priv, domain);
6940
6941         return old_domains & ~new_domains;
6942 }
6943
6944 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6945                                       u64 domains)
6946 {
6947         enum intel_display_power_domain domain;
6948
6949         for_each_power_domain(domain, domains)
6950                 intel_display_power_put_unchecked(dev_priv, domain);
6951 }
6952
6953 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6954                                    struct intel_atomic_state *state)
6955 {
6956         struct drm_crtc *crtc = pipe_config->uapi.crtc;
6957         struct drm_device *dev = crtc->dev;
6958         struct drm_i915_private *dev_priv = to_i915(dev);
6959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6960         enum pipe pipe = intel_crtc->pipe;
6961
6962         if (WARN_ON(intel_crtc->active))
6963                 return;
6964
6965         if (intel_crtc_has_dp_encoder(pipe_config))
6966                 intel_dp_set_m_n(pipe_config, M1_N1);
6967
6968         intel_set_pipe_timings(pipe_config);
6969         intel_set_pipe_src_size(pipe_config);
6970
6971         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6972                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6973                 I915_WRITE(CHV_CANVAS(pipe), 0);
6974         }
6975
6976         i9xx_set_pipeconf(pipe_config);
6977
6978         intel_crtc->active = true;
6979
6980         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6981
6982         intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
6983
6984         if (IS_CHERRYVIEW(dev_priv)) {
6985                 chv_prepare_pll(intel_crtc, pipe_config);
6986                 chv_enable_pll(intel_crtc, pipe_config);
6987         } else {
6988                 vlv_prepare_pll(intel_crtc, pipe_config);
6989                 vlv_enable_pll(intel_crtc, pipe_config);
6990         }
6991
6992         intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6993
6994         i9xx_pfit_enable(pipe_config);
6995
6996         intel_color_load_luts(pipe_config);
6997         intel_color_commit(pipe_config);
6998         /* update DSPCNTR to configure gamma for pipe bottom color */
6999         intel_disable_primary_plane(pipe_config);
7000
7001         dev_priv->display.initial_watermarks(state, pipe_config);
7002         intel_enable_pipe(pipe_config);
7003
7004         assert_vblank_disabled(crtc);
7005         intel_crtc_vblank_on(pipe_config);
7006
7007         intel_encoders_enable(intel_crtc, pipe_config, state);
7008 }
7009
7010 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7011 {
7012         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7013         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7014
7015         I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
7016         I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
7017 }
7018
7019 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
7020                              struct intel_atomic_state *state)
7021 {
7022         struct drm_crtc *crtc = pipe_config->uapi.crtc;
7023         struct drm_device *dev = crtc->dev;
7024         struct drm_i915_private *dev_priv = to_i915(dev);
7025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7026         enum pipe pipe = intel_crtc->pipe;
7027
7028         if (WARN_ON(intel_crtc->active))
7029                 return;
7030
7031         i9xx_set_pll_dividers(pipe_config);
7032
7033         if (intel_crtc_has_dp_encoder(pipe_config))
7034                 intel_dp_set_m_n(pipe_config, M1_N1);
7035
7036         intel_set_pipe_timings(pipe_config);
7037         intel_set_pipe_src_size(pipe_config);
7038
7039         i9xx_set_pipeconf(pipe_config);
7040
7041         intel_crtc->active = true;
7042
7043         if (!IS_GEN(dev_priv, 2))
7044                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7045
7046         intel_encoders_pre_enable(intel_crtc, pipe_config, state);
7047
7048         i9xx_enable_pll(intel_crtc, pipe_config);
7049
7050         i9xx_pfit_enable(pipe_config);
7051
7052         intel_color_load_luts(pipe_config);
7053         intel_color_commit(pipe_config);
7054         /* update DSPCNTR to configure gamma for pipe bottom color */
7055         intel_disable_primary_plane(pipe_config);
7056
7057         if (dev_priv->display.initial_watermarks != NULL)
7058                 dev_priv->display.initial_watermarks(state,
7059                                                      pipe_config);
7060         else
7061                 intel_update_watermarks(intel_crtc);
7062         intel_enable_pipe(pipe_config);
7063
7064         assert_vblank_disabled(crtc);
7065         intel_crtc_vblank_on(pipe_config);
7066
7067         intel_encoders_enable(intel_crtc, pipe_config, state);
7068 }
7069
7070 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7071 {
7072         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7073         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7074
7075         if (!old_crtc_state->gmch_pfit.control)
7076                 return;
7077
7078         assert_pipe_disabled(dev_priv, crtc->pipe);
7079
7080         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
7081                       I915_READ(PFIT_CONTROL));
7082         I915_WRITE(PFIT_CONTROL, 0);
7083 }
7084
7085 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
7086                               struct intel_atomic_state *state)
7087 {
7088         struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
7089         struct drm_device *dev = crtc->dev;
7090         struct drm_i915_private *dev_priv = to_i915(dev);
7091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7092         enum pipe pipe = intel_crtc->pipe;
7093
7094         /*
7095          * On gen2 planes are double buffered but the pipe isn't, so we must
7096          * wait for planes to fully turn off before disabling the pipe.
7097          */
7098         if (IS_GEN(dev_priv, 2))
7099                 intel_wait_for_vblank(dev_priv, pipe);
7100
7101         intel_encoders_disable(intel_crtc, old_crtc_state, state);
7102
7103         drm_crtc_vblank_off(crtc);
7104         assert_vblank_disabled(crtc);
7105
7106         intel_disable_pipe(old_crtc_state);
7107
7108         i9xx_pfit_disable(old_crtc_state);
7109
7110         intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
7111
7112         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7113                 if (IS_CHERRYVIEW(dev_priv))
7114                         chv_disable_pll(dev_priv, pipe);
7115                 else if (IS_VALLEYVIEW(dev_priv))
7116                         vlv_disable_pll(dev_priv, pipe);
7117                 else
7118                         i9xx_disable_pll(old_crtc_state);
7119         }
7120
7121         intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
7122
7123         if (!IS_GEN(dev_priv, 2))
7124                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7125
7126         if (!dev_priv->display.initial_watermarks)
7127                 intel_update_watermarks(intel_crtc);
7128
7129         /* clock the pipe down to 640x480@60 to potentially save power */
7130         if (IS_I830(dev_priv))
7131                 i830_enable_pipe(dev_priv, pipe);
7132 }
7133
7134 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
7135                                         struct drm_modeset_acquire_ctx *ctx)
7136 {
7137         struct intel_encoder *encoder;
7138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7139         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7140         struct intel_bw_state *bw_state =
7141                 to_intel_bw_state(dev_priv->bw_obj.state);
7142         enum intel_display_power_domain domain;
7143         struct intel_plane *plane;
7144         u64 domains;
7145         struct drm_atomic_state *state;
7146         struct intel_crtc_state *crtc_state;
7147         int ret;
7148
7149         if (!intel_crtc->active)
7150                 return;
7151
7152         for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
7153                 const struct intel_plane_state *plane_state =
7154                         to_intel_plane_state(plane->base.state);
7155
7156                 if (plane_state->uapi.visible)
7157                         intel_plane_disable_noatomic(intel_crtc, plane);
7158         }
7159
7160         state = drm_atomic_state_alloc(crtc->dev);
7161         if (!state) {
7162                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7163                               crtc->base.id, crtc->name);
7164                 return;
7165         }
7166
7167         state->acquire_ctx = ctx;
7168
7169         /* Everything's already locked, -EDEADLK can't happen. */
7170         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
7171         ret = drm_atomic_add_affected_connectors(state, crtc);
7172
7173         WARN_ON(IS_ERR(crtc_state) || ret);
7174
7175         dev_priv->display.crtc_disable(crtc_state, to_intel_atomic_state(state));
7176
7177         drm_atomic_state_put(state);
7178
7179         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7180                       crtc->base.id, crtc->name);
7181
7182         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
7183         crtc->state->active = false;
7184         intel_crtc->active = false;
7185         crtc->enabled = false;
7186         crtc->state->connector_mask = 0;
7187         crtc->state->encoder_mask = 0;
7188         intel_crtc_free_hw_state(crtc_state);
7189         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7190
7191         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
7192                 encoder->base.crtc = NULL;
7193
7194         intel_fbc_disable(intel_crtc);
7195         intel_update_watermarks(intel_crtc);
7196         intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
7197
7198         domains = intel_crtc->enabled_power_domains;
7199         for_each_power_domain(domain, domains)
7200                 intel_display_power_put_unchecked(dev_priv, domain);
7201         intel_crtc->enabled_power_domains = 0;
7202
7203         dev_priv->active_pipes &= ~BIT(intel_crtc->pipe);
7204         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
7205         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
7206
7207         bw_state->data_rate[intel_crtc->pipe] = 0;
7208         bw_state->num_active_planes[intel_crtc->pipe] = 0;
7209 }
7210
7211 /*
7212  * turn all crtc's off, but do not adjust state
7213  * This has to be paired with a call to intel_modeset_setup_hw_state.
7214  */
7215 int intel_display_suspend(struct drm_device *dev)
7216 {
7217         struct drm_i915_private *dev_priv = to_i915(dev);
7218         struct drm_atomic_state *state;
7219         int ret;
7220
7221         state = drm_atomic_helper_suspend(dev);
7222         ret = PTR_ERR_OR_ZERO(state);
7223         if (ret)
7224                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7225         else
7226                 dev_priv->modeset_restore_state = state;
7227         return ret;
7228 }
7229
7230 void intel_encoder_destroy(struct drm_encoder *encoder)
7231 {
7232         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7233
7234         drm_encoder_cleanup(encoder);
7235         kfree(intel_encoder);
7236 }
7237
7238 /* Cross check the actual hw state with our own modeset state tracking (and it's
7239  * internal consistency). */
7240 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7241                                          struct drm_connector_state *conn_state)
7242 {
7243         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7244
7245         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7246                       connector->base.base.id,
7247                       connector->base.name);
7248
7249         if (connector->get_hw_state(connector)) {
7250                 struct intel_encoder *encoder = connector->encoder;
7251
7252                 I915_STATE_WARN(!crtc_state,
7253                          "connector enabled without attached crtc\n");
7254
7255                 if (!crtc_state)
7256                         return;
7257
7258                 I915_STATE_WARN(!crtc_state->hw.active,
7259                                 "connector is active, but attached crtc isn't\n");
7260
7261                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7262                         return;
7263
7264                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7265                         "atomic encoder doesn't match attached encoder\n");
7266
7267                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7268                         "attached encoder crtc differs from connector crtc\n");
7269         } else {
7270                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7271                                 "attached crtc is active, but connector isn't\n");
7272                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7273                         "best encoder set without crtc!\n");
7274         }
7275 }
7276
7277 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7278 {
7279         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7280                 return crtc_state->fdi_lanes;
7281
7282         return 0;
7283 }
7284
7285 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7286                                      struct intel_crtc_state *pipe_config)
7287 {
7288         struct drm_i915_private *dev_priv = to_i915(dev);
7289         struct drm_atomic_state *state = pipe_config->uapi.state;
7290         struct intel_crtc *other_crtc;
7291         struct intel_crtc_state *other_crtc_state;
7292
7293         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7294                       pipe_name(pipe), pipe_config->fdi_lanes);
7295         if (pipe_config->fdi_lanes > 4) {
7296                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7297                               pipe_name(pipe), pipe_config->fdi_lanes);
7298                 return -EINVAL;
7299         }
7300
7301         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7302                 if (pipe_config->fdi_lanes > 2) {
7303                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7304                                       pipe_config->fdi_lanes);
7305                         return -EINVAL;
7306                 } else {
7307                         return 0;
7308                 }
7309         }
7310
7311         if (INTEL_NUM_PIPES(dev_priv) == 2)
7312                 return 0;
7313
7314         /* Ivybridge 3 pipe is really complicated */
7315         switch (pipe) {
7316         case PIPE_A:
7317                 return 0;
7318         case PIPE_B:
7319                 if (pipe_config->fdi_lanes <= 2)
7320                         return 0;
7321
7322                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7323                 other_crtc_state =
7324                         intel_atomic_get_crtc_state(state, other_crtc);
7325                 if (IS_ERR(other_crtc_state))
7326                         return PTR_ERR(other_crtc_state);
7327
7328                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7329                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7330                                       pipe_name(pipe), pipe_config->fdi_lanes);
7331                         return -EINVAL;
7332                 }
7333                 return 0;
7334         case PIPE_C:
7335                 if (pipe_config->fdi_lanes > 2) {
7336                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7337                                       pipe_name(pipe), pipe_config->fdi_lanes);
7338                         return -EINVAL;
7339                 }
7340
7341                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7342                 other_crtc_state =
7343                         intel_atomic_get_crtc_state(state, other_crtc);
7344                 if (IS_ERR(other_crtc_state))
7345                         return PTR_ERR(other_crtc_state);
7346
7347                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7348                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7349                         return -EINVAL;
7350                 }
7351                 return 0;
7352         default:
7353                 BUG();
7354         }
7355 }
7356
7357 #define RETRY 1
7358 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7359                                        struct intel_crtc_state *pipe_config)
7360 {
7361         struct drm_device *dev = intel_crtc->base.dev;
7362         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7363         int lane, link_bw, fdi_dotclock, ret;
7364         bool needs_recompute = false;
7365
7366 retry:
7367         /* FDI is a binary signal running at ~2.7GHz, encoding
7368          * each output octet as 10 bits. The actual frequency
7369          * is stored as a divider into a 100MHz clock, and the
7370          * mode pixel clock is stored in units of 1KHz.
7371          * Hence the bw of each lane in terms of the mode signal
7372          * is:
7373          */
7374         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7375
7376         fdi_dotclock = adjusted_mode->crtc_clock;
7377
7378         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7379                                            pipe_config->pipe_bpp);
7380
7381         pipe_config->fdi_lanes = lane;
7382
7383         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7384                                link_bw, &pipe_config->fdi_m_n, false, false);
7385
7386         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7387         if (ret == -EDEADLK)
7388                 return ret;
7389
7390         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7391                 pipe_config->pipe_bpp -= 2*3;
7392                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7393                               pipe_config->pipe_bpp);
7394                 needs_recompute = true;
7395                 pipe_config->bw_constrained = true;
7396
7397                 goto retry;
7398         }
7399
7400         if (needs_recompute)
7401                 return RETRY;
7402
7403         return ret;
7404 }
7405
7406 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7407 {
7408         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7409         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7410
7411         /* IPS only exists on ULT machines and is tied to pipe A. */
7412         if (!hsw_crtc_supports_ips(crtc))
7413                 return false;
7414
7415         if (!i915_modparams.enable_ips)
7416                 return false;
7417
7418         if (crtc_state->pipe_bpp > 24)
7419                 return false;
7420
7421         /*
7422          * We compare against max which means we must take
7423          * the increased cdclk requirement into account when
7424          * calculating the new cdclk.
7425          *
7426          * Should measure whether using a lower cdclk w/o IPS
7427          */
7428         if (IS_BROADWELL(dev_priv) &&
7429             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7430                 return false;
7431
7432         return true;
7433 }
7434
7435 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7436 {
7437         struct drm_i915_private *dev_priv =
7438                 to_i915(crtc_state->uapi.crtc->dev);
7439         struct intel_atomic_state *intel_state =
7440                 to_intel_atomic_state(crtc_state->uapi.state);
7441
7442         if (!hsw_crtc_state_ips_capable(crtc_state))
7443                 return false;
7444
7445         /*
7446          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7447          * enabled and disabled dynamically based on package C states,
7448          * user space can't make reliable use of the CRCs, so let's just
7449          * completely disable it.
7450          */
7451         if (crtc_state->crc_enabled)
7452                 return false;
7453
7454         /* IPS should be fine as long as at least one plane is enabled. */
7455         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7456                 return false;
7457
7458         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7459         if (IS_BROADWELL(dev_priv) &&
7460             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7461                 return false;
7462
7463         return true;
7464 }
7465
7466 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7467 {
7468         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7469
7470         /* GDG double wide on either pipe, otherwise pipe A only */
7471         return INTEL_GEN(dev_priv) < 4 &&
7472                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7473 }
7474
7475 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7476 {
7477         u32 pixel_rate;
7478
7479         pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7480
7481         /*
7482          * We only use IF-ID interlacing. If we ever use
7483          * PF-ID we'll need to adjust the pixel_rate here.
7484          */
7485
7486         if (pipe_config->pch_pfit.enabled) {
7487                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7488                 u32 pfit_size = pipe_config->pch_pfit.size;
7489
7490                 pipe_w = pipe_config->pipe_src_w;
7491                 pipe_h = pipe_config->pipe_src_h;
7492
7493                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7494                 pfit_h = pfit_size & 0xFFFF;
7495                 if (pipe_w < pfit_w)
7496                         pipe_w = pfit_w;
7497                 if (pipe_h < pfit_h)
7498                         pipe_h = pfit_h;
7499
7500                 if (WARN_ON(!pfit_w || !pfit_h))
7501                         return pixel_rate;
7502
7503                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7504                                      pfit_w * pfit_h);
7505         }
7506
7507         return pixel_rate;
7508 }
7509
7510 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7511 {
7512         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7513
7514         if (HAS_GMCH(dev_priv))
7515                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7516                 crtc_state->pixel_rate =
7517                         crtc_state->hw.adjusted_mode.crtc_clock;
7518         else
7519                 crtc_state->pixel_rate =
7520                         ilk_pipe_pixel_rate(crtc_state);
7521 }
7522
7523 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7524                                      struct intel_crtc_state *pipe_config)
7525 {
7526         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7527         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7528         int clock_limit = dev_priv->max_dotclk_freq;
7529
7530         if (INTEL_GEN(dev_priv) < 4) {
7531                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7532
7533                 /*
7534                  * Enable double wide mode when the dot clock
7535                  * is > 90% of the (display) core speed.
7536                  */
7537                 if (intel_crtc_supports_double_wide(crtc) &&
7538                     adjusted_mode->crtc_clock > clock_limit) {
7539                         clock_limit = dev_priv->max_dotclk_freq;
7540                         pipe_config->double_wide = true;
7541                 }
7542         }
7543
7544         if (adjusted_mode->crtc_clock > clock_limit) {
7545                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7546                               adjusted_mode->crtc_clock, clock_limit,
7547                               yesno(pipe_config->double_wide));
7548                 return -EINVAL;
7549         }
7550
7551         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7552              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7553              pipe_config->hw.ctm) {
7554                 /*
7555                  * There is only one pipe CSC unit per pipe, and we need that
7556                  * for output conversion from RGB->YCBCR. So if CTM is already
7557                  * applied we can't support YCBCR420 output.
7558                  */
7559                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7560                 return -EINVAL;
7561         }
7562
7563         /*
7564          * Pipe horizontal size must be even in:
7565          * - DVO ganged mode
7566          * - LVDS dual channel mode
7567          * - Double wide pipe
7568          */
7569         if (pipe_config->pipe_src_w & 1) {
7570                 if (pipe_config->double_wide) {
7571                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7572                         return -EINVAL;
7573                 }
7574
7575                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7576                     intel_is_dual_link_lvds(dev_priv)) {
7577                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7578                         return -EINVAL;
7579                 }
7580         }
7581
7582         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7583          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7584          */
7585         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7586                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7587                 return -EINVAL;
7588
7589         intel_crtc_compute_pixel_rate(pipe_config);
7590
7591         if (pipe_config->has_pch_encoder)
7592                 return ironlake_fdi_compute_config(crtc, pipe_config);
7593
7594         return 0;
7595 }
7596
7597 static void
7598 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7599 {
7600         while (*num > DATA_LINK_M_N_MASK ||
7601                *den > DATA_LINK_M_N_MASK) {
7602                 *num >>= 1;
7603                 *den >>= 1;
7604         }
7605 }
7606
7607 static void compute_m_n(unsigned int m, unsigned int n,
7608                         u32 *ret_m, u32 *ret_n,
7609                         bool constant_n)
7610 {
7611         /*
7612          * Several DP dongles in particular seem to be fussy about
7613          * too large link M/N values. Give N value as 0x8000 that
7614          * should be acceptable by specific devices. 0x8000 is the
7615          * specified fixed N value for asynchronous clock mode,
7616          * which the devices expect also in synchronous clock mode.
7617          */
7618         if (constant_n)
7619                 *ret_n = 0x8000;
7620         else
7621                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7622
7623         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7624         intel_reduce_m_n_ratio(ret_m, ret_n);
7625 }
7626
7627 void
7628 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7629                        int pixel_clock, int link_clock,
7630                        struct intel_link_m_n *m_n,
7631                        bool constant_n, bool fec_enable)
7632 {
7633         u32 data_clock = bits_per_pixel * pixel_clock;
7634
7635         if (fec_enable)
7636                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
7637
7638         m_n->tu = 64;
7639         compute_m_n(data_clock,
7640                     link_clock * nlanes * 8,
7641                     &m_n->gmch_m, &m_n->gmch_n,
7642                     constant_n);
7643
7644         compute_m_n(pixel_clock, link_clock,
7645                     &m_n->link_m, &m_n->link_n,
7646                     constant_n);
7647 }
7648
7649 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
7650 {
7651         /*
7652          * There may be no VBT; and if the BIOS enabled SSC we can
7653          * just keep using it to avoid unnecessary flicker.  Whereas if the
7654          * BIOS isn't using it, don't assume it will work even if the VBT
7655          * indicates as much.
7656          */
7657         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7658                 bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) &
7659                         DREF_SSC1_ENABLE;
7660
7661                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
7662                         DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n",
7663                                       enableddisabled(bios_lvds_use_ssc),
7664                                       enableddisabled(dev_priv->vbt.lvds_use_ssc));
7665                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
7666                 }
7667         }
7668 }
7669
7670 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7671 {
7672         if (i915_modparams.panel_use_ssc >= 0)
7673                 return i915_modparams.panel_use_ssc != 0;
7674         return dev_priv->vbt.lvds_use_ssc
7675                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7676 }
7677
7678 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7679 {
7680         return (1 << dpll->n) << 16 | dpll->m2;
7681 }
7682
7683 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7684 {
7685         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7686 }
7687
7688 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7689                                      struct intel_crtc_state *crtc_state,
7690                                      struct dpll *reduced_clock)
7691 {
7692         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7693         u32 fp, fp2 = 0;
7694
7695         if (IS_PINEVIEW(dev_priv)) {
7696                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7697                 if (reduced_clock)
7698                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7699         } else {
7700                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7701                 if (reduced_clock)
7702                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7703         }
7704
7705         crtc_state->dpll_hw_state.fp0 = fp;
7706
7707         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7708             reduced_clock) {
7709                 crtc_state->dpll_hw_state.fp1 = fp2;
7710         } else {
7711                 crtc_state->dpll_hw_state.fp1 = fp;
7712         }
7713 }
7714
7715 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7716                 pipe)
7717 {
7718         u32 reg_val;
7719
7720         /*
7721          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7722          * and set it to a reasonable value instead.
7723          */
7724         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7725         reg_val &= 0xffffff00;
7726         reg_val |= 0x00000030;
7727         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7728
7729         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7730         reg_val &= 0x00ffffff;
7731         reg_val |= 0x8c000000;
7732         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7733
7734         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7735         reg_val &= 0xffffff00;
7736         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7737
7738         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7739         reg_val &= 0x00ffffff;
7740         reg_val |= 0xb0000000;
7741         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7742 }
7743
7744 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7745                                          const struct intel_link_m_n *m_n)
7746 {
7747         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7748         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7749         enum pipe pipe = crtc->pipe;
7750
7751         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7752         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7753         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7754         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7755 }
7756
7757 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7758                                  enum transcoder transcoder)
7759 {
7760         if (IS_HASWELL(dev_priv))
7761                 return transcoder == TRANSCODER_EDP;
7762
7763         /*
7764          * Strictly speaking some registers are available before
7765          * gen7, but we only support DRRS on gen7+
7766          */
7767         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7768 }
7769
7770 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7771                                          const struct intel_link_m_n *m_n,
7772                                          const struct intel_link_m_n *m2_n2)
7773 {
7774         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7775         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7776         enum pipe pipe = crtc->pipe;
7777         enum transcoder transcoder = crtc_state->cpu_transcoder;
7778
7779         if (INTEL_GEN(dev_priv) >= 5) {
7780                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7781                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7782                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7783                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7784                 /*
7785                  *  M2_N2 registers are set only if DRRS is supported
7786                  * (to make sure the registers are not unnecessarily accessed).
7787                  */
7788                 if (m2_n2 && crtc_state->has_drrs &&
7789                     transcoder_has_m2_n2(dev_priv, transcoder)) {
7790                         I915_WRITE(PIPE_DATA_M2(transcoder),
7791                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7792                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7793                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7794                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7795                 }
7796         } else {
7797                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7798                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7799                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7800                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7801         }
7802 }
7803
7804 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7805 {
7806         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7807
7808         if (m_n == M1_N1) {
7809                 dp_m_n = &crtc_state->dp_m_n;
7810                 dp_m2_n2 = &crtc_state->dp_m2_n2;
7811         } else if (m_n == M2_N2) {
7812
7813                 /*
7814                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7815                  * needs to be programmed into M1_N1.
7816                  */
7817                 dp_m_n = &crtc_state->dp_m2_n2;
7818         } else {
7819                 DRM_ERROR("Unsupported divider value\n");
7820                 return;
7821         }
7822
7823         if (crtc_state->has_pch_encoder)
7824                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7825         else
7826                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7827 }
7828
7829 static void vlv_compute_dpll(struct intel_crtc *crtc,
7830                              struct intel_crtc_state *pipe_config)
7831 {
7832         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7833                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7834         if (crtc->pipe != PIPE_A)
7835                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7836
7837         /* DPLL not used with DSI, but still need the rest set up */
7838         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7839                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7840                         DPLL_EXT_BUFFER_ENABLE_VLV;
7841
7842         pipe_config->dpll_hw_state.dpll_md =
7843                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7844 }
7845
7846 static void chv_compute_dpll(struct intel_crtc *crtc,
7847                              struct intel_crtc_state *pipe_config)
7848 {
7849         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7850                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7851         if (crtc->pipe != PIPE_A)
7852                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7853
7854         /* DPLL not used with DSI, but still need the rest set up */
7855         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7856                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7857
7858         pipe_config->dpll_hw_state.dpll_md =
7859                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7860 }
7861
7862 static void vlv_prepare_pll(struct intel_crtc *crtc,
7863                             const struct intel_crtc_state *pipe_config)
7864 {
7865         struct drm_device *dev = crtc->base.dev;
7866         struct drm_i915_private *dev_priv = to_i915(dev);
7867         enum pipe pipe = crtc->pipe;
7868         u32 mdiv;
7869         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7870         u32 coreclk, reg_val;
7871
7872         /* Enable Refclk */
7873         I915_WRITE(DPLL(pipe),
7874                    pipe_config->dpll_hw_state.dpll &
7875                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7876
7877         /* No need to actually set up the DPLL with DSI */
7878         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7879                 return;
7880
7881         vlv_dpio_get(dev_priv);
7882
7883         bestn = pipe_config->dpll.n;
7884         bestm1 = pipe_config->dpll.m1;
7885         bestm2 = pipe_config->dpll.m2;
7886         bestp1 = pipe_config->dpll.p1;
7887         bestp2 = pipe_config->dpll.p2;
7888
7889         /* See eDP HDMI DPIO driver vbios notes doc */
7890
7891         /* PLL B needs special handling */
7892         if (pipe == PIPE_B)
7893                 vlv_pllb_recal_opamp(dev_priv, pipe);
7894
7895         /* Set up Tx target for periodic Rcomp update */
7896         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7897
7898         /* Disable target IRef on PLL */
7899         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7900         reg_val &= 0x00ffffff;
7901         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7902
7903         /* Disable fast lock */
7904         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7905
7906         /* Set idtafcrecal before PLL is enabled */
7907         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7908         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7909         mdiv |= ((bestn << DPIO_N_SHIFT));
7910         mdiv |= (1 << DPIO_K_SHIFT);
7911
7912         /*
7913          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7914          * but we don't support that).
7915          * Note: don't use the DAC post divider as it seems unstable.
7916          */
7917         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7918         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7919
7920         mdiv |= DPIO_ENABLE_CALIBRATION;
7921         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7922
7923         /* Set HBR and RBR LPF coefficients */
7924         if (pipe_config->port_clock == 162000 ||
7925             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7926             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7927                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7928                                  0x009f0003);
7929         else
7930                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7931                                  0x00d0000f);
7932
7933         if (intel_crtc_has_dp_encoder(pipe_config)) {
7934                 /* Use SSC source */
7935                 if (pipe == PIPE_A)
7936                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7937                                          0x0df40000);
7938                 else
7939                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7940                                          0x0df70000);
7941         } else { /* HDMI or VGA */
7942                 /* Use bend source */
7943                 if (pipe == PIPE_A)
7944                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7945                                          0x0df70000);
7946                 else
7947                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7948                                          0x0df40000);
7949         }
7950
7951         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7952         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7953         if (intel_crtc_has_dp_encoder(pipe_config))
7954                 coreclk |= 0x01000000;
7955         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7956
7957         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7958
7959         vlv_dpio_put(dev_priv);
7960 }
7961
7962 static void chv_prepare_pll(struct intel_crtc *crtc,
7963                             const struct intel_crtc_state *pipe_config)
7964 {
7965         struct drm_device *dev = crtc->base.dev;
7966         struct drm_i915_private *dev_priv = to_i915(dev);
7967         enum pipe pipe = crtc->pipe;
7968         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7969         u32 loopfilter, tribuf_calcntr;
7970         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7971         u32 dpio_val;
7972         int vco;
7973
7974         /* Enable Refclk and SSC */
7975         I915_WRITE(DPLL(pipe),
7976                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7977
7978         /* No need to actually set up the DPLL with DSI */
7979         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7980                 return;
7981
7982         bestn = pipe_config->dpll.n;
7983         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7984         bestm1 = pipe_config->dpll.m1;
7985         bestm2 = pipe_config->dpll.m2 >> 22;
7986         bestp1 = pipe_config->dpll.p1;
7987         bestp2 = pipe_config->dpll.p2;
7988         vco = pipe_config->dpll.vco;
7989         dpio_val = 0;
7990         loopfilter = 0;
7991
7992         vlv_dpio_get(dev_priv);
7993
7994         /* p1 and p2 divider */
7995         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7996                         5 << DPIO_CHV_S1_DIV_SHIFT |
7997                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7998                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7999                         1 << DPIO_CHV_K_DIV_SHIFT);
8000
8001         /* Feedback post-divider - m2 */
8002         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8003
8004         /* Feedback refclk divider - n and m1 */
8005         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8006                         DPIO_CHV_M1_DIV_BY_2 |
8007                         1 << DPIO_CHV_N_DIV_SHIFT);
8008
8009         /* M2 fraction division */
8010         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8011
8012         /* M2 fraction division enable */
8013         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8014         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8015         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8016         if (bestm2_frac)
8017                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8018         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8019
8020         /* Program digital lock detect threshold */
8021         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8022         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8023                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8024         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8025         if (!bestm2_frac)
8026                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8027         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8028
8029         /* Loop filter */
8030         if (vco == 5400000) {
8031                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8032                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8033                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8034                 tribuf_calcntr = 0x9;
8035         } else if (vco <= 6200000) {
8036                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8037                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8038                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8039                 tribuf_calcntr = 0x9;
8040         } else if (vco <= 6480000) {
8041                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8042                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8043                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8044                 tribuf_calcntr = 0x8;
8045         } else {
8046                 /* Not supported. Apply the same limits as in the max case */
8047                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8048                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8049                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8050                 tribuf_calcntr = 0;
8051         }
8052         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8053
8054         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8055         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8056         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8057         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8058
8059         /* AFC Recal */
8060         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8061                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8062                         DPIO_AFC_RECAL);
8063
8064         vlv_dpio_put(dev_priv);
8065 }
8066
8067 /**
8068  * vlv_force_pll_on - forcibly enable just the PLL
8069  * @dev_priv: i915 private structure
8070  * @pipe: pipe PLL to enable
8071  * @dpll: PLL configuration
8072  *
8073  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8074  * in cases where we need the PLL enabled even when @pipe is not going to
8075  * be enabled.
8076  */
8077 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8078                      const struct dpll *dpll)
8079 {
8080         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8081         struct intel_crtc_state *pipe_config;
8082
8083         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8084         if (!pipe_config)
8085                 return -ENOMEM;
8086
8087         pipe_config->uapi.crtc = &crtc->base;
8088         pipe_config->pixel_multiplier = 1;
8089         pipe_config->dpll = *dpll;
8090
8091         if (IS_CHERRYVIEW(dev_priv)) {
8092                 chv_compute_dpll(crtc, pipe_config);
8093                 chv_prepare_pll(crtc, pipe_config);
8094                 chv_enable_pll(crtc, pipe_config);
8095         } else {
8096                 vlv_compute_dpll(crtc, pipe_config);
8097                 vlv_prepare_pll(crtc, pipe_config);
8098                 vlv_enable_pll(crtc, pipe_config);
8099         }
8100
8101         kfree(pipe_config);
8102
8103         return 0;
8104 }
8105
8106 /**
8107  * vlv_force_pll_off - forcibly disable just the PLL
8108  * @dev_priv: i915 private structure
8109  * @pipe: pipe PLL to disable
8110  *
8111  * Disable the PLL for @pipe. To be used in cases where we need
8112  * the PLL enabled even when @pipe is not going to be enabled.
8113  */
8114 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8115 {
8116         if (IS_CHERRYVIEW(dev_priv))
8117                 chv_disable_pll(dev_priv, pipe);
8118         else
8119                 vlv_disable_pll(dev_priv, pipe);
8120 }
8121
8122 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8123                               struct intel_crtc_state *crtc_state,
8124                               struct dpll *reduced_clock)
8125 {
8126         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8127         u32 dpll;
8128         struct dpll *clock = &crtc_state->dpll;
8129
8130         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8131
8132         dpll = DPLL_VGA_MODE_DIS;
8133
8134         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8135                 dpll |= DPLLB_MODE_LVDS;
8136         else
8137                 dpll |= DPLLB_MODE_DAC_SERIAL;
8138
8139         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8140             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8141                 dpll |= (crtc_state->pixel_multiplier - 1)
8142                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8143         }
8144
8145         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8146             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8147                 dpll |= DPLL_SDVO_HIGH_SPEED;
8148
8149         if (intel_crtc_has_dp_encoder(crtc_state))
8150                 dpll |= DPLL_SDVO_HIGH_SPEED;
8151
8152         /* compute bitmask from p1 value */
8153         if (IS_PINEVIEW(dev_priv))
8154                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8155         else {
8156                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8157                 if (IS_G4X(dev_priv) && reduced_clock)
8158                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8159         }
8160         switch (clock->p2) {
8161         case 5:
8162                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8163                 break;
8164         case 7:
8165                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8166                 break;
8167         case 10:
8168                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8169                 break;
8170         case 14:
8171                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8172                 break;
8173         }
8174         if (INTEL_GEN(dev_priv) >= 4)
8175                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8176
8177         if (crtc_state->sdvo_tv_clock)
8178                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8179         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8180                  intel_panel_use_ssc(dev_priv))
8181                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8182         else
8183                 dpll |= PLL_REF_INPUT_DREFCLK;
8184
8185         dpll |= DPLL_VCO_ENABLE;
8186         crtc_state->dpll_hw_state.dpll = dpll;
8187
8188         if (INTEL_GEN(dev_priv) >= 4) {
8189                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8190                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8191                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8192         }
8193 }
8194
8195 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8196                               struct intel_crtc_state *crtc_state,
8197                               struct dpll *reduced_clock)
8198 {
8199         struct drm_device *dev = crtc->base.dev;
8200         struct drm_i915_private *dev_priv = to_i915(dev);
8201         u32 dpll;
8202         struct dpll *clock = &crtc_state->dpll;
8203
8204         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8205
8206         dpll = DPLL_VGA_MODE_DIS;
8207
8208         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8209                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8210         } else {
8211                 if (clock->p1 == 2)
8212                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8213                 else
8214                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8215                 if (clock->p2 == 4)
8216                         dpll |= PLL_P2_DIVIDE_BY_4;
8217         }
8218
8219         /*
8220          * Bspec:
8221          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8222          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8223          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8224          *  Enable) must be set to “1” in both the DPLL A Control Register
8225          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8226          *
8227          * For simplicity We simply keep both bits always enabled in
8228          * both DPLLS. The spec says we should disable the DVO 2X clock
8229          * when not needed, but this seems to work fine in practice.
8230          */
8231         if (IS_I830(dev_priv) ||
8232             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8233                 dpll |= DPLL_DVO_2X_MODE;
8234
8235         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8236             intel_panel_use_ssc(dev_priv))
8237                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8238         else
8239                 dpll |= PLL_REF_INPUT_DREFCLK;
8240
8241         dpll |= DPLL_VCO_ENABLE;
8242         crtc_state->dpll_hw_state.dpll = dpll;
8243 }
8244
8245 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8246 {
8247         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8248         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8249         enum pipe pipe = crtc->pipe;
8250         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8251         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8252         u32 crtc_vtotal, crtc_vblank_end;
8253         int vsyncshift = 0;
8254
8255         /* We need to be careful not to changed the adjusted mode, for otherwise
8256          * the hw state checker will get angry at the mismatch. */
8257         crtc_vtotal = adjusted_mode->crtc_vtotal;
8258         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8259
8260         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8261                 /* the chip adds 2 halflines automatically */
8262                 crtc_vtotal -= 1;
8263                 crtc_vblank_end -= 1;
8264
8265                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8266                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8267                 else
8268                         vsyncshift = adjusted_mode->crtc_hsync_start -
8269                                 adjusted_mode->crtc_htotal / 2;
8270                 if (vsyncshift < 0)
8271                         vsyncshift += adjusted_mode->crtc_htotal;
8272         }
8273
8274         if (INTEL_GEN(dev_priv) > 3)
8275                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8276
8277         I915_WRITE(HTOTAL(cpu_transcoder),
8278                    (adjusted_mode->crtc_hdisplay - 1) |
8279                    ((adjusted_mode->crtc_htotal - 1) << 16));
8280         I915_WRITE(HBLANK(cpu_transcoder),
8281                    (adjusted_mode->crtc_hblank_start - 1) |
8282                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8283         I915_WRITE(HSYNC(cpu_transcoder),
8284                    (adjusted_mode->crtc_hsync_start - 1) |
8285                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8286
8287         I915_WRITE(VTOTAL(cpu_transcoder),
8288                    (adjusted_mode->crtc_vdisplay - 1) |
8289                    ((crtc_vtotal - 1) << 16));
8290         I915_WRITE(VBLANK(cpu_transcoder),
8291                    (adjusted_mode->crtc_vblank_start - 1) |
8292                    ((crtc_vblank_end - 1) << 16));
8293         I915_WRITE(VSYNC(cpu_transcoder),
8294                    (adjusted_mode->crtc_vsync_start - 1) |
8295                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8296
8297         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8298          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8299          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8300          * bits. */
8301         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8302             (pipe == PIPE_B || pipe == PIPE_C))
8303                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8304
8305 }
8306
8307 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8308 {
8309         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8310         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8311         enum pipe pipe = crtc->pipe;
8312
8313         /* pipesrc controls the size that is scaled from, which should
8314          * always be the user's requested size.
8315          */
8316         I915_WRITE(PIPESRC(pipe),
8317                    ((crtc_state->pipe_src_w - 1) << 16) |
8318                    (crtc_state->pipe_src_h - 1));
8319 }
8320
8321 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8322 {
8323         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8324         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8325
8326         if (IS_GEN(dev_priv, 2))
8327                 return false;
8328
8329         if (INTEL_GEN(dev_priv) >= 9 ||
8330             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8331                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8332         else
8333                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8334 }
8335
8336 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8337                                    struct intel_crtc_state *pipe_config)
8338 {
8339         struct drm_device *dev = crtc->base.dev;
8340         struct drm_i915_private *dev_priv = to_i915(dev);
8341         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8342         u32 tmp;
8343
8344         tmp = I915_READ(HTOTAL(cpu_transcoder));
8345         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8346         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8347
8348         if (!transcoder_is_dsi(cpu_transcoder)) {
8349                 tmp = I915_READ(HBLANK(cpu_transcoder));
8350                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8351                                                         (tmp & 0xffff) + 1;
8352                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8353                                                 ((tmp >> 16) & 0xffff) + 1;
8354         }
8355         tmp = I915_READ(HSYNC(cpu_transcoder));
8356         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8357         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8358
8359         tmp = I915_READ(VTOTAL(cpu_transcoder));
8360         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8361         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8362
8363         if (!transcoder_is_dsi(cpu_transcoder)) {
8364                 tmp = I915_READ(VBLANK(cpu_transcoder));
8365                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8366                                                         (tmp & 0xffff) + 1;
8367                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8368                                                 ((tmp >> 16) & 0xffff) + 1;
8369         }
8370         tmp = I915_READ(VSYNC(cpu_transcoder));
8371         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8372         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8373
8374         if (intel_pipe_is_interlaced(pipe_config)) {
8375                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8376                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8377                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8378         }
8379 }
8380
8381 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8382                                     struct intel_crtc_state *pipe_config)
8383 {
8384         struct drm_device *dev = crtc->base.dev;
8385         struct drm_i915_private *dev_priv = to_i915(dev);
8386         u32 tmp;
8387
8388         tmp = I915_READ(PIPESRC(crtc->pipe));
8389         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8390         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8391
8392         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8393         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8394 }
8395
8396 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8397                                  struct intel_crtc_state *pipe_config)
8398 {
8399         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8400         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8401         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8402         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8403
8404         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8405         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8406         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8407         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8408
8409         mode->flags = pipe_config->hw.adjusted_mode.flags;
8410         mode->type = DRM_MODE_TYPE_DRIVER;
8411
8412         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8413
8414         mode->hsync = drm_mode_hsync(mode);
8415         mode->vrefresh = drm_mode_vrefresh(mode);
8416         drm_mode_set_name(mode);
8417 }
8418
8419 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8420 {
8421         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8423         u32 pipeconf;
8424
8425         pipeconf = 0;
8426
8427         /* we keep both pipes enabled on 830 */
8428         if (IS_I830(dev_priv))
8429                 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8430
8431         if (crtc_state->double_wide)
8432                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8433
8434         /* only g4x and later have fancy bpc/dither controls */
8435         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8436             IS_CHERRYVIEW(dev_priv)) {
8437                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8438                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8439                         pipeconf |= PIPECONF_DITHER_EN |
8440                                     PIPECONF_DITHER_TYPE_SP;
8441
8442                 switch (crtc_state->pipe_bpp) {
8443                 case 18:
8444                         pipeconf |= PIPECONF_6BPC;
8445                         break;
8446                 case 24:
8447                         pipeconf |= PIPECONF_8BPC;
8448                         break;
8449                 case 30:
8450                         pipeconf |= PIPECONF_10BPC;
8451                         break;
8452                 default:
8453                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8454                         BUG();
8455                 }
8456         }
8457
8458         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8459                 if (INTEL_GEN(dev_priv) < 4 ||
8460                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8461                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8462                 else
8463                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8464         } else {
8465                 pipeconf |= PIPECONF_PROGRESSIVE;
8466         }
8467
8468         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8469              crtc_state->limited_color_range)
8470                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8471
8472         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8473
8474         I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8475         POSTING_READ(PIPECONF(crtc->pipe));
8476 }
8477
8478 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8479                                    struct intel_crtc_state *crtc_state)
8480 {
8481         struct drm_device *dev = crtc->base.dev;
8482         struct drm_i915_private *dev_priv = to_i915(dev);
8483         const struct intel_limit *limit;
8484         int refclk = 48000;
8485
8486         memset(&crtc_state->dpll_hw_state, 0,
8487                sizeof(crtc_state->dpll_hw_state));
8488
8489         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8490                 if (intel_panel_use_ssc(dev_priv)) {
8491                         refclk = dev_priv->vbt.lvds_ssc_freq;
8492                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8493                 }
8494
8495                 limit = &intel_limits_i8xx_lvds;
8496         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8497                 limit = &intel_limits_i8xx_dvo;
8498         } else {
8499                 limit = &intel_limits_i8xx_dac;
8500         }
8501
8502         if (!crtc_state->clock_set &&
8503             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8504                                  refclk, NULL, &crtc_state->dpll)) {
8505                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8506                 return -EINVAL;
8507         }
8508
8509         i8xx_compute_dpll(crtc, crtc_state, NULL);
8510
8511         return 0;
8512 }
8513
8514 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8515                                   struct intel_crtc_state *crtc_state)
8516 {
8517         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8518         const struct intel_limit *limit;
8519         int refclk = 96000;
8520
8521         memset(&crtc_state->dpll_hw_state, 0,
8522                sizeof(crtc_state->dpll_hw_state));
8523
8524         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8525                 if (intel_panel_use_ssc(dev_priv)) {
8526                         refclk = dev_priv->vbt.lvds_ssc_freq;
8527                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8528                 }
8529
8530                 if (intel_is_dual_link_lvds(dev_priv))
8531                         limit = &intel_limits_g4x_dual_channel_lvds;
8532                 else
8533                         limit = &intel_limits_g4x_single_channel_lvds;
8534         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8535                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8536                 limit = &intel_limits_g4x_hdmi;
8537         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8538                 limit = &intel_limits_g4x_sdvo;
8539         } else {
8540                 /* The option is for other outputs */
8541                 limit = &intel_limits_i9xx_sdvo;
8542         }
8543
8544         if (!crtc_state->clock_set &&
8545             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8546                                 refclk, NULL, &crtc_state->dpll)) {
8547                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8548                 return -EINVAL;
8549         }
8550
8551         i9xx_compute_dpll(crtc, crtc_state, NULL);
8552
8553         return 0;
8554 }
8555
8556 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8557                                   struct intel_crtc_state *crtc_state)
8558 {
8559         struct drm_device *dev = crtc->base.dev;
8560         struct drm_i915_private *dev_priv = to_i915(dev);
8561         const struct intel_limit *limit;
8562         int refclk = 96000;
8563
8564         memset(&crtc_state->dpll_hw_state, 0,
8565                sizeof(crtc_state->dpll_hw_state));
8566
8567         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8568                 if (intel_panel_use_ssc(dev_priv)) {
8569                         refclk = dev_priv->vbt.lvds_ssc_freq;
8570                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8571                 }
8572
8573                 limit = &intel_limits_pineview_lvds;
8574         } else {
8575                 limit = &intel_limits_pineview_sdvo;
8576         }
8577
8578         if (!crtc_state->clock_set &&
8579             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8580                                 refclk, NULL, &crtc_state->dpll)) {
8581                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8582                 return -EINVAL;
8583         }
8584
8585         i9xx_compute_dpll(crtc, crtc_state, NULL);
8586
8587         return 0;
8588 }
8589
8590 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8591                                    struct intel_crtc_state *crtc_state)
8592 {
8593         struct drm_device *dev = crtc->base.dev;
8594         struct drm_i915_private *dev_priv = to_i915(dev);
8595         const struct intel_limit *limit;
8596         int refclk = 96000;
8597
8598         memset(&crtc_state->dpll_hw_state, 0,
8599                sizeof(crtc_state->dpll_hw_state));
8600
8601         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8602                 if (intel_panel_use_ssc(dev_priv)) {
8603                         refclk = dev_priv->vbt.lvds_ssc_freq;
8604                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8605                 }
8606
8607                 limit = &intel_limits_i9xx_lvds;
8608         } else {
8609                 limit = &intel_limits_i9xx_sdvo;
8610         }
8611
8612         if (!crtc_state->clock_set &&
8613             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8614                                  refclk, NULL, &crtc_state->dpll)) {
8615                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8616                 return -EINVAL;
8617         }
8618
8619         i9xx_compute_dpll(crtc, crtc_state, NULL);
8620
8621         return 0;
8622 }
8623
8624 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8625                                   struct intel_crtc_state *crtc_state)
8626 {
8627         int refclk = 100000;
8628         const struct intel_limit *limit = &intel_limits_chv;
8629
8630         memset(&crtc_state->dpll_hw_state, 0,
8631                sizeof(crtc_state->dpll_hw_state));
8632
8633         if (!crtc_state->clock_set &&
8634             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8635                                 refclk, NULL, &crtc_state->dpll)) {
8636                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8637                 return -EINVAL;
8638         }
8639
8640         chv_compute_dpll(crtc, crtc_state);
8641
8642         return 0;
8643 }
8644
8645 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8646                                   struct intel_crtc_state *crtc_state)
8647 {
8648         int refclk = 100000;
8649         const struct intel_limit *limit = &intel_limits_vlv;
8650
8651         memset(&crtc_state->dpll_hw_state, 0,
8652                sizeof(crtc_state->dpll_hw_state));
8653
8654         if (!crtc_state->clock_set &&
8655             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8656                                 refclk, NULL, &crtc_state->dpll)) {
8657                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8658                 return -EINVAL;
8659         }
8660
8661         vlv_compute_dpll(crtc, crtc_state);
8662
8663         return 0;
8664 }
8665
8666 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8667 {
8668         if (IS_I830(dev_priv))
8669                 return false;
8670
8671         return INTEL_GEN(dev_priv) >= 4 ||
8672                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8673 }
8674
8675 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8676                                  struct intel_crtc_state *pipe_config)
8677 {
8678         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8679         u32 tmp;
8680
8681         if (!i9xx_has_pfit(dev_priv))
8682                 return;
8683
8684         tmp = I915_READ(PFIT_CONTROL);
8685         if (!(tmp & PFIT_ENABLE))
8686                 return;
8687
8688         /* Check whether the pfit is attached to our pipe. */
8689         if (INTEL_GEN(dev_priv) < 4) {
8690                 if (crtc->pipe != PIPE_B)
8691                         return;
8692         } else {
8693                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8694                         return;
8695         }
8696
8697         pipe_config->gmch_pfit.control = tmp;
8698         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8699 }
8700
8701 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8702                                struct intel_crtc_state *pipe_config)
8703 {
8704         struct drm_device *dev = crtc->base.dev;
8705         struct drm_i915_private *dev_priv = to_i915(dev);
8706         enum pipe pipe = crtc->pipe;
8707         struct dpll clock;
8708         u32 mdiv;
8709         int refclk = 100000;
8710
8711         /* In case of DSI, DPLL will not be used */
8712         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8713                 return;
8714
8715         vlv_dpio_get(dev_priv);
8716         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8717         vlv_dpio_put(dev_priv);
8718
8719         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8720         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8721         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8722         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8723         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8724
8725         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8726 }
8727
8728 static void
8729 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8730                               struct intel_initial_plane_config *plane_config)
8731 {
8732         struct drm_device *dev = crtc->base.dev;
8733         struct drm_i915_private *dev_priv = to_i915(dev);
8734         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8735         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8736         enum pipe pipe;
8737         u32 val, base, offset;
8738         int fourcc, pixel_format;
8739         unsigned int aligned_height;
8740         struct drm_framebuffer *fb;
8741         struct intel_framebuffer *intel_fb;
8742
8743         if (!plane->get_hw_state(plane, &pipe))
8744                 return;
8745
8746         WARN_ON(pipe != crtc->pipe);
8747
8748         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8749         if (!intel_fb) {
8750                 DRM_DEBUG_KMS("failed to alloc fb\n");
8751                 return;
8752         }
8753
8754         fb = &intel_fb->base;
8755
8756         fb->dev = dev;
8757
8758         val = I915_READ(DSPCNTR(i9xx_plane));
8759
8760         if (INTEL_GEN(dev_priv) >= 4) {
8761                 if (val & DISPPLANE_TILED) {
8762                         plane_config->tiling = I915_TILING_X;
8763                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8764                 }
8765
8766                 if (val & DISPPLANE_ROTATE_180)
8767                         plane_config->rotation = DRM_MODE_ROTATE_180;
8768         }
8769
8770         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8771             val & DISPPLANE_MIRROR)
8772                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8773
8774         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8775         fourcc = i9xx_format_to_fourcc(pixel_format);
8776         fb->format = drm_format_info(fourcc);
8777
8778         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8779                 offset = I915_READ(DSPOFFSET(i9xx_plane));
8780                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8781         } else if (INTEL_GEN(dev_priv) >= 4) {
8782                 if (plane_config->tiling)
8783                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
8784                 else
8785                         offset = I915_READ(DSPLINOFF(i9xx_plane));
8786                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8787         } else {
8788                 base = I915_READ(DSPADDR(i9xx_plane));
8789         }
8790         plane_config->base = base;
8791
8792         val = I915_READ(PIPESRC(pipe));
8793         fb->width = ((val >> 16) & 0xfff) + 1;
8794         fb->height = ((val >> 0) & 0xfff) + 1;
8795
8796         val = I915_READ(DSPSTRIDE(i9xx_plane));
8797         fb->pitches[0] = val & 0xffffffc0;
8798
8799         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8800
8801         plane_config->size = fb->pitches[0] * aligned_height;
8802
8803         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8804                       crtc->base.name, plane->base.name, fb->width, fb->height,
8805                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8806                       plane_config->size);
8807
8808         plane_config->fb = intel_fb;
8809 }
8810
8811 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8812                                struct intel_crtc_state *pipe_config)
8813 {
8814         struct drm_device *dev = crtc->base.dev;
8815         struct drm_i915_private *dev_priv = to_i915(dev);
8816         enum pipe pipe = crtc->pipe;
8817         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8818         struct dpll clock;
8819         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8820         int refclk = 100000;
8821
8822         /* In case of DSI, DPLL will not be used */
8823         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8824                 return;
8825
8826         vlv_dpio_get(dev_priv);
8827         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8828         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8829         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8830         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8831         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8832         vlv_dpio_put(dev_priv);
8833
8834         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8835         clock.m2 = (pll_dw0 & 0xff) << 22;
8836         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8837                 clock.m2 |= pll_dw2 & 0x3fffff;
8838         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8839         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8840         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8841
8842         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8843 }
8844
8845 static enum intel_output_format
8846 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
8847 {
8848         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8849         u32 tmp;
8850
8851         tmp = I915_READ(PIPEMISC(crtc->pipe));
8852
8853         if (tmp & PIPEMISC_YUV420_ENABLE) {
8854                 /* We support 4:2:0 in full blend mode only */
8855                 WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
8856
8857                 return INTEL_OUTPUT_FORMAT_YCBCR420;
8858         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8859                 return INTEL_OUTPUT_FORMAT_YCBCR444;
8860         } else {
8861                 return INTEL_OUTPUT_FORMAT_RGB;
8862         }
8863 }
8864
8865 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8866 {
8867         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8868         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8869         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8870         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8871         u32 tmp;
8872
8873         tmp = I915_READ(DSPCNTR(i9xx_plane));
8874
8875         if (tmp & DISPPLANE_GAMMA_ENABLE)
8876                 crtc_state->gamma_enable = true;
8877
8878         if (!HAS_GMCH(dev_priv) &&
8879             tmp & DISPPLANE_PIPE_CSC_ENABLE)
8880                 crtc_state->csc_enable = true;
8881 }
8882
8883 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8884                                  struct intel_crtc_state *pipe_config)
8885 {
8886         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8887         enum intel_display_power_domain power_domain;
8888         intel_wakeref_t wakeref;
8889         u32 tmp;
8890         bool ret;
8891
8892         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8893         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8894         if (!wakeref)
8895                 return false;
8896
8897         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8898         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8899         pipe_config->shared_dpll = NULL;
8900         pipe_config->master_transcoder = INVALID_TRANSCODER;
8901
8902         ret = false;
8903
8904         tmp = I915_READ(PIPECONF(crtc->pipe));
8905         if (!(tmp & PIPECONF_ENABLE))
8906                 goto out;
8907
8908         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8909             IS_CHERRYVIEW(dev_priv)) {
8910                 switch (tmp & PIPECONF_BPC_MASK) {
8911                 case PIPECONF_6BPC:
8912                         pipe_config->pipe_bpp = 18;
8913                         break;
8914                 case PIPECONF_8BPC:
8915                         pipe_config->pipe_bpp = 24;
8916                         break;
8917                 case PIPECONF_10BPC:
8918                         pipe_config->pipe_bpp = 30;
8919                         break;
8920                 default:
8921                         break;
8922                 }
8923         }
8924
8925         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8926             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8927                 pipe_config->limited_color_range = true;
8928
8929         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8930                 PIPECONF_GAMMA_MODE_SHIFT;
8931
8932         if (IS_CHERRYVIEW(dev_priv))
8933                 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8934
8935         i9xx_get_pipe_color_config(pipe_config);
8936         intel_color_get_config(pipe_config);
8937
8938         if (INTEL_GEN(dev_priv) < 4)
8939                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8940
8941         intel_get_pipe_timings(crtc, pipe_config);
8942         intel_get_pipe_src_size(crtc, pipe_config);
8943
8944         i9xx_get_pfit_config(crtc, pipe_config);
8945
8946         if (INTEL_GEN(dev_priv) >= 4) {
8947                 /* No way to read it out on pipes B and C */
8948                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8949                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8950                 else
8951                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8952                 pipe_config->pixel_multiplier =
8953                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8954                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8955                 pipe_config->dpll_hw_state.dpll_md = tmp;
8956         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8957                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8958                 tmp = I915_READ(DPLL(crtc->pipe));
8959                 pipe_config->pixel_multiplier =
8960                         ((tmp & SDVO_MULTIPLIER_MASK)
8961                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8962         } else {
8963                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8964                  * port and will be fixed up in the encoder->get_config
8965                  * function. */
8966                 pipe_config->pixel_multiplier = 1;
8967         }
8968         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8969         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8970                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8971                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8972         } else {
8973                 /* Mask out read-only status bits. */
8974                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8975                                                      DPLL_PORTC_READY_MASK |
8976                                                      DPLL_PORTB_READY_MASK);
8977         }
8978
8979         if (IS_CHERRYVIEW(dev_priv))
8980                 chv_crtc_clock_get(crtc, pipe_config);
8981         else if (IS_VALLEYVIEW(dev_priv))
8982                 vlv_crtc_clock_get(crtc, pipe_config);
8983         else
8984                 i9xx_crtc_clock_get(crtc, pipe_config);
8985
8986         /*
8987          * Normally the dotclock is filled in by the encoder .get_config()
8988          * but in case the pipe is enabled w/o any ports we need a sane
8989          * default.
8990          */
8991         pipe_config->hw.adjusted_mode.crtc_clock =
8992                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8993
8994         ret = true;
8995
8996 out:
8997         intel_display_power_put(dev_priv, power_domain, wakeref);
8998
8999         return ret;
9000 }
9001
9002 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
9003 {
9004         struct intel_encoder *encoder;
9005         int i;
9006         u32 val, final;
9007         bool has_lvds = false;
9008         bool has_cpu_edp = false;
9009         bool has_panel = false;
9010         bool has_ck505 = false;
9011         bool can_ssc = false;
9012         bool using_ssc_source = false;
9013
9014         /* We need to take the global config into account */
9015         for_each_intel_encoder(&dev_priv->drm, encoder) {
9016                 switch (encoder->type) {
9017                 case INTEL_OUTPUT_LVDS:
9018                         has_panel = true;
9019                         has_lvds = true;
9020                         break;
9021                 case INTEL_OUTPUT_EDP:
9022                         has_panel = true;
9023                         if (encoder->port == PORT_A)
9024                                 has_cpu_edp = true;
9025                         break;
9026                 default:
9027                         break;
9028                 }
9029         }
9030
9031         if (HAS_PCH_IBX(dev_priv)) {
9032                 has_ck505 = dev_priv->vbt.display_clock_mode;
9033                 can_ssc = has_ck505;
9034         } else {
9035                 has_ck505 = false;
9036                 can_ssc = true;
9037         }
9038
9039         /* Check if any DPLLs are using the SSC source */
9040         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9041                 u32 temp = I915_READ(PCH_DPLL(i));
9042
9043                 if (!(temp & DPLL_VCO_ENABLE))
9044                         continue;
9045
9046                 if ((temp & PLL_REF_INPUT_MASK) ==
9047                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9048                         using_ssc_source = true;
9049                         break;
9050                 }
9051         }
9052
9053         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9054                       has_panel, has_lvds, has_ck505, using_ssc_source);
9055
9056         /* Ironlake: try to setup display ref clock before DPLL
9057          * enabling. This is only under driver's control after
9058          * PCH B stepping, previous chipset stepping should be
9059          * ignoring this setting.
9060          */
9061         val = I915_READ(PCH_DREF_CONTROL);
9062
9063         /* As we must carefully and slowly disable/enable each source in turn,
9064          * compute the final state we want first and check if we need to
9065          * make any changes at all.
9066          */
9067         final = val;
9068         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9069         if (has_ck505)
9070                 final |= DREF_NONSPREAD_CK505_ENABLE;
9071         else
9072                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9073
9074         final &= ~DREF_SSC_SOURCE_MASK;
9075         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9076         final &= ~DREF_SSC1_ENABLE;
9077
9078         if (has_panel) {
9079                 final |= DREF_SSC_SOURCE_ENABLE;
9080
9081                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9082                         final |= DREF_SSC1_ENABLE;
9083
9084                 if (has_cpu_edp) {
9085                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9086                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9087                         else
9088                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9089                 } else
9090                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9091         } else if (using_ssc_source) {
9092                 final |= DREF_SSC_SOURCE_ENABLE;
9093                 final |= DREF_SSC1_ENABLE;
9094         }
9095
9096         if (final == val)
9097                 return;
9098
9099         /* Always enable nonspread source */
9100         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9101
9102         if (has_ck505)
9103                 val |= DREF_NONSPREAD_CK505_ENABLE;
9104         else
9105                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9106
9107         if (has_panel) {
9108                 val &= ~DREF_SSC_SOURCE_MASK;
9109                 val |= DREF_SSC_SOURCE_ENABLE;
9110
9111                 /* SSC must be turned on before enabling the CPU output  */
9112                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9113                         DRM_DEBUG_KMS("Using SSC on panel\n");
9114                         val |= DREF_SSC1_ENABLE;
9115                 } else
9116                         val &= ~DREF_SSC1_ENABLE;
9117
9118                 /* Get SSC going before enabling the outputs */
9119                 I915_WRITE(PCH_DREF_CONTROL, val);
9120                 POSTING_READ(PCH_DREF_CONTROL);
9121                 udelay(200);
9122
9123                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9124
9125                 /* Enable CPU source on CPU attached eDP */
9126                 if (has_cpu_edp) {
9127                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9128                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9129                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9130                         } else
9131                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9132                 } else
9133                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9134
9135                 I915_WRITE(PCH_DREF_CONTROL, val);
9136                 POSTING_READ(PCH_DREF_CONTROL);
9137                 udelay(200);
9138         } else {
9139                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9140
9141                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9142
9143                 /* Turn off CPU output */
9144                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9145
9146                 I915_WRITE(PCH_DREF_CONTROL, val);
9147                 POSTING_READ(PCH_DREF_CONTROL);
9148                 udelay(200);
9149
9150                 if (!using_ssc_source) {
9151                         DRM_DEBUG_KMS("Disabling SSC source\n");
9152
9153                         /* Turn off the SSC source */
9154                         val &= ~DREF_SSC_SOURCE_MASK;
9155                         val |= DREF_SSC_SOURCE_DISABLE;
9156
9157                         /* Turn off SSC1 */
9158                         val &= ~DREF_SSC1_ENABLE;
9159
9160                         I915_WRITE(PCH_DREF_CONTROL, val);
9161                         POSTING_READ(PCH_DREF_CONTROL);
9162                         udelay(200);
9163                 }
9164         }
9165
9166         BUG_ON(val != final);
9167 }
9168
9169 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9170 {
9171         u32 tmp;
9172
9173         tmp = I915_READ(SOUTH_CHICKEN2);
9174         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9175         I915_WRITE(SOUTH_CHICKEN2, tmp);
9176
9177         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9178                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9179                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9180
9181         tmp = I915_READ(SOUTH_CHICKEN2);
9182         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9183         I915_WRITE(SOUTH_CHICKEN2, tmp);
9184
9185         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9186                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9187                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9188 }
9189
9190 /* WaMPhyProgramming:hsw */
9191 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9192 {
9193         u32 tmp;
9194
9195         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9196         tmp &= ~(0xFF << 24);
9197         tmp |= (0x12 << 24);
9198         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9199
9200         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9201         tmp |= (1 << 11);
9202         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9203
9204         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9205         tmp |= (1 << 11);
9206         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9207
9208         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9209         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9210         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9211
9212         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9213         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9214         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9215
9216         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9217         tmp &= ~(7 << 13);
9218         tmp |= (5 << 13);
9219         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9220
9221         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9222         tmp &= ~(7 << 13);
9223         tmp |= (5 << 13);
9224         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9225
9226         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9227         tmp &= ~0xFF;
9228         tmp |= 0x1C;
9229         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9230
9231         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9232         tmp &= ~0xFF;
9233         tmp |= 0x1C;
9234         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9235
9236         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9237         tmp &= ~(0xFF << 16);
9238         tmp |= (0x1C << 16);
9239         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9240
9241         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9242         tmp &= ~(0xFF << 16);
9243         tmp |= (0x1C << 16);
9244         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9245
9246         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9247         tmp |= (1 << 27);
9248         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9249
9250         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9251         tmp |= (1 << 27);
9252         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9253
9254         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9255         tmp &= ~(0xF << 28);
9256         tmp |= (4 << 28);
9257         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9258
9259         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9260         tmp &= ~(0xF << 28);
9261         tmp |= (4 << 28);
9262         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9263 }
9264
9265 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9266  * Programming" based on the parameters passed:
9267  * - Sequence to enable CLKOUT_DP
9268  * - Sequence to enable CLKOUT_DP without spread
9269  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9270  */
9271 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9272                                  bool with_spread, bool with_fdi)
9273 {
9274         u32 reg, tmp;
9275
9276         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9277                 with_spread = true;
9278         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9279             with_fdi, "LP PCH doesn't have FDI\n"))
9280                 with_fdi = false;
9281
9282         mutex_lock(&dev_priv->sb_lock);
9283
9284         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9285         tmp &= ~SBI_SSCCTL_DISABLE;
9286         tmp |= SBI_SSCCTL_PATHALT;
9287         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9288
9289         udelay(24);
9290
9291         if (with_spread) {
9292                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9293                 tmp &= ~SBI_SSCCTL_PATHALT;
9294                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9295
9296                 if (with_fdi) {
9297                         lpt_reset_fdi_mphy(dev_priv);
9298                         lpt_program_fdi_mphy(dev_priv);
9299                 }
9300         }
9301
9302         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9303         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9304         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9305         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9306
9307         mutex_unlock(&dev_priv->sb_lock);
9308 }
9309
9310 /* Sequence to disable CLKOUT_DP */
9311 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9312 {
9313         u32 reg, tmp;
9314
9315         mutex_lock(&dev_priv->sb_lock);
9316
9317         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9318         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9319         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9320         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9321
9322         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9323         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9324                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9325                         tmp |= SBI_SSCCTL_PATHALT;
9326                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9327                         udelay(32);
9328                 }
9329                 tmp |= SBI_SSCCTL_DISABLE;
9330                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9331         }
9332
9333         mutex_unlock(&dev_priv->sb_lock);
9334 }
9335
9336 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9337
9338 static const u16 sscdivintphase[] = {
9339         [BEND_IDX( 50)] = 0x3B23,
9340         [BEND_IDX( 45)] = 0x3B23,
9341         [BEND_IDX( 40)] = 0x3C23,
9342         [BEND_IDX( 35)] = 0x3C23,
9343         [BEND_IDX( 30)] = 0x3D23,
9344         [BEND_IDX( 25)] = 0x3D23,
9345         [BEND_IDX( 20)] = 0x3E23,
9346         [BEND_IDX( 15)] = 0x3E23,
9347         [BEND_IDX( 10)] = 0x3F23,
9348         [BEND_IDX(  5)] = 0x3F23,
9349         [BEND_IDX(  0)] = 0x0025,
9350         [BEND_IDX( -5)] = 0x0025,
9351         [BEND_IDX(-10)] = 0x0125,
9352         [BEND_IDX(-15)] = 0x0125,
9353         [BEND_IDX(-20)] = 0x0225,
9354         [BEND_IDX(-25)] = 0x0225,
9355         [BEND_IDX(-30)] = 0x0325,
9356         [BEND_IDX(-35)] = 0x0325,
9357         [BEND_IDX(-40)] = 0x0425,
9358         [BEND_IDX(-45)] = 0x0425,
9359         [BEND_IDX(-50)] = 0x0525,
9360 };
9361
9362 /*
9363  * Bend CLKOUT_DP
9364  * steps -50 to 50 inclusive, in steps of 5
9365  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9366  * change in clock period = -(steps / 10) * 5.787 ps
9367  */
9368 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9369 {
9370         u32 tmp;
9371         int idx = BEND_IDX(steps);
9372
9373         if (WARN_ON(steps % 5 != 0))
9374                 return;
9375
9376         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9377                 return;
9378
9379         mutex_lock(&dev_priv->sb_lock);
9380
9381         if (steps % 10 != 0)
9382                 tmp = 0xAAAAAAAB;
9383         else
9384                 tmp = 0x00000000;
9385         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9386
9387         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9388         tmp &= 0xffff0000;
9389         tmp |= sscdivintphase[idx];
9390         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9391
9392         mutex_unlock(&dev_priv->sb_lock);
9393 }
9394
9395 #undef BEND_IDX
9396
9397 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9398 {
9399         u32 fuse_strap = I915_READ(FUSE_STRAP);
9400         u32 ctl = I915_READ(SPLL_CTL);
9401
9402         if ((ctl & SPLL_PLL_ENABLE) == 0)
9403                 return false;
9404
9405         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9406             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9407                 return true;
9408
9409         if (IS_BROADWELL(dev_priv) &&
9410             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9411                 return true;
9412
9413         return false;
9414 }
9415
9416 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9417                                enum intel_dpll_id id)
9418 {
9419         u32 fuse_strap = I915_READ(FUSE_STRAP);
9420         u32 ctl = I915_READ(WRPLL_CTL(id));
9421
9422         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9423                 return false;
9424
9425         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9426                 return true;
9427
9428         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9429             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9430             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9431                 return true;
9432
9433         return false;
9434 }
9435
9436 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9437 {
9438         struct intel_encoder *encoder;
9439         bool has_fdi = false;
9440
9441         for_each_intel_encoder(&dev_priv->drm, encoder) {
9442                 switch (encoder->type) {
9443                 case INTEL_OUTPUT_ANALOG:
9444                         has_fdi = true;
9445                         break;
9446                 default:
9447                         break;
9448                 }
9449         }
9450
9451         /*
9452          * The BIOS may have decided to use the PCH SSC
9453          * reference so we must not disable it until the
9454          * relevant PLLs have stopped relying on it. We'll
9455          * just leave the PCH SSC reference enabled in case
9456          * any active PLL is using it. It will get disabled
9457          * after runtime suspend if we don't have FDI.
9458          *
9459          * TODO: Move the whole reference clock handling
9460          * to the modeset sequence proper so that we can
9461          * actually enable/disable/reconfigure these things
9462          * safely. To do that we need to introduce a real
9463          * clock hierarchy. That would also allow us to do
9464          * clock bending finally.
9465          */
9466         dev_priv->pch_ssc_use = 0;
9467
9468         if (spll_uses_pch_ssc(dev_priv)) {
9469                 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9470                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9471         }
9472
9473         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9474                 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9475                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9476         }
9477
9478         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9479                 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9480                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9481         }
9482
9483         if (dev_priv->pch_ssc_use)
9484                 return;
9485
9486         if (has_fdi) {
9487                 lpt_bend_clkout_dp(dev_priv, 0);
9488                 lpt_enable_clkout_dp(dev_priv, true, true);
9489         } else {
9490                 lpt_disable_clkout_dp(dev_priv);
9491         }
9492 }
9493
9494 /*
9495  * Initialize reference clocks when the driver loads
9496  */
9497 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9498 {
9499         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9500                 ironlake_init_pch_refclk(dev_priv);
9501         else if (HAS_PCH_LPT(dev_priv))
9502                 lpt_init_pch_refclk(dev_priv);
9503 }
9504
9505 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9506 {
9507         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9508         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9509         enum pipe pipe = crtc->pipe;
9510         u32 val;
9511
9512         val = 0;
9513
9514         switch (crtc_state->pipe_bpp) {
9515         case 18:
9516                 val |= PIPECONF_6BPC;
9517                 break;
9518         case 24:
9519                 val |= PIPECONF_8BPC;
9520                 break;
9521         case 30:
9522                 val |= PIPECONF_10BPC;
9523                 break;
9524         case 36:
9525                 val |= PIPECONF_12BPC;
9526                 break;
9527         default:
9528                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9529                 BUG();
9530         }
9531
9532         if (crtc_state->dither)
9533                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9534
9535         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9536                 val |= PIPECONF_INTERLACED_ILK;
9537         else
9538                 val |= PIPECONF_PROGRESSIVE;
9539
9540         /*
9541          * This would end up with an odd purple hue over
9542          * the entire display. Make sure we don't do it.
9543          */
9544         WARN_ON(crtc_state->limited_color_range &&
9545                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
9546
9547         if (crtc_state->limited_color_range)
9548                 val |= PIPECONF_COLOR_RANGE_SELECT;
9549
9550         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9551                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
9552
9553         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9554
9555         I915_WRITE(PIPECONF(pipe), val);
9556         POSTING_READ(PIPECONF(pipe));
9557 }
9558
9559 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9560 {
9561         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9562         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9563         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9564         u32 val = 0;
9565
9566         if (IS_HASWELL(dev_priv) && crtc_state->dither)
9567                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9568
9569         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9570                 val |= PIPECONF_INTERLACED_ILK;
9571         else
9572                 val |= PIPECONF_PROGRESSIVE;
9573
9574         if (IS_HASWELL(dev_priv) &&
9575             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9576                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
9577
9578         I915_WRITE(PIPECONF(cpu_transcoder), val);
9579         POSTING_READ(PIPECONF(cpu_transcoder));
9580 }
9581
9582 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9583 {
9584         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9585         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9586         u32 val = 0;
9587
9588         switch (crtc_state->pipe_bpp) {
9589         case 18:
9590                 val |= PIPEMISC_DITHER_6_BPC;
9591                 break;
9592         case 24:
9593                 val |= PIPEMISC_DITHER_8_BPC;
9594                 break;
9595         case 30:
9596                 val |= PIPEMISC_DITHER_10_BPC;
9597                 break;
9598         case 36:
9599                 val |= PIPEMISC_DITHER_12_BPC;
9600                 break;
9601         default:
9602                 MISSING_CASE(crtc_state->pipe_bpp);
9603                 break;
9604         }
9605
9606         if (crtc_state->dither)
9607                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9608
9609         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9610             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9611                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9612
9613         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9614                 val |= PIPEMISC_YUV420_ENABLE |
9615                         PIPEMISC_YUV420_MODE_FULL_BLEND;
9616
9617         if (INTEL_GEN(dev_priv) >= 11 &&
9618             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9619                                            BIT(PLANE_CURSOR))) == 0)
9620                 val |= PIPEMISC_HDR_MODE_PRECISION;
9621
9622         I915_WRITE(PIPEMISC(crtc->pipe), val);
9623 }
9624
9625 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9626 {
9627         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9628         u32 tmp;
9629
9630         tmp = I915_READ(PIPEMISC(crtc->pipe));
9631
9632         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9633         case PIPEMISC_DITHER_6_BPC:
9634                 return 18;
9635         case PIPEMISC_DITHER_8_BPC:
9636                 return 24;
9637         case PIPEMISC_DITHER_10_BPC:
9638                 return 30;
9639         case PIPEMISC_DITHER_12_BPC:
9640                 return 36;
9641         default:
9642                 MISSING_CASE(tmp);
9643                 return 0;
9644         }
9645 }
9646
9647 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9648 {
9649         /*
9650          * Account for spread spectrum to avoid
9651          * oversubscribing the link. Max center spread
9652          * is 2.5%; use 5% for safety's sake.
9653          */
9654         u32 bps = target_clock * bpp * 21 / 20;
9655         return DIV_ROUND_UP(bps, link_bw * 8);
9656 }
9657
9658 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9659 {
9660         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9661 }
9662
9663 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9664                                   struct intel_crtc_state *crtc_state,
9665                                   struct dpll *reduced_clock)
9666 {
9667         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9668         u32 dpll, fp, fp2;
9669         int factor;
9670
9671         /* Enable autotuning of the PLL clock (if permissible) */
9672         factor = 21;
9673         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9674                 if ((intel_panel_use_ssc(dev_priv) &&
9675                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9676                     (HAS_PCH_IBX(dev_priv) &&
9677                      intel_is_dual_link_lvds(dev_priv)))
9678                         factor = 25;
9679         } else if (crtc_state->sdvo_tv_clock) {
9680                 factor = 20;
9681         }
9682
9683         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9684
9685         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9686                 fp |= FP_CB_TUNE;
9687
9688         if (reduced_clock) {
9689                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9690
9691                 if (reduced_clock->m < factor * reduced_clock->n)
9692                         fp2 |= FP_CB_TUNE;
9693         } else {
9694                 fp2 = fp;
9695         }
9696
9697         dpll = 0;
9698
9699         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9700                 dpll |= DPLLB_MODE_LVDS;
9701         else
9702                 dpll |= DPLLB_MODE_DAC_SERIAL;
9703
9704         dpll |= (crtc_state->pixel_multiplier - 1)
9705                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9706
9707         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9708             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9709                 dpll |= DPLL_SDVO_HIGH_SPEED;
9710
9711         if (intel_crtc_has_dp_encoder(crtc_state))
9712                 dpll |= DPLL_SDVO_HIGH_SPEED;
9713
9714         /*
9715          * The high speed IO clock is only really required for
9716          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9717          * possible to share the DPLL between CRT and HDMI. Enabling
9718          * the clock needlessly does no real harm, except use up a
9719          * bit of power potentially.
9720          *
9721          * We'll limit this to IVB with 3 pipes, since it has only two
9722          * DPLLs and so DPLL sharing is the only way to get three pipes
9723          * driving PCH ports at the same time. On SNB we could do this,
9724          * and potentially avoid enabling the second DPLL, but it's not
9725          * clear if it''s a win or loss power wise. No point in doing
9726          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9727          */
9728         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
9729             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9730                 dpll |= DPLL_SDVO_HIGH_SPEED;
9731
9732         /* compute bitmask from p1 value */
9733         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9734         /* also FPA1 */
9735         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9736
9737         switch (crtc_state->dpll.p2) {
9738         case 5:
9739                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9740                 break;
9741         case 7:
9742                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9743                 break;
9744         case 10:
9745                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9746                 break;
9747         case 14:
9748                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9749                 break;
9750         }
9751
9752         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9753             intel_panel_use_ssc(dev_priv))
9754                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9755         else
9756                 dpll |= PLL_REF_INPUT_DREFCLK;
9757
9758         dpll |= DPLL_VCO_ENABLE;
9759
9760         crtc_state->dpll_hw_state.dpll = dpll;
9761         crtc_state->dpll_hw_state.fp0 = fp;
9762         crtc_state->dpll_hw_state.fp1 = fp2;
9763 }
9764
9765 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9766                                        struct intel_crtc_state *crtc_state)
9767 {
9768         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9769         struct intel_atomic_state *state =
9770                 to_intel_atomic_state(crtc_state->uapi.state);
9771         const struct intel_limit *limit;
9772         int refclk = 120000;
9773
9774         memset(&crtc_state->dpll_hw_state, 0,
9775                sizeof(crtc_state->dpll_hw_state));
9776
9777         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9778         if (!crtc_state->has_pch_encoder)
9779                 return 0;
9780
9781         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9782                 if (intel_panel_use_ssc(dev_priv)) {
9783                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9784                                       dev_priv->vbt.lvds_ssc_freq);
9785                         refclk = dev_priv->vbt.lvds_ssc_freq;
9786                 }
9787
9788                 if (intel_is_dual_link_lvds(dev_priv)) {
9789                         if (refclk == 100000)
9790                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9791                         else
9792                                 limit = &intel_limits_ironlake_dual_lvds;
9793                 } else {
9794                         if (refclk == 100000)
9795                                 limit = &intel_limits_ironlake_single_lvds_100m;
9796                         else
9797                                 limit = &intel_limits_ironlake_single_lvds;
9798                 }
9799         } else {
9800                 limit = &intel_limits_ironlake_dac;
9801         }
9802
9803         if (!crtc_state->clock_set &&
9804             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9805                                 refclk, NULL, &crtc_state->dpll)) {
9806                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9807                 return -EINVAL;
9808         }
9809
9810         ironlake_compute_dpll(crtc, crtc_state, NULL);
9811
9812         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9813                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9814                               pipe_name(crtc->pipe));
9815                 return -EINVAL;
9816         }
9817
9818         return 0;
9819 }
9820
9821 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9822                                          struct intel_link_m_n *m_n)
9823 {
9824         struct drm_device *dev = crtc->base.dev;
9825         struct drm_i915_private *dev_priv = to_i915(dev);
9826         enum pipe pipe = crtc->pipe;
9827
9828         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9829         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9830         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9831                 & ~TU_SIZE_MASK;
9832         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9833         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9834                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9835 }
9836
9837 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9838                                          enum transcoder transcoder,
9839                                          struct intel_link_m_n *m_n,
9840                                          struct intel_link_m_n *m2_n2)
9841 {
9842         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9843         enum pipe pipe = crtc->pipe;
9844
9845         if (INTEL_GEN(dev_priv) >= 5) {
9846                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9847                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9848                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9849                         & ~TU_SIZE_MASK;
9850                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9851                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9852                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9853
9854                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9855                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9856                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9857                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9858                                         & ~TU_SIZE_MASK;
9859                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9860                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9861                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9862                 }
9863         } else {
9864                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9865                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9866                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9867                         & ~TU_SIZE_MASK;
9868                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9869                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9870                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9871         }
9872 }
9873
9874 void intel_dp_get_m_n(struct intel_crtc *crtc,
9875                       struct intel_crtc_state *pipe_config)
9876 {
9877         if (pipe_config->has_pch_encoder)
9878                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9879         else
9880                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9881                                              &pipe_config->dp_m_n,
9882                                              &pipe_config->dp_m2_n2);
9883 }
9884
9885 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9886                                         struct intel_crtc_state *pipe_config)
9887 {
9888         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9889                                      &pipe_config->fdi_m_n, NULL);
9890 }
9891
9892 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9893                                     struct intel_crtc_state *pipe_config)
9894 {
9895         struct drm_device *dev = crtc->base.dev;
9896         struct drm_i915_private *dev_priv = to_i915(dev);
9897         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9898         u32 ps_ctrl = 0;
9899         int id = -1;
9900         int i;
9901
9902         /* find scaler attached to this pipe */
9903         for (i = 0; i < crtc->num_scalers; i++) {
9904                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9905                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9906                         id = i;
9907                         pipe_config->pch_pfit.enabled = true;
9908                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9909                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9910                         scaler_state->scalers[i].in_use = true;
9911                         break;
9912                 }
9913         }
9914
9915         scaler_state->scaler_id = id;
9916         if (id >= 0) {
9917                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9918         } else {
9919                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9920         }
9921 }
9922
9923 static void
9924 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9925                                  struct intel_initial_plane_config *plane_config)
9926 {
9927         struct drm_device *dev = crtc->base.dev;
9928         struct drm_i915_private *dev_priv = to_i915(dev);
9929         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9930         enum plane_id plane_id = plane->id;
9931         enum pipe pipe;
9932         u32 val, base, offset, stride_mult, tiling, alpha;
9933         int fourcc, pixel_format;
9934         unsigned int aligned_height;
9935         struct drm_framebuffer *fb;
9936         struct intel_framebuffer *intel_fb;
9937
9938         if (!plane->get_hw_state(plane, &pipe))
9939                 return;
9940
9941         WARN_ON(pipe != crtc->pipe);
9942
9943         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9944         if (!intel_fb) {
9945                 DRM_DEBUG_KMS("failed to alloc fb\n");
9946                 return;
9947         }
9948
9949         fb = &intel_fb->base;
9950
9951         fb->dev = dev;
9952
9953         val = I915_READ(PLANE_CTL(pipe, plane_id));
9954
9955         if (INTEL_GEN(dev_priv) >= 11)
9956                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9957         else
9958                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9959
9960         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9961                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9962                 alpha &= PLANE_COLOR_ALPHA_MASK;
9963         } else {
9964                 alpha = val & PLANE_CTL_ALPHA_MASK;
9965         }
9966
9967         fourcc = skl_format_to_fourcc(pixel_format,
9968                                       val & PLANE_CTL_ORDER_RGBX, alpha);
9969         fb->format = drm_format_info(fourcc);
9970
9971         tiling = val & PLANE_CTL_TILED_MASK;
9972         switch (tiling) {
9973         case PLANE_CTL_TILED_LINEAR:
9974                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9975                 break;
9976         case PLANE_CTL_TILED_X:
9977                 plane_config->tiling = I915_TILING_X;
9978                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9979                 break;
9980         case PLANE_CTL_TILED_Y:
9981                 plane_config->tiling = I915_TILING_Y;
9982                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9983                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
9984                 else
9985                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
9986                 break;
9987         case PLANE_CTL_TILED_YF:
9988                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9989                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
9990                 else
9991                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9992                 break;
9993         default:
9994                 MISSING_CASE(tiling);
9995                 goto error;
9996         }
9997
9998         /*
9999          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10000          * while i915 HW rotation is clockwise, thats why this swapping.
10001          */
10002         switch (val & PLANE_CTL_ROTATE_MASK) {
10003         case PLANE_CTL_ROTATE_0:
10004                 plane_config->rotation = DRM_MODE_ROTATE_0;
10005                 break;
10006         case PLANE_CTL_ROTATE_90:
10007                 plane_config->rotation = DRM_MODE_ROTATE_270;
10008                 break;
10009         case PLANE_CTL_ROTATE_180:
10010                 plane_config->rotation = DRM_MODE_ROTATE_180;
10011                 break;
10012         case PLANE_CTL_ROTATE_270:
10013                 plane_config->rotation = DRM_MODE_ROTATE_90;
10014                 break;
10015         }
10016
10017         if (INTEL_GEN(dev_priv) >= 10 &&
10018             val & PLANE_CTL_FLIP_HORIZONTAL)
10019                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10020
10021         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10022         plane_config->base = base;
10023
10024         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
10025
10026         val = I915_READ(PLANE_SIZE(pipe, plane_id));
10027         fb->height = ((val >> 16) & 0xffff) + 1;
10028         fb->width = ((val >> 0) & 0xffff) + 1;
10029
10030         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
10031         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10032         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10033
10034         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10035
10036         plane_config->size = fb->pitches[0] * aligned_height;
10037
10038         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10039                       crtc->base.name, plane->base.name, fb->width, fb->height,
10040                       fb->format->cpp[0] * 8, base, fb->pitches[0],
10041                       plane_config->size);
10042
10043         plane_config->fb = intel_fb;
10044         return;
10045
10046 error:
10047         kfree(intel_fb);
10048 }
10049
10050 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
10051                                      struct intel_crtc_state *pipe_config)
10052 {
10053         struct drm_device *dev = crtc->base.dev;
10054         struct drm_i915_private *dev_priv = to_i915(dev);
10055         u32 tmp;
10056
10057         tmp = I915_READ(PF_CTL(crtc->pipe));
10058
10059         if (tmp & PF_ENABLE) {
10060                 pipe_config->pch_pfit.enabled = true;
10061                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
10062                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
10063
10064                 /* We currently do not free assignements of panel fitters on
10065                  * ivb/hsw (since we don't use the higher upscaling modes which
10066                  * differentiates them) so just WARN about this case for now. */
10067                 if (IS_GEN(dev_priv, 7)) {
10068                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
10069                                 PF_PIPE_SEL_IVB(crtc->pipe));
10070                 }
10071         }
10072 }
10073
10074 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
10075                                      struct intel_crtc_state *pipe_config)
10076 {
10077         struct drm_device *dev = crtc->base.dev;
10078         struct drm_i915_private *dev_priv = to_i915(dev);
10079         enum intel_display_power_domain power_domain;
10080         intel_wakeref_t wakeref;
10081         u32 tmp;
10082         bool ret;
10083
10084         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10085         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10086         if (!wakeref)
10087                 return false;
10088
10089         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10090         pipe_config->shared_dpll = NULL;
10091         pipe_config->master_transcoder = INVALID_TRANSCODER;
10092
10093         ret = false;
10094         tmp = I915_READ(PIPECONF(crtc->pipe));
10095         if (!(tmp & PIPECONF_ENABLE))
10096                 goto out;
10097
10098         switch (tmp & PIPECONF_BPC_MASK) {
10099         case PIPECONF_6BPC:
10100                 pipe_config->pipe_bpp = 18;
10101                 break;
10102         case PIPECONF_8BPC:
10103                 pipe_config->pipe_bpp = 24;
10104                 break;
10105         case PIPECONF_10BPC:
10106                 pipe_config->pipe_bpp = 30;
10107                 break;
10108         case PIPECONF_12BPC:
10109                 pipe_config->pipe_bpp = 36;
10110                 break;
10111         default:
10112                 break;
10113         }
10114
10115         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10116                 pipe_config->limited_color_range = true;
10117
10118         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10119         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10120         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10121                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10122                 break;
10123         default:
10124                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10125                 break;
10126         }
10127
10128         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10129                 PIPECONF_GAMMA_MODE_SHIFT;
10130
10131         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10132
10133         i9xx_get_pipe_color_config(pipe_config);
10134         intel_color_get_config(pipe_config);
10135
10136         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10137                 struct intel_shared_dpll *pll;
10138                 enum intel_dpll_id pll_id;
10139
10140                 pipe_config->has_pch_encoder = true;
10141
10142                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
10143                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10144                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10145
10146                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10147
10148                 if (HAS_PCH_IBX(dev_priv)) {
10149                         /*
10150                          * The pipe->pch transcoder and pch transcoder->pll
10151                          * mapping is fixed.
10152                          */
10153                         pll_id = (enum intel_dpll_id) crtc->pipe;
10154                 } else {
10155                         tmp = I915_READ(PCH_DPLL_SEL);
10156                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10157                                 pll_id = DPLL_ID_PCH_PLL_B;
10158                         else
10159                                 pll_id= DPLL_ID_PCH_PLL_A;
10160                 }
10161
10162                 pipe_config->shared_dpll =
10163                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10164                 pll = pipe_config->shared_dpll;
10165
10166                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10167                                                 &pipe_config->dpll_hw_state));
10168
10169                 tmp = pipe_config->dpll_hw_state.dpll;
10170                 pipe_config->pixel_multiplier =
10171                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10172                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10173
10174                 ironlake_pch_clock_get(crtc, pipe_config);
10175         } else {
10176                 pipe_config->pixel_multiplier = 1;
10177         }
10178
10179         intel_get_pipe_timings(crtc, pipe_config);
10180         intel_get_pipe_src_size(crtc, pipe_config);
10181
10182         ironlake_get_pfit_config(crtc, pipe_config);
10183
10184         ret = true;
10185
10186 out:
10187         intel_display_power_put(dev_priv, power_domain, wakeref);
10188
10189         return ret;
10190 }
10191 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10192                                       struct intel_crtc_state *crtc_state)
10193 {
10194         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10195         struct intel_atomic_state *state =
10196                 to_intel_atomic_state(crtc_state->uapi.state);
10197
10198         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10199             INTEL_GEN(dev_priv) >= 11) {
10200                 struct intel_encoder *encoder =
10201                         intel_get_crtc_new_encoder(state, crtc_state);
10202
10203                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10204                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10205                                       pipe_name(crtc->pipe));
10206                         return -EINVAL;
10207                 }
10208         }
10209
10210         return 0;
10211 }
10212
10213 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10214                                    enum port port,
10215                                    struct intel_crtc_state *pipe_config)
10216 {
10217         enum intel_dpll_id id;
10218         u32 temp;
10219
10220         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10221         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10222
10223         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10224                 return;
10225
10226         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10227 }
10228
10229 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10230                                 enum port port,
10231                                 struct intel_crtc_state *pipe_config)
10232 {
10233         enum phy phy = intel_port_to_phy(dev_priv, port);
10234         enum icl_port_dpll_id port_dpll_id;
10235         enum intel_dpll_id id;
10236         u32 temp;
10237
10238         if (intel_phy_is_combo(dev_priv, phy)) {
10239                 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10240                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10241                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10242                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10243         } else if (intel_phy_is_tc(dev_priv, phy)) {
10244                 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10245
10246                 if (clk_sel == DDI_CLK_SEL_MG) {
10247                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10248                                                                     port));
10249                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10250                 } else {
10251                         WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10252                         id = DPLL_ID_ICL_TBTPLL;
10253                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10254                 }
10255         } else {
10256                 WARN(1, "Invalid port %x\n", port);
10257                 return;
10258         }
10259
10260         pipe_config->icl_port_dplls[port_dpll_id].pll =
10261                 intel_get_shared_dpll_by_id(dev_priv, id);
10262
10263         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10264 }
10265
10266 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10267                                 enum port port,
10268                                 struct intel_crtc_state *pipe_config)
10269 {
10270         enum intel_dpll_id id;
10271
10272         switch (port) {
10273         case PORT_A:
10274                 id = DPLL_ID_SKL_DPLL0;
10275                 break;
10276         case PORT_B:
10277                 id = DPLL_ID_SKL_DPLL1;
10278                 break;
10279         case PORT_C:
10280                 id = DPLL_ID_SKL_DPLL2;
10281                 break;
10282         default:
10283                 DRM_ERROR("Incorrect port type\n");
10284                 return;
10285         }
10286
10287         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10288 }
10289
10290 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10291                                 enum port port,
10292                                 struct intel_crtc_state *pipe_config)
10293 {
10294         enum intel_dpll_id id;
10295         u32 temp;
10296
10297         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10298         id = temp >> (port * 3 + 1);
10299
10300         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10301                 return;
10302
10303         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10304 }
10305
10306 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10307                                 enum port port,
10308                                 struct intel_crtc_state *pipe_config)
10309 {
10310         enum intel_dpll_id id;
10311         u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10312
10313         switch (ddi_pll_sel) {
10314         case PORT_CLK_SEL_WRPLL1:
10315                 id = DPLL_ID_WRPLL1;
10316                 break;
10317         case PORT_CLK_SEL_WRPLL2:
10318                 id = DPLL_ID_WRPLL2;
10319                 break;
10320         case PORT_CLK_SEL_SPLL:
10321                 id = DPLL_ID_SPLL;
10322                 break;
10323         case PORT_CLK_SEL_LCPLL_810:
10324                 id = DPLL_ID_LCPLL_810;
10325                 break;
10326         case PORT_CLK_SEL_LCPLL_1350:
10327                 id = DPLL_ID_LCPLL_1350;
10328                 break;
10329         case PORT_CLK_SEL_LCPLL_2700:
10330                 id = DPLL_ID_LCPLL_2700;
10331                 break;
10332         default:
10333                 MISSING_CASE(ddi_pll_sel);
10334                 /* fall through */
10335         case PORT_CLK_SEL_NONE:
10336                 return;
10337         }
10338
10339         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10340 }
10341
10342 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10343                                      struct intel_crtc_state *pipe_config,
10344                                      u64 *power_domain_mask,
10345                                      intel_wakeref_t *wakerefs)
10346 {
10347         struct drm_device *dev = crtc->base.dev;
10348         struct drm_i915_private *dev_priv = to_i915(dev);
10349         enum intel_display_power_domain power_domain;
10350         unsigned long panel_transcoder_mask = 0;
10351         unsigned long enabled_panel_transcoders = 0;
10352         enum transcoder panel_transcoder;
10353         intel_wakeref_t wf;
10354         u32 tmp;
10355
10356         if (INTEL_GEN(dev_priv) >= 11)
10357                 panel_transcoder_mask |=
10358                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10359
10360         if (HAS_TRANSCODER_EDP(dev_priv))
10361                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10362
10363         /*
10364          * The pipe->transcoder mapping is fixed with the exception of the eDP
10365          * and DSI transcoders handled below.
10366          */
10367         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10368
10369         /*
10370          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10371          * consistency and less surprising code; it's in always on power).
10372          */
10373         for_each_set_bit(panel_transcoder,
10374                          &panel_transcoder_mask,
10375                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10376                 bool force_thru = false;
10377                 enum pipe trans_pipe;
10378
10379                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10380                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10381                         continue;
10382
10383                 /*
10384                  * Log all enabled ones, only use the first one.
10385                  *
10386                  * FIXME: This won't work for two separate DSI displays.
10387                  */
10388                 enabled_panel_transcoders |= BIT(panel_transcoder);
10389                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10390                         continue;
10391
10392                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10393                 default:
10394                         WARN(1, "unknown pipe linked to transcoder %s\n",
10395                              transcoder_name(panel_transcoder));
10396                         /* fall through */
10397                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10398                         force_thru = true;
10399                         /* fall through */
10400                 case TRANS_DDI_EDP_INPUT_A_ON:
10401                         trans_pipe = PIPE_A;
10402                         break;
10403                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10404                         trans_pipe = PIPE_B;
10405                         break;
10406                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10407                         trans_pipe = PIPE_C;
10408                         break;
10409                 }
10410
10411                 if (trans_pipe == crtc->pipe) {
10412                         pipe_config->cpu_transcoder = panel_transcoder;
10413                         pipe_config->pch_pfit.force_thru = force_thru;
10414                 }
10415         }
10416
10417         /*
10418          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10419          */
10420         WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10421                 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10422
10423         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10424         WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10425
10426         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10427         if (!wf)
10428                 return false;
10429
10430         wakerefs[power_domain] = wf;
10431         *power_domain_mask |= BIT_ULL(power_domain);
10432
10433         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10434
10435         return tmp & PIPECONF_ENABLE;
10436 }
10437
10438 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10439                                          struct intel_crtc_state *pipe_config,
10440                                          u64 *power_domain_mask,
10441                                          intel_wakeref_t *wakerefs)
10442 {
10443         struct drm_device *dev = crtc->base.dev;
10444         struct drm_i915_private *dev_priv = to_i915(dev);
10445         enum intel_display_power_domain power_domain;
10446         enum transcoder cpu_transcoder;
10447         intel_wakeref_t wf;
10448         enum port port;
10449         u32 tmp;
10450
10451         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10452                 if (port == PORT_A)
10453                         cpu_transcoder = TRANSCODER_DSI_A;
10454                 else
10455                         cpu_transcoder = TRANSCODER_DSI_C;
10456
10457                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10458                 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10459
10460                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10461                 if (!wf)
10462                         continue;
10463
10464                 wakerefs[power_domain] = wf;
10465                 *power_domain_mask |= BIT_ULL(power_domain);
10466
10467                 /*
10468                  * The PLL needs to be enabled with a valid divider
10469                  * configuration, otherwise accessing DSI registers will hang
10470                  * the machine. See BSpec North Display Engine
10471                  * registers/MIPI[BXT]. We can break out here early, since we
10472                  * need the same DSI PLL to be enabled for both DSI ports.
10473                  */
10474                 if (!bxt_dsi_pll_is_enabled(dev_priv))
10475                         break;
10476
10477                 /* XXX: this works for video mode only */
10478                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10479                 if (!(tmp & DPI_ENABLE))
10480                         continue;
10481
10482                 tmp = I915_READ(MIPI_CTRL(port));
10483                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10484                         continue;
10485
10486                 pipe_config->cpu_transcoder = cpu_transcoder;
10487                 break;
10488         }
10489
10490         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10491 }
10492
10493 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10494                                        struct intel_crtc_state *pipe_config)
10495 {
10496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10497         struct intel_shared_dpll *pll;
10498         enum port port;
10499         u32 tmp;
10500
10501         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10502
10503         if (INTEL_GEN(dev_priv) >= 12)
10504                 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10505         else
10506                 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10507
10508         if (INTEL_GEN(dev_priv) >= 11)
10509                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10510         else if (IS_CANNONLAKE(dev_priv))
10511                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10512         else if (IS_GEN9_BC(dev_priv))
10513                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10514         else if (IS_GEN9_LP(dev_priv))
10515                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10516         else
10517                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10518
10519         pll = pipe_config->shared_dpll;
10520         if (pll) {
10521                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10522                                                 &pipe_config->dpll_hw_state));
10523         }
10524
10525         /*
10526          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10527          * DDI E. So just check whether this pipe is wired to DDI E and whether
10528          * the PCH transcoder is on.
10529          */
10530         if (INTEL_GEN(dev_priv) < 9 &&
10531             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10532                 pipe_config->has_pch_encoder = true;
10533
10534                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10535                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10536                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10537
10538                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10539         }
10540 }
10541
10542 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
10543                                                  enum transcoder cpu_transcoder)
10544 {
10545         u32 trans_port_sync, master_select;
10546
10547         trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
10548
10549         if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
10550                 return INVALID_TRANSCODER;
10551
10552         master_select = trans_port_sync &
10553                         PORT_SYNC_MODE_MASTER_SELECT_MASK;
10554         if (master_select == 0)
10555                 return TRANSCODER_EDP;
10556         else
10557                 return master_select - 1;
10558 }
10559
10560 static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
10561 {
10562         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
10563         u32 transcoders;
10564         enum transcoder cpu_transcoder;
10565
10566         crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
10567                                                                   crtc_state->cpu_transcoder);
10568
10569         transcoders = BIT(TRANSCODER_A) |
10570                 BIT(TRANSCODER_B) |
10571                 BIT(TRANSCODER_C) |
10572                 BIT(TRANSCODER_D);
10573         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
10574                 enum intel_display_power_domain power_domain;
10575                 intel_wakeref_t trans_wakeref;
10576
10577                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10578                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
10579                                                                    power_domain);
10580
10581                 if (!trans_wakeref)
10582                         continue;
10583
10584                 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
10585                     crtc_state->cpu_transcoder)
10586                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
10587
10588                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
10589         }
10590
10591         WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
10592                 crtc_state->sync_mode_slaves_mask);
10593 }
10594
10595 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10596                                     struct intel_crtc_state *pipe_config)
10597 {
10598         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10599         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10600         enum intel_display_power_domain power_domain;
10601         u64 power_domain_mask;
10602         bool active;
10603
10604         intel_crtc_init_scalers(crtc, pipe_config);
10605
10606         pipe_config->master_transcoder = INVALID_TRANSCODER;
10607
10608         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10609         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10610         if (!wf)
10611                 return false;
10612
10613         wakerefs[power_domain] = wf;
10614         power_domain_mask = BIT_ULL(power_domain);
10615
10616         pipe_config->shared_dpll = NULL;
10617
10618         active = hsw_get_transcoder_state(crtc, pipe_config,
10619                                           &power_domain_mask, wakerefs);
10620
10621         if (IS_GEN9_LP(dev_priv) &&
10622             bxt_get_dsi_transcoder_state(crtc, pipe_config,
10623                                          &power_domain_mask, wakerefs)) {
10624                 WARN_ON(active);
10625                 active = true;
10626         }
10627
10628         if (!active)
10629                 goto out;
10630
10631         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10632             INTEL_GEN(dev_priv) >= 11) {
10633                 haswell_get_ddi_port_state(crtc, pipe_config);
10634                 intel_get_pipe_timings(crtc, pipe_config);
10635         }
10636
10637         intel_get_pipe_src_size(crtc, pipe_config);
10638
10639         if (IS_HASWELL(dev_priv)) {
10640                 u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10641
10642                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
10643                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10644                 else
10645                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10646         } else {
10647                 pipe_config->output_format =
10648                         bdw_get_pipemisc_output_format(crtc);
10649
10650                 /*
10651                  * Currently there is no interface defined to
10652                  * check user preference between RGB/YCBCR444
10653                  * or YCBCR420. So the only possible case for
10654                  * YCBCR444 usage is driving YCBCR420 output
10655                  * with LSPCON, when pipe is configured for
10656                  * YCBCR444 output and LSPCON takes care of
10657                  * downsampling it.
10658                  */
10659                 pipe_config->lspcon_downsampling =
10660                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
10661         }
10662
10663         pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10664
10665         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10666
10667         if (INTEL_GEN(dev_priv) >= 9) {
10668                 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10669
10670                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10671                         pipe_config->gamma_enable = true;
10672
10673                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10674                         pipe_config->csc_enable = true;
10675         } else {
10676                 i9xx_get_pipe_color_config(pipe_config);
10677         }
10678
10679         intel_color_get_config(pipe_config);
10680
10681         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10682         WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10683
10684         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10685         if (wf) {
10686                 wakerefs[power_domain] = wf;
10687                 power_domain_mask |= BIT_ULL(power_domain);
10688
10689                 if (INTEL_GEN(dev_priv) >= 9)
10690                         skylake_get_pfit_config(crtc, pipe_config);
10691                 else
10692                         ironlake_get_pfit_config(crtc, pipe_config);
10693         }
10694
10695         if (hsw_crtc_supports_ips(crtc)) {
10696                 if (IS_HASWELL(dev_priv))
10697                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10698                 else {
10699                         /*
10700                          * We cannot readout IPS state on broadwell, set to
10701                          * true so we can set it to a defined state on first
10702                          * commit.
10703                          */
10704                         pipe_config->ips_enabled = true;
10705                 }
10706         }
10707
10708         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10709             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10710                 pipe_config->pixel_multiplier =
10711                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10712         } else {
10713                 pipe_config->pixel_multiplier = 1;
10714         }
10715
10716         if (INTEL_GEN(dev_priv) >= 11 &&
10717             !transcoder_is_dsi(pipe_config->cpu_transcoder))
10718                 icelake_get_trans_port_sync_config(pipe_config);
10719
10720 out:
10721         for_each_power_domain(power_domain, power_domain_mask)
10722                 intel_display_power_put(dev_priv,
10723                                         power_domain, wakerefs[power_domain]);
10724
10725         return active;
10726 }
10727
10728 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10729 {
10730         struct drm_i915_private *dev_priv =
10731                 to_i915(plane_state->uapi.plane->dev);
10732         const struct drm_framebuffer *fb = plane_state->hw.fb;
10733         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10734         u32 base;
10735
10736         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10737                 base = obj->phys_handle->busaddr;
10738         else
10739                 base = intel_plane_ggtt_offset(plane_state);
10740
10741         return base + plane_state->color_plane[0].offset;
10742 }
10743
10744 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10745 {
10746         int x = plane_state->uapi.dst.x1;
10747         int y = plane_state->uapi.dst.y1;
10748         u32 pos = 0;
10749
10750         if (x < 0) {
10751                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10752                 x = -x;
10753         }
10754         pos |= x << CURSOR_X_SHIFT;
10755
10756         if (y < 0) {
10757                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10758                 y = -y;
10759         }
10760         pos |= y << CURSOR_Y_SHIFT;
10761
10762         return pos;
10763 }
10764
10765 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10766 {
10767         const struct drm_mode_config *config =
10768                 &plane_state->uapi.plane->dev->mode_config;
10769         int width = drm_rect_width(&plane_state->uapi.dst);
10770         int height = drm_rect_height(&plane_state->uapi.dst);
10771
10772         return width > 0 && width <= config->cursor_width &&
10773                 height > 0 && height <= config->cursor_height;
10774 }
10775
10776 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10777 {
10778         struct drm_i915_private *dev_priv =
10779                 to_i915(plane_state->uapi.plane->dev);
10780         unsigned int rotation = plane_state->hw.rotation;
10781         int src_x, src_y;
10782         u32 offset;
10783         int ret;
10784
10785         ret = intel_plane_compute_gtt(plane_state);
10786         if (ret)
10787                 return ret;
10788
10789         if (!plane_state->uapi.visible)
10790                 return 0;
10791
10792         src_x = plane_state->uapi.src.x1 >> 16;
10793         src_y = plane_state->uapi.src.y1 >> 16;
10794
10795         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10796         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10797                                                     plane_state, 0);
10798
10799         if (src_x != 0 || src_y != 0) {
10800                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10801                 return -EINVAL;
10802         }
10803
10804         /*
10805          * Put the final coordinates back so that the src
10806          * coordinate checks will see the right values.
10807          */
10808         drm_rect_translate_to(&plane_state->uapi.src,
10809                               src_x << 16, src_y << 16);
10810
10811         /* ILK+ do this automagically in hardware */
10812         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
10813                 const struct drm_framebuffer *fb = plane_state->hw.fb;
10814                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
10815                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
10816
10817                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
10818         }
10819
10820         plane_state->color_plane[0].offset = offset;
10821         plane_state->color_plane[0].x = src_x;
10822         plane_state->color_plane[0].y = src_y;
10823
10824         return 0;
10825 }
10826
10827 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10828                               struct intel_plane_state *plane_state)
10829 {
10830         const struct drm_framebuffer *fb = plane_state->hw.fb;
10831         int ret;
10832
10833         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10834                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10835                 return -EINVAL;
10836         }
10837
10838         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
10839                                                   &crtc_state->uapi,
10840                                                   DRM_PLANE_HELPER_NO_SCALING,
10841                                                   DRM_PLANE_HELPER_NO_SCALING,
10842                                                   true, true);
10843         if (ret)
10844                 return ret;
10845
10846         /* Use the unclipped src/dst rectangles, which we program to hw */
10847         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
10848         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
10849
10850         ret = intel_cursor_check_surface(plane_state);
10851         if (ret)
10852                 return ret;
10853
10854         if (!plane_state->uapi.visible)
10855                 return 0;
10856
10857         ret = intel_plane_check_src_coordinates(plane_state);
10858         if (ret)
10859                 return ret;
10860
10861         return 0;
10862 }
10863
10864 static unsigned int
10865 i845_cursor_max_stride(struct intel_plane *plane,
10866                        u32 pixel_format, u64 modifier,
10867                        unsigned int rotation)
10868 {
10869         return 2048;
10870 }
10871
10872 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10873 {
10874         u32 cntl = 0;
10875
10876         if (crtc_state->gamma_enable)
10877                 cntl |= CURSOR_GAMMA_ENABLE;
10878
10879         return cntl;
10880 }
10881
10882 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10883                            const struct intel_plane_state *plane_state)
10884 {
10885         return CURSOR_ENABLE |
10886                 CURSOR_FORMAT_ARGB |
10887                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10888 }
10889
10890 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10891 {
10892         int width = drm_rect_width(&plane_state->uapi.dst);
10893
10894         /*
10895          * 845g/865g are only limited by the width of their cursors,
10896          * the height is arbitrary up to the precision of the register.
10897          */
10898         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10899 }
10900
10901 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10902                              struct intel_plane_state *plane_state)
10903 {
10904         const struct drm_framebuffer *fb = plane_state->hw.fb;
10905         int ret;
10906
10907         ret = intel_check_cursor(crtc_state, plane_state);
10908         if (ret)
10909                 return ret;
10910
10911         /* if we want to turn off the cursor ignore width and height */
10912         if (!fb)
10913                 return 0;
10914
10915         /* Check for which cursor types we support */
10916         if (!i845_cursor_size_ok(plane_state)) {
10917                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10918                           drm_rect_width(&plane_state->uapi.dst),
10919                           drm_rect_height(&plane_state->uapi.dst));
10920                 return -EINVAL;
10921         }
10922
10923         WARN_ON(plane_state->uapi.visible &&
10924                 plane_state->color_plane[0].stride != fb->pitches[0]);
10925
10926         switch (fb->pitches[0]) {
10927         case 256:
10928         case 512:
10929         case 1024:
10930         case 2048:
10931                 break;
10932         default:
10933                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10934                               fb->pitches[0]);
10935                 return -EINVAL;
10936         }
10937
10938         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10939
10940         return 0;
10941 }
10942
10943 static void i845_update_cursor(struct intel_plane *plane,
10944                                const struct intel_crtc_state *crtc_state,
10945                                const struct intel_plane_state *plane_state)
10946 {
10947         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10948         u32 cntl = 0, base = 0, pos = 0, size = 0;
10949         unsigned long irqflags;
10950
10951         if (plane_state && plane_state->uapi.visible) {
10952                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
10953                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
10954
10955                 cntl = plane_state->ctl |
10956                         i845_cursor_ctl_crtc(crtc_state);
10957
10958                 size = (height << 12) | width;
10959
10960                 base = intel_cursor_base(plane_state);
10961                 pos = intel_cursor_position(plane_state);
10962         }
10963
10964         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10965
10966         /* On these chipsets we can only modify the base/size/stride
10967          * whilst the cursor is disabled.
10968          */
10969         if (plane->cursor.base != base ||
10970             plane->cursor.size != size ||
10971             plane->cursor.cntl != cntl) {
10972                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10973                 I915_WRITE_FW(CURBASE(PIPE_A), base);
10974                 I915_WRITE_FW(CURSIZE, size);
10975                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10976                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
10977
10978                 plane->cursor.base = base;
10979                 plane->cursor.size = size;
10980                 plane->cursor.cntl = cntl;
10981         } else {
10982                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10983         }
10984
10985         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10986 }
10987
10988 static void i845_disable_cursor(struct intel_plane *plane,
10989                                 const struct intel_crtc_state *crtc_state)
10990 {
10991         i845_update_cursor(plane, crtc_state, NULL);
10992 }
10993
10994 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
10995                                      enum pipe *pipe)
10996 {
10997         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10998         enum intel_display_power_domain power_domain;
10999         intel_wakeref_t wakeref;
11000         bool ret;
11001
11002         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11003         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11004         if (!wakeref)
11005                 return false;
11006
11007         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11008
11009         *pipe = PIPE_A;
11010
11011         intel_display_power_put(dev_priv, power_domain, wakeref);
11012
11013         return ret;
11014 }
11015
11016 static unsigned int
11017 i9xx_cursor_max_stride(struct intel_plane *plane,
11018                        u32 pixel_format, u64 modifier,
11019                        unsigned int rotation)
11020 {
11021         return plane->base.dev->mode_config.cursor_width * 4;
11022 }
11023
11024 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11025 {
11026         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11027         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11028         u32 cntl = 0;
11029
11030         if (INTEL_GEN(dev_priv) >= 11)
11031                 return cntl;
11032
11033         if (crtc_state->gamma_enable)
11034                 cntl = MCURSOR_GAMMA_ENABLE;
11035
11036         if (crtc_state->csc_enable)
11037                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11038
11039         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11040                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11041
11042         return cntl;
11043 }
11044
11045 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11046                            const struct intel_plane_state *plane_state)
11047 {
11048         struct drm_i915_private *dev_priv =
11049                 to_i915(plane_state->uapi.plane->dev);
11050         u32 cntl = 0;
11051
11052         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11053                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11054
11055         switch (drm_rect_width(&plane_state->uapi.dst)) {
11056         case 64:
11057                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11058                 break;
11059         case 128:
11060                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11061                 break;
11062         case 256:
11063                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11064                 break;
11065         default:
11066                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11067                 return 0;
11068         }
11069
11070         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11071                 cntl |= MCURSOR_ROTATE_180;
11072
11073         return cntl;
11074 }
11075
11076 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11077 {
11078         struct drm_i915_private *dev_priv =
11079                 to_i915(plane_state->uapi.plane->dev);
11080         int width = drm_rect_width(&plane_state->uapi.dst);
11081         int height = drm_rect_height(&plane_state->uapi.dst);
11082
11083         if (!intel_cursor_size_ok(plane_state))
11084                 return false;
11085
11086         /* Cursor width is limited to a few power-of-two sizes */
11087         switch (width) {
11088         case 256:
11089         case 128:
11090         case 64:
11091                 break;
11092         default:
11093                 return false;
11094         }
11095
11096         /*
11097          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11098          * height from 8 lines up to the cursor width, when the
11099          * cursor is not rotated. Everything else requires square
11100          * cursors.
11101          */
11102         if (HAS_CUR_FBC(dev_priv) &&
11103             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11104                 if (height < 8 || height > width)
11105                         return false;
11106         } else {
11107                 if (height != width)
11108                         return false;
11109         }
11110
11111         return true;
11112 }
11113
11114 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11115                              struct intel_plane_state *plane_state)
11116 {
11117         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11118         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11119         const struct drm_framebuffer *fb = plane_state->hw.fb;
11120         enum pipe pipe = plane->pipe;
11121         int ret;
11122
11123         ret = intel_check_cursor(crtc_state, plane_state);
11124         if (ret)
11125                 return ret;
11126
11127         /* if we want to turn off the cursor ignore width and height */
11128         if (!fb)
11129                 return 0;
11130
11131         /* Check for which cursor types we support */
11132         if (!i9xx_cursor_size_ok(plane_state)) {
11133                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11134                           drm_rect_width(&plane_state->uapi.dst),
11135                           drm_rect_height(&plane_state->uapi.dst));
11136                 return -EINVAL;
11137         }
11138
11139         WARN_ON(plane_state->uapi.visible &&
11140                 plane_state->color_plane[0].stride != fb->pitches[0]);
11141
11142         if (fb->pitches[0] !=
11143             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11144                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
11145                               fb->pitches[0],
11146                               drm_rect_width(&plane_state->uapi.dst));
11147                 return -EINVAL;
11148         }
11149
11150         /*
11151          * There's something wrong with the cursor on CHV pipe C.
11152          * If it straddles the left edge of the screen then
11153          * moving it away from the edge or disabling it often
11154          * results in a pipe underrun, and often that can lead to
11155          * dead pipe (constant underrun reported, and it scans
11156          * out just a solid color). To recover from that, the
11157          * display power well must be turned off and on again.
11158          * Refuse the put the cursor into that compromised position.
11159          */
11160         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11161             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11162                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11163                 return -EINVAL;
11164         }
11165
11166         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11167
11168         return 0;
11169 }
11170
11171 static void i9xx_update_cursor(struct intel_plane *plane,
11172                                const struct intel_crtc_state *crtc_state,
11173                                const struct intel_plane_state *plane_state)
11174 {
11175         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11176         enum pipe pipe = plane->pipe;
11177         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11178         unsigned long irqflags;
11179
11180         if (plane_state && plane_state->uapi.visible) {
11181                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11182                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11183
11184                 cntl = plane_state->ctl |
11185                         i9xx_cursor_ctl_crtc(crtc_state);
11186
11187                 if (width != height)
11188                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11189
11190                 base = intel_cursor_base(plane_state);
11191                 pos = intel_cursor_position(plane_state);
11192         }
11193
11194         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11195
11196         /*
11197          * On some platforms writing CURCNTR first will also
11198          * cause CURPOS to be armed by the CURBASE write.
11199          * Without the CURCNTR write the CURPOS write would
11200          * arm itself. Thus we always update CURCNTR before
11201          * CURPOS.
11202          *
11203          * On other platforms CURPOS always requires the
11204          * CURBASE write to arm the update. Additonally
11205          * a write to any of the cursor register will cancel
11206          * an already armed cursor update. Thus leaving out
11207          * the CURBASE write after CURPOS could lead to a
11208          * cursor that doesn't appear to move, or even change
11209          * shape. Thus we always write CURBASE.
11210          *
11211          * The other registers are armed by by the CURBASE write
11212          * except when the plane is getting enabled at which time
11213          * the CURCNTR write arms the update.
11214          */
11215
11216         if (INTEL_GEN(dev_priv) >= 9)
11217                 skl_write_cursor_wm(plane, crtc_state);
11218
11219         if (plane->cursor.base != base ||
11220             plane->cursor.size != fbc_ctl ||
11221             plane->cursor.cntl != cntl) {
11222                 if (HAS_CUR_FBC(dev_priv))
11223                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
11224                 I915_WRITE_FW(CURCNTR(pipe), cntl);
11225                 I915_WRITE_FW(CURPOS(pipe), pos);
11226                 I915_WRITE_FW(CURBASE(pipe), base);
11227
11228                 plane->cursor.base = base;
11229                 plane->cursor.size = fbc_ctl;
11230                 plane->cursor.cntl = cntl;
11231         } else {
11232                 I915_WRITE_FW(CURPOS(pipe), pos);
11233                 I915_WRITE_FW(CURBASE(pipe), base);
11234         }
11235
11236         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11237 }
11238
11239 static void i9xx_disable_cursor(struct intel_plane *plane,
11240                                 const struct intel_crtc_state *crtc_state)
11241 {
11242         i9xx_update_cursor(plane, crtc_state, NULL);
11243 }
11244
11245 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11246                                      enum pipe *pipe)
11247 {
11248         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11249         enum intel_display_power_domain power_domain;
11250         intel_wakeref_t wakeref;
11251         bool ret;
11252         u32 val;
11253
11254         /*
11255          * Not 100% correct for planes that can move between pipes,
11256          * but that's only the case for gen2-3 which don't have any
11257          * display power wells.
11258          */
11259         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11260         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11261         if (!wakeref)
11262                 return false;
11263
11264         val = I915_READ(CURCNTR(plane->pipe));
11265
11266         ret = val & MCURSOR_MODE;
11267
11268         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11269                 *pipe = plane->pipe;
11270         else
11271                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11272                         MCURSOR_PIPE_SELECT_SHIFT;
11273
11274         intel_display_power_put(dev_priv, power_domain, wakeref);
11275
11276         return ret;
11277 }
11278
11279 /* VESA 640x480x72Hz mode to set on the pipe */
11280 static const struct drm_display_mode load_detect_mode = {
11281         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11282                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11283 };
11284
11285 struct drm_framebuffer *
11286 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11287                          struct drm_mode_fb_cmd2 *mode_cmd)
11288 {
11289         struct intel_framebuffer *intel_fb;
11290         int ret;
11291
11292         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11293         if (!intel_fb)
11294                 return ERR_PTR(-ENOMEM);
11295
11296         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11297         if (ret)
11298                 goto err;
11299
11300         return &intel_fb->base;
11301
11302 err:
11303         kfree(intel_fb);
11304         return ERR_PTR(ret);
11305 }
11306
11307 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11308                                         struct drm_crtc *crtc)
11309 {
11310         struct drm_plane *plane;
11311         struct drm_plane_state *plane_state;
11312         int ret, i;
11313
11314         ret = drm_atomic_add_affected_planes(state, crtc);
11315         if (ret)
11316                 return ret;
11317
11318         for_each_new_plane_in_state(state, plane, plane_state, i) {
11319                 if (plane_state->crtc != crtc)
11320                         continue;
11321
11322                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11323                 if (ret)
11324                         return ret;
11325
11326                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11327         }
11328
11329         return 0;
11330 }
11331
11332 int intel_get_load_detect_pipe(struct drm_connector *connector,
11333                                struct intel_load_detect_pipe *old,
11334                                struct drm_modeset_acquire_ctx *ctx)
11335 {
11336         struct intel_crtc *intel_crtc;
11337         struct intel_encoder *intel_encoder =
11338                 intel_attached_encoder(connector);
11339         struct drm_crtc *possible_crtc;
11340         struct drm_encoder *encoder = &intel_encoder->base;
11341         struct drm_crtc *crtc = NULL;
11342         struct drm_device *dev = encoder->dev;
11343         struct drm_i915_private *dev_priv = to_i915(dev);
11344         struct drm_mode_config *config = &dev->mode_config;
11345         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11346         struct drm_connector_state *connector_state;
11347         struct intel_crtc_state *crtc_state;
11348         int ret, i = -1;
11349
11350         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11351                       connector->base.id, connector->name,
11352                       encoder->base.id, encoder->name);
11353
11354         old->restore_state = NULL;
11355
11356         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11357
11358         /*
11359          * Algorithm gets a little messy:
11360          *
11361          *   - if the connector already has an assigned crtc, use it (but make
11362          *     sure it's on first)
11363          *
11364          *   - try to find the first unused crtc that can drive this connector,
11365          *     and use that if we find one
11366          */
11367
11368         /* See if we already have a CRTC for this connector */
11369         if (connector->state->crtc) {
11370                 crtc = connector->state->crtc;
11371
11372                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11373                 if (ret)
11374                         goto fail;
11375
11376                 /* Make sure the crtc and connector are running */
11377                 goto found;
11378         }
11379
11380         /* Find an unused one (if possible) */
11381         for_each_crtc(dev, possible_crtc) {
11382                 i++;
11383                 if (!(encoder->possible_crtcs & (1 << i)))
11384                         continue;
11385
11386                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11387                 if (ret)
11388                         goto fail;
11389
11390                 if (possible_crtc->state->enable) {
11391                         drm_modeset_unlock(&possible_crtc->mutex);
11392                         continue;
11393                 }
11394
11395                 crtc = possible_crtc;
11396                 break;
11397         }
11398
11399         /*
11400          * If we didn't find an unused CRTC, don't use any.
11401          */
11402         if (!crtc) {
11403                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11404                 ret = -ENODEV;
11405                 goto fail;
11406         }
11407
11408 found:
11409         intel_crtc = to_intel_crtc(crtc);
11410
11411         state = drm_atomic_state_alloc(dev);
11412         restore_state = drm_atomic_state_alloc(dev);
11413         if (!state || !restore_state) {
11414                 ret = -ENOMEM;
11415                 goto fail;
11416         }
11417
11418         state->acquire_ctx = ctx;
11419         restore_state->acquire_ctx = ctx;
11420
11421         connector_state = drm_atomic_get_connector_state(state, connector);
11422         if (IS_ERR(connector_state)) {
11423                 ret = PTR_ERR(connector_state);
11424                 goto fail;
11425         }
11426
11427         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11428         if (ret)
11429                 goto fail;
11430
11431         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11432         if (IS_ERR(crtc_state)) {
11433                 ret = PTR_ERR(crtc_state);
11434                 goto fail;
11435         }
11436
11437         crtc_state->uapi.active = true;
11438
11439         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11440                                            &load_detect_mode);
11441         if (ret)
11442                 goto fail;
11443
11444         ret = intel_modeset_disable_planes(state, crtc);
11445         if (ret)
11446                 goto fail;
11447
11448         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11449         if (!ret)
11450                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11451         if (!ret)
11452                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11453         if (ret) {
11454                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11455                 goto fail;
11456         }
11457
11458         ret = drm_atomic_commit(state);
11459         if (ret) {
11460                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11461                 goto fail;
11462         }
11463
11464         old->restore_state = restore_state;
11465         drm_atomic_state_put(state);
11466
11467         /* let the connector get through one full cycle before testing */
11468         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11469         return true;
11470
11471 fail:
11472         if (state) {
11473                 drm_atomic_state_put(state);
11474                 state = NULL;
11475         }
11476         if (restore_state) {
11477                 drm_atomic_state_put(restore_state);
11478                 restore_state = NULL;
11479         }
11480
11481         if (ret == -EDEADLK)
11482                 return ret;
11483
11484         return false;
11485 }
11486
11487 void intel_release_load_detect_pipe(struct drm_connector *connector,
11488                                     struct intel_load_detect_pipe *old,
11489                                     struct drm_modeset_acquire_ctx *ctx)
11490 {
11491         struct intel_encoder *intel_encoder =
11492                 intel_attached_encoder(connector);
11493         struct drm_encoder *encoder = &intel_encoder->base;
11494         struct drm_atomic_state *state = old->restore_state;
11495         int ret;
11496
11497         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11498                       connector->base.id, connector->name,
11499                       encoder->base.id, encoder->name);
11500
11501         if (!state)
11502                 return;
11503
11504         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11505         if (ret)
11506                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11507         drm_atomic_state_put(state);
11508 }
11509
11510 static int i9xx_pll_refclk(struct drm_device *dev,
11511                            const struct intel_crtc_state *pipe_config)
11512 {
11513         struct drm_i915_private *dev_priv = to_i915(dev);
11514         u32 dpll = pipe_config->dpll_hw_state.dpll;
11515
11516         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11517                 return dev_priv->vbt.lvds_ssc_freq;
11518         else if (HAS_PCH_SPLIT(dev_priv))
11519                 return 120000;
11520         else if (!IS_GEN(dev_priv, 2))
11521                 return 96000;
11522         else
11523                 return 48000;
11524 }
11525
11526 /* Returns the clock of the currently programmed mode of the given pipe. */
11527 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11528                                 struct intel_crtc_state *pipe_config)
11529 {
11530         struct drm_device *dev = crtc->base.dev;
11531         struct drm_i915_private *dev_priv = to_i915(dev);
11532         enum pipe pipe = crtc->pipe;
11533         u32 dpll = pipe_config->dpll_hw_state.dpll;
11534         u32 fp;
11535         struct dpll clock;
11536         int port_clock;
11537         int refclk = i9xx_pll_refclk(dev, pipe_config);
11538
11539         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11540                 fp = pipe_config->dpll_hw_state.fp0;
11541         else
11542                 fp = pipe_config->dpll_hw_state.fp1;
11543
11544         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11545         if (IS_PINEVIEW(dev_priv)) {
11546                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11547                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11548         } else {
11549                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11550                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11551         }
11552
11553         if (!IS_GEN(dev_priv, 2)) {
11554                 if (IS_PINEVIEW(dev_priv))
11555                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11556                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11557                 else
11558                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11559                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11560
11561                 switch (dpll & DPLL_MODE_MASK) {
11562                 case DPLLB_MODE_DAC_SERIAL:
11563                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11564                                 5 : 10;
11565                         break;
11566                 case DPLLB_MODE_LVDS:
11567                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11568                                 7 : 14;
11569                         break;
11570                 default:
11571                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11572                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11573                         return;
11574                 }
11575
11576                 if (IS_PINEVIEW(dev_priv))
11577                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11578                 else
11579                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11580         } else {
11581                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11582                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11583
11584                 if (is_lvds) {
11585                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11586                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11587
11588                         if (lvds & LVDS_CLKB_POWER_UP)
11589                                 clock.p2 = 7;
11590                         else
11591                                 clock.p2 = 14;
11592                 } else {
11593                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11594                                 clock.p1 = 2;
11595                         else {
11596                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11597                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11598                         }
11599                         if (dpll & PLL_P2_DIVIDE_BY_4)
11600                                 clock.p2 = 4;
11601                         else
11602                                 clock.p2 = 2;
11603                 }
11604
11605                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11606         }
11607
11608         /*
11609          * This value includes pixel_multiplier. We will use
11610          * port_clock to compute adjusted_mode.crtc_clock in the
11611          * encoder's get_config() function.
11612          */
11613         pipe_config->port_clock = port_clock;
11614 }
11615
11616 int intel_dotclock_calculate(int link_freq,
11617                              const struct intel_link_m_n *m_n)
11618 {
11619         /*
11620          * The calculation for the data clock is:
11621          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11622          * But we want to avoid losing precison if possible, so:
11623          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11624          *
11625          * and the link clock is simpler:
11626          * link_clock = (m * link_clock) / n
11627          */
11628
11629         if (!m_n->link_n)
11630                 return 0;
11631
11632         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11633 }
11634
11635 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11636                                    struct intel_crtc_state *pipe_config)
11637 {
11638         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11639
11640         /* read out port_clock from the DPLL */
11641         i9xx_crtc_clock_get(crtc, pipe_config);
11642
11643         /*
11644          * In case there is an active pipe without active ports,
11645          * we may need some idea for the dotclock anyway.
11646          * Calculate one based on the FDI configuration.
11647          */
11648         pipe_config->hw.adjusted_mode.crtc_clock =
11649                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11650                                          &pipe_config->fdi_m_n);
11651 }
11652
11653 /* Returns the currently programmed mode of the given encoder. */
11654 struct drm_display_mode *
11655 intel_encoder_current_mode(struct intel_encoder *encoder)
11656 {
11657         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11658         struct intel_crtc_state *crtc_state;
11659         struct drm_display_mode *mode;
11660         struct intel_crtc *crtc;
11661         enum pipe pipe;
11662
11663         if (!encoder->get_hw_state(encoder, &pipe))
11664                 return NULL;
11665
11666         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11667
11668         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11669         if (!mode)
11670                 return NULL;
11671
11672         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11673         if (!crtc_state) {
11674                 kfree(mode);
11675                 return NULL;
11676         }
11677
11678         crtc_state->uapi.crtc = &crtc->base;
11679
11680         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11681                 kfree(crtc_state);
11682                 kfree(mode);
11683                 return NULL;
11684         }
11685
11686         encoder->get_config(encoder, crtc_state);
11687
11688         intel_mode_from_pipe_config(mode, crtc_state);
11689
11690         kfree(crtc_state);
11691
11692         return mode;
11693 }
11694
11695 static void intel_crtc_destroy(struct drm_crtc *crtc)
11696 {
11697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11698
11699         drm_crtc_cleanup(crtc);
11700         kfree(intel_crtc);
11701 }
11702
11703 /**
11704  * intel_wm_need_update - Check whether watermarks need updating
11705  * @cur: current plane state
11706  * @new: new plane state
11707  *
11708  * Check current plane state versus the new one to determine whether
11709  * watermarks need to be recalculated.
11710  *
11711  * Returns true or false.
11712  */
11713 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11714                                  struct intel_plane_state *new)
11715 {
11716         /* Update watermarks on tiling or size changes. */
11717         if (new->uapi.visible != cur->uapi.visible)
11718                 return true;
11719
11720         if (!cur->hw.fb || !new->hw.fb)
11721                 return false;
11722
11723         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
11724             cur->hw.rotation != new->hw.rotation ||
11725             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
11726             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
11727             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
11728             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
11729                 return true;
11730
11731         return false;
11732 }
11733
11734 static bool needs_scaling(const struct intel_plane_state *state)
11735 {
11736         int src_w = drm_rect_width(&state->uapi.src) >> 16;
11737         int src_h = drm_rect_height(&state->uapi.src) >> 16;
11738         int dst_w = drm_rect_width(&state->uapi.dst);
11739         int dst_h = drm_rect_height(&state->uapi.dst);
11740
11741         return (src_w != dst_w || src_h != dst_h);
11742 }
11743
11744 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11745                                     struct intel_crtc_state *crtc_state,
11746                                     const struct intel_plane_state *old_plane_state,
11747                                     struct intel_plane_state *plane_state)
11748 {
11749         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11750         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11751         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11752         bool mode_changed = needs_modeset(crtc_state);
11753         bool was_crtc_enabled = old_crtc_state->hw.active;
11754         bool is_crtc_enabled = crtc_state->hw.active;
11755         bool turn_off, turn_on, visible, was_visible;
11756         int ret;
11757
11758         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11759                 ret = skl_update_scaler_plane(crtc_state, plane_state);
11760                 if (ret)
11761                         return ret;
11762         }
11763
11764         was_visible = old_plane_state->uapi.visible;
11765         visible = plane_state->uapi.visible;
11766
11767         if (!was_crtc_enabled && WARN_ON(was_visible))
11768                 was_visible = false;
11769
11770         /*
11771          * Visibility is calculated as if the crtc was on, but
11772          * after scaler setup everything depends on it being off
11773          * when the crtc isn't active.
11774          *
11775          * FIXME this is wrong for watermarks. Watermarks should also
11776          * be computed as if the pipe would be active. Perhaps move
11777          * per-plane wm computation to the .check_plane() hook, and
11778          * only combine the results from all planes in the current place?
11779          */
11780         if (!is_crtc_enabled) {
11781                 plane_state->uapi.visible = visible = false;
11782                 crtc_state->active_planes &= ~BIT(plane->id);
11783                 crtc_state->data_rate[plane->id] = 0;
11784                 crtc_state->min_cdclk[plane->id] = 0;
11785         }
11786
11787         if (!was_visible && !visible)
11788                 return 0;
11789
11790         turn_off = was_visible && (!visible || mode_changed);
11791         turn_on = visible && (!was_visible || mode_changed);
11792
11793         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11794                          crtc->base.base.id, crtc->base.name,
11795                          plane->base.base.id, plane->base.name,
11796                          was_visible, visible,
11797                          turn_off, turn_on, mode_changed);
11798
11799         if (turn_on) {
11800                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11801                         crtc_state->update_wm_pre = true;
11802
11803                 /* must disable cxsr around plane enable/disable */
11804                 if (plane->id != PLANE_CURSOR)
11805                         crtc_state->disable_cxsr = true;
11806         } else if (turn_off) {
11807                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11808                         crtc_state->update_wm_post = true;
11809
11810                 /* must disable cxsr around plane enable/disable */
11811                 if (plane->id != PLANE_CURSOR)
11812                         crtc_state->disable_cxsr = true;
11813         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11814                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11815                         /* FIXME bollocks */
11816                         crtc_state->update_wm_pre = true;
11817                         crtc_state->update_wm_post = true;
11818                 }
11819         }
11820
11821         if (visible || was_visible)
11822                 crtc_state->fb_bits |= plane->frontbuffer_bit;
11823
11824         /*
11825          * ILK/SNB DVSACNTR/Sprite Enable
11826          * IVB SPR_CTL/Sprite Enable
11827          * "When in Self Refresh Big FIFO mode, a write to enable the
11828          *  plane will be internally buffered and delayed while Big FIFO
11829          *  mode is exiting."
11830          *
11831          * Which means that enabling the sprite can take an extra frame
11832          * when we start in big FIFO mode (LP1+). Thus we need to drop
11833          * down to LP0 and wait for vblank in order to make sure the
11834          * sprite gets enabled on the next vblank after the register write.
11835          * Doing otherwise would risk enabling the sprite one frame after
11836          * we've already signalled flip completion. We can resume LP1+
11837          * once the sprite has been enabled.
11838          *
11839          *
11840          * WaCxSRDisabledForSpriteScaling:ivb
11841          * IVB SPR_SCALE/Scaling Enable
11842          * "Low Power watermarks must be disabled for at least one
11843          *  frame before enabling sprite scaling, and kept disabled
11844          *  until sprite scaling is disabled."
11845          *
11846          * ILK/SNB DVSASCALE/Scaling Enable
11847          * "When in Self Refresh Big FIFO mode, scaling enable will be
11848          *  masked off while Big FIFO mode is exiting."
11849          *
11850          * Despite the w/a only being listed for IVB we assume that
11851          * the ILK/SNB note has similar ramifications, hence we apply
11852          * the w/a on all three platforms.
11853          *
11854          * With experimental results seems this is needed also for primary
11855          * plane, not only sprite plane.
11856          */
11857         if (plane->id != PLANE_CURSOR &&
11858             (IS_GEN_RANGE(dev_priv, 5, 6) ||
11859              IS_IVYBRIDGE(dev_priv)) &&
11860             (turn_on || (!needs_scaling(old_plane_state) &&
11861                          needs_scaling(plane_state))))
11862                 crtc_state->disable_lp_wm = true;
11863
11864         return 0;
11865 }
11866
11867 static bool encoders_cloneable(const struct intel_encoder *a,
11868                                const struct intel_encoder *b)
11869 {
11870         /* masks could be asymmetric, so check both ways */
11871         return a == b || (a->cloneable & (1 << b->type) &&
11872                           b->cloneable & (1 << a->type));
11873 }
11874
11875 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11876                                          struct intel_crtc *crtc,
11877                                          struct intel_encoder *encoder)
11878 {
11879         struct intel_encoder *source_encoder;
11880         struct drm_connector *connector;
11881         struct drm_connector_state *connector_state;
11882         int i;
11883
11884         for_each_new_connector_in_state(state, connector, connector_state, i) {
11885                 if (connector_state->crtc != &crtc->base)
11886                         continue;
11887
11888                 source_encoder =
11889                         to_intel_encoder(connector_state->best_encoder);
11890                 if (!encoders_cloneable(encoder, source_encoder))
11891                         return false;
11892         }
11893
11894         return true;
11895 }
11896
11897 static int icl_add_linked_planes(struct intel_atomic_state *state)
11898 {
11899         struct intel_plane *plane, *linked;
11900         struct intel_plane_state *plane_state, *linked_plane_state;
11901         int i;
11902
11903         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11904                 linked = plane_state->planar_linked_plane;
11905
11906                 if (!linked)
11907                         continue;
11908
11909                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11910                 if (IS_ERR(linked_plane_state))
11911                         return PTR_ERR(linked_plane_state);
11912
11913                 WARN_ON(linked_plane_state->planar_linked_plane != plane);
11914                 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
11915         }
11916
11917         return 0;
11918 }
11919
11920 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11921 {
11922         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11923         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11924         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
11925         struct intel_plane *plane, *linked;
11926         struct intel_plane_state *plane_state;
11927         int i;
11928
11929         if (INTEL_GEN(dev_priv) < 11)
11930                 return 0;
11931
11932         /*
11933          * Destroy all old plane links and make the slave plane invisible
11934          * in the crtc_state->active_planes mask.
11935          */
11936         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11937                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
11938                         continue;
11939
11940                 plane_state->planar_linked_plane = NULL;
11941                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
11942                         crtc_state->active_planes &= ~BIT(plane->id);
11943                         crtc_state->update_planes |= BIT(plane->id);
11944                 }
11945
11946                 plane_state->planar_slave = false;
11947         }
11948
11949         if (!crtc_state->nv12_planes)
11950                 return 0;
11951
11952         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11953                 struct intel_plane_state *linked_state = NULL;
11954
11955                 if (plane->pipe != crtc->pipe ||
11956                     !(crtc_state->nv12_planes & BIT(plane->id)))
11957                         continue;
11958
11959                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
11960                         if (!icl_is_nv12_y_plane(linked->id))
11961                                 continue;
11962
11963                         if (crtc_state->active_planes & BIT(linked->id))
11964                                 continue;
11965
11966                         linked_state = intel_atomic_get_plane_state(state, linked);
11967                         if (IS_ERR(linked_state))
11968                                 return PTR_ERR(linked_state);
11969
11970                         break;
11971                 }
11972
11973                 if (!linked_state) {
11974                         DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11975                                       hweight8(crtc_state->nv12_planes));
11976
11977                         return -EINVAL;
11978                 }
11979
11980                 plane_state->planar_linked_plane = linked;
11981
11982                 linked_state->planar_slave = true;
11983                 linked_state->planar_linked_plane = plane;
11984                 crtc_state->active_planes |= BIT(linked->id);
11985                 crtc_state->update_planes |= BIT(linked->id);
11986                 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
11987         }
11988
11989         return 0;
11990 }
11991
11992 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
11993 {
11994         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
11995         struct intel_atomic_state *state =
11996                 to_intel_atomic_state(new_crtc_state->uapi.state);
11997         const struct intel_crtc_state *old_crtc_state =
11998                 intel_atomic_get_old_crtc_state(state, crtc);
11999
12000         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12001 }
12002
12003 static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
12004 {
12005         struct drm_crtc *crtc = crtc_state->uapi.crtc;
12006         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12007         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12008         struct drm_connector *master_connector, *connector;
12009         struct drm_connector_state *connector_state;
12010         struct drm_connector_list_iter conn_iter;
12011         struct drm_crtc *master_crtc = NULL;
12012         struct drm_crtc_state *master_crtc_state;
12013         struct intel_crtc_state *master_pipe_config;
12014         int i, tile_group_id;
12015
12016         if (INTEL_GEN(dev_priv) < 11)
12017                 return 0;
12018
12019         /*
12020          * In case of tiled displays there could be one or more slaves but there is
12021          * only one master. Lets make the CRTC used by the connector corresponding
12022          * to the last horizonal and last vertical tile a master/genlock CRTC.
12023          * All the other CRTCs corresponding to other tiles of the same Tile group
12024          * are the slave CRTCs and hold a pointer to their genlock CRTC.
12025          */
12026         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
12027                 if (connector_state->crtc != crtc)
12028                         continue;
12029                 if (!connector->has_tile)
12030                         continue;
12031                 if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
12032                     crtc_state->hw.mode.vdisplay != connector->tile_v_size)
12033                         return 0;
12034                 if (connector->tile_h_loc == connector->num_h_tile - 1 &&
12035                     connector->tile_v_loc == connector->num_v_tile - 1)
12036                         continue;
12037                 crtc_state->sync_mode_slaves_mask = 0;
12038                 tile_group_id = connector->tile_group->id;
12039                 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
12040                 drm_for_each_connector_iter(master_connector, &conn_iter) {
12041                         struct drm_connector_state *master_conn_state = NULL;
12042
12043                         if (!master_connector->has_tile)
12044                                 continue;
12045                         if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
12046                             master_connector->tile_v_loc != master_connector->num_v_tile - 1)
12047                                 continue;
12048                         if (master_connector->tile_group->id != tile_group_id)
12049                                 continue;
12050
12051                         master_conn_state = drm_atomic_get_connector_state(&state->base,
12052                                                                            master_connector);
12053                         if (IS_ERR(master_conn_state)) {
12054                                 drm_connector_list_iter_end(&conn_iter);
12055                                 return PTR_ERR(master_conn_state);
12056                         }
12057                         if (master_conn_state->crtc) {
12058                                 master_crtc = master_conn_state->crtc;
12059                                 break;
12060                         }
12061                 }
12062                 drm_connector_list_iter_end(&conn_iter);
12063
12064                 if (!master_crtc) {
12065                         DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
12066                                       connector_state->crtc->base.id);
12067                         return -EINVAL;
12068                 }
12069
12070                 master_crtc_state = drm_atomic_get_crtc_state(&state->base,
12071                                                               master_crtc);
12072                 if (IS_ERR(master_crtc_state))
12073                         return PTR_ERR(master_crtc_state);
12074
12075                 master_pipe_config = to_intel_crtc_state(master_crtc_state);
12076                 crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
12077                 master_pipe_config->sync_mode_slaves_mask |=
12078                         BIT(crtc_state->cpu_transcoder);
12079                 DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
12080                               transcoder_name(crtc_state->master_transcoder),
12081                               crtc_state->uapi.crtc->base.id,
12082                               master_pipe_config->sync_mode_slaves_mask);
12083         }
12084
12085         return 0;
12086 }
12087
12088 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12089                                    struct intel_crtc *crtc)
12090 {
12091         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12092         struct intel_crtc_state *crtc_state =
12093                 intel_atomic_get_new_crtc_state(state, crtc);
12094         bool mode_changed = needs_modeset(crtc_state);
12095         int ret;
12096
12097         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12098             mode_changed && !crtc_state->hw.active)
12099                 crtc_state->update_wm_post = true;
12100
12101         if (mode_changed && crtc_state->hw.enable &&
12102             dev_priv->display.crtc_compute_clock &&
12103             !WARN_ON(crtc_state->shared_dpll)) {
12104                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12105                 if (ret)
12106                         return ret;
12107         }
12108
12109         /*
12110          * May need to update pipe gamma enable bits
12111          * when C8 planes are getting enabled/disabled.
12112          */
12113         if (c8_planes_changed(crtc_state))
12114                 crtc_state->uapi.color_mgmt_changed = true;
12115
12116         if (mode_changed || crtc_state->update_pipe ||
12117             crtc_state->uapi.color_mgmt_changed) {
12118                 ret = intel_color_check(crtc_state);
12119                 if (ret)
12120                         return ret;
12121         }
12122
12123         ret = 0;
12124         if (dev_priv->display.compute_pipe_wm) {
12125                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12126                 if (ret) {
12127                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12128                         return ret;
12129                 }
12130         }
12131
12132         if (dev_priv->display.compute_intermediate_wm) {
12133                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12134                         return 0;
12135
12136                 /*
12137                  * Calculate 'intermediate' watermarks that satisfy both the
12138                  * old state and the new state.  We can program these
12139                  * immediately.
12140                  */
12141                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12142                 if (ret) {
12143                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12144                         return ret;
12145                 }
12146         }
12147
12148         if (INTEL_GEN(dev_priv) >= 9) {
12149                 if (mode_changed || crtc_state->update_pipe)
12150                         ret = skl_update_scaler_crtc(crtc_state);
12151                 if (!ret)
12152                         ret = intel_atomic_setup_scalers(dev_priv, crtc,
12153                                                          crtc_state);
12154         }
12155
12156         if (HAS_IPS(dev_priv))
12157                 crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
12158
12159         return ret;
12160 }
12161
12162 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12163 {
12164         struct intel_connector *connector;
12165         struct drm_connector_list_iter conn_iter;
12166
12167         drm_connector_list_iter_begin(dev, &conn_iter);
12168         for_each_intel_connector_iter(connector, &conn_iter) {
12169                 if (connector->base.state->crtc)
12170                         drm_connector_put(&connector->base);
12171
12172                 if (connector->base.encoder) {
12173                         connector->base.state->best_encoder =
12174                                 connector->base.encoder;
12175                         connector->base.state->crtc =
12176                                 connector->base.encoder->crtc;
12177
12178                         drm_connector_get(&connector->base);
12179                 } else {
12180                         connector->base.state->best_encoder = NULL;
12181                         connector->base.state->crtc = NULL;
12182                 }
12183         }
12184         drm_connector_list_iter_end(&conn_iter);
12185 }
12186
12187 static int
12188 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12189                       struct intel_crtc_state *pipe_config)
12190 {
12191         struct drm_connector *connector = conn_state->connector;
12192         const struct drm_display_info *info = &connector->display_info;
12193         int bpp;
12194
12195         switch (conn_state->max_bpc) {
12196         case 6 ... 7:
12197                 bpp = 6 * 3;
12198                 break;
12199         case 8 ... 9:
12200                 bpp = 8 * 3;
12201                 break;
12202         case 10 ... 11:
12203                 bpp = 10 * 3;
12204                 break;
12205         case 12:
12206                 bpp = 12 * 3;
12207                 break;
12208         default:
12209                 return -EINVAL;
12210         }
12211
12212         if (bpp < pipe_config->pipe_bpp) {
12213                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12214                               "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12215                               connector->base.id, connector->name,
12216                               bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
12217                               pipe_config->pipe_bpp);
12218
12219                 pipe_config->pipe_bpp = bpp;
12220         }
12221
12222         return 0;
12223 }
12224
12225 static int
12226 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12227                           struct intel_crtc_state *pipe_config)
12228 {
12229         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12230         struct drm_atomic_state *state = pipe_config->uapi.state;
12231         struct drm_connector *connector;
12232         struct drm_connector_state *connector_state;
12233         int bpp, i;
12234
12235         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12236             IS_CHERRYVIEW(dev_priv)))
12237                 bpp = 10*3;
12238         else if (INTEL_GEN(dev_priv) >= 5)
12239                 bpp = 12*3;
12240         else
12241                 bpp = 8*3;
12242
12243         pipe_config->pipe_bpp = bpp;
12244
12245         /* Clamp display bpp to connector max bpp */
12246         for_each_new_connector_in_state(state, connector, connector_state, i) {
12247                 int ret;
12248
12249                 if (connector_state->crtc != &crtc->base)
12250                         continue;
12251
12252                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12253                 if (ret)
12254                         return ret;
12255         }
12256
12257         return 0;
12258 }
12259
12260 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12261 {
12262         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12263                       "type: 0x%x flags: 0x%x\n",
12264                       mode->crtc_clock,
12265                       mode->crtc_hdisplay, mode->crtc_hsync_start,
12266                       mode->crtc_hsync_end, mode->crtc_htotal,
12267                       mode->crtc_vdisplay, mode->crtc_vsync_start,
12268                       mode->crtc_vsync_end, mode->crtc_vtotal,
12269                       mode->type, mode->flags);
12270 }
12271
12272 static inline void
12273 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12274                       const char *id, unsigned int lane_count,
12275                       const struct intel_link_m_n *m_n)
12276 {
12277         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12278                       id, lane_count,
12279                       m_n->gmch_m, m_n->gmch_n,
12280                       m_n->link_m, m_n->link_n, m_n->tu);
12281 }
12282
12283 static void
12284 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12285                      const union hdmi_infoframe *frame)
12286 {
12287         if ((drm_debug & DRM_UT_KMS) == 0)
12288                 return;
12289
12290         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12291 }
12292
12293 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12294
12295 static const char * const output_type_str[] = {
12296         OUTPUT_TYPE(UNUSED),
12297         OUTPUT_TYPE(ANALOG),
12298         OUTPUT_TYPE(DVO),
12299         OUTPUT_TYPE(SDVO),
12300         OUTPUT_TYPE(LVDS),
12301         OUTPUT_TYPE(TVOUT),
12302         OUTPUT_TYPE(HDMI),
12303         OUTPUT_TYPE(DP),
12304         OUTPUT_TYPE(EDP),
12305         OUTPUT_TYPE(DSI),
12306         OUTPUT_TYPE(DDI),
12307         OUTPUT_TYPE(DP_MST),
12308 };
12309
12310 #undef OUTPUT_TYPE
12311
12312 static void snprintf_output_types(char *buf, size_t len,
12313                                   unsigned int output_types)
12314 {
12315         char *str = buf;
12316         int i;
12317
12318         str[0] = '\0';
12319
12320         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12321                 int r;
12322
12323                 if ((output_types & BIT(i)) == 0)
12324                         continue;
12325
12326                 r = snprintf(str, len, "%s%s",
12327                              str != buf ? "," : "", output_type_str[i]);
12328                 if (r >= len)
12329                         break;
12330                 str += r;
12331                 len -= r;
12332
12333                 output_types &= ~BIT(i);
12334         }
12335
12336         WARN_ON_ONCE(output_types != 0);
12337 }
12338
12339 static const char * const output_format_str[] = {
12340         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12341         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12342         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12343         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12344 };
12345
12346 static const char *output_formats(enum intel_output_format format)
12347 {
12348         if (format >= ARRAY_SIZE(output_format_str))
12349                 format = INTEL_OUTPUT_FORMAT_INVALID;
12350         return output_format_str[format];
12351 }
12352
12353 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12354 {
12355         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12356         const struct drm_framebuffer *fb = plane_state->hw.fb;
12357         struct drm_format_name_buf format_name;
12358
12359         if (!fb) {
12360                 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12361                               plane->base.base.id, plane->base.name,
12362                               yesno(plane_state->uapi.visible));
12363                 return;
12364         }
12365
12366         DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12367                       plane->base.base.id, plane->base.name,
12368                       fb->base.id, fb->width, fb->height,
12369                       drm_get_format_name(fb->format->format, &format_name),
12370                       yesno(plane_state->uapi.visible));
12371         DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12372                       plane_state->hw.rotation, plane_state->scaler_id);
12373         if (plane_state->uapi.visible)
12374                 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12375                               DRM_RECT_FP_ARG(&plane_state->uapi.src),
12376                               DRM_RECT_ARG(&plane_state->uapi.dst));
12377 }
12378
12379 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12380                                    struct intel_atomic_state *state,
12381                                    const char *context)
12382 {
12383         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12384         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12385         const struct intel_plane_state *plane_state;
12386         struct intel_plane *plane;
12387         char buf[64];
12388         int i;
12389
12390         DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12391                       crtc->base.base.id, crtc->base.name,
12392                       yesno(pipe_config->hw.enable), context);
12393
12394         if (!pipe_config->hw.enable)
12395                 goto dump_planes;
12396
12397         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12398         DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12399                       yesno(pipe_config->hw.active),
12400                       buf, pipe_config->output_types,
12401                       output_formats(pipe_config->output_format));
12402
12403         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12404                       transcoder_name(pipe_config->cpu_transcoder),
12405                       pipe_config->pipe_bpp, pipe_config->dither);
12406
12407         if (pipe_config->has_pch_encoder)
12408                 intel_dump_m_n_config(pipe_config, "fdi",
12409                                       pipe_config->fdi_lanes,
12410                                       &pipe_config->fdi_m_n);
12411
12412         if (intel_crtc_has_dp_encoder(pipe_config)) {
12413                 intel_dump_m_n_config(pipe_config, "dp m_n",
12414                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12415                 if (pipe_config->has_drrs)
12416                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12417                                               pipe_config->lane_count,
12418                                               &pipe_config->dp_m2_n2);
12419         }
12420
12421         DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12422                       pipe_config->has_audio, pipe_config->has_infoframe,
12423                       pipe_config->infoframes.enable);
12424
12425         if (pipe_config->infoframes.enable &
12426             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12427                 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12428         if (pipe_config->infoframes.enable &
12429             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12430                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12431         if (pipe_config->infoframes.enable &
12432             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12433                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12434         if (pipe_config->infoframes.enable &
12435             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12436                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12437
12438         DRM_DEBUG_KMS("requested mode:\n");
12439         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
12440         DRM_DEBUG_KMS("adjusted mode:\n");
12441         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
12442         intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
12443         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12444                       pipe_config->port_clock,
12445                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12446                       pipe_config->pixel_rate);
12447
12448         if (INTEL_GEN(dev_priv) >= 9)
12449                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12450                               crtc->num_scalers,
12451                               pipe_config->scaler_state.scaler_users,
12452                               pipe_config->scaler_state.scaler_id);
12453
12454         if (HAS_GMCH(dev_priv))
12455                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12456                               pipe_config->gmch_pfit.control,
12457                               pipe_config->gmch_pfit.pgm_ratios,
12458                               pipe_config->gmch_pfit.lvds_border_bits);
12459         else
12460                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12461                               pipe_config->pch_pfit.pos,
12462                               pipe_config->pch_pfit.size,
12463                               enableddisabled(pipe_config->pch_pfit.enabled),
12464                               yesno(pipe_config->pch_pfit.force_thru));
12465
12466         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12467                       pipe_config->ips_enabled, pipe_config->double_wide);
12468
12469         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12470
12471         if (IS_CHERRYVIEW(dev_priv))
12472                 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12473                               pipe_config->cgm_mode, pipe_config->gamma_mode,
12474                               pipe_config->gamma_enable, pipe_config->csc_enable);
12475         else
12476                 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12477                               pipe_config->csc_mode, pipe_config->gamma_mode,
12478                               pipe_config->gamma_enable, pipe_config->csc_enable);
12479
12480 dump_planes:
12481         if (!state)
12482                 return;
12483
12484         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12485                 if (plane->pipe == crtc->pipe)
12486                         intel_dump_plane_state(plane_state);
12487         }
12488 }
12489
12490 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12491 {
12492         struct drm_device *dev = state->base.dev;
12493         struct drm_connector *connector;
12494         struct drm_connector_list_iter conn_iter;
12495         unsigned int used_ports = 0;
12496         unsigned int used_mst_ports = 0;
12497         bool ret = true;
12498
12499         /*
12500          * We're going to peek into connector->state,
12501          * hence connection_mutex must be held.
12502          */
12503         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
12504
12505         /*
12506          * Walk the connector list instead of the encoder
12507          * list to detect the problem on ddi platforms
12508          * where there's just one encoder per digital port.
12509          */
12510         drm_connector_list_iter_begin(dev, &conn_iter);
12511         drm_for_each_connector_iter(connector, &conn_iter) {
12512                 struct drm_connector_state *connector_state;
12513                 struct intel_encoder *encoder;
12514
12515                 connector_state =
12516                         drm_atomic_get_new_connector_state(&state->base,
12517                                                            connector);
12518                 if (!connector_state)
12519                         connector_state = connector->state;
12520
12521                 if (!connector_state->best_encoder)
12522                         continue;
12523
12524                 encoder = to_intel_encoder(connector_state->best_encoder);
12525
12526                 WARN_ON(!connector_state->crtc);
12527
12528                 switch (encoder->type) {
12529                         unsigned int port_mask;
12530                 case INTEL_OUTPUT_DDI:
12531                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12532                                 break;
12533                         /* else, fall through */
12534                 case INTEL_OUTPUT_DP:
12535                 case INTEL_OUTPUT_HDMI:
12536                 case INTEL_OUTPUT_EDP:
12537                         port_mask = 1 << encoder->port;
12538
12539                         /* the same port mustn't appear more than once */
12540                         if (used_ports & port_mask)
12541                                 ret = false;
12542
12543                         used_ports |= port_mask;
12544                         break;
12545                 case INTEL_OUTPUT_DP_MST:
12546                         used_mst_ports |=
12547                                 1 << encoder->port;
12548                         break;
12549                 default:
12550                         break;
12551                 }
12552         }
12553         drm_connector_list_iter_end(&conn_iter);
12554
12555         /* can't mix MST and SST/HDMI on the same port */
12556         if (used_ports & used_mst_ports)
12557                 return false;
12558
12559         return ret;
12560 }
12561
12562 static void
12563 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
12564 {
12565         intel_crtc_copy_color_blobs(crtc_state);
12566 }
12567
12568 static void
12569 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
12570 {
12571         crtc_state->hw.enable = crtc_state->uapi.enable;
12572         crtc_state->hw.active = crtc_state->uapi.active;
12573         crtc_state->hw.mode = crtc_state->uapi.mode;
12574         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
12575         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
12576 }
12577
12578 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
12579 {
12580         crtc_state->uapi.enable = crtc_state->hw.enable;
12581         crtc_state->uapi.active = crtc_state->hw.active;
12582         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
12583
12584         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
12585
12586         /* copy color blobs to uapi */
12587         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
12588                                   crtc_state->hw.degamma_lut);
12589         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
12590                                   crtc_state->hw.gamma_lut);
12591         drm_property_replace_blob(&crtc_state->uapi.ctm,
12592                                   crtc_state->hw.ctm);
12593 }
12594
12595 static int
12596 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
12597 {
12598         struct drm_i915_private *dev_priv =
12599                 to_i915(crtc_state->uapi.crtc->dev);
12600         struct intel_crtc_state *saved_state;
12601
12602         saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12603         if (!saved_state)
12604                 return -ENOMEM;
12605
12606         /* free the old crtc_state->hw members */
12607         intel_crtc_free_hw_state(crtc_state);
12608
12609         /* FIXME: before the switch to atomic started, a new pipe_config was
12610          * kzalloc'd. Code that depends on any field being zero should be
12611          * fixed, so that the crtc_state can be safely duplicated. For now,
12612          * only fields that are know to not cause problems are preserved. */
12613
12614         saved_state->uapi = crtc_state->uapi;
12615         saved_state->scaler_state = crtc_state->scaler_state;
12616         saved_state->shared_dpll = crtc_state->shared_dpll;
12617         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12618         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12619                sizeof(saved_state->icl_port_dplls));
12620         saved_state->crc_enabled = crtc_state->crc_enabled;
12621         if (IS_G4X(dev_priv) ||
12622             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12623                 saved_state->wm = crtc_state->wm;
12624         /*
12625          * Save the slave bitmask which gets filled for master crtc state during
12626          * slave atomic check call.
12627          */
12628         if (is_trans_port_sync_master(crtc_state))
12629                 saved_state->sync_mode_slaves_mask =
12630                         crtc_state->sync_mode_slaves_mask;
12631
12632         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
12633         kfree(saved_state);
12634
12635         intel_crtc_copy_uapi_to_hw_state(crtc_state);
12636
12637         return 0;
12638 }
12639
12640 static int
12641 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12642 {
12643         struct drm_crtc *crtc = pipe_config->uapi.crtc;
12644         struct drm_atomic_state *state = pipe_config->uapi.state;
12645         struct intel_encoder *encoder;
12646         struct drm_connector *connector;
12647         struct drm_connector_state *connector_state;
12648         int base_bpp, ret;
12649         int i;
12650         bool retry = true;
12651
12652         pipe_config->cpu_transcoder =
12653                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12654
12655         /*
12656          * Sanitize sync polarity flags based on requested ones. If neither
12657          * positive or negative polarity is requested, treat this as meaning
12658          * negative polarity.
12659          */
12660         if (!(pipe_config->hw.adjusted_mode.flags &
12661               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12662                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12663
12664         if (!(pipe_config->hw.adjusted_mode.flags &
12665               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12666                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12667
12668         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12669                                         pipe_config);
12670         if (ret)
12671                 return ret;
12672
12673         base_bpp = pipe_config->pipe_bpp;
12674
12675         /*
12676          * Determine the real pipe dimensions. Note that stereo modes can
12677          * increase the actual pipe size due to the frame doubling and
12678          * insertion of additional space for blanks between the frame. This
12679          * is stored in the crtc timings. We use the requested mode to do this
12680          * computation to clearly distinguish it from the adjusted mode, which
12681          * can be changed by the connectors in the below retry loop.
12682          */
12683         drm_mode_get_hv_timing(&pipe_config->hw.mode,
12684                                &pipe_config->pipe_src_w,
12685                                &pipe_config->pipe_src_h);
12686
12687         for_each_new_connector_in_state(state, connector, connector_state, i) {
12688                 if (connector_state->crtc != crtc)
12689                         continue;
12690
12691                 encoder = to_intel_encoder(connector_state->best_encoder);
12692
12693                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12694                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12695                         return -EINVAL;
12696                 }
12697
12698                 /*
12699                  * Determine output_types before calling the .compute_config()
12700                  * hooks so that the hooks can use this information safely.
12701                  */
12702                 if (encoder->compute_output_type)
12703                         pipe_config->output_types |=
12704                                 BIT(encoder->compute_output_type(encoder, pipe_config,
12705                                                                  connector_state));
12706                 else
12707                         pipe_config->output_types |= BIT(encoder->type);
12708         }
12709
12710 encoder_retry:
12711         /* Ensure the port clock defaults are reset when retrying. */
12712         pipe_config->port_clock = 0;
12713         pipe_config->pixel_multiplier = 1;
12714
12715         /* Fill in default crtc timings, allow encoders to overwrite them. */
12716         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
12717                               CRTC_STEREO_DOUBLE);
12718
12719         /* Set the crtc_state defaults for trans_port_sync */
12720         pipe_config->master_transcoder = INVALID_TRANSCODER;
12721         ret = icl_add_sync_mode_crtcs(pipe_config);
12722         if (ret) {
12723                 DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
12724                               ret);
12725                 return ret;
12726         }
12727
12728         /* Pass our mode to the connectors and the CRTC to give them a chance to
12729          * adjust it according to limitations or connector properties, and also
12730          * a chance to reject the mode entirely.
12731          */
12732         for_each_new_connector_in_state(state, connector, connector_state, i) {
12733                 if (connector_state->crtc != crtc)
12734                         continue;
12735
12736                 encoder = to_intel_encoder(connector_state->best_encoder);
12737                 ret = encoder->compute_config(encoder, pipe_config,
12738                                               connector_state);
12739                 if (ret < 0) {
12740                         if (ret != -EDEADLK)
12741                                 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12742                                               ret);
12743                         return ret;
12744                 }
12745         }
12746
12747         /* Set default port clock if not overwritten by the encoder. Needs to be
12748          * done afterwards in case the encoder adjusts the mode. */
12749         if (!pipe_config->port_clock)
12750                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
12751                         * pipe_config->pixel_multiplier;
12752
12753         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12754         if (ret == -EDEADLK)
12755                 return ret;
12756         if (ret < 0) {
12757                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12758                 return ret;
12759         }
12760
12761         if (ret == RETRY) {
12762                 if (WARN(!retry, "loop in pipe configuration computation\n"))
12763                         return -EINVAL;
12764
12765                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12766                 retry = false;
12767                 goto encoder_retry;
12768         }
12769
12770         /* Dithering seems to not pass-through bits correctly when it should, so
12771          * only enable it on 6bpc panels and when its not a compliance
12772          * test requesting 6bpc video pattern.
12773          */
12774         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12775                 !pipe_config->dither_force_disable;
12776         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12777                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12778
12779         /*
12780          * Make drm_calc_timestamping_constants in
12781          * drm_atomic_helper_update_legacy_modeset_state() happy
12782          */
12783         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
12784
12785         return 0;
12786 }
12787
12788 bool intel_fuzzy_clock_check(int clock1, int clock2)
12789 {
12790         int diff;
12791
12792         if (clock1 == clock2)
12793                 return true;
12794
12795         if (!clock1 || !clock2)
12796                 return false;
12797
12798         diff = abs(clock1 - clock2);
12799
12800         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12801                 return true;
12802
12803         return false;
12804 }
12805
12806 static bool
12807 intel_compare_m_n(unsigned int m, unsigned int n,
12808                   unsigned int m2, unsigned int n2,
12809                   bool exact)
12810 {
12811         if (m == m2 && n == n2)
12812                 return true;
12813
12814         if (exact || !m || !n || !m2 || !n2)
12815                 return false;
12816
12817         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12818
12819         if (n > n2) {
12820                 while (n > n2) {
12821                         m2 <<= 1;
12822                         n2 <<= 1;
12823                 }
12824         } else if (n < n2) {
12825                 while (n < n2) {
12826                         m <<= 1;
12827                         n <<= 1;
12828                 }
12829         }
12830
12831         if (n != n2)
12832                 return false;
12833
12834         return intel_fuzzy_clock_check(m, m2);
12835 }
12836
12837 static bool
12838 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12839                        const struct intel_link_m_n *m2_n2,
12840                        bool exact)
12841 {
12842         return m_n->tu == m2_n2->tu &&
12843                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12844                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12845                 intel_compare_m_n(m_n->link_m, m_n->link_n,
12846                                   m2_n2->link_m, m2_n2->link_n, exact);
12847 }
12848
12849 static bool
12850 intel_compare_infoframe(const union hdmi_infoframe *a,
12851                         const union hdmi_infoframe *b)
12852 {
12853         return memcmp(a, b, sizeof(*a)) == 0;
12854 }
12855
12856 static void
12857 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12858                                bool fastset, const char *name,
12859                                const union hdmi_infoframe *a,
12860                                const union hdmi_infoframe *b)
12861 {
12862         if (fastset) {
12863                 if ((drm_debug & DRM_UT_KMS) == 0)
12864                         return;
12865
12866                 DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name);
12867                 DRM_DEBUG_KMS("expected:\n");
12868                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12869                 DRM_DEBUG_KMS("found:\n");
12870                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12871         } else {
12872                 DRM_ERROR("mismatch in %s infoframe\n", name);
12873                 DRM_ERROR("expected:\n");
12874                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12875                 DRM_ERROR("found:\n");
12876                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12877         }
12878 }
12879
12880 static void __printf(4, 5)
12881 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
12882                      const char *name, const char *format, ...)
12883 {
12884         struct va_format vaf;
12885         va_list args;
12886
12887         va_start(args, format);
12888         vaf.fmt = format;
12889         vaf.va = &args;
12890
12891         if (fastset)
12892                 DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
12893                               crtc->base.base.id, crtc->base.name, name, &vaf);
12894         else
12895                 DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
12896                           crtc->base.base.id, crtc->base.name, name, &vaf);
12897
12898         va_end(args);
12899 }
12900
12901 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12902 {
12903         if (i915_modparams.fastboot != -1)
12904                 return i915_modparams.fastboot;
12905
12906         /* Enable fastboot by default on Skylake and newer */
12907         if (INTEL_GEN(dev_priv) >= 9)
12908                 return true;
12909
12910         /* Enable fastboot by default on VLV and CHV */
12911         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12912                 return true;
12913
12914         /* Disabled by default on all others */
12915         return false;
12916 }
12917
12918 static bool
12919 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
12920                           const struct intel_crtc_state *pipe_config,
12921                           bool fastset)
12922 {
12923         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
12924         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12925         bool ret = true;
12926         u32 bp_gamma = 0;
12927         bool fixup_inherited = fastset &&
12928                 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12929                 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
12930
12931         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12932                 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12933                 ret = false;
12934         }
12935
12936 #define PIPE_CONF_CHECK_X(name) do { \
12937         if (current_config->name != pipe_config->name) { \
12938                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12939                                      "(expected 0x%08x, found 0x%08x)", \
12940                                      current_config->name, \
12941                                      pipe_config->name); \
12942                 ret = false; \
12943         } \
12944 } while (0)
12945
12946 #define PIPE_CONF_CHECK_I(name) do { \
12947         if (current_config->name != pipe_config->name) { \
12948                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12949                                      "(expected %i, found %i)", \
12950                                      current_config->name, \
12951                                      pipe_config->name); \
12952                 ret = false; \
12953         } \
12954 } while (0)
12955
12956 #define PIPE_CONF_CHECK_BOOL(name) do { \
12957         if (current_config->name != pipe_config->name) { \
12958                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
12959                                      "(expected %s, found %s)", \
12960                                      yesno(current_config->name), \
12961                                      yesno(pipe_config->name)); \
12962                 ret = false; \
12963         } \
12964 } while (0)
12965
12966 /*
12967  * Checks state where we only read out the enabling, but not the entire
12968  * state itself (like full infoframes or ELD for audio). These states
12969  * require a full modeset on bootup to fix up.
12970  */
12971 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12972         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12973                 PIPE_CONF_CHECK_BOOL(name); \
12974         } else { \
12975                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12976                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
12977                                      yesno(current_config->name), \
12978                                      yesno(pipe_config->name)); \
12979                 ret = false; \
12980         } \
12981 } while (0)
12982
12983 #define PIPE_CONF_CHECK_P(name) do { \
12984         if (current_config->name != pipe_config->name) { \
12985                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12986                                      "(expected %p, found %p)", \
12987                                      current_config->name, \
12988                                      pipe_config->name); \
12989                 ret = false; \
12990         } \
12991 } while (0)
12992
12993 #define PIPE_CONF_CHECK_M_N(name) do { \
12994         if (!intel_compare_link_m_n(&current_config->name, \
12995                                     &pipe_config->name,\
12996                                     !fastset)) { \
12997                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12998                                      "(expected tu %i gmch %i/%i link %i/%i, " \
12999                                      "found tu %i, gmch %i/%i link %i/%i)", \
13000                                      current_config->name.tu, \
13001                                      current_config->name.gmch_m, \
13002                                      current_config->name.gmch_n, \
13003                                      current_config->name.link_m, \
13004                                      current_config->name.link_n, \
13005                                      pipe_config->name.tu, \
13006                                      pipe_config->name.gmch_m, \
13007                                      pipe_config->name.gmch_n, \
13008                                      pipe_config->name.link_m, \
13009                                      pipe_config->name.link_n); \
13010                 ret = false; \
13011         } \
13012 } while (0)
13013
13014 /* This is required for BDW+ where there is only one set of registers for
13015  * switching between high and low RR.
13016  * This macro can be used whenever a comparison has to be made between one
13017  * hw state and multiple sw state variables.
13018  */
13019 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13020         if (!intel_compare_link_m_n(&current_config->name, \
13021                                     &pipe_config->name, !fastset) && \
13022             !intel_compare_link_m_n(&current_config->alt_name, \
13023                                     &pipe_config->name, !fastset)) { \
13024                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13025                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13026                                      "or tu %i gmch %i/%i link %i/%i, " \
13027                                      "found tu %i, gmch %i/%i link %i/%i)", \
13028                                      current_config->name.tu, \
13029                                      current_config->name.gmch_m, \
13030                                      current_config->name.gmch_n, \
13031                                      current_config->name.link_m, \
13032                                      current_config->name.link_n, \
13033                                      current_config->alt_name.tu, \
13034                                      current_config->alt_name.gmch_m, \
13035                                      current_config->alt_name.gmch_n, \
13036                                      current_config->alt_name.link_m, \
13037                                      current_config->alt_name.link_n, \
13038                                      pipe_config->name.tu, \
13039                                      pipe_config->name.gmch_m, \
13040                                      pipe_config->name.gmch_n, \
13041                                      pipe_config->name.link_m, \
13042                                      pipe_config->name.link_n); \
13043                 ret = false; \
13044         } \
13045 } while (0)
13046
13047 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13048         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13049                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13050                                      "(%x) (expected %i, found %i)", \
13051                                      (mask), \
13052                                      current_config->name & (mask), \
13053                                      pipe_config->name & (mask)); \
13054                 ret = false; \
13055         } \
13056 } while (0)
13057
13058 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13059         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13060                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13061                                      "(expected %i, found %i)", \
13062                                      current_config->name, \
13063                                      pipe_config->name); \
13064                 ret = false; \
13065         } \
13066 } while (0)
13067
13068 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13069         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13070                                      &pipe_config->infoframes.name)) { \
13071                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13072                                                &current_config->infoframes.name, \
13073                                                &pipe_config->infoframes.name); \
13074                 ret = false; \
13075         } \
13076 } while (0)
13077
13078 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13079         if (current_config->name1 != pipe_config->name1) { \
13080                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13081                                 "(expected %i, found %i, won't compare lut values)", \
13082                                 current_config->name1, \
13083                                 pipe_config->name1); \
13084                 ret = false;\
13085         } else { \
13086                 if (!intel_color_lut_equal(current_config->name2, \
13087                                         pipe_config->name2, pipe_config->name1, \
13088                                         bit_precision)) { \
13089                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13090                                         "hw_state doesn't match sw_state"); \
13091                         ret = false; \
13092                 } \
13093         } \
13094 } while (0)
13095
13096 #define PIPE_CONF_QUIRK(quirk) \
13097         ((current_config->quirks | pipe_config->quirks) & (quirk))
13098
13099         PIPE_CONF_CHECK_I(cpu_transcoder);
13100
13101         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13102         PIPE_CONF_CHECK_I(fdi_lanes);
13103         PIPE_CONF_CHECK_M_N(fdi_m_n);
13104
13105         PIPE_CONF_CHECK_I(lane_count);
13106         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13107
13108         if (INTEL_GEN(dev_priv) < 8) {
13109                 PIPE_CONF_CHECK_M_N(dp_m_n);
13110
13111                 if (current_config->has_drrs)
13112                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13113         } else
13114                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13115
13116         PIPE_CONF_CHECK_X(output_types);
13117
13118         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13119         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13120         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13121         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13122         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13123         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13124
13125         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13126         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13127         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13128         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13129         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13130         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13131
13132         PIPE_CONF_CHECK_I(pixel_multiplier);
13133         PIPE_CONF_CHECK_I(output_format);
13134         PIPE_CONF_CHECK_I(dc3co_exitline);
13135         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13136         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13137             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13138                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13139
13140         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13141         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13142         PIPE_CONF_CHECK_BOOL(has_infoframe);
13143         PIPE_CONF_CHECK_BOOL(fec_enable);
13144
13145         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13146
13147         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13148                               DRM_MODE_FLAG_INTERLACE);
13149
13150         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13151                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13152                                       DRM_MODE_FLAG_PHSYNC);
13153                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13154                                       DRM_MODE_FLAG_NHSYNC);
13155                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13156                                       DRM_MODE_FLAG_PVSYNC);
13157                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13158                                       DRM_MODE_FLAG_NVSYNC);
13159         }
13160
13161         PIPE_CONF_CHECK_X(gmch_pfit.control);
13162         /* pfit ratios are autocomputed by the hw on gen4+ */
13163         if (INTEL_GEN(dev_priv) < 4)
13164                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13165         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13166
13167         /*
13168          * Changing the EDP transcoder input mux
13169          * (A_ONOFF vs. A_ON) requires a full modeset.
13170          */
13171         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13172
13173         if (!fastset) {
13174                 PIPE_CONF_CHECK_I(pipe_src_w);
13175                 PIPE_CONF_CHECK_I(pipe_src_h);
13176
13177                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13178                 if (current_config->pch_pfit.enabled) {
13179                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13180                         PIPE_CONF_CHECK_X(pch_pfit.size);
13181                 }
13182
13183                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13184                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13185
13186                 PIPE_CONF_CHECK_X(gamma_mode);
13187                 if (IS_CHERRYVIEW(dev_priv))
13188                         PIPE_CONF_CHECK_X(cgm_mode);
13189                 else
13190                         PIPE_CONF_CHECK_X(csc_mode);
13191                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13192                 PIPE_CONF_CHECK_BOOL(csc_enable);
13193
13194                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13195                 if (bp_gamma)
13196                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13197
13198         }
13199
13200         PIPE_CONF_CHECK_BOOL(double_wide);
13201
13202         PIPE_CONF_CHECK_P(shared_dpll);
13203         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13204         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13205         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13206         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13207         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13208         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13209         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13210         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13211         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13212         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13213         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13214         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13215         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13216         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13217         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13218         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13219         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13220         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13221         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13222         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13223         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13224         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13225         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13226         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13227         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13228         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13229         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13230         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13231         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13232         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13233         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13234
13235         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13236         PIPE_CONF_CHECK_X(dsi_pll.div);
13237
13238         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13239                 PIPE_CONF_CHECK_I(pipe_bpp);
13240
13241         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13242         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13243
13244         PIPE_CONF_CHECK_I(min_voltage_level);
13245
13246         PIPE_CONF_CHECK_X(infoframes.enable);
13247         PIPE_CONF_CHECK_X(infoframes.gcp);
13248         PIPE_CONF_CHECK_INFOFRAME(avi);
13249         PIPE_CONF_CHECK_INFOFRAME(spd);
13250         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13251         PIPE_CONF_CHECK_INFOFRAME(drm);
13252
13253         PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
13254         PIPE_CONF_CHECK_I(master_transcoder);
13255
13256 #undef PIPE_CONF_CHECK_X
13257 #undef PIPE_CONF_CHECK_I
13258 #undef PIPE_CONF_CHECK_BOOL
13259 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13260 #undef PIPE_CONF_CHECK_P
13261 #undef PIPE_CONF_CHECK_FLAGS
13262 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13263 #undef PIPE_CONF_CHECK_COLOR_LUT
13264 #undef PIPE_CONF_QUIRK
13265
13266         return ret;
13267 }
13268
13269 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13270                                            const struct intel_crtc_state *pipe_config)
13271 {
13272         if (pipe_config->has_pch_encoder) {
13273                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13274                                                             &pipe_config->fdi_m_n);
13275                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13276
13277                 /*
13278                  * FDI already provided one idea for the dotclock.
13279                  * Yell if the encoder disagrees.
13280                  */
13281                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13282                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13283                      fdi_dotclock, dotclock);
13284         }
13285 }
13286
13287 static void verify_wm_state(struct intel_crtc *crtc,
13288                             struct intel_crtc_state *new_crtc_state)
13289 {
13290         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13291         struct skl_hw_state {
13292                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13293                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13294                 struct skl_ddb_allocation ddb;
13295                 struct skl_pipe_wm wm;
13296         } *hw;
13297         struct skl_ddb_allocation *sw_ddb;
13298         struct skl_pipe_wm *sw_wm;
13299         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13300         const enum pipe pipe = crtc->pipe;
13301         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13302
13303         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13304                 return;
13305
13306         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13307         if (!hw)
13308                 return;
13309
13310         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13311         sw_wm = &new_crtc_state->wm.skl.optimal;
13312
13313         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13314
13315         skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13316         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13317
13318         if (INTEL_GEN(dev_priv) >= 11 &&
13319             hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13320                 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
13321                           sw_ddb->enabled_slices,
13322                           hw->ddb.enabled_slices);
13323
13324         /* planes */
13325         for_each_universal_plane(dev_priv, pipe, plane) {
13326                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13327
13328                 hw_plane_wm = &hw->wm.planes[plane];
13329                 sw_plane_wm = &sw_wm->planes[plane];
13330
13331                 /* Watermarks */
13332                 for (level = 0; level <= max_level; level++) {
13333                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13334                                                 &sw_plane_wm->wm[level]))
13335                                 continue;
13336
13337                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13338                                   pipe_name(pipe), plane + 1, level,
13339                                   sw_plane_wm->wm[level].plane_en,
13340                                   sw_plane_wm->wm[level].plane_res_b,
13341                                   sw_plane_wm->wm[level].plane_res_l,
13342                                   hw_plane_wm->wm[level].plane_en,
13343                                   hw_plane_wm->wm[level].plane_res_b,
13344                                   hw_plane_wm->wm[level].plane_res_l);
13345                 }
13346
13347                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13348                                          &sw_plane_wm->trans_wm)) {
13349                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13350                                   pipe_name(pipe), plane + 1,
13351                                   sw_plane_wm->trans_wm.plane_en,
13352                                   sw_plane_wm->trans_wm.plane_res_b,
13353                                   sw_plane_wm->trans_wm.plane_res_l,
13354                                   hw_plane_wm->trans_wm.plane_en,
13355                                   hw_plane_wm->trans_wm.plane_res_b,
13356                                   hw_plane_wm->trans_wm.plane_res_l);
13357                 }
13358
13359                 /* DDB */
13360                 hw_ddb_entry = &hw->ddb_y[plane];
13361                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13362
13363                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13364                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13365                                   pipe_name(pipe), plane + 1,
13366                                   sw_ddb_entry->start, sw_ddb_entry->end,
13367                                   hw_ddb_entry->start, hw_ddb_entry->end);
13368                 }
13369         }
13370
13371         /*
13372          * cursor
13373          * If the cursor plane isn't active, we may not have updated it's ddb
13374          * allocation. In that case since the ddb allocation will be updated
13375          * once the plane becomes visible, we can skip this check
13376          */
13377         if (1) {
13378                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13379
13380                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13381                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13382
13383                 /* Watermarks */
13384                 for (level = 0; level <= max_level; level++) {
13385                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13386                                                 &sw_plane_wm->wm[level]))
13387                                 continue;
13388
13389                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13390                                   pipe_name(pipe), level,
13391                                   sw_plane_wm->wm[level].plane_en,
13392                                   sw_plane_wm->wm[level].plane_res_b,
13393                                   sw_plane_wm->wm[level].plane_res_l,
13394                                   hw_plane_wm->wm[level].plane_en,
13395                                   hw_plane_wm->wm[level].plane_res_b,
13396                                   hw_plane_wm->wm[level].plane_res_l);
13397                 }
13398
13399                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13400                                          &sw_plane_wm->trans_wm)) {
13401                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13402                                   pipe_name(pipe),
13403                                   sw_plane_wm->trans_wm.plane_en,
13404                                   sw_plane_wm->trans_wm.plane_res_b,
13405                                   sw_plane_wm->trans_wm.plane_res_l,
13406                                   hw_plane_wm->trans_wm.plane_en,
13407                                   hw_plane_wm->trans_wm.plane_res_b,
13408                                   hw_plane_wm->trans_wm.plane_res_l);
13409                 }
13410
13411                 /* DDB */
13412                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13413                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13414
13415                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13416                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13417                                   pipe_name(pipe),
13418                                   sw_ddb_entry->start, sw_ddb_entry->end,
13419                                   hw_ddb_entry->start, hw_ddb_entry->end);
13420                 }
13421         }
13422
13423         kfree(hw);
13424 }
13425
13426 static void
13427 verify_connector_state(struct intel_atomic_state *state,
13428                        struct intel_crtc *crtc)
13429 {
13430         struct drm_connector *connector;
13431         struct drm_connector_state *new_conn_state;
13432         int i;
13433
13434         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13435                 struct drm_encoder *encoder = connector->encoder;
13436                 struct intel_crtc_state *crtc_state = NULL;
13437
13438                 if (new_conn_state->crtc != &crtc->base)
13439                         continue;
13440
13441                 if (crtc)
13442                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13443
13444                 intel_connector_verify_state(crtc_state, new_conn_state);
13445
13446                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13447                      "connector's atomic encoder doesn't match legacy encoder\n");
13448         }
13449 }
13450
13451 static void
13452 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13453 {
13454         struct intel_encoder *encoder;
13455         struct drm_connector *connector;
13456         struct drm_connector_state *old_conn_state, *new_conn_state;
13457         int i;
13458
13459         for_each_intel_encoder(&dev_priv->drm, encoder) {
13460                 bool enabled = false, found = false;
13461                 enum pipe pipe;
13462
13463                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13464                               encoder->base.base.id,
13465                               encoder->base.name);
13466
13467                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13468                                                    new_conn_state, i) {
13469                         if (old_conn_state->best_encoder == &encoder->base)
13470                                 found = true;
13471
13472                         if (new_conn_state->best_encoder != &encoder->base)
13473                                 continue;
13474                         found = enabled = true;
13475
13476                         I915_STATE_WARN(new_conn_state->crtc !=
13477                                         encoder->base.crtc,
13478                              "connector's crtc doesn't match encoder crtc\n");
13479                 }
13480
13481                 if (!found)
13482                         continue;
13483
13484                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13485                      "encoder's enabled state mismatch "
13486                      "(expected %i, found %i)\n",
13487                      !!encoder->base.crtc, enabled);
13488
13489                 if (!encoder->base.crtc) {
13490                         bool active;
13491
13492                         active = encoder->get_hw_state(encoder, &pipe);
13493                         I915_STATE_WARN(active,
13494                              "encoder detached but still enabled on pipe %c.\n",
13495                              pipe_name(pipe));
13496                 }
13497         }
13498 }
13499
13500 static void
13501 verify_crtc_state(struct intel_crtc *crtc,
13502                   struct intel_crtc_state *old_crtc_state,
13503                   struct intel_crtc_state *new_crtc_state)
13504 {
13505         struct drm_device *dev = crtc->base.dev;
13506         struct drm_i915_private *dev_priv = to_i915(dev);
13507         struct intel_encoder *encoder;
13508         struct intel_crtc_state *pipe_config;
13509         struct drm_atomic_state *state;
13510         bool active;
13511
13512         state = old_crtc_state->uapi.state;
13513         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
13514         intel_crtc_free_hw_state(old_crtc_state);
13515
13516         pipe_config = old_crtc_state;
13517         memset(pipe_config, 0, sizeof(*pipe_config));
13518         pipe_config->uapi.crtc = &crtc->base;
13519         pipe_config->uapi.state = state;
13520
13521         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13522
13523         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13524
13525         /* we keep both pipes enabled on 830 */
13526         if (IS_I830(dev_priv))
13527                 active = new_crtc_state->hw.active;
13528
13529         I915_STATE_WARN(new_crtc_state->hw.active != active,
13530                         "crtc active state doesn't match with hw state "
13531                         "(expected %i, found %i)\n",
13532                         new_crtc_state->hw.active, active);
13533
13534         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
13535                         "transitional active state does not match atomic hw state "
13536                         "(expected %i, found %i)\n",
13537                         new_crtc_state->hw.active, crtc->active);
13538
13539         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13540                 enum pipe pipe;
13541
13542                 active = encoder->get_hw_state(encoder, &pipe);
13543                 I915_STATE_WARN(active != new_crtc_state->hw.active,
13544                                 "[ENCODER:%i] active %i with crtc active %i\n",
13545                                 encoder->base.base.id, active,
13546                                 new_crtc_state->hw.active);
13547
13548                 I915_STATE_WARN(active && crtc->pipe != pipe,
13549                                 "Encoder connected to wrong pipe %c\n",
13550                                 pipe_name(pipe));
13551
13552                 if (active)
13553                         encoder->get_config(encoder, pipe_config);
13554         }
13555
13556         intel_crtc_compute_pixel_rate(pipe_config);
13557
13558         if (!new_crtc_state->hw.active)
13559                 return;
13560
13561         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13562
13563         if (!intel_pipe_config_compare(new_crtc_state,
13564                                        pipe_config, false)) {
13565                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13566                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13567                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13568         }
13569 }
13570
13571 static void
13572 intel_verify_planes(struct intel_atomic_state *state)
13573 {
13574         struct intel_plane *plane;
13575         const struct intel_plane_state *plane_state;
13576         int i;
13577
13578         for_each_new_intel_plane_in_state(state, plane,
13579                                           plane_state, i)
13580                 assert_plane(plane, plane_state->planar_slave ||
13581                              plane_state->uapi.visible);
13582 }
13583
13584 static void
13585 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13586                          struct intel_shared_dpll *pll,
13587                          struct intel_crtc *crtc,
13588                          struct intel_crtc_state *new_crtc_state)
13589 {
13590         struct intel_dpll_hw_state dpll_hw_state;
13591         unsigned int crtc_mask;
13592         bool active;
13593
13594         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13595
13596         DRM_DEBUG_KMS("%s\n", pll->info->name);
13597
13598         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13599
13600         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13601                 I915_STATE_WARN(!pll->on && pll->active_mask,
13602                      "pll in active use but not on in sw tracking\n");
13603                 I915_STATE_WARN(pll->on && !pll->active_mask,
13604                      "pll is on but not used by any active crtc\n");
13605                 I915_STATE_WARN(pll->on != active,
13606                      "pll on state mismatch (expected %i, found %i)\n",
13607                      pll->on, active);
13608         }
13609
13610         if (!crtc) {
13611                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13612                                 "more active pll users than references: %x vs %x\n",
13613                                 pll->active_mask, pll->state.crtc_mask);
13614
13615                 return;
13616         }
13617
13618         crtc_mask = drm_crtc_mask(&crtc->base);
13619
13620         if (new_crtc_state->hw.active)
13621                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13622                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13623                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13624         else
13625                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13626                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13627                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13628
13629         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13630                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13631                         crtc_mask, pll->state.crtc_mask);
13632
13633         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13634                                           &dpll_hw_state,
13635                                           sizeof(dpll_hw_state)),
13636                         "pll hw state mismatch\n");
13637 }
13638
13639 static void
13640 verify_shared_dpll_state(struct intel_crtc *crtc,
13641                          struct intel_crtc_state *old_crtc_state,
13642                          struct intel_crtc_state *new_crtc_state)
13643 {
13644         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13645
13646         if (new_crtc_state->shared_dpll)
13647                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13648
13649         if (old_crtc_state->shared_dpll &&
13650             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13651                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13652                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13653
13654                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13655                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13656                                 pipe_name(drm_crtc_index(&crtc->base)));
13657                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13658                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13659                                 pipe_name(drm_crtc_index(&crtc->base)));
13660         }
13661 }
13662
13663 static void
13664 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13665                           struct intel_atomic_state *state,
13666                           struct intel_crtc_state *old_crtc_state,
13667                           struct intel_crtc_state *new_crtc_state)
13668 {
13669         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13670                 return;
13671
13672         verify_wm_state(crtc, new_crtc_state);
13673         verify_connector_state(state, crtc);
13674         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13675         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13676 }
13677
13678 static void
13679 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13680 {
13681         int i;
13682
13683         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13684                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13685 }
13686
13687 static void
13688 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13689                               struct intel_atomic_state *state)
13690 {
13691         verify_encoder_state(dev_priv, state);
13692         verify_connector_state(state, NULL);
13693         verify_disabled_dpll_state(dev_priv);
13694 }
13695
13696 static void
13697 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
13698 {
13699         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13700         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13701         const struct drm_display_mode *adjusted_mode =
13702                 &crtc_state->hw.adjusted_mode;
13703
13704         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
13705
13706         /*
13707          * The scanline counter increments at the leading edge of hsync.
13708          *
13709          * On most platforms it starts counting from vtotal-1 on the
13710          * first active line. That means the scanline counter value is
13711          * always one less than what we would expect. Ie. just after
13712          * start of vblank, which also occurs at start of hsync (on the
13713          * last active line), the scanline counter will read vblank_start-1.
13714          *
13715          * On gen2 the scanline counter starts counting from 1 instead
13716          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13717          * to keep the value positive), instead of adding one.
13718          *
13719          * On HSW+ the behaviour of the scanline counter depends on the output
13720          * type. For DP ports it behaves like most other platforms, but on HDMI
13721          * there's an extra 1 line difference. So we need to add two instead of
13722          * one to the value.
13723          *
13724          * On VLV/CHV DSI the scanline counter would appear to increment
13725          * approx. 1/3 of a scanline before start of vblank. Unfortunately
13726          * that means we can't tell whether we're in vblank or not while
13727          * we're on that particular line. We must still set scanline_offset
13728          * to 1 so that the vblank timestamps come out correct when we query
13729          * the scanline counter from within the vblank interrupt handler.
13730          * However if queried just before the start of vblank we'll get an
13731          * answer that's slightly in the future.
13732          */
13733         if (IS_GEN(dev_priv, 2)) {
13734                 int vtotal;
13735
13736                 vtotal = adjusted_mode->crtc_vtotal;
13737                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13738                         vtotal /= 2;
13739
13740                 crtc->scanline_offset = vtotal - 1;
13741         } else if (HAS_DDI(dev_priv) &&
13742                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13743                 crtc->scanline_offset = 2;
13744         } else {
13745                 crtc->scanline_offset = 1;
13746         }
13747 }
13748
13749 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13750 {
13751         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13752         struct intel_crtc_state *new_crtc_state;
13753         struct intel_crtc *crtc;
13754         int i;
13755
13756         if (!dev_priv->display.crtc_compute_clock)
13757                 return;
13758
13759         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13760                 if (!needs_modeset(new_crtc_state))
13761                         continue;
13762
13763                 intel_release_shared_dplls(state, crtc);
13764         }
13765 }
13766
13767 /*
13768  * This implements the workaround described in the "notes" section of the mode
13769  * set sequence documentation. When going from no pipes or single pipe to
13770  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13771  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13772  */
13773 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13774 {
13775         struct intel_crtc_state *crtc_state;
13776         struct intel_crtc *crtc;
13777         struct intel_crtc_state *first_crtc_state = NULL;
13778         struct intel_crtc_state *other_crtc_state = NULL;
13779         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13780         int i;
13781
13782         /* look at all crtc's that are going to be enabled in during modeset */
13783         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13784                 if (!crtc_state->hw.active ||
13785                     !needs_modeset(crtc_state))
13786                         continue;
13787
13788                 if (first_crtc_state) {
13789                         other_crtc_state = crtc_state;
13790                         break;
13791                 } else {
13792                         first_crtc_state = crtc_state;
13793                         first_pipe = crtc->pipe;
13794                 }
13795         }
13796
13797         /* No workaround needed? */
13798         if (!first_crtc_state)
13799                 return 0;
13800
13801         /* w/a possibly needed, check how many crtc's are already enabled. */
13802         for_each_intel_crtc(state->base.dev, crtc) {
13803                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13804                 if (IS_ERR(crtc_state))
13805                         return PTR_ERR(crtc_state);
13806
13807                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13808
13809                 if (!crtc_state->hw.active ||
13810                     needs_modeset(crtc_state))
13811                         continue;
13812
13813                 /* 2 or more enabled crtcs means no need for w/a */
13814                 if (enabled_pipe != INVALID_PIPE)
13815                         return 0;
13816
13817                 enabled_pipe = crtc->pipe;
13818         }
13819
13820         if (enabled_pipe != INVALID_PIPE)
13821                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13822         else if (other_crtc_state)
13823                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13824
13825         return 0;
13826 }
13827
13828 static int intel_modeset_checks(struct intel_atomic_state *state)
13829 {
13830         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13831         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13832         struct intel_crtc *crtc;
13833         int ret, i;
13834
13835         /* keep the current setting */
13836         if (!state->cdclk.force_min_cdclk_changed)
13837                 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13838
13839         state->modeset = true;
13840         state->active_pipes = dev_priv->active_pipes;
13841         state->cdclk.logical = dev_priv->cdclk.logical;
13842         state->cdclk.actual = dev_priv->cdclk.actual;
13843
13844         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13845                                             new_crtc_state, i) {
13846                 if (new_crtc_state->hw.active)
13847                         state->active_pipes |= BIT(crtc->pipe);
13848                 else
13849                         state->active_pipes &= ~BIT(crtc->pipe);
13850
13851                 if (old_crtc_state->hw.active != new_crtc_state->hw.active)
13852                         state->active_pipe_changes |= BIT(crtc->pipe);
13853         }
13854
13855         if (state->active_pipe_changes) {
13856                 ret = intel_atomic_lock_global_state(state);
13857                 if (ret)
13858                         return ret;
13859         }
13860
13861         ret = intel_modeset_calc_cdclk(state);
13862         if (ret)
13863                 return ret;
13864
13865         intel_modeset_clear_plls(state);
13866
13867         if (IS_HASWELL(dev_priv))
13868                 return haswell_mode_set_planes_workaround(state);
13869
13870         return 0;
13871 }
13872
13873 /*
13874  * Handle calculation of various watermark data at the end of the atomic check
13875  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13876  * handlers to ensure that all derived state has been updated.
13877  */
13878 static int calc_watermark_data(struct intel_atomic_state *state)
13879 {
13880         struct drm_device *dev = state->base.dev;
13881         struct drm_i915_private *dev_priv = to_i915(dev);
13882
13883         /* Is there platform-specific watermark information to calculate? */
13884         if (dev_priv->display.compute_global_watermarks)
13885                 return dev_priv->display.compute_global_watermarks(state);
13886
13887         return 0;
13888 }
13889
13890 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13891                                      struct intel_crtc_state *new_crtc_state)
13892 {
13893         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
13894                 return;
13895
13896         new_crtc_state->uapi.mode_changed = false;
13897         new_crtc_state->update_pipe = true;
13898
13899         /*
13900          * If we're not doing the full modeset we want to
13901          * keep the current M/N values as they may be
13902          * sufficiently different to the computed values
13903          * to cause problems.
13904          *
13905          * FIXME: should really copy more fuzzy state here
13906          */
13907         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
13908         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
13909         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
13910         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
13911 }
13912
13913 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
13914                                           struct intel_crtc *crtc,
13915                                           u8 plane_ids_mask)
13916 {
13917         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13918         struct intel_plane *plane;
13919
13920         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13921                 struct intel_plane_state *plane_state;
13922
13923                 if ((plane_ids_mask & BIT(plane->id)) == 0)
13924                         continue;
13925
13926                 plane_state = intel_atomic_get_plane_state(state, plane);
13927                 if (IS_ERR(plane_state))
13928                         return PTR_ERR(plane_state);
13929         }
13930
13931         return 0;
13932 }
13933
13934 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
13935 {
13936         /* See {hsw,vlv,ivb}_plane_ratio() */
13937         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
13938                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
13939                 IS_IVYBRIDGE(dev_priv);
13940 }
13941
13942 static int intel_atomic_check_planes(struct intel_atomic_state *state,
13943                                      bool *need_modeset)
13944 {
13945         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13946         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13947         struct intel_plane_state *plane_state;
13948         struct intel_plane *plane;
13949         struct intel_crtc *crtc;
13950         int i, ret;
13951
13952         ret = icl_add_linked_planes(state);
13953         if (ret)
13954                 return ret;
13955
13956         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13957                 ret = intel_plane_atomic_check(state, plane);
13958                 if (ret) {
13959                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
13960                                          plane->base.base.id, plane->base.name);
13961                         return ret;
13962                 }
13963         }
13964
13965         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13966                                             new_crtc_state, i) {
13967                 u8 old_active_planes, new_active_planes;
13968
13969                 ret = icl_check_nv12_planes(new_crtc_state);
13970                 if (ret)
13971                         return ret;
13972
13973                 /*
13974                  * On some platforms the number of active planes affects
13975                  * the planes' minimum cdclk calculation. Add such planes
13976                  * to the state before we compute the minimum cdclk.
13977                  */
13978                 if (!active_planes_affects_min_cdclk(dev_priv))
13979                         continue;
13980
13981                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
13982                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
13983
13984                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
13985                         continue;
13986
13987                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
13988                 if (ret)
13989                         return ret;
13990         }
13991
13992         /*
13993          * active_planes bitmask has been updated, and potentially
13994          * affected planes are part of the state. We can now
13995          * compute the minimum cdclk for each plane.
13996          */
13997         for_each_new_intel_plane_in_state(state, plane, plane_state, i)
13998                 *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
13999
14000         return 0;
14001 }
14002
14003 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14004 {
14005         struct intel_crtc_state *crtc_state;
14006         struct intel_crtc *crtc;
14007         int i;
14008
14009         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14010                 int ret = intel_crtc_atomic_check(state, crtc);
14011                 if (ret) {
14012                         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
14013                                          crtc->base.base.id, crtc->base.name);
14014                         return ret;
14015                 }
14016         }
14017
14018         return 0;
14019 }
14020
14021 /**
14022  * intel_atomic_check - validate state object
14023  * @dev: drm device
14024  * @_state: state to validate
14025  */
14026 static int intel_atomic_check(struct drm_device *dev,
14027                               struct drm_atomic_state *_state)
14028 {
14029         struct drm_i915_private *dev_priv = to_i915(dev);
14030         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14031         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14032         struct intel_crtc *crtc;
14033         int ret, i;
14034         bool any_ms = false;
14035
14036         /* Catch I915_MODE_FLAG_INHERITED */
14037         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14038                                             new_crtc_state, i) {
14039                 if (new_crtc_state->hw.mode.private_flags !=
14040                     old_crtc_state->hw.mode.private_flags)
14041                         new_crtc_state->uapi.mode_changed = true;
14042         }
14043
14044         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14045         if (ret)
14046                 goto fail;
14047
14048         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14049                                             new_crtc_state, i) {
14050                 if (!needs_modeset(new_crtc_state)) {
14051                         /* Light copy */
14052                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14053
14054                         continue;
14055                 }
14056
14057                 if (!new_crtc_state->uapi.enable) {
14058                         intel_crtc_copy_uapi_to_hw_state(new_crtc_state);
14059
14060                         any_ms = true;
14061                         continue;
14062                 }
14063
14064                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14065                 if (ret)
14066                         goto fail;
14067
14068                 ret = intel_modeset_pipe_config(new_crtc_state);
14069                 if (ret)
14070                         goto fail;
14071
14072                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14073
14074                 if (needs_modeset(new_crtc_state))
14075                         any_ms = true;
14076         }
14077
14078         if (any_ms && !check_digital_port_conflicts(state)) {
14079                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14080                 ret = EINVAL;
14081                 goto fail;
14082         }
14083
14084         ret = drm_dp_mst_atomic_check(&state->base);
14085         if (ret)
14086                 goto fail;
14087
14088         any_ms |= state->cdclk.force_min_cdclk_changed;
14089
14090         ret = intel_atomic_check_planes(state, &any_ms);
14091         if (ret)
14092                 goto fail;
14093
14094         if (any_ms) {
14095                 ret = intel_modeset_checks(state);
14096                 if (ret)
14097                         goto fail;
14098         } else {
14099                 state->cdclk.logical = dev_priv->cdclk.logical;
14100         }
14101
14102         ret = intel_atomic_check_crtcs(state);
14103         if (ret)
14104                 goto fail;
14105
14106         intel_fbc_choose_crtc(dev_priv, state);
14107         ret = calc_watermark_data(state);
14108         if (ret)
14109                 goto fail;
14110
14111         ret = intel_bw_atomic_check(state);
14112         if (ret)
14113                 goto fail;
14114
14115         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14116                                             new_crtc_state, i) {
14117                 if (!needs_modeset(new_crtc_state) &&
14118                     !new_crtc_state->update_pipe)
14119                         continue;
14120
14121                 intel_dump_pipe_config(new_crtc_state, state,
14122                                        needs_modeset(new_crtc_state) ?
14123                                        "[modeset]" : "[fastset]");
14124         }
14125
14126         return 0;
14127
14128  fail:
14129         if (ret == -EDEADLK)
14130                 return ret;
14131
14132         /*
14133          * FIXME would probably be nice to know which crtc specifically
14134          * caused the failure, in cases where we can pinpoint it.
14135          */
14136         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14137                                             new_crtc_state, i)
14138                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14139
14140         return ret;
14141 }
14142
14143 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14144 {
14145         return drm_atomic_helper_prepare_planes(state->base.dev,
14146                                                 &state->base);
14147 }
14148
14149 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14150 {
14151         struct drm_device *dev = crtc->base.dev;
14152         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14153
14154         if (!vblank->max_vblank_count)
14155                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14156
14157         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14158 }
14159
14160 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14161                                   struct intel_crtc_state *crtc_state)
14162 {
14163         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14164
14165         if (!IS_GEN(dev_priv, 2))
14166                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14167
14168         if (crtc_state->has_pch_encoder) {
14169                 enum pipe pch_transcoder =
14170                         intel_crtc_pch_transcoder(crtc);
14171
14172                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14173         }
14174 }
14175
14176 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14177                                const struct intel_crtc_state *new_crtc_state)
14178 {
14179         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14180         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14181
14182         /*
14183          * Update pipe size and adjust fitter if needed: the reason for this is
14184          * that in compute_mode_changes we check the native mode (not the pfit
14185          * mode) to see if we can flip rather than do a full mode set. In the
14186          * fastboot case, we'll flip, but if we don't update the pipesrc and
14187          * pfit state, we'll end up with a big fb scanned out into the wrong
14188          * sized surface.
14189          */
14190         intel_set_pipe_src_size(new_crtc_state);
14191
14192         /* on skylake this is done by detaching scalers */
14193         if (INTEL_GEN(dev_priv) >= 9) {
14194                 skl_detach_scalers(new_crtc_state);
14195
14196                 if (new_crtc_state->pch_pfit.enabled)
14197                         skylake_pfit_enable(new_crtc_state);
14198         } else if (HAS_PCH_SPLIT(dev_priv)) {
14199                 if (new_crtc_state->pch_pfit.enabled)
14200                         ironlake_pfit_enable(new_crtc_state);
14201                 else if (old_crtc_state->pch_pfit.enabled)
14202                         ironlake_pfit_disable(old_crtc_state);
14203         }
14204
14205         if (INTEL_GEN(dev_priv) >= 11)
14206                 icl_set_pipe_chicken(crtc);
14207 }
14208
14209 static void commit_pipe_config(struct intel_atomic_state *state,
14210                                struct intel_crtc_state *old_crtc_state,
14211                                struct intel_crtc_state *new_crtc_state)
14212 {
14213         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14214         bool modeset = needs_modeset(new_crtc_state);
14215
14216         /*
14217          * During modesets pipe configuration was programmed as the
14218          * CRTC was enabled.
14219          */
14220         if (!modeset) {
14221                 if (new_crtc_state->uapi.color_mgmt_changed ||
14222                     new_crtc_state->update_pipe)
14223                         intel_color_commit(new_crtc_state);
14224
14225                 if (INTEL_GEN(dev_priv) >= 9)
14226                         skl_detach_scalers(new_crtc_state);
14227
14228                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14229                         bdw_set_pipemisc(new_crtc_state);
14230
14231                 if (new_crtc_state->update_pipe)
14232                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
14233         }
14234
14235         if (dev_priv->display.atomic_update_watermarks)
14236                 dev_priv->display.atomic_update_watermarks(state,
14237                                                            new_crtc_state);
14238 }
14239
14240 static void intel_update_crtc(struct intel_crtc *crtc,
14241                               struct intel_atomic_state *state,
14242                               struct intel_crtc_state *old_crtc_state,
14243                               struct intel_crtc_state *new_crtc_state)
14244 {
14245         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14246         bool modeset = needs_modeset(new_crtc_state);
14247         struct intel_plane_state *new_plane_state =
14248                 intel_atomic_get_new_plane_state(state,
14249                                                  to_intel_plane(crtc->base.primary));
14250
14251         if (modeset) {
14252                 intel_crtc_update_active_timings(new_crtc_state);
14253
14254                 dev_priv->display.crtc_enable(new_crtc_state, state);
14255
14256                 /* vblanks work again, re-enable pipe CRC. */
14257                 intel_crtc_enable_pipe_crc(crtc);
14258         } else {
14259                 intel_pre_plane_update(old_crtc_state, new_crtc_state);
14260
14261                 if (new_crtc_state->update_pipe)
14262                         intel_encoders_update_pipe(crtc, new_crtc_state, state);
14263         }
14264
14265         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14266                 intel_fbc_disable(crtc);
14267         else if (new_plane_state)
14268                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14269
14270         /* Perform vblank evasion around commit operation */
14271         intel_pipe_update_start(new_crtc_state);
14272
14273         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14274
14275         if (INTEL_GEN(dev_priv) >= 9)
14276                 skl_update_planes_on_crtc(state, crtc);
14277         else
14278                 i9xx_update_planes_on_crtc(state, crtc);
14279
14280         intel_pipe_update_end(new_crtc_state);
14281
14282         /*
14283          * We usually enable FIFO underrun interrupts as part of the
14284          * CRTC enable sequence during modesets.  But when we inherit a
14285          * valid pipe configuration from the BIOS we need to take care
14286          * of enabling them on the CRTC's first fastset.
14287          */
14288         if (new_crtc_state->update_pipe && !modeset &&
14289             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14290                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14291 }
14292
14293 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
14294 {
14295         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
14296         enum transcoder slave_transcoder;
14297
14298         WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
14299
14300         slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
14301         return intel_get_crtc_for_pipe(dev_priv,
14302                                        (enum pipe)slave_transcoder);
14303 }
14304
14305 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
14306                                           struct intel_crtc_state *old_crtc_state,
14307                                           struct intel_crtc_state *new_crtc_state,
14308                                           struct intel_crtc *crtc)
14309 {
14310         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14311
14312         intel_crtc_disable_planes(state, crtc);
14313
14314         /*
14315          * We need to disable pipe CRC before disabling the pipe,
14316          * or we race against vblank off.
14317          */
14318         intel_crtc_disable_pipe_crc(crtc);
14319
14320         dev_priv->display.crtc_disable(old_crtc_state, state);
14321         crtc->active = false;
14322         intel_fbc_disable(crtc);
14323         intel_disable_shared_dpll(old_crtc_state);
14324
14325         /*
14326          * Underruns don't always raise interrupts,
14327          * so check manually.
14328          */
14329         intel_check_cpu_fifo_underruns(dev_priv);
14330         intel_check_pch_fifo_underruns(dev_priv);
14331
14332         /* FIXME unify this for all platforms */
14333         if (!new_crtc_state->hw.active &&
14334             !HAS_GMCH(dev_priv) &&
14335             dev_priv->display.initial_watermarks)
14336                 dev_priv->display.initial_watermarks(state,
14337                                                      new_crtc_state);
14338 }
14339
14340 static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
14341                                                    struct intel_crtc *crtc,
14342                                                    struct intel_crtc_state *old_crtc_state,
14343                                                    struct intel_crtc_state *new_crtc_state)
14344 {
14345         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14346         struct intel_crtc_state *new_slave_crtc_state =
14347                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14348         struct intel_crtc_state *old_slave_crtc_state =
14349                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14350
14351         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14352                 !old_slave_crtc_state);
14353
14354         /* Disable Slave first */
14355         intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
14356         if (old_slave_crtc_state->hw.active)
14357                 intel_old_crtc_state_disables(state,
14358                                               old_slave_crtc_state,
14359                                               new_slave_crtc_state,
14360                                               slave_crtc);
14361
14362         /* Disable Master */
14363         intel_pre_plane_update(old_crtc_state, new_crtc_state);
14364         if (old_crtc_state->hw.active)
14365                 intel_old_crtc_state_disables(state,
14366                                               old_crtc_state,
14367                                               new_crtc_state,
14368                                               crtc);
14369 }
14370
14371 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
14372 {
14373         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14374         struct intel_crtc *crtc;
14375         int i;
14376
14377         /*
14378          * Disable CRTC/pipes in reverse order because some features(MST in
14379          * TGL+) requires master and slave relationship between pipes, so it
14380          * should always pick the lowest pipe as master as it will be enabled
14381          * first and disable in the reverse order so the master will be the
14382          * last one to be disabled.
14383          */
14384         for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
14385                                                     new_crtc_state, i) {
14386                 if (!needs_modeset(new_crtc_state))
14387                         continue;
14388
14389                 /* In case of Transcoder port Sync master slave CRTCs can be
14390                  * assigned in any order and we need to make sure that
14391                  * slave CRTCs are disabled first and then master CRTC since
14392                  * Slave vblanks are masked till Master Vblanks.
14393                  */
14394                 if (is_trans_port_sync_mode(new_crtc_state)) {
14395                         if (is_trans_port_sync_master(new_crtc_state))
14396                                 intel_trans_port_sync_modeset_disables(state,
14397                                                                        crtc,
14398                                                                        old_crtc_state,
14399                                                                        new_crtc_state);
14400                         else
14401                                 continue;
14402                 } else {
14403                         intel_pre_plane_update(old_crtc_state, new_crtc_state);
14404
14405                         if (old_crtc_state->hw.active)
14406                                 intel_old_crtc_state_disables(state,
14407                                                               old_crtc_state,
14408                                                               new_crtc_state,
14409                                                               crtc);
14410                 }
14411         }
14412 }
14413
14414 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
14415 {
14416         struct intel_crtc *crtc;
14417         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14418         int i;
14419
14420         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14421                 if (!new_crtc_state->hw.active)
14422                         continue;
14423
14424                 intel_update_crtc(crtc, state, old_crtc_state,
14425                                   new_crtc_state);
14426         }
14427 }
14428
14429 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
14430                                               struct intel_atomic_state *state,
14431                                               struct intel_crtc_state *new_crtc_state)
14432 {
14433         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14434
14435         intel_crtc_update_active_timings(new_crtc_state);
14436         dev_priv->display.crtc_enable(new_crtc_state, state);
14437         intel_crtc_enable_pipe_crc(crtc);
14438 }
14439
14440 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
14441                                        struct intel_atomic_state *state)
14442 {
14443         struct drm_connector *uninitialized_var(conn);
14444         struct drm_connector_state *conn_state;
14445         struct intel_dp *intel_dp;
14446         int i;
14447
14448         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
14449                 if (conn_state->crtc == &crtc->base)
14450                         break;
14451         }
14452         intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
14453         intel_dp_stop_link_train(intel_dp);
14454 }
14455
14456 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
14457                                            struct intel_atomic_state *state)
14458 {
14459         struct intel_crtc_state *new_crtc_state =
14460                 intel_atomic_get_new_crtc_state(state, crtc);
14461         struct intel_crtc_state *old_crtc_state =
14462                 intel_atomic_get_old_crtc_state(state, crtc);
14463         struct intel_plane_state *new_plane_state =
14464                 intel_atomic_get_new_plane_state(state,
14465                                                  to_intel_plane(crtc->base.primary));
14466         bool modeset = needs_modeset(new_crtc_state);
14467
14468         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14469                 intel_fbc_disable(crtc);
14470         else if (new_plane_state)
14471                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14472
14473         /* Perform vblank evasion around commit operation */
14474         intel_pipe_update_start(new_crtc_state);
14475         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14476         skl_update_planes_on_crtc(state, crtc);
14477         intel_pipe_update_end(new_crtc_state);
14478
14479         /*
14480          * We usually enable FIFO underrun interrupts as part of the
14481          * CRTC enable sequence during modesets.  But when we inherit a
14482          * valid pipe configuration from the BIOS we need to take care
14483          * of enabling them on the CRTC's first fastset.
14484          */
14485         if (new_crtc_state->update_pipe && !modeset &&
14486             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14487                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14488 }
14489
14490 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
14491                                                struct intel_atomic_state *state,
14492                                                struct intel_crtc_state *old_crtc_state,
14493                                                struct intel_crtc_state *new_crtc_state)
14494 {
14495         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14496         struct intel_crtc_state *new_slave_crtc_state =
14497                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14498         struct intel_crtc_state *old_slave_crtc_state =
14499                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14500
14501         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14502                 !old_slave_crtc_state);
14503
14504         DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
14505                       crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
14506                       slave_crtc->base.name);
14507
14508         /* Enable seq for slave with with DP_TP_CTL left Idle until the
14509          * master is ready
14510          */
14511         intel_crtc_enable_trans_port_sync(slave_crtc,
14512                                           state,
14513                                           new_slave_crtc_state);
14514
14515         /* Enable seq for master with with DP_TP_CTL left Idle */
14516         intel_crtc_enable_trans_port_sync(crtc,
14517                                           state,
14518                                           new_crtc_state);
14519
14520         /* Set Slave's DP_TP_CTL to Normal */
14521         intel_set_dp_tp_ctl_normal(slave_crtc,
14522                                    state);
14523
14524         /* Set Master's DP_TP_CTL To Normal */
14525         usleep_range(200, 400);
14526         intel_set_dp_tp_ctl_normal(crtc,
14527                                    state);
14528
14529         /* Now do the post crtc enable for all master and slaves */
14530         intel_post_crtc_enable_updates(slave_crtc,
14531                                        state);
14532         intel_post_crtc_enable_updates(crtc,
14533                                        state);
14534 }
14535
14536 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
14537 {
14538         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14539         struct intel_crtc *crtc;
14540         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14541         unsigned int updated = 0;
14542         bool progress;
14543         int i;
14544         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
14545         u8 required_slices = state->wm_results.ddb.enabled_slices;
14546         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
14547
14548         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
14549                 /* ignore allocations for crtc's that have been turned off. */
14550                 if (new_crtc_state->hw.active)
14551                         entries[i] = old_crtc_state->wm.skl.ddb;
14552
14553         /* If 2nd DBuf slice required, enable it here */
14554         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
14555                 icl_dbuf_slices_update(dev_priv, required_slices);
14556
14557         /*
14558          * Whenever the number of active pipes changes, we need to make sure we
14559          * update the pipes in the right order so that their ddb allocations
14560          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14561          * cause pipe underruns and other bad stuff.
14562          */
14563         do {
14564                 progress = false;
14565
14566                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14567                         enum pipe pipe = crtc->pipe;
14568                         bool vbl_wait = false;
14569                         bool modeset = needs_modeset(new_crtc_state);
14570
14571                         if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
14572                                 continue;
14573
14574                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
14575                                                         entries,
14576                                                         INTEL_NUM_PIPES(dev_priv), i))
14577                                 continue;
14578
14579                         updated |= BIT(pipe);
14580                         entries[i] = new_crtc_state->wm.skl.ddb;
14581
14582                         /*
14583                          * If this is an already active pipe, it's DDB changed,
14584                          * and this isn't the last pipe that needs updating
14585                          * then we need to wait for a vblank to pass for the
14586                          * new ddb allocation to take effect.
14587                          */
14588                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
14589                                                  &old_crtc_state->wm.skl.ddb) &&
14590                             !modeset &&
14591                             state->wm_results.dirty_pipes != updated)
14592                                 vbl_wait = true;
14593
14594                         if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
14595                                 if (is_trans_port_sync_master(new_crtc_state))
14596                                         intel_update_trans_port_sync_crtcs(crtc,
14597                                                                            state,
14598                                                                            old_crtc_state,
14599                                                                            new_crtc_state);
14600                                 else
14601                                         continue;
14602                         } else {
14603                                 intel_update_crtc(crtc, state, old_crtc_state,
14604                                                   new_crtc_state);
14605                         }
14606
14607                         if (vbl_wait)
14608                                 intel_wait_for_vblank(dev_priv, pipe);
14609
14610                         progress = true;
14611                 }
14612         } while (progress);
14613
14614         /* If 2nd DBuf slice is no more required disable it */
14615         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
14616                 icl_dbuf_slices_update(dev_priv, required_slices);
14617 }
14618
14619 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14620 {
14621         struct intel_atomic_state *state, *next;
14622         struct llist_node *freed;
14623
14624         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14625         llist_for_each_entry_safe(state, next, freed, freed)
14626                 drm_atomic_state_put(&state->base);
14627 }
14628
14629 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14630 {
14631         struct drm_i915_private *dev_priv =
14632                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14633
14634         intel_atomic_helper_free_state(dev_priv);
14635 }
14636
14637 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
14638 {
14639         struct wait_queue_entry wait_fence, wait_reset;
14640         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
14641
14642         init_wait_entry(&wait_fence, 0);
14643         init_wait_entry(&wait_reset, 0);
14644         for (;;) {
14645                 prepare_to_wait(&intel_state->commit_ready.wait,
14646                                 &wait_fence, TASK_UNINTERRUPTIBLE);
14647                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14648                                               I915_RESET_MODESET),
14649                                 &wait_reset, TASK_UNINTERRUPTIBLE);
14650
14651
14652                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
14653                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
14654                         break;
14655
14656                 schedule();
14657         }
14658         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
14659         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14660                                   I915_RESET_MODESET),
14661                     &wait_reset);
14662 }
14663
14664 static void intel_atomic_cleanup_work(struct work_struct *work)
14665 {
14666         struct drm_atomic_state *state =
14667                 container_of(work, struct drm_atomic_state, commit_work);
14668         struct drm_i915_private *i915 = to_i915(state->dev);
14669
14670         drm_atomic_helper_cleanup_planes(&i915->drm, state);
14671         drm_atomic_helper_commit_cleanup_done(state);
14672         drm_atomic_state_put(state);
14673
14674         intel_atomic_helper_free_state(i915);
14675 }
14676
14677 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
14678 {
14679         struct drm_device *dev = state->base.dev;
14680         struct drm_i915_private *dev_priv = to_i915(dev);
14681         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14682         struct intel_crtc *crtc;
14683         u64 put_domains[I915_MAX_PIPES] = {};
14684         intel_wakeref_t wakeref = 0;
14685         int i;
14686
14687         intel_atomic_commit_fence_wait(state);
14688
14689         drm_atomic_helper_wait_for_dependencies(&state->base);
14690
14691         if (state->modeset)
14692                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14693
14694         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14695                                             new_crtc_state, i) {
14696                 if (needs_modeset(new_crtc_state) ||
14697                     new_crtc_state->update_pipe) {
14698
14699                         put_domains[crtc->pipe] =
14700                                 modeset_get_crtc_power_domains(new_crtc_state);
14701                 }
14702         }
14703
14704         intel_commit_modeset_disables(state);
14705
14706         /* FIXME: Eventually get rid of our crtc->config pointer */
14707         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14708                 crtc->config = new_crtc_state;
14709
14710         if (state->modeset) {
14711                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14712
14713                 intel_set_cdclk_pre_plane_update(dev_priv,
14714                                                  &state->cdclk.actual,
14715                                                  &dev_priv->cdclk.actual,
14716                                                  state->cdclk.pipe);
14717
14718                 /*
14719                  * SKL workaround: bspec recommends we disable the SAGV when we
14720                  * have more then one pipe enabled
14721                  */
14722                 if (!intel_can_enable_sagv(state))
14723                         intel_disable_sagv(dev_priv);
14724
14725                 intel_modeset_verify_disabled(dev_priv, state);
14726         }
14727
14728         /* Complete the events for pipes that have now been disabled */
14729         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14730                 bool modeset = needs_modeset(new_crtc_state);
14731
14732                 /* Complete events for now disable pipes here. */
14733                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
14734                         spin_lock_irq(&dev->event_lock);
14735                         drm_crtc_send_vblank_event(&crtc->base,
14736                                                    new_crtc_state->uapi.event);
14737                         spin_unlock_irq(&dev->event_lock);
14738
14739                         new_crtc_state->uapi.event = NULL;
14740                 }
14741         }
14742
14743         if (state->modeset)
14744                 intel_encoders_update_prepare(state);
14745
14746         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14747         dev_priv->display.commit_modeset_enables(state);
14748
14749         if (state->modeset) {
14750                 intel_encoders_update_complete(state);
14751
14752                 intel_set_cdclk_post_plane_update(dev_priv,
14753                                                   &state->cdclk.actual,
14754                                                   &dev_priv->cdclk.actual,
14755                                                   state->cdclk.pipe);
14756         }
14757
14758         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14759          * already, but still need the state for the delayed optimization. To
14760          * fix this:
14761          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14762          * - schedule that vblank worker _before_ calling hw_done
14763          * - at the start of commit_tail, cancel it _synchrously
14764          * - switch over to the vblank wait helper in the core after that since
14765          *   we don't need out special handling any more.
14766          */
14767         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14768
14769         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14770                 if (new_crtc_state->hw.active &&
14771                     !needs_modeset(new_crtc_state) &&
14772                     (new_crtc_state->uapi.color_mgmt_changed ||
14773                      new_crtc_state->update_pipe))
14774                         intel_color_load_luts(new_crtc_state);
14775         }
14776
14777         /*
14778          * Now that the vblank has passed, we can go ahead and program the
14779          * optimal watermarks on platforms that need two-step watermark
14780          * programming.
14781          *
14782          * TODO: Move this (and other cleanup) to an async worker eventually.
14783          */
14784         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14785                 if (dev_priv->display.optimize_watermarks)
14786                         dev_priv->display.optimize_watermarks(state,
14787                                                               new_crtc_state);
14788         }
14789
14790         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14791                 intel_post_plane_update(old_crtc_state);
14792
14793                 if (put_domains[i])
14794                         modeset_put_power_domains(dev_priv, put_domains[i]);
14795
14796                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14797         }
14798
14799         if (state->modeset)
14800                 intel_verify_planes(state);
14801
14802         if (state->modeset && intel_can_enable_sagv(state))
14803                 intel_enable_sagv(dev_priv);
14804
14805         drm_atomic_helper_commit_hw_done(&state->base);
14806
14807         if (state->modeset) {
14808                 /* As one of the primary mmio accessors, KMS has a high
14809                  * likelihood of triggering bugs in unclaimed access. After we
14810                  * finish modesetting, see if an error has been flagged, and if
14811                  * so enable debugging for the next modeset - and hope we catch
14812                  * the culprit.
14813                  */
14814                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14815                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14816         }
14817         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14818
14819         /*
14820          * Defer the cleanup of the old state to a separate worker to not
14821          * impede the current task (userspace for blocking modesets) that
14822          * are executed inline. For out-of-line asynchronous modesets/flips,
14823          * deferring to a new worker seems overkill, but we would place a
14824          * schedule point (cond_resched()) here anyway to keep latencies
14825          * down.
14826          */
14827         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14828         queue_work(system_highpri_wq, &state->base.commit_work);
14829 }
14830
14831 static void intel_atomic_commit_work(struct work_struct *work)
14832 {
14833         struct intel_atomic_state *state =
14834                 container_of(work, struct intel_atomic_state, base.commit_work);
14835
14836         intel_atomic_commit_tail(state);
14837 }
14838
14839 static int __i915_sw_fence_call
14840 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14841                           enum i915_sw_fence_notify notify)
14842 {
14843         struct intel_atomic_state *state =
14844                 container_of(fence, struct intel_atomic_state, commit_ready);
14845
14846         switch (notify) {
14847         case FENCE_COMPLETE:
14848                 /* we do blocking waits in the worker, nothing to do here */
14849                 break;
14850         case FENCE_FREE:
14851                 {
14852                         struct intel_atomic_helper *helper =
14853                                 &to_i915(state->base.dev)->atomic_helper;
14854
14855                         if (llist_add(&state->freed, &helper->free_list))
14856                                 schedule_work(&helper->free_work);
14857                         break;
14858                 }
14859         }
14860
14861         return NOTIFY_DONE;
14862 }
14863
14864 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14865 {
14866         struct intel_plane_state *old_plane_state, *new_plane_state;
14867         struct intel_plane *plane;
14868         int i;
14869
14870         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14871                                              new_plane_state, i)
14872                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
14873                                         to_intel_frontbuffer(new_plane_state->hw.fb),
14874                                         plane->frontbuffer_bit);
14875 }
14876
14877 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
14878 {
14879         struct intel_crtc *crtc;
14880
14881         for_each_intel_crtc(&dev_priv->drm, crtc)
14882                 drm_modeset_lock_assert_held(&crtc->base.mutex);
14883 }
14884
14885 static int intel_atomic_commit(struct drm_device *dev,
14886                                struct drm_atomic_state *_state,
14887                                bool nonblock)
14888 {
14889         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14890         struct drm_i915_private *dev_priv = to_i915(dev);
14891         int ret = 0;
14892
14893         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
14894
14895         drm_atomic_state_get(&state->base);
14896         i915_sw_fence_init(&state->commit_ready,
14897                            intel_atomic_commit_ready);
14898
14899         /*
14900          * The intel_legacy_cursor_update() fast path takes care
14901          * of avoiding the vblank waits for simple cursor
14902          * movement and flips. For cursor on/off and size changes,
14903          * we want to perform the vblank waits so that watermark
14904          * updates happen during the correct frames. Gen9+ have
14905          * double buffered watermarks and so shouldn't need this.
14906          *
14907          * Unset state->legacy_cursor_update before the call to
14908          * drm_atomic_helper_setup_commit() because otherwise
14909          * drm_atomic_helper_wait_for_flip_done() is a noop and
14910          * we get FIFO underruns because we didn't wait
14911          * for vblank.
14912          *
14913          * FIXME doing watermarks and fb cleanup from a vblank worker
14914          * (assuming we had any) would solve these problems.
14915          */
14916         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
14917                 struct intel_crtc_state *new_crtc_state;
14918                 struct intel_crtc *crtc;
14919                 int i;
14920
14921                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14922                         if (new_crtc_state->wm.need_postvbl_update ||
14923                             new_crtc_state->update_wm_post)
14924                                 state->base.legacy_cursor_update = false;
14925         }
14926
14927         ret = intel_atomic_prepare_commit(state);
14928         if (ret) {
14929                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14930                 i915_sw_fence_commit(&state->commit_ready);
14931                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14932                 return ret;
14933         }
14934
14935         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
14936         if (!ret)
14937                 ret = drm_atomic_helper_swap_state(&state->base, true);
14938
14939         if (ret) {
14940                 i915_sw_fence_commit(&state->commit_ready);
14941
14942                 drm_atomic_helper_cleanup_planes(dev, &state->base);
14943                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14944                 return ret;
14945         }
14946         dev_priv->wm.distrust_bios_wm = false;
14947         intel_shared_dpll_swap_state(state);
14948         intel_atomic_track_fbs(state);
14949
14950         if (state->global_state_changed) {
14951                 assert_global_state_locked(dev_priv);
14952
14953                 memcpy(dev_priv->min_cdclk, state->min_cdclk,
14954                        sizeof(state->min_cdclk));
14955                 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
14956                        sizeof(state->min_voltage_level));
14957                 dev_priv->active_pipes = state->active_pipes;
14958                 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
14959
14960                 intel_cdclk_swap_state(state);
14961         }
14962
14963         drm_atomic_state_get(&state->base);
14964         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
14965
14966         i915_sw_fence_commit(&state->commit_ready);
14967         if (nonblock && state->modeset) {
14968                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
14969         } else if (nonblock) {
14970                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
14971         } else {
14972                 if (state->modeset)
14973                         flush_workqueue(dev_priv->modeset_wq);
14974                 intel_atomic_commit_tail(state);
14975         }
14976
14977         return 0;
14978 }
14979
14980 struct wait_rps_boost {
14981         struct wait_queue_entry wait;
14982
14983         struct drm_crtc *crtc;
14984         struct i915_request *request;
14985 };
14986
14987 static int do_rps_boost(struct wait_queue_entry *_wait,
14988                         unsigned mode, int sync, void *key)
14989 {
14990         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
14991         struct i915_request *rq = wait->request;
14992
14993         /*
14994          * If we missed the vblank, but the request is already running it
14995          * is reasonable to assume that it will complete before the next
14996          * vblank without our intervention, so leave RPS alone.
14997          */
14998         if (!i915_request_started(rq))
14999                 intel_rps_boost(rq);
15000         i915_request_put(rq);
15001
15002         drm_crtc_vblank_put(wait->crtc);
15003
15004         list_del(&wait->wait.entry);
15005         kfree(wait);
15006         return 1;
15007 }
15008
15009 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15010                                        struct dma_fence *fence)
15011 {
15012         struct wait_rps_boost *wait;
15013
15014         if (!dma_fence_is_i915(fence))
15015                 return;
15016
15017         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15018                 return;
15019
15020         if (drm_crtc_vblank_get(crtc))
15021                 return;
15022
15023         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15024         if (!wait) {
15025                 drm_crtc_vblank_put(crtc);
15026                 return;
15027         }
15028
15029         wait->request = to_request(dma_fence_get(fence));
15030         wait->crtc = crtc;
15031
15032         wait->wait.func = do_rps_boost;
15033         wait->wait.flags = 0;
15034
15035         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15036 }
15037
15038 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15039 {
15040         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15041         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15042         struct drm_framebuffer *fb = plane_state->hw.fb;
15043         struct i915_vma *vma;
15044
15045         if (plane->id == PLANE_CURSOR &&
15046             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15047                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15048                 const int align = intel_cursor_alignment(dev_priv);
15049                 int err;
15050
15051                 err = i915_gem_object_attach_phys(obj, align);
15052                 if (err)
15053                         return err;
15054         }
15055
15056         vma = intel_pin_and_fence_fb_obj(fb,
15057                                          &plane_state->view,
15058                                          intel_plane_uses_fence(plane_state),
15059                                          &plane_state->flags);
15060         if (IS_ERR(vma))
15061                 return PTR_ERR(vma);
15062
15063         plane_state->vma = vma;
15064
15065         return 0;
15066 }
15067
15068 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15069 {
15070         struct i915_vma *vma;
15071
15072         vma = fetch_and_zero(&old_plane_state->vma);
15073         if (vma)
15074                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15075 }
15076
15077 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15078 {
15079         struct i915_sched_attr attr = {
15080                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15081         };
15082
15083         i915_gem_object_wait_priority(obj, 0, &attr);
15084 }
15085
15086 /**
15087  * intel_prepare_plane_fb - Prepare fb for usage on plane
15088  * @plane: drm plane to prepare for
15089  * @_new_plane_state: the plane state being prepared
15090  *
15091  * Prepares a framebuffer for usage on a display plane.  Generally this
15092  * involves pinning the underlying object and updating the frontbuffer tracking
15093  * bits.  Some older platforms need special physical address handling for
15094  * cursor planes.
15095  *
15096  * Returns 0 on success, negative error code on failure.
15097  */
15098 int
15099 intel_prepare_plane_fb(struct drm_plane *plane,
15100                        struct drm_plane_state *_new_plane_state)
15101 {
15102         struct intel_plane_state *new_plane_state =
15103                 to_intel_plane_state(_new_plane_state);
15104         struct intel_atomic_state *intel_state =
15105                 to_intel_atomic_state(new_plane_state->uapi.state);
15106         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15107         struct drm_framebuffer *fb = new_plane_state->hw.fb;
15108         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15109         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
15110         int ret;
15111
15112         if (old_obj) {
15113                 struct intel_crtc_state *crtc_state =
15114                         intel_atomic_get_new_crtc_state(intel_state,
15115                                                         to_intel_crtc(plane->state->crtc));
15116
15117                 /* Big Hammer, we also need to ensure that any pending
15118                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15119                  * current scanout is retired before unpinning the old
15120                  * framebuffer. Note that we rely on userspace rendering
15121                  * into the buffer attached to the pipe they are waiting
15122                  * on. If not, userspace generates a GPU hang with IPEHR
15123                  * point to the MI_WAIT_FOR_EVENT.
15124                  *
15125                  * This should only fail upon a hung GPU, in which case we
15126                  * can safely continue.
15127                  */
15128                 if (needs_modeset(crtc_state)) {
15129                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15130                                                               old_obj->base.resv, NULL,
15131                                                               false, 0,
15132                                                               GFP_KERNEL);
15133                         if (ret < 0)
15134                                 return ret;
15135                 }
15136         }
15137
15138         if (new_plane_state->uapi.fence) { /* explicit fencing */
15139                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
15140                                                     new_plane_state->uapi.fence,
15141                                                     I915_FENCE_TIMEOUT,
15142                                                     GFP_KERNEL);
15143                 if (ret < 0)
15144                         return ret;
15145         }
15146
15147         if (!obj)
15148                 return 0;
15149
15150         ret = i915_gem_object_pin_pages(obj);
15151         if (ret)
15152                 return ret;
15153
15154         ret = intel_plane_pin_fb(new_plane_state);
15155
15156         i915_gem_object_unpin_pages(obj);
15157         if (ret)
15158                 return ret;
15159
15160         fb_obj_bump_render_priority(obj);
15161         intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
15162
15163         if (!new_plane_state->uapi.fence) { /* implicit fencing */
15164                 struct dma_fence *fence;
15165
15166                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15167                                                       obj->base.resv, NULL,
15168                                                       false, I915_FENCE_TIMEOUT,
15169                                                       GFP_KERNEL);
15170                 if (ret < 0)
15171                         return ret;
15172
15173                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15174                 if (fence) {
15175                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15176                                                    fence);
15177                         dma_fence_put(fence);
15178                 }
15179         } else {
15180                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15181                                            new_plane_state->uapi.fence);
15182         }
15183
15184         /*
15185          * We declare pageflips to be interactive and so merit a small bias
15186          * towards upclocking to deliver the frame on time. By only changing
15187          * the RPS thresholds to sample more regularly and aim for higher
15188          * clocks we can hopefully deliver low power workloads (like kodi)
15189          * that are not quite steady state without resorting to forcing
15190          * maximum clocks following a vblank miss (see do_rps_boost()).
15191          */
15192         if (!intel_state->rps_interactive) {
15193                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15194                 intel_state->rps_interactive = true;
15195         }
15196
15197         return 0;
15198 }
15199
15200 /**
15201  * intel_cleanup_plane_fb - Cleans up an fb after plane use
15202  * @plane: drm plane to clean up for
15203  * @_old_plane_state: the state from the previous modeset
15204  *
15205  * Cleans up a framebuffer that has just been removed from a plane.
15206  */
15207 void
15208 intel_cleanup_plane_fb(struct drm_plane *plane,
15209                        struct drm_plane_state *_old_plane_state)
15210 {
15211         struct intel_plane_state *old_plane_state =
15212                 to_intel_plane_state(_old_plane_state);
15213         struct intel_atomic_state *intel_state =
15214                 to_intel_atomic_state(old_plane_state->uapi.state);
15215         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15216
15217         if (intel_state->rps_interactive) {
15218                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15219                 intel_state->rps_interactive = false;
15220         }
15221
15222         /* Should only be called after a successful intel_prepare_plane_fb()! */
15223         intel_plane_unpin_fb(old_plane_state);
15224 }
15225
15226 /**
15227  * intel_plane_destroy - destroy a plane
15228  * @plane: plane to destroy
15229  *
15230  * Common destruction function for all types of planes (primary, cursor,
15231  * sprite).
15232  */
15233 void intel_plane_destroy(struct drm_plane *plane)
15234 {
15235         drm_plane_cleanup(plane);
15236         kfree(to_intel_plane(plane));
15237 }
15238
15239 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15240                                             u32 format, u64 modifier)
15241 {
15242         switch (modifier) {
15243         case DRM_FORMAT_MOD_LINEAR:
15244         case I915_FORMAT_MOD_X_TILED:
15245                 break;
15246         default:
15247                 return false;
15248         }
15249
15250         switch (format) {
15251         case DRM_FORMAT_C8:
15252         case DRM_FORMAT_RGB565:
15253         case DRM_FORMAT_XRGB1555:
15254         case DRM_FORMAT_XRGB8888:
15255                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15256                         modifier == I915_FORMAT_MOD_X_TILED;
15257         default:
15258                 return false;
15259         }
15260 }
15261
15262 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15263                                             u32 format, u64 modifier)
15264 {
15265         switch (modifier) {
15266         case DRM_FORMAT_MOD_LINEAR:
15267         case I915_FORMAT_MOD_X_TILED:
15268                 break;
15269         default:
15270                 return false;
15271         }
15272
15273         switch (format) {
15274         case DRM_FORMAT_C8:
15275         case DRM_FORMAT_RGB565:
15276         case DRM_FORMAT_XRGB8888:
15277         case DRM_FORMAT_XBGR8888:
15278         case DRM_FORMAT_XRGB2101010:
15279         case DRM_FORMAT_XBGR2101010:
15280         case DRM_FORMAT_XBGR16161616F:
15281                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15282                         modifier == I915_FORMAT_MOD_X_TILED;
15283         default:
15284                 return false;
15285         }
15286 }
15287
15288 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15289                                               u32 format, u64 modifier)
15290 {
15291         return modifier == DRM_FORMAT_MOD_LINEAR &&
15292                 format == DRM_FORMAT_ARGB8888;
15293 }
15294
15295 static const struct drm_plane_funcs i965_plane_funcs = {
15296         .update_plane = drm_atomic_helper_update_plane,
15297         .disable_plane = drm_atomic_helper_disable_plane,
15298         .destroy = intel_plane_destroy,
15299         .atomic_duplicate_state = intel_plane_duplicate_state,
15300         .atomic_destroy_state = intel_plane_destroy_state,
15301         .format_mod_supported = i965_plane_format_mod_supported,
15302 };
15303
15304 static const struct drm_plane_funcs i8xx_plane_funcs = {
15305         .update_plane = drm_atomic_helper_update_plane,
15306         .disable_plane = drm_atomic_helper_disable_plane,
15307         .destroy = intel_plane_destroy,
15308         .atomic_duplicate_state = intel_plane_duplicate_state,
15309         .atomic_destroy_state = intel_plane_destroy_state,
15310         .format_mod_supported = i8xx_plane_format_mod_supported,
15311 };
15312
15313 static int
15314 intel_legacy_cursor_update(struct drm_plane *_plane,
15315                            struct drm_crtc *_crtc,
15316                            struct drm_framebuffer *fb,
15317                            int crtc_x, int crtc_y,
15318                            unsigned int crtc_w, unsigned int crtc_h,
15319                            u32 src_x, u32 src_y,
15320                            u32 src_w, u32 src_h,
15321                            struct drm_modeset_acquire_ctx *ctx)
15322 {
15323         struct intel_plane *plane = to_intel_plane(_plane);
15324         struct intel_crtc *crtc = to_intel_crtc(_crtc);
15325         struct intel_plane_state *old_plane_state =
15326                 to_intel_plane_state(plane->base.state);
15327         struct intel_plane_state *new_plane_state;
15328         struct intel_crtc_state *crtc_state =
15329                 to_intel_crtc_state(crtc->base.state);
15330         struct intel_crtc_state *new_crtc_state;
15331         int ret;
15332
15333         /*
15334          * When crtc is inactive or there is a modeset pending,
15335          * wait for it to complete in the slowpath
15336          */
15337         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
15338             crtc_state->update_pipe)
15339                 goto slow;
15340
15341         /*
15342          * Don't do an async update if there is an outstanding commit modifying
15343          * the plane.  This prevents our async update's changes from getting
15344          * overridden by a previous synchronous update's state.
15345          */
15346         if (old_plane_state->uapi.commit &&
15347             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
15348                 goto slow;
15349
15350         /*
15351          * If any parameters change that may affect watermarks,
15352          * take the slowpath. Only changing fb or position should be
15353          * in the fastpath.
15354          */
15355         if (old_plane_state->uapi.crtc != &crtc->base ||
15356             old_plane_state->uapi.src_w != src_w ||
15357             old_plane_state->uapi.src_h != src_h ||
15358             old_plane_state->uapi.crtc_w != crtc_w ||
15359             old_plane_state->uapi.crtc_h != crtc_h ||
15360             !old_plane_state->uapi.fb != !fb)
15361                 goto slow;
15362
15363         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
15364         if (!new_plane_state)
15365                 return -ENOMEM;
15366
15367         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
15368         if (!new_crtc_state) {
15369                 ret = -ENOMEM;
15370                 goto out_free;
15371         }
15372
15373         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
15374
15375         new_plane_state->uapi.src_x = src_x;
15376         new_plane_state->uapi.src_y = src_y;
15377         new_plane_state->uapi.src_w = src_w;
15378         new_plane_state->uapi.src_h = src_h;
15379         new_plane_state->uapi.crtc_x = crtc_x;
15380         new_plane_state->uapi.crtc_y = crtc_y;
15381         new_plane_state->uapi.crtc_w = crtc_w;
15382         new_plane_state->uapi.crtc_h = crtc_h;
15383
15384         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
15385                                                   old_plane_state, new_plane_state);
15386         if (ret)
15387                 goto out_free;
15388
15389         ret = intel_plane_pin_fb(new_plane_state);
15390         if (ret)
15391                 goto out_free;
15392
15393         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
15394                                 ORIGIN_FLIP);
15395         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15396                                 to_intel_frontbuffer(new_plane_state->hw.fb),
15397                                 plane->frontbuffer_bit);
15398
15399         /* Swap plane state */
15400         plane->base.state = &new_plane_state->uapi;
15401
15402         /*
15403          * We cannot swap crtc_state as it may be in use by an atomic commit or
15404          * page flip that's running simultaneously. If we swap crtc_state and
15405          * destroy the old state, we will cause a use-after-free there.
15406          *
15407          * Only update active_planes, which is needed for our internal
15408          * bookkeeping. Either value will do the right thing when updating
15409          * planes atomically. If the cursor was part of the atomic update then
15410          * we would have taken the slowpath.
15411          */
15412         crtc_state->active_planes = new_crtc_state->active_planes;
15413
15414         if (new_plane_state->uapi.visible)
15415                 intel_update_plane(plane, crtc_state, new_plane_state);
15416         else
15417                 intel_disable_plane(plane, crtc_state);
15418
15419         intel_plane_unpin_fb(old_plane_state);
15420
15421 out_free:
15422         if (new_crtc_state)
15423                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
15424         if (ret)
15425                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
15426         else
15427                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
15428         return ret;
15429
15430 slow:
15431         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
15432                                               crtc_x, crtc_y, crtc_w, crtc_h,
15433                                               src_x, src_y, src_w, src_h, ctx);
15434 }
15435
15436 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15437         .update_plane = intel_legacy_cursor_update,
15438         .disable_plane = drm_atomic_helper_disable_plane,
15439         .destroy = intel_plane_destroy,
15440         .atomic_duplicate_state = intel_plane_duplicate_state,
15441         .atomic_destroy_state = intel_plane_destroy_state,
15442         .format_mod_supported = intel_cursor_format_mod_supported,
15443 };
15444
15445 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
15446                                enum i9xx_plane_id i9xx_plane)
15447 {
15448         if (!HAS_FBC(dev_priv))
15449                 return false;
15450
15451         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15452                 return i9xx_plane == PLANE_A; /* tied to pipe A */
15453         else if (IS_IVYBRIDGE(dev_priv))
15454                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
15455                         i9xx_plane == PLANE_C;
15456         else if (INTEL_GEN(dev_priv) >= 4)
15457                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
15458         else
15459                 return i9xx_plane == PLANE_A;
15460 }
15461
15462 static struct intel_plane *
15463 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15464 {
15465         struct intel_plane *plane;
15466         const struct drm_plane_funcs *plane_funcs;
15467         unsigned int supported_rotations;
15468         unsigned int possible_crtcs;
15469         const u64 *modifiers;
15470         const u32 *formats;
15471         int num_formats;
15472         int ret, zpos;
15473
15474         if (INTEL_GEN(dev_priv) >= 9)
15475                 return skl_universal_plane_create(dev_priv, pipe,
15476                                                   PLANE_PRIMARY);
15477
15478         plane = intel_plane_alloc();
15479         if (IS_ERR(plane))
15480                 return plane;
15481
15482         plane->pipe = pipe;
15483         /*
15484          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15485          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15486          */
15487         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15488                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
15489         else
15490                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
15491         plane->id = PLANE_PRIMARY;
15492         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
15493
15494         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
15495         if (plane->has_fbc) {
15496                 struct intel_fbc *fbc = &dev_priv->fbc;
15497
15498                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
15499         }
15500
15501         if (INTEL_GEN(dev_priv) >= 4) {
15502                 /*
15503                  * WaFP16GammaEnabling:ivb
15504                  * "Workaround : When using the 64-bit format, the plane
15505                  *  output on each color channel has one quarter amplitude.
15506                  *  It can be brought up to full amplitude by using pipe
15507                  *  gamma correction or pipe color space conversion to
15508                  *  multiply the plane output by four."
15509                  *
15510                  * There is no dedicated plane gamma for the primary plane,
15511                  * and using the pipe gamma/csc could conflict with other
15512                  * planes, so we choose not to expose fp16 on IVB primary
15513                  * planes. HSW primary planes no longer have this problem.
15514                  */
15515                 if (IS_IVYBRIDGE(dev_priv)) {
15516                         formats = ivb_primary_formats;
15517                         num_formats = ARRAY_SIZE(ivb_primary_formats);
15518                 } else {
15519                         formats = i965_primary_formats;
15520                         num_formats = ARRAY_SIZE(i965_primary_formats);
15521                 }
15522                 modifiers = i9xx_format_modifiers;
15523
15524                 plane->max_stride = i9xx_plane_max_stride;
15525                 plane->update_plane = i9xx_update_plane;
15526                 plane->disable_plane = i9xx_disable_plane;
15527                 plane->get_hw_state = i9xx_plane_get_hw_state;
15528                 plane->check_plane = i9xx_plane_check;
15529
15530                 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15531                         plane->min_cdclk = hsw_plane_min_cdclk;
15532                 else if (IS_IVYBRIDGE(dev_priv))
15533                         plane->min_cdclk = ivb_plane_min_cdclk;
15534                 else if (IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv))
15535                         plane->min_cdclk = vlv_plane_min_cdclk;
15536                 else
15537                         plane->min_cdclk = i9xx_plane_min_cdclk;
15538
15539                 plane_funcs = &i965_plane_funcs;
15540         } else {
15541                 formats = i8xx_primary_formats;
15542                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15543                 modifiers = i9xx_format_modifiers;
15544
15545                 plane->max_stride = i9xx_plane_max_stride;
15546                 plane->update_plane = i9xx_update_plane;
15547                 plane->disable_plane = i9xx_disable_plane;
15548                 plane->get_hw_state = i9xx_plane_get_hw_state;
15549                 plane->check_plane = i9xx_plane_check;
15550                 plane->min_cdclk = i9xx_plane_min_cdclk;
15551
15552                 plane_funcs = &i8xx_plane_funcs;
15553         }
15554
15555         possible_crtcs = BIT(pipe);
15556
15557         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15558                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15559                                                possible_crtcs, plane_funcs,
15560                                                formats, num_formats, modifiers,
15561                                                DRM_PLANE_TYPE_PRIMARY,
15562                                                "primary %c", pipe_name(pipe));
15563         else
15564                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15565                                                possible_crtcs, plane_funcs,
15566                                                formats, num_formats, modifiers,
15567                                                DRM_PLANE_TYPE_PRIMARY,
15568                                                "plane %c",
15569                                                plane_name(plane->i9xx_plane));
15570         if (ret)
15571                 goto fail;
15572
15573         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15574                 supported_rotations =
15575                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
15576                         DRM_MODE_REFLECT_X;
15577         } else if (INTEL_GEN(dev_priv) >= 4) {
15578                 supported_rotations =
15579                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
15580         } else {
15581                 supported_rotations = DRM_MODE_ROTATE_0;
15582         }
15583
15584         if (INTEL_GEN(dev_priv) >= 4)
15585                 drm_plane_create_rotation_property(&plane->base,
15586                                                    DRM_MODE_ROTATE_0,
15587                                                    supported_rotations);
15588
15589         zpos = 0;
15590         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
15591
15592         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
15593
15594         return plane;
15595
15596 fail:
15597         intel_plane_free(plane);
15598
15599         return ERR_PTR(ret);
15600 }
15601
15602 static struct intel_plane *
15603 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
15604                           enum pipe pipe)
15605 {
15606         unsigned int possible_crtcs;
15607         struct intel_plane *cursor;
15608         int ret, zpos;
15609
15610         cursor = intel_plane_alloc();
15611         if (IS_ERR(cursor))
15612                 return cursor;
15613
15614         cursor->pipe = pipe;
15615         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15616         cursor->id = PLANE_CURSOR;
15617         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15618
15619         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15620                 cursor->max_stride = i845_cursor_max_stride;
15621                 cursor->update_plane = i845_update_cursor;
15622                 cursor->disable_plane = i845_disable_cursor;
15623                 cursor->get_hw_state = i845_cursor_get_hw_state;
15624                 cursor->check_plane = i845_check_cursor;
15625         } else {
15626                 cursor->max_stride = i9xx_cursor_max_stride;
15627                 cursor->update_plane = i9xx_update_cursor;
15628                 cursor->disable_plane = i9xx_disable_cursor;
15629                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15630                 cursor->check_plane = i9xx_check_cursor;
15631         }
15632
15633         cursor->cursor.base = ~0;
15634         cursor->cursor.cntl = ~0;
15635
15636         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15637                 cursor->cursor.size = ~0;
15638
15639         possible_crtcs = BIT(pipe);
15640
15641         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15642                                        possible_crtcs, &intel_cursor_plane_funcs,
15643                                        intel_cursor_formats,
15644                                        ARRAY_SIZE(intel_cursor_formats),
15645                                        cursor_format_modifiers,
15646                                        DRM_PLANE_TYPE_CURSOR,
15647                                        "cursor %c", pipe_name(pipe));
15648         if (ret)
15649                 goto fail;
15650
15651         if (INTEL_GEN(dev_priv) >= 4)
15652                 drm_plane_create_rotation_property(&cursor->base,
15653                                                    DRM_MODE_ROTATE_0,
15654                                                    DRM_MODE_ROTATE_0 |
15655                                                    DRM_MODE_ROTATE_180);
15656
15657         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15658         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15659
15660         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15661
15662         return cursor;
15663
15664 fail:
15665         intel_plane_free(cursor);
15666
15667         return ERR_PTR(ret);
15668 }
15669
15670 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15671                                     struct intel_crtc_state *crtc_state)
15672 {
15673         struct intel_crtc_scaler_state *scaler_state =
15674                 &crtc_state->scaler_state;
15675         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15676         int i;
15677
15678         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
15679         if (!crtc->num_scalers)
15680                 return;
15681
15682         for (i = 0; i < crtc->num_scalers; i++) {
15683                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15684
15685                 scaler->in_use = 0;
15686                 scaler->mode = 0;
15687         }
15688
15689         scaler_state->scaler_id = -1;
15690 }
15691
15692 #define INTEL_CRTC_FUNCS \
15693         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15694         .set_config = drm_atomic_helper_set_config, \
15695         .destroy = intel_crtc_destroy, \
15696         .page_flip = drm_atomic_helper_page_flip, \
15697         .atomic_duplicate_state = intel_crtc_duplicate_state, \
15698         .atomic_destroy_state = intel_crtc_destroy_state, \
15699         .set_crc_source = intel_crtc_set_crc_source, \
15700         .verify_crc_source = intel_crtc_verify_crc_source, \
15701         .get_crc_sources = intel_crtc_get_crc_sources
15702
15703 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15704         INTEL_CRTC_FUNCS,
15705
15706         .get_vblank_counter = g4x_get_vblank_counter,
15707         .enable_vblank = bdw_enable_vblank,
15708         .disable_vblank = bdw_disable_vblank,
15709 };
15710
15711 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15712         INTEL_CRTC_FUNCS,
15713
15714         .get_vblank_counter = g4x_get_vblank_counter,
15715         .enable_vblank = ilk_enable_vblank,
15716         .disable_vblank = ilk_disable_vblank,
15717 };
15718
15719 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15720         INTEL_CRTC_FUNCS,
15721
15722         .get_vblank_counter = g4x_get_vblank_counter,
15723         .enable_vblank = i965_enable_vblank,
15724         .disable_vblank = i965_disable_vblank,
15725 };
15726
15727 static const struct drm_crtc_funcs i965_crtc_funcs = {
15728         INTEL_CRTC_FUNCS,
15729
15730         .get_vblank_counter = i915_get_vblank_counter,
15731         .enable_vblank = i965_enable_vblank,
15732         .disable_vblank = i965_disable_vblank,
15733 };
15734
15735 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
15736         INTEL_CRTC_FUNCS,
15737
15738         .get_vblank_counter = i915_get_vblank_counter,
15739         .enable_vblank = i915gm_enable_vblank,
15740         .disable_vblank = i915gm_disable_vblank,
15741 };
15742
15743 static const struct drm_crtc_funcs i915_crtc_funcs = {
15744         INTEL_CRTC_FUNCS,
15745
15746         .get_vblank_counter = i915_get_vblank_counter,
15747         .enable_vblank = i8xx_enable_vblank,
15748         .disable_vblank = i8xx_disable_vblank,
15749 };
15750
15751 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15752         INTEL_CRTC_FUNCS,
15753
15754         /* no hw vblank counter */
15755         .enable_vblank = i8xx_enable_vblank,
15756         .disable_vblank = i8xx_disable_vblank,
15757 };
15758
15759 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15760 {
15761         const struct drm_crtc_funcs *funcs;
15762         struct intel_crtc *intel_crtc;
15763         struct intel_crtc_state *crtc_state = NULL;
15764         struct intel_plane *primary = NULL;
15765         struct intel_plane *cursor = NULL;
15766         int sprite, ret;
15767
15768         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15769         if (!intel_crtc)
15770                 return -ENOMEM;
15771
15772         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15773         if (!crtc_state) {
15774                 ret = -ENOMEM;
15775                 goto fail;
15776         }
15777         __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
15778         intel_crtc->config = crtc_state;
15779
15780         primary = intel_primary_plane_create(dev_priv, pipe);
15781         if (IS_ERR(primary)) {
15782                 ret = PTR_ERR(primary);
15783                 goto fail;
15784         }
15785         intel_crtc->plane_ids_mask |= BIT(primary->id);
15786
15787         for_each_sprite(dev_priv, pipe, sprite) {
15788                 struct intel_plane *plane;
15789
15790                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15791                 if (IS_ERR(plane)) {
15792                         ret = PTR_ERR(plane);
15793                         goto fail;
15794                 }
15795                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15796         }
15797
15798         cursor = intel_cursor_plane_create(dev_priv, pipe);
15799         if (IS_ERR(cursor)) {
15800                 ret = PTR_ERR(cursor);
15801                 goto fail;
15802         }
15803         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15804
15805         if (HAS_GMCH(dev_priv)) {
15806                 if (IS_CHERRYVIEW(dev_priv) ||
15807                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15808                         funcs = &g4x_crtc_funcs;
15809                 else if (IS_GEN(dev_priv, 4))
15810                         funcs = &i965_crtc_funcs;
15811                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
15812                         funcs = &i915gm_crtc_funcs;
15813                 else if (IS_GEN(dev_priv, 3))
15814                         funcs = &i915_crtc_funcs;
15815                 else
15816                         funcs = &i8xx_crtc_funcs;
15817         } else {
15818                 if (INTEL_GEN(dev_priv) >= 8)
15819                         funcs = &bdw_crtc_funcs;
15820                 else
15821                         funcs = &ilk_crtc_funcs;
15822         }
15823
15824         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15825                                         &primary->base, &cursor->base,
15826                                         funcs, "pipe %c", pipe_name(pipe));
15827         if (ret)
15828                 goto fail;
15829
15830         intel_crtc->pipe = pipe;
15831
15832         /* initialize shared scalers */
15833         intel_crtc_init_scalers(intel_crtc, crtc_state);
15834
15835         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15836                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15837         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
15838
15839         if (INTEL_GEN(dev_priv) < 9) {
15840                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15841
15842                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15843                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15844                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
15845         }
15846
15847         intel_color_init(intel_crtc);
15848
15849         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15850
15851         return 0;
15852
15853 fail:
15854         /*
15855          * drm_mode_config_cleanup() will free up any
15856          * crtcs/planes already initialized.
15857          */
15858         kfree(crtc_state);
15859         kfree(intel_crtc);
15860
15861         return ret;
15862 }
15863
15864 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15865                                       struct drm_file *file)
15866 {
15867         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15868         struct drm_crtc *drmmode_crtc;
15869         struct intel_crtc *crtc;
15870
15871         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15872         if (!drmmode_crtc)
15873                 return -ENOENT;
15874
15875         crtc = to_intel_crtc(drmmode_crtc);
15876         pipe_from_crtc_id->pipe = crtc->pipe;
15877
15878         return 0;
15879 }
15880
15881 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
15882 {
15883         struct drm_device *dev = encoder->base.dev;
15884         struct intel_encoder *source_encoder;
15885         u32 possible_clones = 0;
15886
15887         for_each_intel_encoder(dev, source_encoder) {
15888                 if (encoders_cloneable(encoder, source_encoder))
15889                         possible_clones |= drm_encoder_mask(&source_encoder->base);
15890         }
15891
15892         return possible_clones;
15893 }
15894
15895 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
15896 {
15897         struct drm_device *dev = encoder->base.dev;
15898         struct intel_crtc *crtc;
15899         u32 possible_crtcs = 0;
15900
15901         for_each_intel_crtc(dev, crtc) {
15902                 if (encoder->pipe_mask & BIT(crtc->pipe))
15903                         possible_crtcs |= drm_crtc_mask(&crtc->base);
15904         }
15905
15906         return possible_crtcs;
15907 }
15908
15909 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
15910 {
15911         if (!IS_MOBILE(dev_priv))
15912                 return false;
15913
15914         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15915                 return false;
15916
15917         if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15918                 return false;
15919
15920         return true;
15921 }
15922
15923 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
15924 {
15925         if (INTEL_GEN(dev_priv) >= 9)
15926                 return false;
15927
15928         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15929                 return false;
15930
15931         if (HAS_PCH_LPT_H(dev_priv) &&
15932             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15933                 return false;
15934
15935         /* DDI E can't be used if DDI A requires 4 lanes */
15936         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15937                 return false;
15938
15939         if (!dev_priv->vbt.int_crt_support)
15940                 return false;
15941
15942         return true;
15943 }
15944
15945 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15946 {
15947         int pps_num;
15948         int pps_idx;
15949
15950         if (HAS_DDI(dev_priv))
15951                 return;
15952         /*
15953          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15954          * everywhere where registers can be write protected.
15955          */
15956         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15957                 pps_num = 2;
15958         else
15959                 pps_num = 1;
15960
15961         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15962                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15963
15964                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15965                 I915_WRITE(PP_CONTROL(pps_idx), val);
15966         }
15967 }
15968
15969 static void intel_pps_init(struct drm_i915_private *dev_priv)
15970 {
15971         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15972                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15973         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15974                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15975         else
15976                 dev_priv->pps_mmio_base = PPS_BASE;
15977
15978         intel_pps_unlock_regs_wa(dev_priv);
15979 }
15980
15981 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
15982 {
15983         struct intel_encoder *encoder;
15984         bool dpd_is_edp = false;
15985
15986         intel_pps_init(dev_priv);
15987
15988         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
15989                 return;
15990
15991         if (INTEL_GEN(dev_priv) >= 12) {
15992                 intel_ddi_init(dev_priv, PORT_A);
15993                 intel_ddi_init(dev_priv, PORT_B);
15994                 intel_ddi_init(dev_priv, PORT_D);
15995                 intel_ddi_init(dev_priv, PORT_E);
15996                 intel_ddi_init(dev_priv, PORT_F);
15997                 intel_ddi_init(dev_priv, PORT_G);
15998                 intel_ddi_init(dev_priv, PORT_H);
15999                 intel_ddi_init(dev_priv, PORT_I);
16000                 icl_dsi_init(dev_priv);
16001         } else if (IS_ELKHARTLAKE(dev_priv)) {
16002                 intel_ddi_init(dev_priv, PORT_A);
16003                 intel_ddi_init(dev_priv, PORT_B);
16004                 intel_ddi_init(dev_priv, PORT_C);
16005                 intel_ddi_init(dev_priv, PORT_D);
16006                 icl_dsi_init(dev_priv);
16007         } else if (IS_GEN(dev_priv, 11)) {
16008                 intel_ddi_init(dev_priv, PORT_A);
16009                 intel_ddi_init(dev_priv, PORT_B);
16010                 intel_ddi_init(dev_priv, PORT_C);
16011                 intel_ddi_init(dev_priv, PORT_D);
16012                 intel_ddi_init(dev_priv, PORT_E);
16013                 /*
16014                  * On some ICL SKUs port F is not present. No strap bits for
16015                  * this, so rely on VBT.
16016                  * Work around broken VBTs on SKUs known to have no port F.
16017                  */
16018                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16019                     intel_bios_is_port_present(dev_priv, PORT_F))
16020                         intel_ddi_init(dev_priv, PORT_F);
16021
16022                 icl_dsi_init(dev_priv);
16023         } else if (IS_GEN9_LP(dev_priv)) {
16024                 /*
16025                  * FIXME: Broxton doesn't support port detection via the
16026                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16027                  * detect the ports.
16028                  */
16029                 intel_ddi_init(dev_priv, PORT_A);
16030                 intel_ddi_init(dev_priv, PORT_B);
16031                 intel_ddi_init(dev_priv, PORT_C);
16032
16033                 vlv_dsi_init(dev_priv);
16034         } else if (HAS_DDI(dev_priv)) {
16035                 int found;
16036
16037                 if (intel_ddi_crt_present(dev_priv))
16038                         intel_crt_init(dev_priv);
16039
16040                 /*
16041                  * Haswell uses DDI functions to detect digital outputs.
16042                  * On SKL pre-D0 the strap isn't connected, so we assume
16043                  * it's there.
16044                  */
16045                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16046                 /* WaIgnoreDDIAStrap: skl */
16047                 if (found || IS_GEN9_BC(dev_priv))
16048                         intel_ddi_init(dev_priv, PORT_A);
16049
16050                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16051                  * register */
16052                 found = I915_READ(SFUSE_STRAP);
16053
16054                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16055                         intel_ddi_init(dev_priv, PORT_B);
16056                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16057                         intel_ddi_init(dev_priv, PORT_C);
16058                 if (found & SFUSE_STRAP_DDID_DETECTED)
16059                         intel_ddi_init(dev_priv, PORT_D);
16060                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16061                         intel_ddi_init(dev_priv, PORT_F);
16062                 /*
16063                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16064                  */
16065                 if (IS_GEN9_BC(dev_priv) &&
16066                     intel_bios_is_port_present(dev_priv, PORT_E))
16067                         intel_ddi_init(dev_priv, PORT_E);
16068
16069         } else if (HAS_PCH_SPLIT(dev_priv)) {
16070                 int found;
16071
16072                 /*
16073                  * intel_edp_init_connector() depends on this completing first,
16074                  * to prevent the registration of both eDP and LVDS and the
16075                  * incorrect sharing of the PPS.
16076                  */
16077                 intel_lvds_init(dev_priv);
16078                 intel_crt_init(dev_priv);
16079
16080                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16081
16082                 if (ilk_has_edp_a(dev_priv))
16083                         intel_dp_init(dev_priv, DP_A, PORT_A);
16084
16085                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
16086                         /* PCH SDVOB multiplex with HDMIB */
16087                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16088                         if (!found)
16089                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16090                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
16091                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16092                 }
16093
16094                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
16095                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16096
16097                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
16098                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16099
16100                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
16101                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16102
16103                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
16104                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16105         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16106                 bool has_edp, has_port;
16107
16108                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16109                         intel_crt_init(dev_priv);
16110
16111                 /*
16112                  * The DP_DETECTED bit is the latched state of the DDC
16113                  * SDA pin at boot. However since eDP doesn't require DDC
16114                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16115                  * eDP ports may have been muxed to an alternate function.
16116                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16117                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16118                  * detect eDP ports.
16119                  *
16120                  * Sadly the straps seem to be missing sometimes even for HDMI
16121                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16122                  * and VBT for the presence of the port. Additionally we can't
16123                  * trust the port type the VBT declares as we've seen at least
16124                  * HDMI ports that the VBT claim are DP or eDP.
16125                  */
16126                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16127                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16128                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
16129                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16130                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16131                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16132
16133                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16134                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16135                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
16136                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16137                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16138                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16139
16140                 if (IS_CHERRYVIEW(dev_priv)) {
16141                         /*
16142                          * eDP not supported on port D,
16143                          * so no need to worry about it
16144                          */
16145                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16146                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
16147                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16148                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
16149                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16150                 }
16151
16152                 vlv_dsi_init(dev_priv);
16153         } else if (IS_PINEVIEW(dev_priv)) {
16154                 intel_lvds_init(dev_priv);
16155                 intel_crt_init(dev_priv);
16156         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16157                 bool found = false;
16158
16159                 if (IS_MOBILE(dev_priv))
16160                         intel_lvds_init(dev_priv);
16161
16162                 intel_crt_init(dev_priv);
16163
16164                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16165                         DRM_DEBUG_KMS("probing SDVOB\n");
16166                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16167                         if (!found && IS_G4X(dev_priv)) {
16168                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
16169                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16170                         }
16171
16172                         if (!found && IS_G4X(dev_priv))
16173                                 intel_dp_init(dev_priv, DP_B, PORT_B);
16174                 }
16175
16176                 /* Before G4X SDVOC doesn't have its own detect register */
16177
16178                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16179                         DRM_DEBUG_KMS("probing SDVOC\n");
16180                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16181                 }
16182
16183                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
16184
16185                         if (IS_G4X(dev_priv)) {
16186                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
16187                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16188                         }
16189                         if (IS_G4X(dev_priv))
16190                                 intel_dp_init(dev_priv, DP_C, PORT_C);
16191                 }
16192
16193                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
16194                         intel_dp_init(dev_priv, DP_D, PORT_D);
16195
16196                 if (SUPPORTS_TV(dev_priv))
16197                         intel_tv_init(dev_priv);
16198         } else if (IS_GEN(dev_priv, 2)) {
16199                 if (IS_I85X(dev_priv))
16200                         intel_lvds_init(dev_priv);
16201
16202                 intel_crt_init(dev_priv);
16203                 intel_dvo_init(dev_priv);
16204         }
16205
16206         intel_psr_init(dev_priv);
16207
16208         for_each_intel_encoder(&dev_priv->drm, encoder) {
16209                 encoder->base.possible_crtcs =
16210                         intel_encoder_possible_crtcs(encoder);
16211                 encoder->base.possible_clones =
16212                         intel_encoder_possible_clones(encoder);
16213         }
16214
16215         intel_init_pch_refclk(dev_priv);
16216
16217         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16218 }
16219
16220 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16221 {
16222         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16223
16224         drm_framebuffer_cleanup(fb);
16225         intel_frontbuffer_put(intel_fb->frontbuffer);
16226
16227         kfree(intel_fb);
16228 }
16229
16230 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16231                                                 struct drm_file *file,
16232                                                 unsigned int *handle)
16233 {
16234         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16235
16236         if (obj->userptr.mm) {
16237                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
16238                 return -EINVAL;
16239         }
16240
16241         return drm_gem_handle_create(file, &obj->base, handle);
16242 }
16243
16244 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16245                                         struct drm_file *file,
16246                                         unsigned flags, unsigned color,
16247                                         struct drm_clip_rect *clips,
16248                                         unsigned num_clips)
16249 {
16250         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16251
16252         i915_gem_object_flush_if_display(obj);
16253         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16254
16255         return 0;
16256 }
16257
16258 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16259         .destroy = intel_user_framebuffer_destroy,
16260         .create_handle = intel_user_framebuffer_create_handle,
16261         .dirty = intel_user_framebuffer_dirty,
16262 };
16263
16264 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16265                                   struct drm_i915_gem_object *obj,
16266                                   struct drm_mode_fb_cmd2 *mode_cmd)
16267 {
16268         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16269         struct drm_framebuffer *fb = &intel_fb->base;
16270         u32 max_stride;
16271         unsigned int tiling, stride;
16272         int ret = -EINVAL;
16273         int i;
16274
16275         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16276         if (!intel_fb->frontbuffer)
16277                 return -ENOMEM;
16278
16279         i915_gem_object_lock(obj);
16280         tiling = i915_gem_object_get_tiling(obj);
16281         stride = i915_gem_object_get_stride(obj);
16282         i915_gem_object_unlock(obj);
16283
16284         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16285                 /*
16286                  * If there's a fence, enforce that
16287                  * the fb modifier and tiling mode match.
16288                  */
16289                 if (tiling != I915_TILING_NONE &&
16290                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16291                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
16292                         goto err;
16293                 }
16294         } else {
16295                 if (tiling == I915_TILING_X) {
16296                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16297                 } else if (tiling == I915_TILING_Y) {
16298                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
16299                         goto err;
16300                 }
16301         }
16302
16303         if (!drm_any_plane_has_format(&dev_priv->drm,
16304                                       mode_cmd->pixel_format,
16305                                       mode_cmd->modifier[0])) {
16306                 struct drm_format_name_buf format_name;
16307
16308                 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
16309                               drm_get_format_name(mode_cmd->pixel_format,
16310                                                   &format_name),
16311                               mode_cmd->modifier[0]);
16312                 goto err;
16313         }
16314
16315         /*
16316          * gen2/3 display engine uses the fence if present,
16317          * so the tiling mode must match the fb modifier exactly.
16318          */
16319         if (INTEL_GEN(dev_priv) < 4 &&
16320             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16321                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
16322                 goto err;
16323         }
16324
16325         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
16326                                          mode_cmd->modifier[0]);
16327         if (mode_cmd->pitches[0] > max_stride) {
16328                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
16329                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
16330                               "tiled" : "linear",
16331                               mode_cmd->pitches[0], max_stride);
16332                 goto err;
16333         }
16334
16335         /*
16336          * If there's a fence, enforce that
16337          * the fb pitch and fence stride match.
16338          */
16339         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
16340                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
16341                               mode_cmd->pitches[0], stride);
16342                 goto err;
16343         }
16344
16345         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16346         if (mode_cmd->offsets[0] != 0)
16347                 goto err;
16348
16349         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
16350
16351         for (i = 0; i < fb->format->num_planes; i++) {
16352                 u32 stride_alignment;
16353
16354                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
16355                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
16356                         goto err;
16357                 }
16358
16359                 stride_alignment = intel_fb_stride_alignment(fb, i);
16360
16361                 /*
16362                  * Display WA #0531: skl,bxt,kbl,glk
16363                  *
16364                  * Render decompression and plane width > 3840
16365                  * combined with horizontal panning requires the
16366                  * plane stride to be a multiple of 4. We'll just
16367                  * require the entire fb to accommodate that to avoid
16368                  * potential runtime errors at plane configuration time.
16369                  */
16370                 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
16371                     is_ccs_modifier(fb->modifier))
16372                         stride_alignment *= 4;
16373
16374                 if (fb->pitches[i] & (stride_alignment - 1)) {
16375                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
16376                                       i, fb->pitches[i], stride_alignment);
16377                         goto err;
16378                 }
16379
16380                 fb->obj[i] = &obj->base;
16381         }
16382
16383         ret = intel_fill_fb_info(dev_priv, fb);
16384         if (ret)
16385                 goto err;
16386
16387         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
16388         if (ret) {
16389                 DRM_ERROR("framebuffer init failed %d\n", ret);
16390                 goto err;
16391         }
16392
16393         return 0;
16394
16395 err:
16396         intel_frontbuffer_put(intel_fb->frontbuffer);
16397         return ret;
16398 }
16399
16400 static struct drm_framebuffer *
16401 intel_user_framebuffer_create(struct drm_device *dev,
16402                               struct drm_file *filp,
16403                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16404 {
16405         struct drm_framebuffer *fb;
16406         struct drm_i915_gem_object *obj;
16407         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16408
16409         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16410         if (!obj)
16411                 return ERR_PTR(-ENOENT);
16412
16413         fb = intel_framebuffer_create(obj, &mode_cmd);
16414         i915_gem_object_put(obj);
16415
16416         return fb;
16417 }
16418
16419 static void intel_atomic_state_free(struct drm_atomic_state *state)
16420 {
16421         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16422
16423         drm_atomic_state_default_release(state);
16424
16425         i915_sw_fence_fini(&intel_state->commit_ready);
16426
16427         kfree(state);
16428 }
16429
16430 static enum drm_mode_status
16431 intel_mode_valid(struct drm_device *dev,
16432                  const struct drm_display_mode *mode)
16433 {
16434         struct drm_i915_private *dev_priv = to_i915(dev);
16435         int hdisplay_max, htotal_max;
16436         int vdisplay_max, vtotal_max;
16437
16438         /*
16439          * Can't reject DBLSCAN here because Xorg ddxen can add piles
16440          * of DBLSCAN modes to the output's mode list when they detect
16441          * the scaling mode property on the connector. And they don't
16442          * ask the kernel to validate those modes in any way until
16443          * modeset time at which point the client gets a protocol error.
16444          * So in order to not upset those clients we silently ignore the
16445          * DBLSCAN flag on such connectors. For other connectors we will
16446          * reject modes with the DBLSCAN flag in encoder->compute_config().
16447          * And we always reject DBLSCAN modes in connector->mode_valid()
16448          * as we never want such modes on the connector's mode list.
16449          */
16450
16451         if (mode->vscan > 1)
16452                 return MODE_NO_VSCAN;
16453
16454         if (mode->flags & DRM_MODE_FLAG_HSKEW)
16455                 return MODE_H_ILLEGAL;
16456
16457         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
16458                            DRM_MODE_FLAG_NCSYNC |
16459                            DRM_MODE_FLAG_PCSYNC))
16460                 return MODE_HSYNC;
16461
16462         if (mode->flags & (DRM_MODE_FLAG_BCAST |
16463                            DRM_MODE_FLAG_PIXMUX |
16464                            DRM_MODE_FLAG_CLKDIV2))
16465                 return MODE_BAD;
16466
16467         /* Transcoder timing limits */
16468         if (INTEL_GEN(dev_priv) >= 11) {
16469                 hdisplay_max = 16384;
16470                 vdisplay_max = 8192;
16471                 htotal_max = 16384;
16472                 vtotal_max = 8192;
16473         } else if (INTEL_GEN(dev_priv) >= 9 ||
16474                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
16475                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
16476                 vdisplay_max = 4096;
16477                 htotal_max = 8192;
16478                 vtotal_max = 8192;
16479         } else if (INTEL_GEN(dev_priv) >= 3) {
16480                 hdisplay_max = 4096;
16481                 vdisplay_max = 4096;
16482                 htotal_max = 8192;
16483                 vtotal_max = 8192;
16484         } else {
16485                 hdisplay_max = 2048;
16486                 vdisplay_max = 2048;
16487                 htotal_max = 4096;
16488                 vtotal_max = 4096;
16489         }
16490
16491         if (mode->hdisplay > hdisplay_max ||
16492             mode->hsync_start > htotal_max ||
16493             mode->hsync_end > htotal_max ||
16494             mode->htotal > htotal_max)
16495                 return MODE_H_ILLEGAL;
16496
16497         if (mode->vdisplay > vdisplay_max ||
16498             mode->vsync_start > vtotal_max ||
16499             mode->vsync_end > vtotal_max ||
16500             mode->vtotal > vtotal_max)
16501                 return MODE_V_ILLEGAL;
16502
16503         if (INTEL_GEN(dev_priv) >= 5) {
16504                 if (mode->hdisplay < 64 ||
16505                     mode->htotal - mode->hdisplay < 32)
16506                         return MODE_H_ILLEGAL;
16507
16508                 if (mode->vtotal - mode->vdisplay < 5)
16509                         return MODE_V_ILLEGAL;
16510         } else {
16511                 if (mode->htotal - mode->hdisplay < 32)
16512                         return MODE_H_ILLEGAL;
16513
16514                 if (mode->vtotal - mode->vdisplay < 3)
16515                         return MODE_V_ILLEGAL;
16516         }
16517
16518         return MODE_OK;
16519 }
16520
16521 enum drm_mode_status
16522 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
16523                                 const struct drm_display_mode *mode)
16524 {
16525         int plane_width_max, plane_height_max;
16526
16527         /*
16528          * intel_mode_valid() should be
16529          * sufficient on older platforms.
16530          */
16531         if (INTEL_GEN(dev_priv) < 9)
16532                 return MODE_OK;
16533
16534         /*
16535          * Most people will probably want a fullscreen
16536          * plane so let's not advertize modes that are
16537          * too big for that.
16538          */
16539         if (INTEL_GEN(dev_priv) >= 11) {
16540                 plane_width_max = 5120;
16541                 plane_height_max = 4320;
16542         } else {
16543                 plane_width_max = 5120;
16544                 plane_height_max = 4096;
16545         }
16546
16547         if (mode->hdisplay > plane_width_max)
16548                 return MODE_H_ILLEGAL;
16549
16550         if (mode->vdisplay > plane_height_max)
16551                 return MODE_V_ILLEGAL;
16552
16553         return MODE_OK;
16554 }
16555
16556 static const struct drm_mode_config_funcs intel_mode_funcs = {
16557         .fb_create = intel_user_framebuffer_create,
16558         .get_format_info = intel_get_format_info,
16559         .output_poll_changed = intel_fbdev_output_poll_changed,
16560         .mode_valid = intel_mode_valid,
16561         .atomic_check = intel_atomic_check,
16562         .atomic_commit = intel_atomic_commit,
16563         .atomic_state_alloc = intel_atomic_state_alloc,
16564         .atomic_state_clear = intel_atomic_state_clear,
16565         .atomic_state_free = intel_atomic_state_free,
16566 };
16567
16568 /**
16569  * intel_init_display_hooks - initialize the display modesetting hooks
16570  * @dev_priv: device private
16571  */
16572 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16573 {
16574         intel_init_cdclk_hooks(dev_priv);
16575
16576         if (INTEL_GEN(dev_priv) >= 9) {
16577                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16578                 dev_priv->display.get_initial_plane_config =
16579                         skylake_get_initial_plane_config;
16580                 dev_priv->display.crtc_compute_clock =
16581                         haswell_crtc_compute_clock;
16582                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16583                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16584         } else if (HAS_DDI(dev_priv)) {
16585                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16586                 dev_priv->display.get_initial_plane_config =
16587                         i9xx_get_initial_plane_config;
16588                 dev_priv->display.crtc_compute_clock =
16589                         haswell_crtc_compute_clock;
16590                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16591                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16592         } else if (HAS_PCH_SPLIT(dev_priv)) {
16593                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16594                 dev_priv->display.get_initial_plane_config =
16595                         i9xx_get_initial_plane_config;
16596                 dev_priv->display.crtc_compute_clock =
16597                         ironlake_crtc_compute_clock;
16598                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16599                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16600         } else if (IS_CHERRYVIEW(dev_priv)) {
16601                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16602                 dev_priv->display.get_initial_plane_config =
16603                         i9xx_get_initial_plane_config;
16604                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16605                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16606                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16607         } else if (IS_VALLEYVIEW(dev_priv)) {
16608                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16609                 dev_priv->display.get_initial_plane_config =
16610                         i9xx_get_initial_plane_config;
16611                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16612                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16613                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16614         } else if (IS_G4X(dev_priv)) {
16615                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16616                 dev_priv->display.get_initial_plane_config =
16617                         i9xx_get_initial_plane_config;
16618                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16619                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16620                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16621         } else if (IS_PINEVIEW(dev_priv)) {
16622                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16623                 dev_priv->display.get_initial_plane_config =
16624                         i9xx_get_initial_plane_config;
16625                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16626                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16627                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16628         } else if (!IS_GEN(dev_priv, 2)) {
16629                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16630                 dev_priv->display.get_initial_plane_config =
16631                         i9xx_get_initial_plane_config;
16632                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16633                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16634                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16635         } else {
16636                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16637                 dev_priv->display.get_initial_plane_config =
16638                         i9xx_get_initial_plane_config;
16639                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16640                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16641                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16642         }
16643
16644         if (IS_GEN(dev_priv, 5)) {
16645                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16646         } else if (IS_GEN(dev_priv, 6)) {
16647                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16648         } else if (IS_IVYBRIDGE(dev_priv)) {
16649                 /* FIXME: detect B0+ stepping and use auto training */
16650                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16651         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16652                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16653         }
16654
16655         if (INTEL_GEN(dev_priv) >= 9)
16656                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
16657         else
16658                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
16659
16660 }
16661
16662 void intel_modeset_init_hw(struct drm_i915_private *i915)
16663 {
16664         intel_update_cdclk(i915);
16665         intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
16666         i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
16667 }
16668
16669 /*
16670  * Calculate what we think the watermarks should be for the state we've read
16671  * out of the hardware and then immediately program those watermarks so that
16672  * we ensure the hardware settings match our internal state.
16673  *
16674  * We can calculate what we think WM's should be by creating a duplicate of the
16675  * current state (which was constructed during hardware readout) and running it
16676  * through the atomic check code to calculate new watermark values in the
16677  * state object.
16678  */
16679 static void sanitize_watermarks(struct drm_device *dev)
16680 {
16681         struct drm_i915_private *dev_priv = to_i915(dev);
16682         struct drm_atomic_state *state;
16683         struct intel_atomic_state *intel_state;
16684         struct intel_crtc *crtc;
16685         struct intel_crtc_state *crtc_state;
16686         struct drm_modeset_acquire_ctx ctx;
16687         int ret;
16688         int i;
16689
16690         /* Only supported on platforms that use atomic watermark design */
16691         if (!dev_priv->display.optimize_watermarks)
16692                 return;
16693
16694         /*
16695          * We need to hold connection_mutex before calling duplicate_state so
16696          * that the connector loop is protected.
16697          */
16698         drm_modeset_acquire_init(&ctx, 0);
16699 retry:
16700         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16701         if (ret == -EDEADLK) {
16702                 drm_modeset_backoff(&ctx);
16703                 goto retry;
16704         } else if (WARN_ON(ret)) {
16705                 goto fail;
16706         }
16707
16708         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16709         if (WARN_ON(IS_ERR(state)))
16710                 goto fail;
16711
16712         intel_state = to_intel_atomic_state(state);
16713
16714         /*
16715          * Hardware readout is the only time we don't want to calculate
16716          * intermediate watermarks (since we don't trust the current
16717          * watermarks).
16718          */
16719         if (!HAS_GMCH(dev_priv))
16720                 intel_state->skip_intermediate_wm = true;
16721
16722         ret = intel_atomic_check(dev, state);
16723         if (ret) {
16724                 /*
16725                  * If we fail here, it means that the hardware appears to be
16726                  * programmed in a way that shouldn't be possible, given our
16727                  * understanding of watermark requirements.  This might mean a
16728                  * mistake in the hardware readout code or a mistake in the
16729                  * watermark calculations for a given platform.  Raise a WARN
16730                  * so that this is noticeable.
16731                  *
16732                  * If this actually happens, we'll have to just leave the
16733                  * BIOS-programmed watermarks untouched and hope for the best.
16734                  */
16735                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16736                 goto put_state;
16737         }
16738
16739         /* Write calculated watermark values back */
16740         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16741                 crtc_state->wm.need_postvbl_update = true;
16742                 dev_priv->display.optimize_watermarks(intel_state, crtc_state);
16743
16744                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16745         }
16746
16747 put_state:
16748         drm_atomic_state_put(state);
16749 fail:
16750         drm_modeset_drop_locks(&ctx);
16751         drm_modeset_acquire_fini(&ctx);
16752 }
16753
16754 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16755 {
16756         if (IS_GEN(dev_priv, 5)) {
16757                 u32 fdi_pll_clk =
16758                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16759
16760                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16761         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16762                 dev_priv->fdi_pll_freq = 270000;
16763         } else {
16764                 return;
16765         }
16766
16767         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16768 }
16769
16770 static int intel_initial_commit(struct drm_device *dev)
16771 {
16772         struct drm_atomic_state *state = NULL;
16773         struct drm_modeset_acquire_ctx ctx;
16774         struct intel_crtc *crtc;
16775         int ret = 0;
16776
16777         state = drm_atomic_state_alloc(dev);
16778         if (!state)
16779                 return -ENOMEM;
16780
16781         drm_modeset_acquire_init(&ctx, 0);
16782
16783 retry:
16784         state->acquire_ctx = &ctx;
16785
16786         for_each_intel_crtc(dev, crtc) {
16787                 struct intel_crtc_state *crtc_state =
16788                         intel_atomic_get_crtc_state(state, crtc);
16789
16790                 if (IS_ERR(crtc_state)) {
16791                         ret = PTR_ERR(crtc_state);
16792                         goto out;
16793                 }
16794
16795                 if (crtc_state->hw.active) {
16796                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
16797                         if (ret)
16798                                 goto out;
16799
16800                         /*
16801                          * FIXME hack to force a LUT update to avoid the
16802                          * plane update forcing the pipe gamma on without
16803                          * having a proper LUT loaded. Remove once we
16804                          * have readout for pipe gamma enable.
16805                          */
16806                         crtc_state->uapi.color_mgmt_changed = true;
16807                 }
16808         }
16809
16810         ret = drm_atomic_commit(state);
16811
16812 out:
16813         if (ret == -EDEADLK) {
16814                 drm_atomic_state_clear(state);
16815                 drm_modeset_backoff(&ctx);
16816                 goto retry;
16817         }
16818
16819         drm_atomic_state_put(state);
16820
16821         drm_modeset_drop_locks(&ctx);
16822         drm_modeset_acquire_fini(&ctx);
16823
16824         return ret;
16825 }
16826
16827 static void intel_mode_config_init(struct drm_i915_private *i915)
16828 {
16829         struct drm_mode_config *mode_config = &i915->drm.mode_config;
16830
16831         drm_mode_config_init(&i915->drm);
16832
16833         mode_config->min_width = 0;
16834         mode_config->min_height = 0;
16835
16836         mode_config->preferred_depth = 24;
16837         mode_config->prefer_shadow = 1;
16838
16839         mode_config->allow_fb_modifiers = true;
16840
16841         mode_config->funcs = &intel_mode_funcs;
16842
16843         /*
16844          * Maximum framebuffer dimensions, chosen to match
16845          * the maximum render engine surface size on gen4+.
16846          */
16847         if (INTEL_GEN(i915) >= 7) {
16848                 mode_config->max_width = 16384;
16849                 mode_config->max_height = 16384;
16850         } else if (INTEL_GEN(i915) >= 4) {
16851                 mode_config->max_width = 8192;
16852                 mode_config->max_height = 8192;
16853         } else if (IS_GEN(i915, 3)) {
16854                 mode_config->max_width = 4096;
16855                 mode_config->max_height = 4096;
16856         } else {
16857                 mode_config->max_width = 2048;
16858                 mode_config->max_height = 2048;
16859         }
16860
16861         if (IS_I845G(i915) || IS_I865G(i915)) {
16862                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
16863                 mode_config->cursor_height = 1023;
16864         } else if (IS_GEN(i915, 2)) {
16865                 mode_config->cursor_width = 64;
16866                 mode_config->cursor_height = 64;
16867         } else {
16868                 mode_config->cursor_width = 256;
16869                 mode_config->cursor_height = 256;
16870         }
16871 }
16872
16873 int intel_modeset_init(struct drm_i915_private *i915)
16874 {
16875         struct drm_device *dev = &i915->drm;
16876         enum pipe pipe;
16877         struct intel_crtc *crtc;
16878         int ret;
16879
16880         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16881         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16882                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16883
16884         intel_mode_config_init(i915);
16885
16886         ret = intel_bw_init(i915);
16887         if (ret)
16888                 return ret;
16889
16890         init_llist_head(&i915->atomic_helper.free_list);
16891         INIT_WORK(&i915->atomic_helper.free_work,
16892                   intel_atomic_helper_free_state_worker);
16893
16894         intel_init_quirks(i915);
16895
16896         intel_fbc_init(i915);
16897
16898         intel_init_pm(i915);
16899
16900         intel_panel_sanitize_ssc(i915);
16901
16902         intel_gmbus_setup(i915);
16903
16904         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16905                       INTEL_NUM_PIPES(i915),
16906                       INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
16907
16908         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
16909                 for_each_pipe(i915, pipe) {
16910                         ret = intel_crtc_init(i915, pipe);
16911                         if (ret) {
16912                                 drm_mode_config_cleanup(dev);
16913                                 return ret;
16914                         }
16915                 }
16916         }
16917
16918         intel_shared_dpll_init(dev);
16919         intel_update_fdi_pll_freq(i915);
16920
16921         intel_update_czclk(i915);
16922         intel_modeset_init_hw(i915);
16923
16924         intel_hdcp_component_init(i915);
16925
16926         if (i915->max_cdclk_freq == 0)
16927                 intel_update_max_cdclk(i915);
16928
16929         /* Just disable it once at startup */
16930         intel_vga_disable(i915);
16931         intel_setup_outputs(i915);
16932
16933         drm_modeset_lock_all(dev);
16934         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
16935         drm_modeset_unlock_all(dev);
16936
16937         for_each_intel_crtc(dev, crtc) {
16938                 struct intel_initial_plane_config plane_config = {};
16939
16940                 if (!crtc->active)
16941                         continue;
16942
16943                 /*
16944                  * Note that reserving the BIOS fb up front prevents us
16945                  * from stuffing other stolen allocations like the ring
16946                  * on top.  This prevents some ugliness at boot time, and
16947                  * can even allow for smooth boot transitions if the BIOS
16948                  * fb is large enough for the active pipe configuration.
16949                  */
16950                 i915->display.get_initial_plane_config(crtc, &plane_config);
16951
16952                 /*
16953                  * If the fb is shared between multiple heads, we'll
16954                  * just get the first one.
16955                  */
16956                 intel_find_initial_plane_obj(crtc, &plane_config);
16957         }
16958
16959         /*
16960          * Make sure hardware watermarks really match the state we read out.
16961          * Note that we need to do this after reconstructing the BIOS fb's
16962          * since the watermark calculation done here will use pstate->fb.
16963          */
16964         if (!HAS_GMCH(i915))
16965                 sanitize_watermarks(dev);
16966
16967         /*
16968          * Force all active planes to recompute their states. So that on
16969          * mode_setcrtc after probe, all the intel_plane_state variables
16970          * are already calculated and there is no assert_plane warnings
16971          * during bootup.
16972          */
16973         ret = intel_initial_commit(dev);
16974         if (ret)
16975                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
16976
16977         return 0;
16978 }
16979
16980 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
16981 {
16982         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16983         /* 640x480@60Hz, ~25175 kHz */
16984         struct dpll clock = {
16985                 .m1 = 18,
16986                 .m2 = 7,
16987                 .p1 = 13,
16988                 .p2 = 4,
16989                 .n = 2,
16990         };
16991         u32 dpll, fp;
16992         int i;
16993
16994         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
16995
16996         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
16997                       pipe_name(pipe), clock.vco, clock.dot);
16998
16999         fp = i9xx_dpll_compute_fp(&clock);
17000         dpll = DPLL_DVO_2X_MODE |
17001                 DPLL_VGA_MODE_DIS |
17002                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17003                 PLL_P2_DIVIDE_BY_4 |
17004                 PLL_REF_INPUT_DREFCLK |
17005                 DPLL_VCO_ENABLE;
17006
17007         I915_WRITE(FP0(pipe), fp);
17008         I915_WRITE(FP1(pipe), fp);
17009
17010         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17011         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17012         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17013         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17014         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17015         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17016         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17017
17018         /*
17019          * Apparently we need to have VGA mode enabled prior to changing
17020          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17021          * dividers, even though the register value does change.
17022          */
17023         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17024         I915_WRITE(DPLL(pipe), dpll);
17025
17026         /* Wait for the clocks to stabilize. */
17027         POSTING_READ(DPLL(pipe));
17028         udelay(150);
17029
17030         /* The pixel multiplier can only be updated once the
17031          * DPLL is enabled and the clocks are stable.
17032          *
17033          * So write it again.
17034          */
17035         I915_WRITE(DPLL(pipe), dpll);
17036
17037         /* We do this three times for luck */
17038         for (i = 0; i < 3 ; i++) {
17039                 I915_WRITE(DPLL(pipe), dpll);
17040                 POSTING_READ(DPLL(pipe));
17041                 udelay(150); /* wait for warmup */
17042         }
17043
17044         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17045         POSTING_READ(PIPECONF(pipe));
17046
17047         intel_wait_for_pipe_scanline_moving(crtc);
17048 }
17049
17050 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17051 {
17052         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17053
17054         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
17055                       pipe_name(pipe));
17056
17057         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
17058         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
17059         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
17060         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
17061         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
17062
17063         I915_WRITE(PIPECONF(pipe), 0);
17064         POSTING_READ(PIPECONF(pipe));
17065
17066         intel_wait_for_pipe_scanline_stopped(crtc);
17067
17068         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
17069         POSTING_READ(DPLL(pipe));
17070 }
17071
17072 static void
17073 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17074 {
17075         struct intel_crtc *crtc;
17076
17077         if (INTEL_GEN(dev_priv) >= 4)
17078                 return;
17079
17080         for_each_intel_crtc(&dev_priv->drm, crtc) {
17081                 struct intel_plane *plane =
17082                         to_intel_plane(crtc->base.primary);
17083                 struct intel_crtc *plane_crtc;
17084                 enum pipe pipe;
17085
17086                 if (!plane->get_hw_state(plane, &pipe))
17087                         continue;
17088
17089                 if (pipe == crtc->pipe)
17090                         continue;
17091
17092                 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17093                               plane->base.base.id, plane->base.name);
17094
17095                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17096                 intel_plane_disable_noatomic(plane_crtc, plane);
17097         }
17098 }
17099
17100 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17101 {
17102         struct drm_device *dev = crtc->base.dev;
17103         struct intel_encoder *encoder;
17104
17105         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17106                 return true;
17107
17108         return false;
17109 }
17110
17111 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17112 {
17113         struct drm_device *dev = encoder->base.dev;
17114         struct intel_connector *connector;
17115
17116         for_each_connector_on_encoder(dev, &encoder->base, connector)
17117                 return connector;
17118
17119         return NULL;
17120 }
17121
17122 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17123                               enum pipe pch_transcoder)
17124 {
17125         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17126                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17127 }
17128
17129 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17130                                 struct drm_modeset_acquire_ctx *ctx)
17131 {
17132         struct drm_device *dev = crtc->base.dev;
17133         struct drm_i915_private *dev_priv = to_i915(dev);
17134         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17135         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17136
17137         /* Clear any frame start delays used for debugging left by the BIOS */
17138         if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
17139                 i915_reg_t reg = PIPECONF(cpu_transcoder);
17140
17141                 I915_WRITE(reg,
17142                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
17143         }
17144
17145         if (crtc_state->hw.active) {
17146                 struct intel_plane *plane;
17147
17148                 /* Disable everything but the primary plane */
17149                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17150                         const struct intel_plane_state *plane_state =
17151                                 to_intel_plane_state(plane->base.state);
17152
17153                         if (plane_state->uapi.visible &&
17154                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17155                                 intel_plane_disable_noatomic(crtc, plane);
17156                 }
17157
17158                 /*
17159                  * Disable any background color set by the BIOS, but enable the
17160                  * gamma and CSC to match how we program our planes.
17161                  */
17162                 if (INTEL_GEN(dev_priv) >= 9)
17163                         I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
17164                                    SKL_BOTTOM_COLOR_GAMMA_ENABLE |
17165                                    SKL_BOTTOM_COLOR_CSC_ENABLE);
17166         }
17167
17168         /* Adjust the state of the output pipe according to whether we
17169          * have active connectors/encoders. */
17170         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
17171                 intel_crtc_disable_noatomic(&crtc->base, ctx);
17172
17173         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
17174                 /*
17175                  * We start out with underrun reporting disabled to avoid races.
17176                  * For correct bookkeeping mark this on active crtcs.
17177                  *
17178                  * Also on gmch platforms we dont have any hardware bits to
17179                  * disable the underrun reporting. Which means we need to start
17180                  * out with underrun reporting disabled also on inactive pipes,
17181                  * since otherwise we'll complain about the garbage we read when
17182                  * e.g. coming up after runtime pm.
17183                  *
17184                  * No protection against concurrent access is required - at
17185                  * worst a fifo underrun happens which also sets this to false.
17186                  */
17187                 crtc->cpu_fifo_underrun_disabled = true;
17188                 /*
17189                  * We track the PCH trancoder underrun reporting state
17190                  * within the crtc. With crtc for pipe A housing the underrun
17191                  * reporting state for PCH transcoder A, crtc for pipe B housing
17192                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
17193                  * and marking underrun reporting as disabled for the non-existing
17194                  * PCH transcoders B and C would prevent enabling the south
17195                  * error interrupt (see cpt_can_enable_serr_int()).
17196                  */
17197                 if (has_pch_trancoder(dev_priv, crtc->pipe))
17198                         crtc->pch_fifo_underrun_disabled = true;
17199         }
17200 }
17201
17202 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
17203 {
17204         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
17205
17206         /*
17207          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
17208          * the hardware when a high res displays plugged in. DPLL P
17209          * divider is zero, and the pipe timings are bonkers. We'll
17210          * try to disable everything in that case.
17211          *
17212          * FIXME would be nice to be able to sanitize this state
17213          * without several WARNs, but for now let's take the easy
17214          * road.
17215          */
17216         return IS_GEN(dev_priv, 6) &&
17217                 crtc_state->hw.active &&
17218                 crtc_state->shared_dpll &&
17219                 crtc_state->port_clock == 0;
17220 }
17221
17222 static void intel_sanitize_encoder(struct intel_encoder *encoder)
17223 {
17224         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
17225         struct intel_connector *connector;
17226         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
17227         struct intel_crtc_state *crtc_state = crtc ?
17228                 to_intel_crtc_state(crtc->base.state) : NULL;
17229
17230         /* We need to check both for a crtc link (meaning that the
17231          * encoder is active and trying to read from a pipe) and the
17232          * pipe itself being active. */
17233         bool has_active_crtc = crtc_state &&
17234                 crtc_state->hw.active;
17235
17236         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
17237                 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
17238                               pipe_name(crtc->pipe));
17239                 has_active_crtc = false;
17240         }
17241
17242         connector = intel_encoder_find_connector(encoder);
17243         if (connector && !has_active_crtc) {
17244                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
17245                               encoder->base.base.id,
17246                               encoder->base.name);
17247
17248                 /* Connector is active, but has no active pipe. This is
17249                  * fallout from our resume register restoring. Disable
17250                  * the encoder manually again. */
17251                 if (crtc_state) {
17252                         struct drm_encoder *best_encoder;
17253
17254                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
17255                                       encoder->base.base.id,
17256                                       encoder->base.name);
17257
17258                         /* avoid oopsing in case the hooks consult best_encoder */
17259                         best_encoder = connector->base.state->best_encoder;
17260                         connector->base.state->best_encoder = &encoder->base;
17261
17262                         if (encoder->disable)
17263                                 encoder->disable(encoder, crtc_state,
17264                                                  connector->base.state);
17265                         if (encoder->post_disable)
17266                                 encoder->post_disable(encoder, crtc_state,
17267                                                       connector->base.state);
17268
17269                         connector->base.state->best_encoder = best_encoder;
17270                 }
17271                 encoder->base.crtc = NULL;
17272
17273                 /* Inconsistent output/port/pipe state happens presumably due to
17274                  * a bug in one of the get_hw_state functions. Or someplace else
17275                  * in our code, like the register restore mess on resume. Clamp
17276                  * things to off as a safer default. */
17277
17278                 connector->base.dpms = DRM_MODE_DPMS_OFF;
17279                 connector->base.encoder = NULL;
17280         }
17281
17282         /* notify opregion of the sanitized encoder state */
17283         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
17284
17285         if (INTEL_GEN(dev_priv) >= 11)
17286                 icl_sanitize_encoder_pll_mapping(encoder);
17287 }
17288
17289 /* FIXME read out full plane state for all planes */
17290 static void readout_plane_state(struct drm_i915_private *dev_priv)
17291 {
17292         struct intel_plane *plane;
17293         struct intel_crtc *crtc;
17294
17295         for_each_intel_plane(&dev_priv->drm, plane) {
17296                 struct intel_plane_state *plane_state =
17297                         to_intel_plane_state(plane->base.state);
17298                 struct intel_crtc_state *crtc_state;
17299                 enum pipe pipe = PIPE_A;
17300                 bool visible;
17301
17302                 visible = plane->get_hw_state(plane, &pipe);
17303
17304                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17305                 crtc_state = to_intel_crtc_state(crtc->base.state);
17306
17307                 intel_set_plane_visible(crtc_state, plane_state, visible);
17308
17309                 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
17310                               plane->base.base.id, plane->base.name,
17311                               enableddisabled(visible), pipe_name(pipe));
17312         }
17313
17314         for_each_intel_crtc(&dev_priv->drm, crtc) {
17315                 struct intel_crtc_state *crtc_state =
17316                         to_intel_crtc_state(crtc->base.state);
17317
17318                 fixup_active_planes(crtc_state);
17319         }
17320 }
17321
17322 static void intel_modeset_readout_hw_state(struct drm_device *dev)
17323 {
17324         struct drm_i915_private *dev_priv = to_i915(dev);
17325         enum pipe pipe;
17326         struct intel_crtc *crtc;
17327         struct intel_encoder *encoder;
17328         struct intel_connector *connector;
17329         struct drm_connector_list_iter conn_iter;
17330         int i;
17331
17332         dev_priv->active_pipes = 0;
17333
17334         for_each_intel_crtc(dev, crtc) {
17335                 struct intel_crtc_state *crtc_state =
17336                         to_intel_crtc_state(crtc->base.state);
17337
17338                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
17339                 intel_crtc_free_hw_state(crtc_state);
17340                 memset(crtc_state, 0, sizeof(*crtc_state));
17341                 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
17342
17343                 crtc_state->hw.active = crtc_state->hw.enable =
17344                         dev_priv->display.get_pipe_config(crtc, crtc_state);
17345
17346                 crtc->base.enabled = crtc_state->hw.enable;
17347                 crtc->active = crtc_state->hw.active;
17348
17349                 if (crtc_state->hw.active)
17350                         dev_priv->active_pipes |= BIT(crtc->pipe);
17351
17352                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17353                               crtc->base.base.id, crtc->base.name,
17354                               enableddisabled(crtc_state->hw.active));
17355         }
17356
17357         readout_plane_state(dev_priv);
17358
17359         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17360                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17361
17362                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
17363                                                         &pll->state.hw_state);
17364
17365                 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
17366                     pll->info->id == DPLL_ID_EHL_DPLL4) {
17367                         pll->wakeref = intel_display_power_get(dev_priv,
17368                                                                POWER_DOMAIN_DPLL_DC_OFF);
17369                 }
17370
17371                 pll->state.crtc_mask = 0;
17372                 for_each_intel_crtc(dev, crtc) {
17373                         struct intel_crtc_state *crtc_state =
17374                                 to_intel_crtc_state(crtc->base.state);
17375
17376                         if (crtc_state->hw.active &&
17377                             crtc_state->shared_dpll == pll)
17378                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17379                 }
17380                 pll->active_mask = pll->state.crtc_mask;
17381
17382                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17383                               pll->info->name, pll->state.crtc_mask, pll->on);
17384         }
17385
17386         for_each_intel_encoder(dev, encoder) {
17387                 pipe = 0;
17388
17389                 if (encoder->get_hw_state(encoder, &pipe)) {
17390                         struct intel_crtc_state *crtc_state;
17391
17392                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17393                         crtc_state = to_intel_crtc_state(crtc->base.state);
17394
17395                         encoder->base.crtc = &crtc->base;
17396                         encoder->get_config(encoder, crtc_state);
17397                 } else {
17398                         encoder->base.crtc = NULL;
17399                 }
17400
17401                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17402                               encoder->base.base.id, encoder->base.name,
17403                               enableddisabled(encoder->base.crtc),
17404                               pipe_name(pipe));
17405         }
17406
17407         drm_connector_list_iter_begin(dev, &conn_iter);
17408         for_each_intel_connector_iter(connector, &conn_iter) {
17409                 if (connector->get_hw_state(connector)) {
17410                         struct intel_crtc_state *crtc_state;
17411                         struct intel_crtc *crtc;
17412
17413                         connector->base.dpms = DRM_MODE_DPMS_ON;
17414
17415                         encoder = connector->encoder;
17416                         connector->base.encoder = &encoder->base;
17417
17418                         crtc = to_intel_crtc(encoder->base.crtc);
17419                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
17420
17421                         if (crtc_state && crtc_state->hw.active) {
17422                                 /*
17423                                  * This has to be done during hardware readout
17424                                  * because anything calling .crtc_disable may
17425                                  * rely on the connector_mask being accurate.
17426                                  */
17427                                 crtc_state->uapi.connector_mask |=
17428                                         drm_connector_mask(&connector->base);
17429                                 crtc_state->uapi.encoder_mask |=
17430                                         drm_encoder_mask(&encoder->base);
17431                         }
17432                 } else {
17433                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17434                         connector->base.encoder = NULL;
17435                 }
17436                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17437                               connector->base.base.id, connector->base.name,
17438                               enableddisabled(connector->base.encoder));
17439         }
17440         drm_connector_list_iter_end(&conn_iter);
17441
17442         for_each_intel_crtc(dev, crtc) {
17443                 struct intel_bw_state *bw_state =
17444                         to_intel_bw_state(dev_priv->bw_obj.state);
17445                 struct intel_crtc_state *crtc_state =
17446                         to_intel_crtc_state(crtc->base.state);
17447                 struct intel_plane *plane;
17448                 int min_cdclk = 0;
17449
17450                 if (crtc_state->hw.active) {
17451                         struct drm_display_mode *mode = &crtc_state->hw.mode;
17452
17453                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
17454                                                     crtc_state);
17455
17456                         *mode = crtc_state->hw.adjusted_mode;
17457                         mode->hdisplay = crtc_state->pipe_src_w;
17458                         mode->vdisplay = crtc_state->pipe_src_h;
17459
17460                         /*
17461                          * The initial mode needs to be set in order to keep
17462                          * the atomic core happy. It wants a valid mode if the
17463                          * crtc's enabled, so we do the above call.
17464                          *
17465                          * But we don't set all the derived state fully, hence
17466                          * set a flag to indicate that a full recalculation is
17467                          * needed on the next commit.
17468                          */
17469                         mode->private_flags = I915_MODE_FLAG_INHERITED;
17470
17471                         intel_crtc_compute_pixel_rate(crtc_state);
17472
17473                         intel_crtc_update_active_timings(crtc_state);
17474
17475                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
17476                 }
17477
17478                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
17479                         const struct intel_plane_state *plane_state =
17480                                 to_intel_plane_state(plane->base.state);
17481
17482                         /*
17483                          * FIXME don't have the fb yet, so can't
17484                          * use intel_plane_data_rate() :(
17485                          */
17486                         if (plane_state->uapi.visible)
17487                                 crtc_state->data_rate[plane->id] =
17488                                         4 * crtc_state->pixel_rate;
17489                         /*
17490                          * FIXME don't have the fb yet, so can't
17491                          * use plane->min_cdclk() :(
17492                          */
17493                         if (plane_state->uapi.visible && plane->min_cdclk) {
17494                                 if (crtc_state->double_wide ||
17495                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
17496                                         crtc_state->min_cdclk[plane->id] =
17497                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
17498                                 else
17499                                         crtc_state->min_cdclk[plane->id] =
17500                                                 crtc_state->pixel_rate;
17501                         }
17502                         DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n",
17503                                       plane->base.base.id, plane->base.name,
17504                                       crtc_state->min_cdclk[plane->id]);
17505                 }
17506
17507                 if (crtc_state->hw.active) {
17508                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
17509                         if (WARN_ON(min_cdclk < 0))
17510                                 min_cdclk = 0;
17511                 }
17512
17513                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
17514                 dev_priv->min_voltage_level[crtc->pipe] =
17515                         crtc_state->min_voltage_level;
17516
17517                 intel_bw_crtc_update(bw_state, crtc_state);
17518
17519                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17520         }
17521 }
17522
17523 static void
17524 get_encoder_power_domains(struct drm_i915_private *dev_priv)
17525 {
17526         struct intel_encoder *encoder;
17527
17528         for_each_intel_encoder(&dev_priv->drm, encoder) {
17529                 struct intel_crtc_state *crtc_state;
17530
17531                 if (!encoder->get_power_domains)
17532                         continue;
17533
17534                 /*
17535                  * MST-primary and inactive encoders don't have a crtc state
17536                  * and neither of these require any power domain references.
17537                  */
17538                 if (!encoder->base.crtc)
17539                         continue;
17540
17541                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
17542                 encoder->get_power_domains(encoder, crtc_state);
17543         }
17544 }
17545
17546 static void intel_early_display_was(struct drm_i915_private *dev_priv)
17547 {
17548         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
17549         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
17550                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
17551                            DARBF_GATING_DIS);
17552
17553         if (IS_HASWELL(dev_priv)) {
17554                 /*
17555                  * WaRsPkgCStateDisplayPMReq:hsw
17556                  * System hang if this isn't done before disabling all planes!
17557                  */
17558                 I915_WRITE(CHICKEN_PAR1_1,
17559                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
17560         }
17561 }
17562
17563 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
17564                                        enum port port, i915_reg_t hdmi_reg)
17565 {
17566         u32 val = I915_READ(hdmi_reg);
17567
17568         if (val & SDVO_ENABLE ||
17569             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
17570                 return;
17571
17572         DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
17573                       port_name(port));
17574
17575         val &= ~SDVO_PIPE_SEL_MASK;
17576         val |= SDVO_PIPE_SEL(PIPE_A);
17577
17578         I915_WRITE(hdmi_reg, val);
17579 }
17580
17581 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
17582                                      enum port port, i915_reg_t dp_reg)
17583 {
17584         u32 val = I915_READ(dp_reg);
17585
17586         if (val & DP_PORT_EN ||
17587             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
17588                 return;
17589
17590         DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
17591                       port_name(port));
17592
17593         val &= ~DP_PIPE_SEL_MASK;
17594         val |= DP_PIPE_SEL(PIPE_A);
17595
17596         I915_WRITE(dp_reg, val);
17597 }
17598
17599 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
17600 {
17601         /*
17602          * The BIOS may select transcoder B on some of the PCH
17603          * ports even it doesn't enable the port. This would trip
17604          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
17605          * Sanitize the transcoder select bits to prevent that. We
17606          * assume that the BIOS never actually enabled the port,
17607          * because if it did we'd actually have to toggle the port
17608          * on and back off to make the transcoder A select stick
17609          * (see. intel_dp_link_down(), intel_disable_hdmi(),
17610          * intel_disable_sdvo()).
17611          */
17612         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
17613         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
17614         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
17615
17616         /* PCH SDVOB multiplex with HDMIB */
17617         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
17618         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
17619         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
17620 }
17621
17622 /* Scan out the current hw modeset state,
17623  * and sanitizes it to the current state
17624  */
17625 static void
17626 intel_modeset_setup_hw_state(struct drm_device *dev,
17627                              struct drm_modeset_acquire_ctx *ctx)
17628 {
17629         struct drm_i915_private *dev_priv = to_i915(dev);
17630         struct intel_crtc_state *crtc_state;
17631         struct intel_encoder *encoder;
17632         struct intel_crtc *crtc;
17633         intel_wakeref_t wakeref;
17634         int i;
17635
17636         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17637
17638         intel_early_display_was(dev_priv);
17639         intel_modeset_readout_hw_state(dev);
17640
17641         /* HW state is read out, now we need to sanitize this mess. */
17642
17643         /* Sanitize the TypeC port mode upfront, encoders depend on this */
17644         for_each_intel_encoder(dev, encoder) {
17645                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17646
17647                 /* We need to sanitize only the MST primary port. */
17648                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17649                     intel_phy_is_tc(dev_priv, phy))
17650                         intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17651         }
17652
17653         get_encoder_power_domains(dev_priv);
17654
17655         if (HAS_PCH_IBX(dev_priv))
17656                 ibx_sanitize_pch_ports(dev_priv);
17657
17658         /*
17659          * intel_sanitize_plane_mapping() may need to do vblank
17660          * waits, so we need vblank interrupts restored beforehand.
17661          */
17662         for_each_intel_crtc(&dev_priv->drm, crtc) {
17663                 crtc_state = to_intel_crtc_state(crtc->base.state);
17664
17665                 drm_crtc_vblank_reset(&crtc->base);
17666
17667                 if (crtc_state->hw.active)
17668                         intel_crtc_vblank_on(crtc_state);
17669         }
17670
17671         intel_sanitize_plane_mapping(dev_priv);
17672
17673         for_each_intel_encoder(dev, encoder)
17674                 intel_sanitize_encoder(encoder);
17675
17676         for_each_intel_crtc(&dev_priv->drm, crtc) {
17677                 crtc_state = to_intel_crtc_state(crtc->base.state);
17678                 intel_sanitize_crtc(crtc, ctx);
17679                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17680         }
17681
17682         intel_modeset_update_connector_atomic_state(dev);
17683
17684         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17685                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17686
17687                 if (!pll->on || pll->active_mask)
17688                         continue;
17689
17690                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17691                               pll->info->name);
17692
17693                 pll->info->funcs->disable(dev_priv, pll);
17694                 pll->on = false;
17695         }
17696
17697         if (IS_G4X(dev_priv)) {
17698                 g4x_wm_get_hw_state(dev_priv);
17699                 g4x_wm_sanitize(dev_priv);
17700         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17701                 vlv_wm_get_hw_state(dev_priv);
17702                 vlv_wm_sanitize(dev_priv);
17703         } else if (INTEL_GEN(dev_priv) >= 9) {
17704                 skl_wm_get_hw_state(dev_priv);
17705         } else if (HAS_PCH_SPLIT(dev_priv)) {
17706                 ilk_wm_get_hw_state(dev_priv);
17707         }
17708
17709         for_each_intel_crtc(dev, crtc) {
17710                 u64 put_domains;
17711
17712                 crtc_state = to_intel_crtc_state(crtc->base.state);
17713                 put_domains = modeset_get_crtc_power_domains(crtc_state);
17714                 if (WARN_ON(put_domains))
17715                         modeset_put_power_domains(dev_priv, put_domains);
17716         }
17717
17718         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17719
17720         intel_fbc_init_pipe_state(dev_priv);
17721 }
17722
17723 void intel_display_resume(struct drm_device *dev)
17724 {
17725         struct drm_i915_private *dev_priv = to_i915(dev);
17726         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17727         struct drm_modeset_acquire_ctx ctx;
17728         int ret;
17729
17730         dev_priv->modeset_restore_state = NULL;
17731         if (state)
17732                 state->acquire_ctx = &ctx;
17733
17734         drm_modeset_acquire_init(&ctx, 0);
17735
17736         while (1) {
17737                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17738                 if (ret != -EDEADLK)
17739                         break;
17740
17741                 drm_modeset_backoff(&ctx);
17742         }
17743
17744         if (!ret)
17745                 ret = __intel_display_resume(dev, state, &ctx);
17746
17747         intel_enable_ipc(dev_priv);
17748         drm_modeset_drop_locks(&ctx);
17749         drm_modeset_acquire_fini(&ctx);
17750
17751         if (ret)
17752                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17753         if (state)
17754                 drm_atomic_state_put(state);
17755 }
17756
17757 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
17758 {
17759         struct intel_connector *connector;
17760         struct drm_connector_list_iter conn_iter;
17761
17762         /* Kill all the work that may have been queued by hpd. */
17763         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
17764         for_each_intel_connector_iter(connector, &conn_iter) {
17765                 if (connector->modeset_retry_work.func)
17766                         cancel_work_sync(&connector->modeset_retry_work);
17767                 if (connector->hdcp.shim) {
17768                         cancel_delayed_work_sync(&connector->hdcp.check_work);
17769                         cancel_work_sync(&connector->hdcp.prop_work);
17770                 }
17771         }
17772         drm_connector_list_iter_end(&conn_iter);
17773 }
17774
17775 void intel_modeset_driver_remove(struct drm_i915_private *i915)
17776 {
17777         flush_workqueue(i915->flip_wq);
17778         flush_workqueue(i915->modeset_wq);
17779
17780         flush_work(&i915->atomic_helper.free_work);
17781         WARN_ON(!llist_empty(&i915->atomic_helper.free_list));
17782
17783         /*
17784          * Interrupts and polling as the first thing to avoid creating havoc.
17785          * Too much stuff here (turning of connectors, ...) would
17786          * experience fancy races otherwise.
17787          */
17788         intel_irq_uninstall(i915);
17789
17790         /*
17791          * Due to the hpd irq storm handling the hotplug work can re-arm the
17792          * poll handlers. Hence disable polling after hpd handling is shut down.
17793          */
17794         intel_hpd_poll_fini(i915);
17795
17796         /* poll work can call into fbdev, hence clean that up afterwards */
17797         intel_fbdev_fini(i915);
17798
17799         intel_unregister_dsm_handler();
17800
17801         intel_fbc_global_disable(i915);
17802
17803         /* flush any delayed tasks or pending work */
17804         flush_scheduled_work();
17805
17806         intel_hdcp_component_fini(i915);
17807
17808         drm_mode_config_cleanup(&i915->drm);
17809
17810         intel_overlay_cleanup(i915);
17811
17812         intel_gmbus_teardown(i915);
17813
17814         destroy_workqueue(i915->flip_wq);
17815         destroy_workqueue(i915->modeset_wq);
17816
17817         intel_fbc_cleanup_cfb(i915);
17818 }
17819
17820 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17821
17822 struct intel_display_error_state {
17823
17824         u32 power_well_driver;
17825
17826         struct intel_cursor_error_state {
17827                 u32 control;
17828                 u32 position;
17829                 u32 base;
17830                 u32 size;
17831         } cursor[I915_MAX_PIPES];
17832
17833         struct intel_pipe_error_state {
17834                 bool power_domain_on;
17835                 u32 source;
17836                 u32 stat;
17837         } pipe[I915_MAX_PIPES];
17838
17839         struct intel_plane_error_state {
17840                 u32 control;
17841                 u32 stride;
17842                 u32 size;
17843                 u32 pos;
17844                 u32 addr;
17845                 u32 surface;
17846                 u32 tile_offset;
17847         } plane[I915_MAX_PIPES];
17848
17849         struct intel_transcoder_error_state {
17850                 bool available;
17851                 bool power_domain_on;
17852                 enum transcoder cpu_transcoder;
17853
17854                 u32 conf;
17855
17856                 u32 htotal;
17857                 u32 hblank;
17858                 u32 hsync;
17859                 u32 vtotal;
17860                 u32 vblank;
17861                 u32 vsync;
17862         } transcoder[5];
17863 };
17864
17865 struct intel_display_error_state *
17866 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17867 {
17868         struct intel_display_error_state *error;
17869         int transcoders[] = {
17870                 TRANSCODER_A,
17871                 TRANSCODER_B,
17872                 TRANSCODER_C,
17873                 TRANSCODER_D,
17874                 TRANSCODER_EDP,
17875         };
17876         int i;
17877
17878         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
17879
17880         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
17881                 return NULL;
17882
17883         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17884         if (error == NULL)
17885                 return NULL;
17886
17887         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17888                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
17889
17890         for_each_pipe(dev_priv, i) {
17891                 error->pipe[i].power_domain_on =
17892                         __intel_display_power_is_enabled(dev_priv,
17893                                                          POWER_DOMAIN_PIPE(i));
17894                 if (!error->pipe[i].power_domain_on)
17895                         continue;
17896
17897                 error->cursor[i].control = I915_READ(CURCNTR(i));
17898                 error->cursor[i].position = I915_READ(CURPOS(i));
17899                 error->cursor[i].base = I915_READ(CURBASE(i));
17900
17901                 error->plane[i].control = I915_READ(DSPCNTR(i));
17902                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17903                 if (INTEL_GEN(dev_priv) <= 3) {
17904                         error->plane[i].size = I915_READ(DSPSIZE(i));
17905                         error->plane[i].pos = I915_READ(DSPPOS(i));
17906                 }
17907                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17908                         error->plane[i].addr = I915_READ(DSPADDR(i));
17909                 if (INTEL_GEN(dev_priv) >= 4) {
17910                         error->plane[i].surface = I915_READ(DSPSURF(i));
17911                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17912                 }
17913
17914                 error->pipe[i].source = I915_READ(PIPESRC(i));
17915
17916                 if (HAS_GMCH(dev_priv))
17917                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17918         }
17919
17920         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
17921                 enum transcoder cpu_transcoder = transcoders[i];
17922
17923                 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
17924                         continue;
17925
17926                 error->transcoder[i].available = true;
17927                 error->transcoder[i].power_domain_on =
17928                         __intel_display_power_is_enabled(dev_priv,
17929                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17930                 if (!error->transcoder[i].power_domain_on)
17931                         continue;
17932
17933                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17934
17935                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17936                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17937                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17938                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17939                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17940                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17941                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17942         }
17943
17944         return error;
17945 }
17946
17947 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17948
17949 void
17950 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17951                                 struct intel_display_error_state *error)
17952 {
17953         struct drm_i915_private *dev_priv = m->i915;
17954         int i;
17955
17956         if (!error)
17957                 return;
17958
17959         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
17960         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17961                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17962                            error->power_well_driver);
17963         for_each_pipe(dev_priv, i) {
17964                 err_printf(m, "Pipe [%d]:\n", i);
17965                 err_printf(m, "  Power: %s\n",
17966                            onoff(error->pipe[i].power_domain_on));
17967                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17968                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17969
17970                 err_printf(m, "Plane [%d]:\n", i);
17971                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17972                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17973                 if (INTEL_GEN(dev_priv) <= 3) {
17974                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17975                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17976                 }
17977                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17978                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17979                 if (INTEL_GEN(dev_priv) >= 4) {
17980                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17981                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17982                 }
17983
17984                 err_printf(m, "Cursor [%d]:\n", i);
17985                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17986                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17987                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17988         }
17989
17990         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
17991                 if (!error->transcoder[i].available)
17992                         continue;
17993
17994                 err_printf(m, "CPU transcoder: %s\n",
17995                            transcoder_name(error->transcoder[i].cpu_transcoder));
17996                 err_printf(m, "  Power: %s\n",
17997                            onoff(error->transcoder[i].power_domain_on));
17998                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17999                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
18000                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
18001                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
18002                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
18003                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
18004                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
18005         }
18006 }
18007
18008 #endif