drivers/gpu/drm/i915/display/intel_display.h

   1 /*
   2  * Copyright © 2006-2019 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29 #include <drm/i915_drm.h>
  30 #include "intel_dp_link_training.h"
  31
  32 enum link_m_n_set;
  33 struct dpll;
  34 struct drm_connector;
  35 struct drm_device;
  36 struct drm_display_mode;
  37 struct drm_encoder;
  38 struct drm_file;
  39 struct drm_format_info;
  40 struct drm_framebuffer;
  41 struct drm_i915_error_state_buf;
  42 struct drm_i915_gem_object;
  43 struct drm_i915_private;
  44 struct drm_modeset_acquire_ctx;
  45 struct drm_plane;
  46 struct drm_plane_state;
  47 struct i915_ggtt_view;
  48 struct intel_crtc;
  49 struct intel_crtc_state;
  50 struct intel_digital_port;
  51 struct intel_dp;
  52 struct intel_encoder;
  53 struct intel_load_detect_pipe;
  54 struct intel_plane;
  55 struct intel_plane_state;
  56 struct intel_remapped_info;
  57 struct intel_rotation_info;
  58 struct intel_crtc_state;
  59
  60 enum i915_gpio {
  61         GPIOA,
  62         GPIOB,
  63         GPIOC,
  64         GPIOD,
  65         GPIOE,
  66         GPIOF,
  67         GPIOG,
  68         GPIOH,
  69         __GPIOI_UNUSED,
  70         GPIOJ,
  71         GPIOK,
  72         GPIOL,
  73         GPIOM,
  74         GPION,
  75         GPIOO,
  76 };
  77
  78 /*
  79  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
  80  * rest have consecutive values and match the enum values of transcoders
  81  * with a 1:1 transcoder -> pipe mapping.
  82  */
  83 enum pipe {
  84         INVALID_PIPE = -1,
  85
  86         PIPE_A = 0,
  87         PIPE_B,
  88         PIPE_C,
  89         PIPE_D,
  90         _PIPE_EDP,
  91
  92         I915_MAX_PIPES = _PIPE_EDP
  93 };
  94
  95 #define pipe_name(p) ((p) + 'A')
  96
  97 enum transcoder {
  98         INVALID_TRANSCODER = -1,
  99         /*
 100          * The following transcoders have a 1:1 transcoder -> pipe mapping,
 101          * keep their values fixed: the code assumes that TRANSCODER_A=0, the
 102          * rest have consecutive values and match the enum values of the pipes
 103          * they map to.
 104          */
 105         TRANSCODER_A = PIPE_A,
 106         TRANSCODER_B = PIPE_B,
 107         TRANSCODER_C = PIPE_C,
 108         TRANSCODER_D = PIPE_D,
 109
 110         /*
 111          * The following transcoders can map to any pipe, their enum value
 112          * doesn't need to stay fixed.
 113          */
 114         TRANSCODER_EDP,
 115         TRANSCODER_DSI_0,
 116         TRANSCODER_DSI_1,
 117         TRANSCODER_DSI_A = TRANSCODER_DSI_0,    /* legacy DSI */
 118         TRANSCODER_DSI_C = TRANSCODER_DSI_1,    /* legacy DSI */
 119
 120         I915_MAX_TRANSCODERS
 121 };
 122
 123 static inline const char *transcoder_name(enum transcoder transcoder)
 124 {
 125         switch (transcoder) {
 126         case TRANSCODER_A:
 127                 return "A";
 128         case TRANSCODER_B:
 129                 return "B";
 130         case TRANSCODER_C:
 131                 return "C";
 132         case TRANSCODER_D:
 133                 return "D";
 134         case TRANSCODER_EDP:
 135                 return "EDP";
 136         case TRANSCODER_DSI_A:
 137                 return "DSI A";
 138         case TRANSCODER_DSI_C:
 139                 return "DSI C";
 140         default:
 141                 return "<invalid>";
 142         }
 143 }
 144
 145 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 146 {
 147         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 148 }
 149
 150 /*
 151  * Global legacy plane identifier. Valid only for primary/sprite
 152  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 153  */
 154 enum i9xx_plane_id {
 155         PLANE_A,
 156         PLANE_B,
 157         PLANE_C,
 158 };
 159
 160 #define plane_name(p) ((p) + 'A')
 161 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 162
 163 /*
 164  * Per-pipe plane identifier.
 165  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 166  * number of planes per CRTC.  Not all platforms really have this many planes,
 167  * which means some arrays of size I915_MAX_PLANES may have unused entries
 168  * between the topmost sprite plane and the cursor plane.
 169  *
 170  * This is expected to be passed to various register macros
 171  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 172  */
 173 enum plane_id {
 174         PLANE_PRIMARY,
 175         PLANE_SPRITE0,
 176         PLANE_SPRITE1,
 177         PLANE_SPRITE2,
 178         PLANE_SPRITE3,
 179         PLANE_SPRITE4,
 180         PLANE_SPRITE5,
 181         PLANE_CURSOR,
 182
 183         I915_MAX_PLANES,
 184 };
 185
 186 #define for_each_plane_id_on_crtc(__crtc, __p) \
 187         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 188                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 189
 190 enum port {
 191         PORT_NONE = -1,
 192
 193         PORT_A = 0,
 194         PORT_B,
 195         PORT_C,
 196         PORT_D,
 197         PORT_E,
 198         PORT_F,
 199         PORT_G,
 200         PORT_H,
 201         PORT_I,
 202
 203         I915_MAX_PORTS
 204 };
 205
 206 #define port_name(p) ((p) + 'A')
 207
 208 /*
 209  * Ports identifier referenced from other drivers.
 210  * Expected to remain stable over time
 211  */
 212 static inline const char *port_identifier(enum port port)
 213 {
 214         switch (port) {
 215         case PORT_A:
 216                 return "Port A";
 217         case PORT_B:
 218                 return "Port B";
 219         case PORT_C:
 220                 return "Port C";
 221         case PORT_D:
 222                 return "Port D";
 223         case PORT_E:
 224                 return "Port E";
 225         case PORT_F:
 226                 return "Port F";
 227         case PORT_G:
 228                 return "Port G";
 229         case PORT_H:
 230                 return "Port H";
 231         case PORT_I:
 232                 return "Port I";
 233         default:
 234                 return "<invalid>";
 235         }
 236 }
 237
 238 enum tc_port {
 239         PORT_TC_NONE = -1,
 240
 241         PORT_TC1 = 0,
 242         PORT_TC2,
 243         PORT_TC3,
 244         PORT_TC4,
 245         PORT_TC5,
 246         PORT_TC6,
 247
 248         I915_MAX_TC_PORTS
 249 };
 250
 251 enum tc_port_mode {
 252         TC_PORT_TBT_ALT,
 253         TC_PORT_DP_ALT,
 254         TC_PORT_LEGACY,
 255 };
 256
 257 enum dpio_channel {
 258         DPIO_CH0,
 259         DPIO_CH1
 260 };
 261
 262 enum dpio_phy {
 263         DPIO_PHY0,
 264         DPIO_PHY1,
 265         DPIO_PHY2,
 266 };
 267
 268 #define I915_NUM_PHYS_VLV 2
 269
 270 enum aux_ch {
 271         AUX_CH_A,
 272         AUX_CH_B,
 273         AUX_CH_C,
 274         AUX_CH_D,
 275         AUX_CH_E, /* ICL+ */
 276         AUX_CH_F,
 277         AUX_CH_G,
 278 };
 279
 280 #define aux_ch_name(a) ((a) + 'A')
 281
 282 /* Used by dp and fdi links */
 283 struct intel_link_m_n {
 284         u32 tu;
 285         u32 gmch_m;
 286         u32 gmch_n;
 287         u32 link_m;
 288         u32 link_n;
 289 };
 290
 291 enum phy {
 292         PHY_NONE = -1,
 293
 294         PHY_A = 0,
 295         PHY_B,
 296         PHY_C,
 297         PHY_D,
 298         PHY_E,
 299         PHY_F,
 300         PHY_G,
 301         PHY_H,
 302         PHY_I,
 303
 304         I915_MAX_PHYS
 305 };
 306
 307 #define phy_name(a) ((a) + 'A')
 308
 309 enum phy_fia {
 310         FIA1,
 311         FIA2,
 312         FIA3,
 313 };
 314
 315 #define for_each_pipe(__dev_priv, __p) \
 316         for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++)
 317
 318 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 319         for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \
 320                 for_each_if((__mask) & BIT(__p))
 321
 322 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 323         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 324                 for_each_if ((__mask) & (1 << (__t)))
 325
 326 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 327         for ((__p) = 0;                                                 \
 328              (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;       \
 329              (__p)++)
 330
 331 #define for_each_sprite(__dev_priv, __p, __s)                           \
 332         for ((__s) = 0;                                                 \
 333              (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
 334              (__s)++)
 335
 336 #define for_each_port_masked(__port, __ports_mask) \
 337         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 338                 for_each_if((__ports_mask) & BIT(__port))
 339
 340 #define for_each_phy_masked(__phy, __phys_mask) \
 341         for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)       \
 342                 for_each_if((__phys_mask) & BIT(__phy))
 343
 344 #define for_each_crtc(dev, crtc) \
 345         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 346
 347 #define for_each_intel_plane(dev, intel_plane) \
 348         list_for_each_entry(intel_plane,                        \
 349                             &(dev)->mode_config.plane_list,     \
 350                             base.head)
 351
 352 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 353         list_for_each_entry(intel_plane,                                \
 354                             &(dev)->mode_config.plane_list,             \
 355                             base.head)                                  \
 356                 for_each_if((plane_mask) &                              \
 357                             drm_plane_mask(&intel_plane->base))
 358
 359 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 360         list_for_each_entry(intel_plane,                                \
 361                             &(dev)->mode_config.plane_list,             \
 362                             base.head)                                  \
 363                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 364
 365 #define for_each_intel_crtc(dev, intel_crtc)                            \
 366         list_for_each_entry(intel_crtc,                                 \
 367                             &(dev)->mode_config.crtc_list,              \
 368                             base.head)
 369
 370 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 371         list_for_each_entry(intel_crtc,                                 \
 372                             &(dev)->mode_config.crtc_list,              \
 373                             base.head)                                  \
 374                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 375
 376 #define for_each_intel_encoder(dev, intel_encoder)              \
 377         list_for_each_entry(intel_encoder,                      \
 378                             &(dev)->mode_config.encoder_list,   \
 379                             base.head)
 380
 381 #define for_each_intel_dp(dev, intel_encoder)                   \
 382         for_each_intel_encoder(dev, intel_encoder)              \
 383                 for_each_if(intel_encoder_is_dp(intel_encoder))
 384
 385 #define for_each_intel_connector_iter(intel_connector, iter) \
 386         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 387
 388 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 389         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 390                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 391
 392 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 393         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 394                 for_each_if((intel_connector)->base.encoder == (__encoder))
 395
 396 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 397         for ((__i) = 0; \
 398              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 399                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 400                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 401              (__i)++) \
 402                 for_each_if(plane)
 403
 404 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 405         for ((__i) = 0; \
 406              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 407                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 408                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 409              (__i)++) \
 410                 for_each_if(plane)
 411
 412 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 413         for ((__i) = 0; \
 414              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 415                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 416                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 417              (__i)++) \
 418                 for_each_if(crtc)
 419
 420 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 421         for ((__i) = 0; \
 422              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 423                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 424                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 425                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 426              (__i)++) \
 427                 for_each_if(plane)
 428
 429 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 430         for ((__i) = 0; \
 431              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 432                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 433                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 434                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 435              (__i)++) \
 436                 for_each_if(crtc)
 437
 438 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 439         for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
 440              (__i) >= 0  && \
 441              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 442               (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 443               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 444              (__i)--) \
 445                 for_each_if(crtc)
 446
 447 #define intel_atomic_crtc_state_for_each_plane_state( \
 448                   plane, plane_state, \
 449                   crtc_state) \
 450         for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
 451                                 ((crtc_state)->base.plane_mask)) \
 452                 for_each_if ((plane_state = \
 453                               to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
 454
 455 void intel_link_compute_m_n(u16 bpp, int nlanes,
 456                             int pixel_clock, int link_clock,
 457                             struct intel_link_m_n *m_n,
 458                             bool constant_n, bool fec_enable);
 459 bool is_ccs_modifier(u64 modifier);
 460 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 461 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 462                               u32 pixel_format, u64 modifier);
 463 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
 464 enum drm_mode_status
 465 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 466                                 const struct drm_display_mode *mode);
 467 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 468 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 469
 470 void intel_plane_destroy(struct drm_plane *plane);
 471 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 472 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 473 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
 474 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
 475 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 476                       const char *name, u32 reg, int ref_freq);
 477 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 478                            const char *name, u32 reg);
 479 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
 480 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
 481 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
 482 unsigned int intel_fb_xy_to_linear(int x, int y,
 483                                    const struct intel_plane_state *state,
 484                                    int plane);
 485 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
 486                                    int color_plane, unsigned int height);
 487 void intel_add_fb_offsets(int *x, int *y,
 488                           const struct intel_plane_state *state, int plane);
 489 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
 490 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
 491 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
 492 int intel_display_suspend(struct drm_device *dev);
 493 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 494 void intel_encoder_destroy(struct drm_encoder *encoder);
 495 struct drm_display_mode *
 496 intel_encoder_current_mode(struct intel_encoder *encoder);
 497 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
 498 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 499 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 500                               enum port port);
 501 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
 502                                       struct drm_file *file_priv);
 503 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 504                                              enum pipe pipe);
 505 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
 506
 507 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 508 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 509                          struct intel_digital_port *dport,
 510                          unsigned int expected_mask);
 511 int intel_get_load_detect_pipe(struct drm_connector *connector,
 512                                const struct drm_display_mode *mode,
 513                                struct intel_load_detect_pipe *old,
 514                                struct drm_modeset_acquire_ctx *ctx);
 515 void intel_release_load_detect_pipe(struct drm_connector *connector,
 516                                     struct intel_load_detect_pipe *old,
 517                                     struct drm_modeset_acquire_ctx *ctx);
 518 struct i915_vma *
 519 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
 520                            const struct i915_ggtt_view *view,
 521                            bool uses_fence,
 522                            unsigned long *out_flags);
 523 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
 524 struct drm_framebuffer *
 525 intel_framebuffer_create(struct drm_i915_gem_object *obj,
 526                          struct drm_mode_fb_cmd2 *mode_cmd);
 527 int intel_prepare_plane_fb(struct drm_plane *plane,
 528                            struct drm_plane_state *new_state);
 529 void intel_cleanup_plane_fb(struct drm_plane *plane,
 530                             struct drm_plane_state *old_state);
 531
 532 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 533                                     enum pipe pipe);
 534
 535 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
 536                      const struct dpll *dpll);
 537 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
 538 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
 539 bool intel_fuzzy_clock_check(int clock1, int clock2);
 540
 541 void intel_prepare_reset(struct drm_i915_private *dev_priv);
 542 void intel_finish_reset(struct drm_i915_private *dev_priv);
 543 void intel_dp_get_m_n(struct intel_crtc *crtc,
 544                       struct intel_crtc_state *pipe_config);
 545 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
 546                       enum link_m_n_set m_n);
 547 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 548 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 549                         struct dpll *best_clock);
 550 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
 551
 552 bool intel_crtc_active(struct intel_crtc *crtc);
 553 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 554 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
 555 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
 556 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 557 enum intel_display_power_domain
 558 intel_aux_power_domain(struct intel_digital_port *dig_port);
 559 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 560                                  struct intel_crtc_state *pipe_config);
 561 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 562                                   struct intel_crtc_state *crtc_state);
 563
 564 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
 565 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
 566 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 567                         const struct intel_plane_state *plane_state);
 568 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
 569 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 570                   const struct intel_plane_state *plane_state);
 571 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
 572 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 573                      int plane);
 574 int skl_check_plane_surface(struct intel_plane_state *plane_state);
 575 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
 576 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 577 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
 578                                    u32 pixel_format, u64 modifier,
 579                                    unsigned int rotation);
 580 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
 581
 582 struct intel_display_error_state *
 583 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
 584 void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
 585                                      struct intel_display_error_state *error);
 586
 587 /* modesetting */
 588 void intel_modeset_init_hw(struct drm_i915_private *i915);
 589 int intel_modeset_init(struct drm_i915_private *i915);
 590 void intel_modeset_driver_remove(struct drm_i915_private *i915);
 591 void intel_display_resume(struct drm_device *dev);
 592 void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
 593
 594 /* modesetting asserts */
 595 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 596                            enum pipe pipe);
 597 void assert_pll(struct drm_i915_private *dev_priv,
 598                 enum pipe pipe, bool state);
 599 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 600 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 601 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
 602 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 603 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 604 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 605                        enum pipe pipe, bool state);
 606 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 607 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 608 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 609 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 610 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 611
 612 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 613  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 614  * which may not necessarily be a user visible problem.  This will either
 615  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 616  * enable distros and users to tailor their preferred amount of i915 abrt
 617  * spam.
 618  */
 619 #define I915_STATE_WARN(condition, format...) ({                        \
 620         int __ret_warn_on = !!(condition);                              \
 621         if (unlikely(__ret_warn_on))                                    \
 622                 if (!WARN(i915_modparams.verbose_state_checks, format)) \
 623                         DRM_ERROR(format);                              \
 624         unlikely(__ret_warn_on);                                        \
 625 })
 626
 627 #define I915_STATE_WARN_ON(x)                                           \
 628         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 629
 630 #endif