drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/i915_drm.h>
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_drv.h"
  47 #include "i915_trace.h"
  48 #include "intel_atomic.h"
  49 #include "intel_audio.h"
  50 #include "intel_connector.h"
  51 #include "intel_ddi.h"
  52 #include "intel_display_types.h"
  53 #include "intel_dp.h"
  54 #include "intel_dp_link_training.h"
  55 #include "intel_dp_mst.h"
  56 #include "intel_dpio_phy.h"
  57 #include "intel_fifo_underrun.h"
  58 #include "intel_hdcp.h"
  59 #include "intel_hdmi.h"
  60 #include "intel_hotplug.h"
  61 #include "intel_lspcon.h"
  62 #include "intel_lvds.h"
  63 #include "intel_panel.h"
  64 #include "intel_psr.h"
  65 #include "intel_sideband.h"
  66 #include "intel_tc.h"
  67 #include "intel_vdsc.h"
  68
  69 #define DP_DPRX_ESI_LEN 14
  70
  71 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  72 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  73
  74 /* DP DSC throughput values used for slice count calculations KPixels/s */
  75 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  76 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  77 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  78
  79 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
  80 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
  81
  82 /* Compliance test status bits  */
  83 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  84 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  85 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  86 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  87
  88 struct dp_link_dpll {
  89         int clock;
  90         struct dpll dpll;
  91 };
  92
  93 static const struct dp_link_dpll g4x_dpll[] = {
  94         { 162000,
  95                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  96         { 270000,
  97                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  98 };
  99
 100 static const struct dp_link_dpll pch_dpll[] = {
 101         { 162000,
 102                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 103         { 270000,
 104                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 105 };
 106
 107 static const struct dp_link_dpll vlv_dpll[] = {
 108         { 162000,
 109                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 110         { 270000,
 111                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 112 };
 113
 114 /*
 115  * CHV supports eDP 1.4 that have  more link rates.
 116  * Below only provides the fixed rate but exclude variable rate.
 117  */
 118 static const struct dp_link_dpll chv_dpll[] = {
 119         /*
 120          * CHV requires to program fractional division for m2.
 121          * m2 is stored in fixed point format using formula below
 122          * (m2_int << 22) | m2_fraction
 123          */
 124         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 125                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 126         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 127                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 128 };
 129
 130 /* Constants for DP DSC configurations */
 131 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 132
 133 /* With Single pipe configuration, HW is capable of supporting maximum
 134  * of 4 slices per line.
 135  */
 136 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 137
 138 /**
 139  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 140  * @intel_dp: DP struct
 141  *
 142  * If a CPU or PCH DP output is attached to an eDP panel, this function
 143  * will return true, and false otherwise.
 144  */
 145 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 146 {
 147         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 148
 149         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 150 }
 151
 152 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 153 {
 154         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 155 }
 156
 157 static void intel_dp_link_down(struct intel_encoder *encoder,
 158                                const struct intel_crtc_state *old_crtc_state);
 159 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 160 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 161 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 162                                            const struct intel_crtc_state *crtc_state);
 163 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 164                                       enum pipe pipe);
 165 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 166
 167 /* update sink rates from dpcd */
 168 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 169 {
 170         static const int dp_rates[] = {
 171                 162000, 270000, 540000, 810000
 172         };
 173         int i, max_rate;
 174
 175         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 176
 177         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 178                 if (dp_rates[i] > max_rate)
 179                         break;
 180                 intel_dp->sink_rates[i] = dp_rates[i];
 181         }
 182
 183         intel_dp->num_sink_rates = i;
 184 }
 185
 186 /* Get length of rates array potentially limited by max_rate. */
 187 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 188 {
 189         int i;
 190
 191         /* Limit results by potentially reduced max rate */
 192         for (i = 0; i < len; i++) {
 193                 if (rates[len - i - 1] <= max_rate)
 194                         return len - i;
 195         }
 196
 197         return 0;
 198 }
 199
 200 /* Get length of common rates array potentially limited by max_rate. */
 201 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 202                                           int max_rate)
 203 {
 204         return intel_dp_rate_limit_len(intel_dp->common_rates,
 205                                        intel_dp->num_common_rates, max_rate);
 206 }
 207
 208 /* Theoretical max between source and sink */
 209 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 210 {
 211         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 212 }
 213
 214 /* Theoretical max between source and sink */
 215 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 216 {
 217         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 218         int source_max = intel_dig_port->max_lanes;
 219         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 220         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 221
 222         return min3(source_max, sink_max, fia_max);
 223 }
 224
 225 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 226 {
 227         return intel_dp->max_link_lane_count;
 228 }
 229
 230 int
 231 intel_dp_link_required(int pixel_clock, int bpp)
 232 {
 233         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 234         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 235 }
 236
 237 int
 238 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 239 {
 240         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 241          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 242          * is transmitted every LS_Clk per lane, there is no need to account for
 243          * the channel encoding that is done in the PHY layer here.
 244          */
 245
 246         return max_link_clock * max_lanes;
 247 }
 248
 249 static int
 250 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 251 {
 252         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 253         struct intel_encoder *encoder = &intel_dig_port->base;
 254         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 255         int max_dotclk = dev_priv->max_dotclk_freq;
 256         int ds_max_dotclk;
 257
 258         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 259
 260         if (type != DP_DS_PORT_TYPE_VGA)
 261                 return max_dotclk;
 262
 263         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 264                                                     intel_dp->downstream_ports);
 265
 266         if (ds_max_dotclk != 0)
 267                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 268
 269         return max_dotclk;
 270 }
 271
 272 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 273 {
 274         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 275         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 276         enum port port = dig_port->base.port;
 277
 278         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 279
 280         /* Low voltage SKUs are limited to max of 5.4G */
 281         if (voltage == VOLTAGE_INFO_0_85V)
 282                 return 540000;
 283
 284         /* For this SKU 8.1G is supported in all ports */
 285         if (IS_CNL_WITH_PORT_F(dev_priv))
 286                 return 810000;
 287
 288         /* For other SKUs, max rate on ports A and D is 5.4G */
 289         if (port == PORT_A || port == PORT_D)
 290                 return 540000;
 291
 292         return 810000;
 293 }
 294
 295 static int icl_max_source_rate(struct intel_dp *intel_dp)
 296 {
 297         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 298         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 299         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 300
 301         if (intel_phy_is_combo(dev_priv, phy) &&
 302             !IS_ELKHARTLAKE(dev_priv) &&
 303             !intel_dp_is_edp(intel_dp))
 304                 return 540000;
 305
 306         return 810000;
 307 }
 308
 309 static void
 310 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 311 {
 312         /* The values must be in increasing order */
 313         static const int cnl_rates[] = {
 314                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 315         };
 316         static const int bxt_rates[] = {
 317                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 318         };
 319         static const int skl_rates[] = {
 320                 162000, 216000, 270000, 324000, 432000, 540000
 321         };
 322         static const int hsw_rates[] = {
 323                 162000, 270000, 540000
 324         };
 325         static const int g4x_rates[] = {
 326                 162000, 270000
 327         };
 328         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 329         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 330         const struct ddi_vbt_port_info *info =
 331                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 332         const int *source_rates;
 333         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 334
 335         /* This should only be done once */
 336         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 337
 338         if (INTEL_GEN(dev_priv) >= 10) {
 339                 source_rates = cnl_rates;
 340                 size = ARRAY_SIZE(cnl_rates);
 341                 if (IS_GEN(dev_priv, 10))
 342                         max_rate = cnl_max_source_rate(intel_dp);
 343                 else
 344                         max_rate = icl_max_source_rate(intel_dp);
 345         } else if (IS_GEN9_LP(dev_priv)) {
 346                 source_rates = bxt_rates;
 347                 size = ARRAY_SIZE(bxt_rates);
 348         } else if (IS_GEN9_BC(dev_priv)) {
 349                 source_rates = skl_rates;
 350                 size = ARRAY_SIZE(skl_rates);
 351         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 352                    IS_BROADWELL(dev_priv)) {
 353                 source_rates = hsw_rates;
 354                 size = ARRAY_SIZE(hsw_rates);
 355         } else {
 356                 source_rates = g4x_rates;
 357                 size = ARRAY_SIZE(g4x_rates);
 358         }
 359
 360         if (max_rate && vbt_max_rate)
 361                 max_rate = min(max_rate, vbt_max_rate);
 362         else if (vbt_max_rate)
 363                 max_rate = vbt_max_rate;
 364
 365         if (max_rate)
 366                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 367
 368         intel_dp->source_rates = source_rates;
 369         intel_dp->num_source_rates = size;
 370 }
 371
 372 static int intersect_rates(const int *source_rates, int source_len,
 373                            const int *sink_rates, int sink_len,
 374                            int *common_rates)
 375 {
 376         int i = 0, j = 0, k = 0;
 377
 378         while (i < source_len && j < sink_len) {
 379                 if (source_rates[i] == sink_rates[j]) {
 380                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 381                                 return k;
 382                         common_rates[k] = source_rates[i];
 383                         ++k;
 384                         ++i;
 385                         ++j;
 386                 } else if (source_rates[i] < sink_rates[j]) {
 387                         ++i;
 388                 } else {
 389                         ++j;
 390                 }
 391         }
 392         return k;
 393 }
 394
 395 /* return index of rate in rates array, or -1 if not found */
 396 static int intel_dp_rate_index(const int *rates, int len, int rate)
 397 {
 398         int i;
 399
 400         for (i = 0; i < len; i++)
 401                 if (rate == rates[i])
 402                         return i;
 403
 404         return -1;
 405 }
 406
 407 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 408 {
 409         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 410
 411         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 412                                                      intel_dp->num_source_rates,
 413                                                      intel_dp->sink_rates,
 414                                                      intel_dp->num_sink_rates,
 415                                                      intel_dp->common_rates);
 416
 417         /* Paranoia, there should always be something in common. */
 418         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 419                 intel_dp->common_rates[0] = 162000;
 420                 intel_dp->num_common_rates = 1;
 421         }
 422 }
 423
 424 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 425                                        u8 lane_count)
 426 {
 427         /*
 428          * FIXME: we need to synchronize the current link parameters with
 429          * hardware readout. Currently fast link training doesn't work on
 430          * boot-up.
 431          */
 432         if (link_rate == 0 ||
 433             link_rate > intel_dp->max_link_rate)
 434                 return false;
 435
 436         if (lane_count == 0 ||
 437             lane_count > intel_dp_max_lane_count(intel_dp))
 438                 return false;
 439
 440         return true;
 441 }
 442
 443 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 444                                                      int link_rate,
 445                                                      u8 lane_count)
 446 {
 447         const struct drm_display_mode *fixed_mode =
 448                 intel_dp->attached_connector->panel.fixed_mode;
 449         int mode_rate, max_rate;
 450
 451         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 452         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 453         if (mode_rate > max_rate)
 454                 return false;
 455
 456         return true;
 457 }
 458
 459 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 460                                             int link_rate, u8 lane_count)
 461 {
 462         int index;
 463
 464         index = intel_dp_rate_index(intel_dp->common_rates,
 465                                     intel_dp->num_common_rates,
 466                                     link_rate);
 467         if (index > 0) {
 468                 if (intel_dp_is_edp(intel_dp) &&
 469                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 470                                                               intel_dp->common_rates[index - 1],
 471                                                               lane_count)) {
 472                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 473                         return 0;
 474                 }
 475                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 476                 intel_dp->max_link_lane_count = lane_count;
 477         } else if (lane_count > 1) {
 478                 if (intel_dp_is_edp(intel_dp) &&
 479                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 480                                                               intel_dp_max_common_rate(intel_dp),
 481                                                               lane_count >> 1)) {
 482                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 483                         return 0;
 484                 }
 485                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 486                 intel_dp->max_link_lane_count = lane_count >> 1;
 487         } else {
 488                 DRM_ERROR("Link Training Unsuccessful\n");
 489                 return -1;
 490         }
 491
 492         return 0;
 493 }
 494
 495 static enum drm_mode_status
 496 intel_dp_mode_valid(struct drm_connector *connector,
 497                     struct drm_display_mode *mode)
 498 {
 499         struct intel_dp *intel_dp = intel_attached_dp(connector);
 500         struct intel_connector *intel_connector = to_intel_connector(connector);
 501         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 502         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 503         int target_clock = mode->clock;
 504         int max_rate, mode_rate, max_lanes, max_link_clock;
 505         int max_dotclk;
 506         u16 dsc_max_output_bpp = 0;
 507         u8 dsc_slice_count = 0;
 508
 509         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 510                 return MODE_NO_DBLESCAN;
 511
 512         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 513
 514         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 515                 if (mode->hdisplay > fixed_mode->hdisplay)
 516                         return MODE_PANEL;
 517
 518                 if (mode->vdisplay > fixed_mode->vdisplay)
 519                         return MODE_PANEL;
 520
 521                 target_clock = fixed_mode->clock;
 522         }
 523
 524         max_link_clock = intel_dp_max_link_rate(intel_dp);
 525         max_lanes = intel_dp_max_lane_count(intel_dp);
 526
 527         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 528         mode_rate = intel_dp_link_required(target_clock, 18);
 529
 530         /*
 531          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 532          * integer value since we support only integer values of bpp.
 533          */
 534         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 535             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 536                 if (intel_dp_is_edp(intel_dp)) {
 537                         dsc_max_output_bpp =
 538                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 539                         dsc_slice_count =
 540                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 541                                                                 true);
 542                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 543                         dsc_max_output_bpp =
 544                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 545                                                             max_lanes,
 546                                                             target_clock,
 547                                                             mode->hdisplay) >> 4;
 548                         dsc_slice_count =
 549                                 intel_dp_dsc_get_slice_count(intel_dp,
 550                                                              target_clock,
 551                                                              mode->hdisplay);
 552                 }
 553         }
 554
 555         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 556             target_clock > max_dotclk)
 557                 return MODE_CLOCK_HIGH;
 558
 559         if (mode->clock < 10000)
 560                 return MODE_CLOCK_LOW;
 561
 562         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 563                 return MODE_H_ILLEGAL;
 564
 565         return intel_mode_valid_max_plane_size(dev_priv, mode);
 566 }
 567
 568 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 569 {
 570         int i;
 571         u32 v = 0;
 572
 573         if (src_bytes > 4)
 574                 src_bytes = 4;
 575         for (i = 0; i < src_bytes; i++)
 576                 v |= ((u32)src[i]) << ((3 - i) * 8);
 577         return v;
 578 }
 579
 580 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 581 {
 582         int i;
 583         if (dst_bytes > 4)
 584                 dst_bytes = 4;
 585         for (i = 0; i < dst_bytes; i++)
 586                 dst[i] = src >> ((3-i) * 8);
 587 }
 588
 589 static void
 590 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 591 static void
 592 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 593                                               bool force_disable_vdd);
 594 static void
 595 intel_dp_pps_init(struct intel_dp *intel_dp);
 596
 597 static intel_wakeref_t
 598 pps_lock(struct intel_dp *intel_dp)
 599 {
 600         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 601         intel_wakeref_t wakeref;
 602
 603         /*
 604          * See intel_power_sequencer_reset() why we need
 605          * a power domain reference here.
 606          */
 607         wakeref = intel_display_power_get(dev_priv,
 608                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 609
 610         mutex_lock(&dev_priv->pps_mutex);
 611
 612         return wakeref;
 613 }
 614
 615 static intel_wakeref_t
 616 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 617 {
 618         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 619
 620         mutex_unlock(&dev_priv->pps_mutex);
 621         intel_display_power_put(dev_priv,
 622                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 623                                 wakeref);
 624         return 0;
 625 }
 626
 627 #define with_pps_lock(dp, wf) \
 628         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 629
 630 static void
 631 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 632 {
 633         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 634         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 635         enum pipe pipe = intel_dp->pps_pipe;
 636         bool pll_enabled, release_cl_override = false;
 637         enum dpio_phy phy = DPIO_PHY(pipe);
 638         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 639         u32 DP;
 640
 641         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 642                  "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 643                  pipe_name(pipe), intel_dig_port->base.base.base.id,
 644                  intel_dig_port->base.base.name))
 645                 return;
 646
 647         DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 648                       pipe_name(pipe), intel_dig_port->base.base.base.id,
 649                       intel_dig_port->base.base.name);
 650
 651         /* Preserve the BIOS-computed detected bit. This is
 652          * supposed to be read-only.
 653          */
 654         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 655         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 656         DP |= DP_PORT_WIDTH(1);
 657         DP |= DP_LINK_TRAIN_PAT_1;
 658
 659         if (IS_CHERRYVIEW(dev_priv))
 660                 DP |= DP_PIPE_SEL_CHV(pipe);
 661         else
 662                 DP |= DP_PIPE_SEL(pipe);
 663
 664         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 665
 666         /*
 667          * The DPLL for the pipe must be enabled for this to work.
 668          * So enable temporarily it if it's not already enabled.
 669          */
 670         if (!pll_enabled) {
 671                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 672                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 673
 674                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 675                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 676                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 677                                   pipe_name(pipe));
 678                         return;
 679                 }
 680         }
 681
 682         /*
 683          * Similar magic as in intel_dp_enable_port().
 684          * We _must_ do this port enable + disable trick
 685          * to make this power sequencer lock onto the port.
 686          * Otherwise even VDD force bit won't work.
 687          */
 688         I915_WRITE(intel_dp->output_reg, DP);
 689         POSTING_READ(intel_dp->output_reg);
 690
 691         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 692         POSTING_READ(intel_dp->output_reg);
 693
 694         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 695         POSTING_READ(intel_dp->output_reg);
 696
 697         if (!pll_enabled) {
 698                 vlv_force_pll_off(dev_priv, pipe);
 699
 700                 if (release_cl_override)
 701                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 702         }
 703 }
 704
 705 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 706 {
 707         struct intel_encoder *encoder;
 708         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 709
 710         /*
 711          * We don't have power sequencer currently.
 712          * Pick one that's not used by other ports.
 713          */
 714         for_each_intel_dp(&dev_priv->drm, encoder) {
 715                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 716
 717                 if (encoder->type == INTEL_OUTPUT_EDP) {
 718                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 719                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 720
 721                         if (intel_dp->pps_pipe != INVALID_PIPE)
 722                                 pipes &= ~(1 << intel_dp->pps_pipe);
 723                 } else {
 724                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 725
 726                         if (intel_dp->active_pipe != INVALID_PIPE)
 727                                 pipes &= ~(1 << intel_dp->active_pipe);
 728                 }
 729         }
 730
 731         if (pipes == 0)
 732                 return INVALID_PIPE;
 733
 734         return ffs(pipes) - 1;
 735 }
 736
 737 static enum pipe
 738 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 739 {
 740         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 741         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 742         enum pipe pipe;
 743
 744         lockdep_assert_held(&dev_priv->pps_mutex);
 745
 746         /* We should never land here with regular DP ports */
 747         WARN_ON(!intel_dp_is_edp(intel_dp));
 748
 749         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 750                 intel_dp->active_pipe != intel_dp->pps_pipe);
 751
 752         if (intel_dp->pps_pipe != INVALID_PIPE)
 753                 return intel_dp->pps_pipe;
 754
 755         pipe = vlv_find_free_pps(dev_priv);
 756
 757         /*
 758          * Didn't find one. This should not happen since there
 759          * are two power sequencers and up to two eDP ports.
 760          */
 761         if (WARN_ON(pipe == INVALID_PIPE))
 762                 pipe = PIPE_A;
 763
 764         vlv_steal_power_sequencer(dev_priv, pipe);
 765         intel_dp->pps_pipe = pipe;
 766
 767         DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 768                       pipe_name(intel_dp->pps_pipe),
 769                       intel_dig_port->base.base.base.id,
 770                       intel_dig_port->base.base.name);
 771
 772         /* init power sequencer on this pipe and port */
 773         intel_dp_init_panel_power_sequencer(intel_dp);
 774         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 775
 776         /*
 777          * Even vdd force doesn't work until we've made
 778          * the power sequencer lock in on the port.
 779          */
 780         vlv_power_sequencer_kick(intel_dp);
 781
 782         return intel_dp->pps_pipe;
 783 }
 784
 785 static int
 786 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 787 {
 788         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 789         int backlight_controller = dev_priv->vbt.backlight.controller;
 790
 791         lockdep_assert_held(&dev_priv->pps_mutex);
 792
 793         /* We should never land here with regular DP ports */
 794         WARN_ON(!intel_dp_is_edp(intel_dp));
 795
 796         if (!intel_dp->pps_reset)
 797                 return backlight_controller;
 798
 799         intel_dp->pps_reset = false;
 800
 801         /*
 802          * Only the HW needs to be reprogrammed, the SW state is fixed and
 803          * has been setup during connector init.
 804          */
 805         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 806
 807         return backlight_controller;
 808 }
 809
 810 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 811                                enum pipe pipe);
 812
 813 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 814                                enum pipe pipe)
 815 {
 816         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 817 }
 818
 819 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 820                                 enum pipe pipe)
 821 {
 822         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 823 }
 824
 825 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 826                          enum pipe pipe)
 827 {
 828         return true;
 829 }
 830
 831 static enum pipe
 832 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 833                      enum port port,
 834                      vlv_pipe_check pipe_check)
 835 {
 836         enum pipe pipe;
 837
 838         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 839                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 840                         PANEL_PORT_SELECT_MASK;
 841
 842                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 843                         continue;
 844
 845                 if (!pipe_check(dev_priv, pipe))
 846                         continue;
 847
 848                 return pipe;
 849         }
 850
 851         return INVALID_PIPE;
 852 }
 853
 854 static void
 855 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 856 {
 857         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 858         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 859         enum port port = intel_dig_port->base.port;
 860
 861         lockdep_assert_held(&dev_priv->pps_mutex);
 862
 863         /* try to find a pipe with this port selected */
 864         /* first pick one where the panel is on */
 865         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 866                                                   vlv_pipe_has_pp_on);
 867         /* didn't find one? pick one where vdd is on */
 868         if (intel_dp->pps_pipe == INVALID_PIPE)
 869                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 870                                                           vlv_pipe_has_vdd_on);
 871         /* didn't find one? pick one with just the correct port */
 872         if (intel_dp->pps_pipe == INVALID_PIPE)
 873                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 874                                                           vlv_pipe_any);
 875
 876         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 877         if (intel_dp->pps_pipe == INVALID_PIPE) {
 878                 DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n",
 879                               intel_dig_port->base.base.base.id,
 880                               intel_dig_port->base.base.name);
 881                 return;
 882         }
 883
 884         DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
 885                       intel_dig_port->base.base.base.id,
 886                       intel_dig_port->base.base.name,
 887                       pipe_name(intel_dp->pps_pipe));
 888
 889         intel_dp_init_panel_power_sequencer(intel_dp);
 890         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 891 }
 892
 893 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 894 {
 895         struct intel_encoder *encoder;
 896
 897         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 898                     !IS_GEN9_LP(dev_priv)))
 899                 return;
 900
 901         /*
 902          * We can't grab pps_mutex here due to deadlock with power_domain
 903          * mutex when power_domain functions are called while holding pps_mutex.
 904          * That also means that in order to use pps_pipe the code needs to
 905          * hold both a power domain reference and pps_mutex, and the power domain
 906          * reference get/put must be done while _not_ holding pps_mutex.
 907          * pps_{lock,unlock}() do these steps in the correct order, so one
 908          * should use them always.
 909          */
 910
 911         for_each_intel_dp(&dev_priv->drm, encoder) {
 912                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 913
 914                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 915
 916                 if (encoder->type != INTEL_OUTPUT_EDP)
 917                         continue;
 918
 919                 if (IS_GEN9_LP(dev_priv))
 920                         intel_dp->pps_reset = true;
 921                 else
 922                         intel_dp->pps_pipe = INVALID_PIPE;
 923         }
 924 }
 925
 926 struct pps_registers {
 927         i915_reg_t pp_ctrl;
 928         i915_reg_t pp_stat;
 929         i915_reg_t pp_on;
 930         i915_reg_t pp_off;
 931         i915_reg_t pp_div;
 932 };
 933
 934 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 935                                     struct pps_registers *regs)
 936 {
 937         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 938         int pps_idx = 0;
 939
 940         memset(regs, 0, sizeof(*regs));
 941
 942         if (IS_GEN9_LP(dev_priv))
 943                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 944         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 945                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 946
 947         regs->pp_ctrl = PP_CONTROL(pps_idx);
 948         regs->pp_stat = PP_STATUS(pps_idx);
 949         regs->pp_on = PP_ON_DELAYS(pps_idx);
 950         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 951
 952         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 953         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 954                 regs->pp_div = INVALID_MMIO_REG;
 955         else
 956                 regs->pp_div = PP_DIVISOR(pps_idx);
 957 }
 958
 959 static i915_reg_t
 960 _pp_ctrl_reg(struct intel_dp *intel_dp)
 961 {
 962         struct pps_registers regs;
 963
 964         intel_pps_get_registers(intel_dp, &regs);
 965
 966         return regs.pp_ctrl;
 967 }
 968
 969 static i915_reg_t
 970 _pp_stat_reg(struct intel_dp *intel_dp)
 971 {
 972         struct pps_registers regs;
 973
 974         intel_pps_get_registers(intel_dp, &regs);
 975
 976         return regs.pp_stat;
 977 }
 978
 979 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 980    This function only applicable when panel PM state is not to be tracked */
 981 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 982                               void *unused)
 983 {
 984         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 985                                                  edp_notifier);
 986         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 987         intel_wakeref_t wakeref;
 988
 989         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 990                 return 0;
 991
 992         with_pps_lock(intel_dp, wakeref) {
 993                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 994                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 995                         i915_reg_t pp_ctrl_reg, pp_div_reg;
 996                         u32 pp_div;
 997
 998                         pp_ctrl_reg = PP_CONTROL(pipe);
 999                         pp_div_reg  = PP_DIVISOR(pipe);
1000                         pp_div = I915_READ(pp_div_reg);
1001                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1002
1003                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1004                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1005                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1006                         msleep(intel_dp->panel_power_cycle_delay);
1007                 }
1008         }
1009
1010         return 0;
1011 }
1012
1013 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1014 {
1015         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1016
1017         lockdep_assert_held(&dev_priv->pps_mutex);
1018
1019         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1020             intel_dp->pps_pipe == INVALID_PIPE)
1021                 return false;
1022
1023         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1024 }
1025
1026 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1027 {
1028         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1029
1030         lockdep_assert_held(&dev_priv->pps_mutex);
1031
1032         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1033             intel_dp->pps_pipe == INVALID_PIPE)
1034                 return false;
1035
1036         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1037 }
1038
1039 static void
1040 intel_dp_check_edp(struct intel_dp *intel_dp)
1041 {
1042         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1043
1044         if (!intel_dp_is_edp(intel_dp))
1045                 return;
1046
1047         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1048                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1049                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1050                               I915_READ(_pp_stat_reg(intel_dp)),
1051                               I915_READ(_pp_ctrl_reg(intel_dp)));
1052         }
1053 }
1054
1055 static u32
1056 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1057 {
1058         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1059         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1060         u32 status;
1061         bool done;
1062
1063 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1064         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1065                                   msecs_to_jiffies_timeout(10));
1066
1067         /* just trace the final value */
1068         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1069
1070         if (!done)
1071                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1072 #undef C
1073
1074         return status;
1075 }
1076
1077 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1078 {
1079         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1080
1081         if (index)
1082                 return 0;
1083
1084         /*
1085          * The clock divider is based off the hrawclk, and would like to run at
1086          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1087          */
1088         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1089 }
1090
1091 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1092 {
1093         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1094         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1095
1096         if (index)
1097                 return 0;
1098
1099         /*
1100          * The clock divider is based off the cdclk or PCH rawclk, and would
1101          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1102          * divide by 2000 and use that
1103          */
1104         if (dig_port->aux_ch == AUX_CH_A)
1105                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1106         else
1107                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1108 }
1109
1110 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1111 {
1112         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1113         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1114
1115         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1116                 /* Workaround for non-ULT HSW */
1117                 switch (index) {
1118                 case 0: return 63;
1119                 case 1: return 72;
1120                 default: return 0;
1121                 }
1122         }
1123
1124         return ilk_get_aux_clock_divider(intel_dp, index);
1125 }
1126
1127 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1128 {
1129         /*
1130          * SKL doesn't need us to program the AUX clock divider (Hardware will
1131          * derive the clock from CDCLK automatically). We still implement the
1132          * get_aux_clock_divider vfunc to plug-in into the existing code.
1133          */
1134         return index ? 0 : 1;
1135 }
1136
1137 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1138                                 int send_bytes,
1139                                 u32 aux_clock_divider)
1140 {
1141         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1142         struct drm_i915_private *dev_priv =
1143                         to_i915(intel_dig_port->base.base.dev);
1144         u32 precharge, timeout;
1145
1146         if (IS_GEN(dev_priv, 6))
1147                 precharge = 3;
1148         else
1149                 precharge = 5;
1150
1151         if (IS_BROADWELL(dev_priv))
1152                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1153         else
1154                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1155
1156         return DP_AUX_CH_CTL_SEND_BUSY |
1157                DP_AUX_CH_CTL_DONE |
1158                DP_AUX_CH_CTL_INTERRUPT |
1159                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1160                timeout |
1161                DP_AUX_CH_CTL_RECEIVE_ERROR |
1162                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1163                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1164                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1165 }
1166
1167 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1168                                 int send_bytes,
1169                                 u32 unused)
1170 {
1171         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1172         u32 ret;
1173
1174         ret = DP_AUX_CH_CTL_SEND_BUSY |
1175               DP_AUX_CH_CTL_DONE |
1176               DP_AUX_CH_CTL_INTERRUPT |
1177               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1178               DP_AUX_CH_CTL_TIME_OUT_MAX |
1179               DP_AUX_CH_CTL_RECEIVE_ERROR |
1180               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1181               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1182               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1183
1184         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1185                 ret |= DP_AUX_CH_CTL_TBT_IO;
1186
1187         return ret;
1188 }
1189
1190 static int
1191 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1192                   const u8 *send, int send_bytes,
1193                   u8 *recv, int recv_size,
1194                   u32 aux_send_ctl_flags)
1195 {
1196         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1197         struct drm_i915_private *i915 =
1198                         to_i915(intel_dig_port->base.base.dev);
1199         struct intel_uncore *uncore = &i915->uncore;
1200         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1201         bool is_tc_port = intel_phy_is_tc(i915, phy);
1202         i915_reg_t ch_ctl, ch_data[5];
1203         u32 aux_clock_divider;
1204         enum intel_display_power_domain aux_domain =
1205                 intel_aux_power_domain(intel_dig_port);
1206         intel_wakeref_t aux_wakeref;
1207         intel_wakeref_t pps_wakeref;
1208         int i, ret, recv_bytes;
1209         int try, clock = 0;
1210         u32 status;
1211         bool vdd;
1212
1213         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1214         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1215                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1216
1217         if (is_tc_port)
1218                 intel_tc_port_lock(intel_dig_port);
1219
1220         aux_wakeref = intel_display_power_get(i915, aux_domain);
1221         pps_wakeref = pps_lock(intel_dp);
1222
1223         /*
1224          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1225          * In such cases we want to leave VDD enabled and it's up to upper layers
1226          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1227          * ourselves.
1228          */
1229         vdd = edp_panel_vdd_on(intel_dp);
1230
1231         /* dp aux is extremely sensitive to irq latency, hence request the
1232          * lowest possible wakeup latency and so prevent the cpu from going into
1233          * deep sleep states.
1234          */
1235         pm_qos_update_request(&i915->pm_qos, 0);
1236
1237         intel_dp_check_edp(intel_dp);
1238
1239         /* Try to wait for any previous AUX channel activity */
1240         for (try = 0; try < 3; try++) {
1241                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1242                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1243                         break;
1244                 msleep(1);
1245         }
1246         /* just trace the final value */
1247         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1248
1249         if (try == 3) {
1250                 static u32 last_status = -1;
1251                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1252
1253                 if (status != last_status) {
1254                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1255                              status);
1256                         last_status = status;
1257                 }
1258
1259                 ret = -EBUSY;
1260                 goto out;
1261         }
1262
1263         /* Only 5 data registers! */
1264         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1265                 ret = -E2BIG;
1266                 goto out;
1267         }
1268
1269         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1270                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1271                                                           send_bytes,
1272                                                           aux_clock_divider);
1273
1274                 send_ctl |= aux_send_ctl_flags;
1275
1276                 /* Must try at least 3 times according to DP spec */
1277                 for (try = 0; try < 5; try++) {
1278                         /* Load the send data into the aux channel data registers */
1279                         for (i = 0; i < send_bytes; i += 4)
1280                                 intel_uncore_write(uncore,
1281                                                    ch_data[i >> 2],
1282                                                    intel_dp_pack_aux(send + i,
1283                                                                      send_bytes - i));
1284
1285                         /* Send the command and wait for it to complete */
1286                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1287
1288                         status = intel_dp_aux_wait_done(intel_dp);
1289
1290                         /* Clear done status and any errors */
1291                         intel_uncore_write(uncore,
1292                                            ch_ctl,
1293                                            status |
1294                                            DP_AUX_CH_CTL_DONE |
1295                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1296                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1297
1298                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1299                          *   400us delay required for errors and timeouts
1300                          *   Timeout errors from the HW already meet this
1301                          *   requirement so skip to next iteration
1302                          */
1303                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1304                                 continue;
1305
1306                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1307                                 usleep_range(400, 500);
1308                                 continue;
1309                         }
1310                         if (status & DP_AUX_CH_CTL_DONE)
1311                                 goto done;
1312                 }
1313         }
1314
1315         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1316                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1317                 ret = -EBUSY;
1318                 goto out;
1319         }
1320
1321 done:
1322         /* Check for timeout or receive error.
1323          * Timeouts occur when the sink is not connected
1324          */
1325         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1326                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1327                 ret = -EIO;
1328                 goto out;
1329         }
1330
1331         /* Timeouts occur when the device isn't connected, so they're
1332          * "normal" -- don't fill the kernel log with these */
1333         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1334                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1335                 ret = -ETIMEDOUT;
1336                 goto out;
1337         }
1338
1339         /* Unload any bytes sent back from the other side */
1340         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1341                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1342
1343         /*
1344          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1345          * We have no idea of what happened so we return -EBUSY so
1346          * drm layer takes care for the necessary retries.
1347          */
1348         if (recv_bytes == 0 || recv_bytes > 20) {
1349                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1350                               recv_bytes);
1351                 ret = -EBUSY;
1352                 goto out;
1353         }
1354
1355         if (recv_bytes > recv_size)
1356                 recv_bytes = recv_size;
1357
1358         for (i = 0; i < recv_bytes; i += 4)
1359                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1360                                     recv + i, recv_bytes - i);
1361
1362         ret = recv_bytes;
1363 out:
1364         pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1365
1366         if (vdd)
1367                 edp_panel_vdd_off(intel_dp, false);
1368
1369         pps_unlock(intel_dp, pps_wakeref);
1370         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1371
1372         if (is_tc_port)
1373                 intel_tc_port_unlock(intel_dig_port);
1374
1375         return ret;
1376 }
1377
1378 #define BARE_ADDRESS_SIZE       3
1379 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1380
1381 static void
1382 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1383                     const struct drm_dp_aux_msg *msg)
1384 {
1385         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1386         txbuf[1] = (msg->address >> 8) & 0xff;
1387         txbuf[2] = msg->address & 0xff;
1388         txbuf[3] = msg->size - 1;
1389 }
1390
1391 static ssize_t
1392 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1393 {
1394         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1395         u8 txbuf[20], rxbuf[20];
1396         size_t txsize, rxsize;
1397         int ret;
1398
1399         intel_dp_aux_header(txbuf, msg);
1400
1401         switch (msg->request & ~DP_AUX_I2C_MOT) {
1402         case DP_AUX_NATIVE_WRITE:
1403         case DP_AUX_I2C_WRITE:
1404         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1405                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1406                 rxsize = 2; /* 0 or 1 data bytes */
1407
1408                 if (WARN_ON(txsize > 20))
1409                         return -E2BIG;
1410
1411                 WARN_ON(!msg->buffer != !msg->size);
1412
1413                 if (msg->buffer)
1414                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1415
1416                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1417                                         rxbuf, rxsize, 0);
1418                 if (ret > 0) {
1419                         msg->reply = rxbuf[0] >> 4;
1420
1421                         if (ret > 1) {
1422                                 /* Number of bytes written in a short write. */
1423                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1424                         } else {
1425                                 /* Return payload size. */
1426                                 ret = msg->size;
1427                         }
1428                 }
1429                 break;
1430
1431         case DP_AUX_NATIVE_READ:
1432         case DP_AUX_I2C_READ:
1433                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1434                 rxsize = msg->size + 1;
1435
1436                 if (WARN_ON(rxsize > 20))
1437                         return -E2BIG;
1438
1439                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1440                                         rxbuf, rxsize, 0);
1441                 if (ret > 0) {
1442                         msg->reply = rxbuf[0] >> 4;
1443                         /*
1444                          * Assume happy day, and copy the data. The caller is
1445                          * expected to check msg->reply before touching it.
1446                          *
1447                          * Return payload size.
1448                          */
1449                         ret--;
1450                         memcpy(msg->buffer, rxbuf + 1, ret);
1451                 }
1452                 break;
1453
1454         default:
1455                 ret = -EINVAL;
1456                 break;
1457         }
1458
1459         return ret;
1460 }
1461
1462
1463 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1464 {
1465         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1466         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1467         enum aux_ch aux_ch = dig_port->aux_ch;
1468
1469         switch (aux_ch) {
1470         case AUX_CH_B:
1471         case AUX_CH_C:
1472         case AUX_CH_D:
1473                 return DP_AUX_CH_CTL(aux_ch);
1474         default:
1475                 MISSING_CASE(aux_ch);
1476                 return DP_AUX_CH_CTL(AUX_CH_B);
1477         }
1478 }
1479
1480 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1481 {
1482         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1483         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1484         enum aux_ch aux_ch = dig_port->aux_ch;
1485
1486         switch (aux_ch) {
1487         case AUX_CH_B:
1488         case AUX_CH_C:
1489         case AUX_CH_D:
1490                 return DP_AUX_CH_DATA(aux_ch, index);
1491         default:
1492                 MISSING_CASE(aux_ch);
1493                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1494         }
1495 }
1496
1497 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1498 {
1499         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1500         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1501         enum aux_ch aux_ch = dig_port->aux_ch;
1502
1503         switch (aux_ch) {
1504         case AUX_CH_A:
1505                 return DP_AUX_CH_CTL(aux_ch);
1506         case AUX_CH_B:
1507         case AUX_CH_C:
1508         case AUX_CH_D:
1509                 return PCH_DP_AUX_CH_CTL(aux_ch);
1510         default:
1511                 MISSING_CASE(aux_ch);
1512                 return DP_AUX_CH_CTL(AUX_CH_A);
1513         }
1514 }
1515
1516 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1517 {
1518         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1519         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1520         enum aux_ch aux_ch = dig_port->aux_ch;
1521
1522         switch (aux_ch) {
1523         case AUX_CH_A:
1524                 return DP_AUX_CH_DATA(aux_ch, index);
1525         case AUX_CH_B:
1526         case AUX_CH_C:
1527         case AUX_CH_D:
1528                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1529         default:
1530                 MISSING_CASE(aux_ch);
1531                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1532         }
1533 }
1534
1535 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1536 {
1537         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1538         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1539         enum aux_ch aux_ch = dig_port->aux_ch;
1540
1541         switch (aux_ch) {
1542         case AUX_CH_A:
1543         case AUX_CH_B:
1544         case AUX_CH_C:
1545         case AUX_CH_D:
1546         case AUX_CH_E:
1547         case AUX_CH_F:
1548                 return DP_AUX_CH_CTL(aux_ch);
1549         default:
1550                 MISSING_CASE(aux_ch);
1551                 return DP_AUX_CH_CTL(AUX_CH_A);
1552         }
1553 }
1554
1555 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1556 {
1557         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1558         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1559         enum aux_ch aux_ch = dig_port->aux_ch;
1560
1561         switch (aux_ch) {
1562         case AUX_CH_A:
1563         case AUX_CH_B:
1564         case AUX_CH_C:
1565         case AUX_CH_D:
1566         case AUX_CH_E:
1567         case AUX_CH_F:
1568                 return DP_AUX_CH_DATA(aux_ch, index);
1569         default:
1570                 MISSING_CASE(aux_ch);
1571                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1572         }
1573 }
1574
1575 static void
1576 intel_dp_aux_fini(struct intel_dp *intel_dp)
1577 {
1578         kfree(intel_dp->aux.name);
1579 }
1580
1581 static void
1582 intel_dp_aux_init(struct intel_dp *intel_dp)
1583 {
1584         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1585         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1586         struct intel_encoder *encoder = &dig_port->base;
1587
1588         if (INTEL_GEN(dev_priv) >= 9) {
1589                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1590                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1591         } else if (HAS_PCH_SPLIT(dev_priv)) {
1592                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1593                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1594         } else {
1595                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1596                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1597         }
1598
1599         if (INTEL_GEN(dev_priv) >= 9)
1600                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1601         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1602                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1603         else if (HAS_PCH_SPLIT(dev_priv))
1604                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1605         else
1606                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1607
1608         if (INTEL_GEN(dev_priv) >= 9)
1609                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1610         else
1611                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1612
1613         drm_dp_aux_init(&intel_dp->aux);
1614
1615         /* Failure to allocate our preferred name is not critical */
1616         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1617                                        port_name(encoder->port));
1618         intel_dp->aux.transfer = intel_dp_aux_transfer;
1619 }
1620
1621 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1622 {
1623         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1624
1625         return max_rate >= 540000;
1626 }
1627
1628 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1629 {
1630         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1631
1632         return max_rate >= 810000;
1633 }
1634
1635 static void
1636 intel_dp_set_clock(struct intel_encoder *encoder,
1637                    struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1640         const struct dp_link_dpll *divisor = NULL;
1641         int i, count = 0;
1642
1643         if (IS_G4X(dev_priv)) {
1644                 divisor = g4x_dpll;
1645                 count = ARRAY_SIZE(g4x_dpll);
1646         } else if (HAS_PCH_SPLIT(dev_priv)) {
1647                 divisor = pch_dpll;
1648                 count = ARRAY_SIZE(pch_dpll);
1649         } else if (IS_CHERRYVIEW(dev_priv)) {
1650                 divisor = chv_dpll;
1651                 count = ARRAY_SIZE(chv_dpll);
1652         } else if (IS_VALLEYVIEW(dev_priv)) {
1653                 divisor = vlv_dpll;
1654                 count = ARRAY_SIZE(vlv_dpll);
1655         }
1656
1657         if (divisor && count) {
1658                 for (i = 0; i < count; i++) {
1659                         if (pipe_config->port_clock == divisor[i].clock) {
1660                                 pipe_config->dpll = divisor[i].dpll;
1661                                 pipe_config->clock_set = true;
1662                                 break;
1663                         }
1664                 }
1665         }
1666 }
1667
1668 static void snprintf_int_array(char *str, size_t len,
1669                                const int *array, int nelem)
1670 {
1671         int i;
1672
1673         str[0] = '\0';
1674
1675         for (i = 0; i < nelem; i++) {
1676                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1677                 if (r >= len)
1678                         return;
1679                 str += r;
1680                 len -= r;
1681         }
1682 }
1683
1684 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1685 {
1686         char str[128]; /* FIXME: too big for stack? */
1687
1688         if ((drm_debug & DRM_UT_KMS) == 0)
1689                 return;
1690
1691         snprintf_int_array(str, sizeof(str),
1692                            intel_dp->source_rates, intel_dp->num_source_rates);
1693         DRM_DEBUG_KMS("source rates: %s\n", str);
1694
1695         snprintf_int_array(str, sizeof(str),
1696                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1697         DRM_DEBUG_KMS("sink rates: %s\n", str);
1698
1699         snprintf_int_array(str, sizeof(str),
1700                            intel_dp->common_rates, intel_dp->num_common_rates);
1701         DRM_DEBUG_KMS("common rates: %s\n", str);
1702 }
1703
1704 int
1705 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1706 {
1707         int len;
1708
1709         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1710         if (WARN_ON(len <= 0))
1711                 return 162000;
1712
1713         return intel_dp->common_rates[len - 1];
1714 }
1715
1716 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1717 {
1718         int i = intel_dp_rate_index(intel_dp->sink_rates,
1719                                     intel_dp->num_sink_rates, rate);
1720
1721         if (WARN_ON(i < 0))
1722                 i = 0;
1723
1724         return i;
1725 }
1726
1727 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1728                            u8 *link_bw, u8 *rate_select)
1729 {
1730         /* eDP 1.4 rate select method. */
1731         if (intel_dp->use_rate_select) {
1732                 *link_bw = 0;
1733                 *rate_select =
1734                         intel_dp_rate_select(intel_dp, port_clock);
1735         } else {
1736                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1737                 *rate_select = 0;
1738         }
1739 }
1740
1741 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1742                                          const struct intel_crtc_state *pipe_config)
1743 {
1744         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1745
1746         /* On TGL, FEC is supported on all Pipes */
1747         if (INTEL_GEN(dev_priv) >= 12)
1748                 return true;
1749
1750         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1751                 return true;
1752
1753         return false;
1754 }
1755
1756 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1757                                   const struct intel_crtc_state *pipe_config)
1758 {
1759         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1760                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1761 }
1762
1763 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1764                                          const struct intel_crtc_state *pipe_config)
1765 {
1766         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1767
1768         /* On TGL, DSC is supported on all Pipes */
1769         if (INTEL_GEN(dev_priv) >= 12)
1770                 return true;
1771
1772         if (INTEL_GEN(dev_priv) >= 10 &&
1773             pipe_config->cpu_transcoder != TRANSCODER_A)
1774                 return true;
1775
1776         return false;
1777 }
1778
1779 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1780                                   const struct intel_crtc_state *pipe_config)
1781 {
1782         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1783                 return false;
1784
1785         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1786                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1787 }
1788
1789 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1790                                 struct intel_crtc_state *pipe_config)
1791 {
1792         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1793         struct intel_connector *intel_connector = intel_dp->attached_connector;
1794         int bpp, bpc;
1795
1796         bpp = pipe_config->pipe_bpp;
1797         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1798
1799         if (bpc > 0)
1800                 bpp = min(bpp, 3*bpc);
1801
1802         if (intel_dp_is_edp(intel_dp)) {
1803                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1804                 if (intel_connector->base.display_info.bpc == 0 &&
1805                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1806                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1807                                       dev_priv->vbt.edp.bpp);
1808                         bpp = dev_priv->vbt.edp.bpp;
1809                 }
1810         }
1811
1812         return bpp;
1813 }
1814
1815 /* Adjust link config limits based on compliance test requests. */
1816 void
1817 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1818                                   struct intel_crtc_state *pipe_config,
1819                                   struct link_config_limits *limits)
1820 {
1821         /* For DP Compliance we override the computed bpp for the pipe */
1822         if (intel_dp->compliance.test_data.bpc != 0) {
1823                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1824
1825                 limits->min_bpp = limits->max_bpp = bpp;
1826                 pipe_config->dither_force_disable = bpp == 6 * 3;
1827
1828                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1829         }
1830
1831         /* Use values requested by Compliance Test Request */
1832         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1833                 int index;
1834
1835                 /* Validate the compliance test data since max values
1836                  * might have changed due to link train fallback.
1837                  */
1838                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1839                                                intel_dp->compliance.test_lane_count)) {
1840                         index = intel_dp_rate_index(intel_dp->common_rates,
1841                                                     intel_dp->num_common_rates,
1842                                                     intel_dp->compliance.test_link_rate);
1843                         if (index >= 0)
1844                                 limits->min_clock = limits->max_clock = index;
1845                         limits->min_lane_count = limits->max_lane_count =
1846                                 intel_dp->compliance.test_lane_count;
1847                 }
1848         }
1849 }
1850
1851 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1852 {
1853         /*
1854          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1855          * format of the number of bytes per pixel will be half the number
1856          * of bytes of RGB pixel.
1857          */
1858         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1859                 bpp /= 2;
1860
1861         return bpp;
1862 }
1863
1864 /* Optimize link config in order: max bpp, min clock, min lanes */
1865 static int
1866 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1867                                   struct intel_crtc_state *pipe_config,
1868                                   const struct link_config_limits *limits)
1869 {
1870         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1871         int bpp, clock, lane_count;
1872         int mode_rate, link_clock, link_avail;
1873
1874         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1875                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
1876
1877                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1878                                                    output_bpp);
1879
1880                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1881                         for (lane_count = limits->min_lane_count;
1882                              lane_count <= limits->max_lane_count;
1883                              lane_count <<= 1) {
1884                                 link_clock = intel_dp->common_rates[clock];
1885                                 link_avail = intel_dp_max_data_rate(link_clock,
1886                                                                     lane_count);
1887
1888                                 if (mode_rate <= link_avail) {
1889                                         pipe_config->lane_count = lane_count;
1890                                         pipe_config->pipe_bpp = bpp;
1891                                         pipe_config->port_clock = link_clock;
1892
1893                                         return 0;
1894                                 }
1895                         }
1896                 }
1897         }
1898
1899         return -EINVAL;
1900 }
1901
1902 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1903 {
1904         int i, num_bpc;
1905         u8 dsc_bpc[3] = {0};
1906
1907         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1908                                                        dsc_bpc);
1909         for (i = 0; i < num_bpc; i++) {
1910                 if (dsc_max_bpc >= dsc_bpc[i])
1911                         return dsc_bpc[i] * 3;
1912         }
1913
1914         return 0;
1915 }
1916
1917 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1918                                        struct intel_crtc_state *pipe_config,
1919                                        struct drm_connector_state *conn_state,
1920                                        struct link_config_limits *limits)
1921 {
1922         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1923         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1924         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1925         u8 dsc_max_bpc;
1926         int pipe_bpp;
1927         int ret;
1928
1929         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1930                 intel_dp_supports_fec(intel_dp, pipe_config);
1931
1932         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1933                 return -EINVAL;
1934
1935         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1936         if (INTEL_GEN(dev_priv) >= 12)
1937                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
1938         else
1939                 dsc_max_bpc = min_t(u8, 10,
1940                                     conn_state->max_requested_bpc);
1941
1942         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1943
1944         /* Min Input BPC for ICL+ is 8 */
1945         if (pipe_bpp < 8 * 3) {
1946                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1947                 return -EINVAL;
1948         }
1949
1950         /*
1951          * For now enable DSC for max bpp, max link rate, max lane count.
1952          * Optimize this later for the minimum possible link rate/lane count
1953          * with DSC enabled for the requested mode.
1954          */
1955         pipe_config->pipe_bpp = pipe_bpp;
1956         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1957         pipe_config->lane_count = limits->max_lane_count;
1958
1959         if (intel_dp_is_edp(intel_dp)) {
1960                 pipe_config->dsc_params.compressed_bpp =
1961                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1962                               pipe_config->pipe_bpp);
1963                 pipe_config->dsc_params.slice_count =
1964                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1965                                                         true);
1966         } else {
1967                 u16 dsc_max_output_bpp;
1968                 u8 dsc_dp_slice_count;
1969
1970                 dsc_max_output_bpp =
1971                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1972                                                     pipe_config->lane_count,
1973                                                     adjusted_mode->crtc_clock,
1974                                                     adjusted_mode->crtc_hdisplay);
1975                 dsc_dp_slice_count =
1976                         intel_dp_dsc_get_slice_count(intel_dp,
1977                                                      adjusted_mode->crtc_clock,
1978                                                      adjusted_mode->crtc_hdisplay);
1979                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1980                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1981                         return -EINVAL;
1982                 }
1983                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1984                                                                dsc_max_output_bpp >> 4,
1985                                                                pipe_config->pipe_bpp);
1986                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1987         }
1988         /*
1989          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1990          * is greater than the maximum Cdclock and if slice count is even
1991          * then we need to use 2 VDSC instances.
1992          */
1993         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1994                 if (pipe_config->dsc_params.slice_count > 1) {
1995                         pipe_config->dsc_params.dsc_split = true;
1996                 } else {
1997                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1998                         return -EINVAL;
1999                 }
2000         }
2001
2002         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
2003         if (ret < 0) {
2004                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
2005                               "Compressed BPP = %d\n",
2006                               pipe_config->pipe_bpp,
2007                               pipe_config->dsc_params.compressed_bpp);
2008                 return ret;
2009         }
2010
2011         pipe_config->dsc_params.compression_enable = true;
2012         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
2013                       "Compressed Bpp = %d Slice Count = %d\n",
2014                       pipe_config->pipe_bpp,
2015                       pipe_config->dsc_params.compressed_bpp,
2016                       pipe_config->dsc_params.slice_count);
2017
2018         return 0;
2019 }
2020
2021 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2022 {
2023         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2024                 return 6 * 3;
2025         else
2026                 return 8 * 3;
2027 }
2028
2029 static int
2030 intel_dp_compute_link_config(struct intel_encoder *encoder,
2031                              struct intel_crtc_state *pipe_config,
2032                              struct drm_connector_state *conn_state)
2033 {
2034         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2035         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2036         struct link_config_limits limits;
2037         int common_len;
2038         int ret;
2039
2040         common_len = intel_dp_common_len_rate_limit(intel_dp,
2041                                                     intel_dp->max_link_rate);
2042
2043         /* No common link rates between source and sink */
2044         WARN_ON(common_len <= 0);
2045
2046         limits.min_clock = 0;
2047         limits.max_clock = common_len - 1;
2048
2049         limits.min_lane_count = 1;
2050         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2051
2052         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2053         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2054
2055         if (intel_dp_is_edp(intel_dp)) {
2056                 /*
2057                  * Use the maximum clock and number of lanes the eDP panel
2058                  * advertizes being capable of. The panels are generally
2059                  * designed to support only a single clock and lane
2060                  * configuration, and typically these values correspond to the
2061                  * native resolution of the panel.
2062                  */
2063                 limits.min_lane_count = limits.max_lane_count;
2064                 limits.min_clock = limits.max_clock;
2065         }
2066
2067         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2068
2069         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2070                       "max rate %d max bpp %d pixel clock %iKHz\n",
2071                       limits.max_lane_count,
2072                       intel_dp->common_rates[limits.max_clock],
2073                       limits.max_bpp, adjusted_mode->crtc_clock);
2074
2075         /*
2076          * Optimize for slow and wide. This is the place to add alternative
2077          * optimization policy.
2078          */
2079         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2080
2081         /* enable compression if the mode doesn't fit available BW */
2082         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2083         if (ret || intel_dp->force_dsc_en) {
2084                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2085                                                   conn_state, &limits);
2086                 if (ret < 0)
2087                         return ret;
2088         }
2089
2090         if (pipe_config->dsc_params.compression_enable) {
2091                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2092                               pipe_config->lane_count, pipe_config->port_clock,
2093                               pipe_config->pipe_bpp,
2094                               pipe_config->dsc_params.compressed_bpp);
2095
2096                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2097                               intel_dp_link_required(adjusted_mode->crtc_clock,
2098                                                      pipe_config->dsc_params.compressed_bpp),
2099                               intel_dp_max_data_rate(pipe_config->port_clock,
2100                                                      pipe_config->lane_count));
2101         } else {
2102                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2103                               pipe_config->lane_count, pipe_config->port_clock,
2104                               pipe_config->pipe_bpp);
2105
2106                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2107                               intel_dp_link_required(adjusted_mode->crtc_clock,
2108                                                      pipe_config->pipe_bpp),
2109                               intel_dp_max_data_rate(pipe_config->port_clock,
2110                                                      pipe_config->lane_count));
2111         }
2112         return 0;
2113 }
2114
2115 static int
2116 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2117                          struct drm_connector *connector,
2118                          struct intel_crtc_state *crtc_state)
2119 {
2120         const struct drm_display_info *info = &connector->display_info;
2121         const struct drm_display_mode *adjusted_mode =
2122                 &crtc_state->base.adjusted_mode;
2123         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2124         int ret;
2125
2126         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2127             !intel_dp_get_colorimetry_status(intel_dp) ||
2128             !connector->ycbcr_420_allowed)
2129                 return 0;
2130
2131         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2132
2133         /* YCBCR 420 output conversion needs a scaler */
2134         ret = skl_update_scaler_crtc(crtc_state);
2135         if (ret) {
2136                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2137                 return ret;
2138         }
2139
2140         intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2141
2142         return 0;
2143 }
2144
2145 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2146                                   const struct drm_connector_state *conn_state)
2147 {
2148         const struct intel_digital_connector_state *intel_conn_state =
2149                 to_intel_digital_connector_state(conn_state);
2150         const struct drm_display_mode *adjusted_mode =
2151                 &crtc_state->base.adjusted_mode;
2152
2153         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2154                 /*
2155                  * See:
2156                  * CEA-861-E - 5.1 Default Encoding Parameters
2157                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2158                  */
2159                 return crtc_state->pipe_bpp != 18 &&
2160                         drm_default_rgb_quant_range(adjusted_mode) ==
2161                         HDMI_QUANTIZATION_RANGE_LIMITED;
2162         } else {
2163                 return intel_conn_state->broadcast_rgb ==
2164                         INTEL_BROADCAST_RGB_LIMITED;
2165         }
2166 }
2167
2168 int
2169 intel_dp_compute_config(struct intel_encoder *encoder,
2170                         struct intel_crtc_state *pipe_config,
2171                         struct drm_connector_state *conn_state)
2172 {
2173         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2174         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2175         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2176         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2177         enum port port = encoder->port;
2178         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2179         struct intel_connector *intel_connector = intel_dp->attached_connector;
2180         struct intel_digital_connector_state *intel_conn_state =
2181                 to_intel_digital_connector_state(conn_state);
2182         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2183                                            DP_DPCD_QUIRK_CONSTANT_N);
2184         int ret = 0, output_bpp;
2185
2186         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2187                 pipe_config->has_pch_encoder = true;
2188
2189         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2190         if (lspcon->active)
2191                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2192         else
2193                 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2194                                                pipe_config);
2195
2196         if (ret)
2197                 return ret;
2198
2199         pipe_config->has_drrs = false;
2200         if (IS_G4X(dev_priv) || port == PORT_A)
2201                 pipe_config->has_audio = false;
2202         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2203                 pipe_config->has_audio = intel_dp->has_audio;
2204         else
2205                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2206
2207         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2208                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2209                                        adjusted_mode);
2210
2211                 if (INTEL_GEN(dev_priv) >= 9) {
2212                         ret = skl_update_scaler_crtc(pipe_config);
2213                         if (ret)
2214                                 return ret;
2215                 }
2216
2217                 if (HAS_GMCH(dev_priv))
2218                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2219                                                  conn_state->scaling_mode);
2220                 else
2221                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2222                                                 conn_state->scaling_mode);
2223         }
2224
2225         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2226                 return -EINVAL;
2227
2228         if (HAS_GMCH(dev_priv) &&
2229             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2230                 return -EINVAL;
2231
2232         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2233                 return -EINVAL;
2234
2235         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2236         if (ret < 0)
2237                 return ret;
2238
2239         pipe_config->limited_color_range =
2240                 intel_dp_limited_color_range(pipe_config, conn_state);
2241
2242         if (pipe_config->dsc_params.compression_enable)
2243                 output_bpp = pipe_config->dsc_params.compressed_bpp;
2244         else
2245                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2246
2247         intel_link_compute_m_n(output_bpp,
2248                                pipe_config->lane_count,
2249                                adjusted_mode->crtc_clock,
2250                                pipe_config->port_clock,
2251                                &pipe_config->dp_m_n,
2252                                constant_n);
2253
2254         if (intel_connector->panel.downclock_mode != NULL &&
2255                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2256                         pipe_config->has_drrs = true;
2257                         intel_link_compute_m_n(output_bpp,
2258                                                pipe_config->lane_count,
2259                                                intel_connector->panel.downclock_mode->clock,
2260                                                pipe_config->port_clock,
2261                                                &pipe_config->dp_m2_n2,
2262                                                constant_n);
2263         }
2264
2265         if (!HAS_DDI(dev_priv))
2266                 intel_dp_set_clock(encoder, pipe_config);
2267
2268         intel_psr_compute_config(intel_dp, pipe_config);
2269
2270         intel_hdcp_transcoder_config(intel_connector,
2271                                      pipe_config->cpu_transcoder);
2272
2273         return 0;
2274 }
2275
2276 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2277                               int link_rate, u8 lane_count,
2278                               bool link_mst)
2279 {
2280         intel_dp->link_trained = false;
2281         intel_dp->link_rate = link_rate;
2282         intel_dp->lane_count = lane_count;
2283         intel_dp->link_mst = link_mst;
2284 }
2285
2286 static void intel_dp_prepare(struct intel_encoder *encoder,
2287                              const struct intel_crtc_state *pipe_config)
2288 {
2289         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2290         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2291         enum port port = encoder->port;
2292         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2293         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2294
2295         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2296                                  pipe_config->lane_count,
2297                                  intel_crtc_has_type(pipe_config,
2298                                                      INTEL_OUTPUT_DP_MST));
2299
2300         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2301         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2302
2303         /*
2304          * There are four kinds of DP registers:
2305          *
2306          *      IBX PCH
2307          *      SNB CPU
2308          *      IVB CPU
2309          *      CPT PCH
2310          *
2311          * IBX PCH and CPU are the same for almost everything,
2312          * except that the CPU DP PLL is configured in this
2313          * register
2314          *
2315          * CPT PCH is quite different, having many bits moved
2316          * to the TRANS_DP_CTL register instead. That
2317          * configuration happens (oddly) in ironlake_pch_enable
2318          */
2319
2320         /* Preserve the BIOS-computed detected bit. This is
2321          * supposed to be read-only.
2322          */
2323         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2324
2325         /* Handle DP bits in common between all three register formats */
2326         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2327         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2328
2329         /* Split out the IBX/CPU vs CPT settings */
2330
2331         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2332                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2333                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2334                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2335                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2336                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2337
2338                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2339                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2340
2341                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2342         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2343                 u32 trans_dp;
2344
2345                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2346
2347                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2348                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2349                         trans_dp |= TRANS_DP_ENH_FRAMING;
2350                 else
2351                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2352                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2353         } else {
2354                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2355                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2356
2357                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2358                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2359                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2360                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2361                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2362
2363                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2364                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2365
2366                 if (IS_CHERRYVIEW(dev_priv))
2367                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2368                 else
2369                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2370         }
2371 }
2372
2373 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2374 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2375
2376 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2377 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2378
2379 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2380 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2381
2382 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2383
2384 static void wait_panel_status(struct intel_dp *intel_dp,
2385                                        u32 mask,
2386                                        u32 value)
2387 {
2388         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2389         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2390
2391         lockdep_assert_held(&dev_priv->pps_mutex);
2392
2393         intel_pps_verify_state(intel_dp);
2394
2395         pp_stat_reg = _pp_stat_reg(intel_dp);
2396         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2397
2398         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2399                         mask, value,
2400                         I915_READ(pp_stat_reg),
2401                         I915_READ(pp_ctrl_reg));
2402
2403         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2404                                        mask, value, 5000))
2405                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2406                                 I915_READ(pp_stat_reg),
2407                                 I915_READ(pp_ctrl_reg));
2408
2409         DRM_DEBUG_KMS("Wait complete\n");
2410 }
2411
2412 static void wait_panel_on(struct intel_dp *intel_dp)
2413 {
2414         DRM_DEBUG_KMS("Wait for panel power on\n");
2415         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2416 }
2417
2418 static void wait_panel_off(struct intel_dp *intel_dp)
2419 {
2420         DRM_DEBUG_KMS("Wait for panel power off time\n");
2421         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2422 }
2423
2424 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2425 {
2426         ktime_t panel_power_on_time;
2427         s64 panel_power_off_duration;
2428
2429         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2430
2431         /* take the difference of currrent time and panel power off time
2432          * and then make panel wait for t11_t12 if needed. */
2433         panel_power_on_time = ktime_get_boottime();
2434         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2435
2436         /* When we disable the VDD override bit last we have to do the manual
2437          * wait. */
2438         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2439                 wait_remaining_ms_from_jiffies(jiffies,
2440                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2441
2442         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2443 }
2444
2445 static void wait_backlight_on(struct intel_dp *intel_dp)
2446 {
2447         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2448                                        intel_dp->backlight_on_delay);
2449 }
2450
2451 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2452 {
2453         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2454                                        intel_dp->backlight_off_delay);
2455 }
2456
2457 /* Read the current pp_control value, unlocking the register if it
2458  * is locked
2459  */
2460
2461 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2462 {
2463         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2464         u32 control;
2465
2466         lockdep_assert_held(&dev_priv->pps_mutex);
2467
2468         control = I915_READ(_pp_ctrl_reg(intel_dp));
2469         if (WARN_ON(!HAS_DDI(dev_priv) &&
2470                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2471                 control &= ~PANEL_UNLOCK_MASK;
2472                 control |= PANEL_UNLOCK_REGS;
2473         }
2474         return control;
2475 }
2476
2477 /*
2478  * Must be paired with edp_panel_vdd_off().
2479  * Must hold pps_mutex around the whole on/off sequence.
2480  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2481  */
2482 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2483 {
2484         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2485         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2486         u32 pp;
2487         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2488         bool need_to_disable = !intel_dp->want_panel_vdd;
2489
2490         lockdep_assert_held(&dev_priv->pps_mutex);
2491
2492         if (!intel_dp_is_edp(intel_dp))
2493                 return false;
2494
2495         cancel_delayed_work(&intel_dp->panel_vdd_work);
2496         intel_dp->want_panel_vdd = true;
2497
2498         if (edp_have_panel_vdd(intel_dp))
2499                 return need_to_disable;
2500
2501         intel_display_power_get(dev_priv,
2502                                 intel_aux_power_domain(intel_dig_port));
2503
2504         DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n",
2505                       intel_dig_port->base.base.base.id,
2506                       intel_dig_port->base.base.name);
2507
2508         if (!edp_have_panel_power(intel_dp))
2509                 wait_panel_power_cycle(intel_dp);
2510
2511         pp = ironlake_get_pp_control(intel_dp);
2512         pp |= EDP_FORCE_VDD;
2513
2514         pp_stat_reg = _pp_stat_reg(intel_dp);
2515         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2516
2517         I915_WRITE(pp_ctrl_reg, pp);
2518         POSTING_READ(pp_ctrl_reg);
2519         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2520                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2521         /*
2522          * If the panel wasn't on, delay before accessing aux channel
2523          */
2524         if (!edp_have_panel_power(intel_dp)) {
2525                 DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n",
2526                               intel_dig_port->base.base.base.id,
2527                               intel_dig_port->base.base.name);
2528                 msleep(intel_dp->panel_power_up_delay);
2529         }
2530
2531         return need_to_disable;
2532 }
2533
2534 /*
2535  * Must be paired with intel_edp_panel_vdd_off() or
2536  * intel_edp_panel_off().
2537  * Nested calls to these functions are not allowed since
2538  * we drop the lock. Caller must use some higher level
2539  * locking to prevent nested calls from other threads.
2540  */
2541 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2542 {
2543         intel_wakeref_t wakeref;
2544         bool vdd;
2545
2546         if (!intel_dp_is_edp(intel_dp))
2547                 return;
2548
2549         vdd = false;
2550         with_pps_lock(intel_dp, wakeref)
2551                 vdd = edp_panel_vdd_on(intel_dp);
2552         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2553                         dp_to_dig_port(intel_dp)->base.base.base.id,
2554                         dp_to_dig_port(intel_dp)->base.base.name);
2555 }
2556
2557 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2558 {
2559         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2560         struct intel_digital_port *intel_dig_port =
2561                 dp_to_dig_port(intel_dp);
2562         u32 pp;
2563         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2564
2565         lockdep_assert_held(&dev_priv->pps_mutex);
2566
2567         WARN_ON(intel_dp->want_panel_vdd);
2568
2569         if (!edp_have_panel_vdd(intel_dp))
2570                 return;
2571
2572         DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n",
2573                       intel_dig_port->base.base.base.id,
2574                       intel_dig_port->base.base.name);
2575
2576         pp = ironlake_get_pp_control(intel_dp);
2577         pp &= ~EDP_FORCE_VDD;
2578
2579         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2580         pp_stat_reg = _pp_stat_reg(intel_dp);
2581
2582         I915_WRITE(pp_ctrl_reg, pp);
2583         POSTING_READ(pp_ctrl_reg);
2584
2585         /* Make sure sequencer is idle before allowing subsequent activity */
2586         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2587         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2588
2589         if ((pp & PANEL_POWER_ON) == 0)
2590                 intel_dp->panel_power_off_time = ktime_get_boottime();
2591
2592         intel_display_power_put_unchecked(dev_priv,
2593                                           intel_aux_power_domain(intel_dig_port));
2594 }
2595
2596 static void edp_panel_vdd_work(struct work_struct *__work)
2597 {
2598         struct intel_dp *intel_dp =
2599                 container_of(to_delayed_work(__work),
2600                              struct intel_dp, panel_vdd_work);
2601         intel_wakeref_t wakeref;
2602
2603         with_pps_lock(intel_dp, wakeref) {
2604                 if (!intel_dp->want_panel_vdd)
2605                         edp_panel_vdd_off_sync(intel_dp);
2606         }
2607 }
2608
2609 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2610 {
2611         unsigned long delay;
2612
2613         /*
2614          * Queue the timer to fire a long time from now (relative to the power
2615          * down delay) to keep the panel power up across a sequence of
2616          * operations.
2617          */
2618         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2619         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2620 }
2621
2622 /*
2623  * Must be paired with edp_panel_vdd_on().
2624  * Must hold pps_mutex around the whole on/off sequence.
2625  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2626  */
2627 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2628 {
2629         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2630
2631         lockdep_assert_held(&dev_priv->pps_mutex);
2632
2633         if (!intel_dp_is_edp(intel_dp))
2634                 return;
2635
2636         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
2637                         dp_to_dig_port(intel_dp)->base.base.base.id,
2638                         dp_to_dig_port(intel_dp)->base.base.name);
2639
2640         intel_dp->want_panel_vdd = false;
2641
2642         if (sync)
2643                 edp_panel_vdd_off_sync(intel_dp);
2644         else
2645                 edp_panel_vdd_schedule_off(intel_dp);
2646 }
2647
2648 static void edp_panel_on(struct intel_dp *intel_dp)
2649 {
2650         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2651         u32 pp;
2652         i915_reg_t pp_ctrl_reg;
2653
2654         lockdep_assert_held(&dev_priv->pps_mutex);
2655
2656         if (!intel_dp_is_edp(intel_dp))
2657                 return;
2658
2659         DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n",
2660                       dp_to_dig_port(intel_dp)->base.base.base.id,
2661                       dp_to_dig_port(intel_dp)->base.base.name);
2662
2663         if (WARN(edp_have_panel_power(intel_dp),
2664                  "[ENCODER:%d:%s] panel power already on\n",
2665                  dp_to_dig_port(intel_dp)->base.base.base.id,
2666                  dp_to_dig_port(intel_dp)->base.base.name))
2667                 return;
2668
2669         wait_panel_power_cycle(intel_dp);
2670
2671         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2672         pp = ironlake_get_pp_control(intel_dp);
2673         if (IS_GEN(dev_priv, 5)) {
2674                 /* ILK workaround: disable reset around power sequence */
2675                 pp &= ~PANEL_POWER_RESET;
2676                 I915_WRITE(pp_ctrl_reg, pp);
2677                 POSTING_READ(pp_ctrl_reg);
2678         }
2679
2680         pp |= PANEL_POWER_ON;
2681         if (!IS_GEN(dev_priv, 5))
2682                 pp |= PANEL_POWER_RESET;
2683
2684         I915_WRITE(pp_ctrl_reg, pp);
2685         POSTING_READ(pp_ctrl_reg);
2686
2687         wait_panel_on(intel_dp);
2688         intel_dp->last_power_on = jiffies;
2689
2690         if (IS_GEN(dev_priv, 5)) {
2691                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2692                 I915_WRITE(pp_ctrl_reg, pp);
2693                 POSTING_READ(pp_ctrl_reg);
2694         }
2695 }
2696
2697 void intel_edp_panel_on(struct intel_dp *intel_dp)
2698 {
2699         intel_wakeref_t wakeref;
2700
2701         if (!intel_dp_is_edp(intel_dp))
2702                 return;
2703
2704         with_pps_lock(intel_dp, wakeref)
2705                 edp_panel_on(intel_dp);
2706 }
2707
2708
2709 static void edp_panel_off(struct intel_dp *intel_dp)
2710 {
2711         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2712         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2713         u32 pp;
2714         i915_reg_t pp_ctrl_reg;
2715
2716         lockdep_assert_held(&dev_priv->pps_mutex);
2717
2718         if (!intel_dp_is_edp(intel_dp))
2719                 return;
2720
2721         DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n",
2722                       dig_port->base.base.base.id, dig_port->base.base.name);
2723
2724         WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",
2725              dig_port->base.base.base.id, dig_port->base.base.name);
2726
2727         pp = ironlake_get_pp_control(intel_dp);
2728         /* We need to switch off panel power _and_ force vdd, for otherwise some
2729          * panels get very unhappy and cease to work. */
2730         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2731                 EDP_BLC_ENABLE);
2732
2733         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2734
2735         intel_dp->want_panel_vdd = false;
2736
2737         I915_WRITE(pp_ctrl_reg, pp);
2738         POSTING_READ(pp_ctrl_reg);
2739
2740         wait_panel_off(intel_dp);
2741         intel_dp->panel_power_off_time = ktime_get_boottime();
2742
2743         /* We got a reference when we enabled the VDD. */
2744         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2745 }
2746
2747 void intel_edp_panel_off(struct intel_dp *intel_dp)
2748 {
2749         intel_wakeref_t wakeref;
2750
2751         if (!intel_dp_is_edp(intel_dp))
2752                 return;
2753
2754         with_pps_lock(intel_dp, wakeref)
2755                 edp_panel_off(intel_dp);
2756 }
2757
2758 /* Enable backlight in the panel power control. */
2759 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2760 {
2761         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2762         intel_wakeref_t wakeref;
2763
2764         /*
2765          * If we enable the backlight right away following a panel power
2766          * on, we may see slight flicker as the panel syncs with the eDP
2767          * link.  So delay a bit to make sure the image is solid before
2768          * allowing it to appear.
2769          */
2770         wait_backlight_on(intel_dp);
2771
2772         with_pps_lock(intel_dp, wakeref) {
2773                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2774                 u32 pp;
2775
2776                 pp = ironlake_get_pp_control(intel_dp);
2777                 pp |= EDP_BLC_ENABLE;
2778
2779                 I915_WRITE(pp_ctrl_reg, pp);
2780                 POSTING_READ(pp_ctrl_reg);
2781         }
2782 }
2783
2784 /* Enable backlight PWM and backlight PP control. */
2785 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2786                             const struct drm_connector_state *conn_state)
2787 {
2788         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2789
2790         if (!intel_dp_is_edp(intel_dp))
2791                 return;
2792
2793         DRM_DEBUG_KMS("\n");
2794
2795         intel_panel_enable_backlight(crtc_state, conn_state);
2796         _intel_edp_backlight_on(intel_dp);
2797 }
2798
2799 /* Disable backlight in the panel power control. */
2800 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2801 {
2802         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2803         intel_wakeref_t wakeref;
2804
2805         if (!intel_dp_is_edp(intel_dp))
2806                 return;
2807
2808         with_pps_lock(intel_dp, wakeref) {
2809                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2810                 u32 pp;
2811
2812                 pp = ironlake_get_pp_control(intel_dp);
2813                 pp &= ~EDP_BLC_ENABLE;
2814
2815                 I915_WRITE(pp_ctrl_reg, pp);
2816                 POSTING_READ(pp_ctrl_reg);
2817         }
2818
2819         intel_dp->last_backlight_off = jiffies;
2820         edp_wait_backlight_off(intel_dp);
2821 }
2822
2823 /* Disable backlight PP control and backlight PWM. */
2824 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2825 {
2826         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2827
2828         if (!intel_dp_is_edp(intel_dp))
2829                 return;
2830
2831         DRM_DEBUG_KMS("\n");
2832
2833         _intel_edp_backlight_off(intel_dp);
2834         intel_panel_disable_backlight(old_conn_state);
2835 }
2836
2837 /*
2838  * Hook for controlling the panel power control backlight through the bl_power
2839  * sysfs attribute. Take care to handle multiple calls.
2840  */
2841 static void intel_edp_backlight_power(struct intel_connector *connector,
2842                                       bool enable)
2843 {
2844         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2845         intel_wakeref_t wakeref;
2846         bool is_enabled;
2847
2848         is_enabled = false;
2849         with_pps_lock(intel_dp, wakeref)
2850                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2851         if (is_enabled == enable)
2852                 return;
2853
2854         DRM_DEBUG_KMS("panel power control backlight %s\n",
2855                       enable ? "enable" : "disable");
2856
2857         if (enable)
2858                 _intel_edp_backlight_on(intel_dp);
2859         else
2860                 _intel_edp_backlight_off(intel_dp);
2861 }
2862
2863 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2864 {
2865         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2866         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2867         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2868
2869         I915_STATE_WARN(cur_state != state,
2870                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
2871                         dig_port->base.base.base.id, dig_port->base.base.name,
2872                         onoff(state), onoff(cur_state));
2873 }
2874 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2875
2876 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2877 {
2878         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2879
2880         I915_STATE_WARN(cur_state != state,
2881                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2882                         onoff(state), onoff(cur_state));
2883 }
2884 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2885 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2886
2887 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2888                                 const struct intel_crtc_state *pipe_config)
2889 {
2890         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2891         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2892
2893         assert_pipe_disabled(dev_priv, crtc->pipe);
2894         assert_dp_port_disabled(intel_dp);
2895         assert_edp_pll_disabled(dev_priv);
2896
2897         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2898                       pipe_config->port_clock);
2899
2900         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2901
2902         if (pipe_config->port_clock == 162000)
2903                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2904         else
2905                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2906
2907         I915_WRITE(DP_A, intel_dp->DP);
2908         POSTING_READ(DP_A);
2909         udelay(500);
2910
2911         /*
2912          * [DevILK] Work around required when enabling DP PLL
2913          * while a pipe is enabled going to FDI:
2914          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2915          * 2. Program DP PLL enable
2916          */
2917         if (IS_GEN(dev_priv, 5))
2918                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2919
2920         intel_dp->DP |= DP_PLL_ENABLE;
2921
2922         I915_WRITE(DP_A, intel_dp->DP);
2923         POSTING_READ(DP_A);
2924         udelay(200);
2925 }
2926
2927 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2928                                  const struct intel_crtc_state *old_crtc_state)
2929 {
2930         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2931         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2932
2933         assert_pipe_disabled(dev_priv, crtc->pipe);
2934         assert_dp_port_disabled(intel_dp);
2935         assert_edp_pll_enabled(dev_priv);
2936
2937         DRM_DEBUG_KMS("disabling eDP PLL\n");
2938
2939         intel_dp->DP &= ~DP_PLL_ENABLE;
2940
2941         I915_WRITE(DP_A, intel_dp->DP);
2942         POSTING_READ(DP_A);
2943         udelay(200);
2944 }
2945
2946 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2947 {
2948         /*
2949          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2950          * be capable of signalling downstream hpd with a long pulse.
2951          * Whether or not that means D3 is safe to use is not clear,
2952          * but let's assume so until proven otherwise.
2953          *
2954          * FIXME should really check all downstream ports...
2955          */
2956         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2957                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2958                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2959 }
2960
2961 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2962                                            const struct intel_crtc_state *crtc_state,
2963                                            bool enable)
2964 {
2965         int ret;
2966
2967         if (!crtc_state->dsc_params.compression_enable)
2968                 return;
2969
2970         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2971                                  enable ? DP_DECOMPRESSION_EN : 0);
2972         if (ret < 0)
2973                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2974                               enable ? "enable" : "disable");
2975 }
2976
2977 /* If the sink supports it, try to set the power state appropriately */
2978 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2979 {
2980         int ret, i;
2981
2982         /* Should have a valid DPCD by this point */
2983         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2984                 return;
2985
2986         if (mode != DRM_MODE_DPMS_ON) {
2987                 if (downstream_hpd_needs_d0(intel_dp))
2988                         return;
2989
2990                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2991                                          DP_SET_POWER_D3);
2992         } else {
2993                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2994
2995                 /*
2996                  * When turning on, we need to retry for 1ms to give the sink
2997                  * time to wake up.
2998                  */
2999                 for (i = 0; i < 3; i++) {
3000                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3001                                                  DP_SET_POWER_D0);
3002                         if (ret == 1)
3003                                 break;
3004                         msleep(1);
3005                 }
3006
3007                 if (ret == 1 && lspcon->active)
3008                         lspcon_wait_pcon_mode(lspcon);
3009         }
3010
3011         if (ret != 1)
3012                 DRM_DEBUG_KMS("failed to %s sink power state\n",
3013                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3014 }
3015
3016 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3017                                  enum port port, enum pipe *pipe)
3018 {
3019         enum pipe p;
3020
3021         for_each_pipe(dev_priv, p) {
3022                 u32 val = I915_READ(TRANS_DP_CTL(p));
3023
3024                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3025                         *pipe = p;
3026                         return true;
3027                 }
3028         }
3029
3030         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
3031
3032         /* must initialize pipe to something for the asserts */
3033         *pipe = PIPE_A;
3034
3035         return false;
3036 }
3037
3038 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3039                            i915_reg_t dp_reg, enum port port,
3040                            enum pipe *pipe)
3041 {
3042         bool ret;
3043         u32 val;
3044
3045         val = I915_READ(dp_reg);
3046
3047         ret = val & DP_PORT_EN;
3048
3049         /* asserts want to know the pipe even if the port is disabled */
3050         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3051                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3052         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3053                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3054         else if (IS_CHERRYVIEW(dev_priv))
3055                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3056         else
3057                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3058
3059         return ret;
3060 }
3061
3062 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3063                                   enum pipe *pipe)
3064 {
3065         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3066         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3067         intel_wakeref_t wakeref;
3068         bool ret;
3069
3070         wakeref = intel_display_power_get_if_enabled(dev_priv,
3071                                                      encoder->power_domain);
3072         if (!wakeref)
3073                 return false;
3074
3075         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3076                                     encoder->port, pipe);
3077
3078         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3079
3080         return ret;
3081 }
3082
3083 static void intel_dp_get_config(struct intel_encoder *encoder,
3084                                 struct intel_crtc_state *pipe_config)
3085 {
3086         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3087         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3088         u32 tmp, flags = 0;
3089         enum port port = encoder->port;
3090         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3091
3092         if (encoder->type == INTEL_OUTPUT_EDP)
3093                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3094         else
3095                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3096
3097         tmp = I915_READ(intel_dp->output_reg);
3098
3099         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3100
3101         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3102                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3103
3104                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3105                         flags |= DRM_MODE_FLAG_PHSYNC;
3106                 else
3107                         flags |= DRM_MODE_FLAG_NHSYNC;
3108
3109                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3110                         flags |= DRM_MODE_FLAG_PVSYNC;
3111                 else
3112                         flags |= DRM_MODE_FLAG_NVSYNC;
3113         } else {
3114                 if (tmp & DP_SYNC_HS_HIGH)
3115                         flags |= DRM_MODE_FLAG_PHSYNC;
3116                 else
3117                         flags |= DRM_MODE_FLAG_NHSYNC;
3118
3119                 if (tmp & DP_SYNC_VS_HIGH)
3120                         flags |= DRM_MODE_FLAG_PVSYNC;
3121                 else
3122                         flags |= DRM_MODE_FLAG_NVSYNC;
3123         }
3124
3125         pipe_config->base.adjusted_mode.flags |= flags;
3126
3127         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3128                 pipe_config->limited_color_range = true;
3129
3130         pipe_config->lane_count =
3131                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3132
3133         intel_dp_get_m_n(crtc, pipe_config);
3134
3135         if (port == PORT_A) {
3136                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3137                         pipe_config->port_clock = 162000;
3138                 else
3139                         pipe_config->port_clock = 270000;
3140         }
3141
3142         pipe_config->base.adjusted_mode.crtc_clock =
3143                 intel_dotclock_calculate(pipe_config->port_clock,
3144                                          &pipe_config->dp_m_n);
3145
3146         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3147             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3148                 /*
3149                  * This is a big fat ugly hack.
3150                  *
3151                  * Some machines in UEFI boot mode provide us a VBT that has 18
3152                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3153                  * unknown we fail to light up. Yet the same BIOS boots up with
3154                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3155                  * max, not what it tells us to use.
3156                  *
3157                  * Note: This will still be broken if the eDP panel is not lit
3158                  * up by the BIOS, and thus we can't get the mode at module
3159                  * load.
3160                  */
3161                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3162                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3163                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3164         }
3165 }
3166
3167 static void intel_disable_dp(struct intel_encoder *encoder,
3168                              const struct intel_crtc_state *old_crtc_state,
3169                              const struct drm_connector_state *old_conn_state)
3170 {
3171         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3172
3173         intel_dp->link_trained = false;
3174
3175         if (old_crtc_state->has_audio)
3176                 intel_audio_codec_disable(encoder,
3177                                           old_crtc_state, old_conn_state);
3178
3179         /* Make sure the panel is off before trying to change the mode. But also
3180          * ensure that we have vdd while we switch off the panel. */
3181         intel_edp_panel_vdd_on(intel_dp);
3182         intel_edp_backlight_off(old_conn_state);
3183         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3184         intel_edp_panel_off(intel_dp);
3185 }
3186
3187 static void g4x_disable_dp(struct intel_encoder *encoder,
3188                            const struct intel_crtc_state *old_crtc_state,
3189                            const struct drm_connector_state *old_conn_state)
3190 {
3191         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3192 }
3193
3194 static void vlv_disable_dp(struct intel_encoder *encoder,
3195                            const struct intel_crtc_state *old_crtc_state,
3196                            const struct drm_connector_state *old_conn_state)
3197 {
3198         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3199 }
3200
3201 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3202                                 const struct intel_crtc_state *old_crtc_state,
3203                                 const struct drm_connector_state *old_conn_state)
3204 {
3205         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3206         enum port port = encoder->port;
3207
3208         /*
3209          * Bspec does not list a specific disable sequence for g4x DP.
3210          * Follow the ilk+ sequence (disable pipe before the port) for
3211          * g4x DP as it does not suffer from underruns like the normal
3212          * g4x modeset sequence (disable pipe after the port).
3213          */
3214         intel_dp_link_down(encoder, old_crtc_state);
3215
3216         /* Only ilk+ has port A */
3217         if (port == PORT_A)
3218                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3219 }
3220
3221 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3222                                 const struct intel_crtc_state *old_crtc_state,
3223                                 const struct drm_connector_state *old_conn_state)
3224 {
3225         intel_dp_link_down(encoder, old_crtc_state);
3226 }
3227
3228 static void chv_post_disable_dp(struct intel_encoder *encoder,
3229                                 const struct intel_crtc_state *old_crtc_state,
3230                                 const struct drm_connector_state *old_conn_state)
3231 {
3232         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3233
3234         intel_dp_link_down(encoder, old_crtc_state);
3235
3236         vlv_dpio_get(dev_priv);
3237
3238         /* Assert data lane reset */
3239         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3240
3241         vlv_dpio_put(dev_priv);
3242 }
3243
3244 static void
3245 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3246                          u32 *DP,
3247                          u8 dp_train_pat)
3248 {
3249         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3250         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3251         enum port port = intel_dig_port->base.port;
3252         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3253
3254         if (dp_train_pat & train_pat_mask)
3255                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3256                               dp_train_pat & train_pat_mask);
3257
3258         if (HAS_DDI(dev_priv)) {
3259                 u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
3260
3261                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3262                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3263                 else
3264                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3265
3266                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3267                 switch (dp_train_pat & train_pat_mask) {
3268                 case DP_TRAINING_PATTERN_DISABLE:
3269                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3270
3271                         break;
3272                 case DP_TRAINING_PATTERN_1:
3273                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3274                         break;
3275                 case DP_TRAINING_PATTERN_2:
3276                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3277                         break;
3278                 case DP_TRAINING_PATTERN_3:
3279                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3280                         break;
3281                 case DP_TRAINING_PATTERN_4:
3282                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3283                         break;
3284                 }
3285                 I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
3286
3287         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3288                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3289                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3290
3291                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3292                 case DP_TRAINING_PATTERN_DISABLE:
3293                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3294                         break;
3295                 case DP_TRAINING_PATTERN_1:
3296                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3297                         break;
3298                 case DP_TRAINING_PATTERN_2:
3299                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3300                         break;
3301                 case DP_TRAINING_PATTERN_3:
3302                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3303                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3304                         break;
3305                 }
3306
3307         } else {
3308                 *DP &= ~DP_LINK_TRAIN_MASK;
3309
3310                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3311                 case DP_TRAINING_PATTERN_DISABLE:
3312                         *DP |= DP_LINK_TRAIN_OFF;
3313                         break;
3314                 case DP_TRAINING_PATTERN_1:
3315                         *DP |= DP_LINK_TRAIN_PAT_1;
3316                         break;
3317                 case DP_TRAINING_PATTERN_2:
3318                         *DP |= DP_LINK_TRAIN_PAT_2;
3319                         break;
3320                 case DP_TRAINING_PATTERN_3:
3321                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3322                         *DP |= DP_LINK_TRAIN_PAT_2;
3323                         break;
3324                 }
3325         }
3326 }
3327
3328 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3329                                  const struct intel_crtc_state *old_crtc_state)
3330 {
3331         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3332
3333         /* enable with pattern 1 (as per spec) */
3334
3335         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3336
3337         /*
3338          * Magic for VLV/CHV. We _must_ first set up the register
3339          * without actually enabling the port, and then do another
3340          * write to enable the port. Otherwise link training will
3341          * fail when the power sequencer is freshly used for this port.
3342          */
3343         intel_dp->DP |= DP_PORT_EN;
3344         if (old_crtc_state->has_audio)
3345                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3346
3347         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3348         POSTING_READ(intel_dp->output_reg);
3349 }
3350
3351 static void intel_enable_dp(struct intel_encoder *encoder,
3352                             const struct intel_crtc_state *pipe_config,
3353                             const struct drm_connector_state *conn_state)
3354 {
3355         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3356         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3357         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3358         u32 dp_reg = I915_READ(intel_dp->output_reg);
3359         enum pipe pipe = crtc->pipe;
3360         intel_wakeref_t wakeref;
3361
3362         if (WARN_ON(dp_reg & DP_PORT_EN))
3363                 return;
3364
3365         with_pps_lock(intel_dp, wakeref) {
3366                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3367                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3368
3369                 intel_dp_enable_port(intel_dp, pipe_config);
3370
3371                 edp_panel_vdd_on(intel_dp);
3372                 edp_panel_on(intel_dp);
3373                 edp_panel_vdd_off(intel_dp, true);
3374         }
3375
3376         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3377                 unsigned int lane_mask = 0x0;
3378
3379                 if (IS_CHERRYVIEW(dev_priv))
3380                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3381
3382                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3383                                     lane_mask);
3384         }
3385
3386         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3387         intel_dp_start_link_train(intel_dp);
3388         intel_dp_stop_link_train(intel_dp);
3389
3390         if (pipe_config->has_audio) {
3391                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3392                                  pipe_name(pipe));
3393                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3394         }
3395 }
3396
3397 static void g4x_enable_dp(struct intel_encoder *encoder,
3398                           const struct intel_crtc_state *pipe_config,
3399                           const struct drm_connector_state *conn_state)
3400 {
3401         intel_enable_dp(encoder, pipe_config, conn_state);
3402         intel_edp_backlight_on(pipe_config, conn_state);
3403 }
3404
3405 static void vlv_enable_dp(struct intel_encoder *encoder,
3406                           const struct intel_crtc_state *pipe_config,
3407                           const struct drm_connector_state *conn_state)
3408 {
3409         intel_edp_backlight_on(pipe_config, conn_state);
3410 }
3411
3412 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3413                               const struct intel_crtc_state *pipe_config,
3414                               const struct drm_connector_state *conn_state)
3415 {
3416         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3417         enum port port = encoder->port;
3418
3419         intel_dp_prepare(encoder, pipe_config);
3420
3421         /* Only ilk+ has port A */
3422         if (port == PORT_A)
3423                 ironlake_edp_pll_on(intel_dp, pipe_config);
3424 }
3425
3426 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3427 {
3428         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3429         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3430         enum pipe pipe = intel_dp->pps_pipe;
3431         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3432
3433         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3434
3435         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3436                 return;
3437
3438         edp_panel_vdd_off_sync(intel_dp);
3439
3440         /*
3441          * VLV seems to get confused when multiple power sequencers
3442          * have the same port selected (even if only one has power/vdd
3443          * enabled). The failure manifests as vlv_wait_port_ready() failing
3444          * CHV on the other hand doesn't seem to mind having the same port
3445          * selected in multiple power sequencers, but let's clear the
3446          * port select always when logically disconnecting a power sequencer
3447          * from a port.
3448          */
3449         DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3450                       pipe_name(pipe), intel_dig_port->base.base.base.id,
3451                       intel_dig_port->base.base.name);
3452         I915_WRITE(pp_on_reg, 0);
3453         POSTING_READ(pp_on_reg);
3454
3455         intel_dp->pps_pipe = INVALID_PIPE;
3456 }
3457
3458 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3459                                       enum pipe pipe)
3460 {
3461         struct intel_encoder *encoder;
3462
3463         lockdep_assert_held(&dev_priv->pps_mutex);
3464
3465         for_each_intel_dp(&dev_priv->drm, encoder) {
3466                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3467
3468                 WARN(intel_dp->active_pipe == pipe,
3469                      "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3470                      pipe_name(pipe), encoder->base.base.id,
3471                      encoder->base.name);
3472
3473                 if (intel_dp->pps_pipe != pipe)
3474                         continue;
3475
3476                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3477                               pipe_name(pipe), encoder->base.base.id,
3478                               encoder->base.name);
3479
3480                 /* make sure vdd is off before we steal it */
3481                 vlv_detach_power_sequencer(intel_dp);
3482         }
3483 }
3484
3485 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3486                                            const struct intel_crtc_state *crtc_state)
3487 {
3488         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3489         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3490         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3491
3492         lockdep_assert_held(&dev_priv->pps_mutex);
3493
3494         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3495
3496         if (intel_dp->pps_pipe != INVALID_PIPE &&
3497             intel_dp->pps_pipe != crtc->pipe) {
3498                 /*
3499                  * If another power sequencer was being used on this
3500                  * port previously make sure to turn off vdd there while
3501                  * we still have control of it.
3502                  */
3503                 vlv_detach_power_sequencer(intel_dp);
3504         }
3505
3506         /*
3507          * We may be stealing the power
3508          * sequencer from another port.
3509          */
3510         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3511
3512         intel_dp->active_pipe = crtc->pipe;
3513
3514         if (!intel_dp_is_edp(intel_dp))
3515                 return;
3516
3517         /* now it's all ours */
3518         intel_dp->pps_pipe = crtc->pipe;
3519
3520         DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3521                       pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3522                       encoder->base.name);
3523
3524         /* init power sequencer on this pipe and port */
3525         intel_dp_init_panel_power_sequencer(intel_dp);
3526         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3527 }
3528
3529 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3530                               const struct intel_crtc_state *pipe_config,
3531                               const struct drm_connector_state *conn_state)
3532 {
3533         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3534
3535         intel_enable_dp(encoder, pipe_config, conn_state);
3536 }
3537
3538 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3539                                   const struct intel_crtc_state *pipe_config,
3540                                   const struct drm_connector_state *conn_state)
3541 {
3542         intel_dp_prepare(encoder, pipe_config);
3543
3544         vlv_phy_pre_pll_enable(encoder, pipe_config);
3545 }
3546
3547 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3548                               const struct intel_crtc_state *pipe_config,
3549                               const struct drm_connector_state *conn_state)
3550 {
3551         chv_phy_pre_encoder_enable(encoder, pipe_config);
3552
3553         intel_enable_dp(encoder, pipe_config, conn_state);
3554
3555         /* Second common lane will stay alive on its own now */
3556         chv_phy_release_cl2_override(encoder);
3557 }
3558
3559 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3560                                   const struct intel_crtc_state *pipe_config,
3561                                   const struct drm_connector_state *conn_state)
3562 {
3563         intel_dp_prepare(encoder, pipe_config);
3564
3565         chv_phy_pre_pll_enable(encoder, pipe_config);
3566 }
3567
3568 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3569                                     const struct intel_crtc_state *old_crtc_state,
3570                                     const struct drm_connector_state *old_conn_state)
3571 {
3572         chv_phy_post_pll_disable(encoder, old_crtc_state);
3573 }
3574
3575 /*
3576  * Fetch AUX CH registers 0x202 - 0x207 which contain
3577  * link status information
3578  */
3579 bool
3580 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3581 {
3582         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3583                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3584 }
3585
3586 /* These are source-specific values. */
3587 u8
3588 intel_dp_voltage_max(struct intel_dp *intel_dp)
3589 {
3590         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3591         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3592         enum port port = encoder->port;
3593
3594         if (HAS_DDI(dev_priv))
3595                 return intel_ddi_dp_voltage_max(encoder);
3596         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3597                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3598         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3599                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3600         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3601                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3602         else
3603                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3604 }
3605
3606 u8
3607 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3608 {
3609         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3610         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3611         enum port port = encoder->port;
3612
3613         if (HAS_DDI(dev_priv)) {
3614                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3615         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3616                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3617                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3618                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3619                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3620                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3621                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3622                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3623                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3624                 default:
3625                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3626                 }
3627         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3628                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3629                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3630                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3631                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3632                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3633                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3634                 default:
3635                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3636                 }
3637         } else {
3638                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3639                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3640                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3641                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3642                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3643                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3644                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3645                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3646                 default:
3647                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3648                 }
3649         }
3650 }
3651
3652 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3653 {
3654         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3655         unsigned long demph_reg_value, preemph_reg_value,
3656                 uniqtranscale_reg_value;
3657         u8 train_set = intel_dp->train_set[0];
3658
3659         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3660         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3661                 preemph_reg_value = 0x0004000;
3662                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3663                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3664                         demph_reg_value = 0x2B405555;
3665                         uniqtranscale_reg_value = 0x552AB83A;
3666                         break;
3667                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3668                         demph_reg_value = 0x2B404040;
3669                         uniqtranscale_reg_value = 0x5548B83A;
3670                         break;
3671                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3672                         demph_reg_value = 0x2B245555;
3673                         uniqtranscale_reg_value = 0x5560B83A;
3674                         break;
3675                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3676                         demph_reg_value = 0x2B405555;
3677                         uniqtranscale_reg_value = 0x5598DA3A;
3678                         break;
3679                 default:
3680                         return 0;
3681                 }
3682                 break;
3683         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3684                 preemph_reg_value = 0x0002000;
3685                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3686                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3687                         demph_reg_value = 0x2B404040;
3688                         uniqtranscale_reg_value = 0x5552B83A;
3689                         break;
3690                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3691                         demph_reg_value = 0x2B404848;
3692                         uniqtranscale_reg_value = 0x5580B83A;
3693                         break;
3694                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3695                         demph_reg_value = 0x2B404040;
3696                         uniqtranscale_reg_value = 0x55ADDA3A;
3697                         break;
3698                 default:
3699                         return 0;
3700                 }
3701                 break;
3702         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3703                 preemph_reg_value = 0x0000000;
3704                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3705                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3706                         demph_reg_value = 0x2B305555;
3707                         uniqtranscale_reg_value = 0x5570B83A;
3708                         break;
3709                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3710                         demph_reg_value = 0x2B2B4040;
3711                         uniqtranscale_reg_value = 0x55ADDA3A;
3712                         break;
3713                 default:
3714                         return 0;
3715                 }
3716                 break;
3717         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3718                 preemph_reg_value = 0x0006000;
3719                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3720                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3721                         demph_reg_value = 0x1B405555;
3722                         uniqtranscale_reg_value = 0x55ADDA3A;
3723                         break;
3724                 default:
3725                         return 0;
3726                 }
3727                 break;
3728         default:
3729                 return 0;
3730         }
3731
3732         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3733                                  uniqtranscale_reg_value, 0);
3734
3735         return 0;
3736 }
3737
3738 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3739 {
3740         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3741         u32 deemph_reg_value, margin_reg_value;
3742         bool uniq_trans_scale = false;
3743         u8 train_set = intel_dp->train_set[0];
3744
3745         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3746         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3747                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3748                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3749                         deemph_reg_value = 128;
3750                         margin_reg_value = 52;
3751                         break;
3752                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3753                         deemph_reg_value = 128;
3754                         margin_reg_value = 77;
3755                         break;
3756                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3757                         deemph_reg_value = 128;
3758                         margin_reg_value = 102;
3759                         break;
3760                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3761                         deemph_reg_value = 128;
3762                         margin_reg_value = 154;
3763                         uniq_trans_scale = true;
3764                         break;
3765                 default:
3766                         return 0;
3767                 }
3768                 break;
3769         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3770                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3771                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3772                         deemph_reg_value = 85;
3773                         margin_reg_value = 78;
3774                         break;
3775                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3776                         deemph_reg_value = 85;
3777                         margin_reg_value = 116;
3778                         break;
3779                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3780                         deemph_reg_value = 85;
3781                         margin_reg_value = 154;
3782                         break;
3783                 default:
3784                         return 0;
3785                 }
3786                 break;
3787         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3788                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3789                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3790                         deemph_reg_value = 64;
3791                         margin_reg_value = 104;
3792                         break;
3793                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3794                         deemph_reg_value = 64;
3795                         margin_reg_value = 154;
3796                         break;
3797                 default:
3798                         return 0;
3799                 }
3800                 break;
3801         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3802                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3803                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3804                         deemph_reg_value = 43;
3805                         margin_reg_value = 154;
3806                         break;
3807                 default:
3808                         return 0;
3809                 }
3810                 break;
3811         default:
3812                 return 0;
3813         }
3814
3815         chv_set_phy_signal_level(encoder, deemph_reg_value,
3816                                  margin_reg_value, uniq_trans_scale);
3817
3818         return 0;
3819 }
3820
3821 static u32
3822 g4x_signal_levels(u8 train_set)
3823 {
3824         u32 signal_levels = 0;
3825
3826         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3827         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3828         default:
3829                 signal_levels |= DP_VOLTAGE_0_4;
3830                 break;
3831         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3832                 signal_levels |= DP_VOLTAGE_0_6;
3833                 break;
3834         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3835                 signal_levels |= DP_VOLTAGE_0_8;
3836                 break;
3837         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3838                 signal_levels |= DP_VOLTAGE_1_2;
3839                 break;
3840         }
3841         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3842         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3843         default:
3844                 signal_levels |= DP_PRE_EMPHASIS_0;
3845                 break;
3846         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3847                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3848                 break;
3849         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3850                 signal_levels |= DP_PRE_EMPHASIS_6;
3851                 break;
3852         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3853                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3854                 break;
3855         }
3856         return signal_levels;
3857 }
3858
3859 /* SNB CPU eDP voltage swing and pre-emphasis control */
3860 static u32
3861 snb_cpu_edp_signal_levels(u8 train_set)
3862 {
3863         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3864                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3865         switch (signal_levels) {
3866         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3867         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3868                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3869         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3870                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3871         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3872         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3873                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3874         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3875         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3876                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3877         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3878         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3879                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3880         default:
3881                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3882                               "0x%x\n", signal_levels);
3883                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3884         }
3885 }
3886
3887 /* IVB CPU eDP voltage swing and pre-emphasis control */
3888 static u32
3889 ivb_cpu_edp_signal_levels(u8 train_set)
3890 {
3891         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3892                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3893         switch (signal_levels) {
3894         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3895                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3896         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3897                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3898         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3899                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3900
3901         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3902                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3903         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3904                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3905
3906         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3907                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3908         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3909                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3910
3911         default:
3912                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3913                               "0x%x\n", signal_levels);
3914                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3915         }
3916 }
3917
3918 void
3919 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3920 {
3921         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3922         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3923         enum port port = intel_dig_port->base.port;
3924         u32 signal_levels, mask = 0;
3925         u8 train_set = intel_dp->train_set[0];
3926
3927         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3928                 signal_levels = bxt_signal_levels(intel_dp);
3929         } else if (HAS_DDI(dev_priv)) {
3930                 signal_levels = ddi_signal_levels(intel_dp);
3931                 mask = DDI_BUF_EMP_MASK;
3932         } else if (IS_CHERRYVIEW(dev_priv)) {
3933                 signal_levels = chv_signal_levels(intel_dp);
3934         } else if (IS_VALLEYVIEW(dev_priv)) {
3935                 signal_levels = vlv_signal_levels(intel_dp);
3936         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3937                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3938                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3939         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3940                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3941                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3942         } else {
3943                 signal_levels = g4x_signal_levels(train_set);
3944                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3945         }
3946
3947         if (mask)
3948                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3949
3950         DRM_DEBUG_KMS("Using vswing level %d\n",
3951                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3952         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3953                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3954                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3955
3956         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3957
3958         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3959         POSTING_READ(intel_dp->output_reg);
3960 }
3961
3962 void
3963 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3964                                        u8 dp_train_pat)
3965 {
3966         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3967         struct drm_i915_private *dev_priv =
3968                 to_i915(intel_dig_port->base.base.dev);
3969
3970         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3971
3972         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3973         POSTING_READ(intel_dp->output_reg);
3974 }
3975
3976 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3977 {
3978         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3979         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3980         enum port port = intel_dig_port->base.port;
3981         u32 val;
3982
3983         if (!HAS_DDI(dev_priv))
3984                 return;
3985
3986         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3987         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3988         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3989         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3990
3991         /*
3992          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3993          * reason we need to set idle transmission mode is to work around a HW
3994          * issue where we enable the pipe while not in idle link-training mode.
3995          * In this case there is requirement to wait for a minimum number of
3996          * idle patterns to be sent.
3997          */
3998         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
3999                 return;
4000
4001         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4002                                   DP_TP_STATUS_IDLE_DONE, 1))
4003                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
4004 }
4005
4006 static void
4007 intel_dp_link_down(struct intel_encoder *encoder,
4008                    const struct intel_crtc_state *old_crtc_state)
4009 {
4010         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4011         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4012         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4013         enum port port = encoder->port;
4014         u32 DP = intel_dp->DP;
4015
4016         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
4017                 return;
4018
4019         DRM_DEBUG_KMS("\n");
4020
4021         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4022             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4023                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4024                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4025         } else {
4026                 DP &= ~DP_LINK_TRAIN_MASK;
4027                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4028         }
4029         I915_WRITE(intel_dp->output_reg, DP);
4030         POSTING_READ(intel_dp->output_reg);
4031
4032         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4033         I915_WRITE(intel_dp->output_reg, DP);
4034         POSTING_READ(intel_dp->output_reg);
4035
4036         /*
4037          * HW workaround for IBX, we need to move the port
4038          * to transcoder A after disabling it to allow the
4039          * matching HDMI port to be enabled on transcoder A.
4040          */
4041         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4042                 /*
4043                  * We get CPU/PCH FIFO underruns on the other pipe when
4044                  * doing the workaround. Sweep them under the rug.
4045                  */
4046                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4047                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4048
4049                 /* always enable with pattern 1 (as per spec) */
4050                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4051                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4052                         DP_LINK_TRAIN_PAT_1;
4053                 I915_WRITE(intel_dp->output_reg, DP);
4054                 POSTING_READ(intel_dp->output_reg);
4055
4056                 DP &= ~DP_PORT_EN;
4057                 I915_WRITE(intel_dp->output_reg, DP);
4058                 POSTING_READ(intel_dp->output_reg);
4059
4060                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4061                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4062                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4063         }
4064
4065         msleep(intel_dp->panel_power_down_delay);
4066
4067         intel_dp->DP = DP;
4068
4069         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4070                 intel_wakeref_t wakeref;
4071
4072                 with_pps_lock(intel_dp, wakeref)
4073                         intel_dp->active_pipe = INVALID_PIPE;
4074         }
4075 }
4076
4077 static void
4078 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4079 {
4080         u8 dpcd_ext[6];
4081
4082         /*
4083          * Prior to DP1.3 the bit represented by
4084          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4085          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4086          * the true capability of the panel. The only way to check is to
4087          * then compare 0000h and 2200h.
4088          */
4089         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4090               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4091                 return;
4092
4093         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4094                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4095                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4096                 return;
4097         }
4098
4099         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4100                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4101                 return;
4102         }
4103
4104         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4105                 return;
4106
4107         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4108                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4109
4110         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4111 }
4112
4113 bool
4114 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4115 {
4116         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4117                              sizeof(intel_dp->dpcd)) < 0)
4118                 return false; /* aux transfer failed */
4119
4120         intel_dp_extended_receiver_capabilities(intel_dp);
4121
4122         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4123
4124         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4125 }
4126
4127 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4128 {
4129         u8 dprx = 0;
4130
4131         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4132                               &dprx) != 1)
4133                 return false;
4134         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4135 }
4136
4137 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4138 {
4139         /*
4140          * Clear the cached register set to avoid using stale values
4141          * for the sinks that do not support DSC.
4142          */
4143         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4144
4145         /* Clear fec_capable to avoid using stale values */
4146         intel_dp->fec_capable = 0;
4147
4148         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4149         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4150             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4151                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4152                                      intel_dp->dsc_dpcd,
4153                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4154                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4155                                   DP_DSC_SUPPORT);
4156
4157                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4158                               (int)sizeof(intel_dp->dsc_dpcd),
4159                               intel_dp->dsc_dpcd);
4160
4161                 /* FEC is supported only on DP 1.4 */
4162                 if (!intel_dp_is_edp(intel_dp) &&
4163                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4164                                       &intel_dp->fec_capable) < 0)
4165                         DRM_ERROR("Failed to read FEC DPCD register\n");
4166
4167                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4168         }
4169 }
4170
4171 static bool
4172 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4173 {
4174         struct drm_i915_private *dev_priv =
4175                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4176
4177         /* this function is meant to be called only once */
4178         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4179
4180         if (!intel_dp_read_dpcd(intel_dp))
4181                 return false;
4182
4183         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4184                          drm_dp_is_branch(intel_dp->dpcd));
4185
4186         /*
4187          * Read the eDP display control registers.
4188          *
4189          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4190          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4191          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4192          * method). The display control registers should read zero if they're
4193          * not supported anyway.
4194          */
4195         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4196                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4197                              sizeof(intel_dp->edp_dpcd))
4198                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4199                               intel_dp->edp_dpcd);
4200
4201         /*
4202          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4203          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4204          */
4205         intel_psr_init_dpcd(intel_dp);
4206
4207         /* Read the eDP 1.4+ supported link rates. */
4208         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4209                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4210                 int i;
4211
4212                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4213                                 sink_rates, sizeof(sink_rates));
4214
4215                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4216                         int val = le16_to_cpu(sink_rates[i]);
4217
4218                         if (val == 0)
4219                                 break;
4220
4221                         /* Value read multiplied by 200kHz gives the per-lane
4222                          * link rate in kHz. The source rates are, however,
4223                          * stored in terms of LS_Clk kHz. The full conversion
4224                          * back to symbols is
4225                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4226                          */
4227                         intel_dp->sink_rates[i] = (val * 200) / 10;
4228                 }
4229                 intel_dp->num_sink_rates = i;
4230         }
4231
4232         /*
4233          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4234          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4235          */
4236         if (intel_dp->num_sink_rates)
4237                 intel_dp->use_rate_select = true;
4238         else
4239                 intel_dp_set_sink_rates(intel_dp);
4240
4241         intel_dp_set_common_rates(intel_dp);
4242
4243         /* Read the eDP DSC DPCD registers */
4244         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4245                 intel_dp_get_dsc_sink_cap(intel_dp);
4246
4247         return true;
4248 }
4249
4250
4251 static bool
4252 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4253 {
4254         if (!intel_dp_read_dpcd(intel_dp))
4255                 return false;
4256
4257         /*
4258          * Don't clobber cached eDP rates. Also skip re-reading
4259          * the OUI/ID since we know it won't change.
4260          */
4261         if (!intel_dp_is_edp(intel_dp)) {
4262                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4263                                  drm_dp_is_branch(intel_dp->dpcd));
4264
4265                 intel_dp_set_sink_rates(intel_dp);
4266                 intel_dp_set_common_rates(intel_dp);
4267         }
4268
4269         /*
4270          * Some eDP panels do not set a valid value for sink count, that is why
4271          * it don't care about read it here and in intel_edp_init_dpcd().
4272          */
4273         if (!intel_dp_is_edp(intel_dp) &&
4274             !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4275                 u8 count;
4276                 ssize_t r;
4277
4278                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4279                 if (r < 1)
4280                         return false;
4281
4282                 /*
4283                  * Sink count can change between short pulse hpd hence
4284                  * a member variable in intel_dp will track any changes
4285                  * between short pulse interrupts.
4286                  */
4287                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4288
4289                 /*
4290                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4291                  * a dongle is present but no display. Unless we require to know
4292                  * if a dongle is present or not, we don't need to update
4293                  * downstream port information. So, an early return here saves
4294                  * time from performing other operations which are not required.
4295                  */
4296                 if (!intel_dp->sink_count)
4297                         return false;
4298         }
4299
4300         if (!drm_dp_is_branch(intel_dp->dpcd))
4301                 return true; /* native DP sink */
4302
4303         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4304                 return true; /* no per-port downstream info */
4305
4306         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4307                              intel_dp->downstream_ports,
4308                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4309                 return false; /* downstream port status fetch failed */
4310
4311         return true;
4312 }
4313
4314 static bool
4315 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4316 {
4317         u8 mstm_cap;
4318
4319         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4320                 return false;
4321
4322         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4323                 return false;
4324
4325         return mstm_cap & DP_MST_CAP;
4326 }
4327
4328 static bool
4329 intel_dp_can_mst(struct intel_dp *intel_dp)
4330 {
4331         return i915_modparams.enable_dp_mst &&
4332                 intel_dp->can_mst &&
4333                 intel_dp_sink_can_mst(intel_dp);
4334 }
4335
4336 static void
4337 intel_dp_configure_mst(struct intel_dp *intel_dp)
4338 {
4339         struct intel_encoder *encoder =
4340                 &dp_to_dig_port(intel_dp)->base;
4341         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4342
4343         DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support? port: %s, sink: %s, modparam: %s\n",
4344                       encoder->base.base.id, encoder->base.name,
4345                       yesno(intel_dp->can_mst), yesno(sink_can_mst),
4346                       yesno(i915_modparams.enable_dp_mst));
4347
4348         if (!intel_dp->can_mst)
4349                 return;
4350
4351         intel_dp->is_mst = sink_can_mst &&
4352                 i915_modparams.enable_dp_mst;
4353
4354         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4355                                         intel_dp->is_mst);
4356 }
4357
4358 static bool
4359 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4360 {
4361         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4362                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4363                 DP_DPRX_ESI_LEN;
4364 }
4365
4366 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
4367                                 int mode_clock, int mode_hdisplay)
4368 {
4369         u16 bits_per_pixel, max_bpp_small_joiner_ram;
4370         int i;
4371
4372         /*
4373          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4374          * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4375          * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4376          * for MST -> TimeSlotsPerMTP has to be calculated
4377          */
4378         bits_per_pixel = (link_clock * lane_count * 8 *
4379                           DP_DSC_FEC_OVERHEAD_FACTOR) /
4380                 mode_clock;
4381
4382         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4383         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4384                 mode_hdisplay;
4385
4386         /*
4387          * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4388          * check, output bpp from small joiner RAM check)
4389          */
4390         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4391
4392         /* Error out if the max bpp is less than smallest allowed valid bpp */
4393         if (bits_per_pixel < valid_dsc_bpp[0]) {
4394                 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4395                 return 0;
4396         }
4397
4398         /* Find the nearest match in the array of known BPPs from VESA */
4399         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4400                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4401                         break;
4402         }
4403         bits_per_pixel = valid_dsc_bpp[i];
4404
4405         /*
4406          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4407          * fractional part is 0
4408          */
4409         return bits_per_pixel << 4;
4410 }
4411
4412 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4413                                 int mode_clock,
4414                                 int mode_hdisplay)
4415 {
4416         u8 min_slice_count, i;
4417         int max_slice_width;
4418
4419         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4420                 min_slice_count = DIV_ROUND_UP(mode_clock,
4421                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
4422         else
4423                 min_slice_count = DIV_ROUND_UP(mode_clock,
4424                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
4425
4426         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4427         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4428                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4429                               max_slice_width);
4430                 return 0;
4431         }
4432         /* Also take into account max slice width */
4433         min_slice_count = min_t(u8, min_slice_count,
4434                                 DIV_ROUND_UP(mode_hdisplay,
4435                                              max_slice_width));
4436
4437         /* Find the closest match to the valid slice count values */
4438         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4439                 if (valid_dsc_slicecount[i] >
4440                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4441                                                     false))
4442                         break;
4443                 if (min_slice_count  <= valid_dsc_slicecount[i])
4444                         return valid_dsc_slicecount[i];
4445         }
4446
4447         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4448         return 0;
4449 }
4450
4451 static void
4452 intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
4453                                const struct intel_crtc_state *crtc_state)
4454 {
4455         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4456         struct dp_sdp vsc_sdp = {};
4457
4458         /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4459         vsc_sdp.sdp_header.HB0 = 0;
4460         vsc_sdp.sdp_header.HB1 = 0x7;
4461
4462         /*
4463          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4464          * Colorimetry Format indication.
4465          */
4466         vsc_sdp.sdp_header.HB2 = 0x5;
4467
4468         /*
4469          * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4470          * Colorimetry Format indication (HB2 = 05h).
4471          */
4472         vsc_sdp.sdp_header.HB3 = 0x13;
4473
4474         /*
4475          * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
4476          * DB16[3:0] DP 1.4a spec, Table 2-120
4477          */
4478         vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
4479         /* RGB->YCBCR color conversion uses the BT.709 color space. */
4480         vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4481
4482         /*
4483          * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4484          * the following Component Bit Depth values are defined:
4485          * 001b = 8bpc.
4486          * 010b = 10bpc.
4487          * 011b = 12bpc.
4488          * 100b = 16bpc.
4489          */
4490         switch (crtc_state->pipe_bpp) {
4491         case 24: /* 8bpc */
4492                 vsc_sdp.db[17] = 0x1;
4493                 break;
4494         case 30: /* 10bpc */
4495                 vsc_sdp.db[17] = 0x2;
4496                 break;
4497         case 36: /* 12bpc */
4498                 vsc_sdp.db[17] = 0x3;
4499                 break;
4500         case 48: /* 16bpc */
4501                 vsc_sdp.db[17] = 0x4;
4502                 break;
4503         default:
4504                 MISSING_CASE(crtc_state->pipe_bpp);
4505                 break;
4506         }
4507
4508         /*
4509          * Dynamic Range (Bit 7)
4510          * 0 = VESA range, 1 = CTA range.
4511          * all YCbCr are always limited range
4512          */
4513         vsc_sdp.db[17] |= 0x80;
4514
4515         /*
4516          * Content Type (Bits 2:0)
4517          * 000b = Not defined.
4518          * 001b = Graphics.
4519          * 010b = Photo.
4520          * 011b = Video.
4521          * 100b = Game
4522          * All other values are RESERVED.
4523          * Note: See CTA-861-G for the definition and expected
4524          * processing by a stream sink for the above contect types.
4525          */
4526         vsc_sdp.db[18] = 0;
4527
4528         intel_dig_port->write_infoframe(&intel_dig_port->base,
4529                         crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4530 }
4531
4532 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
4533                                const struct intel_crtc_state *crtc_state)
4534 {
4535         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
4536                 return;
4537
4538         intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
4539 }
4540
4541 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4542 {
4543         int status = 0;
4544         int test_link_rate;
4545         u8 test_lane_count, test_link_bw;
4546         /* (DP CTS 1.2)
4547          * 4.3.1.11
4548          */
4549         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4550         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4551                                    &test_lane_count);
4552
4553         if (status <= 0) {
4554                 DRM_DEBUG_KMS("Lane count read failed\n");
4555                 return DP_TEST_NAK;
4556         }
4557         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4558
4559         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4560                                    &test_link_bw);
4561         if (status <= 0) {
4562                 DRM_DEBUG_KMS("Link Rate read failed\n");
4563                 return DP_TEST_NAK;
4564         }
4565         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4566
4567         /* Validate the requested link rate and lane count */
4568         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4569                                         test_lane_count))
4570                 return DP_TEST_NAK;
4571
4572         intel_dp->compliance.test_lane_count = test_lane_count;
4573         intel_dp->compliance.test_link_rate = test_link_rate;
4574
4575         return DP_TEST_ACK;
4576 }
4577
4578 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4579 {
4580         u8 test_pattern;
4581         u8 test_misc;
4582         __be16 h_width, v_height;
4583         int status = 0;
4584
4585         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4586         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4587                                    &test_pattern);
4588         if (status <= 0) {
4589                 DRM_DEBUG_KMS("Test pattern read failed\n");
4590                 return DP_TEST_NAK;
4591         }
4592         if (test_pattern != DP_COLOR_RAMP)
4593                 return DP_TEST_NAK;
4594
4595         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4596                                   &h_width, 2);
4597         if (status <= 0) {
4598                 DRM_DEBUG_KMS("H Width read failed\n");
4599                 return DP_TEST_NAK;
4600         }
4601
4602         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4603                                   &v_height, 2);
4604         if (status <= 0) {
4605                 DRM_DEBUG_KMS("V Height read failed\n");
4606                 return DP_TEST_NAK;
4607         }
4608
4609         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4610                                    &test_misc);
4611         if (status <= 0) {
4612                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4613                 return DP_TEST_NAK;
4614         }
4615         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4616                 return DP_TEST_NAK;
4617         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4618                 return DP_TEST_NAK;
4619         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4620         case DP_TEST_BIT_DEPTH_6:
4621                 intel_dp->compliance.test_data.bpc = 6;
4622                 break;
4623         case DP_TEST_BIT_DEPTH_8:
4624                 intel_dp->compliance.test_data.bpc = 8;
4625                 break;
4626         default:
4627                 return DP_TEST_NAK;
4628         }
4629
4630         intel_dp->compliance.test_data.video_pattern = test_pattern;
4631         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4632         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4633         /* Set test active flag here so userspace doesn't interrupt things */
4634         intel_dp->compliance.test_active = 1;
4635
4636         return DP_TEST_ACK;
4637 }
4638
4639 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4640 {
4641         u8 test_result = DP_TEST_ACK;
4642         struct intel_connector *intel_connector = intel_dp->attached_connector;
4643         struct drm_connector *connector = &intel_connector->base;
4644
4645         if (intel_connector->detect_edid == NULL ||
4646             connector->edid_corrupt ||
4647             intel_dp->aux.i2c_defer_count > 6) {
4648                 /* Check EDID read for NACKs, DEFERs and corruption
4649                  * (DP CTS 1.2 Core r1.1)
4650                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4651                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4652                  *    4.2.2.6 : EDID corruption detected
4653                  * Use failsafe mode for all cases
4654                  */
4655                 if (intel_dp->aux.i2c_nack_count > 0 ||
4656                         intel_dp->aux.i2c_defer_count > 0)
4657                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4658                                       intel_dp->aux.i2c_nack_count,
4659                                       intel_dp->aux.i2c_defer_count);
4660                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4661         } else {
4662                 struct edid *block = intel_connector->detect_edid;
4663
4664                 /* We have to write the checksum
4665                  * of the last block read
4666                  */
4667                 block += intel_connector->detect_edid->extensions;
4668
4669                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4670                                        block->checksum) <= 0)
4671                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4672
4673                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4674                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4675         }
4676
4677         /* Set test active flag here so userspace doesn't interrupt things */
4678         intel_dp->compliance.test_active = 1;
4679
4680         return test_result;
4681 }
4682
4683 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4684 {
4685         u8 test_result = DP_TEST_NAK;
4686         return test_result;
4687 }
4688
4689 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4690 {
4691         u8 response = DP_TEST_NAK;
4692         u8 request = 0;
4693         int status;
4694
4695         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4696         if (status <= 0) {
4697                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4698                 goto update_status;
4699         }
4700
4701         switch (request) {
4702         case DP_TEST_LINK_TRAINING:
4703                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4704                 response = intel_dp_autotest_link_training(intel_dp);
4705                 break;
4706         case DP_TEST_LINK_VIDEO_PATTERN:
4707                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4708                 response = intel_dp_autotest_video_pattern(intel_dp);
4709                 break;
4710         case DP_TEST_LINK_EDID_READ:
4711                 DRM_DEBUG_KMS("EDID test requested\n");
4712                 response = intel_dp_autotest_edid(intel_dp);
4713                 break;
4714         case DP_TEST_LINK_PHY_TEST_PATTERN:
4715                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4716                 response = intel_dp_autotest_phy_pattern(intel_dp);
4717                 break;
4718         default:
4719                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4720                 break;
4721         }
4722
4723         if (response & DP_TEST_ACK)
4724                 intel_dp->compliance.test_type = request;
4725
4726 update_status:
4727         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4728         if (status <= 0)
4729                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4730 }
4731
4732 static int
4733 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4734 {
4735         bool bret;
4736
4737         if (intel_dp->is_mst) {
4738                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4739                 int ret = 0;
4740                 int retry;
4741                 bool handled;
4742
4743                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4744                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4745 go_again:
4746                 if (bret == true) {
4747
4748                         /* check link status - esi[10] = 0x200c */
4749                         if (intel_dp->active_mst_links > 0 &&
4750                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4751                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4752                                 intel_dp_start_link_train(intel_dp);
4753                                 intel_dp_stop_link_train(intel_dp);
4754                         }
4755
4756                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4757                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4758
4759                         if (handled) {
4760                                 for (retry = 0; retry < 3; retry++) {
4761                                         int wret;
4762                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4763                                                                  DP_SINK_COUNT_ESI+1,
4764                                                                  &esi[1], 3);
4765                                         if (wret == 3) {
4766                                                 break;
4767                                         }
4768                                 }
4769
4770                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4771                                 if (bret == true) {
4772                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4773                                         goto go_again;
4774                                 }
4775                         } else
4776                                 ret = 0;
4777
4778                         return ret;
4779                 } else {
4780                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4781                         intel_dp->is_mst = false;
4782                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4783                                                         intel_dp->is_mst);
4784                 }
4785         }
4786         return -EINVAL;
4787 }
4788
4789 static bool
4790 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4791 {
4792         u8 link_status[DP_LINK_STATUS_SIZE];
4793
4794         if (!intel_dp->link_trained)
4795                 return false;
4796
4797         /*
4798          * While PSR source HW is enabled, it will control main-link sending
4799          * frames, enabling and disabling it so trying to do a retrain will fail
4800          * as the link would or not be on or it could mix training patterns
4801          * and frame data at the same time causing retrain to fail.
4802          * Also when exiting PSR, HW will retrain the link anyways fixing
4803          * any link status error.
4804          */
4805         if (intel_psr_enabled(intel_dp))
4806                 return false;
4807
4808         if (!intel_dp_get_link_status(intel_dp, link_status))
4809                 return false;
4810
4811         /*
4812          * Validate the cached values of intel_dp->link_rate and
4813          * intel_dp->lane_count before attempting to retrain.
4814          */
4815         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4816                                         intel_dp->lane_count))
4817                 return false;
4818
4819         /* Retrain if Channel EQ or CR not ok */
4820         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4821 }
4822
4823 int intel_dp_retrain_link(struct intel_encoder *encoder,
4824                           struct drm_modeset_acquire_ctx *ctx)
4825 {
4826         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4827         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4828         struct intel_connector *connector = intel_dp->attached_connector;
4829         struct drm_connector_state *conn_state;
4830         struct intel_crtc_state *crtc_state;
4831         struct intel_crtc *crtc;
4832         int ret;
4833
4834         /* FIXME handle the MST connectors as well */
4835
4836         if (!connector || connector->base.status != connector_status_connected)
4837                 return 0;
4838
4839         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4840                                ctx);
4841         if (ret)
4842                 return ret;
4843
4844         conn_state = connector->base.state;
4845
4846         crtc = to_intel_crtc(conn_state->crtc);
4847         if (!crtc)
4848                 return 0;
4849
4850         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4851         if (ret)
4852                 return ret;
4853
4854         crtc_state = to_intel_crtc_state(crtc->base.state);
4855
4856         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4857
4858         if (!crtc_state->base.active)
4859                 return 0;
4860
4861         if (conn_state->commit &&
4862             !try_wait_for_completion(&conn_state->commit->hw_done))
4863                 return 0;
4864
4865         if (!intel_dp_needs_link_retrain(intel_dp))
4866                 return 0;
4867
4868         /* Suppress underruns caused by re-training */
4869         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4870         if (crtc_state->has_pch_encoder)
4871                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4872                                                       intel_crtc_pch_transcoder(crtc), false);
4873
4874         intel_dp_start_link_train(intel_dp);
4875         intel_dp_stop_link_train(intel_dp);
4876
4877         /* Keep underrun reporting disabled until things are stable */
4878         intel_wait_for_vblank(dev_priv, crtc->pipe);
4879
4880         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4881         if (crtc_state->has_pch_encoder)
4882                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4883                                                       intel_crtc_pch_transcoder(crtc), true);
4884
4885         return 0;
4886 }
4887
4888 /*
4889  * If display is now connected check links status,
4890  * there has been known issues of link loss triggering
4891  * long pulse.
4892  *
4893  * Some sinks (eg. ASUS PB287Q) seem to perform some
4894  * weird HPD ping pong during modesets. So we can apparently
4895  * end up with HPD going low during a modeset, and then
4896  * going back up soon after. And once that happens we must
4897  * retrain the link to get a picture. That's in case no
4898  * userspace component reacted to intermittent HPD dip.
4899  */
4900 static enum intel_hotplug_state
4901 intel_dp_hotplug(struct intel_encoder *encoder,
4902                  struct intel_connector *connector,
4903                  bool irq_received)
4904 {
4905         struct drm_modeset_acquire_ctx ctx;
4906         enum intel_hotplug_state state;
4907         int ret;
4908
4909         state = intel_encoder_hotplug(encoder, connector, irq_received);
4910
4911         drm_modeset_acquire_init(&ctx, 0);
4912
4913         for (;;) {
4914                 ret = intel_dp_retrain_link(encoder, &ctx);
4915
4916                 if (ret == -EDEADLK) {
4917                         drm_modeset_backoff(&ctx);
4918                         continue;
4919                 }
4920
4921                 break;
4922         }
4923
4924         drm_modeset_drop_locks(&ctx);
4925         drm_modeset_acquire_fini(&ctx);
4926         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4927
4928         /*
4929          * Keeping it consistent with intel_ddi_hotplug() and
4930          * intel_hdmi_hotplug().
4931          */
4932         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
4933                 state = INTEL_HOTPLUG_RETRY;
4934
4935         return state;
4936 }
4937
4938 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4939 {
4940         u8 val;
4941
4942         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4943                 return;
4944
4945         if (drm_dp_dpcd_readb(&intel_dp->aux,
4946                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4947                 return;
4948
4949         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4950
4951         if (val & DP_AUTOMATED_TEST_REQUEST)
4952                 intel_dp_handle_test_request(intel_dp);
4953
4954         if (val & DP_CP_IRQ)
4955                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4956
4957         if (val & DP_SINK_SPECIFIC_IRQ)
4958                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4959 }
4960
4961 /*
4962  * According to DP spec
4963  * 5.1.2:
4964  *  1. Read DPCD
4965  *  2. Configure link according to Receiver Capabilities
4966  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4967  *  4. Check link status on receipt of hot-plug interrupt
4968  *
4969  * intel_dp_short_pulse -  handles short pulse interrupts
4970  * when full detection is not required.
4971  * Returns %true if short pulse is handled and full detection
4972  * is NOT required and %false otherwise.
4973  */
4974 static bool
4975 intel_dp_short_pulse(struct intel_dp *intel_dp)
4976 {
4977         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4978         u8 old_sink_count = intel_dp->sink_count;
4979         bool ret;
4980
4981         /*
4982          * Clearing compliance test variables to allow capturing
4983          * of values for next automated test request.
4984          */
4985         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4986
4987         /*
4988          * Now read the DPCD to see if it's actually running
4989          * If the current value of sink count doesn't match with
4990          * the value that was stored earlier or dpcd read failed
4991          * we need to do full detection
4992          */
4993         ret = intel_dp_get_dpcd(intel_dp);
4994
4995         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4996                 /* No need to proceed if we are going to do full detect */
4997                 return false;
4998         }
4999
5000         intel_dp_check_service_irq(intel_dp);
5001
5002         /* Handle CEC interrupts, if any */
5003         drm_dp_cec_irq(&intel_dp->aux);
5004
5005         /* defer to the hotplug work for link retraining if needed */
5006         if (intel_dp_needs_link_retrain(intel_dp))
5007                 return false;
5008
5009         intel_psr_short_pulse(intel_dp);
5010
5011         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5012                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
5013                 /* Send a Hotplug Uevent to userspace to start modeset */
5014                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5015         }
5016
5017         return true;
5018 }
5019
5020 /* XXX this is probably wrong for multiple downstream ports */
5021 static enum drm_connector_status
5022 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5023 {
5024         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5025         u8 *dpcd = intel_dp->dpcd;
5026         u8 type;
5027
5028         if (WARN_ON(intel_dp_is_edp(intel_dp)))
5029                 return connector_status_connected;
5030
5031         if (lspcon->active)
5032                 lspcon_resume(lspcon);
5033
5034         if (!intel_dp_get_dpcd(intel_dp))
5035                 return connector_status_disconnected;
5036
5037         /* if there's no downstream port, we're done */
5038         if (!drm_dp_is_branch(dpcd))
5039                 return connector_status_connected;
5040
5041         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5042         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5043             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5044
5045                 return intel_dp->sink_count ?
5046                 connector_status_connected : connector_status_disconnected;
5047         }
5048
5049         if (intel_dp_can_mst(intel_dp))
5050                 return connector_status_connected;
5051
5052         /* If no HPD, poke DDC gently */
5053         if (drm_probe_ddc(&intel_dp->aux.ddc))
5054                 return connector_status_connected;
5055
5056         /* Well we tried, say unknown for unreliable port types */
5057         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5058                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5059                 if (type == DP_DS_PORT_TYPE_VGA ||
5060                     type == DP_DS_PORT_TYPE_NON_EDID)
5061                         return connector_status_unknown;
5062         } else {
5063                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5064                         DP_DWN_STRM_PORT_TYPE_MASK;
5065                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5066                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5067                         return connector_status_unknown;
5068         }
5069
5070         /* Anything else is out of spec, warn and ignore */
5071         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5072         return connector_status_disconnected;
5073 }
5074
5075 static enum drm_connector_status
5076 edp_detect(struct intel_dp *intel_dp)
5077 {
5078         return connector_status_connected;
5079 }
5080
5081 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5082 {
5083         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5084         u32 bit;
5085
5086         switch (encoder->hpd_pin) {
5087         case HPD_PORT_B:
5088                 bit = SDE_PORTB_HOTPLUG;
5089                 break;
5090         case HPD_PORT_C:
5091                 bit = SDE_PORTC_HOTPLUG;
5092                 break;
5093         case HPD_PORT_D:
5094                 bit = SDE_PORTD_HOTPLUG;
5095                 break;
5096         default:
5097                 MISSING_CASE(encoder->hpd_pin);
5098                 return false;
5099         }
5100
5101         return I915_READ(SDEISR) & bit;
5102 }
5103
5104 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5105 {
5106         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5107         u32 bit;
5108
5109         switch (encoder->hpd_pin) {
5110         case HPD_PORT_B:
5111                 bit = SDE_PORTB_HOTPLUG_CPT;
5112                 break;
5113         case HPD_PORT_C:
5114                 bit = SDE_PORTC_HOTPLUG_CPT;
5115                 break;
5116         case HPD_PORT_D:
5117                 bit = SDE_PORTD_HOTPLUG_CPT;
5118                 break;
5119         default:
5120                 MISSING_CASE(encoder->hpd_pin);
5121                 return false;
5122         }
5123
5124         return I915_READ(SDEISR) & bit;
5125 }
5126
5127 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5128 {
5129         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5130         u32 bit;
5131
5132         switch (encoder->hpd_pin) {
5133         case HPD_PORT_A:
5134                 bit = SDE_PORTA_HOTPLUG_SPT;
5135                 break;
5136         case HPD_PORT_E:
5137                 bit = SDE_PORTE_HOTPLUG_SPT;
5138                 break;
5139         default:
5140                 return cpt_digital_port_connected(encoder);
5141         }
5142
5143         return I915_READ(SDEISR) & bit;
5144 }
5145
5146 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5147 {
5148         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5149         u32 bit;
5150
5151         switch (encoder->hpd_pin) {
5152         case HPD_PORT_B:
5153                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5154                 break;
5155         case HPD_PORT_C:
5156                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5157                 break;
5158         case HPD_PORT_D:
5159                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5160                 break;
5161         default:
5162                 MISSING_CASE(encoder->hpd_pin);
5163                 return false;
5164         }
5165
5166         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5167 }
5168
5169 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5170 {
5171         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5172         u32 bit;
5173
5174         switch (encoder->hpd_pin) {
5175         case HPD_PORT_B:
5176                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5177                 break;
5178         case HPD_PORT_C:
5179                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5180                 break;
5181         case HPD_PORT_D:
5182                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5183                 break;
5184         default:
5185                 MISSING_CASE(encoder->hpd_pin);
5186                 return false;
5187         }
5188
5189         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5190 }
5191
5192 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5193 {
5194         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5195
5196         if (encoder->hpd_pin == HPD_PORT_A)
5197                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5198         else
5199                 return ibx_digital_port_connected(encoder);
5200 }
5201
5202 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5203 {
5204         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5205
5206         if (encoder->hpd_pin == HPD_PORT_A)
5207                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5208         else
5209                 return cpt_digital_port_connected(encoder);
5210 }
5211
5212 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5213 {
5214         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5215
5216         if (encoder->hpd_pin == HPD_PORT_A)
5217                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5218         else
5219                 return cpt_digital_port_connected(encoder);
5220 }
5221
5222 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5223 {
5224         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5225
5226         if (encoder->hpd_pin == HPD_PORT_A)
5227                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5228         else
5229                 return cpt_digital_port_connected(encoder);
5230 }
5231
5232 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5233 {
5234         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5235         u32 bit;
5236
5237         switch (encoder->hpd_pin) {
5238         case HPD_PORT_A:
5239                 bit = BXT_DE_PORT_HP_DDIA;
5240                 break;
5241         case HPD_PORT_B:
5242                 bit = BXT_DE_PORT_HP_DDIB;
5243                 break;
5244         case HPD_PORT_C:
5245                 bit = BXT_DE_PORT_HP_DDIC;
5246                 break;
5247         default:
5248                 MISSING_CASE(encoder->hpd_pin);
5249                 return false;
5250         }
5251
5252         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5253 }
5254
5255 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5256                                      struct intel_digital_port *intel_dig_port)
5257 {
5258         enum port port = intel_dig_port->base.port;
5259
5260         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5261 }
5262
5263 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5264 {
5265         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5266         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5267         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5268
5269         if (intel_phy_is_combo(dev_priv, phy))
5270                 return icl_combo_port_connected(dev_priv, dig_port);
5271         else if (intel_phy_is_tc(dev_priv, phy))
5272                 return intel_tc_port_connected(dig_port);
5273         else
5274                 MISSING_CASE(encoder->hpd_pin);
5275
5276         return false;
5277 }
5278
5279 /*
5280  * intel_digital_port_connected - is the specified port connected?
5281  * @encoder: intel_encoder
5282  *
5283  * In cases where there's a connector physically connected but it can't be used
5284  * by our hardware we also return false, since the rest of the driver should
5285  * pretty much treat the port as disconnected. This is relevant for type-C
5286  * (starting on ICL) where there's ownership involved.
5287  *
5288  * Return %true if port is connected, %false otherwise.
5289  */
5290 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5291 {
5292         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5293
5294         if (HAS_GMCH(dev_priv)) {
5295                 if (IS_GM45(dev_priv))
5296                         return gm45_digital_port_connected(encoder);
5297                 else
5298                         return g4x_digital_port_connected(encoder);
5299         }
5300
5301         if (INTEL_GEN(dev_priv) >= 11)
5302                 return icl_digital_port_connected(encoder);
5303         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5304                 return spt_digital_port_connected(encoder);
5305         else if (IS_GEN9_LP(dev_priv))
5306                 return bxt_digital_port_connected(encoder);
5307         else if (IS_GEN(dev_priv, 8))
5308                 return bdw_digital_port_connected(encoder);
5309         else if (IS_GEN(dev_priv, 7))
5310                 return ivb_digital_port_connected(encoder);
5311         else if (IS_GEN(dev_priv, 6))
5312                 return snb_digital_port_connected(encoder);
5313         else if (IS_GEN(dev_priv, 5))
5314                 return ilk_digital_port_connected(encoder);
5315
5316         MISSING_CASE(INTEL_GEN(dev_priv));
5317         return false;
5318 }
5319
5320 bool intel_digital_port_connected(struct intel_encoder *encoder)
5321 {
5322         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5323         bool is_connected = false;
5324         intel_wakeref_t wakeref;
5325
5326         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5327                 is_connected = __intel_digital_port_connected(encoder);
5328
5329         return is_connected;
5330 }
5331
5332 static struct edid *
5333 intel_dp_get_edid(struct intel_dp *intel_dp)
5334 {
5335         struct intel_connector *intel_connector = intel_dp->attached_connector;
5336
5337         /* use cached edid if we have one */
5338         if (intel_connector->edid) {
5339                 /* invalid edid */
5340                 if (IS_ERR(intel_connector->edid))
5341                         return NULL;
5342
5343                 return drm_edid_duplicate(intel_connector->edid);
5344         } else
5345                 return drm_get_edid(&intel_connector->base,
5346                                     &intel_dp->aux.ddc);
5347 }
5348
5349 static void
5350 intel_dp_set_edid(struct intel_dp *intel_dp)
5351 {
5352         struct intel_connector *intel_connector = intel_dp->attached_connector;
5353         struct edid *edid;
5354
5355         intel_dp_unset_edid(intel_dp);
5356         edid = intel_dp_get_edid(intel_dp);
5357         intel_connector->detect_edid = edid;
5358
5359         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5360         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5361 }
5362
5363 static void
5364 intel_dp_unset_edid(struct intel_dp *intel_dp)
5365 {
5366         struct intel_connector *intel_connector = intel_dp->attached_connector;
5367
5368         drm_dp_cec_unset_edid(&intel_dp->aux);
5369         kfree(intel_connector->detect_edid);
5370         intel_connector->detect_edid = NULL;
5371
5372         intel_dp->has_audio = false;
5373 }
5374
5375 static int
5376 intel_dp_detect(struct drm_connector *connector,
5377                 struct drm_modeset_acquire_ctx *ctx,
5378                 bool force)
5379 {
5380         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5381         struct intel_dp *intel_dp = intel_attached_dp(connector);
5382         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5383         struct intel_encoder *encoder = &dig_port->base;
5384         enum drm_connector_status status;
5385
5386         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5387                       connector->base.id, connector->name);
5388         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5389
5390         /* Can't disconnect eDP */
5391         if (intel_dp_is_edp(intel_dp))
5392                 status = edp_detect(intel_dp);
5393         else if (intel_digital_port_connected(encoder))
5394                 status = intel_dp_detect_dpcd(intel_dp);
5395         else
5396                 status = connector_status_disconnected;
5397
5398         if (status == connector_status_disconnected) {
5399                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5400                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5401
5402                 if (intel_dp->is_mst) {
5403                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5404                                       intel_dp->is_mst,
5405                                       intel_dp->mst_mgr.mst_state);
5406                         intel_dp->is_mst = false;
5407                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5408                                                         intel_dp->is_mst);
5409                 }
5410
5411                 goto out;
5412         }
5413
5414         if (intel_dp->reset_link_params) {
5415                 /* Initial max link lane count */
5416                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5417
5418                 /* Initial max link rate */
5419                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5420
5421                 intel_dp->reset_link_params = false;
5422         }
5423
5424         intel_dp_print_rates(intel_dp);
5425
5426         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5427         if (INTEL_GEN(dev_priv) >= 11)
5428                 intel_dp_get_dsc_sink_cap(intel_dp);
5429
5430         intel_dp_configure_mst(intel_dp);
5431
5432         if (intel_dp->is_mst) {
5433                 /*
5434                  * If we are in MST mode then this connector
5435                  * won't appear connected or have anything
5436                  * with EDID on it
5437                  */
5438                 status = connector_status_disconnected;
5439                 goto out;
5440         }
5441
5442         /*
5443          * Some external monitors do not signal loss of link synchronization
5444          * with an IRQ_HPD, so force a link status check.
5445          */
5446         if (!intel_dp_is_edp(intel_dp)) {
5447                 int ret;
5448
5449                 ret = intel_dp_retrain_link(encoder, ctx);
5450                 if (ret)
5451                         return ret;
5452         }
5453
5454         /*
5455          * Clearing NACK and defer counts to get their exact values
5456          * while reading EDID which are required by Compliance tests
5457          * 4.2.2.4 and 4.2.2.5
5458          */
5459         intel_dp->aux.i2c_nack_count = 0;
5460         intel_dp->aux.i2c_defer_count = 0;
5461
5462         intel_dp_set_edid(intel_dp);
5463         if (intel_dp_is_edp(intel_dp) ||
5464             to_intel_connector(connector)->detect_edid)
5465                 status = connector_status_connected;
5466
5467         intel_dp_check_service_irq(intel_dp);
5468
5469 out:
5470         if (status != connector_status_connected && !intel_dp->is_mst)
5471                 intel_dp_unset_edid(intel_dp);
5472
5473         return status;
5474 }
5475
5476 static void
5477 intel_dp_force(struct drm_connector *connector)
5478 {
5479         struct intel_dp *intel_dp = intel_attached_dp(connector);
5480         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5481         struct intel_encoder *intel_encoder = &dig_port->base;
5482         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5483         enum intel_display_power_domain aux_domain =
5484                 intel_aux_power_domain(dig_port);
5485         intel_wakeref_t wakeref;
5486
5487         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5488                       connector->base.id, connector->name);
5489         intel_dp_unset_edid(intel_dp);
5490
5491         if (connector->status != connector_status_connected)
5492                 return;
5493
5494         wakeref = intel_display_power_get(dev_priv, aux_domain);
5495
5496         intel_dp_set_edid(intel_dp);
5497
5498         intel_display_power_put(dev_priv, aux_domain, wakeref);
5499 }
5500
5501 static int intel_dp_get_modes(struct drm_connector *connector)
5502 {
5503         struct intel_connector *intel_connector = to_intel_connector(connector);
5504         struct edid *edid;
5505
5506         edid = intel_connector->detect_edid;
5507         if (edid) {
5508                 int ret = intel_connector_update_modes(connector, edid);
5509                 if (ret)
5510                         return ret;
5511         }
5512
5513         /* if eDP has no EDID, fall back to fixed mode */
5514         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5515             intel_connector->panel.fixed_mode) {
5516                 struct drm_display_mode *mode;
5517
5518                 mode = drm_mode_duplicate(connector->dev,
5519                                           intel_connector->panel.fixed_mode);
5520                 if (mode) {
5521                         drm_mode_probed_add(connector, mode);
5522                         return 1;
5523                 }
5524         }
5525
5526         return 0;
5527 }
5528
5529 static int
5530 intel_dp_connector_register(struct drm_connector *connector)
5531 {
5532         struct intel_dp *intel_dp = intel_attached_dp(connector);
5533         struct drm_device *dev = connector->dev;
5534         int ret;
5535
5536         ret = intel_connector_register(connector);
5537         if (ret)
5538                 return ret;
5539
5540         i915_debugfs_connector_add(connector);
5541
5542         DRM_DEBUG_KMS("registering %s bus for %s\n",
5543                       intel_dp->aux.name, connector->kdev->kobj.name);
5544
5545         intel_dp->aux.dev = connector->kdev;
5546         ret = drm_dp_aux_register(&intel_dp->aux);
5547         if (!ret)
5548                 drm_dp_cec_register_connector(&intel_dp->aux,
5549                                               connector->name, dev->dev);
5550         return ret;
5551 }
5552
5553 static void
5554 intel_dp_connector_unregister(struct drm_connector *connector)
5555 {
5556         struct intel_dp *intel_dp = intel_attached_dp(connector);
5557
5558         drm_dp_cec_unregister_connector(&intel_dp->aux);
5559         drm_dp_aux_unregister(&intel_dp->aux);
5560         intel_connector_unregister(connector);
5561 }
5562
5563 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5564 {
5565         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5566         struct intel_dp *intel_dp = &intel_dig_port->dp;
5567
5568         intel_dp_mst_encoder_cleanup(intel_dig_port);
5569         if (intel_dp_is_edp(intel_dp)) {
5570                 intel_wakeref_t wakeref;
5571
5572                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5573                 /*
5574                  * vdd might still be enabled do to the delayed vdd off.
5575                  * Make sure vdd is actually turned off here.
5576                  */
5577                 with_pps_lock(intel_dp, wakeref)
5578                         edp_panel_vdd_off_sync(intel_dp);
5579
5580                 if (intel_dp->edp_notifier.notifier_call) {
5581                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5582                         intel_dp->edp_notifier.notifier_call = NULL;
5583                 }
5584         }
5585
5586         intel_dp_aux_fini(intel_dp);
5587 }
5588
5589 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5590 {
5591         intel_dp_encoder_flush_work(encoder);
5592
5593         drm_encoder_cleanup(encoder);
5594         kfree(enc_to_dig_port(encoder));
5595 }
5596
5597 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5598 {
5599         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5600         intel_wakeref_t wakeref;
5601
5602         if (!intel_dp_is_edp(intel_dp))
5603                 return;
5604
5605         /*
5606          * vdd might still be enabled do to the delayed vdd off.
5607          * Make sure vdd is actually turned off here.
5608          */
5609         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5610         with_pps_lock(intel_dp, wakeref)
5611                 edp_panel_vdd_off_sync(intel_dp);
5612 }
5613
5614 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5615 {
5616         long ret;
5617
5618 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5619         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5620                                                msecs_to_jiffies(timeout));
5621
5622         if (!ret)
5623                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5624 }
5625
5626 static
5627 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5628                                 u8 *an)
5629 {
5630         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5631         static const struct drm_dp_aux_msg msg = {
5632                 .request = DP_AUX_NATIVE_WRITE,
5633                 .address = DP_AUX_HDCP_AKSV,
5634                 .size = DRM_HDCP_KSV_LEN,
5635         };
5636         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5637         ssize_t dpcd_ret;
5638         int ret;
5639
5640         /* Output An first, that's easy */
5641         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5642                                      an, DRM_HDCP_AN_LEN);
5643         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5644                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5645                               dpcd_ret);
5646                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5647         }
5648
5649         /*
5650          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5651          * order to get it on the wire, we need to create the AUX header as if
5652          * we were writing the data, and then tickle the hardware to output the
5653          * data once the header is sent out.
5654          */
5655         intel_dp_aux_header(txbuf, &msg);
5656
5657         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5658                                 rxbuf, sizeof(rxbuf),
5659                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5660         if (ret < 0) {
5661                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5662                 return ret;
5663         } else if (ret == 0) {
5664                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5665                 return -EIO;
5666         }
5667
5668         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5669         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5670                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5671                               reply);
5672                 return -EIO;
5673         }
5674         return 0;
5675 }
5676
5677 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5678                                    u8 *bksv)
5679 {
5680         ssize_t ret;
5681         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5682                                DRM_HDCP_KSV_LEN);
5683         if (ret != DRM_HDCP_KSV_LEN) {
5684                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5685                 return ret >= 0 ? -EIO : ret;
5686         }
5687         return 0;
5688 }
5689
5690 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5691                                       u8 *bstatus)
5692 {
5693         ssize_t ret;
5694         /*
5695          * For some reason the HDMI and DP HDCP specs call this register
5696          * definition by different names. In the HDMI spec, it's called BSTATUS,
5697          * but in DP it's called BINFO.
5698          */
5699         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5700                                bstatus, DRM_HDCP_BSTATUS_LEN);
5701         if (ret != DRM_HDCP_BSTATUS_LEN) {
5702                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5703                 return ret >= 0 ? -EIO : ret;
5704         }
5705         return 0;
5706 }
5707
5708 static
5709 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5710                              u8 *bcaps)
5711 {
5712         ssize_t ret;
5713
5714         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5715                                bcaps, 1);
5716         if (ret != 1) {
5717                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5718                 return ret >= 0 ? -EIO : ret;
5719         }
5720
5721         return 0;
5722 }
5723
5724 static
5725 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5726                                    bool *repeater_present)
5727 {
5728         ssize_t ret;
5729         u8 bcaps;
5730
5731         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5732         if (ret)
5733                 return ret;
5734
5735         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5736         return 0;
5737 }
5738
5739 static
5740 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5741                                 u8 *ri_prime)
5742 {
5743         ssize_t ret;
5744         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5745                                ri_prime, DRM_HDCP_RI_LEN);
5746         if (ret != DRM_HDCP_RI_LEN) {
5747                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5748                 return ret >= 0 ? -EIO : ret;
5749         }
5750         return 0;
5751 }
5752
5753 static
5754 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5755                                  bool *ksv_ready)
5756 {
5757         ssize_t ret;
5758         u8 bstatus;
5759         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5760                                &bstatus, 1);
5761         if (ret != 1) {
5762                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5763                 return ret >= 0 ? -EIO : ret;
5764         }
5765         *ksv_ready = bstatus & DP_BSTATUS_READY;
5766         return 0;
5767 }
5768
5769 static
5770 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5771                                 int num_downstream, u8 *ksv_fifo)
5772 {
5773         ssize_t ret;
5774         int i;
5775
5776         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5777         for (i = 0; i < num_downstream; i += 3) {
5778                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5779                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5780                                        DP_AUX_HDCP_KSV_FIFO,
5781                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5782                                        len);
5783                 if (ret != len) {
5784                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5785                                       i, ret);
5786                         return ret >= 0 ? -EIO : ret;
5787                 }
5788         }
5789         return 0;
5790 }
5791
5792 static
5793 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5794                                     int i, u32 *part)
5795 {
5796         ssize_t ret;
5797
5798         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5799                 return -EINVAL;
5800
5801         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5802                                DP_AUX_HDCP_V_PRIME(i), part,
5803                                DRM_HDCP_V_PRIME_PART_LEN);
5804         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5805                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5806                 return ret >= 0 ? -EIO : ret;
5807         }
5808         return 0;
5809 }
5810
5811 static
5812 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5813                                     bool enable)
5814 {
5815         /* Not used for single stream DisplayPort setups */
5816         return 0;
5817 }
5818
5819 static
5820 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5821 {
5822         ssize_t ret;
5823         u8 bstatus;
5824
5825         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5826                                &bstatus, 1);
5827         if (ret != 1) {
5828                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5829                 return false;
5830         }
5831
5832         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5833 }
5834
5835 static
5836 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5837                           bool *hdcp_capable)
5838 {
5839         ssize_t ret;
5840         u8 bcaps;
5841
5842         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5843         if (ret)
5844                 return ret;
5845
5846         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5847         return 0;
5848 }
5849
5850 struct hdcp2_dp_errata_stream_type {
5851         u8      msg_id;
5852         u8      stream_type;
5853 } __packed;
5854
5855 struct hdcp2_dp_msg_data {
5856         u8 msg_id;
5857         u32 offset;
5858         bool msg_detectable;
5859         u32 timeout;
5860         u32 timeout2; /* Added for non_paired situation */
5861 };
5862
5863 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
5864         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
5865         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
5866           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
5867         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
5868           false, 0, 0 },
5869         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
5870           false, 0, 0 },
5871         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
5872           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
5873           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
5874         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
5875           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
5876           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
5877         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
5878         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
5879           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
5880         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
5881           0, 0 },
5882         { HDCP_2_2_REP_SEND_RECVID_LIST,
5883           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
5884           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
5885         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
5886           0, 0 },
5887         { HDCP_2_2_REP_STREAM_MANAGE,
5888           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
5889           0, 0 },
5890         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
5891           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
5892 /* local define to shovel this through the write_2_2 interface */
5893 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
5894         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
5895           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
5896           0, 0 },
5897 };
5898
5899 static inline
5900 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
5901                                   u8 *rx_status)
5902 {
5903         ssize_t ret;
5904
5905         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5906                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
5907                                HDCP_2_2_DP_RXSTATUS_LEN);
5908         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
5909                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5910                 return ret >= 0 ? -EIO : ret;
5911         }
5912
5913         return 0;
5914 }
5915
5916 static
5917 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
5918                                   u8 msg_id, bool *msg_ready)
5919 {
5920         u8 rx_status;
5921         int ret;
5922
5923         *msg_ready = false;
5924         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
5925         if (ret < 0)
5926                 return ret;
5927
5928         switch (msg_id) {
5929         case HDCP_2_2_AKE_SEND_HPRIME:
5930                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
5931                         *msg_ready = true;
5932                 break;
5933         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
5934                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
5935                         *msg_ready = true;
5936                 break;
5937         case HDCP_2_2_REP_SEND_RECVID_LIST:
5938                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
5939                         *msg_ready = true;
5940                 break;
5941         default:
5942                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
5943                 return -EINVAL;
5944         }
5945
5946         return 0;
5947 }
5948
5949 static ssize_t
5950 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
5951                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
5952 {
5953         struct intel_dp *dp = &intel_dig_port->dp;
5954         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5955         u8 msg_id = hdcp2_msg_data->msg_id;
5956         int ret, timeout;
5957         bool msg_ready = false;
5958
5959         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
5960                 timeout = hdcp2_msg_data->timeout2;
5961         else
5962                 timeout = hdcp2_msg_data->timeout;
5963
5964         /*
5965          * There is no way to detect the CERT, LPRIME and STREAM_READY
5966          * availability. So Wait for timeout and read the msg.
5967          */
5968         if (!hdcp2_msg_data->msg_detectable) {
5969                 mdelay(timeout);
5970                 ret = 0;
5971         } else {
5972                 /*
5973                  * As we want to check the msg availability at timeout, Ignoring
5974                  * the timeout at wait for CP_IRQ.
5975                  */
5976                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
5977                 ret = hdcp2_detect_msg_availability(intel_dig_port,
5978                                                     msg_id, &msg_ready);
5979                 if (!msg_ready)
5980                         ret = -ETIMEDOUT;
5981         }
5982
5983         if (ret)
5984                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
5985                               hdcp2_msg_data->msg_id, ret, timeout);
5986
5987         return ret;
5988 }
5989
5990 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
5991 {
5992         int i;
5993
5994         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
5995                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
5996                         return &hdcp2_dp_msg_data[i];
5997
5998         return NULL;
5999 }
6000
6001 static
6002 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6003                              void *buf, size_t size)
6004 {
6005         struct intel_dp *dp = &intel_dig_port->dp;
6006         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6007         unsigned int offset;
6008         u8 *byte = buf;
6009         ssize_t ret, bytes_to_write, len;
6010         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6011
6012         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6013         if (!hdcp2_msg_data)
6014                 return -EINVAL;
6015
6016         offset = hdcp2_msg_data->offset;
6017
6018         /* No msg_id in DP HDCP2.2 msgs */
6019         bytes_to_write = size - 1;
6020         byte++;
6021
6022         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6023
6024         while (bytes_to_write) {
6025                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6026                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6027
6028                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6029                                         offset, (void *)byte, len);
6030                 if (ret < 0)
6031                         return ret;
6032
6033                 bytes_to_write -= ret;
6034                 byte += ret;
6035                 offset += ret;
6036         }
6037
6038         return size;
6039 }
6040
6041 static
6042 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6043 {
6044         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6045         u32 dev_cnt;
6046         ssize_t ret;
6047
6048         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6049                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6050                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6051         if (ret != HDCP_2_2_RXINFO_LEN)
6052                 return ret >= 0 ? -EIO : ret;
6053
6054         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6055                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6056
6057         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6058                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6059
6060         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6061                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6062                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6063
6064         return ret;
6065 }
6066
6067 static
6068 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6069                             u8 msg_id, void *buf, size_t size)
6070 {
6071         unsigned int offset;
6072         u8 *byte = buf;
6073         ssize_t ret, bytes_to_recv, len;
6074         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6075
6076         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6077         if (!hdcp2_msg_data)
6078                 return -EINVAL;
6079         offset = hdcp2_msg_data->offset;
6080
6081         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6082         if (ret < 0)
6083                 return ret;
6084
6085         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6086                 ret = get_receiver_id_list_size(intel_dig_port);
6087                 if (ret < 0)
6088                         return ret;
6089
6090                 size = ret;
6091         }
6092         bytes_to_recv = size - 1;
6093
6094         /* DP adaptation msgs has no msg_id */
6095         byte++;
6096
6097         while (bytes_to_recv) {
6098                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6099                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6100
6101                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6102                                        (void *)byte, len);
6103                 if (ret < 0) {
6104                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6105                         return ret;
6106                 }
6107
6108                 bytes_to_recv -= ret;
6109                 byte += ret;
6110                 offset += ret;
6111         }
6112         byte = buf;
6113         *byte = msg_id;
6114
6115         return size;
6116 }
6117
6118 static
6119 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6120                                       bool is_repeater, u8 content_type)
6121 {
6122         struct hdcp2_dp_errata_stream_type stream_type_msg;
6123
6124         if (is_repeater)
6125                 return 0;
6126
6127         /*
6128          * Errata for DP: As Stream type is used for encryption, Receiver
6129          * should be communicated with stream type for the decryption of the
6130          * content.
6131          * Repeater will be communicated with stream type as a part of it's
6132          * auth later in time.
6133          */
6134         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6135         stream_type_msg.stream_type = content_type;
6136
6137         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6138                                         sizeof(stream_type_msg));
6139 }
6140
6141 static
6142 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6143 {
6144         u8 rx_status;
6145         int ret;
6146
6147         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6148         if (ret)
6149                 return ret;
6150
6151         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6152                 ret = HDCP_REAUTH_REQUEST;
6153         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6154                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6155         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6156                 ret = HDCP_TOPOLOGY_CHANGE;
6157
6158         return ret;
6159 }
6160
6161 static
6162 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6163                            bool *capable)
6164 {
6165         u8 rx_caps[3];
6166         int ret;
6167
6168         *capable = false;
6169         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6170                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6171                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6172         if (ret != HDCP_2_2_RXCAPS_LEN)
6173                 return ret >= 0 ? -EIO : ret;
6174
6175         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6176             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6177                 *capable = true;
6178
6179         return 0;
6180 }
6181
6182 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6183         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6184         .read_bksv = intel_dp_hdcp_read_bksv,
6185         .read_bstatus = intel_dp_hdcp_read_bstatus,
6186         .repeater_present = intel_dp_hdcp_repeater_present,
6187         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6188         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6189         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6190         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6191         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6192         .check_link = intel_dp_hdcp_check_link,
6193         .hdcp_capable = intel_dp_hdcp_capable,
6194         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6195         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6196         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6197         .check_2_2_link = intel_dp_hdcp2_check_link,
6198         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6199         .protocol = HDCP_PROTOCOL_DP,
6200 };
6201
6202 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6203 {
6204         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6205         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6206
6207         lockdep_assert_held(&dev_priv->pps_mutex);
6208
6209         if (!edp_have_panel_vdd(intel_dp))
6210                 return;
6211
6212         /*
6213          * The VDD bit needs a power domain reference, so if the bit is
6214          * already enabled when we boot or resume, grab this reference and
6215          * schedule a vdd off, so we don't hold on to the reference
6216          * indefinitely.
6217          */
6218         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6219         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6220
6221         edp_panel_vdd_schedule_off(intel_dp);
6222 }
6223
6224 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6225 {
6226         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6227         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6228         enum pipe pipe;
6229
6230         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6231                                   encoder->port, &pipe))
6232                 return pipe;
6233
6234         return INVALID_PIPE;
6235 }
6236
6237 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6238 {
6239         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6240         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6241         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6242         intel_wakeref_t wakeref;
6243
6244         if (!HAS_DDI(dev_priv))
6245                 intel_dp->DP = I915_READ(intel_dp->output_reg);
6246
6247         if (lspcon->active)
6248                 lspcon_resume(lspcon);
6249
6250         intel_dp->reset_link_params = true;
6251
6252         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6253             !intel_dp_is_edp(intel_dp))
6254                 return;
6255
6256         with_pps_lock(intel_dp, wakeref) {
6257                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6258                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6259
6260                 if (intel_dp_is_edp(intel_dp)) {
6261                         /*
6262                          * Reinit the power sequencer, in case BIOS did
6263                          * something nasty with it.
6264                          */
6265                         intel_dp_pps_init(intel_dp);
6266                         intel_edp_panel_vdd_sanitize(intel_dp);
6267                 }
6268         }
6269 }
6270
6271 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6272         .force = intel_dp_force,
6273         .fill_modes = drm_helper_probe_single_connector_modes,
6274         .atomic_get_property = intel_digital_connector_atomic_get_property,
6275         .atomic_set_property = intel_digital_connector_atomic_set_property,
6276         .late_register = intel_dp_connector_register,
6277         .early_unregister = intel_dp_connector_unregister,
6278         .destroy = intel_connector_destroy,
6279         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6280         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6281 };
6282
6283 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6284         .detect_ctx = intel_dp_detect,
6285         .get_modes = intel_dp_get_modes,
6286         .mode_valid = intel_dp_mode_valid,
6287         .atomic_check = intel_digital_connector_atomic_check,
6288 };
6289
6290 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6291         .reset = intel_dp_encoder_reset,
6292         .destroy = intel_dp_encoder_destroy,
6293 };
6294
6295 enum irqreturn
6296 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6297 {
6298         struct intel_dp *intel_dp = &intel_dig_port->dp;
6299
6300         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6301                 /*
6302                  * vdd off can generate a long pulse on eDP which
6303                  * would require vdd on to handle it, and thus we
6304                  * would end up in an endless cycle of
6305                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6306                  */
6307                 DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n",
6308                               intel_dig_port->base.base.base.id,
6309                               intel_dig_port->base.base.name);
6310                 return IRQ_HANDLED;
6311         }
6312
6313         DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n",
6314                       intel_dig_port->base.base.base.id,
6315                       intel_dig_port->base.base.name,
6316                       long_hpd ? "long" : "short");
6317
6318         if (long_hpd) {
6319                 intel_dp->reset_link_params = true;
6320                 return IRQ_NONE;
6321         }
6322
6323         if (intel_dp->is_mst) {
6324                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6325                         /*
6326                          * If we were in MST mode, and device is not
6327                          * there, get out of MST mode
6328                          */
6329                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6330                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6331                         intel_dp->is_mst = false;
6332                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6333                                                         intel_dp->is_mst);
6334
6335                         return IRQ_NONE;
6336                 }
6337         }
6338
6339         if (!intel_dp->is_mst) {
6340                 bool handled;
6341
6342                 handled = intel_dp_short_pulse(intel_dp);
6343
6344                 if (!handled)
6345                         return IRQ_NONE;
6346         }
6347
6348         return IRQ_HANDLED;
6349 }
6350
6351 /* check the VBT to see whether the eDP is on another port */
6352 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6353 {
6354         /*
6355          * eDP not supported on g4x. so bail out early just
6356          * for a bit extra safety in case the VBT is bonkers.
6357          */
6358         if (INTEL_GEN(dev_priv) < 5)
6359                 return false;
6360
6361         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6362                 return true;
6363
6364         return intel_bios_is_port_edp(dev_priv, port);
6365 }
6366
6367 static void
6368 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6369 {
6370         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6371         enum port port = dp_to_dig_port(intel_dp)->base.port;
6372
6373         if (!IS_G4X(dev_priv) && port != PORT_A)
6374                 intel_attach_force_audio_property(connector);
6375
6376         intel_attach_broadcast_rgb_property(connector);
6377         if (HAS_GMCH(dev_priv))
6378                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6379         else if (INTEL_GEN(dev_priv) >= 5)
6380                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6381
6382         if (intel_dp_is_edp(intel_dp)) {
6383                 u32 allowed_scalers;
6384
6385                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6386                 if (!HAS_GMCH(dev_priv))
6387                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6388
6389                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6390
6391                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6392
6393         }
6394 }
6395
6396 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6397 {
6398         intel_dp->panel_power_off_time = ktime_get_boottime();
6399         intel_dp->last_power_on = jiffies;
6400         intel_dp->last_backlight_off = jiffies;
6401 }
6402
6403 static void
6404 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6405 {
6406         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6407         u32 pp_on, pp_off, pp_ctl;
6408         struct pps_registers regs;
6409
6410         intel_pps_get_registers(intel_dp, &regs);
6411
6412         pp_ctl = ironlake_get_pp_control(intel_dp);
6413
6414         /* Ensure PPS is unlocked */
6415         if (!HAS_DDI(dev_priv))
6416                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6417
6418         pp_on = I915_READ(regs.pp_on);
6419         pp_off = I915_READ(regs.pp_off);
6420
6421         /* Pull timing values out of registers */
6422         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6423         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6424         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6425         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6426
6427         if (i915_mmio_reg_valid(regs.pp_div)) {
6428                 u32 pp_div;
6429
6430                 pp_div = I915_READ(regs.pp_div);
6431
6432                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6433         } else {
6434                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6435         }
6436 }
6437
6438 static void
6439 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6440 {
6441         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6442                       state_name,
6443                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6444 }
6445
6446 static void
6447 intel_pps_verify_state(struct intel_dp *intel_dp)
6448 {
6449         struct edp_power_seq hw;
6450         struct edp_power_seq *sw = &intel_dp->pps_delays;
6451
6452         intel_pps_readout_hw_state(intel_dp, &hw);
6453
6454         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6455             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6456                 DRM_ERROR("PPS state mismatch\n");
6457                 intel_pps_dump_state("sw", sw);
6458                 intel_pps_dump_state("hw", &hw);
6459         }
6460 }
6461
6462 static void
6463 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6464 {
6465         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6466         struct edp_power_seq cur, vbt, spec,
6467                 *final = &intel_dp->pps_delays;
6468
6469         lockdep_assert_held(&dev_priv->pps_mutex);
6470
6471         /* already initialized? */
6472         if (final->t11_t12 != 0)
6473                 return;
6474
6475         intel_pps_readout_hw_state(intel_dp, &cur);
6476
6477         intel_pps_dump_state("cur", &cur);
6478
6479         vbt = dev_priv->vbt.edp.pps;
6480         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6481          * of 500ms appears to be too short. Ocassionally the panel
6482          * just fails to power back on. Increasing the delay to 800ms
6483          * seems sufficient to avoid this problem.
6484          */
6485         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6486                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6487                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6488                               vbt.t11_t12);
6489         }
6490         /* T11_T12 delay is special and actually in units of 100ms, but zero
6491          * based in the hw (so we need to add 100 ms). But the sw vbt
6492          * table multiplies it with 1000 to make it in units of 100usec,
6493          * too. */
6494         vbt.t11_t12 += 100 * 10;
6495
6496         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6497          * our hw here, which are all in 100usec. */
6498         spec.t1_t3 = 210 * 10;
6499         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6500         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6501         spec.t10 = 500 * 10;
6502         /* This one is special and actually in units of 100ms, but zero
6503          * based in the hw (so we need to add 100 ms). But the sw vbt
6504          * table multiplies it with 1000 to make it in units of 100usec,
6505          * too. */
6506         spec.t11_t12 = (510 + 100) * 10;
6507
6508         intel_pps_dump_state("vbt", &vbt);
6509
6510         /* Use the max of the register settings and vbt. If both are
6511          * unset, fall back to the spec limits. */
6512 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6513                                        spec.field : \
6514                                        max(cur.field, vbt.field))
6515         assign_final(t1_t3);
6516         assign_final(t8);
6517         assign_final(t9);
6518         assign_final(t10);
6519         assign_final(t11_t12);
6520 #undef assign_final
6521
6522 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6523         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6524         intel_dp->backlight_on_delay = get_delay(t8);
6525         intel_dp->backlight_off_delay = get_delay(t9);
6526         intel_dp->panel_power_down_delay = get_delay(t10);
6527         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6528 #undef get_delay
6529
6530         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6531                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6532                       intel_dp->panel_power_cycle_delay);
6533
6534         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6535                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6536
6537         /*
6538          * We override the HW backlight delays to 1 because we do manual waits
6539          * on them. For T8, even BSpec recommends doing it. For T9, if we
6540          * don't do this, we'll end up waiting for the backlight off delay
6541          * twice: once when we do the manual sleep, and once when we disable
6542          * the panel and wait for the PP_STATUS bit to become zero.
6543          */
6544         final->t8 = 1;
6545         final->t9 = 1;
6546
6547         /*
6548          * HW has only a 100msec granularity for t11_t12 so round it up
6549          * accordingly.
6550          */
6551         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6552 }
6553
6554 static void
6555 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6556                                               bool force_disable_vdd)
6557 {
6558         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6559         u32 pp_on, pp_off, port_sel = 0;
6560         int div = dev_priv->rawclk_freq / 1000;
6561         struct pps_registers regs;
6562         enum port port = dp_to_dig_port(intel_dp)->base.port;
6563         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6564
6565         lockdep_assert_held(&dev_priv->pps_mutex);
6566
6567         intel_pps_get_registers(intel_dp, &regs);
6568
6569         /*
6570          * On some VLV machines the BIOS can leave the VDD
6571          * enabled even on power sequencers which aren't
6572          * hooked up to any port. This would mess up the
6573          * power domain tracking the first time we pick
6574          * one of these power sequencers for use since
6575          * edp_panel_vdd_on() would notice that the VDD was
6576          * already on and therefore wouldn't grab the power
6577          * domain reference. Disable VDD first to avoid this.
6578          * This also avoids spuriously turning the VDD on as
6579          * soon as the new power sequencer gets initialized.
6580          */
6581         if (force_disable_vdd) {
6582                 u32 pp = ironlake_get_pp_control(intel_dp);
6583
6584                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6585
6586                 if (pp & EDP_FORCE_VDD)
6587                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6588
6589                 pp &= ~EDP_FORCE_VDD;
6590
6591                 I915_WRITE(regs.pp_ctrl, pp);
6592         }
6593
6594         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6595                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6596         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6597                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6598
6599         /* Haswell doesn't have any port selection bits for the panel
6600          * power sequencer any more. */
6601         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6602                 port_sel = PANEL_PORT_SELECT_VLV(port);
6603         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6604                 switch (port) {
6605                 case PORT_A:
6606                         port_sel = PANEL_PORT_SELECT_DPA;
6607                         break;
6608                 case PORT_C:
6609                         port_sel = PANEL_PORT_SELECT_DPC;
6610                         break;
6611                 case PORT_D:
6612                         port_sel = PANEL_PORT_SELECT_DPD;
6613                         break;
6614                 default:
6615                         MISSING_CASE(port);
6616                         break;
6617                 }
6618         }
6619
6620         pp_on |= port_sel;
6621
6622         I915_WRITE(regs.pp_on, pp_on);
6623         I915_WRITE(regs.pp_off, pp_off);
6624
6625         /*
6626          * Compute the divisor for the pp clock, simply match the Bspec formula.
6627          */
6628         if (i915_mmio_reg_valid(regs.pp_div)) {
6629                 I915_WRITE(regs.pp_div,
6630                            REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6631                            REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6632         } else {
6633                 u32 pp_ctl;
6634
6635                 pp_ctl = I915_READ(regs.pp_ctrl);
6636                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6637                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6638                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6639         }
6640
6641         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6642                       I915_READ(regs.pp_on),
6643                       I915_READ(regs.pp_off),
6644                       i915_mmio_reg_valid(regs.pp_div) ?
6645                       I915_READ(regs.pp_div) :
6646                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6647 }
6648
6649 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6650 {
6651         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6652
6653         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6654                 vlv_initial_power_sequencer_setup(intel_dp);
6655         } else {
6656                 intel_dp_init_panel_power_sequencer(intel_dp);
6657                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6658         }
6659 }
6660
6661 /**
6662  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6663  * @dev_priv: i915 device
6664  * @crtc_state: a pointer to the active intel_crtc_state
6665  * @refresh_rate: RR to be programmed
6666  *
6667  * This function gets called when refresh rate (RR) has to be changed from
6668  * one frequency to another. Switches can be between high and low RR
6669  * supported by the panel or to any other RR based on media playback (in
6670  * this case, RR value needs to be passed from user space).
6671  *
6672  * The caller of this function needs to take a lock on dev_priv->drrs.
6673  */
6674 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6675                                     const struct intel_crtc_state *crtc_state,
6676                                     int refresh_rate)
6677 {
6678         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6680         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6681
6682         if (refresh_rate <= 0) {
6683                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6684                 return;
6685         }
6686
6687         if (intel_dp == NULL) {
6688                 DRM_DEBUG_KMS("DRRS not supported.\n");
6689                 return;
6690         }
6691
6692         if (!intel_crtc) {
6693                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6694                 return;
6695         }
6696
6697         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6698                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6699                 return;
6700         }
6701
6702         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6703                         refresh_rate)
6704                 index = DRRS_LOW_RR;
6705
6706         if (index == dev_priv->drrs.refresh_rate_type) {
6707                 DRM_DEBUG_KMS(
6708                         "DRRS requested for previously set RR...ignoring\n");
6709                 return;
6710         }
6711
6712         if (!crtc_state->base.active) {
6713                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6714                 return;
6715         }
6716
6717         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6718                 switch (index) {
6719                 case DRRS_HIGH_RR:
6720                         intel_dp_set_m_n(crtc_state, M1_N1);
6721                         break;
6722                 case DRRS_LOW_RR:
6723                         intel_dp_set_m_n(crtc_state, M2_N2);
6724                         break;
6725                 case DRRS_MAX_RR:
6726                 default:
6727                         DRM_ERROR("Unsupported refreshrate type\n");
6728                 }
6729         } else if (INTEL_GEN(dev_priv) > 6) {
6730                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6731                 u32 val;
6732
6733                 val = I915_READ(reg);
6734                 if (index > DRRS_HIGH_RR) {
6735                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6736                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6737                         else
6738                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6739                 } else {
6740                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6741                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6742                         else
6743                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6744                 }
6745                 I915_WRITE(reg, val);
6746         }
6747
6748         dev_priv->drrs.refresh_rate_type = index;
6749
6750         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6751 }
6752
6753 /**
6754  * intel_edp_drrs_enable - init drrs struct if supported
6755  * @intel_dp: DP struct
6756  * @crtc_state: A pointer to the active crtc state.
6757  *
6758  * Initializes frontbuffer_bits and drrs.dp
6759  */
6760 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6761                            const struct intel_crtc_state *crtc_state)
6762 {
6763         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6764
6765         if (!crtc_state->has_drrs) {
6766                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6767                 return;
6768         }
6769
6770         if (dev_priv->psr.enabled) {
6771                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6772                 return;
6773         }
6774
6775         mutex_lock(&dev_priv->drrs.mutex);
6776         if (dev_priv->drrs.dp) {
6777                 DRM_DEBUG_KMS("DRRS already enabled\n");
6778                 goto unlock;
6779         }
6780
6781         dev_priv->drrs.busy_frontbuffer_bits = 0;
6782
6783         dev_priv->drrs.dp = intel_dp;
6784
6785 unlock:
6786         mutex_unlock(&dev_priv->drrs.mutex);
6787 }
6788
6789 /**
6790  * intel_edp_drrs_disable - Disable DRRS
6791  * @intel_dp: DP struct
6792  * @old_crtc_state: Pointer to old crtc_state.
6793  *
6794  */
6795 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6796                             const struct intel_crtc_state *old_crtc_state)
6797 {
6798         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6799
6800         if (!old_crtc_state->has_drrs)
6801                 return;
6802
6803         mutex_lock(&dev_priv->drrs.mutex);
6804         if (!dev_priv->drrs.dp) {
6805                 mutex_unlock(&dev_priv->drrs.mutex);
6806                 return;
6807         }
6808
6809         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6810                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6811                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6812
6813         dev_priv->drrs.dp = NULL;
6814         mutex_unlock(&dev_priv->drrs.mutex);
6815
6816         cancel_delayed_work_sync(&dev_priv->drrs.work);
6817 }
6818
6819 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6820 {
6821         struct drm_i915_private *dev_priv =
6822                 container_of(work, typeof(*dev_priv), drrs.work.work);
6823         struct intel_dp *intel_dp;
6824
6825         mutex_lock(&dev_priv->drrs.mutex);
6826
6827         intel_dp = dev_priv->drrs.dp;
6828
6829         if (!intel_dp)
6830                 goto unlock;
6831
6832         /*
6833          * The delayed work can race with an invalidate hence we need to
6834          * recheck.
6835          */
6836
6837         if (dev_priv->drrs.busy_frontbuffer_bits)
6838                 goto unlock;
6839
6840         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6841                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6842
6843                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6844                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6845         }
6846
6847 unlock:
6848         mutex_unlock(&dev_priv->drrs.mutex);
6849 }
6850
6851 /**
6852  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6853  * @dev_priv: i915 device
6854  * @frontbuffer_bits: frontbuffer plane tracking bits
6855  *
6856  * This function gets called everytime rendering on the given planes start.
6857  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6858  *
6859  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6860  */
6861 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6862                                unsigned int frontbuffer_bits)
6863 {
6864         struct drm_crtc *crtc;
6865         enum pipe pipe;
6866
6867         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6868                 return;
6869
6870         cancel_delayed_work(&dev_priv->drrs.work);
6871
6872         mutex_lock(&dev_priv->drrs.mutex);
6873         if (!dev_priv->drrs.dp) {
6874                 mutex_unlock(&dev_priv->drrs.mutex);
6875                 return;
6876         }
6877
6878         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6879         pipe = to_intel_crtc(crtc)->pipe;
6880
6881         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6882         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6883
6884         /* invalidate means busy screen hence upclock */
6885         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6886                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6887                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6888
6889         mutex_unlock(&dev_priv->drrs.mutex);
6890 }
6891
6892 /**
6893  * intel_edp_drrs_flush - Restart Idleness DRRS
6894  * @dev_priv: i915 device
6895  * @frontbuffer_bits: frontbuffer plane tracking bits
6896  *
6897  * This function gets called every time rendering on the given planes has
6898  * completed or flip on a crtc is completed. So DRRS should be upclocked
6899  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6900  * if no other planes are dirty.
6901  *
6902  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6903  */
6904 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6905                           unsigned int frontbuffer_bits)
6906 {
6907         struct drm_crtc *crtc;
6908         enum pipe pipe;
6909
6910         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6911                 return;
6912
6913         cancel_delayed_work(&dev_priv->drrs.work);
6914
6915         mutex_lock(&dev_priv->drrs.mutex);
6916         if (!dev_priv->drrs.dp) {
6917                 mutex_unlock(&dev_priv->drrs.mutex);
6918                 return;
6919         }
6920
6921         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6922         pipe = to_intel_crtc(crtc)->pipe;
6923
6924         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6925         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6926
6927         /* flush means busy screen hence upclock */
6928         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6929                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6930                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6931
6932         /*
6933          * flush also means no more activity hence schedule downclock, if all
6934          * other fbs are quiescent too
6935          */
6936         if (!dev_priv->drrs.busy_frontbuffer_bits)
6937                 schedule_delayed_work(&dev_priv->drrs.work,
6938                                 msecs_to_jiffies(1000));
6939         mutex_unlock(&dev_priv->drrs.mutex);
6940 }
6941
6942 /**
6943  * DOC: Display Refresh Rate Switching (DRRS)
6944  *
6945  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6946  * which enables swtching between low and high refresh rates,
6947  * dynamically, based on the usage scenario. This feature is applicable
6948  * for internal panels.
6949  *
6950  * Indication that the panel supports DRRS is given by the panel EDID, which
6951  * would list multiple refresh rates for one resolution.
6952  *
6953  * DRRS is of 2 types - static and seamless.
6954  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6955  * (may appear as a blink on screen) and is used in dock-undock scenario.
6956  * Seamless DRRS involves changing RR without any visual effect to the user
6957  * and can be used during normal system usage. This is done by programming
6958  * certain registers.
6959  *
6960  * Support for static/seamless DRRS may be indicated in the VBT based on
6961  * inputs from the panel spec.
6962  *
6963  * DRRS saves power by switching to low RR based on usage scenarios.
6964  *
6965  * The implementation is based on frontbuffer tracking implementation.  When
6966  * there is a disturbance on the screen triggered by user activity or a periodic
6967  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6968  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6969  * made.
6970  *
6971  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6972  * and intel_edp_drrs_flush() are called.
6973  *
6974  * DRRS can be further extended to support other internal panels and also
6975  * the scenario of video playback wherein RR is set based on the rate
6976  * requested by userspace.
6977  */
6978
6979 /**
6980  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6981  * @connector: eDP connector
6982  * @fixed_mode: preferred mode of panel
6983  *
6984  * This function is  called only once at driver load to initialize basic
6985  * DRRS stuff.
6986  *
6987  * Returns:
6988  * Downclock mode if panel supports it, else return NULL.
6989  * DRRS support is determined by the presence of downclock mode (apart
6990  * from VBT setting).
6991  */
6992 static struct drm_display_mode *
6993 intel_dp_drrs_init(struct intel_connector *connector,
6994                    struct drm_display_mode *fixed_mode)
6995 {
6996         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6997         struct drm_display_mode *downclock_mode = NULL;
6998
6999         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7000         mutex_init(&dev_priv->drrs.mutex);
7001
7002         if (INTEL_GEN(dev_priv) <= 6) {
7003                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7004                 return NULL;
7005         }
7006
7007         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7008                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7009                 return NULL;
7010         }
7011
7012         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7013         if (!downclock_mode) {
7014                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7015                 return NULL;
7016         }
7017
7018         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7019
7020         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7021         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7022         return downclock_mode;
7023 }
7024
7025 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7026                                      struct intel_connector *intel_connector)
7027 {
7028         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7029         struct drm_device *dev = &dev_priv->drm;
7030         struct drm_connector *connector = &intel_connector->base;
7031         struct drm_display_mode *fixed_mode = NULL;
7032         struct drm_display_mode *downclock_mode = NULL;
7033         bool has_dpcd;
7034         enum pipe pipe = INVALID_PIPE;
7035         intel_wakeref_t wakeref;
7036         struct edid *edid;
7037
7038         if (!intel_dp_is_edp(intel_dp))
7039                 return true;
7040
7041         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7042
7043         /*
7044          * On IBX/CPT we may get here with LVDS already registered. Since the
7045          * driver uses the only internal power sequencer available for both
7046          * eDP and LVDS bail out early in this case to prevent interfering
7047          * with an already powered-on LVDS power sequencer.
7048          */
7049         if (intel_get_lvds_encoder(dev_priv)) {
7050                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7051                 DRM_INFO("LVDS was detected, not registering eDP\n");
7052
7053                 return false;
7054         }
7055
7056         with_pps_lock(intel_dp, wakeref) {
7057                 intel_dp_init_panel_power_timestamps(intel_dp);
7058                 intel_dp_pps_init(intel_dp);
7059                 intel_edp_panel_vdd_sanitize(intel_dp);
7060         }
7061
7062         /* Cache DPCD and EDID for edp. */
7063         has_dpcd = intel_edp_init_dpcd(intel_dp);
7064
7065         if (!has_dpcd) {
7066                 /* if this fails, presume the device is a ghost */
7067                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7068                 goto out_vdd_off;
7069         }
7070
7071         mutex_lock(&dev->mode_config.mutex);
7072         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7073         if (edid) {
7074                 if (drm_add_edid_modes(connector, edid)) {
7075                         drm_connector_update_edid_property(connector,
7076                                                                 edid);
7077                 } else {
7078                         kfree(edid);
7079                         edid = ERR_PTR(-EINVAL);
7080                 }
7081         } else {
7082                 edid = ERR_PTR(-ENOENT);
7083         }
7084         intel_connector->edid = edid;
7085
7086         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7087         if (fixed_mode)
7088                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7089
7090         /* fallback to VBT if available for eDP */
7091         if (!fixed_mode)
7092                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7093         mutex_unlock(&dev->mode_config.mutex);
7094
7095         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7096                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7097                 register_reboot_notifier(&intel_dp->edp_notifier);
7098
7099                 /*
7100                  * Figure out the current pipe for the initial backlight setup.
7101                  * If the current pipe isn't valid, try the PPS pipe, and if that
7102                  * fails just assume pipe A.
7103                  */
7104                 pipe = vlv_active_pipe(intel_dp);
7105
7106                 if (pipe != PIPE_A && pipe != PIPE_B)
7107                         pipe = intel_dp->pps_pipe;
7108
7109                 if (pipe != PIPE_A && pipe != PIPE_B)
7110                         pipe = PIPE_A;
7111
7112                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7113                               pipe_name(pipe));
7114         }
7115
7116         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7117         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7118         intel_panel_setup_backlight(connector, pipe);
7119
7120         if (fixed_mode)
7121                 drm_connector_init_panel_orientation_property(
7122                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7123
7124         return true;
7125
7126 out_vdd_off:
7127         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7128         /*
7129          * vdd might still be enabled do to the delayed vdd off.
7130          * Make sure vdd is actually turned off here.
7131          */
7132         with_pps_lock(intel_dp, wakeref)
7133                 edp_panel_vdd_off_sync(intel_dp);
7134
7135         return false;
7136 }
7137
7138 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7139 {
7140         struct intel_connector *intel_connector;
7141         struct drm_connector *connector;
7142
7143         intel_connector = container_of(work, typeof(*intel_connector),
7144                                        modeset_retry_work);
7145         connector = &intel_connector->base;
7146         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7147                       connector->name);
7148
7149         /* Grab the locks before changing connector property*/
7150         mutex_lock(&connector->dev->mode_config.mutex);
7151         /* Set connector link status to BAD and send a Uevent to notify
7152          * userspace to do a modeset.
7153          */
7154         drm_connector_set_link_status_property(connector,
7155                                                DRM_MODE_LINK_STATUS_BAD);
7156         mutex_unlock(&connector->dev->mode_config.mutex);
7157         /* Send Hotplug uevent so userspace can reprobe */
7158         drm_kms_helper_hotplug_event(connector->dev);
7159 }
7160
7161 bool
7162 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7163                         struct intel_connector *intel_connector)
7164 {
7165         struct drm_connector *connector = &intel_connector->base;
7166         struct intel_dp *intel_dp = &intel_dig_port->dp;
7167         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7168         struct drm_device *dev = intel_encoder->base.dev;
7169         struct drm_i915_private *dev_priv = to_i915(dev);
7170         enum port port = intel_encoder->port;
7171         enum phy phy = intel_port_to_phy(dev_priv, port);
7172         int type;
7173
7174         /* Initialize the work for modeset in case of link train failure */
7175         INIT_WORK(&intel_connector->modeset_retry_work,
7176                   intel_dp_modeset_retry_work_fn);
7177
7178         if (WARN(intel_dig_port->max_lanes < 1,
7179                  "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
7180                  intel_dig_port->max_lanes, intel_encoder->base.base.id,
7181                  intel_encoder->base.name))
7182                 return false;
7183
7184         intel_dp_set_source_rates(intel_dp);
7185
7186         intel_dp->reset_link_params = true;
7187         intel_dp->pps_pipe = INVALID_PIPE;
7188         intel_dp->active_pipe = INVALID_PIPE;
7189
7190         /* Preserve the current hw state. */
7191         intel_dp->DP = I915_READ(intel_dp->output_reg);
7192         intel_dp->attached_connector = intel_connector;
7193
7194         if (intel_dp_is_port_edp(dev_priv, port)) {
7195                 /*
7196                  * Currently we don't support eDP on TypeC ports, although in
7197                  * theory it could work on TypeC legacy ports.
7198                  */
7199                 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7200                 type = DRM_MODE_CONNECTOR_eDP;
7201         } else {
7202                 type = DRM_MODE_CONNECTOR_DisplayPort;
7203         }
7204
7205         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7206                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7207
7208         /*
7209          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7210          * for DP the encoder type can be set by the caller to
7211          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7212          */
7213         if (type == DRM_MODE_CONNECTOR_eDP)
7214                 intel_encoder->type = INTEL_OUTPUT_EDP;
7215
7216         /* eDP only on port B and/or C on vlv/chv */
7217         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7218                     intel_dp_is_edp(intel_dp) &&
7219                     port != PORT_B && port != PORT_C))
7220                 return false;
7221
7222         DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n",
7223                       type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7224                       intel_encoder->base.base.id, intel_encoder->base.name);
7225
7226         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7227         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7228
7229         if (!HAS_GMCH(dev_priv))
7230                 connector->interlace_allowed = true;
7231         connector->doublescan_allowed = 0;
7232
7233         if (INTEL_GEN(dev_priv) >= 11)
7234                 connector->ycbcr_420_allowed = true;
7235
7236         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7237
7238         intel_dp_aux_init(intel_dp);
7239
7240         intel_connector_attach_encoder(intel_connector, intel_encoder);
7241
7242         if (HAS_DDI(dev_priv))
7243                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7244         else
7245                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7246
7247         /* init MST on ports that can support it */
7248         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
7249             (port == PORT_B || port == PORT_C ||
7250              port == PORT_D || port == PORT_F))
7251                 intel_dp_mst_encoder_init(intel_dig_port,
7252                                           intel_connector->base.base.id);
7253
7254         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7255                 intel_dp_aux_fini(intel_dp);
7256                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7257                 goto fail;
7258         }
7259
7260         intel_dp_add_properties(intel_dp, connector);
7261
7262         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7263                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7264                 if (ret)
7265                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7266         }
7267
7268         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7269          * 0xd.  Failure to do so will result in spurious interrupts being
7270          * generated on the port when a cable is not attached.
7271          */
7272         if (IS_G45(dev_priv)) {
7273                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7274                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7275         }
7276
7277         return true;
7278
7279 fail:
7280         drm_connector_cleanup(connector);
7281
7282         return false;
7283 }
7284
7285 bool intel_dp_init(struct drm_i915_private *dev_priv,
7286                    i915_reg_t output_reg,
7287                    enum port port)
7288 {
7289         struct intel_digital_port *intel_dig_port;
7290         struct intel_encoder *intel_encoder;
7291         struct drm_encoder *encoder;
7292         struct intel_connector *intel_connector;
7293
7294         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7295         if (!intel_dig_port)
7296                 return false;
7297
7298         intel_connector = intel_connector_alloc();
7299         if (!intel_connector)
7300                 goto err_connector_alloc;
7301
7302         intel_encoder = &intel_dig_port->base;
7303         encoder = &intel_encoder->base;
7304
7305         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7306                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7307                              "DP %c", port_name(port)))
7308                 goto err_encoder_init;
7309
7310         intel_encoder->hotplug = intel_dp_hotplug;
7311         intel_encoder->compute_config = intel_dp_compute_config;
7312         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7313         intel_encoder->get_config = intel_dp_get_config;
7314         intel_encoder->update_pipe = intel_panel_update_backlight;
7315         intel_encoder->suspend = intel_dp_encoder_suspend;
7316         if (IS_CHERRYVIEW(dev_priv)) {
7317                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7318                 intel_encoder->pre_enable = chv_pre_enable_dp;
7319                 intel_encoder->enable = vlv_enable_dp;
7320                 intel_encoder->disable = vlv_disable_dp;
7321                 intel_encoder->post_disable = chv_post_disable_dp;
7322                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7323         } else if (IS_VALLEYVIEW(dev_priv)) {
7324                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7325                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7326                 intel_encoder->enable = vlv_enable_dp;
7327                 intel_encoder->disable = vlv_disable_dp;
7328                 intel_encoder->post_disable = vlv_post_disable_dp;
7329         } else {
7330                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7331                 intel_encoder->enable = g4x_enable_dp;
7332                 intel_encoder->disable = g4x_disable_dp;
7333                 intel_encoder->post_disable = g4x_post_disable_dp;
7334         }
7335
7336         intel_dig_port->dp.output_reg = output_reg;
7337         intel_dig_port->max_lanes = 4;
7338
7339         intel_encoder->type = INTEL_OUTPUT_DP;
7340         intel_encoder->power_domain = intel_port_to_power_domain(port);
7341         if (IS_CHERRYVIEW(dev_priv)) {
7342                 if (port == PORT_D)
7343                         intel_encoder->crtc_mask = 1 << 2;
7344                 else
7345                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7346         } else {
7347                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7348         }
7349         intel_encoder->cloneable = 0;
7350         intel_encoder->port = port;
7351
7352         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7353
7354         if (port != PORT_A)
7355                 intel_infoframe_init(intel_dig_port);
7356
7357         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7358         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7359                 goto err_init_connector;
7360
7361         return true;
7362
7363 err_init_connector:
7364         drm_encoder_cleanup(encoder);
7365 err_encoder_init:
7366         kfree(intel_connector);
7367 err_connector_alloc:
7368         kfree(intel_dig_port);
7369         return false;
7370 }
7371
7372 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7373 {
7374         struct intel_encoder *encoder;
7375
7376         for_each_intel_encoder(&dev_priv->drm, encoder) {
7377                 struct intel_dp *intel_dp;
7378
7379                 if (encoder->type != INTEL_OUTPUT_DDI)
7380                         continue;
7381
7382                 intel_dp = enc_to_intel_dp(&encoder->base);
7383
7384                 if (!intel_dp->can_mst)
7385                         continue;
7386
7387                 if (intel_dp->is_mst)
7388                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7389         }
7390 }
7391
7392 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7393 {
7394         struct intel_encoder *encoder;
7395
7396         for_each_intel_encoder(&dev_priv->drm, encoder) {
7397                 struct intel_dp *intel_dp;
7398                 int ret;
7399
7400                 if (encoder->type != INTEL_OUTPUT_DDI)
7401                         continue;
7402
7403                 intel_dp = enc_to_intel_dp(&encoder->base);
7404
7405                 if (!intel_dp->can_mst)
7406                         continue;
7407
7408                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7409                 if (ret) {
7410                         intel_dp->is_mst = false;
7411                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7412                                                         false);
7413                 }
7414         }
7415 }