drivers/gpu/drm/i915/display/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <drm/drm_fourcc.h>
  42
  43 #include "i915_drv.h"
  44 #include "intel_display_types.h"
  45 #include "intel_fbc.h"
  46 #include "intel_frontbuffer.h"
  47
  48 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  49 {
  50         return HAS_FBC(dev_priv);
  51 }
  52
  53 /*
  54  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  55  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  56  * origin so the x and y offsets can actually fit the registers. As a
  57  * consequence, the fence doesn't really start exactly at the display plane
  58  * address we program because it starts at the real start of the buffer, so we
  59  * have to take this into consideration here.
  60  */
  61 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  62 {
  63         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  64 }
  65
  66 /*
  67  * For SKL+, the plane source size used by the hardware is based on the value we
  68  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  69  * we wrote to PIPESRC.
  70  */
  71 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  72                                             int *width, int *height)
  73 {
  74         if (width)
  75                 *width = cache->plane.src_w;
  76         if (height)
  77                 *height = cache->plane.src_h;
  78 }
  79
  80 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  81                                         struct intel_fbc_state_cache *cache)
  82 {
  83         int lines;
  84
  85         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  86         if (IS_GEN(dev_priv, 7))
  87                 lines = min(lines, 2048);
  88         else if (INTEL_GEN(dev_priv) >= 8)
  89                 lines = min(lines, 2560);
  90
  91         /* Hardware needs the full buffer stride, not just the active area. */
  92         return lines * cache->fb.stride;
  93 }
  94
  95 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  96 {
  97         u32 fbc_ctl;
  98
  99         /* Disable compression */
 100         fbc_ctl = I915_READ(FBC_CONTROL);
 101         if ((fbc_ctl & FBC_CTL_EN) == 0)
 102                 return;
 103
 104         fbc_ctl &= ~FBC_CTL_EN;
 105         I915_WRITE(FBC_CONTROL, fbc_ctl);
 106
 107         /* Wait for compressing bit to clear */
 108         if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
 109                                     FBC_STAT_COMPRESSING, 10)) {
 110                 DRM_DEBUG_KMS("FBC idle timed out\n");
 111                 return;
 112         }
 113 }
 114
 115 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 116 {
 117         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 118         int cfb_pitch;
 119         int i;
 120         u32 fbc_ctl;
 121
 122         /* Note: fbc.threshold == 1 for i8xx */
 123         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 124         if (params->fb.stride < cfb_pitch)
 125                 cfb_pitch = params->fb.stride;
 126
 127         /* FBC_CTL wants 32B or 64B units */
 128         if (IS_GEN(dev_priv, 2))
 129                 cfb_pitch = (cfb_pitch / 32) - 1;
 130         else
 131                 cfb_pitch = (cfb_pitch / 64) - 1;
 132
 133         /* Clear old tags */
 134         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 135                 I915_WRITE(FBC_TAG(i), 0);
 136
 137         if (IS_GEN(dev_priv, 4)) {
 138                 u32 fbc_ctl2;
 139
 140                 /* Set it up... */
 141                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 142                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 143                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 144                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 145         }
 146
 147         /* enable it... */
 148         fbc_ctl = I915_READ(FBC_CONTROL);
 149         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 150         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 151         if (IS_I945GM(dev_priv))
 152                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 153         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 154         fbc_ctl |= params->fence_id;
 155         I915_WRITE(FBC_CONTROL, fbc_ctl);
 156 }
 157
 158 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 159 {
 160         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 161 }
 162
 163 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 164 {
 165         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 166         u32 dpfc_ctl;
 167
 168         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 169         if (params->fb.format->cpp[0] == 2)
 170                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 171         else
 172                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 173
 174         if (params->fence_id >= 0) {
 175                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
 176                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 177         } else {
 178                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 179         }
 180
 181         /* enable it... */
 182         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 183 }
 184
 185 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 186 {
 187         u32 dpfc_ctl;
 188
 189         /* Disable compression */
 190         dpfc_ctl = I915_READ(DPFC_CONTROL);
 191         if (dpfc_ctl & DPFC_CTL_EN) {
 192                 dpfc_ctl &= ~DPFC_CTL_EN;
 193                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 194         }
 195 }
 196
 197 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 198 {
 199         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 200 }
 201
 202 /* This function forces a CFB recompression through the nuke operation. */
 203 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 204 {
 205         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 206         POSTING_READ(MSG_FBC_REND_STATE);
 207 }
 208
 209 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 210 {
 211         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 212         u32 dpfc_ctl;
 213         int threshold = dev_priv->fbc.threshold;
 214
 215         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 216         if (params->fb.format->cpp[0] == 2)
 217                 threshold++;
 218
 219         switch (threshold) {
 220         case 4:
 221         case 3:
 222                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 223                 break;
 224         case 2:
 225                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 226                 break;
 227         case 1:
 228                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 229                 break;
 230         }
 231
 232         if (params->fence_id >= 0) {
 233                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 234                 if (IS_GEN(dev_priv, 5))
 235                         dpfc_ctl |= params->fence_id;
 236                 if (IS_GEN(dev_priv, 6)) {
 237                         I915_WRITE(SNB_DPFC_CTL_SA,
 238                                    SNB_CPU_FENCE_ENABLE |
 239                                    params->fence_id);
 240                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 241                                    params->crtc.fence_y_offset);
 242                 }
 243         } else {
 244                 if (IS_GEN(dev_priv, 6)) {
 245                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 246                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 247                 }
 248         }
 249
 250         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 251         /* enable it... */
 252         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 253
 254         intel_fbc_recompress(dev_priv);
 255 }
 256
 257 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 258 {
 259         u32 dpfc_ctl;
 260
 261         /* Disable compression */
 262         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 263         if (dpfc_ctl & DPFC_CTL_EN) {
 264                 dpfc_ctl &= ~DPFC_CTL_EN;
 265                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 266         }
 267 }
 268
 269 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 270 {
 271         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 272 }
 273
 274 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 275 {
 276         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 277         u32 dpfc_ctl;
 278         int threshold = dev_priv->fbc.threshold;
 279
 280         /* Display WA #0529: skl, kbl, bxt. */
 281         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) {
 282                 u32 val = I915_READ(CHICKEN_MISC_4);
 283
 284                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 285
 286                 if (params->gen9_wa_cfb_stride)
 287                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 288
 289                 I915_WRITE(CHICKEN_MISC_4, val);
 290         }
 291
 292         dpfc_ctl = 0;
 293         if (IS_IVYBRIDGE(dev_priv))
 294                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 295
 296         if (params->fb.format->cpp[0] == 2)
 297                 threshold++;
 298
 299         switch (threshold) {
 300         case 4:
 301         case 3:
 302                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 303                 break;
 304         case 2:
 305                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 306                 break;
 307         case 1:
 308                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 309                 break;
 310         }
 311
 312         if (params->fence_id >= 0) {
 313                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 314                 I915_WRITE(SNB_DPFC_CTL_SA,
 315                            SNB_CPU_FENCE_ENABLE |
 316                            params->fence_id);
 317                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 318         } else {
 319                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 320                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 321         }
 322
 323         if (dev_priv->fbc.false_color)
 324                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 325
 326         if (IS_IVYBRIDGE(dev_priv)) {
 327                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 328                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 329                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 330                            ILK_FBCQ_DIS);
 331         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 332                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 333                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 334                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 335                            HSW_FBCQ_DIS);
 336         }
 337
 338         if (INTEL_GEN(dev_priv) >= 11)
 339                 /* Wa_1409120013:icl,ehl,tgl */
 340                 I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 341
 342         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 343
 344         intel_fbc_recompress(dev_priv);
 345 }
 346
 347 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 348 {
 349         if (INTEL_GEN(dev_priv) >= 5)
 350                 return ilk_fbc_is_active(dev_priv);
 351         else if (IS_GM45(dev_priv))
 352                 return g4x_fbc_is_active(dev_priv);
 353         else
 354                 return i8xx_fbc_is_active(dev_priv);
 355 }
 356
 357 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 358 {
 359         struct intel_fbc *fbc = &dev_priv->fbc;
 360
 361         fbc->active = true;
 362
 363         if (INTEL_GEN(dev_priv) >= 7)
 364                 gen7_fbc_activate(dev_priv);
 365         else if (INTEL_GEN(dev_priv) >= 5)
 366                 ilk_fbc_activate(dev_priv);
 367         else if (IS_GM45(dev_priv))
 368                 g4x_fbc_activate(dev_priv);
 369         else
 370                 i8xx_fbc_activate(dev_priv);
 371 }
 372
 373 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 374 {
 375         struct intel_fbc *fbc = &dev_priv->fbc;
 376
 377         fbc->active = false;
 378
 379         if (INTEL_GEN(dev_priv) >= 5)
 380                 ilk_fbc_deactivate(dev_priv);
 381         else if (IS_GM45(dev_priv))
 382                 g4x_fbc_deactivate(dev_priv);
 383         else
 384                 i8xx_fbc_deactivate(dev_priv);
 385 }
 386
 387 /**
 388  * intel_fbc_is_active - Is FBC active?
 389  * @dev_priv: i915 device instance
 390  *
 391  * This function is used to verify the current state of FBC.
 392  *
 393  * FIXME: This should be tracked in the plane config eventually
 394  * instead of queried at runtime for most callers.
 395  */
 396 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 397 {
 398         return dev_priv->fbc.active;
 399 }
 400
 401 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 402                                  const char *reason)
 403 {
 404         struct intel_fbc *fbc = &dev_priv->fbc;
 405
 406         WARN_ON(!mutex_is_locked(&fbc->lock));
 407
 408         if (fbc->active)
 409                 intel_fbc_hw_deactivate(dev_priv);
 410
 411         fbc->no_fbc_reason = reason;
 412 }
 413
 414 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 415                                       struct drm_mm_node *node,
 416                                       unsigned int size,
 417                                       unsigned int fb_cpp)
 418 {
 419         int compression_threshold = 1;
 420         int ret;
 421         u64 end;
 422
 423         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 424          * reserved range size, so it always assumes the maximum (8mb) is used.
 425          * If we enable FBC using a CFB on that memory range we'll get FIFO
 426          * underruns, even if that range is not reserved by the BIOS. */
 427         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 428                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 429         else
 430                 end = U64_MAX;
 431
 432         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 433          * code changes, this code needs to change as well.
 434          *
 435          * The enable_fbc code will attempt to use one of our 2 compression
 436          * thresholds, therefore, in that case, we only have 1 resort.
 437          */
 438
 439         /* Try to over-allocate to reduce reallocations and fragmentation. */
 440         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 441                                                    4096, 0, end);
 442         if (ret == 0)
 443                 return compression_threshold;
 444
 445 again:
 446         /* HW's ability to limit the CFB is 1:4 */
 447         if (compression_threshold > 4 ||
 448             (fb_cpp == 2 && compression_threshold == 2))
 449                 return 0;
 450
 451         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 452                                                    4096, 0, end);
 453         if (ret && INTEL_GEN(dev_priv) <= 4) {
 454                 return 0;
 455         } else if (ret) {
 456                 compression_threshold <<= 1;
 457                 goto again;
 458         } else {
 459                 return compression_threshold;
 460         }
 461 }
 462
 463 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
 464                                unsigned int size, unsigned int fb_cpp)
 465 {
 466         struct intel_fbc *fbc = &dev_priv->fbc;
 467         struct drm_mm_node *uninitialized_var(compressed_llb);
 468         int ret;
 469
 470         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 471
 472         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 473                                          size, fb_cpp);
 474         if (!ret)
 475                 goto err_llb;
 476         else if (ret > 1) {
 477                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 478
 479         }
 480
 481         fbc->threshold = ret;
 482
 483         if (INTEL_GEN(dev_priv) >= 5)
 484                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 485         else if (IS_GM45(dev_priv)) {
 486                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 487         } else {
 488                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 489                 if (!compressed_llb)
 490                         goto err_fb;
 491
 492                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 493                                                   4096, 4096);
 494                 if (ret)
 495                         goto err_fb;
 496
 497                 fbc->compressed_llb = compressed_llb;
 498
 499                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 500                                              fbc->compressed_fb.start,
 501                                              U32_MAX));
 502                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 503                                              fbc->compressed_llb->start,
 504                                              U32_MAX));
 505                 I915_WRITE(FBC_CFB_BASE,
 506                            dev_priv->dsm.start + fbc->compressed_fb.start);
 507                 I915_WRITE(FBC_LL_BASE,
 508                            dev_priv->dsm.start + compressed_llb->start);
 509         }
 510
 511         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 512                       fbc->compressed_fb.size, fbc->threshold);
 513
 514         return 0;
 515
 516 err_fb:
 517         kfree(compressed_llb);
 518         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 519 err_llb:
 520         if (drm_mm_initialized(&dev_priv->mm.stolen))
 521                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 522         return -ENOSPC;
 523 }
 524
 525 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 526 {
 527         struct intel_fbc *fbc = &dev_priv->fbc;
 528
 529         if (drm_mm_node_allocated(&fbc->compressed_fb))
 530                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 531
 532         if (fbc->compressed_llb) {
 533                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 534                 kfree(fbc->compressed_llb);
 535         }
 536 }
 537
 538 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 539 {
 540         struct intel_fbc *fbc = &dev_priv->fbc;
 541
 542         if (!fbc_supported(dev_priv))
 543                 return;
 544
 545         mutex_lock(&fbc->lock);
 546         __intel_fbc_cleanup_cfb(dev_priv);
 547         mutex_unlock(&fbc->lock);
 548 }
 549
 550 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 551                             unsigned int stride)
 552 {
 553         /* This should have been caught earlier. */
 554         if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
 555                 return false;
 556
 557         /* Below are the additional FBC restrictions. */
 558         if (stride < 512)
 559                 return false;
 560
 561         if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
 562                 return stride == 4096 || stride == 8192;
 563
 564         if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
 565                 return false;
 566
 567         if (stride > 16384)
 568                 return false;
 569
 570         return true;
 571 }
 572
 573 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 574                                   u32 pixel_format)
 575 {
 576         switch (pixel_format) {
 577         case DRM_FORMAT_XRGB8888:
 578         case DRM_FORMAT_XBGR8888:
 579                 return true;
 580         case DRM_FORMAT_XRGB1555:
 581         case DRM_FORMAT_RGB565:
 582                 /* 16bpp not supported on gen2 */
 583                 if (IS_GEN(dev_priv, 2))
 584                         return false;
 585                 /* WaFbcOnly1to1Ratio:ctg */
 586                 if (IS_G4X(dev_priv))
 587                         return false;
 588                 return true;
 589         default:
 590                 return false;
 591         }
 592 }
 593
 594 /*
 595  * For some reason, the hardware tracking starts looking at whatever we
 596  * programmed as the display plane base address register. It does not look at
 597  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 598  * variables instead of just looking at the pipe/plane size.
 599  */
 600 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 601 {
 602         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 603         struct intel_fbc *fbc = &dev_priv->fbc;
 604         unsigned int effective_w, effective_h, max_w, max_h;
 605
 606         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 607                 max_w = 5120;
 608                 max_h = 4096;
 609         } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 610                 max_w = 4096;
 611                 max_h = 4096;
 612         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 613                 max_w = 4096;
 614                 max_h = 2048;
 615         } else {
 616                 max_w = 2048;
 617                 max_h = 1536;
 618         }
 619
 620         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 621                                         &effective_h);
 622         effective_w += fbc->state_cache.plane.adjusted_x;
 623         effective_h += fbc->state_cache.plane.adjusted_y;
 624
 625         return effective_w <= max_w && effective_h <= max_h;
 626 }
 627
 628 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 629                                          const struct intel_crtc_state *crtc_state,
 630                                          const struct intel_plane_state *plane_state)
 631 {
 632         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 633         struct intel_fbc *fbc = &dev_priv->fbc;
 634         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 635         struct drm_framebuffer *fb = plane_state->hw.fb;
 636
 637         cache->plane.visible = plane_state->uapi.visible;
 638         if (!cache->plane.visible)
 639                 return;
 640
 641         cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
 642         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 643                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 644
 645         cache->plane.rotation = plane_state->hw.rotation;
 646         /*
 647          * Src coordinates are already rotated by 270 degrees for
 648          * the 90/270 degree plane rotation cases (to match the
 649          * GTT mapping), hence no need to account for rotation here.
 650          */
 651         cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 652         cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 653         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 654         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 655         cache->plane.y = plane_state->uapi.src.y1 >> 16;
 656
 657         cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 658
 659         cache->fb.format = fb->format;
 660         cache->fb.stride = fb->pitches[0];
 661
 662         WARN_ON(plane_state->flags & PLANE_HAS_FENCE &&
 663                 !plane_state->vma->fence);
 664
 665         if (plane_state->flags & PLANE_HAS_FENCE &&
 666             plane_state->vma->fence)
 667                 cache->fence_id = plane_state->vma->fence->id;
 668         else
 669                 cache->fence_id = -1;
 670 }
 671
 672 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 673 {
 674         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 675         struct intel_fbc *fbc = &dev_priv->fbc;
 676         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 677
 678         if (!cache->plane.visible) {
 679                 fbc->no_fbc_reason = "primary plane not visible";
 680                 return false;
 681         }
 682
 683         /* We don't need to use a state cache here since this information is
 684          * global for all CRTC.
 685          */
 686         if (fbc->underrun_detected) {
 687                 fbc->no_fbc_reason = "underrun detected";
 688                 return false;
 689         }
 690
 691         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 692                 fbc->no_fbc_reason = "incompatible mode";
 693                 return false;
 694         }
 695
 696         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 697                 fbc->no_fbc_reason = "mode too large for compression";
 698                 return false;
 699         }
 700
 701         /* The use of a CPU fence is mandatory in order to detect writes
 702          * by the CPU to the scanout and trigger updates to the FBC.
 703          *
 704          * Note that is possible for a tiled surface to be unmappable (and
 705          * so have no fence associated with it) due to aperture constaints
 706          * at the time of pinning.
 707          *
 708          * FIXME with 90/270 degree rotation we should use the fence on
 709          * the normal GTT view (the rotated view doesn't even have a
 710          * fence). Would need changes to the FBC fence Y offset as well.
 711          * For now this will effecively disable FBC with 90/270 degree
 712          * rotation.
 713          */
 714         if (cache->fence_id < 0) {
 715                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 716                 return false;
 717         }
 718         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 719             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 720                 fbc->no_fbc_reason = "rotation unsupported";
 721                 return false;
 722         }
 723
 724         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 725                 fbc->no_fbc_reason = "framebuffer stride not supported";
 726                 return false;
 727         }
 728
 729         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 730                 fbc->no_fbc_reason = "pixel format is invalid";
 731                 return false;
 732         }
 733
 734         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 735             cache->fb.format->has_alpha) {
 736                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 737                 return false;
 738         }
 739
 740         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 741         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 742             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 743                 fbc->no_fbc_reason = "pixel rate is too big";
 744                 return false;
 745         }
 746
 747         /* It is possible for the required CFB size change without a
 748          * crtc->disable + crtc->enable since it is possible to change the
 749          * stride without triggering a full modeset. Since we try to
 750          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 751          * if this happens, but if we exceed the current CFB size we'll have to
 752          * disable FBC. Notice that it would be possible to disable FBC, wait
 753          * for a frame, free the stolen node, then try to reenable FBC in case
 754          * we didn't get any invalidate/deactivate calls, but this would require
 755          * a lot of tracking just for a specific case. If we conclude it's an
 756          * important case, we can implement it later. */
 757         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 758             fbc->compressed_fb.size * fbc->threshold) {
 759                 fbc->no_fbc_reason = "CFB requirements changed";
 760                 return false;
 761         }
 762
 763         /*
 764          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 765          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 766          * and screen flicker.
 767          */
 768         if (IS_GEN_RANGE(dev_priv, 9, 10) &&
 769             (fbc->state_cache.plane.adjusted_y & 3)) {
 770                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 771                 return false;
 772         }
 773
 774         return true;
 775 }
 776
 777 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 778 {
 779         struct intel_fbc *fbc = &dev_priv->fbc;
 780
 781         if (intel_vgpu_active(dev_priv)) {
 782                 fbc->no_fbc_reason = "VGPU is active";
 783                 return false;
 784         }
 785
 786         if (!i915_modparams.enable_fbc) {
 787                 fbc->no_fbc_reason = "disabled per module param or by default";
 788                 return false;
 789         }
 790
 791         if (fbc->underrun_detected) {
 792                 fbc->no_fbc_reason = "underrun detected";
 793                 return false;
 794         }
 795
 796         return true;
 797 }
 798
 799 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 800                                      struct intel_fbc_reg_params *params)
 801 {
 802         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 803         struct intel_fbc *fbc = &dev_priv->fbc;
 804         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 805
 806         /* Since all our fields are integer types, use memset here so the
 807          * comparison function can rely on memcmp because the padding will be
 808          * zero. */
 809         memset(params, 0, sizeof(*params));
 810
 811         params->fence_id = cache->fence_id;
 812
 813         params->crtc.pipe = crtc->pipe;
 814         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 815         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 816
 817         params->fb.format = cache->fb.format;
 818         params->fb.stride = cache->fb.stride;
 819
 820         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 821
 822         params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
 823
 824         params->plane_visible = cache->plane.visible;
 825 }
 826
 827 void intel_fbc_pre_update(struct intel_crtc *crtc,
 828                           const struct intel_crtc_state *crtc_state,
 829                           const struct intel_plane_state *plane_state)
 830 {
 831         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 832         struct intel_fbc *fbc = &dev_priv->fbc;
 833         const char *reason = "update pending";
 834
 835         if (!fbc_supported(dev_priv))
 836                 return;
 837
 838         mutex_lock(&fbc->lock);
 839
 840         if (!fbc->enabled || fbc->crtc != crtc)
 841                 goto unlock;
 842
 843         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 844         fbc->flip_pending = true;
 845
 846         intel_fbc_deactivate(dev_priv, reason);
 847 unlock:
 848         mutex_unlock(&fbc->lock);
 849 }
 850
 851 /**
 852  * __intel_fbc_disable - disable FBC
 853  * @dev_priv: i915 device instance
 854  *
 855  * This is the low level function that actually disables FBC. Callers should
 856  * grab the FBC lock.
 857  */
 858 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 859 {
 860         struct intel_fbc *fbc = &dev_priv->fbc;
 861         struct intel_crtc *crtc = fbc->crtc;
 862
 863         WARN_ON(!mutex_is_locked(&fbc->lock));
 864         WARN_ON(!fbc->enabled);
 865         WARN_ON(fbc->active);
 866
 867         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
 868
 869         __intel_fbc_cleanup_cfb(dev_priv);
 870
 871         fbc->enabled = false;
 872         fbc->crtc = NULL;
 873 }
 874
 875 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 876 {
 877         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 878         struct intel_fbc *fbc = &dev_priv->fbc;
 879
 880         WARN_ON(!mutex_is_locked(&fbc->lock));
 881
 882         if (!fbc->enabled || fbc->crtc != crtc)
 883                 return;
 884
 885         fbc->flip_pending = false;
 886         WARN_ON(fbc->active);
 887
 888         if (!i915_modparams.enable_fbc) {
 889                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
 890                 __intel_fbc_disable(dev_priv);
 891
 892                 return;
 893         }
 894
 895         intel_fbc_get_reg_params(crtc, &fbc->params);
 896
 897         if (!intel_fbc_can_activate(crtc))
 898                 return;
 899
 900         if (!fbc->busy_bits) {
 901                 intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)");
 902                 intel_fbc_hw_activate(dev_priv);
 903         } else
 904                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 905 }
 906
 907 void intel_fbc_post_update(struct intel_crtc *crtc)
 908 {
 909         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 910         struct intel_fbc *fbc = &dev_priv->fbc;
 911
 912         if (!fbc_supported(dev_priv))
 913                 return;
 914
 915         mutex_lock(&fbc->lock);
 916         __intel_fbc_post_update(crtc);
 917         mutex_unlock(&fbc->lock);
 918 }
 919
 920 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 921 {
 922         if (fbc->enabled)
 923                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 924         else
 925                 return fbc->possible_framebuffer_bits;
 926 }
 927
 928 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 929                           unsigned int frontbuffer_bits,
 930                           enum fb_op_origin origin)
 931 {
 932         struct intel_fbc *fbc = &dev_priv->fbc;
 933
 934         if (!fbc_supported(dev_priv))
 935                 return;
 936
 937         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 938                 return;
 939
 940         mutex_lock(&fbc->lock);
 941
 942         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
 943
 944         if (fbc->enabled && fbc->busy_bits)
 945                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 946
 947         mutex_unlock(&fbc->lock);
 948 }
 949
 950 void intel_fbc_flush(struct drm_i915_private *dev_priv,
 951                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
 952 {
 953         struct intel_fbc *fbc = &dev_priv->fbc;
 954
 955         if (!fbc_supported(dev_priv))
 956                 return;
 957
 958         mutex_lock(&fbc->lock);
 959
 960         fbc->busy_bits &= ~frontbuffer_bits;
 961
 962         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 963                 goto out;
 964
 965         if (!fbc->busy_bits && fbc->enabled &&
 966             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
 967                 if (fbc->active)
 968                         intel_fbc_recompress(dev_priv);
 969                 else if (!fbc->flip_pending)
 970                         __intel_fbc_post_update(fbc->crtc);
 971         }
 972
 973 out:
 974         mutex_unlock(&fbc->lock);
 975 }
 976
 977 /**
 978  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
 979  * @dev_priv: i915 device instance
 980  * @state: the atomic state structure
 981  *
 982  * This function looks at the proposed state for CRTCs and planes, then chooses
 983  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
 984  * true.
 985  *
 986  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
 987  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
 988  */
 989 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 990                            struct intel_atomic_state *state)
 991 {
 992         struct intel_fbc *fbc = &dev_priv->fbc;
 993         struct intel_plane *plane;
 994         struct intel_plane_state *plane_state;
 995         bool crtc_chosen = false;
 996         int i;
 997
 998         mutex_lock(&fbc->lock);
 999
1000         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1001         if (fbc->crtc &&
1002             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1003                 goto out;
1004
1005         if (!intel_fbc_can_enable(dev_priv))
1006                 goto out;
1007
1008         /* Simply choose the first CRTC that is compatible and has a visible
1009          * plane. We could go for fancier schemes such as checking the plane
1010          * size, but this would just affect the few platforms that don't tie FBC
1011          * to pipe or plane A. */
1012         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1013                 struct intel_crtc_state *crtc_state;
1014                 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1015
1016                 if (!plane->has_fbc)
1017                         continue;
1018
1019                 if (!plane_state->uapi.visible)
1020                         continue;
1021
1022                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1023
1024                 crtc_state->enable_fbc = true;
1025                 crtc_chosen = true;
1026                 break;
1027         }
1028
1029         if (!crtc_chosen)
1030                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1031
1032 out:
1033         mutex_unlock(&fbc->lock);
1034 }
1035
1036 /**
1037  * intel_fbc_enable: tries to enable FBC on the CRTC
1038  * @crtc: the CRTC
1039  * @crtc_state: corresponding &drm_crtc_state for @crtc
1040  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1041  *
1042  * This function checks if the given CRTC was chosen for FBC, then enables it if
1043  * possible. Notice that it doesn't activate FBC. It is valid to call
1044  * intel_fbc_enable multiple times for the same pipe without an
1045  * intel_fbc_disable in the middle, as long as it is deactivated.
1046  */
1047 void intel_fbc_enable(struct intel_crtc *crtc,
1048                       const struct intel_crtc_state *crtc_state,
1049                       const struct intel_plane_state *plane_state)
1050 {
1051         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1052         struct intel_fbc *fbc = &dev_priv->fbc;
1053         struct intel_fbc_state_cache *cache = &fbc->state_cache;
1054         const struct drm_framebuffer *fb = plane_state->hw.fb;
1055
1056         if (!fbc_supported(dev_priv))
1057                 return;
1058
1059         mutex_lock(&fbc->lock);
1060
1061         if (fbc->enabled) {
1062                 WARN_ON(fbc->crtc == NULL);
1063                 if (fbc->crtc == crtc) {
1064                         WARN_ON(!crtc_state->enable_fbc);
1065                         WARN_ON(fbc->active);
1066                 }
1067                 goto out;
1068         }
1069
1070         if (!crtc_state->enable_fbc)
1071                 goto out;
1072
1073         WARN_ON(fbc->active);
1074         WARN_ON(fbc->crtc != NULL);
1075
1076         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1077
1078         /* FIXME crtc_state->enable_fbc lies :( */
1079         if (!cache->plane.visible)
1080                 goto out;
1081
1082         if (intel_fbc_alloc_cfb(dev_priv,
1083                                 intel_fbc_calculate_cfb_size(dev_priv, cache),
1084                                 fb->format->cpp[0])) {
1085                 fbc->no_fbc_reason = "not enough stolen memory";
1086                 goto out;
1087         }
1088
1089         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) &&
1090             fb->modifier != I915_FORMAT_MOD_X_TILED)
1091                 cache->gen9_wa_cfb_stride =
1092                         DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
1093         else
1094                 cache->gen9_wa_cfb_stride = 0;
1095
1096         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1097         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1098
1099         fbc->enabled = true;
1100         fbc->crtc = crtc;
1101 out:
1102         mutex_unlock(&fbc->lock);
1103 }
1104
1105 /**
1106  * intel_fbc_disable - disable FBC if it's associated with crtc
1107  * @crtc: the CRTC
1108  *
1109  * This function disables FBC if it's associated with the provided CRTC.
1110  */
1111 void intel_fbc_disable(struct intel_crtc *crtc)
1112 {
1113         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1114         struct intel_fbc *fbc = &dev_priv->fbc;
1115
1116         if (!fbc_supported(dev_priv))
1117                 return;
1118
1119         mutex_lock(&fbc->lock);
1120         if (fbc->crtc == crtc)
1121                 __intel_fbc_disable(dev_priv);
1122         mutex_unlock(&fbc->lock);
1123 }
1124
1125 /**
1126  * intel_fbc_global_disable - globally disable FBC
1127  * @dev_priv: i915 device instance
1128  *
1129  * This function disables FBC regardless of which CRTC is associated with it.
1130  */
1131 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1132 {
1133         struct intel_fbc *fbc = &dev_priv->fbc;
1134
1135         if (!fbc_supported(dev_priv))
1136                 return;
1137
1138         mutex_lock(&fbc->lock);
1139         if (fbc->enabled) {
1140                 WARN_ON(fbc->crtc->active);
1141                 __intel_fbc_disable(dev_priv);
1142         }
1143         mutex_unlock(&fbc->lock);
1144 }
1145
1146 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1147 {
1148         struct drm_i915_private *dev_priv =
1149                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1150         struct intel_fbc *fbc = &dev_priv->fbc;
1151
1152         mutex_lock(&fbc->lock);
1153
1154         /* Maybe we were scheduled twice. */
1155         if (fbc->underrun_detected || !fbc->enabled)
1156                 goto out;
1157
1158         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1159         fbc->underrun_detected = true;
1160
1161         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1162 out:
1163         mutex_unlock(&fbc->lock);
1164 }
1165
1166 /*
1167  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1168  * @dev_priv: i915 device instance
1169  *
1170  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1171  * want to re-enable FBC after an underrun to increase test coverage.
1172  */
1173 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1174 {
1175         int ret;
1176
1177         cancel_work_sync(&dev_priv->fbc.underrun_work);
1178
1179         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1180         if (ret)
1181                 return ret;
1182
1183         if (dev_priv->fbc.underrun_detected) {
1184                 DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
1185                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1186         }
1187
1188         dev_priv->fbc.underrun_detected = false;
1189         mutex_unlock(&dev_priv->fbc.lock);
1190
1191         return 0;
1192 }
1193
1194 /**
1195  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1196  * @dev_priv: i915 device instance
1197  *
1198  * Without FBC, most underruns are harmless and don't really cause too many
1199  * problems, except for an annoying message on dmesg. With FBC, underruns can
1200  * become black screens or even worse, especially when paired with bad
1201  * watermarks. So in order for us to be on the safe side, completely disable FBC
1202  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1203  * already suggests that watermarks may be bad, so try to be as safe as
1204  * possible.
1205  *
1206  * This function is called from the IRQ handler.
1207  */
1208 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1209 {
1210         struct intel_fbc *fbc = &dev_priv->fbc;
1211
1212         if (!fbc_supported(dev_priv))
1213                 return;
1214
1215         /* There's no guarantee that underrun_detected won't be set to true
1216          * right after this check and before the work is scheduled, but that's
1217          * not a problem since we'll check it again under the work function
1218          * while FBC is locked. This check here is just to prevent us from
1219          * unnecessarily scheduling the work, and it relies on the fact that we
1220          * never switch underrun_detect back to false after it's true. */
1221         if (READ_ONCE(fbc->underrun_detected))
1222                 return;
1223
1224         schedule_work(&fbc->underrun_work);
1225 }
1226
1227 /*
1228  * The DDX driver changes its behavior depending on the value it reads from
1229  * i915.enable_fbc, so sanitize it by translating the default value into either
1230  * 0 or 1 in order to allow it to know what's going on.
1231  *
1232  * Notice that this is done at driver initialization and we still allow user
1233  * space to change the value during runtime without sanitizing it again. IGT
1234  * relies on being able to change i915.enable_fbc at runtime.
1235  */
1236 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1237 {
1238         if (i915_modparams.enable_fbc >= 0)
1239                 return !!i915_modparams.enable_fbc;
1240
1241         if (!HAS_FBC(dev_priv))
1242                 return 0;
1243
1244         /* https://bugs.freedesktop.org/show_bug.cgi?id=108085 */
1245         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1246                 return 0;
1247
1248         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1249                 return 1;
1250
1251         return 0;
1252 }
1253
1254 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1255 {
1256         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1257         if (intel_vtd_active() &&
1258             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1259                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1260                 return true;
1261         }
1262
1263         return false;
1264 }
1265
1266 /**
1267  * intel_fbc_init - Initialize FBC
1268  * @dev_priv: the i915 device
1269  *
1270  * This function might be called during PM init process.
1271  */
1272 void intel_fbc_init(struct drm_i915_private *dev_priv)
1273 {
1274         struct intel_fbc *fbc = &dev_priv->fbc;
1275
1276         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1277         mutex_init(&fbc->lock);
1278         fbc->enabled = false;
1279         fbc->active = false;
1280
1281         if (!drm_mm_initialized(&dev_priv->mm.stolen))
1282                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1283
1284         if (need_fbc_vtd_wa(dev_priv))
1285                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1286
1287         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1288         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1289                       i915_modparams.enable_fbc);
1290
1291         if (!HAS_FBC(dev_priv)) {
1292                 fbc->no_fbc_reason = "unsupported by this chipset";
1293                 return;
1294         }
1295
1296         /* This value was pulled out of someone's hat */
1297         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1298                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1299
1300         /* We still don't have any sort of hardware state readout for FBC, so
1301          * deactivate it in case the BIOS activated it to make sure software
1302          * matches the hardware state. */
1303         if (intel_fbc_hw_is_active(dev_priv))
1304                 intel_fbc_hw_deactivate(dev_priv);
1305 }