drivers/gpu/drm/i915/display/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32
  33 #include <drm/drm_atomic.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_color_mgmt.h>
  36 #include <drm/drm_crtc.h>
  37 #include <drm/drm_fourcc.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_rect.h>
  40 #include <drm/i915_drm.h>
  41
  42 #include "i915_drv.h"
  43 #include "i915_trace.h"
  44 #include "intel_atomic_plane.h"
  45 #include "intel_display_types.h"
  46 #include "intel_frontbuffer.h"
  47 #include "intel_pm.h"
  48 #include "intel_psr.h"
  49 #include "intel_sprite.h"
  50
  51 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  52                              int usecs)
  53 {
  54         /* paranoia */
  55         if (!adjusted_mode->crtc_htotal)
  56                 return 1;
  57
  58         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  59                             1000 * adjusted_mode->crtc_htotal);
  60 }
  61
  62 /* FIXME: We should instead only take spinlocks once for the entire update
  63  * instead of once per mmio. */
  64 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  65 #define VBLANK_EVASION_TIME_US 250
  66 #else
  67 #define VBLANK_EVASION_TIME_US 100
  68 #endif
  69
  70 /**
  71  * intel_pipe_update_start() - start update of a set of display registers
  72  * @new_crtc_state: the new crtc state
  73  *
  74  * Mark the start of an update to pipe registers that should be updated
  75  * atomically regarding vblank. If the next vblank will happens within
  76  * the next 100 us, this function waits until the vblank passes.
  77  *
  78  * After a successful call to this function, interrupts will be disabled
  79  * until a subsequent call to intel_pipe_update_end(). That is done to
  80  * avoid random delays.
  81  */
  82 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  83 {
  84         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
  85         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  86         const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
  87         long timeout = msecs_to_jiffies_timeout(1);
  88         int scanline, min, max, vblank_start;
  89         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  90         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  91                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  92         DEFINE_WAIT(wait);
  93         u32 psr_status;
  94
  95         vblank_start = adjusted_mode->crtc_vblank_start;
  96         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  97                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  98
  99         /* FIXME needs to be calibrated sensibly */
 100         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
 101                                                       VBLANK_EVASION_TIME_US);
 102         max = vblank_start - 1;
 103
 104         if (min <= 0 || max <= 0)
 105                 goto irq_disable;
 106
 107         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 108                 goto irq_disable;
 109
 110         /*
 111          * Wait for psr to idle out after enabling the VBL interrupts
 112          * VBL interrupts will start the PSR exit and prevent a PSR
 113          * re-entry as well.
 114          */
 115         if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
 116                 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
 117                           psr_status);
 118
 119         local_irq_disable();
 120
 121         crtc->debug.min_vbl = min;
 122         crtc->debug.max_vbl = max;
 123         trace_i915_pipe_update_start(crtc);
 124
 125         for (;;) {
 126                 /*
 127                  * prepare_to_wait() has a memory barrier, which guarantees
 128                  * other CPUs can see the task state update by the time we
 129                  * read the scanline.
 130                  */
 131                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 132
 133                 scanline = intel_get_crtc_scanline(crtc);
 134                 if (scanline < min || scanline > max)
 135                         break;
 136
 137                 if (!timeout) {
 138                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 139                                   pipe_name(crtc->pipe));
 140                         break;
 141                 }
 142
 143                 local_irq_enable();
 144
 145                 timeout = schedule_timeout(timeout);
 146
 147                 local_irq_disable();
 148         }
 149
 150         finish_wait(wq, &wait);
 151
 152         drm_crtc_vblank_put(&crtc->base);
 153
 154         /*
 155          * On VLV/CHV DSI the scanline counter would appear to
 156          * increment approx. 1/3 of a scanline before start of vblank.
 157          * The registers still get latched at start of vblank however.
 158          * This means we must not write any registers on the first
 159          * line of vblank (since not the whole line is actually in
 160          * vblank). And unfortunately we can't use the interrupt to
 161          * wait here since it will fire too soon. We could use the
 162          * frame start interrupt instead since it will fire after the
 163          * critical scanline, but that would require more changes
 164          * in the interrupt code. So for now we'll just do the nasty
 165          * thing and poll for the bad scanline to pass us by.
 166          *
 167          * FIXME figure out if BXT+ DSI suffers from this as well
 168          */
 169         while (need_vlv_dsi_wa && scanline == vblank_start)
 170                 scanline = intel_get_crtc_scanline(crtc);
 171
 172         crtc->debug.scanline_start = scanline;
 173         crtc->debug.start_vbl_time = ktime_get();
 174         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 175
 176         trace_i915_pipe_update_vblank_evaded(crtc);
 177         return;
 178
 179 irq_disable:
 180         local_irq_disable();
 181 }
 182
 183 /**
 184  * intel_pipe_update_end() - end update of a set of display registers
 185  * @new_crtc_state: the new crtc state
 186  *
 187  * Mark the end of an update started with intel_pipe_update_start(). This
 188  * re-enables interrupts and verifies the update was actually completed
 189  * before a vblank.
 190  */
 191 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 192 {
 193         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 194         enum pipe pipe = crtc->pipe;
 195         int scanline_end = intel_get_crtc_scanline(crtc);
 196         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 197         ktime_t end_vbl_time = ktime_get();
 198         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 199
 200         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 201
 202         /* We're still in the vblank-evade critical section, this can't race.
 203          * Would be slightly nice to just grab the vblank count and arm the
 204          * event outside of the critical section - the spinlock might spin for a
 205          * while ... */
 206         if (new_crtc_state->uapi.event) {
 207                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 208
 209                 spin_lock(&crtc->base.dev->event_lock);
 210                 drm_crtc_arm_vblank_event(&crtc->base,
 211                                           new_crtc_state->uapi.event);
 212                 spin_unlock(&crtc->base.dev->event_lock);
 213
 214                 new_crtc_state->uapi.event = NULL;
 215         }
 216
 217         local_irq_enable();
 218
 219         if (intel_vgpu_active(dev_priv))
 220                 return;
 221
 222         if (crtc->debug.start_vbl_count &&
 223             crtc->debug.start_vbl_count != end_vbl_count) {
 224                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 225                           pipe_name(pipe), crtc->debug.start_vbl_count,
 226                           end_vbl_count,
 227                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 228                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 229                           crtc->debug.scanline_start, scanline_end);
 230         }
 231 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 232         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 233                  VBLANK_EVASION_TIME_US)
 234                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 235                          pipe_name(pipe),
 236                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 237                          VBLANK_EVASION_TIME_US);
 238 #endif
 239 }
 240
 241 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 242 {
 243         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 244         const struct drm_framebuffer *fb = plane_state->hw.fb;
 245         unsigned int rotation = plane_state->hw.rotation;
 246         u32 stride, max_stride;
 247
 248         /*
 249          * We ignore stride for all invisible planes that
 250          * can be remapped. Otherwise we could end up
 251          * with a false positive when the remapping didn't
 252          * kick in due the plane being invisible.
 253          */
 254         if (intel_plane_can_remap(plane_state) &&
 255             !plane_state->uapi.visible)
 256                 return 0;
 257
 258         /* FIXME other color planes? */
 259         stride = plane_state->color_plane[0].stride;
 260         max_stride = plane->max_stride(plane, fb->format->format,
 261                                        fb->modifier, rotation);
 262
 263         if (stride > max_stride) {
 264                 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
 265                               fb->base.id, stride,
 266                               plane->base.base.id, plane->base.name, max_stride);
 267                 return -EINVAL;
 268         }
 269
 270         return 0;
 271 }
 272
 273 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 274 {
 275         const struct drm_framebuffer *fb = plane_state->hw.fb;
 276         struct drm_rect *src = &plane_state->uapi.src;
 277         u32 src_x, src_y, src_w, src_h, hsub, vsub;
 278         bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
 279
 280         /*
 281          * Hardware doesn't handle subpixel coordinates.
 282          * Adjust to (macro)pixel boundary, but be careful not to
 283          * increase the source viewport size, because that could
 284          * push the downscaling factor out of bounds.
 285          */
 286         src_x = src->x1 >> 16;
 287         src_w = drm_rect_width(src) >> 16;
 288         src_y = src->y1 >> 16;
 289         src_h = drm_rect_height(src) >> 16;
 290
 291         drm_rect_init(src, src_x << 16, src_y << 16,
 292                       src_w << 16, src_h << 16);
 293
 294         if (!fb->format->is_yuv)
 295                 return 0;
 296
 297         /* YUV specific checks */
 298         if (!rotated) {
 299                 hsub = fb->format->hsub;
 300                 vsub = fb->format->vsub;
 301         } else {
 302                 hsub = vsub = max(fb->format->hsub, fb->format->vsub);
 303         }
 304
 305         if (src_x % hsub || src_w % hsub) {
 306                 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u for %sYUV planes\n",
 307                               src_x, src_w, hsub, rotated ? "rotated " : "");
 308                 return -EINVAL;
 309         }
 310
 311         if (src_y % vsub || src_h % vsub) {
 312                 DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u for %sYUV planes\n",
 313                               src_y, src_h, vsub, rotated ? "rotated " : "");
 314                 return -EINVAL;
 315         }
 316
 317         return 0;
 318 }
 319
 320 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
 321 {
 322         return INTEL_GEN(dev_priv) >= 11 &&
 323                 icl_hdr_plane_mask() & BIT(plane_id);
 324 }
 325
 326 static void
 327 skl_plane_ratio(const struct intel_crtc_state *crtc_state,
 328                 const struct intel_plane_state *plane_state,
 329                 unsigned int *num, unsigned int *den)
 330 {
 331         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
 332         const struct drm_framebuffer *fb = plane_state->hw.fb;
 333
 334         if (fb->format->cpp[0] == 8) {
 335                 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 336                         *num = 10;
 337                         *den = 8;
 338                 } else {
 339                         *num = 9;
 340                         *den = 8;
 341                 }
 342         } else {
 343                 *num = 1;
 344                 *den = 1;
 345         }
 346 }
 347
 348 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 349                                const struct intel_plane_state *plane_state)
 350 {
 351         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
 352         unsigned int pixel_rate = crtc_state->pixel_rate;
 353         unsigned int src_w, src_h, dst_w, dst_h;
 354         unsigned int num, den;
 355
 356         skl_plane_ratio(crtc_state, plane_state, &num, &den);
 357
 358         /* two pixels per clock on glk+ */
 359         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 360                 den *= 2;
 361
 362         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 363         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 364         dst_w = drm_rect_width(&plane_state->uapi.dst);
 365         dst_h = drm_rect_height(&plane_state->uapi.dst);
 366
 367         /* Downscaling limits the maximum pixel rate */
 368         dst_w = min(src_w, dst_w);
 369         dst_h = min(src_h, dst_h);
 370
 371         return DIV64_U64_ROUND_UP(mul_u32_u32(pixel_rate * num, src_w * src_h),
 372                                   mul_u32_u32(den, dst_w * dst_h));
 373 }
 374
 375 static unsigned int
 376 skl_plane_max_stride(struct intel_plane *plane,
 377                      u32 pixel_format, u64 modifier,
 378                      unsigned int rotation)
 379 {
 380         const struct drm_format_info *info = drm_format_info(pixel_format);
 381         int cpp = info->cpp[0];
 382
 383         /*
 384          * "The stride in bytes must not exceed the
 385          * of the size of 8K pixels and 32K bytes."
 386          */
 387         if (drm_rotation_90_or_270(rotation))
 388                 return min(8192, 32768 / cpp);
 389         else
 390                 return min(8192 * cpp, 32768);
 391 }
 392
 393 static void
 394 skl_program_scaler(struct intel_plane *plane,
 395                    const struct intel_crtc_state *crtc_state,
 396                    const struct intel_plane_state *plane_state)
 397 {
 398         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 399         const struct drm_framebuffer *fb = plane_state->hw.fb;
 400         enum pipe pipe = plane->pipe;
 401         int scaler_id = plane_state->scaler_id;
 402         const struct intel_scaler *scaler =
 403                 &crtc_state->scaler_state.scalers[scaler_id];
 404         int crtc_x = plane_state->uapi.dst.x1;
 405         int crtc_y = plane_state->uapi.dst.y1;
 406         u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
 407         u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
 408         u16 y_hphase, uv_rgb_hphase;
 409         u16 y_vphase, uv_rgb_vphase;
 410         int hscale, vscale;
 411
 412         hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
 413                                       &plane_state->uapi.dst,
 414                                       0, INT_MAX);
 415         vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
 416                                       &plane_state->uapi.dst,
 417                                       0, INT_MAX);
 418
 419         /* TODO: handle sub-pixel coordinates */
 420         if (drm_format_info_is_yuv_semiplanar(fb->format) &&
 421             !icl_is_hdr_plane(dev_priv, plane->id)) {
 422                 y_hphase = skl_scaler_calc_phase(1, hscale, false);
 423                 y_vphase = skl_scaler_calc_phase(1, vscale, false);
 424
 425                 /* MPEG2 chroma siting convention */
 426                 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
 427                 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
 428         } else {
 429                 /* not used */
 430                 y_hphase = 0;
 431                 y_vphase = 0;
 432
 433                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
 434                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
 435         }
 436
 437         I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 438                       PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
 439         I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
 440                       PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 441         I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
 442                       PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 443         I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 444         I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
 445 }
 446
 447 /* Preoffset values for YUV to RGB Conversion */
 448 #define PREOFF_YUV_TO_RGB_HI            0x1800
 449 #define PREOFF_YUV_TO_RGB_ME            0x1F00
 450 #define PREOFF_YUV_TO_RGB_LO            0x1800
 451
 452 #define  ROFF(x)          (((x) & 0xffff) << 16)
 453 #define  GOFF(x)          (((x) & 0xffff) << 0)
 454 #define  BOFF(x)          (((x) & 0xffff) << 16)
 455
 456 static void
 457 icl_program_input_csc(struct intel_plane *plane,
 458                       const struct intel_crtc_state *crtc_state,
 459                       const struct intel_plane_state *plane_state)
 460 {
 461         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 462         enum pipe pipe = plane->pipe;
 463         enum plane_id plane_id = plane->id;
 464
 465         static const u16 input_csc_matrix[][9] = {
 466                 /*
 467                  * BT.601 full range YCbCr -> full range RGB
 468                  * The matrix required is :
 469                  * [1.000, 0.000, 1.371,
 470                  *  1.000, -0.336, -0.698,
 471                  *  1.000, 1.732, 0.0000]
 472                  */
 473                 [DRM_COLOR_YCBCR_BT601] = {
 474                         0x7AF8, 0x7800, 0x0,
 475                         0x8B28, 0x7800, 0x9AC0,
 476                         0x0, 0x7800, 0x7DD8,
 477                 },
 478                 /*
 479                  * BT.709 full range YCbCr -> full range RGB
 480                  * The matrix required is :
 481                  * [1.000, 0.000, 1.574,
 482                  *  1.000, -0.187, -0.468,
 483                  *  1.000, 1.855, 0.0000]
 484                  */
 485                 [DRM_COLOR_YCBCR_BT709] = {
 486                         0x7C98, 0x7800, 0x0,
 487                         0x9EF8, 0x7800, 0xAC00,
 488                         0x0, 0x7800,  0x7ED8,
 489                 },
 490                 /*
 491                  * BT.2020 full range YCbCr -> full range RGB
 492                  * The matrix required is :
 493                  * [1.000, 0.000, 1.474,
 494                  *  1.000, -0.1645, -0.5713,
 495                  *  1.000, 1.8814, 0.0000]
 496                  */
 497                 [DRM_COLOR_YCBCR_BT2020] = {
 498                         0x7BC8, 0x7800, 0x0,
 499                         0x8928, 0x7800, 0xAA88,
 500                         0x0, 0x7800, 0x7F10,
 501                 },
 502         };
 503
 504         /* Matrix for Limited Range to Full Range Conversion */
 505         static const u16 input_csc_matrix_lr[][9] = {
 506                 /*
 507                  * BT.601 Limted range YCbCr -> full range RGB
 508                  * The matrix required is :
 509                  * [1.164384, 0.000, 1.596027,
 510                  *  1.164384, -0.39175, -0.812813,
 511                  *  1.164384, 2.017232, 0.0000]
 512                  */
 513                 [DRM_COLOR_YCBCR_BT601] = {
 514                         0x7CC8, 0x7950, 0x0,
 515                         0x8D00, 0x7950, 0x9C88,
 516                         0x0, 0x7950, 0x6810,
 517                 },
 518                 /*
 519                  * BT.709 Limited range YCbCr -> full range RGB
 520                  * The matrix required is :
 521                  * [1.164384, 0.000, 1.792741,
 522                  *  1.164384, -0.213249, -0.532909,
 523                  *  1.164384, 2.112402, 0.0000]
 524                  */
 525                 [DRM_COLOR_YCBCR_BT709] = {
 526                         0x7E58, 0x7950, 0x0,
 527                         0x8888, 0x7950, 0xADA8,
 528                         0x0, 0x7950,  0x6870,
 529                 },
 530                 /*
 531                  * BT.2020 Limited range YCbCr -> full range RGB
 532                  * The matrix required is :
 533                  * [1.164, 0.000, 1.678,
 534                  *  1.164, -0.1873, -0.6504,
 535                  *  1.164, 2.1417, 0.0000]
 536                  */
 537                 [DRM_COLOR_YCBCR_BT2020] = {
 538                         0x7D70, 0x7950, 0x0,
 539                         0x8A68, 0x7950, 0xAC00,
 540                         0x0, 0x7950, 0x6890,
 541                 },
 542         };
 543         const u16 *csc;
 544
 545         if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 546                 csc = input_csc_matrix[plane_state->hw.color_encoding];
 547         else
 548                 csc = input_csc_matrix_lr[plane_state->hw.color_encoding];
 549
 550         I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |
 551                       GOFF(csc[1]));
 552         I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2]));
 553         I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) |
 554                       GOFF(csc[4]));
 555         I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5]));
 556         I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) |
 557                       GOFF(csc[7]));
 558         I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8]));
 559
 560         I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
 561                       PREOFF_YUV_TO_RGB_HI);
 562         if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 563                 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0);
 564         else
 565                 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
 566                               PREOFF_YUV_TO_RGB_ME);
 567         I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
 568                       PREOFF_YUV_TO_RGB_LO);
 569         I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
 570         I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
 571         I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 572 }
 573
 574 static void
 575 skl_program_plane(struct intel_plane *plane,
 576                   const struct intel_crtc_state *crtc_state,
 577                   const struct intel_plane_state *plane_state,
 578                   int color_plane)
 579 {
 580         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 581         enum plane_id plane_id = plane->id;
 582         enum pipe pipe = plane->pipe;
 583         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 584         u32 surf_addr = plane_state->color_plane[color_plane].offset;
 585         u32 stride = skl_plane_stride(plane_state, color_plane);
 586         u32 aux_stride = skl_plane_stride(plane_state, 1);
 587         int crtc_x = plane_state->uapi.dst.x1;
 588         int crtc_y = plane_state->uapi.dst.y1;
 589         u32 x = plane_state->color_plane[color_plane].x;
 590         u32 y = plane_state->color_plane[color_plane].y;
 591         u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 592         u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 593         const struct drm_framebuffer *fb = plane_state->hw.fb;
 594         u8 alpha = plane_state->hw.alpha >> 8;
 595         u32 plane_color_ctl = 0;
 596         unsigned long irqflags;
 597         u32 keymsk, keymax;
 598         u32 plane_ctl = plane_state->ctl;
 599
 600         plane_ctl |= skl_plane_ctl_crtc(crtc_state);
 601
 602         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 603                 plane_color_ctl = plane_state->color_ctl |
 604                         glk_plane_color_ctl_crtc(crtc_state);
 605
 606         /* Sizes are 0 based */
 607         src_w--;
 608         src_h--;
 609
 610         keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
 611
 612         keymsk = key->channel_mask & 0x7ffffff;
 613         if (alpha < 0xff)
 614                 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
 615
 616         /* The scaler will handle the output position */
 617         if (plane_state->scaler_id >= 0) {
 618                 crtc_x = 0;
 619                 crtc_y = 0;
 620         }
 621
 622         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 623
 624         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 625         I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 626         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 627         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 628                       (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 629
 630         if (icl_is_hdr_plane(dev_priv, plane_id))
 631                 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
 632
 633         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 634                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
 635
 636         if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
 637                 icl_program_input_csc(plane, crtc_state, plane_state);
 638
 639         skl_write_plane_wm(plane, crtc_state);
 640
 641         I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 642         I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
 643         I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
 644
 645         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 646
 647         if (INTEL_GEN(dev_priv) < 11)
 648                 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 649                               (plane_state->color_plane[1].y << 16) |
 650                               plane_state->color_plane[1].x);
 651
 652         /*
 653          * The control register self-arms if the plane was previously
 654          * disabled. Try to make the plane enable atomic by writing
 655          * the control register just before the surface register.
 656          */
 657         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 658         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 659                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 660
 661         if (plane_state->scaler_id >= 0)
 662                 skl_program_scaler(plane, crtc_state, plane_state);
 663
 664         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 665 }
 666
 667 static void
 668 skl_update_plane(struct intel_plane *plane,
 669                  const struct intel_crtc_state *crtc_state,
 670                  const struct intel_plane_state *plane_state)
 671 {
 672         int color_plane = 0;
 673
 674         if (plane_state->planar_linked_plane && !plane_state->planar_slave)
 675                 /* Program the UV plane on planar master */
 676                 color_plane = 1;
 677
 678         skl_program_plane(plane, crtc_state, plane_state, color_plane);
 679 }
 680 static void
 681 skl_disable_plane(struct intel_plane *plane,
 682                   const struct intel_crtc_state *crtc_state)
 683 {
 684         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 685         enum plane_id plane_id = plane->id;
 686         enum pipe pipe = plane->pipe;
 687         unsigned long irqflags;
 688
 689         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 690
 691         if (icl_is_hdr_plane(dev_priv, plane_id))
 692                 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0);
 693
 694         skl_write_plane_wm(plane, crtc_state);
 695
 696         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 697         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 698
 699         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 700 }
 701
 702 static bool
 703 skl_plane_get_hw_state(struct intel_plane *plane,
 704                        enum pipe *pipe)
 705 {
 706         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 707         enum intel_display_power_domain power_domain;
 708         enum plane_id plane_id = plane->id;
 709         intel_wakeref_t wakeref;
 710         bool ret;
 711
 712         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 713         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 714         if (!wakeref)
 715                 return false;
 716
 717         ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
 718
 719         *pipe = plane->pipe;
 720
 721         intel_display_power_put(dev_priv, power_domain, wakeref);
 722
 723         return ret;
 724 }
 725
 726 static void i9xx_plane_linear_gamma(u16 gamma[8])
 727 {
 728         /* The points are not evenly spaced. */
 729         static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 };
 730         int i;
 731
 732         for (i = 0; i < 8; i++)
 733                 gamma[i] = (in[i] << 8) / 32;
 734 }
 735
 736 static void
 737 chv_update_csc(const struct intel_plane_state *plane_state)
 738 {
 739         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 740         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 741         const struct drm_framebuffer *fb = plane_state->hw.fb;
 742         enum plane_id plane_id = plane->id;
 743         /*
 744          * |r|   | c0 c1 c2 |   |cr|
 745          * |g| = | c3 c4 c5 | x |y |
 746          * |b|   | c6 c7 c8 |   |cb|
 747          *
 748          * Coefficients are s3.12.
 749          *
 750          * Cb and Cr apparently come in as signed already, and
 751          * we always get full range data in on account of CLRC0/1.
 752          */
 753         static const s16 csc_matrix[][9] = {
 754                 /* BT.601 full range YCbCr -> full range RGB */
 755                 [DRM_COLOR_YCBCR_BT601] = {
 756                          5743, 4096,     0,
 757                         -2925, 4096, -1410,
 758                             0, 4096,  7258,
 759                 },
 760                 /* BT.709 full range YCbCr -> full range RGB */
 761                 [DRM_COLOR_YCBCR_BT709] = {
 762                          6450, 4096,     0,
 763                         -1917, 4096,  -767,
 764                             0, 4096,  7601,
 765                 },
 766         };
 767         const s16 *csc = csc_matrix[plane_state->hw.color_encoding];
 768
 769         /* Seems RGB data bypasses the CSC always */
 770         if (!fb->format->is_yuv)
 771                 return;
 772
 773         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 774         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 775         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 776
 777         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
 778         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
 779         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
 780         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
 781         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
 782
 783         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
 784         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 785         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 786
 787         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 788         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 789         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 790 }
 791
 792 #define SIN_0 0
 793 #define COS_0 1
 794
 795 static void
 796 vlv_update_clrc(const struct intel_plane_state *plane_state)
 797 {
 798         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 799         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 800         const struct drm_framebuffer *fb = plane_state->hw.fb;
 801         enum pipe pipe = plane->pipe;
 802         enum plane_id plane_id = plane->id;
 803         int contrast, brightness, sh_scale, sh_sin, sh_cos;
 804
 805         if (fb->format->is_yuv &&
 806             plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
 807                 /*
 808                  * Expand limited range to full range:
 809                  * Contrast is applied first and is used to expand Y range.
 810                  * Brightness is applied second and is used to remove the
 811                  * offset from Y. Saturation/hue is used to expand CbCr range.
 812                  */
 813                 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
 814                 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
 815                 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
 816                 sh_sin = SIN_0 * sh_scale;
 817                 sh_cos = COS_0 * sh_scale;
 818         } else {
 819                 /* Pass-through everything. */
 820                 contrast = 1 << 6;
 821                 brightness = 0;
 822                 sh_scale = 1 << 7;
 823                 sh_sin = SIN_0 * sh_scale;
 824                 sh_cos = COS_0 * sh_scale;
 825         }
 826
 827         /* FIXME these register are single buffered :( */
 828         I915_WRITE_FW(SPCLRC0(pipe, plane_id),
 829                       SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
 830         I915_WRITE_FW(SPCLRC1(pipe, plane_id),
 831                       SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
 832 }
 833
 834 static void
 835 vlv_plane_ratio(const struct intel_crtc_state *crtc_state,
 836                 const struct intel_plane_state *plane_state,
 837                 unsigned int *num, unsigned int *den)
 838 {
 839         u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
 840         const struct drm_framebuffer *fb = plane_state->hw.fb;
 841         unsigned int cpp = fb->format->cpp[0];
 842
 843         /*
 844          * VLV bspec only considers cases where all three planes are
 845          * enabled, and cases where the primary and one sprite is enabled.
 846          * Let's assume the case with just two sprites enabled also
 847          * maps to the latter case.
 848          */
 849         if (hweight8(active_planes) == 3) {
 850                 switch (cpp) {
 851                 case 8:
 852                         *num = 11;
 853                         *den = 8;
 854                         break;
 855                 case 4:
 856                         *num = 18;
 857                         *den = 16;
 858                         break;
 859                 default:
 860                         *num = 1;
 861                         *den = 1;
 862                         break;
 863                 }
 864         } else if (hweight8(active_planes) == 2) {
 865                 switch (cpp) {
 866                 case 8:
 867                         *num = 10;
 868                         *den = 8;
 869                         break;
 870                 case 4:
 871                         *num = 17;
 872                         *den = 16;
 873                         break;
 874                 default:
 875                         *num = 1;
 876                         *den = 1;
 877                         break;
 878                 }
 879         } else {
 880                 switch (cpp) {
 881                 case 8:
 882                         *num = 10;
 883                         *den = 8;
 884                         break;
 885                 default:
 886                         *num = 1;
 887                         *den = 1;
 888                         break;
 889                 }
 890         }
 891 }
 892
 893 int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 894                         const struct intel_plane_state *plane_state)
 895 {
 896         unsigned int pixel_rate;
 897         unsigned int num, den;
 898
 899         /*
 900          * Note that crtc_state->pixel_rate accounts for both
 901          * horizontal and vertical panel fitter downscaling factors.
 902          * Pre-HSW bspec tells us to only consider the horizontal
 903          * downscaling factor here. We ignore that and just consider
 904          * both for simplicity.
 905          */
 906         pixel_rate = crtc_state->pixel_rate;
 907
 908         vlv_plane_ratio(crtc_state, plane_state, &num, &den);
 909
 910         return DIV_ROUND_UP(pixel_rate * num, den);
 911 }
 912
 913 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 914 {
 915         u32 sprctl = 0;
 916
 917         if (crtc_state->gamma_enable)
 918                 sprctl |= SP_GAMMA_ENABLE;
 919
 920         return sprctl;
 921 }
 922
 923 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 924                           const struct intel_plane_state *plane_state)
 925 {
 926         const struct drm_framebuffer *fb = plane_state->hw.fb;
 927         unsigned int rotation = plane_state->hw.rotation;
 928         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 929         u32 sprctl;
 930
 931         sprctl = SP_ENABLE;
 932
 933         switch (fb->format->format) {
 934         case DRM_FORMAT_YUYV:
 935                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 936                 break;
 937         case DRM_FORMAT_YVYU:
 938                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 939                 break;
 940         case DRM_FORMAT_UYVY:
 941                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 942                 break;
 943         case DRM_FORMAT_VYUY:
 944                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 945                 break;
 946         case DRM_FORMAT_C8:
 947                 sprctl |= SP_FORMAT_8BPP;
 948                 break;
 949         case DRM_FORMAT_RGB565:
 950                 sprctl |= SP_FORMAT_BGR565;
 951                 break;
 952         case DRM_FORMAT_XRGB8888:
 953                 sprctl |= SP_FORMAT_BGRX8888;
 954                 break;
 955         case DRM_FORMAT_ARGB8888:
 956                 sprctl |= SP_FORMAT_BGRA8888;
 957                 break;
 958         case DRM_FORMAT_XBGR2101010:
 959                 sprctl |= SP_FORMAT_RGBX1010102;
 960                 break;
 961         case DRM_FORMAT_ABGR2101010:
 962                 sprctl |= SP_FORMAT_RGBA1010102;
 963                 break;
 964         case DRM_FORMAT_XRGB2101010:
 965                 sprctl |= SP_FORMAT_BGRX1010102;
 966                 break;
 967         case DRM_FORMAT_ARGB2101010:
 968                 sprctl |= SP_FORMAT_BGRA1010102;
 969                 break;
 970         case DRM_FORMAT_XBGR8888:
 971                 sprctl |= SP_FORMAT_RGBX8888;
 972                 break;
 973         case DRM_FORMAT_ABGR8888:
 974                 sprctl |= SP_FORMAT_RGBA8888;
 975                 break;
 976         default:
 977                 MISSING_CASE(fb->format->format);
 978                 return 0;
 979         }
 980
 981         if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 982                 sprctl |= SP_YUV_FORMAT_BT709;
 983
 984         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 985                 sprctl |= SP_TILED;
 986
 987         if (rotation & DRM_MODE_ROTATE_180)
 988                 sprctl |= SP_ROTATE_180;
 989
 990         if (rotation & DRM_MODE_REFLECT_X)
 991                 sprctl |= SP_MIRROR;
 992
 993         if (key->flags & I915_SET_COLORKEY_SOURCE)
 994                 sprctl |= SP_SOURCE_KEY;
 995
 996         return sprctl;
 997 }
 998
 999 static void vlv_update_gamma(const struct intel_plane_state *plane_state)
1000 {
1001         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1002         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1003         const struct drm_framebuffer *fb = plane_state->hw.fb;
1004         enum pipe pipe = plane->pipe;
1005         enum plane_id plane_id = plane->id;
1006         u16 gamma[8];
1007         int i;
1008
1009         /* Seems RGB data bypasses the gamma always */
1010         if (!fb->format->is_yuv)
1011                 return;
1012
1013         i9xx_plane_linear_gamma(gamma);
1014
1015         /* FIXME these register are single buffered :( */
1016         /* The two end points are implicit (0.0 and 1.0) */
1017         for (i = 1; i < 8 - 1; i++)
1018                 I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1),
1019                               gamma[i] << 16 |
1020                               gamma[i] << 8 |
1021                               gamma[i]);
1022 }
1023
1024 static void
1025 vlv_update_plane(struct intel_plane *plane,
1026                  const struct intel_crtc_state *crtc_state,
1027                  const struct intel_plane_state *plane_state)
1028 {
1029         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1030         enum pipe pipe = plane->pipe;
1031         enum plane_id plane_id = plane->id;
1032         u32 sprsurf_offset = plane_state->color_plane[0].offset;
1033         u32 linear_offset;
1034         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1035         int crtc_x = plane_state->uapi.dst.x1;
1036         int crtc_y = plane_state->uapi.dst.y1;
1037         u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
1038         u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
1039         u32 x = plane_state->color_plane[0].x;
1040         u32 y = plane_state->color_plane[0].y;
1041         unsigned long irqflags;
1042         u32 sprctl;
1043
1044         sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
1045
1046         /* Sizes are 0 based */
1047         crtc_w--;
1048         crtc_h--;
1049
1050         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1051
1052         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1053
1054         I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
1055                       plane_state->color_plane[0].stride);
1056         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
1057         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
1058         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
1059
1060         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
1061                 chv_update_csc(plane_state);
1062
1063         if (key->flags) {
1064                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
1065                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
1066                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
1067         }
1068
1069         I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
1070         I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
1071
1072         /*
1073          * The control register self-arms if the plane was previously
1074          * disabled. Try to make the plane enable atomic by writing
1075          * the control register just before the surface register.
1076          */
1077         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
1078         I915_WRITE_FW(SPSURF(pipe, plane_id),
1079                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
1080
1081         vlv_update_clrc(plane_state);
1082         vlv_update_gamma(plane_state);
1083
1084         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1085 }
1086
1087 static void
1088 vlv_disable_plane(struct intel_plane *plane,
1089                   const struct intel_crtc_state *crtc_state)
1090 {
1091         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1092         enum pipe pipe = plane->pipe;
1093         enum plane_id plane_id = plane->id;
1094         unsigned long irqflags;
1095
1096         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1097
1098         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
1099         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
1100
1101         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1102 }
1103
1104 static bool
1105 vlv_plane_get_hw_state(struct intel_plane *plane,
1106                        enum pipe *pipe)
1107 {
1108         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1109         enum intel_display_power_domain power_domain;
1110         enum plane_id plane_id = plane->id;
1111         intel_wakeref_t wakeref;
1112         bool ret;
1113
1114         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1115         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1116         if (!wakeref)
1117                 return false;
1118
1119         ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
1120
1121         *pipe = plane->pipe;
1122
1123         intel_display_power_put(dev_priv, power_domain, wakeref);
1124
1125         return ret;
1126 }
1127
1128 static void ivb_plane_ratio(const struct intel_crtc_state *crtc_state,
1129                             const struct intel_plane_state *plane_state,
1130                             unsigned int *num, unsigned int *den)
1131 {
1132         u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1133         const struct drm_framebuffer *fb = plane_state->hw.fb;
1134         unsigned int cpp = fb->format->cpp[0];
1135
1136         if (hweight8(active_planes) == 2) {
1137                 switch (cpp) {
1138                 case 8:
1139                         *num = 10;
1140                         *den = 8;
1141                         break;
1142                 case 4:
1143                         *num = 17;
1144                         *den = 16;
1145                         break;
1146                 default:
1147                         *num = 1;
1148                         *den = 1;
1149                         break;
1150                 }
1151         } else {
1152                 switch (cpp) {
1153                 case 8:
1154                         *num = 9;
1155                         *den = 8;
1156                         break;
1157                 default:
1158                         *num = 1;
1159                         *den = 1;
1160                         break;
1161                 }
1162         }
1163 }
1164
1165 static void ivb_plane_ratio_scaling(const struct intel_crtc_state *crtc_state,
1166                                     const struct intel_plane_state *plane_state,
1167                                     unsigned int *num, unsigned int *den)
1168 {
1169         const struct drm_framebuffer *fb = plane_state->hw.fb;
1170         unsigned int cpp = fb->format->cpp[0];
1171
1172         switch (cpp) {
1173         case 8:
1174                 *num = 12;
1175                 *den = 8;
1176                 break;
1177         case 4:
1178                 *num = 19;
1179                 *den = 16;
1180                 break;
1181         case 2:
1182                 *num = 33;
1183                 *den = 32;
1184                 break;
1185         default:
1186                 *num = 1;
1187                 *den = 1;
1188                 break;
1189         }
1190 }
1191
1192 int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
1193                         const struct intel_plane_state *plane_state)
1194 {
1195         unsigned int pixel_rate;
1196         unsigned int num, den;
1197
1198         /*
1199          * Note that crtc_state->pixel_rate accounts for both
1200          * horizontal and vertical panel fitter downscaling factors.
1201          * Pre-HSW bspec tells us to only consider the horizontal
1202          * downscaling factor here. We ignore that and just consider
1203          * both for simplicity.
1204          */
1205         pixel_rate = crtc_state->pixel_rate;
1206
1207         ivb_plane_ratio(crtc_state, plane_state, &num, &den);
1208
1209         return DIV_ROUND_UP(pixel_rate * num, den);
1210 }
1211
1212 static int ivb_sprite_min_cdclk(const struct intel_crtc_state *crtc_state,
1213                                 const struct intel_plane_state *plane_state)
1214 {
1215         unsigned int src_w, dst_w, pixel_rate;
1216         unsigned int num, den;
1217
1218         /*
1219          * Note that crtc_state->pixel_rate accounts for both
1220          * horizontal and vertical panel fitter downscaling factors.
1221          * Pre-HSW bspec tells us to only consider the horizontal
1222          * downscaling factor here. We ignore that and just consider
1223          * both for simplicity.
1224          */
1225         pixel_rate = crtc_state->pixel_rate;
1226
1227         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1228         dst_w = drm_rect_width(&plane_state->uapi.dst);
1229
1230         if (src_w != dst_w)
1231                 ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den);
1232         else
1233                 ivb_plane_ratio(crtc_state, plane_state, &num, &den);
1234
1235         /* Horizontal downscaling limits the maximum pixel rate */
1236         dst_w = min(src_w, dst_w);
1237
1238         return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w),
1239                                 den * dst_w);
1240 }
1241
1242 static void hsw_plane_ratio(const struct intel_crtc_state *crtc_state,
1243                             const struct intel_plane_state *plane_state,
1244                             unsigned int *num, unsigned int *den)
1245 {
1246         u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1247         const struct drm_framebuffer *fb = plane_state->hw.fb;
1248         unsigned int cpp = fb->format->cpp[0];
1249
1250         if (hweight8(active_planes) == 2) {
1251                 switch (cpp) {
1252                 case 8:
1253                         *num = 10;
1254                         *den = 8;
1255                         break;
1256                 default:
1257                         *num = 1;
1258                         *den = 1;
1259                         break;
1260                 }
1261         } else {
1262                 switch (cpp) {
1263                 case 8:
1264                         *num = 9;
1265                         *den = 8;
1266                         break;
1267                 default:
1268                         *num = 1;
1269                         *den = 1;
1270                         break;
1271                 }
1272         }
1273 }
1274
1275 int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
1276                         const struct intel_plane_state *plane_state)
1277 {
1278         unsigned int pixel_rate = crtc_state->pixel_rate;
1279         unsigned int num, den;
1280
1281         hsw_plane_ratio(crtc_state, plane_state, &num, &den);
1282
1283         return DIV_ROUND_UP(pixel_rate * num, den);
1284 }
1285
1286 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
1287 {
1288         u32 sprctl = 0;
1289
1290         if (crtc_state->gamma_enable)
1291                 sprctl |= SPRITE_GAMMA_ENABLE;
1292
1293         if (crtc_state->csc_enable)
1294                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
1295
1296         return sprctl;
1297 }
1298
1299 static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state)
1300 {
1301         struct drm_i915_private *dev_priv =
1302                 to_i915(plane_state->uapi.plane->dev);
1303         const struct drm_framebuffer *fb = plane_state->hw.fb;
1304
1305         return fb->format->cpp[0] == 8 &&
1306                 (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv));
1307 }
1308
1309 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
1310                           const struct intel_plane_state *plane_state)
1311 {
1312         struct drm_i915_private *dev_priv =
1313                 to_i915(plane_state->uapi.plane->dev);
1314         const struct drm_framebuffer *fb = plane_state->hw.fb;
1315         unsigned int rotation = plane_state->hw.rotation;
1316         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1317         u32 sprctl;
1318
1319         sprctl = SPRITE_ENABLE;
1320
1321         if (IS_IVYBRIDGE(dev_priv))
1322                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
1323
1324         switch (fb->format->format) {
1325         case DRM_FORMAT_XBGR8888:
1326                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
1327                 break;
1328         case DRM_FORMAT_XRGB8888:
1329                 sprctl |= SPRITE_FORMAT_RGBX888;
1330                 break;
1331         case DRM_FORMAT_XBGR2101010:
1332                 sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX;
1333                 break;
1334         case DRM_FORMAT_XRGB2101010:
1335                 sprctl |= SPRITE_FORMAT_RGBX101010;
1336                 break;
1337         case DRM_FORMAT_XBGR16161616F:
1338                 sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX;
1339                 break;
1340         case DRM_FORMAT_XRGB16161616F:
1341                 sprctl |= SPRITE_FORMAT_RGBX161616;
1342                 break;
1343         case DRM_FORMAT_YUYV:
1344                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
1345                 break;
1346         case DRM_FORMAT_YVYU:
1347                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
1348                 break;
1349         case DRM_FORMAT_UYVY:
1350                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
1351                 break;
1352         case DRM_FORMAT_VYUY:
1353                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
1354                 break;
1355         default:
1356                 MISSING_CASE(fb->format->format);
1357                 return 0;
1358         }
1359
1360         if (!ivb_need_sprite_gamma(plane_state))
1361                 sprctl |= SPRITE_INT_GAMMA_DISABLE;
1362
1363         if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
1364                 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
1365
1366         if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1367                 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
1368
1369         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1370                 sprctl |= SPRITE_TILED;
1371
1372         if (rotation & DRM_MODE_ROTATE_180)
1373                 sprctl |= SPRITE_ROTATE_180;
1374
1375         if (key->flags & I915_SET_COLORKEY_DESTINATION)
1376                 sprctl |= SPRITE_DEST_KEY;
1377         else if (key->flags & I915_SET_COLORKEY_SOURCE)
1378                 sprctl |= SPRITE_SOURCE_KEY;
1379
1380         return sprctl;
1381 }
1382
1383 static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,
1384                                     u16 gamma[18])
1385 {
1386         int scale, i;
1387
1388         /*
1389          * WaFP16GammaEnabling:ivb,hsw
1390          * "Workaround : When using the 64-bit format, the sprite output
1391          *  on each color channel has one quarter amplitude. It can be
1392          *  brought up to full amplitude by using sprite internal gamma
1393          *  correction, pipe gamma correction, or pipe color space
1394          *  conversion to multiply the sprite output by four."
1395          */
1396         scale = 4;
1397
1398         for (i = 0; i < 16; i++)
1399                 gamma[i] = min((scale * i << 10) / 16, (1 << 10) - 1);
1400
1401         gamma[i] = min((scale * i << 10) / 16, 1 << 10);
1402         i++;
1403
1404         gamma[i] = 3 << 10;
1405         i++;
1406 }
1407
1408 static void ivb_update_gamma(const struct intel_plane_state *plane_state)
1409 {
1410         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1411         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1412         enum pipe pipe = plane->pipe;
1413         u16 gamma[18];
1414         int i;
1415
1416         if (!ivb_need_sprite_gamma(plane_state))
1417                 return;
1418
1419         ivb_sprite_linear_gamma(plane_state, gamma);
1420
1421         /* FIXME these register are single buffered :( */
1422         for (i = 0; i < 16; i++)
1423                 I915_WRITE_FW(SPRGAMC(pipe, i),
1424                               gamma[i] << 20 |
1425                               gamma[i] << 10 |
1426                               gamma[i]);
1427
1428         I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]);
1429         I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]);
1430         I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]);
1431         i++;
1432
1433         I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]);
1434         I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]);
1435         I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]);
1436         i++;
1437 }
1438
1439 static void
1440 ivb_update_plane(struct intel_plane *plane,
1441                  const struct intel_crtc_state *crtc_state,
1442                  const struct intel_plane_state *plane_state)
1443 {
1444         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1445         enum pipe pipe = plane->pipe;
1446         u32 sprsurf_offset = plane_state->color_plane[0].offset;
1447         u32 linear_offset;
1448         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1449         int crtc_x = plane_state->uapi.dst.x1;
1450         int crtc_y = plane_state->uapi.dst.y1;
1451         u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
1452         u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
1453         u32 x = plane_state->color_plane[0].x;
1454         u32 y = plane_state->color_plane[0].y;
1455         u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1456         u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1457         u32 sprctl, sprscale = 0;
1458         unsigned long irqflags;
1459
1460         sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
1461
1462         /* Sizes are 0 based */
1463         src_w--;
1464         src_h--;
1465         crtc_w--;
1466         crtc_h--;
1467
1468         if (crtc_w != src_w || crtc_h != src_h)
1469                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
1470
1471         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1472
1473         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1474
1475         I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
1476         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
1477         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
1478         if (IS_IVYBRIDGE(dev_priv))
1479                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
1480
1481         if (key->flags) {
1482                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
1483                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
1484                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
1485         }
1486
1487         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
1488          * register */
1489         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1490                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
1491         } else {
1492                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
1493                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
1494         }
1495
1496         /*
1497          * The control register self-arms if the plane was previously
1498          * disabled. Try to make the plane enable atomic by writing
1499          * the control register just before the surface register.
1500          */
1501         I915_WRITE_FW(SPRCTL(pipe), sprctl);
1502         I915_WRITE_FW(SPRSURF(pipe),
1503                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
1504
1505         ivb_update_gamma(plane_state);
1506
1507         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1508 }
1509
1510 static void
1511 ivb_disable_plane(struct intel_plane *plane,
1512                   const struct intel_crtc_state *crtc_state)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1515         enum pipe pipe = plane->pipe;
1516         unsigned long irqflags;
1517
1518         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1519
1520         I915_WRITE_FW(SPRCTL(pipe), 0);
1521         /* Disable the scaler */
1522         if (IS_IVYBRIDGE(dev_priv))
1523                 I915_WRITE_FW(SPRSCALE(pipe), 0);
1524         I915_WRITE_FW(SPRSURF(pipe), 0);
1525
1526         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1527 }
1528
1529 static bool
1530 ivb_plane_get_hw_state(struct intel_plane *plane,
1531                        enum pipe *pipe)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1534         enum intel_display_power_domain power_domain;
1535         intel_wakeref_t wakeref;
1536         bool ret;
1537
1538         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1539         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1540         if (!wakeref)
1541                 return false;
1542
1543         ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
1544
1545         *pipe = plane->pipe;
1546
1547         intel_display_power_put(dev_priv, power_domain, wakeref);
1548
1549         return ret;
1550 }
1551
1552 static int g4x_sprite_min_cdclk(const struct intel_crtc_state *crtc_state,
1553                                 const struct intel_plane_state *plane_state)
1554 {
1555         const struct drm_framebuffer *fb = plane_state->hw.fb;
1556         unsigned int hscale, pixel_rate;
1557         unsigned int limit, decimate;
1558
1559         /*
1560          * Note that crtc_state->pixel_rate accounts for both
1561          * horizontal and vertical panel fitter downscaling factors.
1562          * Pre-HSW bspec tells us to only consider the horizontal
1563          * downscaling factor here. We ignore that and just consider
1564          * both for simplicity.
1565          */
1566         pixel_rate = crtc_state->pixel_rate;
1567
1568         /* Horizontal downscaling limits the maximum pixel rate */
1569         hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
1570                                       &plane_state->uapi.dst,
1571                                       0, INT_MAX);
1572         if (hscale < 0x10000)
1573                 return pixel_rate;
1574
1575         /* Decimation steps at 2x,4x,8x,16x */
1576         decimate = ilog2(hscale >> 16);
1577         hscale >>= decimate;
1578
1579         /* Starting limit is 90% of cdclk */
1580         limit = 9;
1581
1582         /* -10% per decimation step */
1583         limit -= decimate;
1584
1585         /* -10% for RGB */
1586         if (fb->format->cpp[0] >= 4)
1587                 limit--; /* -10% for RGB */
1588
1589         /*
1590          * We should also do -10% if sprite scaling is enabled
1591          * on the other pipe, but we can't really check for that,
1592          * so we ignore it.
1593          */
1594
1595         return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale),
1596                                 limit << 16);
1597 }
1598
1599 static unsigned int
1600 g4x_sprite_max_stride(struct intel_plane *plane,
1601                       u32 pixel_format, u64 modifier,
1602                       unsigned int rotation)
1603 {
1604         return 16384;
1605 }
1606
1607 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
1608 {
1609         u32 dvscntr = 0;
1610
1611         if (crtc_state->gamma_enable)
1612                 dvscntr |= DVS_GAMMA_ENABLE;
1613
1614         if (crtc_state->csc_enable)
1615                 dvscntr |= DVS_PIPE_CSC_ENABLE;
1616
1617         return dvscntr;
1618 }
1619
1620 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
1621                           const struct intel_plane_state *plane_state)
1622 {
1623         struct drm_i915_private *dev_priv =
1624                 to_i915(plane_state->uapi.plane->dev);
1625         const struct drm_framebuffer *fb = plane_state->hw.fb;
1626         unsigned int rotation = plane_state->hw.rotation;
1627         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1628         u32 dvscntr;
1629
1630         dvscntr = DVS_ENABLE;
1631
1632         if (IS_GEN(dev_priv, 6))
1633                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
1634
1635         switch (fb->format->format) {
1636         case DRM_FORMAT_XBGR8888:
1637                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
1638                 break;
1639         case DRM_FORMAT_XRGB8888:
1640                 dvscntr |= DVS_FORMAT_RGBX888;
1641                 break;
1642         case DRM_FORMAT_XBGR2101010:
1643                 dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR;
1644                 break;
1645         case DRM_FORMAT_XRGB2101010:
1646                 dvscntr |= DVS_FORMAT_RGBX101010;
1647                 break;
1648         case DRM_FORMAT_XBGR16161616F:
1649                 dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR;
1650                 break;
1651         case DRM_FORMAT_XRGB16161616F:
1652                 dvscntr |= DVS_FORMAT_RGBX161616;
1653                 break;
1654         case DRM_FORMAT_YUYV:
1655                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
1656                 break;
1657         case DRM_FORMAT_YVYU:
1658                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
1659                 break;
1660         case DRM_FORMAT_UYVY:
1661                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
1662                 break;
1663         case DRM_FORMAT_VYUY:
1664                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
1665                 break;
1666         default:
1667                 MISSING_CASE(fb->format->format);
1668                 return 0;
1669         }
1670
1671         if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
1672                 dvscntr |= DVS_YUV_FORMAT_BT709;
1673
1674         if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1675                 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
1676
1677         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1678                 dvscntr |= DVS_TILED;
1679
1680         if (rotation & DRM_MODE_ROTATE_180)
1681                 dvscntr |= DVS_ROTATE_180;
1682
1683         if (key->flags & I915_SET_COLORKEY_DESTINATION)
1684                 dvscntr |= DVS_DEST_KEY;
1685         else if (key->flags & I915_SET_COLORKEY_SOURCE)
1686                 dvscntr |= DVS_SOURCE_KEY;
1687
1688         return dvscntr;
1689 }
1690
1691 static void g4x_update_gamma(const struct intel_plane_state *plane_state)
1692 {
1693         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1694         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1695         const struct drm_framebuffer *fb = plane_state->hw.fb;
1696         enum pipe pipe = plane->pipe;
1697         u16 gamma[8];
1698         int i;
1699
1700         /* Seems RGB data bypasses the gamma always */
1701         if (!fb->format->is_yuv)
1702                 return;
1703
1704         i9xx_plane_linear_gamma(gamma);
1705
1706         /* FIXME these register are single buffered :( */
1707         /* The two end points are implicit (0.0 and 1.0) */
1708         for (i = 1; i < 8 - 1; i++)
1709                 I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1),
1710                               gamma[i] << 16 |
1711                               gamma[i] << 8 |
1712                               gamma[i]);
1713 }
1714
1715 static void ilk_sprite_linear_gamma(u16 gamma[17])
1716 {
1717         int i;
1718
1719         for (i = 0; i < 17; i++)
1720                 gamma[i] = (i << 10) / 16;
1721 }
1722
1723 static void ilk_update_gamma(const struct intel_plane_state *plane_state)
1724 {
1725         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1726         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1727         const struct drm_framebuffer *fb = plane_state->hw.fb;
1728         enum pipe pipe = plane->pipe;
1729         u16 gamma[17];
1730         int i;
1731
1732         /* Seems RGB data bypasses the gamma always */
1733         if (!fb->format->is_yuv)
1734                 return;
1735
1736         ilk_sprite_linear_gamma(gamma);
1737
1738         /* FIXME these register are single buffered :( */
1739         for (i = 0; i < 16; i++)
1740                 I915_WRITE_FW(DVSGAMC_ILK(pipe, i),
1741                               gamma[i] << 20 |
1742                               gamma[i] << 10 |
1743                               gamma[i]);
1744
1745         I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
1746         I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
1747         I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
1748         i++;
1749 }
1750
1751 static void
1752 g4x_update_plane(struct intel_plane *plane,
1753                  const struct intel_crtc_state *crtc_state,
1754                  const struct intel_plane_state *plane_state)
1755 {
1756         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1757         enum pipe pipe = plane->pipe;
1758         u32 dvssurf_offset = plane_state->color_plane[0].offset;
1759         u32 linear_offset;
1760         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1761         int crtc_x = plane_state->uapi.dst.x1;
1762         int crtc_y = plane_state->uapi.dst.y1;
1763         u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
1764         u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
1765         u32 x = plane_state->color_plane[0].x;
1766         u32 y = plane_state->color_plane[0].y;
1767         u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1768         u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1769         u32 dvscntr, dvsscale = 0;
1770         unsigned long irqflags;
1771
1772         dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
1773
1774         /* Sizes are 0 based */
1775         src_w--;
1776         src_h--;
1777         crtc_w--;
1778         crtc_h--;
1779
1780         if (crtc_w != src_w || crtc_h != src_h)
1781                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
1782
1783         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1784
1785         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1786
1787         I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
1788         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
1789         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
1790         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
1791
1792         if (key->flags) {
1793                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
1794                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
1795                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
1796         }
1797
1798         I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
1799         I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
1800
1801         /*
1802          * The control register self-arms if the plane was previously
1803          * disabled. Try to make the plane enable atomic by writing
1804          * the control register just before the surface register.
1805          */
1806         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
1807         I915_WRITE_FW(DVSSURF(pipe),
1808                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1809
1810         if (IS_G4X(dev_priv))
1811                 g4x_update_gamma(plane_state);
1812         else
1813                 ilk_update_gamma(plane_state);
1814
1815         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1816 }
1817
1818 static void
1819 g4x_disable_plane(struct intel_plane *plane,
1820                   const struct intel_crtc_state *crtc_state)
1821 {
1822         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1823         enum pipe pipe = plane->pipe;
1824         unsigned long irqflags;
1825
1826         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1827
1828         I915_WRITE_FW(DVSCNTR(pipe), 0);
1829         /* Disable the scaler */
1830         I915_WRITE_FW(DVSSCALE(pipe), 0);
1831         I915_WRITE_FW(DVSSURF(pipe), 0);
1832
1833         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1834 }
1835
1836 static bool
1837 g4x_plane_get_hw_state(struct intel_plane *plane,
1838                        enum pipe *pipe)
1839 {
1840         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1841         enum intel_display_power_domain power_domain;
1842         intel_wakeref_t wakeref;
1843         bool ret;
1844
1845         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1846         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1847         if (!wakeref)
1848                 return false;
1849
1850         ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
1851
1852         *pipe = plane->pipe;
1853
1854         intel_display_power_put(dev_priv, power_domain, wakeref);
1855
1856         return ret;
1857 }
1858
1859 static bool intel_fb_scalable(const struct drm_framebuffer *fb)
1860 {
1861         if (!fb)
1862                 return false;
1863
1864         switch (fb->format->format) {
1865         case DRM_FORMAT_C8:
1866                 return false;
1867         case DRM_FORMAT_XRGB16161616F:
1868         case DRM_FORMAT_ARGB16161616F:
1869         case DRM_FORMAT_XBGR16161616F:
1870         case DRM_FORMAT_ABGR16161616F:
1871                 return INTEL_GEN(to_i915(fb->dev)) >= 11;
1872         default:
1873                 return true;
1874         }
1875 }
1876
1877 static int
1878 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
1879                          struct intel_plane_state *plane_state)
1880 {
1881         const struct drm_framebuffer *fb = plane_state->hw.fb;
1882         const struct drm_rect *src = &plane_state->uapi.src;
1883         const struct drm_rect *dst = &plane_state->uapi.dst;
1884         int src_x, src_w, src_h, crtc_w, crtc_h;
1885         const struct drm_display_mode *adjusted_mode =
1886                 &crtc_state->hw.adjusted_mode;
1887         unsigned int stride = plane_state->color_plane[0].stride;
1888         unsigned int cpp = fb->format->cpp[0];
1889         unsigned int width_bytes;
1890         int min_width, min_height;
1891
1892         crtc_w = drm_rect_width(dst);
1893         crtc_h = drm_rect_height(dst);
1894
1895         src_x = src->x1 >> 16;
1896         src_w = drm_rect_width(src) >> 16;
1897         src_h = drm_rect_height(src) >> 16;
1898
1899         if (src_w == crtc_w && src_h == crtc_h)
1900                 return 0;
1901
1902         min_width = 3;
1903
1904         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1905                 if (src_h & 1) {
1906                         DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1907                         return -EINVAL;
1908                 }
1909                 min_height = 6;
1910         } else {
1911                 min_height = 3;
1912         }
1913
1914         width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1915
1916         if (src_w < min_width || src_h < min_height ||
1917             src_w > 2048 || src_h > 2048) {
1918                 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1919                               src_w, src_h, min_width, min_height, 2048, 2048);
1920                 return -EINVAL;
1921         }
1922
1923         if (width_bytes > 4096) {
1924                 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1925                               width_bytes, 4096);
1926                 return -EINVAL;
1927         }
1928
1929         if (stride > 4096) {
1930                 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1931                               stride, 4096);
1932                 return -EINVAL;
1933         }
1934
1935         return 0;
1936 }
1937
1938 static int
1939 g4x_sprite_check(struct intel_crtc_state *crtc_state,
1940                  struct intel_plane_state *plane_state)
1941 {
1942         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1943         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1944         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
1945         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1946         int ret;
1947
1948         if (intel_fb_scalable(plane_state->hw.fb)) {
1949                 if (INTEL_GEN(dev_priv) < 7) {
1950                         min_scale = 1;
1951                         max_scale = 16 << 16;
1952                 } else if (IS_IVYBRIDGE(dev_priv)) {
1953                         min_scale = 1;
1954                         max_scale = 2 << 16;
1955                 }
1956         }
1957
1958         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
1959                                                   &crtc_state->uapi,
1960                                                   min_scale, max_scale,
1961                                                   true, true);
1962         if (ret)
1963                 return ret;
1964
1965         ret = i9xx_check_plane_surface(plane_state);
1966         if (ret)
1967                 return ret;
1968
1969         if (!plane_state->uapi.visible)
1970                 return 0;
1971
1972         ret = intel_plane_check_src_coordinates(plane_state);
1973         if (ret)
1974                 return ret;
1975
1976         ret = g4x_sprite_check_scaling(crtc_state, plane_state);
1977         if (ret)
1978                 return ret;
1979
1980         if (INTEL_GEN(dev_priv) >= 7)
1981                 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1982         else
1983                 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1984
1985         return 0;
1986 }
1987
1988 int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
1989 {
1990         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1991         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1992         unsigned int rotation = plane_state->hw.rotation;
1993
1994         /* CHV ignores the mirror bit when the rotate bit is set :( */
1995         if (IS_CHERRYVIEW(dev_priv) &&
1996             rotation & DRM_MODE_ROTATE_180 &&
1997             rotation & DRM_MODE_REFLECT_X) {
1998                 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
1999                 return -EINVAL;
2000         }
2001
2002         return 0;
2003 }
2004
2005 static int
2006 vlv_sprite_check(struct intel_crtc_state *crtc_state,
2007                  struct intel_plane_state *plane_state)
2008 {
2009         int ret;
2010
2011         ret = chv_plane_check_rotation(plane_state);
2012         if (ret)
2013                 return ret;
2014
2015         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
2016                                                   &crtc_state->uapi,
2017                                                   DRM_PLANE_HELPER_NO_SCALING,
2018                                                   DRM_PLANE_HELPER_NO_SCALING,
2019                                                   true, true);
2020         if (ret)
2021                 return ret;
2022
2023         ret = i9xx_check_plane_surface(plane_state);
2024         if (ret)
2025                 return ret;
2026
2027         if (!plane_state->uapi.visible)
2028                 return 0;
2029
2030         ret = intel_plane_check_src_coordinates(plane_state);
2031         if (ret)
2032                 return ret;
2033
2034         plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
2035
2036         return 0;
2037 }
2038
2039 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
2040                               const struct intel_plane_state *plane_state)
2041 {
2042         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2043         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2044         const struct drm_framebuffer *fb = plane_state->hw.fb;
2045         unsigned int rotation = plane_state->hw.rotation;
2046         struct drm_format_name_buf format_name;
2047
2048         if (!fb)
2049                 return 0;
2050
2051         if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
2052             is_ccs_modifier(fb->modifier)) {
2053                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
2054                               rotation);
2055                 return -EINVAL;
2056         }
2057
2058         if (rotation & DRM_MODE_REFLECT_X &&
2059             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2060                 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
2061                 return -EINVAL;
2062         }
2063
2064         if (drm_rotation_90_or_270(rotation)) {
2065                 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2066                     fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
2067                         DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
2068                         return -EINVAL;
2069                 }
2070
2071                 /*
2072                  * 90/270 is not allowed with RGB64 16:16:16:16 and
2073                  * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
2074                  */
2075                 switch (fb->format->format) {
2076                 case DRM_FORMAT_RGB565:
2077                         if (INTEL_GEN(dev_priv) >= 11)
2078                                 break;
2079                         /* fall through */
2080                 case DRM_FORMAT_C8:
2081                 case DRM_FORMAT_XRGB16161616F:
2082                 case DRM_FORMAT_XBGR16161616F:
2083                 case DRM_FORMAT_ARGB16161616F:
2084                 case DRM_FORMAT_ABGR16161616F:
2085                 case DRM_FORMAT_Y210:
2086                 case DRM_FORMAT_Y212:
2087                 case DRM_FORMAT_Y216:
2088                 case DRM_FORMAT_XVYU12_16161616:
2089                 case DRM_FORMAT_XVYU16161616:
2090                         DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
2091                                       drm_get_format_name(fb->format->format,
2092                                                           &format_name));
2093                         return -EINVAL;
2094                 default:
2095                         break;
2096                 }
2097         }
2098
2099         /* Y-tiling is not supported in IF-ID Interlace mode */
2100         if (crtc_state->hw.enable &&
2101             crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
2102             (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
2103              fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
2104              fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2105              fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
2106                 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
2107                 return -EINVAL;
2108         }
2109
2110         return 0;
2111 }
2112
2113 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
2114                                            const struct intel_plane_state *plane_state)
2115 {
2116         struct drm_i915_private *dev_priv =
2117                 to_i915(plane_state->uapi.plane->dev);
2118         int crtc_x = plane_state->uapi.dst.x1;
2119         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
2120         int pipe_src_w = crtc_state->pipe_src_w;
2121
2122         /*
2123          * Display WA #1175: cnl,glk
2124          * Planes other than the cursor may cause FIFO underflow and display
2125          * corruption if starting less than 4 pixels from the right edge of
2126          * the screen.
2127          * Besides the above WA fix the similar problem, where planes other
2128          * than the cursor ending less than 4 pixels from the left edge of the
2129          * screen may cause FIFO underflow and display corruption.
2130          */
2131         if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
2132             (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
2133                 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
2134                               crtc_x + crtc_w < 4 ? "end" : "start",
2135                               crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
2136                               4, pipe_src_w - 4);
2137                 return -ERANGE;
2138         }
2139
2140         return 0;
2141 }
2142
2143 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
2144 {
2145         const struct drm_framebuffer *fb = plane_state->hw.fb;
2146         unsigned int rotation = plane_state->hw.rotation;
2147         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2148
2149         /* Display WA #1106 */
2150         if (drm_format_info_is_yuv_semiplanar(fb->format) && src_w & 3 &&
2151             (rotation == DRM_MODE_ROTATE_270 ||
2152              rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
2153                 DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n");
2154                 return -EINVAL;
2155         }
2156
2157         return 0;
2158 }
2159
2160 static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
2161                                const struct drm_framebuffer *fb)
2162 {
2163         /*
2164          * We don't yet know the final source width nor
2165          * whether we can use the HQ scaler mode. Assume
2166          * the best case.
2167          * FIXME need to properly check this later.
2168          */
2169         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
2170             !drm_format_info_is_yuv_semiplanar(fb->format))
2171                 return 0x30000 - 1;
2172         else
2173                 return 0x20000 - 1;
2174 }
2175
2176 static int skl_plane_check(struct intel_crtc_state *crtc_state,
2177                            struct intel_plane_state *plane_state)
2178 {
2179         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2180         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2181         const struct drm_framebuffer *fb = plane_state->hw.fb;
2182         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
2183         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
2184         int ret;
2185
2186         ret = skl_plane_check_fb(crtc_state, plane_state);
2187         if (ret)
2188                 return ret;
2189
2190         /* use scaler when colorkey is not required */
2191         if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
2192                 min_scale = 1;
2193                 max_scale = skl_plane_max_scale(dev_priv, fb);
2194         }
2195
2196         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
2197                                                   &crtc_state->uapi,
2198                                                   min_scale, max_scale,
2199                                                   true, true);
2200         if (ret)
2201                 return ret;
2202
2203         ret = skl_check_plane_surface(plane_state);
2204         if (ret)
2205                 return ret;
2206
2207         if (!plane_state->uapi.visible)
2208                 return 0;
2209
2210         ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
2211         if (ret)
2212                 return ret;
2213
2214         ret = intel_plane_check_src_coordinates(plane_state);
2215         if (ret)
2216                 return ret;
2217
2218         ret = skl_plane_check_nv12_rotation(plane_state);
2219         if (ret)
2220                 return ret;
2221
2222         /* HW only has 8 bits pixel precision, disable plane if invisible */
2223         if (!(plane_state->hw.alpha >> 8))
2224                 plane_state->uapi.visible = false;
2225
2226         plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
2227
2228         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2229                 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
2230                                                              plane_state);
2231
2232         if (drm_format_info_is_yuv_semiplanar(fb->format) &&
2233             icl_is_hdr_plane(dev_priv, plane->id))
2234                 /* Enable and use MPEG-2 chroma siting */
2235                 plane_state->cus_ctl = PLANE_CUS_ENABLE |
2236                         PLANE_CUS_HPHASE_0 |
2237                         PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
2238         else
2239                 plane_state->cus_ctl = 0;
2240
2241         return 0;
2242 }
2243
2244 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
2245 {
2246         return INTEL_GEN(dev_priv) >= 9;
2247 }
2248
2249 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
2250                                  const struct drm_intel_sprite_colorkey *set)
2251 {
2252         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2253         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2254         struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
2255
2256         *key = *set;
2257
2258         /*
2259          * We want src key enabled on the
2260          * sprite and not on the primary.
2261          */
2262         if (plane->id == PLANE_PRIMARY &&
2263             set->flags & I915_SET_COLORKEY_SOURCE)
2264                 key->flags = 0;
2265
2266         /*
2267          * On SKL+ we want dst key enabled on
2268          * the primary and not on the sprite.
2269          */
2270         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
2271             set->flags & I915_SET_COLORKEY_DESTINATION)
2272                 key->flags = 0;
2273 }
2274
2275 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2276                                     struct drm_file *file_priv)
2277 {
2278         struct drm_i915_private *dev_priv = to_i915(dev);
2279         struct drm_intel_sprite_colorkey *set = data;
2280         struct drm_plane *plane;
2281         struct drm_plane_state *plane_state;
2282         struct drm_atomic_state *state;
2283         struct drm_modeset_acquire_ctx ctx;
2284         int ret = 0;
2285
2286         /* ignore the pointless "none" flag */
2287         set->flags &= ~I915_SET_COLORKEY_NONE;
2288
2289         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
2290                 return -EINVAL;
2291
2292         /* Make sure we don't try to enable both src & dest simultaneously */
2293         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
2294                 return -EINVAL;
2295
2296         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2297             set->flags & I915_SET_COLORKEY_DESTINATION)
2298                 return -EINVAL;
2299
2300         plane = drm_plane_find(dev, file_priv, set->plane_id);
2301         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
2302                 return -ENOENT;
2303
2304         /*
2305          * SKL+ only plane 2 can do destination keying against plane 1.
2306          * Also multiple planes can't do destination keying on the same
2307          * pipe simultaneously.
2308          */
2309         if (INTEL_GEN(dev_priv) >= 9 &&
2310             to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
2311             set->flags & I915_SET_COLORKEY_DESTINATION)
2312                 return -EINVAL;
2313
2314         drm_modeset_acquire_init(&ctx, 0);
2315
2316         state = drm_atomic_state_alloc(plane->dev);
2317         if (!state) {
2318                 ret = -ENOMEM;
2319                 goto out;
2320         }
2321         state->acquire_ctx = &ctx;
2322
2323         while (1) {
2324                 plane_state = drm_atomic_get_plane_state(state, plane);
2325                 ret = PTR_ERR_OR_ZERO(plane_state);
2326                 if (!ret)
2327                         intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
2328
2329                 /*
2330                  * On some platforms we have to configure
2331                  * the dst colorkey on the primary plane.
2332                  */
2333                 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
2334                         struct intel_crtc *crtc =
2335                                 intel_get_crtc_for_pipe(dev_priv,
2336                                                         to_intel_plane(plane)->pipe);
2337
2338                         plane_state = drm_atomic_get_plane_state(state,
2339                                                                  crtc->base.primary);
2340                         ret = PTR_ERR_OR_ZERO(plane_state);
2341                         if (!ret)
2342                                 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
2343                 }
2344
2345                 if (!ret)
2346                         ret = drm_atomic_commit(state);
2347
2348                 if (ret != -EDEADLK)
2349                         break;
2350
2351                 drm_atomic_state_clear(state);
2352                 drm_modeset_backoff(&ctx);
2353         }
2354
2355         drm_atomic_state_put(state);
2356 out:
2357         drm_modeset_drop_locks(&ctx);
2358         drm_modeset_acquire_fini(&ctx);
2359         return ret;
2360 }
2361
2362 static const u32 g4x_plane_formats[] = {
2363         DRM_FORMAT_XRGB8888,
2364         DRM_FORMAT_YUYV,
2365         DRM_FORMAT_YVYU,
2366         DRM_FORMAT_UYVY,
2367         DRM_FORMAT_VYUY,
2368 };
2369
2370 static const u64 i9xx_plane_format_modifiers[] = {
2371         I915_FORMAT_MOD_X_TILED,
2372         DRM_FORMAT_MOD_LINEAR,
2373         DRM_FORMAT_MOD_INVALID
2374 };
2375
2376 static const u32 snb_plane_formats[] = {
2377         DRM_FORMAT_XRGB8888,
2378         DRM_FORMAT_XBGR8888,
2379         DRM_FORMAT_XRGB2101010,
2380         DRM_FORMAT_XBGR2101010,
2381         DRM_FORMAT_XRGB16161616F,
2382         DRM_FORMAT_XBGR16161616F,
2383         DRM_FORMAT_YUYV,
2384         DRM_FORMAT_YVYU,
2385         DRM_FORMAT_UYVY,
2386         DRM_FORMAT_VYUY,
2387 };
2388
2389 static const u32 vlv_plane_formats[] = {
2390         DRM_FORMAT_C8,
2391         DRM_FORMAT_RGB565,
2392         DRM_FORMAT_ABGR8888,
2393         DRM_FORMAT_ARGB8888,
2394         DRM_FORMAT_XBGR8888,
2395         DRM_FORMAT_XRGB8888,
2396         DRM_FORMAT_XBGR2101010,
2397         DRM_FORMAT_ABGR2101010,
2398         DRM_FORMAT_YUYV,
2399         DRM_FORMAT_YVYU,
2400         DRM_FORMAT_UYVY,
2401         DRM_FORMAT_VYUY,
2402 };
2403
2404 static const u32 chv_pipe_b_sprite_formats[] = {
2405         DRM_FORMAT_C8,
2406         DRM_FORMAT_RGB565,
2407         DRM_FORMAT_XRGB8888,
2408         DRM_FORMAT_XBGR8888,
2409         DRM_FORMAT_ARGB8888,
2410         DRM_FORMAT_ABGR8888,
2411         DRM_FORMAT_XRGB2101010,
2412         DRM_FORMAT_XBGR2101010,
2413         DRM_FORMAT_ARGB2101010,
2414         DRM_FORMAT_ABGR2101010,
2415         DRM_FORMAT_YUYV,
2416         DRM_FORMAT_YVYU,
2417         DRM_FORMAT_UYVY,
2418         DRM_FORMAT_VYUY,
2419 };
2420
2421 static const u32 skl_plane_formats[] = {
2422         DRM_FORMAT_C8,
2423         DRM_FORMAT_RGB565,
2424         DRM_FORMAT_XRGB8888,
2425         DRM_FORMAT_XBGR8888,
2426         DRM_FORMAT_ARGB8888,
2427         DRM_FORMAT_ABGR8888,
2428         DRM_FORMAT_XRGB2101010,
2429         DRM_FORMAT_XBGR2101010,
2430         DRM_FORMAT_XRGB16161616F,
2431         DRM_FORMAT_XBGR16161616F,
2432         DRM_FORMAT_YUYV,
2433         DRM_FORMAT_YVYU,
2434         DRM_FORMAT_UYVY,
2435         DRM_FORMAT_VYUY,
2436 };
2437
2438 static const u32 skl_planar_formats[] = {
2439         DRM_FORMAT_C8,
2440         DRM_FORMAT_RGB565,
2441         DRM_FORMAT_XRGB8888,
2442         DRM_FORMAT_XBGR8888,
2443         DRM_FORMAT_ARGB8888,
2444         DRM_FORMAT_ABGR8888,
2445         DRM_FORMAT_XRGB2101010,
2446         DRM_FORMAT_XBGR2101010,
2447         DRM_FORMAT_XRGB16161616F,
2448         DRM_FORMAT_XBGR16161616F,
2449         DRM_FORMAT_YUYV,
2450         DRM_FORMAT_YVYU,
2451         DRM_FORMAT_UYVY,
2452         DRM_FORMAT_VYUY,
2453         DRM_FORMAT_NV12,
2454 };
2455
2456 static const u32 glk_planar_formats[] = {
2457         DRM_FORMAT_C8,
2458         DRM_FORMAT_RGB565,
2459         DRM_FORMAT_XRGB8888,
2460         DRM_FORMAT_XBGR8888,
2461         DRM_FORMAT_ARGB8888,
2462         DRM_FORMAT_ABGR8888,
2463         DRM_FORMAT_XRGB2101010,
2464         DRM_FORMAT_XBGR2101010,
2465         DRM_FORMAT_XRGB16161616F,
2466         DRM_FORMAT_XBGR16161616F,
2467         DRM_FORMAT_YUYV,
2468         DRM_FORMAT_YVYU,
2469         DRM_FORMAT_UYVY,
2470         DRM_FORMAT_VYUY,
2471         DRM_FORMAT_NV12,
2472         DRM_FORMAT_P010,
2473         DRM_FORMAT_P012,
2474         DRM_FORMAT_P016,
2475 };
2476
2477 static const u32 icl_sdr_y_plane_formats[] = {
2478         DRM_FORMAT_C8,
2479         DRM_FORMAT_RGB565,
2480         DRM_FORMAT_XRGB8888,
2481         DRM_FORMAT_XBGR8888,
2482         DRM_FORMAT_ARGB8888,
2483         DRM_FORMAT_ABGR8888,
2484         DRM_FORMAT_XRGB2101010,
2485         DRM_FORMAT_XBGR2101010,
2486         DRM_FORMAT_YUYV,
2487         DRM_FORMAT_YVYU,
2488         DRM_FORMAT_UYVY,
2489         DRM_FORMAT_VYUY,
2490         DRM_FORMAT_Y210,
2491         DRM_FORMAT_Y212,
2492         DRM_FORMAT_Y216,
2493         DRM_FORMAT_XVYU2101010,
2494         DRM_FORMAT_XVYU12_16161616,
2495         DRM_FORMAT_XVYU16161616,
2496 };
2497
2498 static const u32 icl_sdr_uv_plane_formats[] = {
2499         DRM_FORMAT_C8,
2500         DRM_FORMAT_RGB565,
2501         DRM_FORMAT_XRGB8888,
2502         DRM_FORMAT_XBGR8888,
2503         DRM_FORMAT_ARGB8888,
2504         DRM_FORMAT_ABGR8888,
2505         DRM_FORMAT_XRGB2101010,
2506         DRM_FORMAT_XBGR2101010,
2507         DRM_FORMAT_YUYV,
2508         DRM_FORMAT_YVYU,
2509         DRM_FORMAT_UYVY,
2510         DRM_FORMAT_VYUY,
2511         DRM_FORMAT_NV12,
2512         DRM_FORMAT_P010,
2513         DRM_FORMAT_P012,
2514         DRM_FORMAT_P016,
2515         DRM_FORMAT_Y210,
2516         DRM_FORMAT_Y212,
2517         DRM_FORMAT_Y216,
2518         DRM_FORMAT_XVYU2101010,
2519         DRM_FORMAT_XVYU12_16161616,
2520         DRM_FORMAT_XVYU16161616,
2521 };
2522
2523 static const u32 icl_hdr_plane_formats[] = {
2524         DRM_FORMAT_C8,
2525         DRM_FORMAT_RGB565,
2526         DRM_FORMAT_XRGB8888,
2527         DRM_FORMAT_XBGR8888,
2528         DRM_FORMAT_ARGB8888,
2529         DRM_FORMAT_ABGR8888,
2530         DRM_FORMAT_XRGB2101010,
2531         DRM_FORMAT_XBGR2101010,
2532         DRM_FORMAT_XRGB16161616F,
2533         DRM_FORMAT_XBGR16161616F,
2534         DRM_FORMAT_ARGB16161616F,
2535         DRM_FORMAT_ABGR16161616F,
2536         DRM_FORMAT_YUYV,
2537         DRM_FORMAT_YVYU,
2538         DRM_FORMAT_UYVY,
2539         DRM_FORMAT_VYUY,
2540         DRM_FORMAT_NV12,
2541         DRM_FORMAT_P010,
2542         DRM_FORMAT_P012,
2543         DRM_FORMAT_P016,
2544         DRM_FORMAT_Y210,
2545         DRM_FORMAT_Y212,
2546         DRM_FORMAT_Y216,
2547         DRM_FORMAT_XVYU2101010,
2548         DRM_FORMAT_XVYU12_16161616,
2549         DRM_FORMAT_XVYU16161616,
2550 };
2551
2552 static const u64 skl_plane_format_modifiers_noccs[] = {
2553         I915_FORMAT_MOD_Yf_TILED,
2554         I915_FORMAT_MOD_Y_TILED,
2555         I915_FORMAT_MOD_X_TILED,
2556         DRM_FORMAT_MOD_LINEAR,
2557         DRM_FORMAT_MOD_INVALID
2558 };
2559
2560 static const u64 skl_plane_format_modifiers_ccs[] = {
2561         I915_FORMAT_MOD_Yf_TILED_CCS,
2562         I915_FORMAT_MOD_Y_TILED_CCS,
2563         I915_FORMAT_MOD_Yf_TILED,
2564         I915_FORMAT_MOD_Y_TILED,
2565         I915_FORMAT_MOD_X_TILED,
2566         DRM_FORMAT_MOD_LINEAR,
2567         DRM_FORMAT_MOD_INVALID
2568 };
2569
2570 static const u64 gen12_plane_format_modifiers_noccs[] = {
2571         I915_FORMAT_MOD_Y_TILED,
2572         I915_FORMAT_MOD_X_TILED,
2573         DRM_FORMAT_MOD_LINEAR,
2574         DRM_FORMAT_MOD_INVALID
2575 };
2576
2577 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
2578                                             u32 format, u64 modifier)
2579 {
2580         switch (modifier) {
2581         case DRM_FORMAT_MOD_LINEAR:
2582         case I915_FORMAT_MOD_X_TILED:
2583                 break;
2584         default:
2585                 return false;
2586         }
2587
2588         switch (format) {
2589         case DRM_FORMAT_XRGB8888:
2590         case DRM_FORMAT_YUYV:
2591         case DRM_FORMAT_YVYU:
2592         case DRM_FORMAT_UYVY:
2593         case DRM_FORMAT_VYUY:
2594                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2595                     modifier == I915_FORMAT_MOD_X_TILED)
2596                         return true;
2597                 /* fall through */
2598         default:
2599                 return false;
2600         }
2601 }
2602
2603 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
2604                                             u32 format, u64 modifier)
2605 {
2606         switch (modifier) {
2607         case DRM_FORMAT_MOD_LINEAR:
2608         case I915_FORMAT_MOD_X_TILED:
2609                 break;
2610         default:
2611                 return false;
2612         }
2613
2614         switch (format) {
2615         case DRM_FORMAT_XRGB8888:
2616         case DRM_FORMAT_XBGR8888:
2617         case DRM_FORMAT_XRGB2101010:
2618         case DRM_FORMAT_XBGR2101010:
2619         case DRM_FORMAT_XRGB16161616F:
2620         case DRM_FORMAT_XBGR16161616F:
2621         case DRM_FORMAT_YUYV:
2622         case DRM_FORMAT_YVYU:
2623         case DRM_FORMAT_UYVY:
2624         case DRM_FORMAT_VYUY:
2625                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2626                     modifier == I915_FORMAT_MOD_X_TILED)
2627                         return true;
2628                 /* fall through */
2629         default:
2630                 return false;
2631         }
2632 }
2633
2634 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
2635                                             u32 format, u64 modifier)
2636 {
2637         switch (modifier) {
2638         case DRM_FORMAT_MOD_LINEAR:
2639         case I915_FORMAT_MOD_X_TILED:
2640                 break;
2641         default:
2642                 return false;
2643         }
2644
2645         switch (format) {
2646         case DRM_FORMAT_C8:
2647         case DRM_FORMAT_RGB565:
2648         case DRM_FORMAT_ABGR8888:
2649         case DRM_FORMAT_ARGB8888:
2650         case DRM_FORMAT_XBGR8888:
2651         case DRM_FORMAT_XRGB8888:
2652         case DRM_FORMAT_XBGR2101010:
2653         case DRM_FORMAT_ABGR2101010:
2654         case DRM_FORMAT_XRGB2101010:
2655         case DRM_FORMAT_ARGB2101010:
2656         case DRM_FORMAT_YUYV:
2657         case DRM_FORMAT_YVYU:
2658         case DRM_FORMAT_UYVY:
2659         case DRM_FORMAT_VYUY:
2660                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2661                     modifier == I915_FORMAT_MOD_X_TILED)
2662                         return true;
2663                 /* fall through */
2664         default:
2665                 return false;
2666         }
2667 }
2668
2669 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
2670                                            u32 format, u64 modifier)
2671 {
2672         struct intel_plane *plane = to_intel_plane(_plane);
2673
2674         switch (modifier) {
2675         case DRM_FORMAT_MOD_LINEAR:
2676         case I915_FORMAT_MOD_X_TILED:
2677         case I915_FORMAT_MOD_Y_TILED:
2678         case I915_FORMAT_MOD_Yf_TILED:
2679                 break;
2680         case I915_FORMAT_MOD_Y_TILED_CCS:
2681         case I915_FORMAT_MOD_Yf_TILED_CCS:
2682                 if (!plane->has_ccs)
2683                         return false;
2684                 break;
2685         default:
2686                 return false;
2687         }
2688
2689         switch (format) {
2690         case DRM_FORMAT_XRGB8888:
2691         case DRM_FORMAT_XBGR8888:
2692         case DRM_FORMAT_ARGB8888:
2693         case DRM_FORMAT_ABGR8888:
2694                 if (is_ccs_modifier(modifier))
2695                         return true;
2696                 /* fall through */
2697         case DRM_FORMAT_RGB565:
2698         case DRM_FORMAT_XRGB2101010:
2699         case DRM_FORMAT_XBGR2101010:
2700         case DRM_FORMAT_YUYV:
2701         case DRM_FORMAT_YVYU:
2702         case DRM_FORMAT_UYVY:
2703         case DRM_FORMAT_VYUY:
2704         case DRM_FORMAT_NV12:
2705         case DRM_FORMAT_P010:
2706         case DRM_FORMAT_P012:
2707         case DRM_FORMAT_P016:
2708         case DRM_FORMAT_XVYU2101010:
2709                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
2710                         return true;
2711                 /* fall through */
2712         case DRM_FORMAT_C8:
2713         case DRM_FORMAT_XBGR16161616F:
2714         case DRM_FORMAT_ABGR16161616F:
2715         case DRM_FORMAT_XRGB16161616F:
2716         case DRM_FORMAT_ARGB16161616F:
2717         case DRM_FORMAT_Y210:
2718         case DRM_FORMAT_Y212:
2719         case DRM_FORMAT_Y216:
2720         case DRM_FORMAT_XVYU12_16161616:
2721         case DRM_FORMAT_XVYU16161616:
2722                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2723                     modifier == I915_FORMAT_MOD_X_TILED ||
2724                     modifier == I915_FORMAT_MOD_Y_TILED)
2725                         return true;
2726                 /* fall through */
2727         default:
2728                 return false;
2729         }
2730 }
2731
2732 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
2733                                              u32 format, u64 modifier)
2734 {
2735         switch (modifier) {
2736         case DRM_FORMAT_MOD_LINEAR:
2737         case I915_FORMAT_MOD_X_TILED:
2738         case I915_FORMAT_MOD_Y_TILED:
2739                 break;
2740         default:
2741                 return false;
2742         }
2743
2744         switch (format) {
2745         case DRM_FORMAT_XRGB8888:
2746         case DRM_FORMAT_XBGR8888:
2747         case DRM_FORMAT_ARGB8888:
2748         case DRM_FORMAT_ABGR8888:
2749         case DRM_FORMAT_RGB565:
2750         case DRM_FORMAT_XRGB2101010:
2751         case DRM_FORMAT_XBGR2101010:
2752         case DRM_FORMAT_YUYV:
2753         case DRM_FORMAT_YVYU:
2754         case DRM_FORMAT_UYVY:
2755         case DRM_FORMAT_VYUY:
2756         case DRM_FORMAT_NV12:
2757         case DRM_FORMAT_P010:
2758         case DRM_FORMAT_P012:
2759         case DRM_FORMAT_P016:
2760         case DRM_FORMAT_XVYU2101010:
2761         case DRM_FORMAT_C8:
2762         case DRM_FORMAT_XBGR16161616F:
2763         case DRM_FORMAT_ABGR16161616F:
2764         case DRM_FORMAT_XRGB16161616F:
2765         case DRM_FORMAT_ARGB16161616F:
2766         case DRM_FORMAT_Y210:
2767         case DRM_FORMAT_Y212:
2768         case DRM_FORMAT_Y216:
2769         case DRM_FORMAT_XVYU12_16161616:
2770         case DRM_FORMAT_XVYU16161616:
2771                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2772                     modifier == I915_FORMAT_MOD_X_TILED ||
2773                     modifier == I915_FORMAT_MOD_Y_TILED)
2774                         return true;
2775                 /* fall through */
2776         default:
2777                 return false;
2778         }
2779 }
2780
2781 static const struct drm_plane_funcs g4x_sprite_funcs = {
2782         .update_plane = drm_atomic_helper_update_plane,
2783         .disable_plane = drm_atomic_helper_disable_plane,
2784         .destroy = intel_plane_destroy,
2785         .atomic_duplicate_state = intel_plane_duplicate_state,
2786         .atomic_destroy_state = intel_plane_destroy_state,
2787         .format_mod_supported = g4x_sprite_format_mod_supported,
2788 };
2789
2790 static const struct drm_plane_funcs snb_sprite_funcs = {
2791         .update_plane = drm_atomic_helper_update_plane,
2792         .disable_plane = drm_atomic_helper_disable_plane,
2793         .destroy = intel_plane_destroy,
2794         .atomic_duplicate_state = intel_plane_duplicate_state,
2795         .atomic_destroy_state = intel_plane_destroy_state,
2796         .format_mod_supported = snb_sprite_format_mod_supported,
2797 };
2798
2799 static const struct drm_plane_funcs vlv_sprite_funcs = {
2800         .update_plane = drm_atomic_helper_update_plane,
2801         .disable_plane = drm_atomic_helper_disable_plane,
2802         .destroy = intel_plane_destroy,
2803         .atomic_duplicate_state = intel_plane_duplicate_state,
2804         .atomic_destroy_state = intel_plane_destroy_state,
2805         .format_mod_supported = vlv_sprite_format_mod_supported,
2806 };
2807
2808 static const struct drm_plane_funcs skl_plane_funcs = {
2809         .update_plane = drm_atomic_helper_update_plane,
2810         .disable_plane = drm_atomic_helper_disable_plane,
2811         .destroy = intel_plane_destroy,
2812         .atomic_duplicate_state = intel_plane_duplicate_state,
2813         .atomic_destroy_state = intel_plane_destroy_state,
2814         .format_mod_supported = skl_plane_format_mod_supported,
2815 };
2816
2817 static const struct drm_plane_funcs gen12_plane_funcs = {
2818         .update_plane = drm_atomic_helper_update_plane,
2819         .disable_plane = drm_atomic_helper_disable_plane,
2820         .destroy = intel_plane_destroy,
2821         .atomic_duplicate_state = intel_plane_duplicate_state,
2822         .atomic_destroy_state = intel_plane_destroy_state,
2823         .format_mod_supported = gen12_plane_format_mod_supported,
2824 };
2825
2826 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
2827                               enum pipe pipe, enum plane_id plane_id)
2828 {
2829         if (!HAS_FBC(dev_priv))
2830                 return false;
2831
2832         return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
2833 }
2834
2835 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2836                                  enum pipe pipe, enum plane_id plane_id)
2837 {
2838         /* Display WA #0870: skl, bxt */
2839         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
2840                 return false;
2841
2842         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
2843                 return false;
2844
2845         if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
2846                 return false;
2847
2848         return true;
2849 }
2850
2851 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
2852                                         enum pipe pipe, enum plane_id plane_id,
2853                                         int *num_formats)
2854 {
2855         if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2856                 *num_formats = ARRAY_SIZE(skl_planar_formats);
2857                 return skl_planar_formats;
2858         } else {
2859                 *num_formats = ARRAY_SIZE(skl_plane_formats);
2860                 return skl_plane_formats;
2861         }
2862 }
2863
2864 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
2865                                         enum pipe pipe, enum plane_id plane_id,
2866                                         int *num_formats)
2867 {
2868         if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2869                 *num_formats = ARRAY_SIZE(glk_planar_formats);
2870                 return glk_planar_formats;
2871         } else {
2872                 *num_formats = ARRAY_SIZE(skl_plane_formats);
2873                 return skl_plane_formats;
2874         }
2875 }
2876
2877 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
2878                                         enum pipe pipe, enum plane_id plane_id,
2879                                         int *num_formats)
2880 {
2881         if (icl_is_hdr_plane(dev_priv, plane_id)) {
2882                 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
2883                 return icl_hdr_plane_formats;
2884         } else if (icl_is_nv12_y_plane(plane_id)) {
2885                 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
2886                 return icl_sdr_y_plane_formats;
2887         } else {
2888                 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
2889                 return icl_sdr_uv_plane_formats;
2890         }
2891 }
2892
2893 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2894                               enum pipe pipe, enum plane_id plane_id)
2895 {
2896         if (plane_id == PLANE_CURSOR)
2897                 return false;
2898
2899         if (INTEL_GEN(dev_priv) >= 10)
2900                 return true;
2901
2902         if (IS_GEMINILAKE(dev_priv))
2903                 return pipe != PIPE_C;
2904
2905         return pipe != PIPE_C &&
2906                 (plane_id == PLANE_PRIMARY ||
2907                  plane_id == PLANE_SPRITE0);
2908 }
2909
2910 struct intel_plane *
2911 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2912                            enum pipe pipe, enum plane_id plane_id)
2913 {
2914         static const struct drm_plane_funcs *plane_funcs;
2915         struct intel_plane *plane;
2916         enum drm_plane_type plane_type;
2917         unsigned int supported_rotations;
2918         unsigned int possible_crtcs;
2919         const u64 *modifiers;
2920         const u32 *formats;
2921         int num_formats;
2922         int ret;
2923
2924         plane = intel_plane_alloc();
2925         if (IS_ERR(plane))
2926                 return plane;
2927
2928         plane->pipe = pipe;
2929         plane->id = plane_id;
2930         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2931
2932         plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
2933         if (plane->has_fbc) {
2934                 struct intel_fbc *fbc = &dev_priv->fbc;
2935
2936                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
2937         }
2938
2939         plane->max_stride = skl_plane_max_stride;
2940         plane->update_plane = skl_update_plane;
2941         plane->disable_plane = skl_disable_plane;
2942         plane->get_hw_state = skl_plane_get_hw_state;
2943         plane->check_plane = skl_plane_check;
2944         plane->min_cdclk = skl_plane_min_cdclk;
2945
2946         if (INTEL_GEN(dev_priv) >= 11)
2947                 formats = icl_get_plane_formats(dev_priv, pipe,
2948                                                 plane_id, &num_formats);
2949         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2950                 formats = glk_get_plane_formats(dev_priv, pipe,
2951                                                 plane_id, &num_formats);
2952         else
2953                 formats = skl_get_plane_formats(dev_priv, pipe,
2954                                                 plane_id, &num_formats);
2955
2956         if (INTEL_GEN(dev_priv) >= 12) {
2957                 /* TODO: Implement support for gen-12 CCS modifiers */
2958                 plane->has_ccs = false;
2959                 modifiers = gen12_plane_format_modifiers_noccs;
2960                 plane_funcs = &gen12_plane_funcs;
2961         } else {
2962                 plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
2963                 if (plane->has_ccs)
2964                         modifiers = skl_plane_format_modifiers_ccs;
2965                 else
2966                         modifiers = skl_plane_format_modifiers_noccs;
2967                 plane_funcs = &skl_plane_funcs;
2968         }
2969
2970         if (plane_id == PLANE_PRIMARY)
2971                 plane_type = DRM_PLANE_TYPE_PRIMARY;
2972         else
2973                 plane_type = DRM_PLANE_TYPE_OVERLAY;
2974
2975         possible_crtcs = BIT(pipe);
2976
2977         ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2978                                        possible_crtcs, plane_funcs,
2979                                        formats, num_formats, modifiers,
2980                                        plane_type,
2981                                        "plane %d%c", plane_id + 1,
2982                                        pipe_name(pipe));
2983         if (ret)
2984                 goto fail;
2985
2986         supported_rotations =
2987                 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2988                 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2989
2990         if (INTEL_GEN(dev_priv) >= 10)
2991                 supported_rotations |= DRM_MODE_REFLECT_X;
2992
2993         drm_plane_create_rotation_property(&plane->base,
2994                                            DRM_MODE_ROTATE_0,
2995                                            supported_rotations);
2996
2997         drm_plane_create_color_properties(&plane->base,
2998                                           BIT(DRM_COLOR_YCBCR_BT601) |
2999                                           BIT(DRM_COLOR_YCBCR_BT709),
3000                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
3001                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
3002                                           DRM_COLOR_YCBCR_BT709,
3003                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
3004
3005         drm_plane_create_alpha_property(&plane->base);
3006         drm_plane_create_blend_mode_property(&plane->base,
3007                                              BIT(DRM_MODE_BLEND_PIXEL_NONE) |
3008                                              BIT(DRM_MODE_BLEND_PREMULTI) |
3009                                              BIT(DRM_MODE_BLEND_COVERAGE));
3010
3011         drm_plane_create_zpos_immutable_property(&plane->base, plane_id);
3012
3013         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
3014
3015         return plane;
3016
3017 fail:
3018         intel_plane_free(plane);
3019
3020         return ERR_PTR(ret);
3021 }
3022
3023 struct intel_plane *
3024 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
3025                           enum pipe pipe, int sprite)
3026 {
3027         struct intel_plane *plane;
3028         const struct drm_plane_funcs *plane_funcs;
3029         unsigned long possible_crtcs;
3030         unsigned int supported_rotations;
3031         const u64 *modifiers;
3032         const u32 *formats;
3033         int num_formats;
3034         int ret, zpos;
3035
3036         if (INTEL_GEN(dev_priv) >= 9)
3037                 return skl_universal_plane_create(dev_priv, pipe,
3038                                                   PLANE_SPRITE0 + sprite);
3039
3040         plane = intel_plane_alloc();
3041         if (IS_ERR(plane))
3042                 return plane;
3043
3044         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3045                 plane->max_stride = i9xx_plane_max_stride;
3046                 plane->update_plane = vlv_update_plane;
3047                 plane->disable_plane = vlv_disable_plane;
3048                 plane->get_hw_state = vlv_plane_get_hw_state;
3049                 plane->check_plane = vlv_sprite_check;
3050                 plane->min_cdclk = vlv_plane_min_cdclk;
3051
3052                 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
3053                         formats = chv_pipe_b_sprite_formats;
3054                         num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
3055                 } else {
3056                         formats = vlv_plane_formats;
3057                         num_formats = ARRAY_SIZE(vlv_plane_formats);
3058                 }
3059                 modifiers = i9xx_plane_format_modifiers;
3060
3061                 plane_funcs = &vlv_sprite_funcs;
3062         } else if (INTEL_GEN(dev_priv) >= 7) {
3063                 plane->max_stride = g4x_sprite_max_stride;
3064                 plane->update_plane = ivb_update_plane;
3065                 plane->disable_plane = ivb_disable_plane;
3066                 plane->get_hw_state = ivb_plane_get_hw_state;
3067                 plane->check_plane = g4x_sprite_check;
3068
3069                 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3070                         plane->min_cdclk = hsw_plane_min_cdclk;
3071                 else
3072                         plane->min_cdclk = ivb_sprite_min_cdclk;
3073
3074                 formats = snb_plane_formats;
3075                 num_formats = ARRAY_SIZE(snb_plane_formats);
3076                 modifiers = i9xx_plane_format_modifiers;
3077
3078                 plane_funcs = &snb_sprite_funcs;
3079         } else {
3080                 plane->max_stride = g4x_sprite_max_stride;
3081                 plane->update_plane = g4x_update_plane;
3082                 plane->disable_plane = g4x_disable_plane;
3083                 plane->get_hw_state = g4x_plane_get_hw_state;
3084                 plane->check_plane = g4x_sprite_check;
3085                 plane->min_cdclk = g4x_sprite_min_cdclk;
3086
3087                 modifiers = i9xx_plane_format_modifiers;
3088                 if (IS_GEN(dev_priv, 6)) {
3089                         formats = snb_plane_formats;
3090                         num_formats = ARRAY_SIZE(snb_plane_formats);
3091
3092                         plane_funcs = &snb_sprite_funcs;
3093                 } else {
3094                         formats = g4x_plane_formats;
3095                         num_formats = ARRAY_SIZE(g4x_plane_formats);
3096
3097                         plane_funcs = &g4x_sprite_funcs;
3098                 }
3099         }
3100
3101         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
3102                 supported_rotations =
3103                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
3104                         DRM_MODE_REFLECT_X;
3105         } else {
3106                 supported_rotations =
3107                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
3108         }
3109
3110         plane->pipe = pipe;
3111         plane->id = PLANE_SPRITE0 + sprite;
3112         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
3113
3114         possible_crtcs = BIT(pipe);
3115
3116         ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
3117                                        possible_crtcs, plane_funcs,
3118                                        formats, num_formats, modifiers,
3119                                        DRM_PLANE_TYPE_OVERLAY,
3120                                        "sprite %c", sprite_name(pipe, sprite));
3121         if (ret)
3122                 goto fail;
3123
3124         drm_plane_create_rotation_property(&plane->base,
3125                                            DRM_MODE_ROTATE_0,
3126                                            supported_rotations);
3127
3128         drm_plane_create_color_properties(&plane->base,
3129                                           BIT(DRM_COLOR_YCBCR_BT601) |
3130                                           BIT(DRM_COLOR_YCBCR_BT709),
3131                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
3132                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
3133                                           DRM_COLOR_YCBCR_BT709,
3134                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
3135
3136         zpos = sprite + 1;
3137         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
3138
3139         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
3140
3141         return plane;
3142
3143 fail:
3144         intel_plane_free(plane);
3145
3146         return ERR_PTR(ret);
3147 }