drivers/gpu/drm/i915/display/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/slab.h>
  28
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_crtc.h>
  31 #include <drm/drm_edid.h>
  32 #include <drm/drm_mipi_dsi.h>
  33
  34 #include "i915_drv.h"
  35 #include "intel_atomic.h"
  36 #include "intel_connector.h"
  37 #include "intel_display_types.h"
  38 #include "intel_dsi.h"
  39 #include "intel_fifo_underrun.h"
  40 #include "intel_panel.h"
  41 #include "intel_sideband.h"
  42
  43 /* return pixels in terms of txbyteclkhs */
  44 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  45                        u16 burst_mode_ratio)
  46 {
  47         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  48                                          8 * 100), lane_count);
  49 }
  50
  51 /* return pixels equvalent to txbyteclkhs */
  52 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  53                         u16 burst_mode_ratio)
  54 {
  55         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  56                                                 (bpp * burst_mode_ratio));
  57 }
  58
  59 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  60 {
  61         /* It just so happens the VBT matches register contents. */
  62         switch (fmt) {
  63         case VID_MODE_FORMAT_RGB888:
  64                 return MIPI_DSI_FMT_RGB888;
  65         case VID_MODE_FORMAT_RGB666:
  66                 return MIPI_DSI_FMT_RGB666;
  67         case VID_MODE_FORMAT_RGB666_PACKED:
  68                 return MIPI_DSI_FMT_RGB666_PACKED;
  69         case VID_MODE_FORMAT_RGB565:
  70                 return MIPI_DSI_FMT_RGB565;
  71         default:
  72                 MISSING_CASE(fmt);
  73                 return MIPI_DSI_FMT_RGB666;
  74         }
  75 }
  76
  77 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  78 {
  79         struct drm_encoder *encoder = &intel_dsi->base.base;
  80         struct drm_device *dev = encoder->dev;
  81         struct drm_i915_private *dev_priv = to_i915(dev);
  82         u32 mask;
  83
  84         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  85                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  86
  87         if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
  88                                   mask, 100))
  89                 DRM_ERROR("DPI FIFOs are not empty\n");
  90 }
  91
  92 static void write_data(struct drm_i915_private *dev_priv,
  93                        i915_reg_t reg,
  94                        const u8 *data, u32 len)
  95 {
  96         u32 i, j;
  97
  98         for (i = 0; i < len; i += 4) {
  99                 u32 val = 0;
 100
 101                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 102                         val |= *data++ << 8 * j;
 103
 104                 I915_WRITE(reg, val);
 105         }
 106 }
 107
 108 static void read_data(struct drm_i915_private *dev_priv,
 109                       i915_reg_t reg,
 110                       u8 *data, u32 len)
 111 {
 112         u32 i, j;
 113
 114         for (i = 0; i < len; i += 4) {
 115                 u32 val = I915_READ(reg);
 116
 117                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 118                         *data++ = val >> 8 * j;
 119         }
 120 }
 121
 122 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 123                                        const struct mipi_dsi_msg *msg)
 124 {
 125         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 126         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 127         struct drm_i915_private *dev_priv = to_i915(dev);
 128         enum port port = intel_dsi_host->port;
 129         struct mipi_dsi_packet packet;
 130         ssize_t ret;
 131         const u8 *header, *data;
 132         i915_reg_t data_reg, ctrl_reg;
 133         u32 data_mask, ctrl_mask;
 134
 135         ret = mipi_dsi_create_packet(&packet, msg);
 136         if (ret < 0)
 137                 return ret;
 138
 139         header = packet.header;
 140         data = packet.payload;
 141
 142         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 143                 data_reg = MIPI_LP_GEN_DATA(port);
 144                 data_mask = LP_DATA_FIFO_FULL;
 145                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 146                 ctrl_mask = LP_CTRL_FIFO_FULL;
 147         } else {
 148                 data_reg = MIPI_HS_GEN_DATA(port);
 149                 data_mask = HS_DATA_FIFO_FULL;
 150                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 151                 ctrl_mask = HS_CTRL_FIFO_FULL;
 152         }
 153
 154         /* note: this is never true for reads */
 155         if (packet.payload_length) {
 156                 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 157                                             data_mask, 50))
 158                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 159
 160                 write_data(dev_priv, data_reg, packet.payload,
 161                            packet.payload_length);
 162         }
 163
 164         if (msg->rx_len) {
 165                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 166         }
 167
 168         if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 169                                     ctrl_mask, 50)) {
 170                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 171         }
 172
 173         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 174
 175         /* ->rx_len is set only for reads */
 176         if (msg->rx_len) {
 177                 data_mask = GEN_READ_DATA_AVAIL;
 178                 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
 179                                           data_mask, 50))
 180                         DRM_ERROR("Timeout waiting for read data.\n");
 181
 182                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 183         }
 184
 185         /* XXX: fix for reads and writes */
 186         return 4 + packet.payload_length;
 187 }
 188
 189 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 190                                  struct mipi_dsi_device *dsi)
 191 {
 192         return 0;
 193 }
 194
 195 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 196                                  struct mipi_dsi_device *dsi)
 197 {
 198         return 0;
 199 }
 200
 201 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 202         .attach = intel_dsi_host_attach,
 203         .detach = intel_dsi_host_detach,
 204         .transfer = intel_dsi_host_transfer,
 205 };
 206
 207 /*
 208  * send a video mode command
 209  *
 210  * XXX: commands with data in MIPI_DPI_DATA?
 211  */
 212 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 213                         enum port port)
 214 {
 215         struct drm_encoder *encoder = &intel_dsi->base.base;
 216         struct drm_device *dev = encoder->dev;
 217         struct drm_i915_private *dev_priv = to_i915(dev);
 218         u32 mask;
 219
 220         /* XXX: pipe, hs */
 221         if (hs)
 222                 cmd &= ~DPI_LP_MODE;
 223         else
 224                 cmd |= DPI_LP_MODE;
 225
 226         /* clear bit */
 227         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 228
 229         /* XXX: old code skips write if control unchanged */
 230         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 231                 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
 232
 233         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 234
 235         mask = SPL_PKT_SENT_INTERRUPT;
 236         if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
 237                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 238
 239         return 0;
 240 }
 241
 242 static void band_gap_reset(struct drm_i915_private *dev_priv)
 243 {
 244         vlv_flisdsi_get(dev_priv);
 245
 246         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 247         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 248         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 249         udelay(150);
 250         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 251         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 252
 253         vlv_flisdsi_put(dev_priv);
 254 }
 255
 256 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 257                                     struct intel_crtc_state *pipe_config,
 258                                     struct drm_connector_state *conn_state)
 259 {
 260         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 261         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 262                                                    base);
 263         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 264         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 265         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 266         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 267         int ret;
 268
 269         DRM_DEBUG_KMS("\n");
 270         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 271
 272         if (fixed_mode) {
 273                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 274
 275                 if (HAS_GMCH(dev_priv))
 276                         intel_gmch_panel_fitting(crtc, pipe_config,
 277                                                  conn_state->scaling_mode);
 278                 else
 279                         intel_pch_panel_fitting(crtc, pipe_config,
 280                                                 conn_state->scaling_mode);
 281         }
 282
 283         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 284                 return -EINVAL;
 285
 286         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 287         adjusted_mode->flags = 0;
 288
 289         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 290                 pipe_config->pipe_bpp = 24;
 291         else
 292                 pipe_config->pipe_bpp = 18;
 293
 294         if (IS_GEN9_LP(dev_priv)) {
 295                 /* Enable Frame time stamp based scanline reporting */
 296                 adjusted_mode->private_flags |=
 297                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 298
 299                 /* Dual link goes to DSI transcoder A. */
 300                 if (intel_dsi->ports == BIT(PORT_C))
 301                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 302                 else
 303                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 304
 305                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 306                 if (ret)
 307                         return -EINVAL;
 308         } else {
 309                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 310                 if (ret)
 311                         return -EINVAL;
 312         }
 313
 314         pipe_config->clock_set = true;
 315
 316         return 0;
 317 }
 318
 319 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 320 {
 321         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 322         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 323         enum port port;
 324         u32 tmp;
 325         bool cold_boot = false;
 326
 327         /* Set the MIPI mode
 328          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 329          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 330          */
 331         for_each_dsi_port(port, intel_dsi->ports) {
 332                 tmp = I915_READ(MIPI_CTRL(port));
 333                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 334         }
 335
 336         /* Put the IO into reset */
 337         tmp = I915_READ(MIPI_CTRL(PORT_A));
 338         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 339         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 340
 341         /* Program LP Wake */
 342         for_each_dsi_port(port, intel_dsi->ports) {
 343                 tmp = I915_READ(MIPI_CTRL(port));
 344                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 345                         tmp &= ~GLK_LP_WAKE;
 346                 else
 347                         tmp |= GLK_LP_WAKE;
 348                 I915_WRITE(MIPI_CTRL(port), tmp);
 349         }
 350
 351         /* Wait for Pwr ACK */
 352         for_each_dsi_port(port, intel_dsi->ports) {
 353                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 354                                           GLK_MIPIIO_PORT_POWERED, 20))
 355                         DRM_ERROR("MIPIO port is powergated\n");
 356         }
 357
 358         /* Check for cold boot scenario */
 359         for_each_dsi_port(port, intel_dsi->ports) {
 360                 cold_boot |=
 361                         !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY);
 362         }
 363
 364         return cold_boot;
 365 }
 366
 367 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 368 {
 369         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 370         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 371         enum port port;
 372         u32 val;
 373
 374         /* Wait for MIPI PHY status bit to set */
 375         for_each_dsi_port(port, intel_dsi->ports) {
 376                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 377                                           GLK_PHY_STATUS_PORT_READY, 20))
 378                         DRM_ERROR("PHY is not ON\n");
 379         }
 380
 381         /* Get IO out of reset */
 382         val = I915_READ(MIPI_CTRL(PORT_A));
 383         I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
 384
 385         /* Get IO out of Low power state*/
 386         for_each_dsi_port(port, intel_dsi->ports) {
 387                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 388                         val = I915_READ(MIPI_DEVICE_READY(port));
 389                         val &= ~ULPS_STATE_MASK;
 390                         val |= DEVICE_READY;
 391                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 392                         usleep_range(10, 15);
 393                 } else {
 394                         /* Enter ULPS */
 395                         val = I915_READ(MIPI_DEVICE_READY(port));
 396                         val &= ~ULPS_STATE_MASK;
 397                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 398                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 399
 400                         /* Wait for ULPS active */
 401                         if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 402                                                     GLK_ULPS_NOT_ACTIVE, 20))
 403                                 DRM_ERROR("ULPS not active\n");
 404
 405                         /* Exit ULPS */
 406                         val = I915_READ(MIPI_DEVICE_READY(port));
 407                         val &= ~ULPS_STATE_MASK;
 408                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 409                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 410
 411                         /* Enter Normal Mode */
 412                         val = I915_READ(MIPI_DEVICE_READY(port));
 413                         val &= ~ULPS_STATE_MASK;
 414                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 415                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 416
 417                         val = I915_READ(MIPI_CTRL(port));
 418                         val &= ~GLK_LP_WAKE;
 419                         I915_WRITE(MIPI_CTRL(port), val);
 420                 }
 421         }
 422
 423         /* Wait for Stop state */
 424         for_each_dsi_port(port, intel_dsi->ports) {
 425                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 426                                           GLK_DATA_LANE_STOP_STATE, 20))
 427                         DRM_ERROR("Date lane not in STOP state\n");
 428         }
 429
 430         /* Wait for AFE LATCH */
 431         for_each_dsi_port(port, intel_dsi->ports) {
 432                 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
 433                                           AFE_LATCHOUT, 20))
 434                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 435         }
 436 }
 437
 438 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 439 {
 440         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 441         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 442         enum port port;
 443         u32 val;
 444
 445         DRM_DEBUG_KMS("\n");
 446
 447         /* Enable MIPI PHY transparent latch */
 448         for_each_dsi_port(port, intel_dsi->ports) {
 449                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 450                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 451                 usleep_range(2000, 2500);
 452         }
 453
 454         /* Clear ULPS and set device ready */
 455         for_each_dsi_port(port, intel_dsi->ports) {
 456                 val = I915_READ(MIPI_DEVICE_READY(port));
 457                 val &= ~ULPS_STATE_MASK;
 458                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 459                 usleep_range(2000, 2500);
 460                 val |= DEVICE_READY;
 461                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 462         }
 463 }
 464
 465 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 468         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 469         enum port port;
 470         u32 val;
 471
 472         DRM_DEBUG_KMS("\n");
 473
 474         vlv_flisdsi_get(dev_priv);
 475         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 476          * needed everytime after power gate */
 477         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 478         vlv_flisdsi_put(dev_priv);
 479
 480         /* bandgap reset is needed after everytime we do power gate */
 481         band_gap_reset(dev_priv);
 482
 483         for_each_dsi_port(port, intel_dsi->ports) {
 484
 485                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 486                 usleep_range(2500, 3000);
 487
 488                 /* Enable MIPI PHY transparent latch
 489                  * Common bit for both MIPI Port A & MIPI Port C
 490                  * No similar bit in MIPI Port C reg
 491                  */
 492                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 493                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 494                 usleep_range(1000, 1500);
 495
 496                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 497                 usleep_range(2500, 3000);
 498
 499                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 500                 usleep_range(2500, 3000);
 501         }
 502 }
 503
 504 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 505 {
 506         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 507
 508         if (IS_GEMINILAKE(dev_priv))
 509                 glk_dsi_device_ready(encoder);
 510         else if (IS_GEN9_LP(dev_priv))
 511                 bxt_dsi_device_ready(encoder);
 512         else
 513                 vlv_dsi_device_ready(encoder);
 514 }
 515
 516 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 517 {
 518         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 519         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 520         enum port port;
 521         u32 val;
 522
 523         /* Enter ULPS */
 524         for_each_dsi_port(port, intel_dsi->ports) {
 525                 val = I915_READ(MIPI_DEVICE_READY(port));
 526                 val &= ~ULPS_STATE_MASK;
 527                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 528                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 529         }
 530
 531         /* Wait for MIPI PHY status bit to unset */
 532         for_each_dsi_port(port, intel_dsi->ports) {
 533                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 534                                             GLK_PHY_STATUS_PORT_READY, 20))
 535                         DRM_ERROR("PHY is not turning OFF\n");
 536         }
 537
 538         /* Wait for Pwr ACK bit to unset */
 539         for_each_dsi_port(port, intel_dsi->ports) {
 540                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 541                                             GLK_MIPIIO_PORT_POWERED, 20))
 542                         DRM_ERROR("MIPI IO Port is not powergated\n");
 543         }
 544 }
 545
 546 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 547 {
 548         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 549         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 550         enum port port;
 551         u32 tmp;
 552
 553         /* Put the IO into reset */
 554         tmp = I915_READ(MIPI_CTRL(PORT_A));
 555         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 556         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 557
 558         /* Wait for MIPI PHY status bit to unset */
 559         for_each_dsi_port(port, intel_dsi->ports) {
 560                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 561                                             GLK_PHY_STATUS_PORT_READY, 20))
 562                         DRM_ERROR("PHY is not turning OFF\n");
 563         }
 564
 565         /* Clear MIPI mode */
 566         for_each_dsi_port(port, intel_dsi->ports) {
 567                 tmp = I915_READ(MIPI_CTRL(port));
 568                 tmp &= ~GLK_MIPIIO_ENABLE;
 569                 I915_WRITE(MIPI_CTRL(port), tmp);
 570         }
 571 }
 572
 573 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 574 {
 575         glk_dsi_enter_low_power_mode(encoder);
 576         glk_dsi_disable_mipi_io(encoder);
 577 }
 578
 579 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 580 {
 581         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 582         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 583         enum port port;
 584
 585         DRM_DEBUG_KMS("\n");
 586         for_each_dsi_port(port, intel_dsi->ports) {
 587                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 588                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 589                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 590                 u32 val;
 591
 592                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 593                                                         ULPS_STATE_ENTER);
 594                 usleep_range(2000, 2500);
 595
 596                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 597                                                         ULPS_STATE_EXIT);
 598                 usleep_range(2000, 2500);
 599
 600                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 601                                                         ULPS_STATE_ENTER);
 602                 usleep_range(2000, 2500);
 603
 604                 /*
 605                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 606                  * Port A only. MIPI Port C has no similar bit for checking.
 607                  */
 608                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 609                     intel_de_wait_for_clear(dev_priv, port_ctrl,
 610                                             AFE_LATCHOUT, 30))
 611                         DRM_ERROR("DSI LP not going Low\n");
 612
 613                 /* Disable MIPI PHY transparent latch */
 614                 val = I915_READ(port_ctrl);
 615                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 616                 usleep_range(1000, 1500);
 617
 618                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 619                 usleep_range(2000, 2500);
 620         }
 621 }
 622
 623 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 624                                   const struct intel_crtc_state *crtc_state)
 625 {
 626         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 627         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 628         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 629         enum port port;
 630
 631         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 632                 u32 temp;
 633                 if (IS_GEN9_LP(dev_priv)) {
 634                         for_each_dsi_port(port, intel_dsi->ports) {
 635                                 temp = I915_READ(MIPI_CTRL(port));
 636                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 637                                         intel_dsi->pixel_overlap <<
 638                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 639                                 I915_WRITE(MIPI_CTRL(port), temp);
 640                         }
 641                 } else {
 642                         temp = I915_READ(VLV_CHICKEN_3);
 643                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 644                                         intel_dsi->pixel_overlap <<
 645                                         PIXEL_OVERLAP_CNT_SHIFT;
 646                         I915_WRITE(VLV_CHICKEN_3, temp);
 647                 }
 648         }
 649
 650         for_each_dsi_port(port, intel_dsi->ports) {
 651                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 652                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 653                 u32 temp;
 654
 655                 temp = I915_READ(port_ctrl);
 656
 657                 temp &= ~LANE_CONFIGURATION_MASK;
 658                 temp &= ~DUAL_LINK_MODE_MASK;
 659
 660                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 661                         temp |= (intel_dsi->dual_link - 1)
 662                                                 << DUAL_LINK_MODE_SHIFT;
 663                         if (IS_BROXTON(dev_priv))
 664                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 665                         else
 666                                 temp |= crtc->pipe ?
 667                                         LANE_CONFIGURATION_DUAL_LINK_B :
 668                                         LANE_CONFIGURATION_DUAL_LINK_A;
 669                 }
 670
 671                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 672                         temp |= DITHERING_ENABLE;
 673
 674                 /* assert ip_tg_enable signal */
 675                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 676                 POSTING_READ(port_ctrl);
 677         }
 678 }
 679
 680 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 681 {
 682         struct drm_device *dev = encoder->base.dev;
 683         struct drm_i915_private *dev_priv = to_i915(dev);
 684         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 685         enum port port;
 686
 687         for_each_dsi_port(port, intel_dsi->ports) {
 688                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 689                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 690                 u32 temp;
 691
 692                 /* de-assert ip_tg_enable signal */
 693                 temp = I915_READ(port_ctrl);
 694                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 695                 POSTING_READ(port_ctrl);
 696         }
 697 }
 698
 699 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 700                               const struct intel_crtc_state *pipe_config);
 701 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 702
 703 /*
 704  * Panel enable/disable sequences from the VBT spec.
 705  *
 706  * Note the spec has AssertReset / DeassertReset swapped from their
 707  * usual naming. We use the normal names to avoid confusion (so below
 708  * they are swapped compared to the spec).
 709  *
 710  * Steps starting with MIPI refer to VBT sequences, note that for v2
 711  * VBTs several steps which have a VBT in v2 are expected to be handled
 712  * directly by the driver, by directly driving gpios for example.
 713  *
 714  * v2 video mode seq         v3 video mode seq         command mode seq
 715  * - power on                - MIPIPanelPowerOn        - power on
 716  * - wait t1+t2                                        - wait t1+t2
 717  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 718  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 719  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 720  *                                                     - MIPITearOn
 721  *                                                     - MIPIDisplayOn
 722  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 723  * - MIPIDisplayOn           - MIPIDisplayOn
 724  * - wait t5                                           - wait t5
 725  * - backlight on            - MIPIBacklightOn         - backlight on
 726  * ...                       ...                       ... issue mem cmds ...
 727  * - backlight off           - MIPIBacklightOff        - backlight off
 728  * - wait t6                                           - wait t6
 729  * - MIPIDisplayOff
 730  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 731  *                                                     - MIPITearOff
 732  *                           - MIPIDisplayOff          - MIPIDisplayOff
 733  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 734  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 735  * - wait t3                                           - wait t3
 736  * - power off               - MIPIPanelPowerOff       - power off
 737  * - wait t4                                           - wait t4
 738  */
 739
 740 /*
 741  * DSI port enable has to be done before pipe and plane enable, so we do it in
 742  * the pre_enable hook instead of the enable hook.
 743  */
 744 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 745                                  const struct intel_crtc_state *pipe_config,
 746                                  const struct drm_connector_state *conn_state)
 747 {
 748         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 749         struct drm_crtc *crtc = pipe_config->uapi.crtc;
 750         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 752         enum pipe pipe = intel_crtc->pipe;
 753         enum port port;
 754         u32 val;
 755         bool glk_cold_boot = false;
 756
 757         DRM_DEBUG_KMS("\n");
 758
 759         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 760
 761         /*
 762          * The BIOS may leave the PLL in a wonky state where it doesn't
 763          * lock. It needs to be fully powered down to fix it.
 764          */
 765         if (IS_GEN9_LP(dev_priv)) {
 766                 bxt_dsi_pll_disable(encoder);
 767                 bxt_dsi_pll_enable(encoder, pipe_config);
 768         } else {
 769                 vlv_dsi_pll_disable(encoder);
 770                 vlv_dsi_pll_enable(encoder, pipe_config);
 771         }
 772
 773         if (IS_BROXTON(dev_priv)) {
 774                 /* Add MIPI IO reset programming for modeset */
 775                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 776                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 777                                         val | MIPIO_RST_CTRL);
 778
 779                 /* Power up DSI regulator */
 780                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 781                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 782         }
 783
 784         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 785                 u32 val;
 786
 787                 /* Disable DPOunit clock gating, can stall pipe */
 788                 val = I915_READ(DSPCLK_GATE_D);
 789                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 790                 I915_WRITE(DSPCLK_GATE_D, val);
 791         }
 792
 793         if (!IS_GEMINILAKE(dev_priv))
 794                 intel_dsi_prepare(encoder, pipe_config);
 795
 796         /* Power on, try both CRC pmic gpio and VBT */
 797         if (intel_dsi->gpio_panel)
 798                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 799         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 800         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 801
 802         /* Deassert reset */
 803         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 804
 805         if (IS_GEMINILAKE(dev_priv)) {
 806                 glk_cold_boot = glk_dsi_enable_io(encoder);
 807
 808                 /* Prepare port in cold boot(s3/s4) scenario */
 809                 if (glk_cold_boot)
 810                         intel_dsi_prepare(encoder, pipe_config);
 811         }
 812
 813         /* Put device in ready state (LP-11) */
 814         intel_dsi_device_ready(encoder);
 815
 816         /* Prepare port in normal boot scenario */
 817         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 818                 intel_dsi_prepare(encoder, pipe_config);
 819
 820         /* Send initialization commands in LP mode */
 821         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 822
 823         /* Enable port in pre-enable phase itself because as per hw team
 824          * recommendation, port should be enabled befor plane & pipe */
 825         if (is_cmd_mode(intel_dsi)) {
 826                 for_each_dsi_port(port, intel_dsi->ports)
 827                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 828                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 829                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 830         } else {
 831                 msleep(20); /* XXX */
 832                 for_each_dsi_port(port, intel_dsi->ports)
 833                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 834                 intel_dsi_msleep(intel_dsi, 100);
 835
 836                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 837
 838                 intel_dsi_port_enable(encoder, pipe_config);
 839         }
 840
 841         intel_panel_enable_backlight(pipe_config, conn_state);
 842         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 843 }
 844
 845 /*
 846  * DSI port disable has to be done after pipe and plane disable, so we do it in
 847  * the post_disable hook.
 848  */
 849 static void intel_dsi_disable(struct intel_encoder *encoder,
 850                               const struct intel_crtc_state *old_crtc_state,
 851                               const struct drm_connector_state *old_conn_state)
 852 {
 853         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 854         enum port port;
 855
 856         DRM_DEBUG_KMS("\n");
 857
 858         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 859         intel_panel_disable_backlight(old_conn_state);
 860
 861         /*
 862          * According to the spec we should send SHUTDOWN before
 863          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 864          * has shown that the v3 sequence works for v2 VBTs too
 865          */
 866         if (is_vid_mode(intel_dsi)) {
 867                 /* Send Shutdown command to the panel in LP mode */
 868                 for_each_dsi_port(port, intel_dsi->ports)
 869                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 870                 msleep(10);
 871         }
 872 }
 873
 874 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 875 {
 876         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 877
 878         if (IS_GEMINILAKE(dev_priv))
 879                 glk_dsi_clear_device_ready(encoder);
 880         else
 881                 vlv_dsi_clear_device_ready(encoder);
 882 }
 883
 884 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 885                                    const struct intel_crtc_state *old_crtc_state,
 886                                    const struct drm_connector_state *old_conn_state)
 887 {
 888         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 889         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 890         enum port port;
 891         u32 val;
 892
 893         DRM_DEBUG_KMS("\n");
 894
 895         if (IS_GEN9_LP(dev_priv)) {
 896                 intel_crtc_vblank_off(old_crtc_state);
 897
 898                 skl_scaler_disable(old_crtc_state);
 899         }
 900
 901         if (is_vid_mode(intel_dsi)) {
 902                 for_each_dsi_port(port, intel_dsi->ports)
 903                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 904
 905                 intel_dsi_port_disable(encoder);
 906                 usleep_range(2000, 5000);
 907         }
 908
 909         intel_dsi_unprepare(encoder);
 910
 911         /*
 912          * if disable packets are sent before sending shutdown packet then in
 913          * some next enable sequence send turn on packet error is observed
 914          */
 915         if (is_cmd_mode(intel_dsi))
 916                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 917         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 918
 919         /* Transition to LP-00 */
 920         intel_dsi_clear_device_ready(encoder);
 921
 922         if (IS_BROXTON(dev_priv)) {
 923                 /* Power down DSI regulator to save power */
 924                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 925                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 926
 927                 /* Add MIPI IO reset programming for modeset */
 928                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 929                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 930                                 val & ~MIPIO_RST_CTRL);
 931         }
 932
 933         if (IS_GEN9_LP(dev_priv)) {
 934                 bxt_dsi_pll_disable(encoder);
 935         } else {
 936                 u32 val;
 937
 938                 vlv_dsi_pll_disable(encoder);
 939
 940                 val = I915_READ(DSPCLK_GATE_D);
 941                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 942                 I915_WRITE(DSPCLK_GATE_D, val);
 943         }
 944
 945         /* Assert reset */
 946         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 947
 948         /* Power off, try both CRC pmic gpio and VBT */
 949         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 950         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 951         if (intel_dsi->gpio_panel)
 952                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 953
 954         /*
 955          * FIXME As we do with eDP, just make a note of the time here
 956          * and perform the wait before the next panel power on.
 957          */
 958         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
 959 }
 960
 961 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 962                                    enum pipe *pipe)
 963 {
 964         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 965         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 966         intel_wakeref_t wakeref;
 967         enum port port;
 968         bool active = false;
 969
 970         DRM_DEBUG_KMS("\n");
 971
 972         wakeref = intel_display_power_get_if_enabled(dev_priv,
 973                                                      encoder->power_domain);
 974         if (!wakeref)
 975                 return false;
 976
 977         /*
 978          * On Broxton the PLL needs to be enabled with a valid divider
 979          * configuration, otherwise accessing DSI registers will hang the
 980          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 981          */
 982         if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
 983                 goto out_put_power;
 984
 985         /* XXX: this only works for one DSI output */
 986         for_each_dsi_port(port, intel_dsi->ports) {
 987                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
 988                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 989                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 990
 991                 /*
 992                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 993                  * bit in port C control register does not get set. As a
 994                  * workaround, check pipe B conf instead.
 995                  */
 996                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 997                     port == PORT_C)
 998                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
 999
1000                 /* Try command mode if video mode not enabled */
1001                 if (!enabled) {
1002                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1003                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1004                 }
1005
1006                 if (!enabled)
1007                         continue;
1008
1009                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1010                         continue;
1011
1012                 if (IS_GEN9_LP(dev_priv)) {
1013                         u32 tmp = I915_READ(MIPI_CTRL(port));
1014                         tmp &= BXT_PIPE_SELECT_MASK;
1015                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1016
1017                         if (WARN_ON(tmp > PIPE_C))
1018                                 continue;
1019
1020                         *pipe = tmp;
1021                 } else {
1022                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1023                 }
1024
1025                 active = true;
1026                 break;
1027         }
1028
1029 out_put_power:
1030         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1031
1032         return active;
1033 }
1034
1035 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1036                                     struct intel_crtc_state *pipe_config)
1037 {
1038         struct drm_device *dev = encoder->base.dev;
1039         struct drm_i915_private *dev_priv = to_i915(dev);
1040         struct drm_display_mode *adjusted_mode =
1041                                         &pipe_config->hw.adjusted_mode;
1042         struct drm_display_mode *adjusted_mode_sw;
1043         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1044         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1045         unsigned int lane_count = intel_dsi->lane_count;
1046         unsigned int bpp, fmt;
1047         enum port port;
1048         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1049         u16 hfp_sw, hsync_sw, hbp_sw;
1050         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1051                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1052
1053         /* FIXME: hw readout should not depend on SW state */
1054         adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1055
1056         /*
1057          * Atleast one port is active as encoder->get_config called only if
1058          * encoder->get_hw_state() returns true.
1059          */
1060         for_each_dsi_port(port, intel_dsi->ports) {
1061                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1062                         break;
1063         }
1064
1065         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1066         bpp = mipi_dsi_pixel_format_to_bpp(
1067                         pixel_format_from_register_bits(fmt));
1068
1069         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1070
1071         /* Enable Frame time stamo based scanline reporting */
1072         adjusted_mode->private_flags |=
1073                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1074
1075         /* In terms of pixels */
1076         adjusted_mode->crtc_hdisplay =
1077                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1078         adjusted_mode->crtc_vdisplay =
1079                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1080         adjusted_mode->crtc_vtotal =
1081                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1082
1083         hactive = adjusted_mode->crtc_hdisplay;
1084         hfp = I915_READ(MIPI_HFP_COUNT(port));
1085
1086         /*
1087          * Meaningful for video mode non-burst sync pulse mode only,
1088          * can be zero for non-burst sync events and burst modes
1089          */
1090         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1091         hbp = I915_READ(MIPI_HBP_COUNT(port));
1092
1093         /* harizontal values are in terms of high speed byte clock */
1094         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1095                                                 intel_dsi->burst_mode_ratio);
1096         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1097                                                 intel_dsi->burst_mode_ratio);
1098         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1099                                                 intel_dsi->burst_mode_ratio);
1100
1101         if (intel_dsi->dual_link) {
1102                 hfp *= 2;
1103                 hsync *= 2;
1104                 hbp *= 2;
1105         }
1106
1107         /* vertical values are in terms of lines */
1108         vfp = I915_READ(MIPI_VFP_COUNT(port));
1109         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1110         vbp = I915_READ(MIPI_VBP_COUNT(port));
1111
1112         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1113         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1114         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1115         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1116         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1117
1118         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1119         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1120         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1121         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1122
1123         /*
1124          * In BXT DSI there is no regs programmed with few horizontal timings
1125          * in Pixels but txbyteclkhs.. So retrieval process adds some
1126          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1127          * Actually here for the given adjusted_mode, we are calculating the
1128          * value programmed to the port and then back to the horizontal timing
1129          * param in pixels. This is the expected value, including roundup errors
1130          * And if that is same as retrieved value from port, then
1131          * (HW state) adjusted_mode's horizontal timings are corrected to
1132          * match with SW state to nullify the errors.
1133          */
1134         /* Calculating the value programmed to the Port register */
1135         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1136                                         adjusted_mode_sw->crtc_hdisplay;
1137         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1138                                         adjusted_mode_sw->crtc_hsync_start;
1139         hbp_sw = adjusted_mode_sw->crtc_htotal -
1140                                         adjusted_mode_sw->crtc_hsync_end;
1141
1142         if (intel_dsi->dual_link) {
1143                 hfp_sw /= 2;
1144                 hsync_sw /= 2;
1145                 hbp_sw /= 2;
1146         }
1147
1148         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1149                                                 intel_dsi->burst_mode_ratio);
1150         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1151                             intel_dsi->burst_mode_ratio);
1152         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1153                                                 intel_dsi->burst_mode_ratio);
1154
1155         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1156         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1157                                                 intel_dsi->burst_mode_ratio);
1158         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1159                                                 intel_dsi->burst_mode_ratio);
1160         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1161                                                 intel_dsi->burst_mode_ratio);
1162
1163         if (intel_dsi->dual_link) {
1164                 hfp_sw *= 2;
1165                 hsync_sw *= 2;
1166                 hbp_sw *= 2;
1167         }
1168
1169         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1170                                                         hsync_sw + hbp_sw;
1171         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1172         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1173         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1174         crtc_hblank_end_sw = crtc_htotal_sw;
1175
1176         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1177                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1178
1179         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1180                 adjusted_mode->crtc_hsync_start =
1181                                         adjusted_mode_sw->crtc_hsync_start;
1182
1183         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1184                 adjusted_mode->crtc_hsync_end =
1185                                         adjusted_mode_sw->crtc_hsync_end;
1186
1187         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1188                 adjusted_mode->crtc_hblank_start =
1189                                         adjusted_mode_sw->crtc_hblank_start;
1190
1191         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1192                 adjusted_mode->crtc_hblank_end =
1193                                         adjusted_mode_sw->crtc_hblank_end;
1194 }
1195
1196 static void intel_dsi_get_config(struct intel_encoder *encoder,
1197                                  struct intel_crtc_state *pipe_config)
1198 {
1199         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1200         u32 pclk;
1201         DRM_DEBUG_KMS("\n");
1202
1203         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1204
1205         if (IS_GEN9_LP(dev_priv)) {
1206                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1207                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1208         } else {
1209                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1210         }
1211
1212         if (pclk) {
1213                 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1214                 pipe_config->port_clock = pclk;
1215         }
1216 }
1217
1218 /* return txclkesc cycles in terms of divider and duration in us */
1219 static u16 txclkesc(u32 divider, unsigned int us)
1220 {
1221         switch (divider) {
1222         case ESCAPE_CLOCK_DIVIDER_1:
1223         default:
1224                 return 20 * us;
1225         case ESCAPE_CLOCK_DIVIDER_2:
1226                 return 10 * us;
1227         case ESCAPE_CLOCK_DIVIDER_4:
1228                 return 5 * us;
1229         }
1230 }
1231
1232 static void set_dsi_timings(struct drm_encoder *encoder,
1233                             const struct drm_display_mode *adjusted_mode)
1234 {
1235         struct drm_device *dev = encoder->dev;
1236         struct drm_i915_private *dev_priv = to_i915(dev);
1237         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1238         enum port port;
1239         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1240         unsigned int lane_count = intel_dsi->lane_count;
1241
1242         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1243
1244         hactive = adjusted_mode->crtc_hdisplay;
1245         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1246         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1247         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1248
1249         if (intel_dsi->dual_link) {
1250                 hactive /= 2;
1251                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1252                         hactive += intel_dsi->pixel_overlap;
1253                 hfp /= 2;
1254                 hsync /= 2;
1255                 hbp /= 2;
1256         }
1257
1258         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1259         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1260         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1261
1262         /* horizontal values are in terms of high speed byte clock */
1263         hactive = txbyteclkhs(hactive, bpp, lane_count,
1264                               intel_dsi->burst_mode_ratio);
1265         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1266         hsync = txbyteclkhs(hsync, bpp, lane_count,
1267                             intel_dsi->burst_mode_ratio);
1268         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1269
1270         for_each_dsi_port(port, intel_dsi->ports) {
1271                 if (IS_GEN9_LP(dev_priv)) {
1272                         /*
1273                          * Program hdisplay and vdisplay on MIPI transcoder.
1274                          * This is different from calculated hactive and
1275                          * vactive, as they are calculated per channel basis,
1276                          * whereas these values should be based on resolution.
1277                          */
1278                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1279                                    adjusted_mode->crtc_hdisplay);
1280                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1281                                    adjusted_mode->crtc_vdisplay);
1282                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1283                                    adjusted_mode->crtc_vtotal);
1284                 }
1285
1286                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1287                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1288
1289                 /* meaningful for video mode non-burst sync pulse mode only,
1290                  * can be zero for non-burst sync events and burst modes */
1291                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1292                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1293
1294                 /* vertical values are in terms of lines */
1295                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1296                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1297                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1298         }
1299 }
1300
1301 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1302 {
1303         switch (fmt) {
1304         case MIPI_DSI_FMT_RGB888:
1305                 return VID_MODE_FORMAT_RGB888;
1306         case MIPI_DSI_FMT_RGB666:
1307                 return VID_MODE_FORMAT_RGB666;
1308         case MIPI_DSI_FMT_RGB666_PACKED:
1309                 return VID_MODE_FORMAT_RGB666_PACKED;
1310         case MIPI_DSI_FMT_RGB565:
1311                 return VID_MODE_FORMAT_RGB565;
1312         default:
1313                 MISSING_CASE(fmt);
1314                 return VID_MODE_FORMAT_RGB666;
1315         }
1316 }
1317
1318 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1319                               const struct intel_crtc_state *pipe_config)
1320 {
1321         struct drm_encoder *encoder = &intel_encoder->base;
1322         struct drm_device *dev = encoder->dev;
1323         struct drm_i915_private *dev_priv = to_i915(dev);
1324         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
1325         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1326         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1327         enum port port;
1328         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1329         u32 val, tmp;
1330         u16 mode_hdisplay;
1331
1332         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1333
1334         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1335
1336         if (intel_dsi->dual_link) {
1337                 mode_hdisplay /= 2;
1338                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1339                         mode_hdisplay += intel_dsi->pixel_overlap;
1340         }
1341
1342         for_each_dsi_port(port, intel_dsi->ports) {
1343                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1344                         /*
1345                          * escape clock divider, 20MHz, shared for A and C.
1346                          * device ready must be off when doing this! txclkesc?
1347                          */
1348                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1349                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1350                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1351                                         ESCAPE_CLOCK_DIVIDER_1);
1352
1353                         /* read request priority is per pipe */
1354                         tmp = I915_READ(MIPI_CTRL(port));
1355                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1356                         I915_WRITE(MIPI_CTRL(port), tmp |
1357                                         READ_REQUEST_PRIORITY_HIGH);
1358                 } else if (IS_GEN9_LP(dev_priv)) {
1359                         enum pipe pipe = intel_crtc->pipe;
1360
1361                         tmp = I915_READ(MIPI_CTRL(port));
1362                         tmp &= ~BXT_PIPE_SELECT_MASK;
1363
1364                         tmp |= BXT_PIPE_SELECT(pipe);
1365                         I915_WRITE(MIPI_CTRL(port), tmp);
1366                 }
1367
1368                 /* XXX: why here, why like this? handling in irq handler?! */
1369                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1370                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1371
1372                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1373
1374                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1375                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1376                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1377         }
1378
1379         set_dsi_timings(encoder, adjusted_mode);
1380
1381         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1382         if (is_cmd_mode(intel_dsi)) {
1383                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1384                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1385         } else {
1386                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1387                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1388         }
1389
1390         tmp = 0;
1391         if (intel_dsi->eotp_pkt == 0)
1392                 tmp |= EOT_DISABLE;
1393         if (intel_dsi->clock_stop)
1394                 tmp |= CLOCKSTOP;
1395
1396         if (IS_GEN9_LP(dev_priv)) {
1397                 tmp |= BXT_DPHY_DEFEATURE_EN;
1398                 if (!is_cmd_mode(intel_dsi))
1399                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1400         }
1401
1402         for_each_dsi_port(port, intel_dsi->ports) {
1403                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1404
1405                 /* timeouts for recovery. one frame IIUC. if counter expires,
1406                  * EOT and stop state. */
1407
1408                 /*
1409                  * In burst mode, value greater than one DPI line Time in byte
1410                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1411                  * said value is recommended.
1412                  *
1413                  * In non-burst mode, Value greater than one DPI frame time in
1414                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1415                  * said value is recommended.
1416                  *
1417                  * In DBI only mode, value greater than one DBI frame time in
1418                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1419                  * said value is recommended.
1420                  */
1421
1422                 if (is_vid_mode(intel_dsi) &&
1423                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1424                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1425                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1426                                             intel_dsi->lane_count,
1427                                             intel_dsi->burst_mode_ratio) + 1);
1428                 } else {
1429                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1430                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1431                                             adjusted_mode->crtc_htotal,
1432                                             bpp, intel_dsi->lane_count,
1433                                             intel_dsi->burst_mode_ratio) + 1);
1434                 }
1435                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1436                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1437                                                 intel_dsi->turn_arnd_val);
1438                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1439                                                 intel_dsi->rst_timer_val);
1440
1441                 /* dphy stuff */
1442
1443                 /* in terms of low power clock */
1444                 I915_WRITE(MIPI_INIT_COUNT(port),
1445                                 txclkesc(intel_dsi->escape_clk_div, 100));
1446
1447                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1448                         /*
1449                          * BXT spec says write MIPI_INIT_COUNT for
1450                          * both the ports, even if only one is
1451                          * getting used. So write the other port
1452                          * if not in dual link mode.
1453                          */
1454                         I915_WRITE(MIPI_INIT_COUNT(port ==
1455                                                 PORT_A ? PORT_C : PORT_A),
1456                                         intel_dsi->init_count);
1457                 }
1458
1459                 /* recovery disables */
1460                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1461
1462                 /* in terms of low power clock */
1463                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1464
1465                 /* in terms of txbyteclkhs. actual high to low switch +
1466                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1467                  *
1468                  * XXX: write MIPI_STOP_STATE_STALL?
1469                  */
1470                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1471                                                 intel_dsi->hs_to_lp_count);
1472
1473                 /* XXX: low power clock equivalence in terms of byte clock.
1474                  * the number of byte clocks occupied in one low power clock.
1475                  * based on txbyteclkhs and txclkesc.
1476                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1477                  * ) / 105.???
1478                  */
1479                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1480
1481                 if (IS_GEMINILAKE(dev_priv)) {
1482                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1483                                         intel_dsi->lp_byte_clk);
1484                         /* Shadow of DPHY reg */
1485                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1486                                         intel_dsi->dphy_reg);
1487                 }
1488
1489                 /* the bw essential for transmitting 16 long packets containing
1490                  * 252 bytes meant for dcs write memory command is programmed in
1491                  * this register in terms of byte clocks. based on dsi transfer
1492                  * rate and the number of lanes configured the time taken to
1493                  * transmit 16 long packets in a dsi stream varies. */
1494                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1495
1496                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1497                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1498                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1499
1500                 if (is_vid_mode(intel_dsi))
1501                         /* Some panels might have resolution which is not a
1502                          * multiple of 64 like 1366 x 768. Enable RANDOM
1503                          * resolution support for such panels by default */
1504                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1505                                 intel_dsi->video_frmt_cfg_bits |
1506                                 intel_dsi->video_mode_format |
1507                                 IP_TG_CONFIG |
1508                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1509         }
1510 }
1511
1512 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1515         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1516         enum port port;
1517         u32 val;
1518
1519         if (IS_GEMINILAKE(dev_priv))
1520                 return;
1521
1522         for_each_dsi_port(port, intel_dsi->ports) {
1523                 /* Panel commands can be sent when clock is in LP11 */
1524                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1525
1526                 if (IS_GEN9_LP(dev_priv))
1527                         bxt_dsi_reset_clocks(encoder, port);
1528                 else
1529                         vlv_dsi_reset_clocks(encoder, port);
1530                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1531
1532                 val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1533                 val &= ~VID_MODE_FORMAT_MASK;
1534                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1535
1536                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1537         }
1538 }
1539
1540 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1541 {
1542         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1543
1544         /* dispose of the gpios */
1545         if (intel_dsi->gpio_panel)
1546                 gpiod_put(intel_dsi->gpio_panel);
1547
1548         intel_encoder_destroy(encoder);
1549 }
1550
1551 static const struct drm_encoder_funcs intel_dsi_funcs = {
1552         .destroy = intel_dsi_encoder_destroy,
1553 };
1554
1555 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1556         .get_modes = intel_dsi_get_modes,
1557         .mode_valid = intel_dsi_mode_valid,
1558         .atomic_check = intel_digital_connector_atomic_check,
1559 };
1560
1561 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1562         .late_register = intel_connector_register,
1563         .early_unregister = intel_connector_unregister,
1564         .destroy = intel_connector_destroy,
1565         .fill_modes = drm_helper_probe_single_connector_modes,
1566         .atomic_get_property = intel_digital_connector_atomic_get_property,
1567         .atomic_set_property = intel_digital_connector_atomic_set_property,
1568         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1569         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1570 };
1571
1572 static enum drm_panel_orientation
1573 vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector)
1574 {
1575         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1576         struct intel_encoder *encoder = connector->encoder;
1577         enum intel_display_power_domain power_domain;
1578         enum drm_panel_orientation orientation;
1579         struct intel_plane *plane;
1580         struct intel_crtc *crtc;
1581         intel_wakeref_t wakeref;
1582         enum pipe pipe;
1583         u32 val;
1584
1585         if (!encoder->get_hw_state(encoder, &pipe))
1586                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1587
1588         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1589         plane = to_intel_plane(crtc->base.primary);
1590
1591         power_domain = POWER_DOMAIN_PIPE(pipe);
1592         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1593         if (!wakeref)
1594                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1595
1596         val = I915_READ(DSPCNTR(plane->i9xx_plane));
1597
1598         if (!(val & DISPLAY_PLANE_ENABLE))
1599                 orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1600         else if (val & DISPPLANE_ROTATE_180)
1601                 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1602         else
1603                 orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
1604
1605         intel_display_power_put(dev_priv, power_domain, wakeref);
1606
1607         return orientation;
1608 }
1609
1610 static enum drm_panel_orientation
1611 vlv_dsi_get_panel_orientation(struct intel_connector *connector)
1612 {
1613         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1614         enum drm_panel_orientation orientation;
1615
1616         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1617                 orientation = vlv_dsi_get_hw_panel_orientation(connector);
1618                 if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
1619                         return orientation;
1620         }
1621
1622         return intel_dsi_get_panel_orientation(connector);
1623 }
1624
1625 static void vlv_dsi_add_properties(struct intel_connector *connector)
1626 {
1627         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1628
1629         if (connector->panel.fixed_mode) {
1630                 u32 allowed_scalers;
1631
1632                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1633                 if (!HAS_GMCH(dev_priv))
1634                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1635
1636                 drm_connector_attach_scaling_mode_property(&connector->base,
1637                                                                 allowed_scalers);
1638
1639                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1640
1641                 connector->base.display_info.panel_orientation =
1642                         vlv_dsi_get_panel_orientation(connector);
1643                 drm_connector_init_panel_orientation_property(
1644                                 &connector->base,
1645                                 connector->panel.fixed_mode->hdisplay,
1646                                 connector->panel.fixed_mode->vdisplay);
1647         }
1648 }
1649
1650 #define NS_KHZ_RATIO            1000000
1651
1652 #define PREPARE_CNT_MAX         0x3F
1653 #define EXIT_ZERO_CNT_MAX       0x3F
1654 #define CLK_ZERO_CNT_MAX        0xFF
1655 #define TRAIL_CNT_MAX           0x1F
1656
1657 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1658 {
1659         struct drm_device *dev = intel_dsi->base.base.dev;
1660         struct drm_i915_private *dev_priv = to_i915(dev);
1661         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1662         u32 tlpx_ns, extra_byte_count, tlpx_ui;
1663         u32 ui_num, ui_den;
1664         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1665         u32 ths_prepare_ns, tclk_trail_ns;
1666         u32 tclk_prepare_clkzero, ths_prepare_hszero;
1667         u32 lp_to_hs_switch, hs_to_lp_switch;
1668         u32 mul;
1669
1670         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1671
1672         switch (intel_dsi->lane_count) {
1673         case 1:
1674         case 2:
1675                 extra_byte_count = 2;
1676                 break;
1677         case 3:
1678                 extra_byte_count = 4;
1679                 break;
1680         case 4:
1681         default:
1682                 extra_byte_count = 3;
1683                 break;
1684         }
1685
1686         /* in Kbps */
1687         ui_num = NS_KHZ_RATIO;
1688         ui_den = intel_dsi_bitrate(intel_dsi);
1689
1690         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1691         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1692
1693         /*
1694          * B060
1695          * LP byte clock = TLPX/ (8UI)
1696          */
1697         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1698
1699         /* DDR clock period = 2 * UI
1700          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1701          * UI(nsec) = 10^6 / bitrate
1702          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1703          * DDR clock count  = ns_value / DDR clock period
1704          *
1705          * For GEMINILAKE dphy_param_reg will be programmed in terms of
1706          * HS byte clock count for other platform in HS ddr clock count
1707          */
1708         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1709         ths_prepare_ns = max(mipi_config->ths_prepare,
1710                              mipi_config->tclk_prepare);
1711
1712         /* prepare count */
1713         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1714
1715         if (prepare_cnt > PREPARE_CNT_MAX) {
1716                 DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
1717                 prepare_cnt = PREPARE_CNT_MAX;
1718         }
1719
1720         /* exit zero count */
1721         exit_zero_cnt = DIV_ROUND_UP(
1722                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1723                                 ui_num * mul
1724                                 );
1725
1726         /*
1727          * Exit zero is unified val ths_zero and ths_exit
1728          * minimum value for ths_exit = 110ns
1729          * min (exit_zero_cnt * 2) = 110/UI
1730          * exit_zero_cnt = 55/UI
1731          */
1732         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1733                 exit_zero_cnt += 1;
1734
1735         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1736                 DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
1737                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1738         }
1739
1740         /* clk zero count */
1741         clk_zero_cnt = DIV_ROUND_UP(
1742                                 (tclk_prepare_clkzero - ths_prepare_ns)
1743                                 * ui_den, ui_num * mul);
1744
1745         if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1746                 DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
1747                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1748         }
1749
1750         /* trail count */
1751         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1752         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1753
1754         if (trail_cnt > TRAIL_CNT_MAX) {
1755                 DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
1756                 trail_cnt = TRAIL_CNT_MAX;
1757         }
1758
1759         /* B080 */
1760         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1761                                                 clk_zero_cnt << 8 | prepare_cnt;
1762
1763         /*
1764          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1765          *                                      mul + 10UI + Extra Byte Count
1766          *
1767          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1768          * Extra Byte Count is calculated according to number of lanes.
1769          * High Low Switch Count is the Max of LP to HS and
1770          * HS to LP switch count
1771          *
1772          */
1773         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1774
1775         /* B044 */
1776         /* FIXME:
1777          * The comment above does not match with the code */
1778         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1779                                                 exit_zero_cnt * mul + 10, 8);
1780
1781         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1782
1783         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1784         intel_dsi->hs_to_lp_count += extra_byte_count;
1785
1786         /* B088 */
1787         /* LP -> HS for clock lanes
1788          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1789          *                                              extra byte count
1790          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1791          *                                      2(in UI) + extra byte count
1792          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1793          *                                      8 + extra byte count
1794          */
1795         intel_dsi->clk_lp_to_hs_count =
1796                 DIV_ROUND_UP(
1797                         4 * tlpx_ui + prepare_cnt * 2 +
1798                         clk_zero_cnt * 2,
1799                         8);
1800
1801         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1802
1803         /* HS->LP for Clock Lanes
1804          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1805          *                                              Extra byte count
1806          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1807          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1808          *                                              Extra byte count
1809          */
1810         intel_dsi->clk_hs_to_lp_count =
1811                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1812                         8);
1813         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1814
1815         intel_dsi_log_params(intel_dsi);
1816 }
1817
1818 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1819 {
1820         struct drm_device *dev = &dev_priv->drm;
1821         struct intel_dsi *intel_dsi;
1822         struct intel_encoder *intel_encoder;
1823         struct drm_encoder *encoder;
1824         struct intel_connector *intel_connector;
1825         struct drm_connector *connector;
1826         struct drm_display_mode *current_mode, *fixed_mode;
1827         enum port port;
1828
1829         DRM_DEBUG_KMS("\n");
1830
1831         /* There is no detection method for MIPI so rely on VBT */
1832         if (!intel_bios_is_dsi_present(dev_priv, &port))
1833                 return;
1834
1835         if (IS_GEN9_LP(dev_priv))
1836                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1837         else
1838                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1839
1840         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1841         if (!intel_dsi)
1842                 return;
1843
1844         intel_connector = intel_connector_alloc();
1845         if (!intel_connector) {
1846                 kfree(intel_dsi);
1847                 return;
1848         }
1849
1850         intel_encoder = &intel_dsi->base;
1851         encoder = &intel_encoder->base;
1852         intel_dsi->attached_connector = intel_connector;
1853
1854         connector = &intel_connector->base;
1855
1856         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1857                          "DSI %c", port_name(port));
1858
1859         intel_encoder->compute_config = intel_dsi_compute_config;
1860         intel_encoder->pre_enable = intel_dsi_pre_enable;
1861         intel_encoder->disable = intel_dsi_disable;
1862         intel_encoder->post_disable = intel_dsi_post_disable;
1863         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1864         intel_encoder->get_config = intel_dsi_get_config;
1865         intel_encoder->update_pipe = intel_panel_update_backlight;
1866
1867         intel_connector->get_hw_state = intel_connector_get_hw_state;
1868
1869         intel_encoder->port = port;
1870         intel_encoder->type = INTEL_OUTPUT_DSI;
1871         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1872         intel_encoder->cloneable = 0;
1873
1874         /*
1875          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1876          * port C. BXT isn't limited like this.
1877          */
1878         if (IS_GEN9_LP(dev_priv))
1879                 intel_encoder->pipe_mask = ~0;
1880         else if (port == PORT_A)
1881                 intel_encoder->pipe_mask = BIT(PIPE_A);
1882         else
1883                 intel_encoder->pipe_mask = BIT(PIPE_B);
1884
1885         if (dev_priv->vbt.dsi.config->dual_link)
1886                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1887         else
1888                 intel_dsi->ports = BIT(port);
1889
1890         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1891         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1892
1893         /* Create a DSI host (and a device) for each port. */
1894         for_each_dsi_port(port, intel_dsi->ports) {
1895                 struct intel_dsi_host *host;
1896
1897                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1898                                            port);
1899                 if (!host)
1900                         goto err;
1901
1902                 intel_dsi->dsi_hosts[port] = host;
1903         }
1904
1905         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1906                 DRM_DEBUG_KMS("no device found\n");
1907                 goto err;
1908         }
1909
1910         /* Use clock read-back from current hw-state for fastboot */
1911         current_mode = intel_encoder_current_mode(intel_encoder);
1912         if (current_mode) {
1913                 DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n",
1914                               intel_dsi->pclk, current_mode->clock);
1915                 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1916                                             current_mode->clock)) {
1917                         DRM_DEBUG_KMS("Using GOP pclk\n");
1918                         intel_dsi->pclk = current_mode->clock;
1919                 }
1920
1921                 kfree(current_mode);
1922         }
1923
1924         vlv_dphy_param_init(intel_dsi);
1925
1926         /*
1927          * In case of BYT with CRC PMIC, we need to use GPIO for
1928          * Panel control.
1929          */
1930         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1931             (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1932                 intel_dsi->gpio_panel =
1933                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1934
1935                 if (IS_ERR(intel_dsi->gpio_panel)) {
1936                         DRM_ERROR("Failed to own gpio for panel control\n");
1937                         intel_dsi->gpio_panel = NULL;
1938                 }
1939         }
1940
1941         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1942                            DRM_MODE_CONNECTOR_DSI);
1943
1944         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1945
1946         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1947         connector->interlace_allowed = false;
1948         connector->doublescan_allowed = false;
1949
1950         intel_connector_attach_encoder(intel_connector, intel_encoder);
1951
1952         mutex_lock(&dev->mode_config.mutex);
1953         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1954         mutex_unlock(&dev->mode_config.mutex);
1955
1956         if (!fixed_mode) {
1957                 DRM_DEBUG_KMS("no fixed mode\n");
1958                 goto err_cleanup_connector;
1959         }
1960
1961         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1962         intel_panel_setup_backlight(connector, INVALID_PIPE);
1963
1964         vlv_dsi_add_properties(intel_connector);
1965
1966         return;
1967
1968 err_cleanup_connector:
1969         drm_connector_cleanup(&intel_connector->base);
1970 err:
1971         drm_encoder_cleanup(&intel_encoder->base);
1972         kfree(intel_dsi);
1973         kfree(intel_connector);
1974 }