2 * SPDX-License-Identifier: MIT
4 * Copyright © 2016 Intel Corporation
7 #include "display/intel_frontbuffer.h"
10 #include "i915_gem_clflush.h"
11 #include "i915_sw_fence_work.h"
12 #include "i915_trace.h"
15 struct dma_fence_work base;
16 struct drm_i915_gem_object *obj;
19 static void __do_clflush(struct drm_i915_gem_object *obj)
21 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
22 drm_clflush_sg(obj->mm.pages);
23 intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_CPU);
26 static int clflush_work(struct dma_fence_work *base)
28 struct clflush *clflush = container_of(base, typeof(*clflush), base);
29 struct drm_i915_gem_object *obj = fetch_and_zero(&clflush->obj);
32 err = i915_gem_object_pin_pages(obj);
37 i915_gem_object_unpin_pages(obj);
40 i915_gem_object_put(obj);
44 static void clflush_release(struct dma_fence_work *base)
46 struct clflush *clflush = container_of(base, typeof(*clflush), base);
49 i915_gem_object_put(clflush->obj);
52 static const struct dma_fence_work_ops clflush_ops = {
55 .release = clflush_release,
58 static struct clflush *clflush_work_create(struct drm_i915_gem_object *obj)
60 struct clflush *clflush;
62 GEM_BUG_ON(!obj->cache_dirty);
64 clflush = kmalloc(sizeof(*clflush), GFP_KERNEL);
68 dma_fence_work_init(&clflush->base, &clflush_ops);
69 clflush->obj = i915_gem_object_get(obj); /* obj <-> clflush cycle */
74 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
77 struct clflush *clflush;
79 assert_object_held(obj);
82 * Stolen memory is always coherent with the GPU as it is explicitly
83 * marked as wc by the system, or the system is cache-coherent.
84 * Similarly, we only access struct pages through the CPU cache, so
85 * anything not backed by physical memory we consider to be always
86 * coherent and not need clflushing.
88 if (!i915_gem_object_has_struct_page(obj)) {
89 obj->cache_dirty = false;
93 /* If the GPU is snooping the contents of the CPU cache,
94 * we do not need to manually clear the CPU cache lines. However,
95 * the caches are only snooped when the render cache is
96 * flushed/invalidated. As we always have to emit invalidations
97 * and flushes when moving into and out of the RENDER domain, correct
98 * snooping behaviour occurs naturally as the result of our domain
101 if (!(flags & I915_CLFLUSH_FORCE) &&
102 obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
105 trace_i915_gem_object_clflush(obj);
108 if (!(flags & I915_CLFLUSH_SYNC))
109 clflush = clflush_work_create(obj);
111 i915_sw_fence_await_reservation(&clflush->base.chain,
112 obj->base.resv, NULL, true,
115 dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma);
116 dma_fence_work_commit(&clflush->base);
117 } else if (obj->mm.pages) {
120 GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
123 obj->cache_dirty = false;