2 * SPDX-License-Identifier: MIT
4 * Copyright © 2011-2012 Intel Corporation
8 * This file implements HW context support. On gen5+ a HW context consists of an
9 * opaque GPU object which is referenced at times of context saves and restores.
10 * With RC6 enabled, the context is also referenced as the GPU enters and exists
11 * from RC6 (GPU has it's own internal power context, except on gen5). Though
12 * something like a context does exist for the media ring, the code only
13 * supports contexts for the render ring.
15 * In software, there is a distinction between contexts created by the user,
16 * and the default HW context. The default HW context is used by GPU clients
17 * that do not request setup of their own hardware context. The default
18 * context's state is never restored to help prevent programming errors. This
19 * would happen if a client ran and piggy-backed off another clients GPU state.
20 * The default context only exists to give the GPU some offset to load as the
21 * current to invoke a save of the context we actually care about. In fact, the
22 * code could likely be constructed, albeit in a more complicated fashion, to
23 * never use the default context, though that limits the driver's ability to
24 * swap out, and/or destroy other contexts.
26 * All other contexts are created as a request by the GPU client. These contexts
27 * store GPU state, and thus allow GPU clients to not re-emit state (and
28 * potentially query certain state) at any time. The kernel driver makes
29 * certain that the appropriate commands are inserted.
31 * The context life cycle is semi-complicated in that context BOs may live
32 * longer than the context itself because of the way the hardware, and object
33 * tracking works. Below is a very crude representation of the state machine
34 * describing the context life.
35 * refcount pincount active
36 * S0: initial state 0 0 0
37 * S1: context created 1 0 0
38 * S2: context is currently running 2 1 X
39 * S3: GPU referenced, but not current 2 0 1
40 * S4: context is current, but destroyed 1 1 0
41 * S5: like S3, but destroyed 1 0 1
43 * The most common (but not all) transitions:
44 * S0->S1: client creates a context
45 * S1->S2: client submits execbuf with context
46 * S2->S3: other clients submits execbuf with context
47 * S3->S1: context object was retired
48 * S3->S2: clients submits another execbuf
49 * S2->S4: context destroy called with current context
50 * S3->S5->S0: destroy path
51 * S4->S5->S0: destroy path on current context
53 * There are two confusing terms used above:
54 * The "current context" means the context which is currently running on the
55 * GPU. The GPU has loaded its state already and has stored away the gtt
56 * offset of the BO. The GPU is not actively referencing the data at this
57 * offset, but it will on the next context switch. The only way to avoid this
58 * is to do a GPU reset.
60 * An "active context' is one which was previously the "current context" and is
61 * on the active list waiting for the next context switch to occur. Until this
62 * happens, the object must remain at the same gtt offset. It is therefore
63 * possible to destroy a context, but it is still active.
67 #include <linux/log2.h>
68 #include <linux/nospec.h>
70 #include <drm/i915_drm.h>
72 #include "gt/intel_lrc_reg.h"
74 #include "i915_gem_context.h"
75 #include "i915_globals.h"
76 #include "i915_trace.h"
77 #include "i915_user_extensions.h"
79 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
81 static struct i915_global_gem_context {
82 struct i915_global base;
83 struct kmem_cache *slab_luts;
86 struct i915_lut_handle *i915_lut_handle_alloc(void)
88 return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
91 void i915_lut_handle_free(struct i915_lut_handle *lut)
93 return kmem_cache_free(global.slab_luts, lut);
96 static void lut_close(struct i915_gem_context *ctx)
98 struct radix_tree_iter iter;
101 lockdep_assert_held(&ctx->mutex);
104 radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
105 struct i915_vma *vma = rcu_dereference_raw(*slot);
106 struct drm_i915_gem_object *obj = vma->obj;
107 struct i915_lut_handle *lut;
109 if (!kref_get_unless_zero(&obj->base.refcount))
113 i915_gem_object_lock(obj);
114 list_for_each_entry(lut, &obj->lut_list, obj_link) {
118 if (lut->handle != iter.index)
121 list_del(&lut->obj_link);
124 i915_gem_object_unlock(obj);
127 if (&lut->obj_link != &obj->lut_list) {
128 i915_lut_handle_free(lut);
129 radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
130 if (atomic_dec_and_test(&vma->open_count) &&
131 !i915_vma_is_ggtt(vma))
133 i915_gem_object_put(obj);
136 i915_gem_object_put(obj);
141 static struct intel_context *
142 lookup_user_engine(struct i915_gem_context *ctx,
144 const struct i915_engine_class_instance *ci)
145 #define LOOKUP_USER_INDEX BIT(0)
149 if (!!(flags & LOOKUP_USER_INDEX) != i915_gem_context_user_engines(ctx))
150 return ERR_PTR(-EINVAL);
152 if (!i915_gem_context_user_engines(ctx)) {
153 struct intel_engine_cs *engine;
155 engine = intel_engine_lookup_user(ctx->i915,
157 ci->engine_instance);
159 return ERR_PTR(-EINVAL);
163 idx = ci->engine_instance;
166 return i915_gem_context_get_engine(ctx, idx);
169 static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
173 lockdep_assert_held(&i915->contexts.mutex);
175 if (INTEL_GEN(i915) >= 11)
176 max = GEN11_MAX_CONTEXT_HW_ID;
177 else if (USES_GUC_SUBMISSION(i915))
179 * When using GuC in proxy submission, GuC consumes the
180 * highest bit in the context id to indicate proxy submission.
182 max = MAX_GUC_CONTEXT_HW_ID;
184 max = MAX_CONTEXT_HW_ID;
186 return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp);
189 static int steal_hw_id(struct drm_i915_private *i915)
191 struct i915_gem_context *ctx, *cn;
195 lockdep_assert_held(&i915->contexts.mutex);
197 list_for_each_entry_safe(ctx, cn,
198 &i915->contexts.hw_id_list, hw_id_link) {
199 if (atomic_read(&ctx->hw_id_pin_count)) {
200 list_move_tail(&ctx->hw_id_link, &pinned);
204 GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */
205 list_del_init(&ctx->hw_id_link);
211 * Remember how far we got up on the last repossesion scan, so the
212 * list is kept in a "least recently scanned" order.
214 list_splice_tail(&pinned, &i915->contexts.hw_id_list);
218 static int assign_hw_id(struct drm_i915_private *i915, unsigned int *out)
222 lockdep_assert_held(&i915->contexts.mutex);
225 * We prefer to steal/stall ourselves and our users over that of the
226 * entire system. That may be a little unfair to our users, and
227 * even hurt high priority clients. The choice is whether to oomkill
228 * something else, or steal a context id.
230 ret = new_hw_id(i915, GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
231 if (unlikely(ret < 0)) {
232 ret = steal_hw_id(i915);
233 if (ret < 0) /* once again for the correct errno code */
234 ret = new_hw_id(i915, GFP_KERNEL);
243 static void release_hw_id(struct i915_gem_context *ctx)
245 struct drm_i915_private *i915 = ctx->i915;
247 if (list_empty(&ctx->hw_id_link))
250 mutex_lock(&i915->contexts.mutex);
251 if (!list_empty(&ctx->hw_id_link)) {
252 ida_simple_remove(&i915->contexts.hw_ida, ctx->hw_id);
253 list_del_init(&ctx->hw_id_link);
255 mutex_unlock(&i915->contexts.mutex);
258 static void __free_engines(struct i915_gem_engines *e, unsigned int count)
261 if (!e->engines[count])
264 intel_context_put(e->engines[count]);
269 static void free_engines(struct i915_gem_engines *e)
271 __free_engines(e, e->num_engines);
274 static void free_engines_rcu(struct rcu_head *rcu)
276 free_engines(container_of(rcu, struct i915_gem_engines, rcu));
279 static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
281 struct intel_engine_cs *engine;
282 struct i915_gem_engines *e;
283 enum intel_engine_id id;
285 e = kzalloc(struct_size(e, engines, I915_NUM_ENGINES), GFP_KERNEL);
287 return ERR_PTR(-ENOMEM);
289 init_rcu_head(&e->rcu);
290 for_each_engine(engine, ctx->i915, id) {
291 struct intel_context *ce;
293 ce = intel_context_create(ctx, engine);
295 __free_engines(e, id);
306 static void i915_gem_context_free(struct i915_gem_context *ctx)
308 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
309 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
313 i915_vm_put(ctx->vm);
315 free_engines(rcu_access_pointer(ctx->engines));
316 mutex_destroy(&ctx->engines_mutex);
319 intel_timeline_put(ctx->timeline);
324 list_del(&ctx->link);
325 mutex_destroy(&ctx->mutex);
330 static void contexts_free(struct drm_i915_private *i915)
332 struct llist_node *freed = llist_del_all(&i915->contexts.free_list);
333 struct i915_gem_context *ctx, *cn;
335 lockdep_assert_held(&i915->drm.struct_mutex);
337 llist_for_each_entry_safe(ctx, cn, freed, free_link)
338 i915_gem_context_free(ctx);
341 static void contexts_free_first(struct drm_i915_private *i915)
343 struct i915_gem_context *ctx;
344 struct llist_node *freed;
346 lockdep_assert_held(&i915->drm.struct_mutex);
348 freed = llist_del_first(&i915->contexts.free_list);
352 ctx = container_of(freed, typeof(*ctx), free_link);
353 i915_gem_context_free(ctx);
356 static void contexts_free_worker(struct work_struct *work)
358 struct drm_i915_private *i915 =
359 container_of(work, typeof(*i915), contexts.free_work);
361 mutex_lock(&i915->drm.struct_mutex);
363 mutex_unlock(&i915->drm.struct_mutex);
366 void i915_gem_context_release(struct kref *ref)
368 struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
369 struct drm_i915_private *i915 = ctx->i915;
371 trace_i915_context_free(ctx);
372 if (llist_add(&ctx->free_link, &i915->contexts.free_list))
373 queue_work(i915->wq, &i915->contexts.free_work);
376 static void context_close(struct i915_gem_context *ctx)
378 mutex_lock(&ctx->mutex);
380 i915_gem_context_set_closed(ctx);
381 ctx->file_priv = ERR_PTR(-EBADF);
384 * This context will never again be assinged to HW, so we can
385 * reuse its ID for the next context.
390 * The LUT uses the VMA as a backpointer to unref the object,
391 * so we need to clear the LUT before we close all the VMA (inside
396 mutex_unlock(&ctx->mutex);
397 i915_gem_context_put(ctx);
400 static u32 default_desc_template(const struct drm_i915_private *i915,
401 const struct i915_address_space *vm)
406 desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
408 address_mode = INTEL_LEGACY_32B_CONTEXT;
409 if (vm && i915_vm_is_4lvl(vm))
410 address_mode = INTEL_LEGACY_64B_CONTEXT;
411 desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
414 desc |= GEN8_CTX_L3LLC_COHERENT;
416 /* TODO: WaDisableLiteRestore when we start using semaphore
417 * signalling between Command Streamers
418 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
424 static struct i915_gem_context *
425 __create_context(struct drm_i915_private *i915)
427 struct i915_gem_context *ctx;
428 struct i915_gem_engines *e;
432 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
434 return ERR_PTR(-ENOMEM);
436 kref_init(&ctx->ref);
437 list_add_tail(&ctx->link, &i915->contexts.list);
439 ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
440 mutex_init(&ctx->mutex);
442 mutex_init(&ctx->engines_mutex);
443 e = default_engines(ctx);
448 RCU_INIT_POINTER(ctx->engines, e);
450 INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
451 INIT_LIST_HEAD(&ctx->hw_id_link);
453 /* NB: Mark all slices as needing a remap so that when the context first
454 * loads it will restore whatever remap state already exists. If there
455 * is no remap info, it will be a NOP. */
456 ctx->remap_slice = ALL_L3_SLICES(i915);
458 i915_gem_context_set_bannable(ctx);
459 i915_gem_context_set_recoverable(ctx);
461 ctx->ring_size = 4 * PAGE_SIZE;
462 ctx->desc_template = default_desc_template(i915, NULL);
464 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
465 ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
474 static struct i915_address_space *
475 __set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
477 struct i915_address_space *old = ctx->vm;
478 struct i915_gem_engines_iter it;
479 struct intel_context *ce;
481 ctx->vm = i915_vm_get(vm);
482 ctx->desc_template = default_desc_template(ctx->i915, vm);
484 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
486 ce->vm = i915_vm_get(vm);
488 i915_gem_context_unlock_engines(ctx);
493 static void __assign_ppgtt(struct i915_gem_context *ctx,
494 struct i915_address_space *vm)
499 vm = __set_ppgtt(ctx, vm);
504 static struct i915_gem_context *
505 i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags)
507 struct i915_gem_context *ctx;
509 lockdep_assert_held(&dev_priv->drm.struct_mutex);
511 if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE &&
512 !HAS_EXECLISTS(dev_priv))
513 return ERR_PTR(-EINVAL);
515 /* Reap the most stale context */
516 contexts_free_first(dev_priv);
518 ctx = __create_context(dev_priv);
522 if (HAS_FULL_PPGTT(dev_priv)) {
523 struct i915_ppgtt *ppgtt;
525 ppgtt = i915_ppgtt_create(dev_priv);
527 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
530 return ERR_CAST(ppgtt);
533 __assign_ppgtt(ctx, &ppgtt->vm);
534 i915_vm_put(&ppgtt->vm);
537 if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
538 struct intel_timeline *timeline;
540 timeline = intel_timeline_create(&dev_priv->gt, NULL);
541 if (IS_ERR(timeline)) {
543 return ERR_CAST(timeline);
546 ctx->timeline = timeline;
549 trace_i915_context_create(ctx);
555 * i915_gem_context_create_gvt - create a GVT GEM context
558 * This function is used to create a GVT specific GEM context.
561 * pointer to i915_gem_context on success, error pointer if failed
564 struct i915_gem_context *
565 i915_gem_context_create_gvt(struct drm_device *dev)
567 struct i915_gem_context *ctx;
570 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
571 return ERR_PTR(-ENODEV);
573 ret = i915_mutex_lock_interruptible(dev);
577 ctx = i915_gem_create_context(to_i915(dev), 0);
581 ret = i915_gem_context_pin_hw_id(ctx);
588 ctx->file_priv = ERR_PTR(-EBADF);
589 i915_gem_context_set_closed(ctx); /* not user accessible */
590 i915_gem_context_clear_bannable(ctx);
591 i915_gem_context_set_force_single_submission(ctx);
592 if (!USES_GUC_SUBMISSION(to_i915(dev)))
593 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
595 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
597 mutex_unlock(&dev->struct_mutex);
602 destroy_kernel_context(struct i915_gem_context **ctxp)
604 struct i915_gem_context *ctx;
606 /* Keep the context ref so that we can free it immediately ourselves */
607 ctx = i915_gem_context_get(fetch_and_zero(ctxp));
608 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
611 i915_gem_context_free(ctx);
614 struct i915_gem_context *
615 i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
617 struct i915_gem_context *ctx;
620 ctx = i915_gem_create_context(i915, 0);
624 err = i915_gem_context_pin_hw_id(ctx);
626 destroy_kernel_context(&ctx);
630 i915_gem_context_clear_bannable(ctx);
631 ctx->sched.priority = I915_USER_PRIORITY(prio);
632 ctx->ring_size = PAGE_SIZE;
634 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
639 static void init_contexts(struct drm_i915_private *i915)
641 mutex_init(&i915->contexts.mutex);
642 INIT_LIST_HEAD(&i915->contexts.list);
644 /* Using the simple ida interface, the max is limited by sizeof(int) */
645 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
646 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
647 ida_init(&i915->contexts.hw_ida);
648 INIT_LIST_HEAD(&i915->contexts.hw_id_list);
650 INIT_WORK(&i915->contexts.free_work, contexts_free_worker);
651 init_llist_head(&i915->contexts.free_list);
654 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
656 struct i915_gem_context *ctx;
658 /* Reassure ourselves we are only called once */
659 GEM_BUG_ON(dev_priv->kernel_context);
661 init_contexts(dev_priv);
663 /* lowest priority; idle task */
664 ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_MIN);
666 DRM_ERROR("Failed to create default global context\n");
670 * For easy recognisablity, we want the kernel context to be 0 and then
671 * all user contexts will have non-zero hw_id. Kernel contexts are
672 * permanently pinned, so that we never suffer a stall and can
673 * use them from any allocation context (e.g. for evicting other
674 * contexts and from inside the shrinker).
676 GEM_BUG_ON(ctx->hw_id);
677 GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
678 dev_priv->kernel_context = ctx;
680 DRM_DEBUG_DRIVER("%s context support initialized\n",
681 DRIVER_CAPS(dev_priv)->has_logical_contexts ?
686 void i915_gem_contexts_fini(struct drm_i915_private *i915)
688 lockdep_assert_held(&i915->drm.struct_mutex);
690 destroy_kernel_context(&i915->kernel_context);
692 /* Must free all deferred contexts (via flush_workqueue) first */
693 GEM_BUG_ON(!list_empty(&i915->contexts.hw_id_list));
694 ida_destroy(&i915->contexts.hw_ida);
697 static int context_idr_cleanup(int id, void *p, void *data)
703 static int vm_idr_cleanup(int id, void *p, void *data)
709 static int gem_context_register(struct i915_gem_context *ctx,
710 struct drm_i915_file_private *fpriv)
714 ctx->file_priv = fpriv;
716 ctx->vm->file = fpriv;
718 ctx->pid = get_task_pid(current, PIDTYPE_PID);
719 ctx->name = kasprintf(GFP_KERNEL, "%s[%d]",
720 current->comm, pid_nr(ctx->pid));
726 /* And finally expose ourselves to userspace via the idr */
727 mutex_lock(&fpriv->context_idr_lock);
728 ret = idr_alloc(&fpriv->context_idr, ctx, 0, 0, GFP_KERNEL);
729 mutex_unlock(&fpriv->context_idr_lock);
733 kfree(fetch_and_zero(&ctx->name));
735 put_pid(fetch_and_zero(&ctx->pid));
740 int i915_gem_context_open(struct drm_i915_private *i915,
741 struct drm_file *file)
743 struct drm_i915_file_private *file_priv = file->driver_priv;
744 struct i915_gem_context *ctx;
747 mutex_init(&file_priv->context_idr_lock);
748 mutex_init(&file_priv->vm_idr_lock);
750 idr_init(&file_priv->context_idr);
751 idr_init_base(&file_priv->vm_idr, 1);
753 mutex_lock(&i915->drm.struct_mutex);
754 ctx = i915_gem_create_context(i915, 0);
755 mutex_unlock(&i915->drm.struct_mutex);
761 err = gem_context_register(ctx, file_priv);
765 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
773 idr_destroy(&file_priv->vm_idr);
774 idr_destroy(&file_priv->context_idr);
775 mutex_destroy(&file_priv->vm_idr_lock);
776 mutex_destroy(&file_priv->context_idr_lock);
780 void i915_gem_context_close(struct drm_file *file)
782 struct drm_i915_file_private *file_priv = file->driver_priv;
784 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
785 idr_destroy(&file_priv->context_idr);
786 mutex_destroy(&file_priv->context_idr_lock);
788 idr_for_each(&file_priv->vm_idr, vm_idr_cleanup, NULL);
789 idr_destroy(&file_priv->vm_idr);
790 mutex_destroy(&file_priv->vm_idr_lock);
793 int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
794 struct drm_file *file)
796 struct drm_i915_private *i915 = to_i915(dev);
797 struct drm_i915_gem_vm_control *args = data;
798 struct drm_i915_file_private *file_priv = file->driver_priv;
799 struct i915_ppgtt *ppgtt;
802 if (!HAS_FULL_PPGTT(i915))
808 ppgtt = i915_ppgtt_create(i915);
810 return PTR_ERR(ppgtt);
812 ppgtt->vm.file = file_priv;
814 if (args->extensions) {
815 err = i915_user_extensions(u64_to_user_ptr(args->extensions),
822 err = mutex_lock_interruptible(&file_priv->vm_idr_lock);
826 err = idr_alloc(&file_priv->vm_idr, &ppgtt->vm, 0, 0, GFP_KERNEL);
830 GEM_BUG_ON(err == 0); /* reserved for invalid/unassigned ppgtt */
832 mutex_unlock(&file_priv->vm_idr_lock);
838 mutex_unlock(&file_priv->vm_idr_lock);
840 i915_vm_put(&ppgtt->vm);
844 int i915_gem_vm_destroy_ioctl(struct drm_device *dev, void *data,
845 struct drm_file *file)
847 struct drm_i915_file_private *file_priv = file->driver_priv;
848 struct drm_i915_gem_vm_control *args = data;
849 struct i915_address_space *vm;
856 if (args->extensions)
863 err = mutex_lock_interruptible(&file_priv->vm_idr_lock);
867 vm = idr_remove(&file_priv->vm_idr, id);
869 mutex_unlock(&file_priv->vm_idr_lock);
877 struct context_barrier_task {
878 struct i915_active base;
879 void (*task)(void *data);
883 static void cb_retire(struct i915_active *base)
885 struct context_barrier_task *cb = container_of(base, typeof(*cb), base);
890 i915_active_fini(&cb->base);
894 I915_SELFTEST_DECLARE(static intel_engine_mask_t context_barrier_inject_fault);
895 static int context_barrier_task(struct i915_gem_context *ctx,
896 intel_engine_mask_t engines,
897 bool (*skip)(struct intel_context *ce, void *data),
898 int (*emit)(struct i915_request *rq, void *data),
899 void (*task)(void *data),
902 struct drm_i915_private *i915 = ctx->i915;
903 struct context_barrier_task *cb;
904 struct i915_gem_engines_iter it;
905 struct intel_context *ce;
908 lockdep_assert_held(&i915->drm.struct_mutex);
911 cb = kmalloc(sizeof(*cb), GFP_KERNEL);
915 i915_active_init(i915, &cb->base, NULL, cb_retire);
916 err = i915_active_acquire(&cb->base);
922 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
923 struct i915_request *rq;
925 if (I915_SELFTEST_ONLY(context_barrier_inject_fault &
931 if (!(ce->engine->mask & engines))
934 if (skip && skip(ce, data))
937 rq = intel_context_create_request(ce);
945 err = emit(rq, data);
947 err = i915_active_ref(&cb->base, rq->fence.context, rq);
949 i915_request_add(rq);
953 i915_gem_context_unlock_engines(ctx);
955 cb->task = err ? NULL : task; /* caller needs to unwind instead */
958 i915_active_release(&cb->base);
963 static int get_ppgtt(struct drm_i915_file_private *file_priv,
964 struct i915_gem_context *ctx,
965 struct drm_i915_gem_context_param *args)
967 struct i915_address_space *vm;
973 /* XXX rcu acquire? */
974 ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
978 vm = i915_vm_get(ctx->vm);
979 mutex_unlock(&ctx->i915->drm.struct_mutex);
981 ret = mutex_lock_interruptible(&file_priv->vm_idr_lock);
985 ret = idr_alloc(&file_priv->vm_idr, vm, 0, 0, GFP_KERNEL);
997 mutex_unlock(&file_priv->vm_idr_lock);
1003 static void set_ppgtt_barrier(void *data)
1005 struct i915_address_space *old = data;
1007 if (INTEL_GEN(old->i915) < 8)
1008 gen6_ppgtt_unpin_all(i915_vm_to_ppgtt(old));
1013 static int emit_ppgtt_update(struct i915_request *rq, void *data)
1015 struct i915_address_space *vm = rq->hw_context->vm;
1016 struct intel_engine_cs *engine = rq->engine;
1017 u32 base = engine->mmio_base;
1021 if (i915_vm_is_4lvl(vm)) {
1022 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1023 const dma_addr_t pd_daddr = px_dma(ppgtt->pd);
1025 cs = intel_ring_begin(rq, 6);
1029 *cs++ = MI_LOAD_REGISTER_IMM(2);
1031 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
1032 *cs++ = upper_32_bits(pd_daddr);
1033 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
1034 *cs++ = lower_32_bits(pd_daddr);
1037 intel_ring_advance(rq, cs);
1038 } else if (HAS_LOGICAL_RING_CONTEXTS(engine->i915)) {
1039 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1041 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
1045 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES);
1046 for (i = GEN8_3LVL_PDPES; i--; ) {
1047 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1049 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
1050 *cs++ = upper_32_bits(pd_daddr);
1051 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
1052 *cs++ = lower_32_bits(pd_daddr);
1055 intel_ring_advance(rq, cs);
1057 /* ppGTT is not part of the legacy context image */
1058 gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
1064 static bool skip_ppgtt_update(struct intel_context *ce, void *data)
1066 if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
1069 return !atomic_read(&ce->pin_count);
1072 static int set_ppgtt(struct drm_i915_file_private *file_priv,
1073 struct i915_gem_context *ctx,
1074 struct drm_i915_gem_context_param *args)
1076 struct i915_address_space *vm, *old;
1085 if (upper_32_bits(args->value))
1088 err = mutex_lock_interruptible(&file_priv->vm_idr_lock);
1092 vm = idr_find(&file_priv->vm_idr, args->value);
1095 mutex_unlock(&file_priv->vm_idr_lock);
1099 err = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
1106 /* Teardown the existing obj:vma cache, it will have to be rebuilt. */
1107 mutex_lock(&ctx->mutex);
1109 mutex_unlock(&ctx->mutex);
1111 old = __set_ppgtt(ctx, vm);
1114 * We need to flush any requests using the current ppgtt before
1115 * we release it as the requests do not hold a reference themselves,
1116 * only indirectly through the context.
1118 err = context_barrier_task(ctx, ALL_ENGINES,
1124 i915_vm_put(__set_ppgtt(ctx, old));
1129 mutex_unlock(&ctx->i915->drm.struct_mutex);
1136 static int gen8_emit_rpcs_config(struct i915_request *rq,
1137 struct intel_context *ce,
1138 struct intel_sseu sseu)
1143 cs = intel_ring_begin(rq, 4);
1147 offset = i915_ggtt_offset(ce->state) +
1148 LRC_STATE_PN * PAGE_SIZE +
1149 (CTX_R_PWR_CLK_STATE + 1) * 4;
1151 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1152 *cs++ = lower_32_bits(offset);
1153 *cs++ = upper_32_bits(offset);
1154 *cs++ = intel_sseu_make_rpcs(rq->i915, &sseu);
1156 intel_ring_advance(rq, cs);
1162 gen8_modify_rpcs(struct intel_context *ce, struct intel_sseu sseu)
1164 struct i915_request *rq;
1167 lockdep_assert_held(&ce->pin_mutex);
1170 * If the context is not idle, we have to submit an ordered request to
1171 * modify its context image via the kernel context (writing to our own
1172 * image, or into the registers directory, does not stick). Pristine
1173 * and idle contexts will be configured on pinning.
1175 if (!intel_context_is_pinned(ce))
1178 rq = i915_request_create(ce->engine->kernel_context);
1182 /* Serialise with the remote context */
1183 ret = intel_context_prepare_remote_request(ce, rq);
1185 ret = gen8_emit_rpcs_config(rq, ce, sseu);
1187 i915_request_add(rq);
1192 __intel_context_reconfigure_sseu(struct intel_context *ce,
1193 struct intel_sseu sseu)
1197 GEM_BUG_ON(INTEL_GEN(ce->gem_context->i915) < 8);
1199 ret = intel_context_lock_pinned(ce);
1203 /* Nothing to do if unmodified. */
1204 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
1207 ret = gen8_modify_rpcs(ce, sseu);
1212 intel_context_unlock_pinned(ce);
1217 intel_context_reconfigure_sseu(struct intel_context *ce, struct intel_sseu sseu)
1219 struct drm_i915_private *i915 = ce->gem_context->i915;
1222 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1226 ret = __intel_context_reconfigure_sseu(ce, sseu);
1228 mutex_unlock(&i915->drm.struct_mutex);
1234 user_to_context_sseu(struct drm_i915_private *i915,
1235 const struct drm_i915_gem_context_param_sseu *user,
1236 struct intel_sseu *context)
1238 const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
1240 /* No zeros in any field. */
1241 if (!user->slice_mask || !user->subslice_mask ||
1242 !user->min_eus_per_subslice || !user->max_eus_per_subslice)
1246 if (user->max_eus_per_subslice < user->min_eus_per_subslice)
1250 * Some future proofing on the types since the uAPI is wider than the
1251 * current internal implementation.
1253 if (overflows_type(user->slice_mask, context->slice_mask) ||
1254 overflows_type(user->subslice_mask, context->subslice_mask) ||
1255 overflows_type(user->min_eus_per_subslice,
1256 context->min_eus_per_subslice) ||
1257 overflows_type(user->max_eus_per_subslice,
1258 context->max_eus_per_subslice))
1261 /* Check validity against hardware. */
1262 if (user->slice_mask & ~device->slice_mask)
1265 if (user->subslice_mask & ~device->subslice_mask[0])
1268 if (user->max_eus_per_subslice > device->max_eus_per_subslice)
1271 context->slice_mask = user->slice_mask;
1272 context->subslice_mask = user->subslice_mask;
1273 context->min_eus_per_subslice = user->min_eus_per_subslice;
1274 context->max_eus_per_subslice = user->max_eus_per_subslice;
1276 /* Part specific restrictions. */
1277 if (IS_GEN(i915, 11)) {
1278 unsigned int hw_s = hweight8(device->slice_mask);
1279 unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
1280 unsigned int req_s = hweight8(context->slice_mask);
1281 unsigned int req_ss = hweight8(context->subslice_mask);
1284 * Only full subslice enablement is possible if more than one
1285 * slice is turned on.
1287 if (req_s > 1 && req_ss != hw_ss_per_s)
1291 * If more than four (SScount bitfield limit) subslices are
1292 * requested then the number has to be even.
1294 if (req_ss > 4 && (req_ss & 1))
1298 * If only one slice is enabled and subslice count is below the
1299 * device full enablement, it must be at most half of the all
1300 * available subslices.
1302 if (req_s == 1 && req_ss < hw_ss_per_s &&
1303 req_ss > (hw_ss_per_s / 2))
1306 /* ABI restriction - VME use case only. */
1308 /* All slices or one slice only. */
1309 if (req_s != 1 && req_s != hw_s)
1313 * Half subslices or full enablement only when one slice is
1317 (req_ss != hw_ss_per_s && req_ss != (hw_ss_per_s / 2)))
1320 /* No EU configuration changes. */
1321 if ((user->min_eus_per_subslice !=
1322 device->max_eus_per_subslice) ||
1323 (user->max_eus_per_subslice !=
1324 device->max_eus_per_subslice))
1331 static int set_sseu(struct i915_gem_context *ctx,
1332 struct drm_i915_gem_context_param *args)
1334 struct drm_i915_private *i915 = ctx->i915;
1335 struct drm_i915_gem_context_param_sseu user_sseu;
1336 struct intel_context *ce;
1337 struct intel_sseu sseu;
1338 unsigned long lookup;
1341 if (args->size < sizeof(user_sseu))
1344 if (!IS_GEN(i915, 11))
1347 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
1354 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
1358 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
1359 lookup |= LOOKUP_USER_INDEX;
1361 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
1365 /* Only render engine supports RPCS configuration. */
1366 if (ce->engine->class != RENDER_CLASS) {
1371 ret = user_to_context_sseu(i915, &user_sseu, &sseu);
1375 ret = intel_context_reconfigure_sseu(ce, sseu);
1379 args->size = sizeof(user_sseu);
1382 intel_context_put(ce);
1386 struct set_engines {
1387 struct i915_gem_context *ctx;
1388 struct i915_gem_engines *engines;
1392 set_engines__load_balance(struct i915_user_extension __user *base, void *data)
1394 struct i915_context_engines_load_balance __user *ext =
1395 container_of_user(base, typeof(*ext), base);
1396 const struct set_engines *set = data;
1397 struct intel_engine_cs *stack[16];
1398 struct intel_engine_cs **siblings;
1399 struct intel_context *ce;
1400 u16 num_siblings, idx;
1404 if (!HAS_EXECLISTS(set->ctx->i915))
1407 if (USES_GUC_SUBMISSION(set->ctx->i915))
1408 return -ENODEV; /* not implement yet */
1410 if (get_user(idx, &ext->engine_index))
1413 if (idx >= set->engines->num_engines) {
1414 DRM_DEBUG("Invalid placement value, %d >= %d\n",
1415 idx, set->engines->num_engines);
1419 idx = array_index_nospec(idx, set->engines->num_engines);
1420 if (set->engines->engines[idx]) {
1421 DRM_DEBUG("Invalid placement[%d], already occupied\n", idx);
1425 if (get_user(num_siblings, &ext->num_siblings))
1428 err = check_user_mbz(&ext->flags);
1432 err = check_user_mbz(&ext->mbz64);
1437 if (num_siblings > ARRAY_SIZE(stack)) {
1438 siblings = kmalloc_array(num_siblings,
1445 for (n = 0; n < num_siblings; n++) {
1446 struct i915_engine_class_instance ci;
1448 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
1453 siblings[n] = intel_engine_lookup_user(set->ctx->i915,
1455 ci.engine_instance);
1457 DRM_DEBUG("Invalid sibling[%d]: { class:%d, inst:%d }\n",
1458 n, ci.engine_class, ci.engine_instance);
1464 ce = intel_execlists_create_virtual(set->ctx, siblings, n);
1470 if (cmpxchg(&set->engines->engines[idx], NULL, ce)) {
1471 intel_context_put(ce);
1477 if (siblings != stack)
1484 set_engines__bond(struct i915_user_extension __user *base, void *data)
1486 struct i915_context_engines_bond __user *ext =
1487 container_of_user(base, typeof(*ext), base);
1488 const struct set_engines *set = data;
1489 struct i915_engine_class_instance ci;
1490 struct intel_engine_cs *virtual;
1491 struct intel_engine_cs *master;
1495 if (get_user(idx, &ext->virtual_index))
1498 if (idx >= set->engines->num_engines) {
1499 DRM_DEBUG("Invalid index for virtual engine: %d >= %d\n",
1500 idx, set->engines->num_engines);
1504 idx = array_index_nospec(idx, set->engines->num_engines);
1505 if (!set->engines->engines[idx]) {
1506 DRM_DEBUG("Invalid engine at %d\n", idx);
1509 virtual = set->engines->engines[idx]->engine;
1511 err = check_user_mbz(&ext->flags);
1515 for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
1516 err = check_user_mbz(&ext->mbz64[n]);
1521 if (copy_from_user(&ci, &ext->master, sizeof(ci)))
1524 master = intel_engine_lookup_user(set->ctx->i915,
1525 ci.engine_class, ci.engine_instance);
1527 DRM_DEBUG("Unrecognised master engine: { class:%u, instance:%u }\n",
1528 ci.engine_class, ci.engine_instance);
1532 if (get_user(num_bonds, &ext->num_bonds))
1535 for (n = 0; n < num_bonds; n++) {
1536 struct intel_engine_cs *bond;
1538 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci)))
1541 bond = intel_engine_lookup_user(set->ctx->i915,
1543 ci.engine_instance);
1545 DRM_DEBUG("Unrecognised engine[%d] for bonding: { class:%d, instance: %d }\n",
1546 n, ci.engine_class, ci.engine_instance);
1551 * A non-virtual engine has no siblings to choose between; and
1552 * a submit fence will always be directed to the one engine.
1554 if (intel_engine_is_virtual(virtual)) {
1555 err = intel_virtual_engine_attach_bond(virtual,
1566 static const i915_user_extension_fn set_engines__extensions[] = {
1567 [I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_engines__load_balance,
1568 [I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
1572 set_engines(struct i915_gem_context *ctx,
1573 const struct drm_i915_gem_context_param *args)
1575 struct i915_context_param_engines __user *user =
1576 u64_to_user_ptr(args->value);
1577 struct set_engines set = { .ctx = ctx };
1578 unsigned int num_engines, n;
1582 if (!args->size) { /* switch back to legacy user_ring_map */
1583 if (!i915_gem_context_user_engines(ctx))
1586 set.engines = default_engines(ctx);
1587 if (IS_ERR(set.engines))
1588 return PTR_ERR(set.engines);
1593 BUILD_BUG_ON(!IS_ALIGNED(sizeof(*user), sizeof(*user->engines)));
1594 if (args->size < sizeof(*user) ||
1595 !IS_ALIGNED(args->size, sizeof(*user->engines))) {
1596 DRM_DEBUG("Invalid size for engine array: %d\n",
1602 * Note that I915_EXEC_RING_MASK limits execbuf to only using the
1603 * first 64 engines defined here.
1605 num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines);
1607 set.engines = kmalloc(struct_size(set.engines, engines, num_engines),
1612 init_rcu_head(&set.engines->rcu);
1613 for (n = 0; n < num_engines; n++) {
1614 struct i915_engine_class_instance ci;
1615 struct intel_engine_cs *engine;
1617 if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) {
1618 __free_engines(set.engines, n);
1622 if (ci.engine_class == (u16)I915_ENGINE_CLASS_INVALID &&
1623 ci.engine_instance == (u16)I915_ENGINE_CLASS_INVALID_NONE) {
1624 set.engines->engines[n] = NULL;
1628 engine = intel_engine_lookup_user(ctx->i915,
1630 ci.engine_instance);
1632 DRM_DEBUG("Invalid engine[%d]: { class:%d, instance:%d }\n",
1633 n, ci.engine_class, ci.engine_instance);
1634 __free_engines(set.engines, n);
1638 set.engines->engines[n] = intel_context_create(ctx, engine);
1639 if (!set.engines->engines[n]) {
1640 __free_engines(set.engines, n);
1644 set.engines->num_engines = num_engines;
1647 if (!get_user(extensions, &user->extensions))
1648 err = i915_user_extensions(u64_to_user_ptr(extensions),
1649 set_engines__extensions,
1650 ARRAY_SIZE(set_engines__extensions),
1653 free_engines(set.engines);
1658 mutex_lock(&ctx->engines_mutex);
1660 i915_gem_context_set_user_engines(ctx);
1662 i915_gem_context_clear_user_engines(ctx);
1663 rcu_swap_protected(ctx->engines, set.engines, 1);
1664 mutex_unlock(&ctx->engines_mutex);
1666 call_rcu(&set.engines->rcu, free_engines_rcu);
1671 static struct i915_gem_engines *
1672 __copy_engines(struct i915_gem_engines *e)
1674 struct i915_gem_engines *copy;
1677 copy = kmalloc(struct_size(e, engines, e->num_engines), GFP_KERNEL);
1679 return ERR_PTR(-ENOMEM);
1681 init_rcu_head(©->rcu);
1682 for (n = 0; n < e->num_engines; n++) {
1684 copy->engines[n] = intel_context_get(e->engines[n]);
1686 copy->engines[n] = NULL;
1688 copy->num_engines = n;
1694 get_engines(struct i915_gem_context *ctx,
1695 struct drm_i915_gem_context_param *args)
1697 struct i915_context_param_engines __user *user;
1698 struct i915_gem_engines *e;
1699 size_t n, count, size;
1702 err = mutex_lock_interruptible(&ctx->engines_mutex);
1707 if (i915_gem_context_user_engines(ctx))
1708 e = __copy_engines(i915_gem_context_engines(ctx));
1709 mutex_unlock(&ctx->engines_mutex);
1710 if (IS_ERR_OR_NULL(e)) {
1712 return PTR_ERR_OR_ZERO(e);
1715 count = e->num_engines;
1717 /* Be paranoid in case we have an impedance mismatch */
1718 if (!check_struct_size(user, engines, count, &size)) {
1722 if (overflows_type(size, args->size)) {
1732 if (args->size < size) {
1737 user = u64_to_user_ptr(args->value);
1738 if (!access_ok(user, size)) {
1743 if (put_user(0, &user->extensions)) {
1748 for (n = 0; n < count; n++) {
1749 struct i915_engine_class_instance ci = {
1750 .engine_class = I915_ENGINE_CLASS_INVALID,
1751 .engine_instance = I915_ENGINE_CLASS_INVALID_NONE,
1754 if (e->engines[n]) {
1755 ci.engine_class = e->engines[n]->engine->uabi_class;
1756 ci.engine_instance = e->engines[n]->engine->instance;
1759 if (copy_to_user(&user->engines[n], &ci, sizeof(ci))) {
1772 static int ctx_setparam(struct drm_i915_file_private *fpriv,
1773 struct i915_gem_context *ctx,
1774 struct drm_i915_gem_context_param *args)
1778 switch (args->param) {
1779 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1782 else if (args->value)
1783 set_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
1785 clear_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
1788 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1791 else if (args->value)
1792 i915_gem_context_set_no_error_capture(ctx);
1794 i915_gem_context_clear_no_error_capture(ctx);
1797 case I915_CONTEXT_PARAM_BANNABLE:
1800 else if (!capable(CAP_SYS_ADMIN) && !args->value)
1802 else if (args->value)
1803 i915_gem_context_set_bannable(ctx);
1805 i915_gem_context_clear_bannable(ctx);
1808 case I915_CONTEXT_PARAM_RECOVERABLE:
1811 else if (args->value)
1812 i915_gem_context_set_recoverable(ctx);
1814 i915_gem_context_clear_recoverable(ctx);
1817 case I915_CONTEXT_PARAM_PRIORITY:
1819 s64 priority = args->value;
1823 else if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
1825 else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
1826 priority < I915_CONTEXT_MIN_USER_PRIORITY)
1828 else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
1829 !capable(CAP_SYS_NICE))
1832 ctx->sched.priority =
1833 I915_USER_PRIORITY(priority);
1837 case I915_CONTEXT_PARAM_SSEU:
1838 ret = set_sseu(ctx, args);
1841 case I915_CONTEXT_PARAM_VM:
1842 ret = set_ppgtt(fpriv, ctx, args);
1845 case I915_CONTEXT_PARAM_ENGINES:
1846 ret = set_engines(ctx, args);
1849 case I915_CONTEXT_PARAM_BAN_PERIOD:
1859 struct i915_gem_context *ctx;
1860 struct drm_i915_file_private *fpriv;
1863 static int create_setparam(struct i915_user_extension __user *ext, void *data)
1865 struct drm_i915_gem_context_create_ext_setparam local;
1866 const struct create_ext *arg = data;
1868 if (copy_from_user(&local, ext, sizeof(local)))
1871 if (local.param.ctx_id)
1874 return ctx_setparam(arg->fpriv, arg->ctx, &local.param);
1877 static int clone_engines(struct i915_gem_context *dst,
1878 struct i915_gem_context *src)
1880 struct i915_gem_engines *e = i915_gem_context_lock_engines(src);
1881 struct i915_gem_engines *clone;
1885 clone = kmalloc(struct_size(e, engines, e->num_engines), GFP_KERNEL);
1889 init_rcu_head(&clone->rcu);
1890 for (n = 0; n < e->num_engines; n++) {
1891 struct intel_engine_cs *engine;
1893 if (!e->engines[n]) {
1894 clone->engines[n] = NULL;
1897 engine = e->engines[n]->engine;
1900 * Virtual engines are singletons; they can only exist
1901 * inside a single context, because they embed their
1902 * HW context... As each virtual context implies a single
1903 * timeline (each engine can only dequeue a single request
1904 * at any time), it would be surprising for two contexts
1905 * to use the same engine. So let's create a copy of
1906 * the virtual engine instead.
1908 if (intel_engine_is_virtual(engine))
1910 intel_execlists_clone_virtual(dst, engine);
1912 clone->engines[n] = intel_context_create(dst, engine);
1913 if (IS_ERR_OR_NULL(clone->engines[n])) {
1914 __free_engines(clone, n);
1918 clone->num_engines = n;
1920 user_engines = i915_gem_context_user_engines(src);
1921 i915_gem_context_unlock_engines(src);
1923 free_engines(dst->engines);
1924 RCU_INIT_POINTER(dst->engines, clone);
1926 i915_gem_context_set_user_engines(dst);
1928 i915_gem_context_clear_user_engines(dst);
1932 i915_gem_context_unlock_engines(src);
1936 static int clone_flags(struct i915_gem_context *dst,
1937 struct i915_gem_context *src)
1939 dst->user_flags = src->user_flags;
1943 static int clone_schedattr(struct i915_gem_context *dst,
1944 struct i915_gem_context *src)
1946 dst->sched = src->sched;
1950 static int clone_sseu(struct i915_gem_context *dst,
1951 struct i915_gem_context *src)
1953 struct i915_gem_engines *e = i915_gem_context_lock_engines(src);
1954 struct i915_gem_engines *clone;
1958 clone = dst->engines; /* no locking required; sole access */
1959 if (e->num_engines != clone->num_engines) {
1964 for (n = 0; n < e->num_engines; n++) {
1965 struct intel_context *ce = e->engines[n];
1967 if (clone->engines[n]->engine->class != ce->engine->class) {
1968 /* Must have compatible engine maps! */
1973 /* serialises with set_sseu */
1974 err = intel_context_lock_pinned(ce);
1978 clone->engines[n]->sseu = ce->sseu;
1979 intel_context_unlock_pinned(ce);
1984 i915_gem_context_unlock_engines(src);
1988 static int clone_timeline(struct i915_gem_context *dst,
1989 struct i915_gem_context *src)
1991 if (src->timeline) {
1992 GEM_BUG_ON(src->timeline == dst->timeline);
1995 intel_timeline_put(dst->timeline);
1996 dst->timeline = intel_timeline_get(src->timeline);
2002 static int clone_vm(struct i915_gem_context *dst,
2003 struct i915_gem_context *src)
2005 struct i915_address_space *vm;
2009 vm = READ_ONCE(src->vm);
2013 if (!kref_get_unless_zero(&vm->ref))
2017 * This ppgtt may have be reallocated between
2018 * the read and the kref, and reassigned to a third
2019 * context. In order to avoid inadvertent sharing
2020 * of this ppgtt with that third context (and not
2021 * src), we have to confirm that we have the same
2022 * ppgtt after passing through the strong memory
2023 * barrier implied by a successful
2024 * kref_get_unless_zero().
2026 * Once we have acquired the current ppgtt of src,
2027 * we no longer care if it is released from src, as
2028 * it cannot be reallocated elsewhere.
2031 if (vm == READ_ONCE(src->vm))
2039 __assign_ppgtt(dst, vm);
2046 static int create_clone(struct i915_user_extension __user *ext, void *data)
2048 static int (* const fn[])(struct i915_gem_context *dst,
2049 struct i915_gem_context *src) = {
2050 #define MAP(x, y) [ilog2(I915_CONTEXT_CLONE_##x)] = y
2051 MAP(ENGINES, clone_engines),
2052 MAP(FLAGS, clone_flags),
2053 MAP(SCHEDATTR, clone_schedattr),
2054 MAP(SSEU, clone_sseu),
2055 MAP(TIMELINE, clone_timeline),
2059 struct drm_i915_gem_context_create_ext_clone local;
2060 const struct create_ext *arg = data;
2061 struct i915_gem_context *dst = arg->ctx;
2062 struct i915_gem_context *src;
2065 if (copy_from_user(&local, ext, sizeof(local)))
2068 BUILD_BUG_ON(GENMASK(BITS_PER_TYPE(local.flags) - 1, ARRAY_SIZE(fn)) !=
2069 I915_CONTEXT_CLONE_UNKNOWN);
2071 if (local.flags & I915_CONTEXT_CLONE_UNKNOWN)
2078 src = __i915_gem_context_lookup_rcu(arg->fpriv, local.clone_id);
2083 GEM_BUG_ON(src == dst);
2085 for (bit = 0; bit < ARRAY_SIZE(fn); bit++) {
2086 if (!(local.flags & BIT(bit)))
2089 err = fn[bit](dst, src);
2097 static const i915_user_extension_fn create_extensions[] = {
2098 [I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam,
2099 [I915_CONTEXT_CREATE_EXT_CLONE] = create_clone,
2102 static bool client_is_banned(struct drm_i915_file_private *file_priv)
2104 return atomic_read(&file_priv->ban_score) >= I915_CLIENT_SCORE_BANNED;
2107 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2108 struct drm_file *file)
2110 struct drm_i915_private *i915 = to_i915(dev);
2111 struct drm_i915_gem_context_create_ext *args = data;
2112 struct create_ext ext_data;
2115 if (!DRIVER_CAPS(i915)->has_logical_contexts)
2118 if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN)
2121 ret = intel_gt_terminally_wedged(&i915->gt);
2125 ext_data.fpriv = file->driver_priv;
2126 if (client_is_banned(ext_data.fpriv)) {
2127 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
2129 pid_nr(get_task_pid(current, PIDTYPE_PID)));
2133 ret = i915_mutex_lock_interruptible(dev);
2137 ext_data.ctx = i915_gem_create_context(i915, args->flags);
2138 mutex_unlock(&dev->struct_mutex);
2139 if (IS_ERR(ext_data.ctx))
2140 return PTR_ERR(ext_data.ctx);
2142 if (args->flags & I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS) {
2143 ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
2145 ARRAY_SIZE(create_extensions),
2151 ret = gem_context_register(ext_data.ctx, ext_data.fpriv);
2156 DRM_DEBUG("HW context %d created\n", args->ctx_id);
2161 context_close(ext_data.ctx);
2165 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *file)
2168 struct drm_i915_gem_context_destroy *args = data;
2169 struct drm_i915_file_private *file_priv = file->driver_priv;
2170 struct i915_gem_context *ctx;
2178 if (mutex_lock_interruptible(&file_priv->context_idr_lock))
2181 ctx = idr_remove(&file_priv->context_idr, args->ctx_id);
2182 mutex_unlock(&file_priv->context_idr_lock);
2190 static int get_sseu(struct i915_gem_context *ctx,
2191 struct drm_i915_gem_context_param *args)
2193 struct drm_i915_gem_context_param_sseu user_sseu;
2194 struct intel_context *ce;
2195 unsigned long lookup;
2198 if (args->size == 0)
2200 else if (args->size < sizeof(user_sseu))
2203 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
2210 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
2214 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
2215 lookup |= LOOKUP_USER_INDEX;
2217 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
2221 err = intel_context_lock_pinned(ce); /* serialises with set_sseu */
2223 intel_context_put(ce);
2227 user_sseu.slice_mask = ce->sseu.slice_mask;
2228 user_sseu.subslice_mask = ce->sseu.subslice_mask;
2229 user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice;
2230 user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice;
2232 intel_context_unlock_pinned(ce);
2233 intel_context_put(ce);
2235 if (copy_to_user(u64_to_user_ptr(args->value), &user_sseu,
2240 args->size = sizeof(user_sseu);
2245 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2246 struct drm_file *file)
2248 struct drm_i915_file_private *file_priv = file->driver_priv;
2249 struct drm_i915_gem_context_param *args = data;
2250 struct i915_gem_context *ctx;
2253 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
2257 switch (args->param) {
2258 case I915_CONTEXT_PARAM_NO_ZEROMAP:
2260 args->value = test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
2263 case I915_CONTEXT_PARAM_GTT_SIZE:
2266 args->value = ctx->vm->total;
2267 else if (to_i915(dev)->ggtt.alias)
2268 args->value = to_i915(dev)->ggtt.alias->vm.total;
2270 args->value = to_i915(dev)->ggtt.vm.total;
2273 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
2275 args->value = i915_gem_context_no_error_capture(ctx);
2278 case I915_CONTEXT_PARAM_BANNABLE:
2280 args->value = i915_gem_context_is_bannable(ctx);
2283 case I915_CONTEXT_PARAM_RECOVERABLE:
2285 args->value = i915_gem_context_is_recoverable(ctx);
2288 case I915_CONTEXT_PARAM_PRIORITY:
2290 args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT;
2293 case I915_CONTEXT_PARAM_SSEU:
2294 ret = get_sseu(ctx, args);
2297 case I915_CONTEXT_PARAM_VM:
2298 ret = get_ppgtt(file_priv, ctx, args);
2301 case I915_CONTEXT_PARAM_ENGINES:
2302 ret = get_engines(ctx, args);
2305 case I915_CONTEXT_PARAM_BAN_PERIOD:
2311 i915_gem_context_put(ctx);
2315 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2316 struct drm_file *file)
2318 struct drm_i915_file_private *file_priv = file->driver_priv;
2319 struct drm_i915_gem_context_param *args = data;
2320 struct i915_gem_context *ctx;
2323 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
2327 ret = ctx_setparam(file_priv, ctx, args);
2329 i915_gem_context_put(ctx);
2333 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
2334 void *data, struct drm_file *file)
2336 struct drm_i915_private *dev_priv = to_i915(dev);
2337 struct drm_i915_reset_stats *args = data;
2338 struct i915_gem_context *ctx;
2341 if (args->flags || args->pad)
2346 ctx = __i915_gem_context_lookup_rcu(file->driver_priv, args->ctx_id);
2351 * We opt for unserialised reads here. This may result in tearing
2352 * in the extremely unlikely event of a GPU hang on this context
2353 * as we are querying them. If we need that extra layer of protection,
2354 * we should wrap the hangstats with a seqlock.
2357 if (capable(CAP_SYS_ADMIN))
2358 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
2360 args->reset_count = 0;
2362 args->batch_active = atomic_read(&ctx->guilty_count);
2363 args->batch_pending = atomic_read(&ctx->active_count);
2371 int __i915_gem_context_pin_hw_id(struct i915_gem_context *ctx)
2373 struct drm_i915_private *i915 = ctx->i915;
2376 mutex_lock(&i915->contexts.mutex);
2378 GEM_BUG_ON(i915_gem_context_is_closed(ctx));
2380 if (list_empty(&ctx->hw_id_link)) {
2381 GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count));
2383 err = assign_hw_id(i915, &ctx->hw_id);
2387 list_add_tail(&ctx->hw_id_link, &i915->contexts.hw_id_list);
2390 GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count) == ~0u);
2391 atomic_inc(&ctx->hw_id_pin_count);
2394 mutex_unlock(&i915->contexts.mutex);
2398 /* GEM context-engines iterator: for_each_gem_engine() */
2399 struct intel_context *
2400 i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
2402 const struct i915_gem_engines *e = it->engines;
2403 struct intel_context *ctx;
2406 if (it->idx >= e->num_engines)
2409 ctx = e->engines[it->idx++];
2415 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2416 #include "selftests/mock_context.c"
2417 #include "selftests/i915_gem_context.c"
2420 static void i915_global_gem_context_shrink(void)
2422 kmem_cache_shrink(global.slab_luts);
2425 static void i915_global_gem_context_exit(void)
2427 kmem_cache_destroy(global.slab_luts);
2430 static struct i915_global_gem_context global = { {
2431 .shrink = i915_global_gem_context_shrink,
2432 .exit = i915_global_gem_context_exit,
2435 int __init i915_global_gem_context_init(void)
2437 global.slab_luts = KMEM_CACHE(i915_lut_handle, 0);
2438 if (!global.slab_luts)
2441 i915_global_register(&global.base);