2 * SPDX-License-Identifier: MIT
4 * Copyright © 2016 Intel Corporation
7 #ifndef __I915_GEM_OBJECT_TYPES_H__
8 #define __I915_GEM_OBJECT_TYPES_H__
10 #include <drm/drm_gem.h>
12 #include "i915_active.h"
13 #include "i915_selftest.h"
15 struct drm_i915_gem_object;
18 * struct i915_lut_handle tracks the fast lookups from handle to vma used
19 * for execbuf. Although we use a radixtree for that mapping, in order to
20 * remove them as the object or context is closed, we need a secondary list
21 * and a translation entry (i915_lut_handle).
23 struct i915_lut_handle {
24 struct list_head obj_link;
25 struct i915_gem_context *ctx;
29 struct drm_i915_gem_object_ops {
31 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
32 #define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
33 #define I915_GEM_OBJECT_IS_PROXY BIT(2)
34 #define I915_GEM_OBJECT_ASYNC_CANCEL BIT(3)
36 /* Interface between the GEM object and its backing storage.
37 * get_pages() is called once prior to the use of the associated set
38 * of pages before to binding them into the GTT, and put_pages() is
39 * called after we no longer need them. As we expect there to be
40 * associated cost with migrating pages between the backing storage
41 * and making them available for the GPU (e.g. clflush), we may hold
42 * onto the pages after they are no longer referenced by the GPU
43 * in case they may be used again shortly (for example migrating the
44 * pages to a different memory domain within the GTT). put_pages()
45 * will therefore most likely be called when the object itself is
46 * being released or under memory pressure (where we attempt to
47 * reap pages for the shrinker).
49 int (*get_pages)(struct drm_i915_gem_object *obj);
50 void (*put_pages)(struct drm_i915_gem_object *obj,
51 struct sg_table *pages);
52 void (*truncate)(struct drm_i915_gem_object *obj);
53 void (*writeback)(struct drm_i915_gem_object *obj);
55 int (*pwrite)(struct drm_i915_gem_object *obj,
56 const struct drm_i915_gem_pwrite *arg);
58 int (*dmabuf_export)(struct drm_i915_gem_object *obj);
59 void (*release)(struct drm_i915_gem_object *obj);
62 struct drm_i915_gem_object {
63 struct drm_gem_object base;
65 const struct drm_i915_gem_object_ops *ops;
69 * @vma.lock: protect the list/tree of vmas
74 * @vma.list: List of VMAs backed by this object
76 * The VMA on this list are ordered by type, all GGTT vma are
77 * placed at the head and all ppGTT vma are placed at the tail.
78 * The different types of GGTT vma are unordered between
79 * themselves, use the @vma.tree (which has a defined order
80 * between all VMA) to quickly find an exact match.
82 struct list_head list;
85 * @vma.tree: Ordered tree of VMAs backed by this object
87 * All VMA created for this object are placed in the @vma.tree
88 * for fast retrieval via a binary search in
89 * i915_vma_instance(). They are also added to @vma.list for
96 * @lut_list: List of vma lookup entries in use for this object.
98 * If this object is closed, we need to remove all of its VMA from
99 * the fast lookup index in associated contexts; @lut_list provides
100 * this translation from object to context->handles_vma.
102 struct list_head lut_list;
104 /** Stolen memory for this object, instead of being backed by shmem. */
105 struct drm_mm_node *stolen;
108 struct llist_node freed;
112 * Whether the object is currently in the GGTT mmap.
114 unsigned int userfault_count;
115 struct list_head userfault_link;
117 struct list_head batch_pool_link;
118 I915_SELFTEST_DECLARE(struct list_head st_link);
121 * Is the object to be mapped as read-only to the GPU
122 * Only honoured if hardware has relevant pte bit
124 unsigned int cache_level:3;
125 unsigned int cache_coherent:2;
126 #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
127 #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
128 unsigned int cache_dirty:1;
131 * @read_domains: Read memory domains.
133 * These monitor which caches contain read/write data related to the
134 * object. When transitioning from one set of domains to another,
135 * the driver is called to ensure that caches are suitably flushed and
141 * @write_domain: Corresponding unique write memory domain.
145 atomic_t frontbuffer_bits;
146 unsigned int frontbuffer_ggtt_origin; /* write once */
147 struct i915_active_request frontbuffer_write;
149 /** Current tiling stride for the object, if it's tiled. */
150 unsigned int tiling_and_stride;
151 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
152 #define TILING_MASK (FENCE_MINIMUM_STRIDE - 1)
153 #define STRIDE_MASK (~TILING_MASK)
155 /** Count of VMA actually bound by this object */
157 unsigned int active_count;
158 /** Count of how many global VMA are currently pinned for use by HW */
159 unsigned int pin_global;
162 struct mutex lock; /* protects the pages and their use */
163 atomic_t pages_pin_count;
165 struct sg_table *pages;
168 /* TODO: whack some of this into the error state */
169 struct i915_page_sizes {
171 * The sg mask of the pages sg_table. i.e the mask of
172 * of the lengths for each sg entry.
177 * The gtt page sizes we are allowed to use given the
178 * sg mask and the supported page sizes. This will
179 * express the smallest unit we can use for the whole
180 * object, as well as the larger sizes we may be able
181 * to use opportunistically.
186 * The actual gtt page size usage. Since we can have
187 * multiple vma associated with this object we need to
188 * prevent any trampling of state, hence a copy of this
189 * struct also lives in each vma, therefore the gtt
190 * value here should only be read/write through the vma.
195 I915_SELFTEST_DECLARE(unsigned int page_mask);
197 struct i915_gem_object_page_iter {
198 struct scatterlist *sg_pos;
199 unsigned int sg_idx; /* in pages, but 32bit eek! */
201 struct radix_tree_root radix;
202 struct mutex lock; /* protects this cache */
206 * Element within i915->mm.unbound_list or i915->mm.bound_list,
207 * locked by i915->mm.obj_lock.
209 struct list_head link;
212 * Advice: are the backing pages purgeable?
217 * This is set if the object has been written to since the
218 * pages were last acquired.
223 * This is set if the object has been pinned due to unknown
229 /** References from framebuffers, locks out tiling changes. */
230 unsigned int framebuffer_references;
232 /** Record of address bit 17 of each page at last unbind. */
233 unsigned long *bit_17;
236 struct i915_gem_userptr {
239 struct i915_mm_struct *mm;
240 struct i915_mmu_object *mmu_object;
241 struct work_struct *work;
244 unsigned long scratch;
249 /** for phys allocated objects */
250 struct drm_dma_handle *phys_handle;
253 static inline struct drm_i915_gem_object *
254 to_intel_bo(struct drm_gem_object *gem)
256 /* Assert that to_intel_bo(NULL) == NULL */
257 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
259 return container_of(gem, struct drm_i915_gem_object, base);