2 * SPDX-License-Identifier: MIT
4 * Copyright © 2016 Intel Corporation
7 #ifndef __I915_GEM_OBJECT_TYPES_H__
8 #define __I915_GEM_OBJECT_TYPES_H__
10 #include <drm/drm_gem.h>
12 #include "i915_active.h"
13 #include "i915_selftest.h"
15 struct drm_i915_gem_object;
16 struct intel_fronbuffer;
19 * struct i915_lut_handle tracks the fast lookups from handle to vma used
20 * for execbuf. Although we use a radixtree for that mapping, in order to
21 * remove them as the object or context is closed, we need a secondary list
22 * and a translation entry (i915_lut_handle).
24 struct i915_lut_handle {
25 struct list_head obj_link;
26 struct i915_gem_context *ctx;
30 struct drm_i915_gem_object_ops {
32 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
33 #define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
34 #define I915_GEM_OBJECT_IS_PROXY BIT(2)
35 #define I915_GEM_OBJECT_ASYNC_CANCEL BIT(3)
37 /* Interface between the GEM object and its backing storage.
38 * get_pages() is called once prior to the use of the associated set
39 * of pages before to binding them into the GTT, and put_pages() is
40 * called after we no longer need them. As we expect there to be
41 * associated cost with migrating pages between the backing storage
42 * and making them available for the GPU (e.g. clflush), we may hold
43 * onto the pages after they are no longer referenced by the GPU
44 * in case they may be used again shortly (for example migrating the
45 * pages to a different memory domain within the GTT). put_pages()
46 * will therefore most likely be called when the object itself is
47 * being released or under memory pressure (where we attempt to
48 * reap pages for the shrinker).
50 int (*get_pages)(struct drm_i915_gem_object *obj);
51 void (*put_pages)(struct drm_i915_gem_object *obj,
52 struct sg_table *pages);
53 void (*truncate)(struct drm_i915_gem_object *obj);
54 void (*writeback)(struct drm_i915_gem_object *obj);
56 int (*pwrite)(struct drm_i915_gem_object *obj,
57 const struct drm_i915_gem_pwrite *arg);
59 int (*dmabuf_export)(struct drm_i915_gem_object *obj);
60 void (*release)(struct drm_i915_gem_object *obj);
63 struct drm_i915_gem_object {
64 struct drm_gem_object base;
66 const struct drm_i915_gem_object_ops *ops;
70 * @vma.lock: protect the list/tree of vmas
75 * @vma.list: List of VMAs backed by this object
77 * The VMA on this list are ordered by type, all GGTT vma are
78 * placed at the head and all ppGTT vma are placed at the tail.
79 * The different types of GGTT vma are unordered between
80 * themselves, use the @vma.tree (which has a defined order
81 * between all VMA) to quickly find an exact match.
83 struct list_head list;
86 * @vma.tree: Ordered tree of VMAs backed by this object
88 * All VMA created for this object are placed in the @vma.tree
89 * for fast retrieval via a binary search in
90 * i915_vma_instance(). They are also added to @vma.list for
97 * @lut_list: List of vma lookup entries in use for this object.
99 * If this object is closed, we need to remove all of its VMA from
100 * the fast lookup index in associated contexts; @lut_list provides
101 * this translation from object to context->handles_vma.
103 struct list_head lut_list;
105 /** Stolen memory for this object, instead of being backed by shmem. */
106 struct drm_mm_node *stolen;
109 struct llist_node freed;
113 * Whether the object is currently in the GGTT mmap.
115 unsigned int userfault_count;
116 struct list_head userfault_link;
118 I915_SELFTEST_DECLARE(struct list_head st_link);
121 * Is the object to be mapped as read-only to the GPU
122 * Only honoured if hardware has relevant pte bit
124 unsigned int cache_level:3;
125 unsigned int cache_coherent:2;
126 #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
127 #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
128 unsigned int cache_dirty:1;
131 * @read_domains: Read memory domains.
133 * These monitor which caches contain read/write data related to the
134 * object. When transitioning from one set of domains to another,
135 * the driver is called to ensure that caches are suitably flushed and
141 * @write_domain: Corresponding unique write memory domain.
145 struct intel_frontbuffer *frontbuffer;
147 /** Current tiling stride for the object, if it's tiled. */
148 unsigned int tiling_and_stride;
149 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
150 #define TILING_MASK (FENCE_MINIMUM_STRIDE - 1)
151 #define STRIDE_MASK (~TILING_MASK)
153 /** Count of VMA actually bound by this object */
155 /** Count of how many global VMA are currently pinned for use by HW */
156 unsigned int pin_global;
159 struct mutex lock; /* protects the pages and their use */
160 atomic_t pages_pin_count;
162 struct sg_table *pages;
165 /* TODO: whack some of this into the error state */
166 struct i915_page_sizes {
168 * The sg mask of the pages sg_table. i.e the mask of
169 * of the lengths for each sg entry.
174 * The gtt page sizes we are allowed to use given the
175 * sg mask and the supported page sizes. This will
176 * express the smallest unit we can use for the whole
177 * object, as well as the larger sizes we may be able
178 * to use opportunistically.
183 * The actual gtt page size usage. Since we can have
184 * multiple vma associated with this object we need to
185 * prevent any trampling of state, hence a copy of this
186 * struct also lives in each vma, therefore the gtt
187 * value here should only be read/write through the vma.
192 I915_SELFTEST_DECLARE(unsigned int page_mask);
194 struct i915_gem_object_page_iter {
195 struct scatterlist *sg_pos;
196 unsigned int sg_idx; /* in pages, but 32bit eek! */
198 struct radix_tree_root radix;
199 struct mutex lock; /* protects this cache */
203 * Element within i915->mm.unbound_list or i915->mm.bound_list,
204 * locked by i915->mm.obj_lock.
206 struct list_head link;
209 * Advice: are the backing pages purgeable?
214 * This is set if the object has been written to since the
215 * pages were last acquired.
220 * This is set if the object has been pinned due to unknown
226 /** Record of address bit 17 of each page at last unbind. */
227 unsigned long *bit_17;
230 struct i915_gem_userptr {
233 struct i915_mm_struct *mm;
234 struct i915_mmu_object *mmu_object;
235 struct work_struct *work;
238 unsigned long scratch;
243 /** for phys allocated objects */
244 struct drm_dma_handle *phys_handle;
247 static inline struct drm_i915_gem_object *
248 to_intel_bo(struct drm_gem_object *gem)
250 /* Assert that to_intel_bo(NULL) == NULL */
251 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
253 return container_of(gem, struct drm_i915_gem_object, base);