2 * SPDX-License-Identifier: MIT
4 * Copyright © 2019 Intel Corporation
8 #include "i915_globals.h"
9 #include "i915_params.h"
10 #include "intel_context.h"
11 #include "intel_engine_pm.h"
13 #include "intel_gt_pm.h"
14 #include "intel_gt_requests.h"
15 #include "intel_llc.h"
17 #include "intel_rc6.h"
18 #include "intel_rps.h"
19 #include "intel_wakeref.h"
21 static int __gt_unpark(struct intel_wakeref *wf)
23 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
24 struct drm_i915_private *i915 = gt->i915;
28 i915_globals_unpark();
31 * It seems that the DMC likes to transition between the DC states a lot
32 * when there are no connected displays (no active power domains) during
35 * This activity has negative impact on the performance of the chip with
36 * huge latencies observed in the interrupt handler and elsewhere.
38 * Work around it by grabbing a GT IRQ power domain whilst there is any
39 * GT activity, preventing any DC state transitions.
41 gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
42 GEM_BUG_ON(!gt->awake);
44 intel_rps_unpark(>->rps);
45 i915_pmu_gt_unparked(i915);
47 intel_gt_unpark_requests(gt);
52 static int __gt_park(struct intel_wakeref *wf)
54 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
55 intel_wakeref_t wakeref = fetch_and_zero(>->awake);
56 struct drm_i915_private *i915 = gt->i915;
60 intel_gt_park_requests(gt);
63 i915_pmu_gt_parked(i915);
64 intel_rps_park(>->rps);
66 /* Everything switched off, flush any residual interrupt just in case */
67 intel_synchronize_irq(i915);
70 intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ, wakeref);
77 static const struct intel_wakeref_ops wf_ops = {
80 .flags = INTEL_WAKEREF_PUT_ASYNC,
83 void intel_gt_pm_init_early(struct intel_gt *gt)
85 intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
88 void intel_gt_pm_init(struct intel_gt *gt)
91 * Enabling power-management should be "self-healing". If we cannot
92 * enable a feature, simply leave it disabled with a notice to the
95 intel_rc6_init(>->rc6);
96 intel_rps_init(>->rps);
99 static bool reset_engines(struct intel_gt *gt)
101 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
104 return __intel_gt_reset(gt, ALL_ENGINES) == 0;
108 * intel_gt_sanitize: called after the GPU has lost power
109 * @gt: the i915 GT container
110 * @force: ignore a failed reset and sanitize engine state anyway
112 * Anytime we reset the GPU, either with an explicit GPU reset or through a
113 * PCI power cycle, the GPU loses state and we must reset our state tracking
114 * to match. Note that calling intel_gt_sanitize() if the GPU has not
115 * been reset results in much confusion!
117 void intel_gt_sanitize(struct intel_gt *gt, bool force)
119 struct intel_engine_cs *engine;
120 enum intel_engine_id id;
124 intel_uc_sanitize(>->uc);
126 for_each_engine(engine, gt, id)
127 if (engine->reset.prepare)
128 engine->reset.prepare(engine);
130 if (reset_engines(gt) || force) {
131 for_each_engine(engine, gt, id)
132 __intel_engine_reset(engine, false);
135 for_each_engine(engine, gt, id)
136 if (engine->reset.finish)
137 engine->reset.finish(engine);
140 void intel_gt_pm_fini(struct intel_gt *gt)
142 intel_rc6_fini(>->rc6);
145 int intel_gt_resume(struct intel_gt *gt)
147 struct intel_engine_cs *engine;
148 enum intel_engine_id id;
152 * After resume, we may need to poke into the pinned kernel
153 * contexts to paper over any damage caused by the sudden suspend.
154 * Only the kernel contexts should remain pinned over suspend,
155 * allowing us to fixup the user contexts on their first pin.
159 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
160 intel_rc6_sanitize(>->rc6);
162 intel_rps_enable(>->rps);
163 intel_llc_enable(>->llc);
165 for_each_engine(engine, gt, id) {
166 struct intel_context *ce;
168 intel_engine_pm_get(engine);
170 ce = engine->kernel_context;
172 GEM_BUG_ON(!intel_context_is_pinned(ce));
176 engine->serial++; /* kernel context lost */
177 err = engine->resume(engine);
179 intel_engine_pm_put(engine);
181 dev_err(gt->i915->drm.dev,
182 "Failed to restart %s (%d)\n",
188 intel_rc6_enable(>->rc6);
189 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
195 static void wait_for_idle(struct intel_gt *gt)
197 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
199 * Forcibly cancel outstanding work and leave
202 intel_gt_set_wedged(gt);
205 intel_gt_pm_wait_for_idle(gt);
208 void intel_gt_suspend(struct intel_gt *gt)
210 intel_wakeref_t wakeref;
212 /* We expect to be idle already; but also want to be independent */
215 with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
216 intel_rps_disable(>->rps);
217 intel_rc6_disable(>->rc6);
218 intel_llc_disable(>->llc);
222 void intel_gt_runtime_suspend(struct intel_gt *gt)
224 intel_uc_runtime_suspend(>->uc);
227 int intel_gt_runtime_resume(struct intel_gt *gt)
229 intel_gt_init_swizzling(gt);
231 return intel_uc_runtime_resume(>->uc);
234 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
235 #include "selftest_gt_pm.c"