drivers/gpu/drm/i915/gt/intel_gt_types.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_GT_TYPES__
   7 #define __INTEL_GT_TYPES__
   8
   9 #include <linux/ktime.h>
  10 #include <linux/list.h>
  11 #include <linux/mutex.h>
  12 #include <linux/notifier.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/types.h>
  15
  16 #include "uc/intel_uc.h"
  17
  18 #include "i915_vma.h"
  19 #include "intel_reset_types.h"
  20 #include "intel_wakeref.h"
  21
  22 struct drm_i915_private;
  23 struct i915_ggtt;
  24 struct intel_engine_cs;
  25 struct intel_uncore;
  26
  27 struct intel_hangcheck {
  28         /* For hangcheck timer */
  29 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  30 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
  31
  32         struct delayed_work work;
  33 };
  34
  35 struct intel_gt {
  36         struct drm_i915_private *i915;
  37         struct intel_uncore *uncore;
  38         struct i915_ggtt *ggtt;
  39
  40         struct intel_uc uc;
  41
  42         struct intel_gt_timelines {
  43                 struct mutex mutex; /* protects list */
  44                 struct list_head active_list;
  45
  46                 /* Pack multiple timelines' seqnos into the same page */
  47                 spinlock_t hwsp_lock;
  48                 struct list_head hwsp_free_list;
  49         } timelines;
  50
  51         struct list_head active_rings;
  52
  53         struct intel_wakeref wakeref;
  54
  55         struct list_head closed_vma;
  56         spinlock_t closed_lock; /* guards the list of closed_vma */
  57
  58         struct intel_hangcheck hangcheck;
  59         struct intel_reset reset;
  60
  61         /**
  62          * Is the GPU currently considered idle, or busy executing
  63          * userspace requests? Whilst idle, we allow runtime power
  64          * management to power down the hardware and display clocks.
  65          * In order to reduce the effect on performance, there
  66          * is a slight delay before we do so.
  67          */
  68         intel_wakeref_t awake;
  69
  70         struct blocking_notifier_head pm_notifications;
  71
  72         ktime_t last_init_time;
  73
  74         struct i915_vma *scratch;
  75
  76         u32 pm_imr;
  77         u32 pm_ier;
  78
  79         u32 pm_guc_events;
  80
  81         struct intel_engine_cs *engine[I915_NUM_ENGINES];
  82         struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
  83                                             [MAX_ENGINE_INSTANCE + 1];
  84 };
  85
  86 enum intel_gt_scratch_field {
  87         /* 8 bytes */
  88         INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
  89
  90         /* 8 bytes */
  91         INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA = 128,
  92
  93         /* 8 bytes */
  94         INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,
  95
  96         /* 8 bytes */
  97         INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
  98
  99 };
 100
 101 #endif /* __INTEL_GT_TYPES_H__ */