2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include "gem/i915_gem_context.h"
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "i915_vgpu.h"
141 #include "intel_engine_pm.h"
142 #include "intel_lrc_reg.h"
143 #include "intel_mocs.h"
144 #include "intel_reset.h"
145 #include "intel_workarounds.h"
147 #define RING_EXECLIST_QFULL (1 << 0x2)
148 #define RING_EXECLIST1_VALID (1 << 0x3)
149 #define RING_EXECLIST0_VALID (1 << 0x4)
150 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
151 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
152 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
154 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
155 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
156 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
157 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
158 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
159 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
161 #define GEN8_CTX_STATUS_COMPLETED_MASK \
162 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
164 #define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
166 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
167 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
168 #define WA_TAIL_DWORDS 2
169 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
171 struct virtual_engine {
172 struct intel_engine_cs base;
173 struct intel_context context;
176 * We allow only a single request through the virtual engine at a time
177 * (each request in the timeline waits for the completion fence of
178 * the previous before being submitted). By restricting ourselves to
179 * only submitting a single request, each request is placed on to a
180 * physical to maximise load spreading (by virtue of the late greedy
181 * scheduling -- each real engine takes the next available request
184 struct i915_request *request;
187 * We keep a rbtree of available virtual engines inside each physical
188 * engine, sorted by priority. Here we preallocate the nodes we need
189 * for the virtual engine, indexed by physical_engine->id.
194 } nodes[I915_NUM_ENGINES];
197 * Keep track of bonded pairs -- restrictions upon on our selection
198 * of physical engines any particular request may be submitted to.
199 * If we receive a submit-fence from a master engine, we will only
200 * use one of sibling_mask physical engines.
203 const struct intel_engine_cs *master;
204 intel_engine_mask_t sibling_mask;
206 unsigned int num_bonds;
208 /* And finally, which physical engines this virtual engine maps onto. */
209 unsigned int num_siblings;
210 struct intel_engine_cs *siblings[0];
213 static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine)
215 GEM_BUG_ON(!intel_engine_is_virtual(engine));
216 return container_of(engine, struct virtual_engine, base);
219 static int execlists_context_deferred_alloc(struct intel_context *ce,
220 struct intel_engine_cs *engine);
221 static void execlists_init_reg_state(u32 *reg_state,
222 struct intel_context *ce,
223 struct intel_engine_cs *engine,
224 struct intel_ring *ring);
226 static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
228 return (i915_ggtt_offset(engine->status_page.vma) +
229 I915_GEM_HWS_PREEMPT_ADDR);
233 ring_set_paused(const struct intel_engine_cs *engine, int state)
236 * We inspect HWS_PREEMPT with a semaphore inside
237 * engine->emit_fini_breadcrumb. If the dword is true,
238 * the ring is paused as the semaphore will busywait
239 * until the dword is false.
241 engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
245 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
247 return rb_entry(rb, struct i915_priolist, node);
250 static inline int rq_prio(const struct i915_request *rq)
252 return rq->sched.attr.priority;
255 static int effective_prio(const struct i915_request *rq)
257 int prio = rq_prio(rq);
260 * On unwinding the active request, we give it a priority bump
261 * if it has completed waiting on any semaphore. If we know that
262 * the request has already started, we can prevent an unwanted
263 * preempt-to-idle cycle by taking that into account now.
265 if (__i915_request_has_started(rq))
266 prio |= I915_PRIORITY_NOSEMAPHORE;
268 /* Restrict mere WAIT boosts from triggering preemption */
269 BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
270 return prio | __NO_PREEMPTION;
273 static int queue_prio(const struct intel_engine_execlists *execlists)
275 struct i915_priolist *p;
278 rb = rb_first_cached(&execlists->queue);
283 * As the priolist[] are inverted, with the highest priority in [0],
284 * we have to flip the index value to become priority.
287 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
290 static inline bool need_preempt(const struct intel_engine_cs *engine,
291 const struct i915_request *rq,
297 * Check if the current priority hint merits a preemption attempt.
299 * We record the highest value priority we saw during rescheduling
300 * prior to this dequeue, therefore we know that if it is strictly
301 * less than the current tail of ESLP[0], we do not need to force
302 * a preempt-to-idle cycle.
304 * However, the priority hint is a mere hint that we may need to
305 * preempt. If that hint is stale or we may be trying to preempt
306 * ourselves, ignore the request.
308 last_prio = effective_prio(rq);
309 if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint,
314 * Check against the first request in ELSP[1], it will, thanks to the
315 * power of PI, be the highest priority of that context.
317 if (!list_is_last(&rq->sched.link, &engine->active.requests) &&
318 rq_prio(list_next_entry(rq, sched.link)) > last_prio)
322 struct virtual_engine *ve =
323 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
324 bool preempt = false;
326 if (engine == ve->siblings[0]) { /* only preempt one sibling */
327 struct i915_request *next;
330 next = READ_ONCE(ve->request);
332 preempt = rq_prio(next) > last_prio;
341 * If the inflight context did not trigger the preemption, then maybe
342 * it was the set of queued requests? Pick the highest priority in
343 * the queue (the first active priolist) and see if it deserves to be
344 * running instead of ELSP[0].
346 * The highest priority request in the queue can not be either
347 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same
348 * context, it's priority would not exceed ELSP[0] aka last_prio.
350 return queue_prio(&engine->execlists) > last_prio;
353 __maybe_unused static inline bool
354 assert_priority_queue(const struct i915_request *prev,
355 const struct i915_request *next)
358 * Without preemption, the prev may refer to the still active element
359 * which we refuse to let go.
361 * Even with preemption, there are times when we think it is better not
362 * to preempt and leave an ostensibly lower priority request in flight.
364 if (i915_request_is_active(prev))
367 return rq_prio(prev) >= rq_prio(next);
371 * The context descriptor encodes various attributes of a context,
372 * including its GTT address and some flags. Because it's fairly
373 * expensive to calculate, we'll just do it once and cache the result,
374 * which remains valid until the context is unpinned.
376 * This is what a descriptor looks like, from LSB to MSB::
378 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
379 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
380 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
381 * bits 53-54: mbz, reserved for use by hardware
382 * bits 55-63: group ID, currently unused and set to 0
384 * Starting from Gen11, the upper dword of the descriptor has a new format:
386 * bits 32-36: reserved
387 * bits 37-47: SW context ID
388 * bits 48:53: engine instance
389 * bit 54: mbz, reserved for use by hardware
390 * bits 55-60: SW counter
391 * bits 61-63: engine class
393 * engine info, SW context ID and SW counter need to form a unique number
394 * (Context ID) per lrc.
397 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
399 struct i915_gem_context *ctx = ce->gem_context;
402 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
403 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
405 desc = ctx->desc_template; /* bits 0-11 */
406 GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
408 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
410 GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
413 * The following 32bits are copied into the OA reports (dword 2).
414 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
417 if (INTEL_GEN(engine->i915) >= 11) {
418 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
419 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
422 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
425 /* TODO: decide what to do with SW counter (bits 55-60) */
427 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
430 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
431 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
437 static void unwind_wa_tail(struct i915_request *rq)
439 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
440 assert_ring_tail_valid(rq->ring, rq->tail);
443 static struct i915_request *
444 __unwind_incomplete_requests(struct intel_engine_cs *engine)
446 struct i915_request *rq, *rn, *active = NULL;
447 struct list_head *uninitialized_var(pl);
448 int prio = I915_PRIORITY_INVALID;
450 lockdep_assert_held(&engine->active.lock);
452 list_for_each_entry_safe_reverse(rq, rn,
453 &engine->active.requests,
455 struct intel_engine_cs *owner;
457 if (i915_request_completed(rq))
460 __i915_request_unsubmit(rq);
464 * Push the request back into the queue for later resubmission.
465 * If this request is not native to this physical engine (i.e.
466 * it came from a virtual source), push it back onto the virtual
467 * engine so that it can be moved across onto another physical
468 * engine as load dictates.
470 owner = rq->hw_context->engine;
471 if (likely(owner == engine)) {
472 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
473 if (rq_prio(rq) != prio) {
475 pl = i915_sched_lookup_priolist(engine, prio);
477 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
479 list_move(&rq->sched.link, pl);
483 owner->submit_request(rq);
491 struct i915_request *
492 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
494 struct intel_engine_cs *engine =
495 container_of(execlists, typeof(*engine), execlists);
497 return __unwind_incomplete_requests(engine);
501 execlists_context_status_change(struct i915_request *rq, unsigned long status)
504 * Only used when GVT-g is enabled now. When GVT-g is disabled,
505 * The compiler should eliminate this function as dead-code.
507 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
510 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
514 static inline struct i915_request *
515 execlists_schedule_in(struct i915_request *rq, int idx)
517 struct intel_context *ce = rq->hw_context;
520 trace_i915_request_in(rq, idx);
522 count = intel_context_inflight_count(ce);
524 intel_context_get(ce);
525 ce->inflight = rq->engine;
527 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
528 intel_engine_context_in(ce->inflight);
531 intel_context_inflight_inc(ce);
532 GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
534 return i915_request_get(rq);
537 static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
539 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
540 struct i915_request *next = READ_ONCE(ve->request);
542 if (next && next->execution_mask & ~rq->execution_mask)
543 tasklet_schedule(&ve->base.execlists.tasklet);
547 execlists_schedule_out(struct i915_request *rq)
549 struct intel_context *ce = rq->hw_context;
551 GEM_BUG_ON(!intel_context_inflight_count(ce));
553 trace_i915_request_out(rq);
555 intel_context_inflight_dec(ce);
556 if (!intel_context_inflight_count(ce)) {
557 intel_engine_context_out(ce->inflight);
558 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
561 * If this is part of a virtual engine, its next request may
562 * have been blocked waiting for access to the active context.
563 * We have to kick all the siblings again in case we need to
564 * switch (e.g. the next request is not runnable on this
565 * engine). Hopefully, we will already have submitted the next
566 * request before the tasklet runs and do not need to rebuild
567 * each virtual tree and kick everyone again.
570 if (rq->engine != ce->engine)
571 kick_siblings(rq, ce);
573 intel_context_put(ce);
576 i915_request_put(rq);
579 static u64 execlists_update_context(const struct i915_request *rq)
581 struct intel_context *ce = rq->hw_context;
584 ce->lrc_reg_state[CTX_RING_TAIL + 1] =
585 intel_ring_set_tail(rq->ring, rq->tail);
588 * Make sure the context image is complete before we submit it to HW.
590 * Ostensibly, writes (including the WCB) should be flushed prior to
591 * an uncached write such as our mmio register access, the empirical
592 * evidence (esp. on Braswell) suggests that the WC write into memory
593 * may not be visible to the HW prior to the completion of the UC
594 * register write and that we may begin execution from the context
595 * before its image is complete leading to invalid PD chasing.
597 * Furthermore, Braswell, at least, wants a full mb to be sure that
598 * the writes are coherent in memory (visible to the GPU) prior to
599 * execution, and not just visible to other CPUs (as is the result of
605 ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;
610 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
612 if (execlists->ctrl_reg) {
613 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
614 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
616 writel(upper_32_bits(desc), execlists->submit_reg);
617 writel(lower_32_bits(desc), execlists->submit_reg);
621 static __maybe_unused void
622 trace_ports(const struct intel_engine_execlists *execlists,
624 struct i915_request * const *ports)
626 const struct intel_engine_cs *engine =
627 container_of(execlists, typeof(*engine), execlists);
629 GEM_TRACE("%s: %s { %llx:%lld%s, %llx:%lld }\n",
631 ports[0]->fence.context,
632 ports[0]->fence.seqno,
633 i915_request_completed(ports[0]) ? "!" :
634 i915_request_started(ports[0]) ? "*" :
636 ports[1] ? ports[1]->fence.context : 0,
637 ports[1] ? ports[1]->fence.seqno : 0);
640 static __maybe_unused bool
641 assert_pending_valid(const struct intel_engine_execlists *execlists,
644 struct i915_request * const *port, *rq;
645 struct intel_context *ce = NULL;
647 trace_ports(execlists, msg, execlists->pending);
649 if (execlists->pending[execlists_num_ports(execlists)])
652 for (port = execlists->pending; (rq = *port); port++) {
653 if (ce == rq->hw_context)
657 if (i915_request_completed(rq))
660 if (i915_active_is_idle(&ce->active))
663 if (!i915_vma_is_pinned(ce->state))
670 static void execlists_submit_ports(struct intel_engine_cs *engine)
672 struct intel_engine_execlists *execlists = &engine->execlists;
675 GEM_BUG_ON(!assert_pending_valid(execlists, "submit"));
678 * We can skip acquiring intel_runtime_pm_get() here as it was taken
679 * on our behalf by the request (see i915_gem_mark_busy()) and it will
680 * not be relinquished until the device is idle (see
681 * i915_gem_idle_work_handler()). As a precaution, we make sure
682 * that all ELSP are drained i.e. we have processed the CSB,
683 * before allowing ourselves to idle and calling intel_runtime_pm_put().
685 GEM_BUG_ON(!intel_wakeref_active(&engine->wakeref));
688 * ELSQ note: the submit queue is not cleared after being submitted
689 * to the HW so we need to make sure we always clean it up. This is
690 * currently ensured by the fact that we always write the same number
691 * of elsq entries, keep this in mind before changing the loop below.
693 for (n = execlists_num_ports(execlists); n--; ) {
694 struct i915_request *rq = execlists->pending[n];
696 write_desc(execlists,
697 rq ? execlists_update_context(rq) : 0,
701 /* we need to manually load the submit queue */
702 if (execlists->ctrl_reg)
703 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
706 static bool ctx_single_port_submission(const struct intel_context *ce)
708 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
709 i915_gem_context_force_single_submission(ce->gem_context));
712 static bool can_merge_ctx(const struct intel_context *prev,
713 const struct intel_context *next)
718 if (ctx_single_port_submission(prev))
724 static bool can_merge_rq(const struct i915_request *prev,
725 const struct i915_request *next)
727 GEM_BUG_ON(prev == next);
728 GEM_BUG_ON(!assert_priority_queue(prev, next));
730 if (!can_merge_ctx(prev->hw_context, next->hw_context))
736 static void virtual_update_register_offsets(u32 *regs,
737 struct intel_engine_cs *engine)
739 u32 base = engine->mmio_base;
741 /* Must match execlists_init_reg_state()! */
743 regs[CTX_CONTEXT_CONTROL] =
744 i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base));
745 regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base));
746 regs[CTX_RING_TAIL] = i915_mmio_reg_offset(RING_TAIL(base));
747 regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base));
748 regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base));
750 regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base));
751 regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base));
752 regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base));
753 regs[CTX_SECOND_BB_HEAD_U] =
754 i915_mmio_reg_offset(RING_SBBADDR_UDW(base));
755 regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base));
756 regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base));
758 regs[CTX_CTX_TIMESTAMP] =
759 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base));
760 regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3));
761 regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3));
762 regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2));
763 regs[CTX_PDP2_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 2));
764 regs[CTX_PDP1_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 1));
765 regs[CTX_PDP1_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 1));
766 regs[CTX_PDP0_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
767 regs[CTX_PDP0_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
769 if (engine->class == RENDER_CLASS) {
770 regs[CTX_RCS_INDIRECT_CTX] =
771 i915_mmio_reg_offset(RING_INDIRECT_CTX(base));
772 regs[CTX_RCS_INDIRECT_CTX_OFFSET] =
773 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(base));
774 regs[CTX_BB_PER_CTX_PTR] =
775 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(base));
777 regs[CTX_R_PWR_CLK_STATE] =
778 i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
782 static bool virtual_matches(const struct virtual_engine *ve,
783 const struct i915_request *rq,
784 const struct intel_engine_cs *engine)
786 const struct intel_engine_cs *inflight;
788 if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */
792 * We track when the HW has completed saving the context image
793 * (i.e. when we have seen the final CS event switching out of
794 * the context) and must not overwrite the context image before
795 * then. This restricts us to only using the active engine
796 * while the previous virtualized request is inflight (so
797 * we reuse the register offsets). This is a very small
798 * hystersis on the greedy seelction algorithm.
800 inflight = intel_context_inflight(&ve->context);
801 if (inflight && inflight != engine)
807 static void virtual_xfer_breadcrumbs(struct virtual_engine *ve,
808 struct intel_engine_cs *engine)
810 struct intel_engine_cs *old = ve->siblings[0];
812 /* All unattached (rq->engine == old) must already be completed */
814 spin_lock(&old->breadcrumbs.irq_lock);
815 if (!list_empty(&ve->context.signal_link)) {
816 list_move_tail(&ve->context.signal_link,
817 &engine->breadcrumbs.signalers);
818 intel_engine_queue_breadcrumbs(engine);
820 spin_unlock(&old->breadcrumbs.irq_lock);
823 static struct i915_request *
824 last_active(const struct intel_engine_execlists *execlists)
826 struct i915_request * const *last = execlists->active;
828 while (*last && i915_request_completed(*last))
835 defer_request(struct i915_request * const rq, struct list_head * const pl)
837 struct i915_dependency *p;
840 * We want to move the interrupted request to the back of
841 * the round-robin list (i.e. its priority level), but
842 * in doing so, we must then move all requests that were in
843 * flight and were waiting for the interrupted request to
844 * be run after it again.
846 list_move_tail(&rq->sched.link, pl);
848 list_for_each_entry(p, &rq->sched.waiters_list, wait_link) {
849 struct i915_request *w =
850 container_of(p->waiter, typeof(*w), sched);
852 /* Leave semaphores spinning on the other engines */
853 if (w->engine != rq->engine)
856 /* No waiter should start before the active request completed */
857 GEM_BUG_ON(i915_request_started(w));
859 GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
860 if (rq_prio(w) < rq_prio(rq))
863 if (list_empty(&w->sched.link))
864 continue; /* Not yet submitted; unready */
867 * This should be very shallow as it is limited by the
868 * number of requests that can fit in a ring (<64) and
869 * the number of contexts that can be in flight on this
872 defer_request(w, pl);
876 static void defer_active(struct intel_engine_cs *engine)
878 struct i915_request *rq;
880 rq = __unwind_incomplete_requests(engine);
884 defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
888 need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
892 if (list_is_last(&rq->sched.link, &engine->active.requests))
895 hint = max(rq_prio(list_next_entry(rq, sched.link)),
896 engine->execlists.queue_priority_hint);
898 return hint >= rq_prio(rq);
902 enable_timeslice(struct intel_engine_cs *engine)
904 struct i915_request *last = last_active(&engine->execlists);
906 return last && need_timeslice(engine, last);
909 static void execlists_dequeue(struct intel_engine_cs *engine)
911 struct intel_engine_execlists * const execlists = &engine->execlists;
912 struct i915_request **port = execlists->pending;
913 struct i915_request ** const last_port = port + execlists->port_mask;
914 struct i915_request *last;
919 * Hardware submission is through 2 ports. Conceptually each port
920 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
921 * static for a context, and unique to each, so we only execute
922 * requests belonging to a single context from each ring. RING_HEAD
923 * is maintained by the CS in the context image, it marks the place
924 * where it got up to last time, and through RING_TAIL we tell the CS
925 * where we want to execute up to this time.
927 * In this list the requests are in order of execution. Consecutive
928 * requests from the same context are adjacent in the ringbuffer. We
929 * can combine these requests into a single RING_TAIL update:
931 * RING_HEAD...req1...req2
933 * since to execute req2 the CS must first execute req1.
935 * Our goal then is to point each port to the end of a consecutive
936 * sequence of requests as being the most optimal (fewest wake ups
937 * and context switches) submission.
940 for (rb = rb_first_cached(&execlists->virtual); rb; ) {
941 struct virtual_engine *ve =
942 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
943 struct i915_request *rq = READ_ONCE(ve->request);
945 if (!rq) { /* lazily cleanup after another engine handled rq */
946 rb_erase_cached(rb, &execlists->virtual);
948 rb = rb_first_cached(&execlists->virtual);
952 if (!virtual_matches(ve, rq, engine)) {
961 * If the queue is higher priority than the last
962 * request in the currently active context, submit afresh.
963 * We will resubmit again afterwards in case we need to split
964 * the active context to interject the preemption request,
965 * i.e. we will retrigger preemption following the ack in case
968 last = last_active(execlists);
970 if (need_preempt(engine, last, rb)) {
971 GEM_TRACE("%s: preempting last=%llx:%lld, prio=%d, hint=%d\n",
975 last->sched.attr.priority,
976 execlists->queue_priority_hint);
978 * Don't let the RING_HEAD advance past the breadcrumb
979 * as we unwind (and until we resubmit) so that we do
980 * not accidentally tell it to go backwards.
982 ring_set_paused(engine, 1);
985 * Note that we have not stopped the GPU at this point,
986 * so we are unwinding the incomplete requests as they
987 * remain inflight and so by the time we do complete
988 * the preemption, some of the unwound requests may
991 __unwind_incomplete_requests(engine);
994 * If we need to return to the preempted context, we
995 * need to skip the lite-restore and force it to
996 * reload the RING_TAIL. Otherwise, the HW has a
997 * tendency to ignore us rewinding the TAIL to the
998 * end of an earlier request.
1000 last->hw_context->lrc_desc |= CTX_DESC_FORCE_RESTORE;
1002 } else if (need_timeslice(engine, last) &&
1003 !timer_pending(&engine->execlists.timer)) {
1004 GEM_TRACE("%s: expired last=%llx:%lld, prio=%d, hint=%d\n",
1006 last->fence.context,
1008 last->sched.attr.priority,
1009 execlists->queue_priority_hint);
1011 ring_set_paused(engine, 1);
1012 defer_active(engine);
1015 * Unlike for preemption, if we rewind and continue
1016 * executing the same context as previously active,
1017 * the order of execution will remain the same and
1018 * the tail will only advance. We do not need to
1019 * force a full context restore, as a lite-restore
1020 * is sufficient to resample the monotonic TAIL.
1022 * If we switch to any other context, similarly we
1023 * will not rewind TAIL of current context, and
1024 * normal save/restore will preserve state and allow
1025 * us to later continue executing the same request.
1030 * Otherwise if we already have a request pending
1031 * for execution after the current one, we can
1032 * just wait until the next CS event before
1033 * queuing more. In either case we will force a
1034 * lite-restore preemption event, but if we wait
1035 * we hopefully coalesce several updates into a single
1038 if (!list_is_last(&last->sched.link,
1039 &engine->active.requests))
1043 * WaIdleLiteRestore:bdw,skl
1044 * Apply the wa NOOPs to prevent
1045 * ring:HEAD == rq:TAIL as we resubmit the
1046 * request. See gen8_emit_fini_breadcrumb() for
1047 * where we prepare the padding after the
1048 * end of the request.
1050 last->tail = last->wa_tail;
1054 while (rb) { /* XXX virtual is always taking precedence */
1055 struct virtual_engine *ve =
1056 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
1057 struct i915_request *rq;
1059 spin_lock(&ve->base.active.lock);
1062 if (unlikely(!rq)) { /* lost the race to a sibling */
1063 spin_unlock(&ve->base.active.lock);
1064 rb_erase_cached(rb, &execlists->virtual);
1066 rb = rb_first_cached(&execlists->virtual);
1070 GEM_BUG_ON(rq != ve->request);
1071 GEM_BUG_ON(rq->engine != &ve->base);
1072 GEM_BUG_ON(rq->hw_context != &ve->context);
1074 if (rq_prio(rq) >= queue_prio(execlists)) {
1075 if (!virtual_matches(ve, rq, engine)) {
1076 spin_unlock(&ve->base.active.lock);
1081 if (i915_request_completed(rq)) {
1083 ve->base.execlists.queue_priority_hint = INT_MIN;
1084 rb_erase_cached(rb, &execlists->virtual);
1087 rq->engine = engine;
1088 __i915_request_submit(rq);
1090 spin_unlock(&ve->base.active.lock);
1092 rb = rb_first_cached(&execlists->virtual);
1096 if (last && !can_merge_rq(last, rq)) {
1097 spin_unlock(&ve->base.active.lock);
1098 return; /* leave this for another */
1101 GEM_TRACE("%s: virtual rq=%llx:%lld%s, new engine? %s\n",
1105 i915_request_completed(rq) ? "!" :
1106 i915_request_started(rq) ? "*" :
1108 yesno(engine != ve->siblings[0]));
1111 ve->base.execlists.queue_priority_hint = INT_MIN;
1112 rb_erase_cached(rb, &execlists->virtual);
1115 GEM_BUG_ON(!(rq->execution_mask & engine->mask));
1116 rq->engine = engine;
1118 if (engine != ve->siblings[0]) {
1119 u32 *regs = ve->context.lrc_reg_state;
1122 GEM_BUG_ON(READ_ONCE(ve->context.inflight));
1123 virtual_update_register_offsets(regs, engine);
1125 if (!list_empty(&ve->context.signals))
1126 virtual_xfer_breadcrumbs(ve, engine);
1129 * Move the bound engine to the top of the list
1130 * for future execution. We then kick this
1131 * tasklet first before checking others, so that
1132 * we preferentially reuse this set of bound
1135 for (n = 1; n < ve->num_siblings; n++) {
1136 if (ve->siblings[n] == engine) {
1137 swap(ve->siblings[n],
1143 GEM_BUG_ON(ve->siblings[0] != engine);
1146 __i915_request_submit(rq);
1147 if (!i915_request_completed(rq)) {
1153 spin_unlock(&ve->base.active.lock);
1157 while ((rb = rb_first_cached(&execlists->queue))) {
1158 struct i915_priolist *p = to_priolist(rb);
1159 struct i915_request *rq, *rn;
1162 priolist_for_each_request_consume(rq, rn, p, i) {
1163 if (i915_request_completed(rq))
1167 * Can we combine this request with the current port?
1168 * It has to be the same context/ringbuffer and not
1169 * have any exceptions (e.g. GVT saying never to
1170 * combine contexts).
1172 * If we can combine the requests, we can execute both
1173 * by updating the RING_TAIL to point to the end of the
1174 * second request, and so we never need to tell the
1175 * hardware about the first.
1177 if (last && !can_merge_rq(last, rq)) {
1179 * If we are on the second port and cannot
1180 * combine this request with the last, then we
1183 if (port == last_port)
1187 * We must not populate both ELSP[] with the
1188 * same LRCA, i.e. we must submit 2 different
1189 * contexts if we submit 2 ELSP.
1191 if (last->hw_context == rq->hw_context)
1195 * If GVT overrides us we only ever submit
1196 * port[0], leaving port[1] empty. Note that we
1197 * also have to be careful that we don't queue
1198 * the same context (even though a different
1199 * request) to the second port.
1201 if (ctx_single_port_submission(last->hw_context) ||
1202 ctx_single_port_submission(rq->hw_context))
1205 *port = execlists_schedule_in(last, port - execlists->pending);
1212 __i915_request_submit(rq);
1215 rb_erase_cached(&p->node, &execlists->queue);
1216 i915_priolist_free(p);
1221 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
1223 * We choose the priority hint such that if we add a request of greater
1224 * priority than this, we kick the submission tasklet to decide on
1225 * the right order of submitting the requests to hardware. We must
1226 * also be prepared to reorder requests as they are in-flight on the
1227 * HW. We derive the priority hint then as the first "hole" in
1228 * the HW submission ports and if there are no available slots,
1229 * the priority of the lowest executing request, i.e. last.
1231 * When we do receive a higher priority request ready to run from the
1232 * user, see queue_request(), the priority hint is bumped to that
1233 * request triggering preemption on the next dequeue (or subsequent
1234 * interrupt for secondary ports).
1236 execlists->queue_priority_hint = queue_prio(execlists);
1237 GEM_TRACE("%s: queue_priority_hint:%d, submit:%s\n",
1238 engine->name, execlists->queue_priority_hint,
1242 *port = execlists_schedule_in(last, port - execlists->pending);
1243 memset(port + 1, 0, (last_port - port) * sizeof(*port));
1244 execlists_submit_ports(engine);
1249 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
1251 struct i915_request * const *port, *rq;
1253 for (port = execlists->pending; (rq = *port); port++)
1254 execlists_schedule_out(rq);
1255 memset(execlists->pending, 0, sizeof(execlists->pending));
1257 for (port = execlists->active; (rq = *port); port++)
1258 execlists_schedule_out(rq);
1260 memset(execlists->inflight, 0, sizeof(execlists->inflight));
1264 invalidate_csb_entries(const u32 *first, const u32 *last)
1266 clflush((void *)first);
1267 clflush((void *)last);
1271 reset_in_progress(const struct intel_engine_execlists *execlists)
1273 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
1276 static void process_csb(struct intel_engine_cs *engine)
1278 struct intel_engine_execlists * const execlists = &engine->execlists;
1279 const u32 * const buf = execlists->csb_status;
1280 const u8 num_entries = execlists->csb_size;
1283 lockdep_assert_held(&engine->active.lock);
1284 GEM_BUG_ON(USES_GUC_SUBMISSION(engine->i915));
1287 * Note that csb_write, csb_status may be either in HWSP or mmio.
1288 * When reading from the csb_write mmio register, we have to be
1289 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
1290 * the low 4bits. As it happens we know the next 4bits are always
1291 * zero and so we can simply masked off the low u8 of the register
1292 * and treat it identically to reading from the HWSP (without having
1293 * to use explicit shifting and masking, and probably bifurcating
1294 * the code to handle the legacy mmio read).
1296 head = execlists->csb_head;
1297 tail = READ_ONCE(*execlists->csb_write);
1298 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
1299 if (unlikely(head == tail))
1303 * Hopefully paired with a wmb() in HW!
1305 * We must complete the read of the write pointer before any reads
1306 * from the CSB, so that we do not see stale values. Without an rmb
1307 * (lfence) the HW may speculatively perform the CSB[] reads *before*
1308 * we perform the READ_ONCE(*csb_write).
1313 unsigned int status;
1315 if (++head == num_entries)
1319 * We are flying near dragons again.
1321 * We hold a reference to the request in execlist_port[]
1322 * but no more than that. We are operating in softirq
1323 * context and so cannot hold any mutex or sleep. That
1324 * prevents us stopping the requests we are processing
1325 * in port[] from being retired simultaneously (the
1326 * breadcrumb will be complete before we see the
1327 * context-switch). As we only hold the reference to the
1328 * request, any pointer chasing underneath the request
1329 * is subject to a potential use-after-free. Thus we
1330 * store all of the bookkeeping within port[] as
1331 * required, and avoid using unguarded pointers beneath
1332 * request itself. The same applies to the atomic
1336 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x\n",
1338 buf[2 * head + 0], buf[2 * head + 1]);
1340 status = buf[2 * head];
1341 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) {
1342 GEM_BUG_ON(*execlists->active);
1344 GEM_BUG_ON(!assert_pending_valid(execlists, "promote"));
1346 memcpy(execlists->inflight,
1348 execlists_num_ports(execlists) *
1349 sizeof(*execlists->pending));
1350 execlists->pending[0] = NULL;
1352 if (enable_timeslice(engine))
1353 mod_timer(&execlists->timer, jiffies + 1);
1355 if (!inject_preempt_hang(execlists))
1356 ring_set_paused(engine, 0);
1357 } else if (status & GEN8_CTX_STATUS_PREEMPTED) {
1358 struct i915_request * const *port = execlists->active;
1360 trace_ports(execlists, "preempted", execlists->active);
1363 execlists_schedule_out(*port++);
1366 } else if (*execlists->active) {
1367 struct i915_request *rq = *execlists->active++;
1369 trace_ports(execlists, "completed",
1370 execlists->active - 1);
1373 * We rely on the hardware being strongly
1374 * ordered, that the breadcrumb write is
1375 * coherent (visible from the CPU) before the
1376 * user interrupt and CSB is processed.
1378 GEM_BUG_ON(!i915_request_completed(rq));
1379 execlists_schedule_out(rq);
1381 GEM_BUG_ON(execlists->active - execlists->inflight >
1382 execlists_num_ports(execlists));
1384 } while (head != tail);
1386 execlists->csb_head = head;
1389 * Gen11 has proven to fail wrt global observation point between
1390 * entry and tail update, failing on the ordering and thus
1391 * we see an old entry in the context status buffer.
1393 * Forcibly evict out entries for the next gpu csb update,
1394 * to increase the odds that we get a fresh entries with non
1395 * working hardware. The cost for doing so comes out mostly with
1396 * the wash as hardware, working or not, will need to do the
1397 * invalidation before.
1399 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
1402 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
1404 lockdep_assert_held(&engine->active.lock);
1406 process_csb(engine);
1407 if (!engine->execlists.pending[0])
1408 execlists_dequeue(engine);
1412 * Check the unread Context Status Buffers and manage the submission of new
1413 * contexts to the ELSP accordingly.
1415 static void execlists_submission_tasklet(unsigned long data)
1417 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1418 unsigned long flags;
1420 spin_lock_irqsave(&engine->active.lock, flags);
1421 __execlists_submission_tasklet(engine);
1422 spin_unlock_irqrestore(&engine->active.lock, flags);
1425 static void execlists_submission_timer(struct timer_list *timer)
1427 struct intel_engine_cs *engine =
1428 from_timer(engine, timer, execlists.timer);
1430 /* Kick the tasklet for some interrupt coalescing and reset handling */
1431 tasklet_hi_schedule(&engine->execlists.tasklet);
1434 static void queue_request(struct intel_engine_cs *engine,
1435 struct i915_sched_node *node,
1438 GEM_BUG_ON(!list_empty(&node->link));
1439 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio));
1442 static void __submit_queue_imm(struct intel_engine_cs *engine)
1444 struct intel_engine_execlists * const execlists = &engine->execlists;
1446 if (reset_in_progress(execlists))
1447 return; /* defer until we restart the engine following reset */
1449 if (execlists->tasklet.func == execlists_submission_tasklet)
1450 __execlists_submission_tasklet(engine);
1452 tasklet_hi_schedule(&execlists->tasklet);
1455 static void submit_queue(struct intel_engine_cs *engine,
1456 const struct i915_request *rq)
1458 struct intel_engine_execlists *execlists = &engine->execlists;
1460 if (rq_prio(rq) <= execlists->queue_priority_hint)
1463 execlists->queue_priority_hint = rq_prio(rq);
1464 __submit_queue_imm(engine);
1467 static void execlists_submit_request(struct i915_request *request)
1469 struct intel_engine_cs *engine = request->engine;
1470 unsigned long flags;
1472 /* Will be called from irq-context when using foreign fences. */
1473 spin_lock_irqsave(&engine->active.lock, flags);
1475 queue_request(engine, &request->sched, rq_prio(request));
1477 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1478 GEM_BUG_ON(list_empty(&request->sched.link));
1480 submit_queue(engine, request);
1482 spin_unlock_irqrestore(&engine->active.lock, flags);
1485 static void __execlists_context_fini(struct intel_context *ce)
1487 intel_ring_put(ce->ring);
1489 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1490 i915_gem_object_put(ce->state->obj);
1493 static void execlists_context_destroy(struct kref *kref)
1495 struct intel_context *ce = container_of(kref, typeof(*ce), ref);
1497 GEM_BUG_ON(!i915_active_is_idle(&ce->active));
1498 GEM_BUG_ON(intel_context_is_pinned(ce));
1501 __execlists_context_fini(ce);
1503 intel_context_free(ce);
1506 static void execlists_context_unpin(struct intel_context *ce)
1508 i915_gem_context_unpin_hw_id(ce->gem_context);
1509 i915_gem_object_unpin_map(ce->state->obj);
1513 __execlists_update_reg_state(struct intel_context *ce,
1514 struct intel_engine_cs *engine)
1516 struct intel_ring *ring = ce->ring;
1517 u32 *regs = ce->lrc_reg_state;
1519 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
1520 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
1522 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma);
1523 regs[CTX_RING_HEAD + 1] = ring->head;
1524 regs[CTX_RING_TAIL + 1] = ring->tail;
1527 if (engine->class == RENDER_CLASS)
1528 regs[CTX_R_PWR_CLK_STATE + 1] =
1529 intel_sseu_make_rpcs(engine->i915, &ce->sseu);
1533 __execlists_context_pin(struct intel_context *ce,
1534 struct intel_engine_cs *engine)
1539 GEM_BUG_ON(!ce->gem_context->vm);
1541 ret = execlists_context_deferred_alloc(ce, engine);
1544 GEM_BUG_ON(!ce->state);
1546 ret = intel_context_active_acquire(ce,
1547 engine->i915->ggtt.pin_bias |
1553 vaddr = i915_gem_object_pin_map(ce->state->obj,
1554 i915_coherent_map_type(engine->i915) |
1556 if (IS_ERR(vaddr)) {
1557 ret = PTR_ERR(vaddr);
1561 ret = i915_gem_context_pin_hw_id(ce->gem_context);
1565 ce->lrc_desc = lrc_descriptor(ce, engine);
1566 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1567 __execlists_update_reg_state(ce, engine);
1572 i915_gem_object_unpin_map(ce->state->obj);
1574 intel_context_active_release(ce);
1579 static int execlists_context_pin(struct intel_context *ce)
1581 return __execlists_context_pin(ce, ce->engine);
1584 static void execlists_context_reset(struct intel_context *ce)
1587 * Because we emit WA_TAIL_DWORDS there may be a disparity
1588 * between our bookkeeping in ce->ring->head and ce->ring->tail and
1589 * that stored in context. As we only write new commands from
1590 * ce->ring->tail onwards, everything before that is junk. If the GPU
1591 * starts reading from its RING_HEAD from the context, it may try to
1592 * execute that junk and die.
1594 * The contexts that are stilled pinned on resume belong to the
1595 * kernel, and are local to each engine. All other contexts will
1596 * have their head/tail sanitized upon pinning before use, so they
1597 * will never see garbage,
1599 * So to avoid that we reset the context images upon resume. For
1600 * simplicity, we just zero everything out.
1602 intel_ring_reset(ce->ring, 0);
1603 __execlists_update_reg_state(ce, ce->engine);
1606 static const struct intel_context_ops execlists_context_ops = {
1607 .pin = execlists_context_pin,
1608 .unpin = execlists_context_unpin,
1610 .enter = intel_context_enter_engine,
1611 .exit = intel_context_exit_engine,
1613 .reset = execlists_context_reset,
1614 .destroy = execlists_context_destroy,
1617 static int gen8_emit_init_breadcrumb(struct i915_request *rq)
1621 GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb);
1623 cs = intel_ring_begin(rq, 6);
1628 * Check if we have been preempted before we even get started.
1630 * After this point i915_request_started() reports true, even if
1631 * we get preempted and so are no longer running.
1633 *cs++ = MI_ARB_CHECK;
1636 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1637 *cs++ = rq->timeline->hwsp_offset;
1639 *cs++ = rq->fence.seqno - 1;
1641 intel_ring_advance(rq, cs);
1643 /* Record the updated position of the request's payload */
1644 rq->infix = intel_ring_offset(rq, cs);
1649 static int emit_pdps(struct i915_request *rq)
1651 const struct intel_engine_cs * const engine = rq->engine;
1652 struct i915_ppgtt * const ppgtt =
1653 i915_vm_to_ppgtt(rq->gem_context->vm);
1657 GEM_BUG_ON(intel_vgpu_active(rq->i915));
1660 * Beware ye of the dragons, this sequence is magic!
1662 * Small changes to this sequence can cause anything from
1663 * GPU hangs to forcewake errors and machine lockups!
1666 /* Flush any residual operations from the context load */
1667 err = engine->emit_flush(rq, EMIT_FLUSH);
1671 /* Magic required to prevent forcewake errors! */
1672 err = engine->emit_flush(rq, EMIT_INVALIDATE);
1676 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
1680 /* Ensure the LRI have landed before we invalidate & continue */
1681 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
1682 for (i = GEN8_3LVL_PDPES; i--; ) {
1683 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1684 u32 base = engine->mmio_base;
1686 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
1687 *cs++ = upper_32_bits(pd_daddr);
1688 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
1689 *cs++ = lower_32_bits(pd_daddr);
1693 intel_ring_advance(rq, cs);
1695 /* Be doubly sure the LRI have landed before proceeding */
1696 err = engine->emit_flush(rq, EMIT_FLUSH);
1700 /* Re-invalidate the TLB for luck */
1701 return engine->emit_flush(rq, EMIT_INVALIDATE);
1704 static int execlists_request_alloc(struct i915_request *request)
1708 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context));
1711 * Flush enough space to reduce the likelihood of waiting after
1712 * we start building the request - in which case we will just
1713 * have to repeat work.
1715 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1718 * Note that after this point, we have committed to using
1719 * this request as it is being used to both track the
1720 * state of engine initialisation and liveness of the
1721 * golden renderstate above. Think twice before you try
1722 * to cancel/unwind this request now.
1725 /* Unconditionally invalidate GPU caches and TLBs. */
1726 if (i915_vm_is_4lvl(request->gem_context->vm))
1727 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
1729 ret = emit_pdps(request);
1733 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1738 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1739 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1740 * but there is a slight complication as this is applied in WA batch where the
1741 * values are only initialized once so we cannot take register value at the
1742 * beginning and reuse it further; hence we save its value to memory, upload a
1743 * constant value with bit21 set and then we restore it back with the saved value.
1744 * To simplify the WA, a constant value is formed by using the default value
1745 * of this register. This shouldn't be a problem because we are only modifying
1746 * it for a short period and this batch in non-premptible. We can ofcourse
1747 * use additional instructions that read the actual value of the register
1748 * at that time and set our bit of interest but it makes the WA complicated.
1750 * This WA is also required for Gen9 so extracting as a function avoids
1754 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1756 /* NB no one else is allowed to scribble over scratch + 256! */
1757 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1758 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1759 *batch++ = i915_scratch_offset(engine->i915) + 256;
1762 *batch++ = MI_LOAD_REGISTER_IMM(1);
1763 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1764 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1766 batch = gen8_emit_pipe_control(batch,
1767 PIPE_CONTROL_CS_STALL |
1768 PIPE_CONTROL_DC_FLUSH_ENABLE,
1771 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1772 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1773 *batch++ = i915_scratch_offset(engine->i915) + 256;
1780 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1781 * initialized at the beginning and shared across all contexts but this field
1782 * helps us to have multiple batches at different offsets and select them based
1783 * on a criteria. At the moment this batch always start at the beginning of the page
1784 * and at this point we don't have multiple wa_ctx batch buffers.
1786 * The number of WA applied are not known at the beginning; we use this field
1787 * to return the no of DWORDS written.
1789 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1790 * so it adds NOOPs as padding to make it cacheline aligned.
1791 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1792 * makes a complete batch buffer.
1794 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1796 /* WaDisableCtxRestoreArbitration:bdw,chv */
1797 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1799 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1800 if (IS_BROADWELL(engine->i915))
1801 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1803 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1804 /* Actual scratch location is at 128 bytes offset */
1805 batch = gen8_emit_pipe_control(batch,
1806 PIPE_CONTROL_FLUSH_L3 |
1807 PIPE_CONTROL_GLOBAL_GTT_IVB |
1808 PIPE_CONTROL_CS_STALL |
1809 PIPE_CONTROL_QW_WRITE,
1810 i915_scratch_offset(engine->i915) +
1811 2 * CACHELINE_BYTES);
1813 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1815 /* Pad to end of cacheline */
1816 while ((unsigned long)batch % CACHELINE_BYTES)
1820 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1821 * execution depends on the length specified in terms of cache lines
1822 * in the register CTX_RCS_INDIRECT_CTX
1833 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1835 GEM_BUG_ON(!count || count > 63);
1837 *batch++ = MI_LOAD_REGISTER_IMM(count);
1839 *batch++ = i915_mmio_reg_offset(lri->reg);
1840 *batch++ = lri->value;
1841 } while (lri++, --count);
1847 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1849 static const struct lri lri[] = {
1850 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1852 COMMON_SLICE_CHICKEN2,
1853 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1860 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1861 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1867 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1868 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1872 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1874 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1875 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1877 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1879 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1880 if (HAS_POOLED_EU(engine->i915)) {
1882 * EU pool configuration is setup along with golden context
1883 * during context initialization. This value depends on
1884 * device type (2x6 or 3x6) and needs to be updated based
1885 * on which subslice is disabled especially for 2x6
1886 * devices, however it is safe to load default
1887 * configuration of 3x6 device instead of masking off
1888 * corresponding bits because HW ignores bits of a disabled
1889 * subslice and drops down to appropriate config. Please
1890 * see render_state_setup() in i915_gem_render_state.c for
1891 * possible configurations, to avoid duplication they are
1892 * not shown here again.
1894 *batch++ = GEN9_MEDIA_POOL_STATE;
1895 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1896 *batch++ = 0x00777000;
1902 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1904 /* Pad to end of cacheline */
1905 while ((unsigned long)batch % CACHELINE_BYTES)
1912 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1917 * WaPipeControlBefore3DStateSamplePattern: cnl
1919 * Ensure the engine is idle prior to programming a
1920 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1922 batch = gen8_emit_pipe_control(batch,
1923 PIPE_CONTROL_CS_STALL,
1926 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1927 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1928 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1929 * confusing. Since gen8_emit_pipe_control() already advances the
1930 * batch by 6 dwords, we advance the other 10 here, completing a
1931 * cacheline. It's not clear if the workaround requires this padding
1932 * before other commands, or if it's just the regular padding we would
1933 * already have for the workaround bb, so leave it here for now.
1935 for (i = 0; i < 10; i++)
1938 /* Pad to end of cacheline */
1939 while ((unsigned long)batch % CACHELINE_BYTES)
1945 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1947 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1949 struct drm_i915_gem_object *obj;
1950 struct i915_vma *vma;
1953 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_OBJ_SIZE);
1955 return PTR_ERR(obj);
1957 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1963 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1967 engine->wa_ctx.vma = vma;
1971 i915_gem_object_put(obj);
1975 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1977 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1980 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1982 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1984 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1985 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1987 wa_bb_func_t wa_bb_fn[2];
1989 void *batch, *batch_ptr;
1993 if (engine->class != RENDER_CLASS)
1996 switch (INTEL_GEN(engine->i915)) {
2000 wa_bb_fn[0] = gen10_init_indirectctx_bb;
2004 wa_bb_fn[0] = gen9_init_indirectctx_bb;
2008 wa_bb_fn[0] = gen8_init_indirectctx_bb;
2012 MISSING_CASE(INTEL_GEN(engine->i915));
2016 ret = lrc_setup_wa_ctx(engine);
2018 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
2022 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
2023 batch = batch_ptr = kmap_atomic(page);
2026 * Emit the two workaround batch buffers, recording the offset from the
2027 * start of the workaround batch buffer object for each and their
2030 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
2031 wa_bb[i]->offset = batch_ptr - batch;
2032 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
2033 CACHELINE_BYTES))) {
2038 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
2039 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
2042 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
2044 kunmap_atomic(batch);
2046 lrc_destroy_wa_ctx(engine);
2051 static void enable_execlists(struct intel_engine_cs *engine)
2053 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
2055 if (INTEL_GEN(engine->i915) >= 11)
2056 ENGINE_WRITE(engine,
2058 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
2060 ENGINE_WRITE(engine,
2062 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
2064 ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
2066 ENGINE_WRITE(engine,
2068 i915_ggtt_offset(engine->status_page.vma));
2069 ENGINE_POSTING_READ(engine, RING_HWS_PGA);
2072 static bool unexpected_starting_state(struct intel_engine_cs *engine)
2074 bool unexpected = false;
2076 if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
2077 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
2084 static int execlists_resume(struct intel_engine_cs *engine)
2086 intel_engine_apply_workarounds(engine);
2087 intel_engine_apply_whitelist(engine);
2089 intel_mocs_init_engine(engine);
2091 intel_engine_reset_breadcrumbs(engine);
2093 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
2094 struct drm_printer p = drm_debug_printer(__func__);
2096 intel_engine_dump(engine, &p, NULL);
2099 enable_execlists(engine);
2104 static void execlists_reset_prepare(struct intel_engine_cs *engine)
2106 struct intel_engine_execlists * const execlists = &engine->execlists;
2107 unsigned long flags;
2109 GEM_TRACE("%s: depth<-%d\n", engine->name,
2110 atomic_read(&execlists->tasklet.count));
2113 * Prevent request submission to the hardware until we have
2114 * completed the reset in i915_gem_reset_finish(). If a request
2115 * is completed by one engine, it may then queue a request
2116 * to a second via its execlists->tasklet *just* as we are
2117 * calling engine->resume() and also writing the ELSP.
2118 * Turning off the execlists->tasklet until the reset is over
2119 * prevents the race.
2121 __tasklet_disable_sync_once(&execlists->tasklet);
2122 GEM_BUG_ON(!reset_in_progress(execlists));
2124 intel_engine_stop_cs(engine);
2126 /* And flush any current direct submission. */
2127 spin_lock_irqsave(&engine->active.lock, flags);
2128 spin_unlock_irqrestore(&engine->active.lock, flags);
2131 static void reset_csb_pointers(struct intel_engine_cs *engine)
2133 struct intel_engine_execlists * const execlists = &engine->execlists;
2134 const unsigned int reset_value = execlists->csb_size - 1;
2136 ring_set_paused(engine, 0);
2139 * After a reset, the HW starts writing into CSB entry [0]. We
2140 * therefore have to set our HEAD pointer back one entry so that
2141 * the *first* entry we check is entry 0. To complicate this further,
2142 * as we don't wait for the first interrupt after reset, we have to
2143 * fake the HW write to point back to the last entry so that our
2144 * inline comparison of our cached head position against the last HW
2145 * write works even before the first interrupt.
2147 execlists->csb_head = reset_value;
2148 WRITE_ONCE(*execlists->csb_write, reset_value);
2149 wmb(); /* Make sure this is visible to HW (paranoia?) */
2151 invalidate_csb_entries(&execlists->csb_status[0],
2152 &execlists->csb_status[reset_value]);
2155 static struct i915_request *active_request(struct i915_request *rq)
2157 const struct list_head * const list = &rq->engine->active.requests;
2158 const struct intel_context * const context = rq->hw_context;
2159 struct i915_request *active = NULL;
2161 list_for_each_entry_from_reverse(rq, list, sched.link) {
2162 if (i915_request_completed(rq))
2165 if (rq->hw_context != context)
2174 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
2176 struct intel_engine_execlists * const execlists = &engine->execlists;
2177 struct intel_context *ce;
2178 struct i915_request *rq;
2181 process_csb(engine); /* drain preemption events */
2183 /* Following the reset, we need to reload the CSB read/write pointers */
2184 reset_csb_pointers(engine);
2187 * Save the currently executing context, even if we completed
2188 * its request, it was still running at the time of the
2189 * reset and will have been clobbered.
2191 rq = execlists_active(execlists);
2195 ce = rq->hw_context;
2196 GEM_BUG_ON(i915_active_is_idle(&ce->active));
2197 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
2198 rq = active_request(rq);
2201 * Catch up with any missed context-switch interrupts.
2203 * Ideally we would just read the remaining CSB entries now that we
2204 * know the gpu is idle. However, the CSB registers are sometimes^W
2205 * often trashed across a GPU reset! Instead we have to rely on
2206 * guessing the missed context-switch events by looking at what
2207 * requests were completed.
2209 execlists_cancel_port_requests(execlists);
2212 ce->ring->head = ce->ring->tail;
2216 ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
2219 * If this request hasn't started yet, e.g. it is waiting on a
2220 * semaphore, we need to avoid skipping the request or else we
2221 * break the signaling chain. However, if the context is corrupt
2222 * the request will not restart and we will be stuck with a wedged
2223 * device. It is quite often the case that if we issue a reset
2224 * while the GPU is loading the context image, that the context
2225 * image becomes corrupt.
2227 * Otherwise, if we have not started yet, the request should replay
2228 * perfectly and we do not need to flag the result as being erroneous.
2230 if (!i915_request_started(rq))
2234 * If the request was innocent, we leave the request in the ELSP
2235 * and will try to replay it on restarting. The context image may
2236 * have been corrupted by the reset, in which case we may have
2237 * to service a new GPU hang, but more likely we can continue on
2240 * If the request was guilty, we presume the context is corrupt
2241 * and have to at least restore the RING register in the context
2242 * image back to the expected values to skip over the guilty request.
2244 i915_reset_request(rq, stalled);
2249 * We want a simple context + ring to execute the breadcrumb update.
2250 * We cannot rely on the context being intact across the GPU hang,
2251 * so clear it and rebuild just what we need for the breadcrumb.
2252 * All pending requests for this context will be zapped, and any
2253 * future request will be after userspace has had the opportunity
2254 * to recreate its own state.
2256 regs = ce->lrc_reg_state;
2257 if (engine->pinned_default_state) {
2258 memcpy(regs, /* skip restoring the vanilla PPHWSP */
2259 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
2260 engine->context_size - PAGE_SIZE);
2262 execlists_init_reg_state(regs, ce, engine, ce->ring);
2265 GEM_TRACE("%s replay {head:%04x, tail:%04x\n",
2266 engine->name, ce->ring->head, ce->ring->tail);
2267 intel_ring_update_space(ce->ring);
2268 __execlists_update_reg_state(ce, engine);
2270 /* Push back any incomplete requests for replay after the reset. */
2271 __unwind_incomplete_requests(engine);
2274 static void execlists_reset(struct intel_engine_cs *engine, bool stalled)
2276 unsigned long flags;
2278 GEM_TRACE("%s\n", engine->name);
2280 spin_lock_irqsave(&engine->active.lock, flags);
2282 __execlists_reset(engine, stalled);
2284 spin_unlock_irqrestore(&engine->active.lock, flags);
2287 static void nop_submission_tasklet(unsigned long data)
2289 /* The driver is wedged; don't process any more events. */
2292 static void execlists_cancel_requests(struct intel_engine_cs *engine)
2294 struct intel_engine_execlists * const execlists = &engine->execlists;
2295 struct i915_request *rq, *rn;
2297 unsigned long flags;
2299 GEM_TRACE("%s\n", engine->name);
2302 * Before we call engine->cancel_requests(), we should have exclusive
2303 * access to the submission state. This is arranged for us by the
2304 * caller disabling the interrupt generation, the tasklet and other
2305 * threads that may then access the same state, giving us a free hand
2306 * to reset state. However, we still need to let lockdep be aware that
2307 * we know this state may be accessed in hardirq context, so we
2308 * disable the irq around this manipulation and we want to keep
2309 * the spinlock focused on its duties and not accidentally conflate
2310 * coverage to the submission's irq state. (Similarly, although we
2311 * shouldn't need to disable irq around the manipulation of the
2312 * submission's irq state, we also wish to remind ourselves that
2315 spin_lock_irqsave(&engine->active.lock, flags);
2317 __execlists_reset(engine, true);
2319 /* Mark all executing requests as skipped. */
2320 list_for_each_entry(rq, &engine->active.requests, sched.link) {
2321 if (!i915_request_signaled(rq))
2322 dma_fence_set_error(&rq->fence, -EIO);
2324 i915_request_mark_complete(rq);
2327 /* Flush the queued requests to the timeline list (for retiring). */
2328 while ((rb = rb_first_cached(&execlists->queue))) {
2329 struct i915_priolist *p = to_priolist(rb);
2332 priolist_for_each_request_consume(rq, rn, p, i) {
2333 list_del_init(&rq->sched.link);
2334 __i915_request_submit(rq);
2335 dma_fence_set_error(&rq->fence, -EIO);
2336 i915_request_mark_complete(rq);
2339 rb_erase_cached(&p->node, &execlists->queue);
2340 i915_priolist_free(p);
2343 /* Cancel all attached virtual engines */
2344 while ((rb = rb_first_cached(&execlists->virtual))) {
2345 struct virtual_engine *ve =
2346 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
2348 rb_erase_cached(rb, &execlists->virtual);
2351 spin_lock(&ve->base.active.lock);
2353 ve->request->engine = engine;
2354 __i915_request_submit(ve->request);
2355 dma_fence_set_error(&ve->request->fence, -EIO);
2356 i915_request_mark_complete(ve->request);
2357 ve->base.execlists.queue_priority_hint = INT_MIN;
2360 spin_unlock(&ve->base.active.lock);
2363 /* Remaining _unready_ requests will be nop'ed when submitted */
2365 execlists->queue_priority_hint = INT_MIN;
2366 execlists->queue = RB_ROOT_CACHED;
2368 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
2369 execlists->tasklet.func = nop_submission_tasklet;
2371 spin_unlock_irqrestore(&engine->active.lock, flags);
2374 static void execlists_reset_finish(struct intel_engine_cs *engine)
2376 struct intel_engine_execlists * const execlists = &engine->execlists;
2379 * After a GPU reset, we may have requests to replay. Do so now while
2380 * we still have the forcewake to be sure that the GPU is not allowed
2381 * to sleep before we restart and reload a context.
2383 GEM_BUG_ON(!reset_in_progress(execlists));
2384 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
2385 execlists->tasklet.func(execlists->tasklet.data);
2387 if (__tasklet_enable(&execlists->tasklet))
2388 /* And kick in case we missed a new request submission. */
2389 tasklet_hi_schedule(&execlists->tasklet);
2390 GEM_TRACE("%s: depth->%d\n", engine->name,
2391 atomic_read(&execlists->tasklet.count));
2394 static int gen8_emit_bb_start(struct i915_request *rq,
2395 u64 offset, u32 len,
2396 const unsigned int flags)
2400 cs = intel_ring_begin(rq, 4);
2405 * WaDisableCtxRestoreArbitration:bdw,chv
2407 * We don't need to perform MI_ARB_ENABLE as often as we do (in
2408 * particular all the gen that do not need the w/a at all!), if we
2409 * took care to make sure that on every switch into this context
2410 * (both ordinary and for preemption) that arbitrartion was enabled
2411 * we would be fine. However, for gen8 there is another w/a that
2412 * requires us to not preempt inside GPGPU execution, so we keep
2413 * arbitration disabled for gen8 batches. Arbitration will be
2414 * re-enabled before we close the request
2415 * (engine->emit_fini_breadcrumb).
2417 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2419 /* FIXME(BDW+): Address space and security selectors. */
2420 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2421 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
2422 *cs++ = lower_32_bits(offset);
2423 *cs++ = upper_32_bits(offset);
2425 intel_ring_advance(rq, cs);
2430 static int gen9_emit_bb_start(struct i915_request *rq,
2431 u64 offset, u32 len,
2432 const unsigned int flags)
2436 cs = intel_ring_begin(rq, 6);
2440 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2442 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2443 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
2444 *cs++ = lower_32_bits(offset);
2445 *cs++ = upper_32_bits(offset);
2447 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2450 intel_ring_advance(rq, cs);
2455 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
2457 ENGINE_WRITE(engine, RING_IMR,
2458 ~(engine->irq_enable_mask | engine->irq_keep_mask));
2459 ENGINE_POSTING_READ(engine, RING_IMR);
2462 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
2464 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
2467 static int gen8_emit_flush(struct i915_request *request, u32 mode)
2471 cs = intel_ring_begin(request, 4);
2475 cmd = MI_FLUSH_DW + 1;
2477 /* We always require a command barrier so that subsequent
2478 * commands, such as breadcrumb interrupts, are strictly ordered
2479 * wrt the contents of the write cache being flushed to memory
2480 * (and thus being coherent from the CPU).
2482 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2484 if (mode & EMIT_INVALIDATE) {
2485 cmd |= MI_INVALIDATE_TLB;
2486 if (request->engine->class == VIDEO_DECODE_CLASS)
2487 cmd |= MI_INVALIDATE_BSD;
2491 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2492 *cs++ = 0; /* upper addr */
2493 *cs++ = 0; /* value */
2494 intel_ring_advance(request, cs);
2499 static int gen8_emit_flush_render(struct i915_request *request,
2502 struct intel_engine_cs *engine = request->engine;
2504 i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
2505 bool vf_flush_wa = false, dc_flush_wa = false;
2509 flags |= PIPE_CONTROL_CS_STALL;
2511 if (mode & EMIT_FLUSH) {
2512 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
2513 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
2514 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
2515 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2518 if (mode & EMIT_INVALIDATE) {
2519 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2520 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2521 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2522 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2523 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2524 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2525 flags |= PIPE_CONTROL_QW_WRITE;
2526 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2529 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
2532 if (IS_GEN(request->i915, 9))
2535 /* WaForGAMHang:kbl */
2536 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2548 cs = intel_ring_begin(request, len);
2553 cs = gen8_emit_pipe_control(cs, 0, 0);
2556 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2559 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2562 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2564 intel_ring_advance(request, cs);
2570 * Reserve space for 2 NOOPs at the end of each request to be
2571 * used as a workaround for not being allowed to do lite
2572 * restore with HEAD==TAIL (WaIdleLiteRestore).
2574 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2576 /* Ensure there's always at least one preemption point per-request. */
2577 *cs++ = MI_ARB_CHECK;
2579 request->wa_tail = intel_ring_offset(request, cs);
2584 static u32 *emit_preempt_busywait(struct i915_request *request, u32 *cs)
2586 *cs++ = MI_SEMAPHORE_WAIT |
2587 MI_SEMAPHORE_GLOBAL_GTT |
2589 MI_SEMAPHORE_SAD_EQ_SDD;
2591 *cs++ = intel_hws_preempt_address(request->engine);
2597 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
2599 cs = gen8_emit_ggtt_write(cs,
2600 request->fence.seqno,
2601 request->timeline->hwsp_offset,
2603 *cs++ = MI_USER_INTERRUPT;
2605 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2606 cs = emit_preempt_busywait(request, cs);
2608 request->tail = intel_ring_offset(request, cs);
2609 assert_ring_tail_valid(request->ring, request->tail);
2611 return gen8_emit_wa_tail(request, cs);
2614 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2616 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
2617 cs = gen8_emit_ggtt_write_rcs(cs,
2618 request->fence.seqno,
2619 request->timeline->hwsp_offset,
2620 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
2621 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
2622 PIPE_CONTROL_DC_FLUSH_ENABLE);
2623 cs = gen8_emit_pipe_control(cs,
2624 PIPE_CONTROL_FLUSH_ENABLE |
2625 PIPE_CONTROL_CS_STALL,
2627 *cs++ = MI_USER_INTERRUPT;
2629 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2630 cs = emit_preempt_busywait(request, cs);
2632 request->tail = intel_ring_offset(request, cs);
2633 assert_ring_tail_valid(request->ring, request->tail);
2635 return gen8_emit_wa_tail(request, cs);
2638 static int gen8_init_rcs_context(struct i915_request *rq)
2642 ret = intel_engine_emit_ctx_wa(rq);
2646 ret = intel_rcs_context_init_mocs(rq);
2648 * Failing to program the MOCS is non-fatal.The system will not
2649 * run at peak performance. So generate an error and carry on.
2652 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2654 return i915_gem_render_state_emit(rq);
2657 static void execlists_park(struct intel_engine_cs *engine)
2659 del_timer_sync(&engine->execlists.timer);
2660 intel_engine_park(engine);
2663 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
2665 engine->submit_request = execlists_submit_request;
2666 engine->cancel_requests = execlists_cancel_requests;
2667 engine->schedule = i915_schedule;
2668 engine->execlists.tasklet.func = execlists_submission_tasklet;
2670 engine->reset.prepare = execlists_reset_prepare;
2671 engine->reset.reset = execlists_reset;
2672 engine->reset.finish = execlists_reset_finish;
2674 engine->park = execlists_park;
2675 engine->unpark = NULL;
2677 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2678 if (!intel_vgpu_active(engine->i915))
2679 engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
2680 if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
2681 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
2684 static void execlists_destroy(struct intel_engine_cs *engine)
2686 intel_engine_cleanup_common(engine);
2687 lrc_destroy_wa_ctx(engine);
2692 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2694 /* Default vfuncs which can be overriden by each engine. */
2696 engine->destroy = execlists_destroy;
2697 engine->resume = execlists_resume;
2699 engine->reset.prepare = execlists_reset_prepare;
2700 engine->reset.reset = execlists_reset;
2701 engine->reset.finish = execlists_reset_finish;
2703 engine->cops = &execlists_context_ops;
2704 engine->request_alloc = execlists_request_alloc;
2706 engine->emit_flush = gen8_emit_flush;
2707 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
2708 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
2710 engine->set_default_submission = intel_execlists_set_default_submission;
2712 if (INTEL_GEN(engine->i915) < 11) {
2713 engine->irq_enable = gen8_logical_ring_enable_irq;
2714 engine->irq_disable = gen8_logical_ring_disable_irq;
2717 * TODO: On Gen11 interrupt masks need to be clear
2718 * to allow C6 entry. Keep interrupts enabled at
2719 * and take the hit of generating extra interrupts
2720 * until a more refined solution exists.
2723 if (IS_GEN(engine->i915, 8))
2724 engine->emit_bb_start = gen8_emit_bb_start;
2726 engine->emit_bb_start = gen9_emit_bb_start;
2730 logical_ring_default_irqs(struct intel_engine_cs *engine)
2732 unsigned int shift = 0;
2734 if (INTEL_GEN(engine->i915) < 11) {
2735 const u8 irq_shifts[] = {
2736 [RCS0] = GEN8_RCS_IRQ_SHIFT,
2737 [BCS0] = GEN8_BCS_IRQ_SHIFT,
2738 [VCS0] = GEN8_VCS0_IRQ_SHIFT,
2739 [VCS1] = GEN8_VCS1_IRQ_SHIFT,
2740 [VECS0] = GEN8_VECS_IRQ_SHIFT,
2743 shift = irq_shifts[engine->id];
2746 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2747 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2750 int intel_execlists_submission_setup(struct intel_engine_cs *engine)
2752 /* Intentionally left blank. */
2753 engine->buffer = NULL;
2755 tasklet_init(&engine->execlists.tasklet,
2756 execlists_submission_tasklet, (unsigned long)engine);
2757 timer_setup(&engine->execlists.timer, execlists_submission_timer, 0);
2759 logical_ring_default_vfuncs(engine);
2760 logical_ring_default_irqs(engine);
2762 if (engine->class == RENDER_CLASS) {
2763 engine->init_context = gen8_init_rcs_context;
2764 engine->emit_flush = gen8_emit_flush_render;
2765 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
2771 int intel_execlists_submission_init(struct intel_engine_cs *engine)
2773 struct intel_engine_execlists * const execlists = &engine->execlists;
2774 struct drm_i915_private *i915 = engine->i915;
2775 struct intel_uncore *uncore = engine->uncore;
2776 u32 base = engine->mmio_base;
2779 ret = intel_engine_init_common(engine);
2783 intel_engine_init_workarounds(engine);
2784 intel_engine_init_whitelist(engine);
2786 if (intel_init_workaround_bb(engine))
2788 * We continue even if we fail to initialize WA batch
2789 * because we only expect rare glitches but nothing
2790 * critical to prevent us from using GPU
2792 DRM_ERROR("WA batch buffer initialization failed\n");
2794 if (HAS_LOGICAL_RING_ELSQ(i915)) {
2795 execlists->submit_reg = uncore->regs +
2796 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
2797 execlists->ctrl_reg = uncore->regs +
2798 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
2800 execlists->submit_reg = uncore->regs +
2801 i915_mmio_reg_offset(RING_ELSP(base));
2804 execlists->csb_status =
2805 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
2807 execlists->csb_write =
2808 &engine->status_page.addr[intel_hws_csb_write_index(i915)];
2810 if (INTEL_GEN(i915) < 11)
2811 execlists->csb_size = GEN8_CSB_ENTRIES;
2813 execlists->csb_size = GEN11_CSB_ENTRIES;
2815 reset_csb_pointers(engine);
2820 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2822 u32 indirect_ctx_offset;
2824 switch (INTEL_GEN(engine->i915)) {
2826 MISSING_CASE(INTEL_GEN(engine->i915));
2829 indirect_ctx_offset =
2830 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2833 indirect_ctx_offset =
2834 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2837 indirect_ctx_offset =
2838 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2841 indirect_ctx_offset =
2842 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2846 return indirect_ctx_offset;
2849 static void execlists_init_reg_state(u32 *regs,
2850 struct intel_context *ce,
2851 struct intel_engine_cs *engine,
2852 struct intel_ring *ring)
2854 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->gem_context->vm);
2855 bool rcs = engine->class == RENDER_CLASS;
2856 u32 base = engine->mmio_base;
2859 * A context is actually a big batch buffer with several
2860 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2861 * values we are setting here are only for the first context restore:
2862 * on a subsequent save, the GPU will recreate this batchbuffer with new
2863 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2864 * we are not initializing here).
2866 * Must keep consistent with virtual_update_register_offsets().
2868 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2869 MI_LRI_FORCE_POSTED;
2871 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
2872 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
2873 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
2874 if (INTEL_GEN(engine->i915) < 11) {
2875 regs[CTX_CONTEXT_CONTROL + 1] |=
2876 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
2877 CTX_CTRL_RS_CTX_ENABLE);
2879 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2880 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2881 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2882 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2883 RING_CTL_SIZE(ring->size) | RING_VALID);
2884 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2885 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2886 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2887 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2888 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2889 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2891 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2893 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2894 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2895 RING_INDIRECT_CTX_OFFSET(base), 0);
2896 if (wa_ctx->indirect_ctx.size) {
2897 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2899 regs[CTX_RCS_INDIRECT_CTX + 1] =
2900 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2901 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2903 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2904 intel_lr_indirect_ctx_offset(engine) << 6;
2907 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2908 if (wa_ctx->per_ctx.size) {
2909 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2911 regs[CTX_BB_PER_CTX_PTR + 1] =
2912 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2916 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2918 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2919 /* PDP values well be assigned later if needed */
2920 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
2921 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
2922 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0);
2923 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0);
2924 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0);
2925 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0);
2926 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0);
2927 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0);
2929 if (i915_vm_is_4lvl(&ppgtt->vm)) {
2930 /* 64b PPGTT (48bit canonical)
2931 * PDP0_DESCRIPTOR contains the base address to PML4 and
2932 * other PDP Descriptors are ignored.
2934 ASSIGN_CTX_PML4(ppgtt, regs);
2936 ASSIGN_CTX_PDP(ppgtt, regs, 3);
2937 ASSIGN_CTX_PDP(ppgtt, regs, 2);
2938 ASSIGN_CTX_PDP(ppgtt, regs, 1);
2939 ASSIGN_CTX_PDP(ppgtt, regs, 0);
2943 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2944 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
2946 i915_oa_init_reg_state(engine, ce, regs);
2949 regs[CTX_END] = MI_BATCH_BUFFER_END;
2950 if (INTEL_GEN(engine->i915) >= 10)
2951 regs[CTX_END] |= BIT(0);
2955 populate_lr_context(struct intel_context *ce,
2956 struct drm_i915_gem_object *ctx_obj,
2957 struct intel_engine_cs *engine,
2958 struct intel_ring *ring)
2964 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2965 if (IS_ERR(vaddr)) {
2966 ret = PTR_ERR(vaddr);
2967 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2971 if (engine->default_state) {
2973 * We only want to copy over the template context state;
2974 * skipping over the headers reserved for GuC communication,
2975 * leaving those as zero.
2977 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2980 defaults = i915_gem_object_pin_map(engine->default_state,
2982 if (IS_ERR(defaults)) {
2983 ret = PTR_ERR(defaults);
2987 memcpy(vaddr + start, defaults + start, engine->context_size);
2988 i915_gem_object_unpin_map(engine->default_state);
2991 /* The second page of the context object contains some fields which must
2992 * be set up prior to the first execution. */
2993 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2994 execlists_init_reg_state(regs, ce, engine, ring);
2995 if (!engine->default_state)
2996 regs[CTX_CONTEXT_CONTROL + 1] |=
2997 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
3001 __i915_gem_object_flush_map(ctx_obj,
3002 LRC_HEADER_PAGES * PAGE_SIZE,
3003 engine->context_size);
3004 i915_gem_object_unpin_map(ctx_obj);
3008 static struct i915_timeline *
3009 get_timeline(struct i915_gem_context *ctx, struct intel_gt *gt)
3012 return i915_timeline_get(ctx->timeline);
3014 return i915_timeline_create(gt, NULL);
3017 static int execlists_context_deferred_alloc(struct intel_context *ce,
3018 struct intel_engine_cs *engine)
3020 struct drm_i915_gem_object *ctx_obj;
3021 struct i915_vma *vma;
3023 struct intel_ring *ring;
3024 struct i915_timeline *timeline;
3030 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
3033 * Before the actual start of the context image, we insert a few pages
3034 * for our own use and for sharing with the GuC.
3036 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
3038 ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
3039 if (IS_ERR(ctx_obj))
3040 return PTR_ERR(ctx_obj);
3042 vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
3045 goto error_deref_obj;
3048 timeline = get_timeline(ce->gem_context, engine->gt);
3049 if (IS_ERR(timeline)) {
3050 ret = PTR_ERR(timeline);
3051 goto error_deref_obj;
3054 ring = intel_engine_create_ring(engine,
3056 ce->gem_context->ring_size);
3057 i915_timeline_put(timeline);
3059 ret = PTR_ERR(ring);
3060 goto error_deref_obj;
3063 ret = populate_lr_context(ce, ctx_obj, engine, ring);
3065 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
3066 goto error_ring_free;
3075 intel_ring_put(ring);
3077 i915_gem_object_put(ctx_obj);
3081 static struct list_head *virtual_queue(struct virtual_engine *ve)
3083 return &ve->base.execlists.default_priolist.requests[0];
3086 static void virtual_context_destroy(struct kref *kref)
3088 struct virtual_engine *ve =
3089 container_of(kref, typeof(*ve), context.ref);
3092 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
3093 GEM_BUG_ON(ve->request);
3094 GEM_BUG_ON(ve->context.inflight);
3096 for (n = 0; n < ve->num_siblings; n++) {
3097 struct intel_engine_cs *sibling = ve->siblings[n];
3098 struct rb_node *node = &ve->nodes[sibling->id].rb;
3100 if (RB_EMPTY_NODE(node))
3103 spin_lock_irq(&sibling->active.lock);
3105 /* Detachment is lazily performed in the execlists tasklet */
3106 if (!RB_EMPTY_NODE(node))
3107 rb_erase_cached(node, &sibling->execlists.virtual);
3109 spin_unlock_irq(&sibling->active.lock);
3111 GEM_BUG_ON(__tasklet_is_scheduled(&ve->base.execlists.tasklet));
3113 if (ve->context.state)
3114 __execlists_context_fini(&ve->context);
3120 static void virtual_engine_initial_hint(struct virtual_engine *ve)
3125 * Pick a random sibling on starting to help spread the load around.
3127 * New contexts are typically created with exactly the same order
3128 * of siblings, and often started in batches. Due to the way we iterate
3129 * the array of sibling when submitting requests, sibling[0] is
3130 * prioritised for dequeuing. If we make sure that sibling[0] is fairly
3131 * randomised across the system, we also help spread the load by the
3132 * first engine we inspect being different each time.
3134 * NB This does not force us to execute on this engine, it will just
3135 * typically be the first we inspect for submission.
3137 swp = prandom_u32_max(ve->num_siblings);
3141 swap(ve->siblings[swp], ve->siblings[0]);
3142 virtual_update_register_offsets(ve->context.lrc_reg_state,
3146 static int virtual_context_pin(struct intel_context *ce)
3148 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3151 /* Note: we must use a real engine class for setting up reg state */
3152 err = __execlists_context_pin(ce, ve->siblings[0]);
3156 virtual_engine_initial_hint(ve);
3160 static void virtual_context_enter(struct intel_context *ce)
3162 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3165 for (n = 0; n < ve->num_siblings; n++)
3166 intel_engine_pm_get(ve->siblings[n]);
3169 static void virtual_context_exit(struct intel_context *ce)
3171 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3174 for (n = 0; n < ve->num_siblings; n++)
3175 intel_engine_pm_put(ve->siblings[n]);
3178 static const struct intel_context_ops virtual_context_ops = {
3179 .pin = virtual_context_pin,
3180 .unpin = execlists_context_unpin,
3182 .enter = virtual_context_enter,
3183 .exit = virtual_context_exit,
3185 .destroy = virtual_context_destroy,
3188 static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve)
3190 struct i915_request *rq;
3191 intel_engine_mask_t mask;
3193 rq = READ_ONCE(ve->request);
3197 /* The rq is ready for submission; rq->execution_mask is now stable. */
3198 mask = rq->execution_mask;
3199 if (unlikely(!mask)) {
3200 /* Invalid selection, submit to a random engine in error */
3201 i915_request_skip(rq, -ENODEV);
3202 mask = ve->siblings[0]->mask;
3205 GEM_TRACE("%s: rq=%llx:%lld, mask=%x, prio=%d\n",
3207 rq->fence.context, rq->fence.seqno,
3208 mask, ve->base.execlists.queue_priority_hint);
3213 static void virtual_submission_tasklet(unsigned long data)
3215 struct virtual_engine * const ve = (struct virtual_engine *)data;
3216 const int prio = ve->base.execlists.queue_priority_hint;
3217 intel_engine_mask_t mask;
3221 mask = virtual_submission_mask(ve);
3223 if (unlikely(!mask))
3226 local_irq_disable();
3227 for (n = 0; READ_ONCE(ve->request) && n < ve->num_siblings; n++) {
3228 struct intel_engine_cs *sibling = ve->siblings[n];
3229 struct ve_node * const node = &ve->nodes[sibling->id];
3230 struct rb_node **parent, *rb;
3233 if (unlikely(!(mask & sibling->mask))) {
3234 if (!RB_EMPTY_NODE(&node->rb)) {
3235 spin_lock(&sibling->active.lock);
3236 rb_erase_cached(&node->rb,
3237 &sibling->execlists.virtual);
3238 RB_CLEAR_NODE(&node->rb);
3239 spin_unlock(&sibling->active.lock);
3244 spin_lock(&sibling->active.lock);
3246 if (!RB_EMPTY_NODE(&node->rb)) {
3248 * Cheat and avoid rebalancing the tree if we can
3249 * reuse this node in situ.
3251 first = rb_first_cached(&sibling->execlists.virtual) ==
3253 if (prio == node->prio || (prio > node->prio && first))
3256 rb_erase_cached(&node->rb, &sibling->execlists.virtual);
3261 parent = &sibling->execlists.virtual.rb_root.rb_node;
3263 struct ve_node *other;
3266 other = rb_entry(rb, typeof(*other), rb);
3267 if (prio > other->prio) {
3268 parent = &rb->rb_left;
3270 parent = &rb->rb_right;
3275 rb_link_node(&node->rb, rb, parent);
3276 rb_insert_color_cached(&node->rb,
3277 &sibling->execlists.virtual,
3281 GEM_BUG_ON(RB_EMPTY_NODE(&node->rb));
3283 if (first && prio > sibling->execlists.queue_priority_hint) {
3284 sibling->execlists.queue_priority_hint = prio;
3285 tasklet_hi_schedule(&sibling->execlists.tasklet);
3288 spin_unlock(&sibling->active.lock);
3293 static void virtual_submit_request(struct i915_request *rq)
3295 struct virtual_engine *ve = to_virtual_engine(rq->engine);
3297 GEM_TRACE("%s: rq=%llx:%lld\n",
3302 GEM_BUG_ON(ve->base.submit_request != virtual_submit_request);
3304 GEM_BUG_ON(ve->request);
3305 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
3307 ve->base.execlists.queue_priority_hint = rq_prio(rq);
3308 WRITE_ONCE(ve->request, rq);
3310 list_move_tail(&rq->sched.link, virtual_queue(ve));
3312 tasklet_schedule(&ve->base.execlists.tasklet);
3315 static struct ve_bond *
3316 virtual_find_bond(struct virtual_engine *ve,
3317 const struct intel_engine_cs *master)
3321 for (i = 0; i < ve->num_bonds; i++) {
3322 if (ve->bonds[i].master == master)
3323 return &ve->bonds[i];
3330 virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
3332 struct virtual_engine *ve = to_virtual_engine(rq->engine);
3333 struct ve_bond *bond;
3335 bond = virtual_find_bond(ve, to_request(signal)->engine);
3337 intel_engine_mask_t old, new, cmp;
3339 cmp = READ_ONCE(rq->execution_mask);
3342 new = cmp & bond->sibling_mask;
3343 } while ((cmp = cmpxchg(&rq->execution_mask, old, new)) != old);
3347 struct intel_context *
3348 intel_execlists_create_virtual(struct i915_gem_context *ctx,
3349 struct intel_engine_cs **siblings,
3352 struct virtual_engine *ve;
3357 return ERR_PTR(-EINVAL);
3360 return intel_context_create(ctx, siblings[0]);
3362 ve = kzalloc(struct_size(ve, siblings, count), GFP_KERNEL);
3364 return ERR_PTR(-ENOMEM);
3366 ve->base.i915 = ctx->i915;
3367 ve->base.gt = siblings[0]->gt;
3369 ve->base.class = OTHER_CLASS;
3370 ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
3371 ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
3372 ve->base.flags = I915_ENGINE_IS_VIRTUAL;
3375 * The decision on whether to submit a request using semaphores
3376 * depends on the saturated state of the engine. We only compute
3377 * this during HW submission of the request, and we need for this
3378 * state to be globally applied to all requests being submitted
3379 * to this engine. Virtual engines encompass more than one physical
3380 * engine and so we cannot accurately tell in advance if one of those
3381 * engines is already saturated and so cannot afford to use a semaphore
3382 * and be pessimized in priority for doing so -- if we are the only
3383 * context using semaphores after all other clients have stopped, we
3384 * will be starved on the saturated system. Such a global switch for
3385 * semaphores is less than ideal, but alas is the current compromise.
3387 ve->base.saturated = ALL_ENGINES;
3389 snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
3391 intel_engine_init_active(&ve->base, ENGINE_VIRTUAL);
3393 intel_engine_init_execlists(&ve->base);
3395 ve->base.cops = &virtual_context_ops;
3396 ve->base.request_alloc = execlists_request_alloc;
3398 ve->base.schedule = i915_schedule;
3399 ve->base.submit_request = virtual_submit_request;
3400 ve->base.bond_execute = virtual_bond_execute;
3402 INIT_LIST_HEAD(virtual_queue(ve));
3403 ve->base.execlists.queue_priority_hint = INT_MIN;
3404 tasklet_init(&ve->base.execlists.tasklet,
3405 virtual_submission_tasklet,
3408 intel_context_init(&ve->context, ctx, &ve->base);
3410 for (n = 0; n < count; n++) {
3411 struct intel_engine_cs *sibling = siblings[n];
3413 GEM_BUG_ON(!is_power_of_2(sibling->mask));
3414 if (sibling->mask & ve->base.mask) {
3415 DRM_DEBUG("duplicate %s entry in load balancer\n",
3422 * The virtual engine implementation is tightly coupled to
3423 * the execlists backend -- we push out request directly
3424 * into a tree inside each physical engine. We could support
3425 * layering if we handle cloning of the requests and
3426 * submitting a copy into each backend.
3428 if (sibling->execlists.tasklet.func !=
3429 execlists_submission_tasklet) {
3434 GEM_BUG_ON(RB_EMPTY_NODE(&ve->nodes[sibling->id].rb));
3435 RB_CLEAR_NODE(&ve->nodes[sibling->id].rb);
3437 ve->siblings[ve->num_siblings++] = sibling;
3438 ve->base.mask |= sibling->mask;
3441 * All physical engines must be compatible for their emission
3442 * functions (as we build the instructions during request
3443 * construction and do not alter them before submission
3444 * on the physical engine). We use the engine class as a guide
3445 * here, although that could be refined.
3447 if (ve->base.class != OTHER_CLASS) {
3448 if (ve->base.class != sibling->class) {
3449 DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
3450 sibling->class, ve->base.class);
3457 ve->base.class = sibling->class;
3458 ve->base.uabi_class = sibling->uabi_class;
3459 snprintf(ve->base.name, sizeof(ve->base.name),
3460 "v%dx%d", ve->base.class, count);
3461 ve->base.context_size = sibling->context_size;
3463 ve->base.emit_bb_start = sibling->emit_bb_start;
3464 ve->base.emit_flush = sibling->emit_flush;
3465 ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb;
3466 ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb;
3467 ve->base.emit_fini_breadcrumb_dw =
3468 sibling->emit_fini_breadcrumb_dw;
3471 return &ve->context;
3474 intel_context_put(&ve->context);
3475 return ERR_PTR(err);
3478 struct intel_context *
3479 intel_execlists_clone_virtual(struct i915_gem_context *ctx,
3480 struct intel_engine_cs *src)
3482 struct virtual_engine *se = to_virtual_engine(src);
3483 struct intel_context *dst;
3485 dst = intel_execlists_create_virtual(ctx,
3491 if (se->num_bonds) {
3492 struct virtual_engine *de = to_virtual_engine(dst->engine);
3494 de->bonds = kmemdup(se->bonds,
3495 sizeof(*se->bonds) * se->num_bonds,
3498 intel_context_put(dst);
3499 return ERR_PTR(-ENOMEM);
3502 de->num_bonds = se->num_bonds;
3508 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
3509 const struct intel_engine_cs *master,
3510 const struct intel_engine_cs *sibling)
3512 struct virtual_engine *ve = to_virtual_engine(engine);
3513 struct ve_bond *bond;
3516 /* Sanity check the sibling is part of the virtual engine */
3517 for (n = 0; n < ve->num_siblings; n++)
3518 if (sibling == ve->siblings[n])
3520 if (n == ve->num_siblings)
3523 bond = virtual_find_bond(ve, master);
3525 bond->sibling_mask |= sibling->mask;
3529 bond = krealloc(ve->bonds,
3530 sizeof(*bond) * (ve->num_bonds + 1),
3535 bond[ve->num_bonds].master = master;
3536 bond[ve->num_bonds].sibling_mask = sibling->mask;
3544 void intel_execlists_show_requests(struct intel_engine_cs *engine,
3545 struct drm_printer *m,
3546 void (*show_request)(struct drm_printer *m,
3547 struct i915_request *rq,
3548 const char *prefix),
3551 const struct intel_engine_execlists *execlists = &engine->execlists;
3552 struct i915_request *rq, *last;
3553 unsigned long flags;
3557 spin_lock_irqsave(&engine->active.lock, flags);
3561 list_for_each_entry(rq, &engine->active.requests, sched.link) {
3562 if (count++ < max - 1)
3563 show_request(m, rq, "\t\tE ");
3570 "\t\t...skipping %d executing requests...\n",
3573 show_request(m, last, "\t\tE ");
3578 if (execlists->queue_priority_hint != INT_MIN)
3579 drm_printf(m, "\t\tQueue priority hint: %d\n",
3580 execlists->queue_priority_hint);
3581 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
3582 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
3585 priolist_for_each_request(rq, p, i) {
3586 if (count++ < max - 1)
3587 show_request(m, rq, "\t\tQ ");
3595 "\t\t...skipping %d queued requests...\n",
3598 show_request(m, last, "\t\tQ ");
3603 for (rb = rb_first_cached(&execlists->virtual); rb; rb = rb_next(rb)) {
3604 struct virtual_engine *ve =
3605 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
3606 struct i915_request *rq = READ_ONCE(ve->request);
3609 if (count++ < max - 1)
3610 show_request(m, rq, "\t\tV ");
3618 "\t\t...skipping %d virtual requests...\n",
3621 show_request(m, last, "\t\tV ");
3624 spin_unlock_irqrestore(&engine->active.lock, flags);
3627 void intel_lr_context_reset(struct intel_engine_cs *engine,
3628 struct intel_context *ce,
3633 * We want a simple context + ring to execute the breadcrumb update.
3634 * We cannot rely on the context being intact across the GPU hang,
3635 * so clear it and rebuild just what we need for the breadcrumb.
3636 * All pending requests for this context will be zapped, and any
3637 * future request will be after userspace has had the opportunity
3638 * to recreate its own state.
3641 u32 *regs = ce->lrc_reg_state;
3643 if (engine->pinned_default_state) {
3644 memcpy(regs, /* skip restoring the vanilla PPHWSP */
3645 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
3646 engine->context_size - PAGE_SIZE);
3648 execlists_init_reg_state(regs, ce, engine, ce->ring);
3651 /* Rerun the request; its payload has been neutered (if guilty). */
3652 ce->ring->head = head;
3653 intel_ring_update_space(ce->ring);
3655 __execlists_update_reg_state(ce, engine);
3658 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3659 #include "selftest_lrc.c"