2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include "gem/i915_gem_context.h"
138 #include "i915_drv.h"
139 #include "i915_perf.h"
140 #include "i915_trace.h"
141 #include "i915_vgpu.h"
142 #include "intel_engine_pm.h"
143 #include "intel_gt.h"
144 #include "intel_gt_pm.h"
145 #include "intel_lrc_reg.h"
146 #include "intel_mocs.h"
147 #include "intel_reset.h"
148 #include "intel_workarounds.h"
150 #define RING_EXECLIST_QFULL (1 << 0x2)
151 #define RING_EXECLIST1_VALID (1 << 0x3)
152 #define RING_EXECLIST0_VALID (1 << 0x4)
153 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
154 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
155 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
157 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
158 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
159 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
160 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
161 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
162 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
164 #define GEN8_CTX_STATUS_COMPLETED_MASK \
165 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
167 #define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
169 #define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb dword */
170 #define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper csb dword */
171 #define GEN12_CSB_SW_CTX_ID_MASK GENMASK(25, 15)
172 #define GEN12_IDLE_CTX_ID 0x7FF
173 #define GEN12_CSB_CTX_VALID(csb_dw) \
174 (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID)
176 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
177 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
178 #define WA_TAIL_DWORDS 2
179 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
181 struct virtual_engine {
182 struct intel_engine_cs base;
183 struct intel_context context;
186 * We allow only a single request through the virtual engine at a time
187 * (each request in the timeline waits for the completion fence of
188 * the previous before being submitted). By restricting ourselves to
189 * only submitting a single request, each request is placed on to a
190 * physical to maximise load spreading (by virtue of the late greedy
191 * scheduling -- each real engine takes the next available request
194 struct i915_request *request;
197 * We keep a rbtree of available virtual engines inside each physical
198 * engine, sorted by priority. Here we preallocate the nodes we need
199 * for the virtual engine, indexed by physical_engine->id.
204 } nodes[I915_NUM_ENGINES];
207 * Keep track of bonded pairs -- restrictions upon on our selection
208 * of physical engines any particular request may be submitted to.
209 * If we receive a submit-fence from a master engine, we will only
210 * use one of sibling_mask physical engines.
213 const struct intel_engine_cs *master;
214 intel_engine_mask_t sibling_mask;
216 unsigned int num_bonds;
218 /* And finally, which physical engines this virtual engine maps onto. */
219 unsigned int num_siblings;
220 struct intel_engine_cs *siblings[0];
223 static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine)
225 GEM_BUG_ON(!intel_engine_is_virtual(engine));
226 return container_of(engine, struct virtual_engine, base);
229 static int __execlists_context_alloc(struct intel_context *ce,
230 struct intel_engine_cs *engine);
232 static void execlists_init_reg_state(u32 *reg_state,
233 struct intel_context *ce,
234 struct intel_engine_cs *engine,
235 struct intel_ring *ring);
237 static void mark_eio(struct i915_request *rq)
239 if (!i915_request_signaled(rq))
240 dma_fence_set_error(&rq->fence, -EIO);
241 i915_request_mark_complete(rq);
244 static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
246 return (i915_ggtt_offset(engine->status_page.vma) +
247 I915_GEM_HWS_PREEMPT_ADDR);
251 ring_set_paused(const struct intel_engine_cs *engine, int state)
254 * We inspect HWS_PREEMPT with a semaphore inside
255 * engine->emit_fini_breadcrumb. If the dword is true,
256 * the ring is paused as the semaphore will busywait
257 * until the dword is false.
259 engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
264 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
266 return rb_entry(rb, struct i915_priolist, node);
269 static inline int rq_prio(const struct i915_request *rq)
271 return rq->sched.attr.priority;
274 static int effective_prio(const struct i915_request *rq)
276 int prio = rq_prio(rq);
279 * If this request is special and must not be interrupted at any
280 * cost, so be it. Note we are only checking the most recent request
281 * in the context and so may be masking an earlier vip request. It
282 * is hoped that under the conditions where nopreempt is used, this
283 * will not matter (i.e. all requests to that context will be
284 * nopreempt for as long as desired).
286 if (i915_request_has_nopreempt(rq))
287 prio = I915_PRIORITY_UNPREEMPTABLE;
290 * On unwinding the active request, we give it a priority bump
291 * if it has completed waiting on any semaphore. If we know that
292 * the request has already started, we can prevent an unwanted
293 * preempt-to-idle cycle by taking that into account now.
295 if (__i915_request_has_started(rq))
296 prio |= I915_PRIORITY_NOSEMAPHORE;
298 /* Restrict mere WAIT boosts from triggering preemption */
299 BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
300 return prio | __NO_PREEMPTION;
303 static int queue_prio(const struct intel_engine_execlists *execlists)
305 struct i915_priolist *p;
308 rb = rb_first_cached(&execlists->queue);
313 * As the priolist[] are inverted, with the highest priority in [0],
314 * we have to flip the index value to become priority.
317 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
320 static inline bool need_preempt(const struct intel_engine_cs *engine,
321 const struct i915_request *rq,
326 if (!intel_engine_has_semaphores(engine))
330 * Check if the current priority hint merits a preemption attempt.
332 * We record the highest value priority we saw during rescheduling
333 * prior to this dequeue, therefore we know that if it is strictly
334 * less than the current tail of ESLP[0], we do not need to force
335 * a preempt-to-idle cycle.
337 * However, the priority hint is a mere hint that we may need to
338 * preempt. If that hint is stale or we may be trying to preempt
339 * ourselves, ignore the request.
341 last_prio = effective_prio(rq);
342 if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint,
347 * Check against the first request in ELSP[1], it will, thanks to the
348 * power of PI, be the highest priority of that context.
350 if (!list_is_last(&rq->sched.link, &engine->active.requests) &&
351 rq_prio(list_next_entry(rq, sched.link)) > last_prio)
355 struct virtual_engine *ve =
356 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
357 bool preempt = false;
359 if (engine == ve->siblings[0]) { /* only preempt one sibling */
360 struct i915_request *next;
363 next = READ_ONCE(ve->request);
365 preempt = rq_prio(next) > last_prio;
374 * If the inflight context did not trigger the preemption, then maybe
375 * it was the set of queued requests? Pick the highest priority in
376 * the queue (the first active priolist) and see if it deserves to be
377 * running instead of ELSP[0].
379 * The highest priority request in the queue can not be either
380 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same
381 * context, it's priority would not exceed ELSP[0] aka last_prio.
383 return queue_prio(&engine->execlists) > last_prio;
386 __maybe_unused static inline bool
387 assert_priority_queue(const struct i915_request *prev,
388 const struct i915_request *next)
391 * Without preemption, the prev may refer to the still active element
392 * which we refuse to let go.
394 * Even with preemption, there are times when we think it is better not
395 * to preempt and leave an ostensibly lower priority request in flight.
397 if (i915_request_is_active(prev))
400 return rq_prio(prev) >= rq_prio(next);
404 * The context descriptor encodes various attributes of a context,
405 * including its GTT address and some flags. Because it's fairly
406 * expensive to calculate, we'll just do it once and cache the result,
407 * which remains valid until the context is unpinned.
409 * This is what a descriptor looks like, from LSB to MSB::
411 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
412 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
413 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
414 * bits 53-54: mbz, reserved for use by hardware
415 * bits 55-63: group ID, currently unused and set to 0
417 * Starting from Gen11, the upper dword of the descriptor has a new format:
419 * bits 32-36: reserved
420 * bits 37-47: SW context ID
421 * bits 48:53: engine instance
422 * bit 54: mbz, reserved for use by hardware
423 * bits 55-60: SW counter
424 * bits 61-63: engine class
426 * engine info, SW context ID and SW counter need to form a unique number
427 * (Context ID) per lrc.
430 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
432 struct i915_gem_context *ctx = ce->gem_context;
435 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
436 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
438 desc = INTEL_LEGACY_32B_CONTEXT;
439 if (i915_vm_is_4lvl(ce->vm))
440 desc = INTEL_LEGACY_64B_CONTEXT;
441 desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
443 desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
444 if (IS_GEN(engine->i915, 8))
445 desc |= GEN8_CTX_L3LLC_COHERENT;
447 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
450 * The following 32bits are copied into the OA reports (dword 2).
451 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
454 if (INTEL_GEN(engine->i915) >= 11) {
455 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
456 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
459 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
462 /* TODO: decide what to do with SW counter (bits 55-60) */
464 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
467 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
468 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
474 static void unwind_wa_tail(struct i915_request *rq)
476 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
477 assert_ring_tail_valid(rq->ring, rq->tail);
480 static struct i915_request *
481 __unwind_incomplete_requests(struct intel_engine_cs *engine)
483 struct i915_request *rq, *rn, *active = NULL;
484 struct list_head *uninitialized_var(pl);
485 int prio = I915_PRIORITY_INVALID;
487 lockdep_assert_held(&engine->active.lock);
489 list_for_each_entry_safe_reverse(rq, rn,
490 &engine->active.requests,
492 struct intel_engine_cs *owner;
494 if (i915_request_completed(rq))
497 __i915_request_unsubmit(rq);
501 * Push the request back into the queue for later resubmission.
502 * If this request is not native to this physical engine (i.e.
503 * it came from a virtual source), push it back onto the virtual
504 * engine so that it can be moved across onto another physical
505 * engine as load dictates.
507 owner = rq->hw_context->engine;
508 if (likely(owner == engine)) {
509 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
510 if (rq_prio(rq) != prio) {
512 pl = i915_sched_lookup_priolist(engine, prio);
514 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
516 list_move(&rq->sched.link, pl);
520 * Decouple the virtual breadcrumb before moving it
521 * back to the virtual engine -- we don't want the
522 * request to complete in the background and try
523 * and cancel the breadcrumb on the virtual engine
524 * (instead of the old engine where it is linked)!
526 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
528 spin_lock(&rq->lock);
529 i915_request_cancel_breadcrumb(rq);
530 spin_unlock(&rq->lock);
533 owner->submit_request(rq);
541 struct i915_request *
542 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
544 struct intel_engine_cs *engine =
545 container_of(execlists, typeof(*engine), execlists);
547 return __unwind_incomplete_requests(engine);
551 execlists_context_status_change(struct i915_request *rq, unsigned long status)
554 * Only used when GVT-g is enabled now. When GVT-g is disabled,
555 * The compiler should eliminate this function as dead-code.
557 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
560 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
564 static inline struct intel_engine_cs *
565 __execlists_schedule_in(struct i915_request *rq)
567 struct intel_engine_cs * const engine = rq->engine;
568 struct intel_context * const ce = rq->hw_context;
570 intel_context_get(ce);
572 intel_gt_pm_get(engine->gt);
573 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
574 intel_engine_context_in(engine);
579 static inline struct i915_request *
580 execlists_schedule_in(struct i915_request *rq, int idx)
582 struct intel_context * const ce = rq->hw_context;
583 struct intel_engine_cs *old;
585 GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
586 trace_i915_request_in(rq, idx);
588 old = READ_ONCE(ce->inflight);
591 WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq));
594 } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old)));
596 GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
597 return i915_request_get(rq);
600 static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
602 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
603 struct i915_request *next = READ_ONCE(ve->request);
605 if (next && next->execution_mask & ~rq->execution_mask)
606 tasklet_schedule(&ve->base.execlists.tasklet);
610 __execlists_schedule_out(struct i915_request *rq,
611 struct intel_engine_cs * const engine)
613 struct intel_context * const ce = rq->hw_context;
615 intel_engine_context_out(engine);
616 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
617 intel_gt_pm_put(engine->gt);
620 * If this is part of a virtual engine, its next request may
621 * have been blocked waiting for access to the active context.
622 * We have to kick all the siblings again in case we need to
623 * switch (e.g. the next request is not runnable on this
624 * engine). Hopefully, we will already have submitted the next
625 * request before the tasklet runs and do not need to rebuild
626 * each virtual tree and kick everyone again.
628 if (ce->engine != engine)
629 kick_siblings(rq, ce);
631 intel_context_put(ce);
635 execlists_schedule_out(struct i915_request *rq)
637 struct intel_context * const ce = rq->hw_context;
638 struct intel_engine_cs *cur, *old;
640 trace_i915_request_out(rq);
642 old = READ_ONCE(ce->inflight);
644 cur = ptr_unmask_bits(old, 2) ? ptr_dec(old) : NULL;
645 while (!try_cmpxchg(&ce->inflight, &old, cur));
647 __execlists_schedule_out(rq, old);
649 i915_request_put(rq);
652 static u64 execlists_update_context(const struct i915_request *rq)
654 struct intel_context *ce = rq->hw_context;
657 ce->lrc_reg_state[CTX_RING_TAIL + 1] =
658 intel_ring_set_tail(rq->ring, rq->tail);
661 * Make sure the context image is complete before we submit it to HW.
663 * Ostensibly, writes (including the WCB) should be flushed prior to
664 * an uncached write such as our mmio register access, the empirical
665 * evidence (esp. on Braswell) suggests that the WC write into memory
666 * may not be visible to the HW prior to the completion of the UC
667 * register write and that we may begin execution from the context
668 * before its image is complete leading to invalid PD chasing.
670 * Furthermore, Braswell, at least, wants a full mb to be sure that
671 * the writes are coherent in memory (visible to the GPU) prior to
672 * execution, and not just visible to other CPUs (as is the result of
678 ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;
683 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
685 if (execlists->ctrl_reg) {
686 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
687 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
689 writel(upper_32_bits(desc), execlists->submit_reg);
690 writel(lower_32_bits(desc), execlists->submit_reg);
694 static __maybe_unused void
695 trace_ports(const struct intel_engine_execlists *execlists,
697 struct i915_request * const *ports)
699 const struct intel_engine_cs *engine =
700 container_of(execlists, typeof(*engine), execlists);
702 GEM_TRACE("%s: %s { %llx:%lld%s, %llx:%lld }\n",
704 ports[0]->fence.context,
705 ports[0]->fence.seqno,
706 i915_request_completed(ports[0]) ? "!" :
707 i915_request_started(ports[0]) ? "*" :
709 ports[1] ? ports[1]->fence.context : 0,
710 ports[1] ? ports[1]->fence.seqno : 0);
713 static __maybe_unused bool
714 assert_pending_valid(const struct intel_engine_execlists *execlists,
717 struct i915_request * const *port, *rq;
718 struct intel_context *ce = NULL;
720 trace_ports(execlists, msg, execlists->pending);
722 if (!execlists->pending[0])
725 if (execlists->pending[execlists_num_ports(execlists)])
728 for (port = execlists->pending; (rq = *port); port++) {
729 if (ce == rq->hw_context)
733 if (i915_request_completed(rq))
736 if (i915_active_is_idle(&ce->active))
739 if (!i915_vma_is_pinned(ce->state))
746 static void execlists_submit_ports(struct intel_engine_cs *engine)
748 struct intel_engine_execlists *execlists = &engine->execlists;
751 GEM_BUG_ON(!assert_pending_valid(execlists, "submit"));
754 * We can skip acquiring intel_runtime_pm_get() here as it was taken
755 * on our behalf by the request (see i915_gem_mark_busy()) and it will
756 * not be relinquished until the device is idle (see
757 * i915_gem_idle_work_handler()). As a precaution, we make sure
758 * that all ELSP are drained i.e. we have processed the CSB,
759 * before allowing ourselves to idle and calling intel_runtime_pm_put().
761 GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
764 * ELSQ note: the submit queue is not cleared after being submitted
765 * to the HW so we need to make sure we always clean it up. This is
766 * currently ensured by the fact that we always write the same number
767 * of elsq entries, keep this in mind before changing the loop below.
769 for (n = execlists_num_ports(execlists); n--; ) {
770 struct i915_request *rq = execlists->pending[n];
772 write_desc(execlists,
773 rq ? execlists_update_context(rq) : 0,
777 /* we need to manually load the submit queue */
778 if (execlists->ctrl_reg)
779 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
782 static bool ctx_single_port_submission(const struct intel_context *ce)
784 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
785 i915_gem_context_force_single_submission(ce->gem_context));
788 static bool can_merge_ctx(const struct intel_context *prev,
789 const struct intel_context *next)
794 if (ctx_single_port_submission(prev))
800 static bool can_merge_rq(const struct i915_request *prev,
801 const struct i915_request *next)
803 GEM_BUG_ON(prev == next);
804 GEM_BUG_ON(!assert_priority_queue(prev, next));
807 * We do not submit known completed requests. Therefore if the next
808 * request is already completed, we can pretend to merge it in
809 * with the previous context (and we will skip updating the ELSP
810 * and tracking). Thus hopefully keeping the ELSP full with active
811 * contexts, despite the best efforts of preempt-to-busy to confuse
814 if (i915_request_completed(next))
817 if (!can_merge_ctx(prev->hw_context, next->hw_context))
823 static void virtual_update_register_offsets(u32 *regs,
824 struct intel_engine_cs *engine)
826 u32 base = engine->mmio_base;
828 /* Must match execlists_init_reg_state()! */
830 regs[CTX_CONTEXT_CONTROL] =
831 i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base));
832 regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base));
833 regs[CTX_RING_TAIL] = i915_mmio_reg_offset(RING_TAIL(base));
834 regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base));
835 regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base));
837 regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base));
838 regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base));
839 regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base));
840 regs[CTX_SECOND_BB_HEAD_U] =
841 i915_mmio_reg_offset(RING_SBBADDR_UDW(base));
842 regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base));
843 regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base));
845 regs[CTX_CTX_TIMESTAMP] =
846 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base));
847 regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3));
848 regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3));
849 regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2));
850 regs[CTX_PDP2_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 2));
851 regs[CTX_PDP1_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 1));
852 regs[CTX_PDP1_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 1));
853 regs[CTX_PDP0_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
854 regs[CTX_PDP0_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
856 if (engine->class == RENDER_CLASS) {
857 regs[CTX_RCS_INDIRECT_CTX] =
858 i915_mmio_reg_offset(RING_INDIRECT_CTX(base));
859 regs[CTX_RCS_INDIRECT_CTX_OFFSET] =
860 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(base));
861 regs[CTX_BB_PER_CTX_PTR] =
862 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(base));
864 regs[CTX_R_PWR_CLK_STATE] =
865 i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
869 static bool virtual_matches(const struct virtual_engine *ve,
870 const struct i915_request *rq,
871 const struct intel_engine_cs *engine)
873 const struct intel_engine_cs *inflight;
875 if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */
879 * We track when the HW has completed saving the context image
880 * (i.e. when we have seen the final CS event switching out of
881 * the context) and must not overwrite the context image before
882 * then. This restricts us to only using the active engine
883 * while the previous virtualized request is inflight (so
884 * we reuse the register offsets). This is a very small
885 * hystersis on the greedy seelction algorithm.
887 inflight = intel_context_inflight(&ve->context);
888 if (inflight && inflight != engine)
894 static void virtual_xfer_breadcrumbs(struct virtual_engine *ve,
895 struct intel_engine_cs *engine)
897 struct intel_engine_cs *old = ve->siblings[0];
899 /* All unattached (rq->engine == old) must already be completed */
901 spin_lock(&old->breadcrumbs.irq_lock);
902 if (!list_empty(&ve->context.signal_link)) {
903 list_move_tail(&ve->context.signal_link,
904 &engine->breadcrumbs.signalers);
905 intel_engine_queue_breadcrumbs(engine);
907 spin_unlock(&old->breadcrumbs.irq_lock);
910 static struct i915_request *
911 last_active(const struct intel_engine_execlists *execlists)
913 struct i915_request * const *last = READ_ONCE(execlists->active);
915 while (*last && i915_request_completed(*last))
921 static void defer_request(struct i915_request *rq, struct list_head * const pl)
926 * We want to move the interrupted request to the back of
927 * the round-robin list (i.e. its priority level), but
928 * in doing so, we must then move all requests that were in
929 * flight and were waiting for the interrupted request to
930 * be run after it again.
933 struct i915_dependency *p;
935 GEM_BUG_ON(i915_request_is_active(rq));
936 list_move_tail(&rq->sched.link, pl);
938 list_for_each_entry(p, &rq->sched.waiters_list, wait_link) {
939 struct i915_request *w =
940 container_of(p->waiter, typeof(*w), sched);
942 /* Leave semaphores spinning on the other engines */
943 if (w->engine != rq->engine)
946 /* No waiter should start before its signaler */
947 GEM_BUG_ON(i915_request_started(w) &&
948 !i915_request_completed(rq));
950 GEM_BUG_ON(i915_request_is_active(w));
951 if (list_empty(&w->sched.link))
952 continue; /* Not yet submitted; unready */
954 if (rq_prio(w) < rq_prio(rq))
957 GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
958 list_move_tail(&w->sched.link, &list);
961 rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
965 static void defer_active(struct intel_engine_cs *engine)
967 struct i915_request *rq;
969 rq = __unwind_incomplete_requests(engine);
973 defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
977 need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
981 if (!intel_engine_has_semaphores(engine))
984 if (list_is_last(&rq->sched.link, &engine->active.requests))
987 hint = max(rq_prio(list_next_entry(rq, sched.link)),
988 engine->execlists.queue_priority_hint);
990 return hint >= effective_prio(rq);
994 switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
996 if (list_is_last(&rq->sched.link, &engine->active.requests))
999 return rq_prio(list_next_entry(rq, sched.link));
1003 enable_timeslice(const struct intel_engine_execlists *execlists)
1005 const struct i915_request *rq = *execlists->active;
1007 if (i915_request_completed(rq))
1010 return execlists->switch_priority_hint >= effective_prio(rq);
1013 static void record_preemption(struct intel_engine_execlists *execlists)
1015 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
1018 static void execlists_dequeue(struct intel_engine_cs *engine)
1020 struct intel_engine_execlists * const execlists = &engine->execlists;
1021 struct i915_request **port = execlists->pending;
1022 struct i915_request ** const last_port = port + execlists->port_mask;
1023 struct i915_request *last;
1025 bool submit = false;
1028 * Hardware submission is through 2 ports. Conceptually each port
1029 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
1030 * static for a context, and unique to each, so we only execute
1031 * requests belonging to a single context from each ring. RING_HEAD
1032 * is maintained by the CS in the context image, it marks the place
1033 * where it got up to last time, and through RING_TAIL we tell the CS
1034 * where we want to execute up to this time.
1036 * In this list the requests are in order of execution. Consecutive
1037 * requests from the same context are adjacent in the ringbuffer. We
1038 * can combine these requests into a single RING_TAIL update:
1040 * RING_HEAD...req1...req2
1042 * since to execute req2 the CS must first execute req1.
1044 * Our goal then is to point each port to the end of a consecutive
1045 * sequence of requests as being the most optimal (fewest wake ups
1046 * and context switches) submission.
1049 for (rb = rb_first_cached(&execlists->virtual); rb; ) {
1050 struct virtual_engine *ve =
1051 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
1052 struct i915_request *rq = READ_ONCE(ve->request);
1054 if (!rq) { /* lazily cleanup after another engine handled rq */
1055 rb_erase_cached(rb, &execlists->virtual);
1057 rb = rb_first_cached(&execlists->virtual);
1061 if (!virtual_matches(ve, rq, engine)) {
1070 * If the queue is higher priority than the last
1071 * request in the currently active context, submit afresh.
1072 * We will resubmit again afterwards in case we need to split
1073 * the active context to interject the preemption request,
1074 * i.e. we will retrigger preemption following the ack in case
1077 last = last_active(execlists);
1079 if (need_preempt(engine, last, rb)) {
1080 GEM_TRACE("%s: preempting last=%llx:%lld, prio=%d, hint=%d\n",
1082 last->fence.context,
1084 last->sched.attr.priority,
1085 execlists->queue_priority_hint);
1086 record_preemption(execlists);
1089 * Don't let the RING_HEAD advance past the breadcrumb
1090 * as we unwind (and until we resubmit) so that we do
1091 * not accidentally tell it to go backwards.
1093 ring_set_paused(engine, 1);
1096 * Note that we have not stopped the GPU at this point,
1097 * so we are unwinding the incomplete requests as they
1098 * remain inflight and so by the time we do complete
1099 * the preemption, some of the unwound requests may
1102 __unwind_incomplete_requests(engine);
1105 * If we need to return to the preempted context, we
1106 * need to skip the lite-restore and force it to
1107 * reload the RING_TAIL. Otherwise, the HW has a
1108 * tendency to ignore us rewinding the TAIL to the
1109 * end of an earlier request.
1111 last->hw_context->lrc_desc |= CTX_DESC_FORCE_RESTORE;
1113 } else if (need_timeslice(engine, last) &&
1114 !timer_pending(&engine->execlists.timer)) {
1115 GEM_TRACE("%s: expired last=%llx:%lld, prio=%d, hint=%d\n",
1117 last->fence.context,
1119 last->sched.attr.priority,
1120 execlists->queue_priority_hint);
1122 ring_set_paused(engine, 1);
1123 defer_active(engine);
1126 * Unlike for preemption, if we rewind and continue
1127 * executing the same context as previously active,
1128 * the order of execution will remain the same and
1129 * the tail will only advance. We do not need to
1130 * force a full context restore, as a lite-restore
1131 * is sufficient to resample the monotonic TAIL.
1133 * If we switch to any other context, similarly we
1134 * will not rewind TAIL of current context, and
1135 * normal save/restore will preserve state and allow
1136 * us to later continue executing the same request.
1141 * Otherwise if we already have a request pending
1142 * for execution after the current one, we can
1143 * just wait until the next CS event before
1144 * queuing more. In either case we will force a
1145 * lite-restore preemption event, but if we wait
1146 * we hopefully coalesce several updates into a single
1149 if (!list_is_last(&last->sched.link,
1150 &engine->active.requests))
1154 * WaIdleLiteRestore:bdw,skl
1155 * Apply the wa NOOPs to prevent
1156 * ring:HEAD == rq:TAIL as we resubmit the
1157 * request. See gen8_emit_fini_breadcrumb() for
1158 * where we prepare the padding after the
1159 * end of the request.
1161 last->tail = last->wa_tail;
1165 while (rb) { /* XXX virtual is always taking precedence */
1166 struct virtual_engine *ve =
1167 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
1168 struct i915_request *rq;
1170 spin_lock(&ve->base.active.lock);
1173 if (unlikely(!rq)) { /* lost the race to a sibling */
1174 spin_unlock(&ve->base.active.lock);
1175 rb_erase_cached(rb, &execlists->virtual);
1177 rb = rb_first_cached(&execlists->virtual);
1181 GEM_BUG_ON(rq != ve->request);
1182 GEM_BUG_ON(rq->engine != &ve->base);
1183 GEM_BUG_ON(rq->hw_context != &ve->context);
1185 if (rq_prio(rq) >= queue_prio(execlists)) {
1186 if (!virtual_matches(ve, rq, engine)) {
1187 spin_unlock(&ve->base.active.lock);
1192 if (last && !can_merge_rq(last, rq)) {
1193 spin_unlock(&ve->base.active.lock);
1194 return; /* leave this for another */
1197 GEM_TRACE("%s: virtual rq=%llx:%lld%s, new engine? %s\n",
1201 i915_request_completed(rq) ? "!" :
1202 i915_request_started(rq) ? "*" :
1204 yesno(engine != ve->siblings[0]));
1207 ve->base.execlists.queue_priority_hint = INT_MIN;
1208 rb_erase_cached(rb, &execlists->virtual);
1211 GEM_BUG_ON(!(rq->execution_mask & engine->mask));
1212 rq->engine = engine;
1214 if (engine != ve->siblings[0]) {
1215 u32 *regs = ve->context.lrc_reg_state;
1218 GEM_BUG_ON(READ_ONCE(ve->context.inflight));
1219 virtual_update_register_offsets(regs, engine);
1221 if (!list_empty(&ve->context.signals))
1222 virtual_xfer_breadcrumbs(ve, engine);
1225 * Move the bound engine to the top of the list
1226 * for future execution. We then kick this
1227 * tasklet first before checking others, so that
1228 * we preferentially reuse this set of bound
1231 for (n = 1; n < ve->num_siblings; n++) {
1232 if (ve->siblings[n] == engine) {
1233 swap(ve->siblings[n],
1239 GEM_BUG_ON(ve->siblings[0] != engine);
1242 if (__i915_request_submit(rq)) {
1248 * Hmm, we have a bunch of virtual engine requests,
1249 * but the first one was already completed (thanks
1250 * preempt-to-busy!). Keep looking at the veng queue
1251 * until we have no more relevant requests (i.e.
1252 * the normal submit queue has higher priority).
1255 spin_unlock(&ve->base.active.lock);
1256 rb = rb_first_cached(&execlists->virtual);
1261 spin_unlock(&ve->base.active.lock);
1265 while ((rb = rb_first_cached(&execlists->queue))) {
1266 struct i915_priolist *p = to_priolist(rb);
1267 struct i915_request *rq, *rn;
1270 priolist_for_each_request_consume(rq, rn, p, i) {
1274 * Can we combine this request with the current port?
1275 * It has to be the same context/ringbuffer and not
1276 * have any exceptions (e.g. GVT saying never to
1277 * combine contexts).
1279 * If we can combine the requests, we can execute both
1280 * by updating the RING_TAIL to point to the end of the
1281 * second request, and so we never need to tell the
1282 * hardware about the first.
1284 if (last && !can_merge_rq(last, rq)) {
1286 * If we are on the second port and cannot
1287 * combine this request with the last, then we
1290 if (port == last_port)
1294 * We must not populate both ELSP[] with the
1295 * same LRCA, i.e. we must submit 2 different
1296 * contexts if we submit 2 ELSP.
1298 if (last->hw_context == rq->hw_context)
1302 * If GVT overrides us we only ever submit
1303 * port[0], leaving port[1] empty. Note that we
1304 * also have to be careful that we don't queue
1305 * the same context (even though a different
1306 * request) to the second port.
1308 if (ctx_single_port_submission(last->hw_context) ||
1309 ctx_single_port_submission(rq->hw_context))
1315 if (__i915_request_submit(rq)) {
1317 *port = execlists_schedule_in(last, port - execlists->pending);
1323 !can_merge_ctx(last->hw_context,
1331 rb_erase_cached(&p->node, &execlists->queue);
1332 i915_priolist_free(p);
1337 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
1339 * We choose the priority hint such that if we add a request of greater
1340 * priority than this, we kick the submission tasklet to decide on
1341 * the right order of submitting the requests to hardware. We must
1342 * also be prepared to reorder requests as they are in-flight on the
1343 * HW. We derive the priority hint then as the first "hole" in
1344 * the HW submission ports and if there are no available slots,
1345 * the priority of the lowest executing request, i.e. last.
1347 * When we do receive a higher priority request ready to run from the
1348 * user, see queue_request(), the priority hint is bumped to that
1349 * request triggering preemption on the next dequeue (or subsequent
1350 * interrupt for secondary ports).
1352 execlists->queue_priority_hint = queue_prio(execlists);
1353 GEM_TRACE("%s: queue_priority_hint:%d, submit:%s\n",
1354 engine->name, execlists->queue_priority_hint,
1358 *port = execlists_schedule_in(last, port - execlists->pending);
1359 memset(port + 1, 0, (last_port - port) * sizeof(*port));
1360 execlists->switch_priority_hint =
1361 switch_prio(engine, *execlists->pending);
1362 execlists_submit_ports(engine);
1364 ring_set_paused(engine, 0);
1369 cancel_port_requests(struct intel_engine_execlists * const execlists)
1371 struct i915_request * const *port, *rq;
1373 for (port = execlists->pending; (rq = *port); port++)
1374 execlists_schedule_out(rq);
1375 memset(execlists->pending, 0, sizeof(execlists->pending));
1377 for (port = execlists->active; (rq = *port); port++)
1378 execlists_schedule_out(rq);
1380 memset(execlists->inflight, 0, sizeof(execlists->inflight));
1384 invalidate_csb_entries(const u32 *first, const u32 *last)
1386 clflush((void *)first);
1387 clflush((void *)last);
1391 reset_in_progress(const struct intel_engine_execlists *execlists)
1393 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
1404 * Starting with Gen12, the status has a new format:
1406 * bit 0: switched to new queue
1408 * bit 2: semaphore wait mode (poll or signal), only valid when
1409 * switch detail is set to "wait on semaphore"
1410 * bits 3-5: engine class
1411 * bits 6-11: engine instance
1412 * bits 12-14: reserved
1413 * bits 15-25: sw context id of the lrc the GT switched to
1414 * bits 26-31: sw counter of the lrc the GT switched to
1415 * bits 32-35: context switch detail
1417 * - 1: wait on sync flip
1418 * - 2: wait on vblank
1419 * - 3: wait on scanline
1420 * - 4: wait on semaphore
1421 * - 5: context preempted (not on SEMAPHORE_WAIT or
1424 * bits 37-43: wait detail (for switch detail 1 to 4)
1425 * bits 44-46: reserved
1426 * bits 47-57: sw context id of the lrc the GT switched away from
1427 * bits 58-63: sw counter of the lrc the GT switched away from
1429 static inline enum csb_step
1430 gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
1432 u32 lower_dw = csb[0];
1433 u32 upper_dw = csb[1];
1434 bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw);
1435 bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw);
1436 bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE;
1438 if (!ctx_away_valid && ctx_to_valid)
1442 * The context switch detail is not guaranteed to be 5 when a preemption
1443 * occurs, so we can't just check for that. The check below works for
1444 * all the cases we care about, including preemptions of WAIT
1445 * instructions and lite-restore. Preempt-to-idle via the CTRL register
1446 * would require some extra handling, but we don't support that.
1448 if (new_queue && ctx_away_valid)
1452 * switch detail = 5 is covered by the case above and we do not expect a
1453 * context switch on an unsuccessful wait instruction since we always
1456 GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw));
1458 if (*execlists->active) {
1459 GEM_BUG_ON(!ctx_away_valid);
1460 return CSB_COMPLETE;
1466 static inline enum csb_step
1467 gen8_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
1469 unsigned int status = *csb;
1471 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
1474 if (status & GEN8_CTX_STATUS_PREEMPTED)
1477 if (*execlists->active)
1478 return CSB_COMPLETE;
1483 static void process_csb(struct intel_engine_cs *engine)
1485 struct intel_engine_execlists * const execlists = &engine->execlists;
1486 const u32 * const buf = execlists->csb_status;
1487 const u8 num_entries = execlists->csb_size;
1490 GEM_BUG_ON(USES_GUC_SUBMISSION(engine->i915));
1493 * Note that csb_write, csb_status may be either in HWSP or mmio.
1494 * When reading from the csb_write mmio register, we have to be
1495 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
1496 * the low 4bits. As it happens we know the next 4bits are always
1497 * zero and so we can simply masked off the low u8 of the register
1498 * and treat it identically to reading from the HWSP (without having
1499 * to use explicit shifting and masking, and probably bifurcating
1500 * the code to handle the legacy mmio read).
1502 head = execlists->csb_head;
1503 tail = READ_ONCE(*execlists->csb_write);
1504 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
1505 if (unlikely(head == tail))
1509 * Hopefully paired with a wmb() in HW!
1511 * We must complete the read of the write pointer before any reads
1512 * from the CSB, so that we do not see stale values. Without an rmb
1513 * (lfence) the HW may speculatively perform the CSB[] reads *before*
1514 * we perform the READ_ONCE(*csb_write).
1519 enum csb_step csb_step;
1521 if (++head == num_entries)
1525 * We are flying near dragons again.
1527 * We hold a reference to the request in execlist_port[]
1528 * but no more than that. We are operating in softirq
1529 * context and so cannot hold any mutex or sleep. That
1530 * prevents us stopping the requests we are processing
1531 * in port[] from being retired simultaneously (the
1532 * breadcrumb will be complete before we see the
1533 * context-switch). As we only hold the reference to the
1534 * request, any pointer chasing underneath the request
1535 * is subject to a potential use-after-free. Thus we
1536 * store all of the bookkeeping within port[] as
1537 * required, and avoid using unguarded pointers beneath
1538 * request itself. The same applies to the atomic
1542 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x\n",
1544 buf[2 * head + 0], buf[2 * head + 1]);
1546 if (INTEL_GEN(engine->i915) >= 12)
1547 csb_step = gen12_csb_parse(execlists, buf + 2 * head);
1549 csb_step = gen8_csb_parse(execlists, buf + 2 * head);
1552 case CSB_PREEMPT: /* cancel old inflight, prepare for switch */
1553 trace_ports(execlists, "preempted", execlists->active);
1555 while (*execlists->active)
1556 execlists_schedule_out(*execlists->active++);
1559 case CSB_PROMOTE: /* switch pending to inflight */
1560 GEM_BUG_ON(*execlists->active);
1561 GEM_BUG_ON(!assert_pending_valid(execlists, "promote"));
1563 memcpy(execlists->inflight,
1565 execlists_num_ports(execlists) *
1566 sizeof(*execlists->pending));
1568 if (enable_timeslice(execlists))
1569 mod_timer(&execlists->timer, jiffies + 1);
1571 if (!inject_preempt_hang(execlists))
1572 ring_set_paused(engine, 0);
1574 WRITE_ONCE(execlists->pending[0], NULL);
1577 case CSB_COMPLETE: /* port0 completed, advanced to port1 */
1578 trace_ports(execlists, "completed", execlists->active);
1581 * We rely on the hardware being strongly
1582 * ordered, that the breadcrumb write is
1583 * coherent (visible from the CPU) before the
1584 * user interrupt and CSB is processed.
1586 GEM_BUG_ON(!i915_request_completed(*execlists->active) &&
1587 !reset_in_progress(execlists));
1588 execlists_schedule_out(*execlists->active++);
1590 GEM_BUG_ON(execlists->active - execlists->inflight >
1591 execlists_num_ports(execlists));
1597 } while (head != tail);
1599 execlists->csb_head = head;
1602 * Gen11 has proven to fail wrt global observation point between
1603 * entry and tail update, failing on the ordering and thus
1604 * we see an old entry in the context status buffer.
1606 * Forcibly evict out entries for the next gpu csb update,
1607 * to increase the odds that we get a fresh entries with non
1608 * working hardware. The cost for doing so comes out mostly with
1609 * the wash as hardware, working or not, will need to do the
1610 * invalidation before.
1612 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
1615 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
1617 lockdep_assert_held(&engine->active.lock);
1618 if (!engine->execlists.pending[0]) {
1619 rcu_read_lock(); /* protect peeking at execlists->active */
1620 execlists_dequeue(engine);
1626 * Check the unread Context Status Buffers and manage the submission of new
1627 * contexts to the ELSP accordingly.
1629 static void execlists_submission_tasklet(unsigned long data)
1631 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1632 unsigned long flags;
1634 process_csb(engine);
1635 if (!READ_ONCE(engine->execlists.pending[0])) {
1636 spin_lock_irqsave(&engine->active.lock, flags);
1637 __execlists_submission_tasklet(engine);
1638 spin_unlock_irqrestore(&engine->active.lock, flags);
1642 static void execlists_submission_timer(struct timer_list *timer)
1644 struct intel_engine_cs *engine =
1645 from_timer(engine, timer, execlists.timer);
1647 /* Kick the tasklet for some interrupt coalescing and reset handling */
1648 tasklet_hi_schedule(&engine->execlists.tasklet);
1651 static void queue_request(struct intel_engine_cs *engine,
1652 struct i915_sched_node *node,
1655 GEM_BUG_ON(!list_empty(&node->link));
1656 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio));
1659 static void __submit_queue_imm(struct intel_engine_cs *engine)
1661 struct intel_engine_execlists * const execlists = &engine->execlists;
1663 if (reset_in_progress(execlists))
1664 return; /* defer until we restart the engine following reset */
1666 if (execlists->tasklet.func == execlists_submission_tasklet)
1667 __execlists_submission_tasklet(engine);
1669 tasklet_hi_schedule(&execlists->tasklet);
1672 static void submit_queue(struct intel_engine_cs *engine,
1673 const struct i915_request *rq)
1675 struct intel_engine_execlists *execlists = &engine->execlists;
1677 if (rq_prio(rq) <= execlists->queue_priority_hint)
1680 execlists->queue_priority_hint = rq_prio(rq);
1681 __submit_queue_imm(engine);
1684 static void execlists_submit_request(struct i915_request *request)
1686 struct intel_engine_cs *engine = request->engine;
1687 unsigned long flags;
1689 /* Will be called from irq-context when using foreign fences. */
1690 spin_lock_irqsave(&engine->active.lock, flags);
1692 queue_request(engine, &request->sched, rq_prio(request));
1694 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1695 GEM_BUG_ON(list_empty(&request->sched.link));
1697 submit_queue(engine, request);
1699 spin_unlock_irqrestore(&engine->active.lock, flags);
1702 static void __execlists_context_fini(struct intel_context *ce)
1704 intel_ring_put(ce->ring);
1705 i915_vma_put(ce->state);
1708 static void execlists_context_destroy(struct kref *kref)
1710 struct intel_context *ce = container_of(kref, typeof(*ce), ref);
1712 GEM_BUG_ON(!i915_active_is_idle(&ce->active));
1713 GEM_BUG_ON(intel_context_is_pinned(ce));
1716 __execlists_context_fini(ce);
1718 intel_context_fini(ce);
1719 intel_context_free(ce);
1723 set_redzone(void *vaddr, const struct intel_engine_cs *engine)
1725 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1728 vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
1729 vaddr += engine->context_size;
1731 memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
1735 check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
1737 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1740 vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
1741 vaddr += engine->context_size;
1743 if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE))
1744 dev_err_once(engine->i915->drm.dev,
1745 "%s context redzone overwritten!\n",
1749 static void execlists_context_unpin(struct intel_context *ce)
1751 check_redzone((void *)ce->lrc_reg_state - LRC_STATE_PN * PAGE_SIZE,
1754 i915_gem_context_unpin_hw_id(ce->gem_context);
1755 i915_gem_object_unpin_map(ce->state->obj);
1756 intel_ring_reset(ce->ring, ce->ring->tail);
1760 __execlists_update_reg_state(struct intel_context *ce,
1761 struct intel_engine_cs *engine)
1763 struct intel_ring *ring = ce->ring;
1764 u32 *regs = ce->lrc_reg_state;
1766 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
1767 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
1769 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma);
1770 regs[CTX_RING_HEAD + 1] = ring->head;
1771 regs[CTX_RING_TAIL + 1] = ring->tail;
1774 if (engine->class == RENDER_CLASS) {
1775 regs[CTX_R_PWR_CLK_STATE + 1] =
1776 intel_sseu_make_rpcs(engine->i915, &ce->sseu);
1778 i915_oa_init_reg_state(engine, ce, regs);
1783 __execlists_context_pin(struct intel_context *ce,
1784 struct intel_engine_cs *engine)
1789 GEM_BUG_ON(!ce->state);
1791 ret = intel_context_active_acquire(ce);
1794 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
1796 vaddr = i915_gem_object_pin_map(ce->state->obj,
1797 i915_coherent_map_type(engine->i915) |
1799 if (IS_ERR(vaddr)) {
1800 ret = PTR_ERR(vaddr);
1804 ret = i915_gem_context_pin_hw_id(ce->gem_context);
1808 ce->lrc_desc = lrc_descriptor(ce, engine);
1809 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1810 __execlists_update_reg_state(ce, engine);
1815 i915_gem_object_unpin_map(ce->state->obj);
1817 intel_context_active_release(ce);
1822 static int execlists_context_pin(struct intel_context *ce)
1824 return __execlists_context_pin(ce, ce->engine);
1827 static int execlists_context_alloc(struct intel_context *ce)
1829 return __execlists_context_alloc(ce, ce->engine);
1832 static void execlists_context_reset(struct intel_context *ce)
1835 * Because we emit WA_TAIL_DWORDS there may be a disparity
1836 * between our bookkeeping in ce->ring->head and ce->ring->tail and
1837 * that stored in context. As we only write new commands from
1838 * ce->ring->tail onwards, everything before that is junk. If the GPU
1839 * starts reading from its RING_HEAD from the context, it may try to
1840 * execute that junk and die.
1842 * The contexts that are stilled pinned on resume belong to the
1843 * kernel, and are local to each engine. All other contexts will
1844 * have their head/tail sanitized upon pinning before use, so they
1845 * will never see garbage,
1847 * So to avoid that we reset the context images upon resume. For
1848 * simplicity, we just zero everything out.
1850 intel_ring_reset(ce->ring, 0);
1851 __execlists_update_reg_state(ce, ce->engine);
1854 static const struct intel_context_ops execlists_context_ops = {
1855 .alloc = execlists_context_alloc,
1857 .pin = execlists_context_pin,
1858 .unpin = execlists_context_unpin,
1860 .enter = intel_context_enter_engine,
1861 .exit = intel_context_exit_engine,
1863 .reset = execlists_context_reset,
1864 .destroy = execlists_context_destroy,
1867 static int gen8_emit_init_breadcrumb(struct i915_request *rq)
1871 GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb);
1873 cs = intel_ring_begin(rq, 6);
1878 * Check if we have been preempted before we even get started.
1880 * After this point i915_request_started() reports true, even if
1881 * we get preempted and so are no longer running.
1883 *cs++ = MI_ARB_CHECK;
1886 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1887 *cs++ = rq->timeline->hwsp_offset;
1889 *cs++ = rq->fence.seqno - 1;
1891 intel_ring_advance(rq, cs);
1893 /* Record the updated position of the request's payload */
1894 rq->infix = intel_ring_offset(rq, cs);
1899 static int emit_pdps(struct i915_request *rq)
1901 const struct intel_engine_cs * const engine = rq->engine;
1902 struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(rq->hw_context->vm);
1906 GEM_BUG_ON(intel_vgpu_active(rq->i915));
1909 * Beware ye of the dragons, this sequence is magic!
1911 * Small changes to this sequence can cause anything from
1912 * GPU hangs to forcewake errors and machine lockups!
1915 /* Flush any residual operations from the context load */
1916 err = engine->emit_flush(rq, EMIT_FLUSH);
1920 /* Magic required to prevent forcewake errors! */
1921 err = engine->emit_flush(rq, EMIT_INVALIDATE);
1925 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
1929 /* Ensure the LRI have landed before we invalidate & continue */
1930 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
1931 for (i = GEN8_3LVL_PDPES; i--; ) {
1932 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1933 u32 base = engine->mmio_base;
1935 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
1936 *cs++ = upper_32_bits(pd_daddr);
1937 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
1938 *cs++ = lower_32_bits(pd_daddr);
1942 intel_ring_advance(rq, cs);
1944 /* Be doubly sure the LRI have landed before proceeding */
1945 err = engine->emit_flush(rq, EMIT_FLUSH);
1949 /* Re-invalidate the TLB for luck */
1950 return engine->emit_flush(rq, EMIT_INVALIDATE);
1953 static int execlists_request_alloc(struct i915_request *request)
1957 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context));
1960 * Flush enough space to reduce the likelihood of waiting after
1961 * we start building the request - in which case we will just
1962 * have to repeat work.
1964 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1967 * Note that after this point, we have committed to using
1968 * this request as it is being used to both track the
1969 * state of engine initialisation and liveness of the
1970 * golden renderstate above. Think twice before you try
1971 * to cancel/unwind this request now.
1974 /* Unconditionally invalidate GPU caches and TLBs. */
1975 if (i915_vm_is_4lvl(request->hw_context->vm))
1976 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
1978 ret = emit_pdps(request);
1982 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1987 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1988 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1989 * but there is a slight complication as this is applied in WA batch where the
1990 * values are only initialized once so we cannot take register value at the
1991 * beginning and reuse it further; hence we save its value to memory, upload a
1992 * constant value with bit21 set and then we restore it back with the saved value.
1993 * To simplify the WA, a constant value is formed by using the default value
1994 * of this register. This shouldn't be a problem because we are only modifying
1995 * it for a short period and this batch in non-premptible. We can ofcourse
1996 * use additional instructions that read the actual value of the register
1997 * at that time and set our bit of interest but it makes the WA complicated.
1999 * This WA is also required for Gen9 so extracting as a function avoids
2003 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
2005 /* NB no one else is allowed to scribble over scratch + 256! */
2006 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
2007 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
2008 *batch++ = intel_gt_scratch_offset(engine->gt,
2009 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
2012 *batch++ = MI_LOAD_REGISTER_IMM(1);
2013 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
2014 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
2016 batch = gen8_emit_pipe_control(batch,
2017 PIPE_CONTROL_CS_STALL |
2018 PIPE_CONTROL_DC_FLUSH_ENABLE,
2021 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
2022 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
2023 *batch++ = intel_gt_scratch_offset(engine->gt,
2024 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
2030 static u32 slm_offset(struct intel_engine_cs *engine)
2032 return intel_gt_scratch_offset(engine->gt,
2033 INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA);
2037 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
2038 * initialized at the beginning and shared across all contexts but this field
2039 * helps us to have multiple batches at different offsets and select them based
2040 * on a criteria. At the moment this batch always start at the beginning of the page
2041 * and at this point we don't have multiple wa_ctx batch buffers.
2043 * The number of WA applied are not known at the beginning; we use this field
2044 * to return the no of DWORDS written.
2046 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
2047 * so it adds NOOPs as padding to make it cacheline aligned.
2048 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
2049 * makes a complete batch buffer.
2051 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
2053 /* WaDisableCtxRestoreArbitration:bdw,chv */
2054 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2056 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
2057 if (IS_BROADWELL(engine->i915))
2058 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
2060 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
2061 /* Actual scratch location is at 128 bytes offset */
2062 batch = gen8_emit_pipe_control(batch,
2063 PIPE_CONTROL_FLUSH_L3 |
2064 PIPE_CONTROL_GLOBAL_GTT_IVB |
2065 PIPE_CONTROL_CS_STALL |
2066 PIPE_CONTROL_QW_WRITE,
2067 slm_offset(engine));
2069 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2071 /* Pad to end of cacheline */
2072 while ((unsigned long)batch % CACHELINE_BYTES)
2076 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
2077 * execution depends on the length specified in terms of cache lines
2078 * in the register CTX_RCS_INDIRECT_CTX
2089 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
2091 GEM_BUG_ON(!count || count > 63);
2093 *batch++ = MI_LOAD_REGISTER_IMM(count);
2095 *batch++ = i915_mmio_reg_offset(lri->reg);
2096 *batch++ = lri->value;
2097 } while (lri++, --count);
2103 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
2105 static const struct lri lri[] = {
2106 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
2108 COMMON_SLICE_CHICKEN2,
2109 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
2116 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
2117 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
2123 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
2124 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
2128 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2130 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
2131 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
2133 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
2135 /* WaMediaPoolStateCmdInWABB:bxt,glk */
2136 if (HAS_POOLED_EU(engine->i915)) {
2138 * EU pool configuration is setup along with golden context
2139 * during context initialization. This value depends on
2140 * device type (2x6 or 3x6) and needs to be updated based
2141 * on which subslice is disabled especially for 2x6
2142 * devices, however it is safe to load default
2143 * configuration of 3x6 device instead of masking off
2144 * corresponding bits because HW ignores bits of a disabled
2145 * subslice and drops down to appropriate config. Please
2146 * see render_state_setup() in i915_gem_render_state.c for
2147 * possible configurations, to avoid duplication they are
2148 * not shown here again.
2150 *batch++ = GEN9_MEDIA_POOL_STATE;
2151 *batch++ = GEN9_MEDIA_POOL_ENABLE;
2152 *batch++ = 0x00777000;
2158 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2160 /* Pad to end of cacheline */
2161 while ((unsigned long)batch % CACHELINE_BYTES)
2168 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
2173 * WaPipeControlBefore3DStateSamplePattern: cnl
2175 * Ensure the engine is idle prior to programming a
2176 * 3DSTATE_SAMPLE_PATTERN during a context restore.
2178 batch = gen8_emit_pipe_control(batch,
2179 PIPE_CONTROL_CS_STALL,
2182 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
2183 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
2184 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
2185 * confusing. Since gen8_emit_pipe_control() already advances the
2186 * batch by 6 dwords, we advance the other 10 here, completing a
2187 * cacheline. It's not clear if the workaround requires this padding
2188 * before other commands, or if it's just the regular padding we would
2189 * already have for the workaround bb, so leave it here for now.
2191 for (i = 0; i < 10; i++)
2194 /* Pad to end of cacheline */
2195 while ((unsigned long)batch % CACHELINE_BYTES)
2201 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
2203 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
2205 struct drm_i915_gem_object *obj;
2206 struct i915_vma *vma;
2209 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_OBJ_SIZE);
2211 return PTR_ERR(obj);
2213 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
2219 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
2223 engine->wa_ctx.vma = vma;
2227 i915_gem_object_put(obj);
2231 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
2233 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
2236 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
2238 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
2240 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2241 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
2243 wa_bb_func_t wa_bb_fn[2];
2245 void *batch, *batch_ptr;
2249 if (engine->class != RENDER_CLASS)
2252 switch (INTEL_GEN(engine->i915)) {
2257 wa_bb_fn[0] = gen10_init_indirectctx_bb;
2261 wa_bb_fn[0] = gen9_init_indirectctx_bb;
2265 wa_bb_fn[0] = gen8_init_indirectctx_bb;
2269 MISSING_CASE(INTEL_GEN(engine->i915));
2273 ret = lrc_setup_wa_ctx(engine);
2275 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
2279 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
2280 batch = batch_ptr = kmap_atomic(page);
2283 * Emit the two workaround batch buffers, recording the offset from the
2284 * start of the workaround batch buffer object for each and their
2287 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
2288 wa_bb[i]->offset = batch_ptr - batch;
2289 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
2290 CACHELINE_BYTES))) {
2295 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
2296 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
2299 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
2301 kunmap_atomic(batch);
2303 lrc_destroy_wa_ctx(engine);
2308 static void enable_execlists(struct intel_engine_cs *engine)
2312 assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
2314 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
2316 if (INTEL_GEN(engine->i915) >= 11)
2317 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
2319 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
2320 ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);
2322 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
2324 ENGINE_WRITE_FW(engine,
2326 i915_ggtt_offset(engine->status_page.vma));
2327 ENGINE_POSTING_READ(engine, RING_HWS_PGA);
2330 static bool unexpected_starting_state(struct intel_engine_cs *engine)
2332 bool unexpected = false;
2334 if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
2335 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
2342 static int execlists_resume(struct intel_engine_cs *engine)
2344 intel_engine_apply_workarounds(engine);
2345 intel_engine_apply_whitelist(engine);
2347 intel_mocs_init_engine(engine);
2349 intel_engine_reset_breadcrumbs(engine);
2351 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
2352 struct drm_printer p = drm_debug_printer(__func__);
2354 intel_engine_dump(engine, &p, NULL);
2357 enable_execlists(engine);
2362 static void execlists_reset_prepare(struct intel_engine_cs *engine)
2364 struct intel_engine_execlists * const execlists = &engine->execlists;
2365 unsigned long flags;
2367 GEM_TRACE("%s: depth<-%d\n", engine->name,
2368 atomic_read(&execlists->tasklet.count));
2371 * Prevent request submission to the hardware until we have
2372 * completed the reset in i915_gem_reset_finish(). If a request
2373 * is completed by one engine, it may then queue a request
2374 * to a second via its execlists->tasklet *just* as we are
2375 * calling engine->resume() and also writing the ELSP.
2376 * Turning off the execlists->tasklet until the reset is over
2377 * prevents the race.
2379 __tasklet_disable_sync_once(&execlists->tasklet);
2380 GEM_BUG_ON(!reset_in_progress(execlists));
2382 /* And flush any current direct submission. */
2383 spin_lock_irqsave(&engine->active.lock, flags);
2384 spin_unlock_irqrestore(&engine->active.lock, flags);
2387 * We stop engines, otherwise we might get failed reset and a
2388 * dead gpu (on elk). Also as modern gpu as kbl can suffer
2389 * from system hang if batchbuffer is progressing when
2390 * the reset is issued, regardless of READY_TO_RESET ack.
2391 * Thus assume it is best to stop engines on all gens
2392 * where we have a gpu reset.
2394 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
2396 * FIXME: Wa for more modern gens needs to be validated
2398 intel_engine_stop_cs(engine);
2401 static void reset_csb_pointers(struct intel_engine_cs *engine)
2403 struct intel_engine_execlists * const execlists = &engine->execlists;
2404 const unsigned int reset_value = execlists->csb_size - 1;
2406 ring_set_paused(engine, 0);
2409 * After a reset, the HW starts writing into CSB entry [0]. We
2410 * therefore have to set our HEAD pointer back one entry so that
2411 * the *first* entry we check is entry 0. To complicate this further,
2412 * as we don't wait for the first interrupt after reset, we have to
2413 * fake the HW write to point back to the last entry so that our
2414 * inline comparison of our cached head position against the last HW
2415 * write works even before the first interrupt.
2417 execlists->csb_head = reset_value;
2418 WRITE_ONCE(*execlists->csb_write, reset_value);
2419 wmb(); /* Make sure this is visible to HW (paranoia?) */
2421 invalidate_csb_entries(&execlists->csb_status[0],
2422 &execlists->csb_status[reset_value]);
2425 static struct i915_request *active_request(struct i915_request *rq)
2427 const struct intel_context * const ce = rq->hw_context;
2428 struct i915_request *active = NULL;
2429 struct list_head *list;
2431 if (!i915_request_is_active(rq)) /* unwound, but incomplete! */
2434 list = &rq->timeline->requests;
2435 list_for_each_entry_from_reverse(rq, list, link) {
2436 if (i915_request_completed(rq))
2439 if (rq->hw_context != ce)
2448 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
2450 struct intel_engine_execlists * const execlists = &engine->execlists;
2451 struct intel_context *ce;
2452 struct i915_request *rq;
2455 process_csb(engine); /* drain preemption events */
2457 /* Following the reset, we need to reload the CSB read/write pointers */
2458 reset_csb_pointers(engine);
2461 * Save the currently executing context, even if we completed
2462 * its request, it was still running at the time of the
2463 * reset and will have been clobbered.
2465 rq = execlists_active(execlists);
2469 ce = rq->hw_context;
2470 GEM_BUG_ON(i915_active_is_idle(&ce->active));
2471 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
2472 rq = active_request(rq);
2474 ce->ring->head = ce->ring->tail;
2478 ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
2481 * If this request hasn't started yet, e.g. it is waiting on a
2482 * semaphore, we need to avoid skipping the request or else we
2483 * break the signaling chain. However, if the context is corrupt
2484 * the request will not restart and we will be stuck with a wedged
2485 * device. It is quite often the case that if we issue a reset
2486 * while the GPU is loading the context image, that the context
2487 * image becomes corrupt.
2489 * Otherwise, if we have not started yet, the request should replay
2490 * perfectly and we do not need to flag the result as being erroneous.
2492 if (!i915_request_started(rq))
2496 * If the request was innocent, we leave the request in the ELSP
2497 * and will try to replay it on restarting. The context image may
2498 * have been corrupted by the reset, in which case we may have
2499 * to service a new GPU hang, but more likely we can continue on
2502 * If the request was guilty, we presume the context is corrupt
2503 * and have to at least restore the RING register in the context
2504 * image back to the expected values to skip over the guilty request.
2506 __i915_request_reset(rq, stalled);
2511 * We want a simple context + ring to execute the breadcrumb update.
2512 * We cannot rely on the context being intact across the GPU hang,
2513 * so clear it and rebuild just what we need for the breadcrumb.
2514 * All pending requests for this context will be zapped, and any
2515 * future request will be after userspace has had the opportunity
2516 * to recreate its own state.
2518 regs = ce->lrc_reg_state;
2519 if (engine->pinned_default_state) {
2520 memcpy(regs, /* skip restoring the vanilla PPHWSP */
2521 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
2522 engine->context_size - PAGE_SIZE);
2524 execlists_init_reg_state(regs, ce, engine, ce->ring);
2527 GEM_TRACE("%s replay {head:%04x, tail:%04x\n",
2528 engine->name, ce->ring->head, ce->ring->tail);
2529 intel_ring_update_space(ce->ring);
2530 __execlists_update_reg_state(ce, engine);
2533 /* Push back any incomplete requests for replay after the reset. */
2534 cancel_port_requests(execlists);
2535 __unwind_incomplete_requests(engine);
2538 static void execlists_reset(struct intel_engine_cs *engine, bool stalled)
2540 unsigned long flags;
2542 GEM_TRACE("%s\n", engine->name);
2544 spin_lock_irqsave(&engine->active.lock, flags);
2546 __execlists_reset(engine, stalled);
2548 spin_unlock_irqrestore(&engine->active.lock, flags);
2551 static void nop_submission_tasklet(unsigned long data)
2553 /* The driver is wedged; don't process any more events. */
2556 static void execlists_cancel_requests(struct intel_engine_cs *engine)
2558 struct intel_engine_execlists * const execlists = &engine->execlists;
2559 struct i915_request *rq, *rn;
2561 unsigned long flags;
2563 GEM_TRACE("%s\n", engine->name);
2566 * Before we call engine->cancel_requests(), we should have exclusive
2567 * access to the submission state. This is arranged for us by the
2568 * caller disabling the interrupt generation, the tasklet and other
2569 * threads that may then access the same state, giving us a free hand
2570 * to reset state. However, we still need to let lockdep be aware that
2571 * we know this state may be accessed in hardirq context, so we
2572 * disable the irq around this manipulation and we want to keep
2573 * the spinlock focused on its duties and not accidentally conflate
2574 * coverage to the submission's irq state. (Similarly, although we
2575 * shouldn't need to disable irq around the manipulation of the
2576 * submission's irq state, we also wish to remind ourselves that
2579 spin_lock_irqsave(&engine->active.lock, flags);
2581 __execlists_reset(engine, true);
2583 /* Mark all executing requests as skipped. */
2584 list_for_each_entry(rq, &engine->active.requests, sched.link)
2587 /* Flush the queued requests to the timeline list (for retiring). */
2588 while ((rb = rb_first_cached(&execlists->queue))) {
2589 struct i915_priolist *p = to_priolist(rb);
2592 priolist_for_each_request_consume(rq, rn, p, i) {
2594 __i915_request_submit(rq);
2597 rb_erase_cached(&p->node, &execlists->queue);
2598 i915_priolist_free(p);
2601 /* Cancel all attached virtual engines */
2602 while ((rb = rb_first_cached(&execlists->virtual))) {
2603 struct virtual_engine *ve =
2604 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
2606 rb_erase_cached(rb, &execlists->virtual);
2609 spin_lock(&ve->base.active.lock);
2610 rq = fetch_and_zero(&ve->request);
2614 rq->engine = engine;
2615 __i915_request_submit(rq);
2617 ve->base.execlists.queue_priority_hint = INT_MIN;
2619 spin_unlock(&ve->base.active.lock);
2622 /* Remaining _unready_ requests will be nop'ed when submitted */
2624 execlists->queue_priority_hint = INT_MIN;
2625 execlists->queue = RB_ROOT_CACHED;
2627 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
2628 execlists->tasklet.func = nop_submission_tasklet;
2630 spin_unlock_irqrestore(&engine->active.lock, flags);
2633 static void execlists_reset_finish(struct intel_engine_cs *engine)
2635 struct intel_engine_execlists * const execlists = &engine->execlists;
2638 * After a GPU reset, we may have requests to replay. Do so now while
2639 * we still have the forcewake to be sure that the GPU is not allowed
2640 * to sleep before we restart and reload a context.
2642 GEM_BUG_ON(!reset_in_progress(execlists));
2643 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
2644 execlists->tasklet.func(execlists->tasklet.data);
2646 if (__tasklet_enable(&execlists->tasklet))
2647 /* And kick in case we missed a new request submission. */
2648 tasklet_hi_schedule(&execlists->tasklet);
2649 GEM_TRACE("%s: depth->%d\n", engine->name,
2650 atomic_read(&execlists->tasklet.count));
2653 static int gen8_emit_bb_start(struct i915_request *rq,
2654 u64 offset, u32 len,
2655 const unsigned int flags)
2659 cs = intel_ring_begin(rq, 4);
2664 * WaDisableCtxRestoreArbitration:bdw,chv
2666 * We don't need to perform MI_ARB_ENABLE as often as we do (in
2667 * particular all the gen that do not need the w/a at all!), if we
2668 * took care to make sure that on every switch into this context
2669 * (both ordinary and for preemption) that arbitrartion was enabled
2670 * we would be fine. However, for gen8 there is another w/a that
2671 * requires us to not preempt inside GPGPU execution, so we keep
2672 * arbitration disabled for gen8 batches. Arbitration will be
2673 * re-enabled before we close the request
2674 * (engine->emit_fini_breadcrumb).
2676 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2678 /* FIXME(BDW+): Address space and security selectors. */
2679 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2680 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
2681 *cs++ = lower_32_bits(offset);
2682 *cs++ = upper_32_bits(offset);
2684 intel_ring_advance(rq, cs);
2689 static int gen9_emit_bb_start(struct i915_request *rq,
2690 u64 offset, u32 len,
2691 const unsigned int flags)
2695 cs = intel_ring_begin(rq, 6);
2699 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2701 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2702 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
2703 *cs++ = lower_32_bits(offset);
2704 *cs++ = upper_32_bits(offset);
2706 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2709 intel_ring_advance(rq, cs);
2714 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
2716 ENGINE_WRITE(engine, RING_IMR,
2717 ~(engine->irq_enable_mask | engine->irq_keep_mask));
2718 ENGINE_POSTING_READ(engine, RING_IMR);
2721 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
2723 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
2726 static int gen8_emit_flush(struct i915_request *request, u32 mode)
2730 cs = intel_ring_begin(request, 4);
2734 cmd = MI_FLUSH_DW + 1;
2736 /* We always require a command barrier so that subsequent
2737 * commands, such as breadcrumb interrupts, are strictly ordered
2738 * wrt the contents of the write cache being flushed to memory
2739 * (and thus being coherent from the CPU).
2741 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2743 if (mode & EMIT_INVALIDATE) {
2744 cmd |= MI_INVALIDATE_TLB;
2745 if (request->engine->class == VIDEO_DECODE_CLASS)
2746 cmd |= MI_INVALIDATE_BSD;
2750 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2751 *cs++ = 0; /* upper addr */
2752 *cs++ = 0; /* value */
2753 intel_ring_advance(request, cs);
2758 static int gen8_emit_flush_render(struct i915_request *request,
2761 struct intel_engine_cs *engine = request->engine;
2763 intel_gt_scratch_offset(engine->gt,
2764 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
2765 bool vf_flush_wa = false, dc_flush_wa = false;
2769 flags |= PIPE_CONTROL_CS_STALL;
2771 if (mode & EMIT_FLUSH) {
2772 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
2773 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
2774 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
2775 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2778 if (mode & EMIT_INVALIDATE) {
2779 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2780 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2781 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2782 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2783 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2784 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2785 flags |= PIPE_CONTROL_QW_WRITE;
2786 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2789 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
2792 if (IS_GEN(request->i915, 9))
2795 /* WaForGAMHang:kbl */
2796 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2808 cs = intel_ring_begin(request, len);
2813 cs = gen8_emit_pipe_control(cs, 0, 0);
2816 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2819 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2822 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2824 intel_ring_advance(request, cs);
2829 static int gen11_emit_flush_render(struct i915_request *request,
2832 struct intel_engine_cs *engine = request->engine;
2833 const u32 scratch_addr =
2834 intel_gt_scratch_offset(engine->gt,
2835 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
2837 if (mode & EMIT_FLUSH) {
2841 flags |= PIPE_CONTROL_CS_STALL;
2843 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
2844 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
2845 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
2846 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
2847 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2848 flags |= PIPE_CONTROL_QW_WRITE;
2849 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2851 cs = intel_ring_begin(request, 6);
2855 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2856 intel_ring_advance(request, cs);
2859 if (mode & EMIT_INVALIDATE) {
2863 flags |= PIPE_CONTROL_CS_STALL;
2865 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
2866 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2867 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2868 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2869 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2870 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2871 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2872 flags |= PIPE_CONTROL_QW_WRITE;
2873 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2875 cs = intel_ring_begin(request, 6);
2879 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2880 intel_ring_advance(request, cs);
2887 * Reserve space for 2 NOOPs at the end of each request to be
2888 * used as a workaround for not being allowed to do lite
2889 * restore with HEAD==TAIL (WaIdleLiteRestore).
2891 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2893 /* Ensure there's always at least one preemption point per-request. */
2894 *cs++ = MI_ARB_CHECK;
2896 request->wa_tail = intel_ring_offset(request, cs);
2901 static u32 *emit_preempt_busywait(struct i915_request *request, u32 *cs)
2903 *cs++ = MI_SEMAPHORE_WAIT |
2904 MI_SEMAPHORE_GLOBAL_GTT |
2906 MI_SEMAPHORE_SAD_EQ_SDD;
2908 *cs++ = intel_hws_preempt_address(request->engine);
2914 static __always_inline u32*
2915 gen8_emit_fini_breadcrumb_footer(struct i915_request *request,
2918 *cs++ = MI_USER_INTERRUPT;
2920 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2921 if (intel_engine_has_semaphores(request->engine))
2922 cs = emit_preempt_busywait(request, cs);
2924 request->tail = intel_ring_offset(request, cs);
2925 assert_ring_tail_valid(request->ring, request->tail);
2927 return gen8_emit_wa_tail(request, cs);
2930 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
2932 cs = gen8_emit_ggtt_write(cs,
2933 request->fence.seqno,
2934 request->timeline->hwsp_offset,
2937 return gen8_emit_fini_breadcrumb_footer(request, cs);
2940 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2942 cs = gen8_emit_ggtt_write_rcs(cs,
2943 request->fence.seqno,
2944 request->timeline->hwsp_offset,
2945 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
2946 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
2947 PIPE_CONTROL_DC_FLUSH_ENABLE);
2949 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
2950 cs = gen8_emit_pipe_control(cs,
2951 PIPE_CONTROL_FLUSH_ENABLE |
2952 PIPE_CONTROL_CS_STALL,
2955 return gen8_emit_fini_breadcrumb_footer(request, cs);
2958 static u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *request,
2961 cs = gen8_emit_ggtt_write_rcs(cs,
2962 request->fence.seqno,
2963 request->timeline->hwsp_offset,
2964 PIPE_CONTROL_CS_STALL |
2965 PIPE_CONTROL_TILE_CACHE_FLUSH |
2966 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
2967 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
2968 PIPE_CONTROL_DC_FLUSH_ENABLE |
2969 PIPE_CONTROL_FLUSH_ENABLE);
2971 return gen8_emit_fini_breadcrumb_footer(request, cs);
2974 static void execlists_park(struct intel_engine_cs *engine)
2976 del_timer(&engine->execlists.timer);
2979 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
2981 engine->submit_request = execlists_submit_request;
2982 engine->cancel_requests = execlists_cancel_requests;
2983 engine->schedule = i915_schedule;
2984 engine->execlists.tasklet.func = execlists_submission_tasklet;
2986 engine->reset.prepare = execlists_reset_prepare;
2987 engine->reset.reset = execlists_reset;
2988 engine->reset.finish = execlists_reset_finish;
2990 engine->park = execlists_park;
2991 engine->unpark = NULL;
2993 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2994 if (!intel_vgpu_active(engine->i915)) {
2995 engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
2996 if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
2997 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
3001 static void execlists_destroy(struct intel_engine_cs *engine)
3003 intel_engine_cleanup_common(engine);
3004 lrc_destroy_wa_ctx(engine);
3009 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
3011 /* Default vfuncs which can be overriden by each engine. */
3013 engine->destroy = execlists_destroy;
3014 engine->resume = execlists_resume;
3016 engine->reset.prepare = execlists_reset_prepare;
3017 engine->reset.reset = execlists_reset;
3018 engine->reset.finish = execlists_reset_finish;
3020 engine->cops = &execlists_context_ops;
3021 engine->request_alloc = execlists_request_alloc;
3023 engine->emit_flush = gen8_emit_flush;
3024 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
3025 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
3027 engine->set_default_submission = intel_execlists_set_default_submission;
3029 if (INTEL_GEN(engine->i915) < 11) {
3030 engine->irq_enable = gen8_logical_ring_enable_irq;
3031 engine->irq_disable = gen8_logical_ring_disable_irq;
3034 * TODO: On Gen11 interrupt masks need to be clear
3035 * to allow C6 entry. Keep interrupts enabled at
3036 * and take the hit of generating extra interrupts
3037 * until a more refined solution exists.
3040 if (IS_GEN(engine->i915, 8))
3041 engine->emit_bb_start = gen8_emit_bb_start;
3043 engine->emit_bb_start = gen9_emit_bb_start;
3047 logical_ring_default_irqs(struct intel_engine_cs *engine)
3049 unsigned int shift = 0;
3051 if (INTEL_GEN(engine->i915) < 11) {
3052 const u8 irq_shifts[] = {
3053 [RCS0] = GEN8_RCS_IRQ_SHIFT,
3054 [BCS0] = GEN8_BCS_IRQ_SHIFT,
3055 [VCS0] = GEN8_VCS0_IRQ_SHIFT,
3056 [VCS1] = GEN8_VCS1_IRQ_SHIFT,
3057 [VECS0] = GEN8_VECS_IRQ_SHIFT,
3060 shift = irq_shifts[engine->id];
3063 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
3064 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
3067 static void rcs_submission_override(struct intel_engine_cs *engine)
3069 switch (INTEL_GEN(engine->i915)) {
3072 engine->emit_flush = gen11_emit_flush_render;
3073 engine->emit_fini_breadcrumb = gen11_emit_fini_breadcrumb_rcs;
3076 engine->emit_flush = gen8_emit_flush_render;
3077 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
3082 int intel_execlists_submission_setup(struct intel_engine_cs *engine)
3084 tasklet_init(&engine->execlists.tasklet,
3085 execlists_submission_tasklet, (unsigned long)engine);
3086 timer_setup(&engine->execlists.timer, execlists_submission_timer, 0);
3088 logical_ring_default_vfuncs(engine);
3089 logical_ring_default_irqs(engine);
3091 if (engine->class == RENDER_CLASS)
3092 rcs_submission_override(engine);
3097 int intel_execlists_submission_init(struct intel_engine_cs *engine)
3099 struct intel_engine_execlists * const execlists = &engine->execlists;
3100 struct drm_i915_private *i915 = engine->i915;
3101 struct intel_uncore *uncore = engine->uncore;
3102 u32 base = engine->mmio_base;
3105 ret = intel_engine_init_common(engine);
3109 if (intel_init_workaround_bb(engine))
3111 * We continue even if we fail to initialize WA batch
3112 * because we only expect rare glitches but nothing
3113 * critical to prevent us from using GPU
3115 DRM_ERROR("WA batch buffer initialization failed\n");
3117 if (HAS_LOGICAL_RING_ELSQ(i915)) {
3118 execlists->submit_reg = uncore->regs +
3119 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
3120 execlists->ctrl_reg = uncore->regs +
3121 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
3123 execlists->submit_reg = uncore->regs +
3124 i915_mmio_reg_offset(RING_ELSP(base));
3127 execlists->csb_status =
3128 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
3130 execlists->csb_write =
3131 &engine->status_page.addr[intel_hws_csb_write_index(i915)];
3133 if (INTEL_GEN(i915) < 11)
3134 execlists->csb_size = GEN8_CSB_ENTRIES;
3136 execlists->csb_size = GEN11_CSB_ENTRIES;
3138 reset_csb_pointers(engine);
3143 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
3145 u32 indirect_ctx_offset;
3147 switch (INTEL_GEN(engine->i915)) {
3149 MISSING_CASE(INTEL_GEN(engine->i915));
3152 indirect_ctx_offset =
3153 GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
3156 indirect_ctx_offset =
3157 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
3160 indirect_ctx_offset =
3161 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
3164 indirect_ctx_offset =
3165 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
3168 indirect_ctx_offset =
3169 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
3173 return indirect_ctx_offset;
3176 static void execlists_init_reg_state(u32 *regs,
3177 struct intel_context *ce,
3178 struct intel_engine_cs *engine,
3179 struct intel_ring *ring)
3181 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
3182 bool rcs = engine->class == RENDER_CLASS;
3183 u32 base = engine->mmio_base;
3186 * A context is actually a big batch buffer with several
3187 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
3188 * values we are setting here are only for the first context restore:
3189 * on a subsequent save, the GPU will recreate this batchbuffer with new
3190 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
3191 * we are not initializing here).
3193 * Must keep consistent with virtual_update_register_offsets().
3195 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
3196 MI_LRI_FORCE_POSTED;
3198 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
3199 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
3200 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
3201 if (INTEL_GEN(engine->i915) < 11) {
3202 regs[CTX_CONTEXT_CONTROL + 1] |=
3203 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
3204 CTX_CTRL_RS_CTX_ENABLE);
3206 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
3207 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
3208 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
3209 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
3210 RING_CTL_SIZE(ring->size) | RING_VALID);
3211 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
3212 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
3213 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
3214 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
3215 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
3216 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
3218 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
3220 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
3221 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
3222 RING_INDIRECT_CTX_OFFSET(base), 0);
3223 if (wa_ctx->indirect_ctx.size) {
3224 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
3226 regs[CTX_RCS_INDIRECT_CTX + 1] =
3227 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
3228 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
3230 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
3231 intel_lr_indirect_ctx_offset(engine) << 6;
3234 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
3235 if (wa_ctx->per_ctx.size) {
3236 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
3238 regs[CTX_BB_PER_CTX_PTR + 1] =
3239 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
3243 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
3245 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
3246 /* PDP values well be assigned later if needed */
3247 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
3248 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
3249 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0);
3250 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0);
3251 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0);
3252 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0);
3253 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0);
3254 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0);
3256 if (i915_vm_is_4lvl(&ppgtt->vm)) {
3257 /* 64b PPGTT (48bit canonical)
3258 * PDP0_DESCRIPTOR contains the base address to PML4 and
3259 * other PDP Descriptors are ignored.
3261 ASSIGN_CTX_PML4(ppgtt, regs);
3263 ASSIGN_CTX_PDP(ppgtt, regs, 3);
3264 ASSIGN_CTX_PDP(ppgtt, regs, 2);
3265 ASSIGN_CTX_PDP(ppgtt, regs, 1);
3266 ASSIGN_CTX_PDP(ppgtt, regs, 0);
3270 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
3271 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
3274 regs[CTX_END] = MI_BATCH_BUFFER_END;
3275 if (INTEL_GEN(engine->i915) >= 10)
3276 regs[CTX_END] |= BIT(0);
3280 populate_lr_context(struct intel_context *ce,
3281 struct drm_i915_gem_object *ctx_obj,
3282 struct intel_engine_cs *engine,
3283 struct intel_ring *ring)
3289 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
3290 if (IS_ERR(vaddr)) {
3291 ret = PTR_ERR(vaddr);
3292 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
3296 set_redzone(vaddr, engine);
3298 if (engine->default_state) {
3300 * We only want to copy over the template context state;
3301 * skipping over the headers reserved for GuC communication,
3302 * leaving those as zero.
3304 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
3307 defaults = i915_gem_object_pin_map(engine->default_state,
3309 if (IS_ERR(defaults)) {
3310 ret = PTR_ERR(defaults);
3314 memcpy(vaddr + start, defaults + start, engine->context_size);
3315 i915_gem_object_unpin_map(engine->default_state);
3318 /* The second page of the context object contains some fields which must
3319 * be set up prior to the first execution. */
3320 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
3321 execlists_init_reg_state(regs, ce, engine, ring);
3322 if (!engine->default_state)
3323 regs[CTX_CONTEXT_CONTROL + 1] |=
3324 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
3328 __i915_gem_object_flush_map(ctx_obj,
3329 LRC_HEADER_PAGES * PAGE_SIZE,
3330 engine->context_size);
3331 i915_gem_object_unpin_map(ctx_obj);
3335 static int __execlists_context_alloc(struct intel_context *ce,
3336 struct intel_engine_cs *engine)
3338 struct drm_i915_gem_object *ctx_obj;
3339 struct intel_ring *ring;
3340 struct i915_vma *vma;
3344 GEM_BUG_ON(ce->state);
3345 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
3348 * Before the actual start of the context image, we insert a few pages
3349 * for our own use and for sharing with the GuC.
3351 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
3352 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
3353 context_size += I915_GTT_PAGE_SIZE; /* for redzone */
3355 ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
3356 if (IS_ERR(ctx_obj))
3357 return PTR_ERR(ctx_obj);
3359 vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
3362 goto error_deref_obj;
3365 if (!ce->timeline) {
3366 struct intel_timeline *tl;
3368 tl = intel_timeline_create(engine->gt, NULL);
3371 goto error_deref_obj;
3377 ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
3379 ret = PTR_ERR(ring);
3380 goto error_deref_obj;
3383 ret = populate_lr_context(ce, ctx_obj, engine, ring);
3385 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
3386 goto error_ring_free;
3395 intel_ring_put(ring);
3397 i915_gem_object_put(ctx_obj);
3401 static struct list_head *virtual_queue(struct virtual_engine *ve)
3403 return &ve->base.execlists.default_priolist.requests[0];
3406 static void virtual_context_destroy(struct kref *kref)
3408 struct virtual_engine *ve =
3409 container_of(kref, typeof(*ve), context.ref);
3412 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
3413 GEM_BUG_ON(ve->request);
3414 GEM_BUG_ON(ve->context.inflight);
3416 for (n = 0; n < ve->num_siblings; n++) {
3417 struct intel_engine_cs *sibling = ve->siblings[n];
3418 struct rb_node *node = &ve->nodes[sibling->id].rb;
3420 if (RB_EMPTY_NODE(node))
3423 spin_lock_irq(&sibling->active.lock);
3425 /* Detachment is lazily performed in the execlists tasklet */
3426 if (!RB_EMPTY_NODE(node))
3427 rb_erase_cached(node, &sibling->execlists.virtual);
3429 spin_unlock_irq(&sibling->active.lock);
3431 GEM_BUG_ON(__tasklet_is_scheduled(&ve->base.execlists.tasklet));
3433 if (ve->context.state)
3434 __execlists_context_fini(&ve->context);
3435 intel_context_fini(&ve->context);
3441 static void virtual_engine_initial_hint(struct virtual_engine *ve)
3446 * Pick a random sibling on starting to help spread the load around.
3448 * New contexts are typically created with exactly the same order
3449 * of siblings, and often started in batches. Due to the way we iterate
3450 * the array of sibling when submitting requests, sibling[0] is
3451 * prioritised for dequeuing. If we make sure that sibling[0] is fairly
3452 * randomised across the system, we also help spread the load by the
3453 * first engine we inspect being different each time.
3455 * NB This does not force us to execute on this engine, it will just
3456 * typically be the first we inspect for submission.
3458 swp = prandom_u32_max(ve->num_siblings);
3462 swap(ve->siblings[swp], ve->siblings[0]);
3463 virtual_update_register_offsets(ve->context.lrc_reg_state,
3467 static int virtual_context_pin(struct intel_context *ce)
3469 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3472 /* Note: we must use a real engine class for setting up reg state */
3473 err = __execlists_context_pin(ce, ve->siblings[0]);
3477 virtual_engine_initial_hint(ve);
3481 static void virtual_context_enter(struct intel_context *ce)
3483 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3486 for (n = 0; n < ve->num_siblings; n++)
3487 intel_engine_pm_get(ve->siblings[n]);
3489 intel_timeline_enter(ce->timeline);
3492 static void virtual_context_exit(struct intel_context *ce)
3494 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3497 intel_timeline_exit(ce->timeline);
3499 for (n = 0; n < ve->num_siblings; n++)
3500 intel_engine_pm_put(ve->siblings[n]);
3503 static const struct intel_context_ops virtual_context_ops = {
3504 .pin = virtual_context_pin,
3505 .unpin = execlists_context_unpin,
3507 .enter = virtual_context_enter,
3508 .exit = virtual_context_exit,
3510 .destroy = virtual_context_destroy,
3513 static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve)
3515 struct i915_request *rq;
3516 intel_engine_mask_t mask;
3518 rq = READ_ONCE(ve->request);
3522 /* The rq is ready for submission; rq->execution_mask is now stable. */
3523 mask = rq->execution_mask;
3524 if (unlikely(!mask)) {
3525 /* Invalid selection, submit to a random engine in error */
3526 i915_request_skip(rq, -ENODEV);
3527 mask = ve->siblings[0]->mask;
3530 GEM_TRACE("%s: rq=%llx:%lld, mask=%x, prio=%d\n",
3532 rq->fence.context, rq->fence.seqno,
3533 mask, ve->base.execlists.queue_priority_hint);
3538 static void virtual_submission_tasklet(unsigned long data)
3540 struct virtual_engine * const ve = (struct virtual_engine *)data;
3541 const int prio = ve->base.execlists.queue_priority_hint;
3542 intel_engine_mask_t mask;
3546 mask = virtual_submission_mask(ve);
3548 if (unlikely(!mask))
3551 local_irq_disable();
3552 for (n = 0; READ_ONCE(ve->request) && n < ve->num_siblings; n++) {
3553 struct intel_engine_cs *sibling = ve->siblings[n];
3554 struct ve_node * const node = &ve->nodes[sibling->id];
3555 struct rb_node **parent, *rb;
3558 if (unlikely(!(mask & sibling->mask))) {
3559 if (!RB_EMPTY_NODE(&node->rb)) {
3560 spin_lock(&sibling->active.lock);
3561 rb_erase_cached(&node->rb,
3562 &sibling->execlists.virtual);
3563 RB_CLEAR_NODE(&node->rb);
3564 spin_unlock(&sibling->active.lock);
3569 spin_lock(&sibling->active.lock);
3571 if (!RB_EMPTY_NODE(&node->rb)) {
3573 * Cheat and avoid rebalancing the tree if we can
3574 * reuse this node in situ.
3576 first = rb_first_cached(&sibling->execlists.virtual) ==
3578 if (prio == node->prio || (prio > node->prio && first))
3581 rb_erase_cached(&node->rb, &sibling->execlists.virtual);
3586 parent = &sibling->execlists.virtual.rb_root.rb_node;
3588 struct ve_node *other;
3591 other = rb_entry(rb, typeof(*other), rb);
3592 if (prio > other->prio) {
3593 parent = &rb->rb_left;
3595 parent = &rb->rb_right;
3600 rb_link_node(&node->rb, rb, parent);
3601 rb_insert_color_cached(&node->rb,
3602 &sibling->execlists.virtual,
3606 GEM_BUG_ON(RB_EMPTY_NODE(&node->rb));
3608 if (first && prio > sibling->execlists.queue_priority_hint) {
3609 sibling->execlists.queue_priority_hint = prio;
3610 tasklet_hi_schedule(&sibling->execlists.tasklet);
3613 spin_unlock(&sibling->active.lock);
3618 static void virtual_submit_request(struct i915_request *rq)
3620 struct virtual_engine *ve = to_virtual_engine(rq->engine);
3622 GEM_TRACE("%s: rq=%llx:%lld\n",
3627 GEM_BUG_ON(ve->base.submit_request != virtual_submit_request);
3629 GEM_BUG_ON(ve->request);
3630 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
3632 ve->base.execlists.queue_priority_hint = rq_prio(rq);
3633 WRITE_ONCE(ve->request, rq);
3635 list_move_tail(&rq->sched.link, virtual_queue(ve));
3637 tasklet_schedule(&ve->base.execlists.tasklet);
3640 static struct ve_bond *
3641 virtual_find_bond(struct virtual_engine *ve,
3642 const struct intel_engine_cs *master)
3646 for (i = 0; i < ve->num_bonds; i++) {
3647 if (ve->bonds[i].master == master)
3648 return &ve->bonds[i];
3655 virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
3657 struct virtual_engine *ve = to_virtual_engine(rq->engine);
3658 intel_engine_mask_t allowed, exec;
3659 struct ve_bond *bond;
3661 allowed = ~to_request(signal)->engine->mask;
3663 bond = virtual_find_bond(ve, to_request(signal)->engine);
3665 allowed &= bond->sibling_mask;
3667 /* Restrict the bonded request to run on only the available engines */
3668 exec = READ_ONCE(rq->execution_mask);
3669 while (!try_cmpxchg(&rq->execution_mask, &exec, exec & allowed))
3672 /* Prevent the master from being re-run on the bonded engines */
3673 to_request(signal)->execution_mask &= ~allowed;
3676 struct intel_context *
3677 intel_execlists_create_virtual(struct i915_gem_context *ctx,
3678 struct intel_engine_cs **siblings,
3681 struct virtual_engine *ve;
3686 return ERR_PTR(-EINVAL);
3689 return intel_context_create(ctx, siblings[0]);
3691 ve = kzalloc(struct_size(ve, siblings, count), GFP_KERNEL);
3693 return ERR_PTR(-ENOMEM);
3695 ve->base.i915 = ctx->i915;
3696 ve->base.gt = siblings[0]->gt;
3698 ve->base.class = OTHER_CLASS;
3699 ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
3700 ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
3703 * The decision on whether to submit a request using semaphores
3704 * depends on the saturated state of the engine. We only compute
3705 * this during HW submission of the request, and we need for this
3706 * state to be globally applied to all requests being submitted
3707 * to this engine. Virtual engines encompass more than one physical
3708 * engine and so we cannot accurately tell in advance if one of those
3709 * engines is already saturated and so cannot afford to use a semaphore
3710 * and be pessimized in priority for doing so -- if we are the only
3711 * context using semaphores after all other clients have stopped, we
3712 * will be starved on the saturated system. Such a global switch for
3713 * semaphores is less than ideal, but alas is the current compromise.
3715 ve->base.saturated = ALL_ENGINES;
3717 snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
3719 intel_engine_init_active(&ve->base, ENGINE_VIRTUAL);
3721 intel_engine_init_execlists(&ve->base);
3723 ve->base.cops = &virtual_context_ops;
3724 ve->base.request_alloc = execlists_request_alloc;
3726 ve->base.schedule = i915_schedule;
3727 ve->base.submit_request = virtual_submit_request;
3728 ve->base.bond_execute = virtual_bond_execute;
3730 INIT_LIST_HEAD(virtual_queue(ve));
3731 ve->base.execlists.queue_priority_hint = INT_MIN;
3732 tasklet_init(&ve->base.execlists.tasklet,
3733 virtual_submission_tasklet,
3736 intel_context_init(&ve->context, ctx, &ve->base);
3738 for (n = 0; n < count; n++) {
3739 struct intel_engine_cs *sibling = siblings[n];
3741 GEM_BUG_ON(!is_power_of_2(sibling->mask));
3742 if (sibling->mask & ve->base.mask) {
3743 DRM_DEBUG("duplicate %s entry in load balancer\n",
3750 * The virtual engine implementation is tightly coupled to
3751 * the execlists backend -- we push out request directly
3752 * into a tree inside each physical engine. We could support
3753 * layering if we handle cloning of the requests and
3754 * submitting a copy into each backend.
3756 if (sibling->execlists.tasklet.func !=
3757 execlists_submission_tasklet) {
3762 GEM_BUG_ON(RB_EMPTY_NODE(&ve->nodes[sibling->id].rb));
3763 RB_CLEAR_NODE(&ve->nodes[sibling->id].rb);
3765 ve->siblings[ve->num_siblings++] = sibling;
3766 ve->base.mask |= sibling->mask;
3769 * All physical engines must be compatible for their emission
3770 * functions (as we build the instructions during request
3771 * construction and do not alter them before submission
3772 * on the physical engine). We use the engine class as a guide
3773 * here, although that could be refined.
3775 if (ve->base.class != OTHER_CLASS) {
3776 if (ve->base.class != sibling->class) {
3777 DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
3778 sibling->class, ve->base.class);
3785 ve->base.class = sibling->class;
3786 ve->base.uabi_class = sibling->uabi_class;
3787 snprintf(ve->base.name, sizeof(ve->base.name),
3788 "v%dx%d", ve->base.class, count);
3789 ve->base.context_size = sibling->context_size;
3791 ve->base.emit_bb_start = sibling->emit_bb_start;
3792 ve->base.emit_flush = sibling->emit_flush;
3793 ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb;
3794 ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb;
3795 ve->base.emit_fini_breadcrumb_dw =
3796 sibling->emit_fini_breadcrumb_dw;
3798 ve->base.flags = sibling->flags;
3801 ve->base.flags |= I915_ENGINE_IS_VIRTUAL;
3803 err = __execlists_context_alloc(&ve->context, siblings[0]);
3807 __set_bit(CONTEXT_ALLOC_BIT, &ve->context.flags);
3809 return &ve->context;
3812 intel_context_put(&ve->context);
3813 return ERR_PTR(err);
3816 struct intel_context *
3817 intel_execlists_clone_virtual(struct i915_gem_context *ctx,
3818 struct intel_engine_cs *src)
3820 struct virtual_engine *se = to_virtual_engine(src);
3821 struct intel_context *dst;
3823 dst = intel_execlists_create_virtual(ctx,
3829 if (se->num_bonds) {
3830 struct virtual_engine *de = to_virtual_engine(dst->engine);
3832 de->bonds = kmemdup(se->bonds,
3833 sizeof(*se->bonds) * se->num_bonds,
3836 intel_context_put(dst);
3837 return ERR_PTR(-ENOMEM);
3840 de->num_bonds = se->num_bonds;
3846 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
3847 const struct intel_engine_cs *master,
3848 const struct intel_engine_cs *sibling)
3850 struct virtual_engine *ve = to_virtual_engine(engine);
3851 struct ve_bond *bond;
3854 /* Sanity check the sibling is part of the virtual engine */
3855 for (n = 0; n < ve->num_siblings; n++)
3856 if (sibling == ve->siblings[n])
3858 if (n == ve->num_siblings)
3861 bond = virtual_find_bond(ve, master);
3863 bond->sibling_mask |= sibling->mask;
3867 bond = krealloc(ve->bonds,
3868 sizeof(*bond) * (ve->num_bonds + 1),
3873 bond[ve->num_bonds].master = master;
3874 bond[ve->num_bonds].sibling_mask = sibling->mask;
3882 void intel_execlists_show_requests(struct intel_engine_cs *engine,
3883 struct drm_printer *m,
3884 void (*show_request)(struct drm_printer *m,
3885 struct i915_request *rq,
3886 const char *prefix),
3889 const struct intel_engine_execlists *execlists = &engine->execlists;
3890 struct i915_request *rq, *last;
3891 unsigned long flags;
3895 spin_lock_irqsave(&engine->active.lock, flags);
3899 list_for_each_entry(rq, &engine->active.requests, sched.link) {
3900 if (count++ < max - 1)
3901 show_request(m, rq, "\t\tE ");
3908 "\t\t...skipping %d executing requests...\n",
3911 show_request(m, last, "\t\tE ");
3916 if (execlists->queue_priority_hint != INT_MIN)
3917 drm_printf(m, "\t\tQueue priority hint: %d\n",
3918 execlists->queue_priority_hint);
3919 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
3920 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
3923 priolist_for_each_request(rq, p, i) {
3924 if (count++ < max - 1)
3925 show_request(m, rq, "\t\tQ ");
3933 "\t\t...skipping %d queued requests...\n",
3936 show_request(m, last, "\t\tQ ");
3941 for (rb = rb_first_cached(&execlists->virtual); rb; rb = rb_next(rb)) {
3942 struct virtual_engine *ve =
3943 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
3944 struct i915_request *rq = READ_ONCE(ve->request);
3947 if (count++ < max - 1)
3948 show_request(m, rq, "\t\tV ");
3956 "\t\t...skipping %d virtual requests...\n",
3959 show_request(m, last, "\t\tV ");
3962 spin_unlock_irqrestore(&engine->active.lock, flags);
3965 void intel_lr_context_reset(struct intel_engine_cs *engine,
3966 struct intel_context *ce,
3971 * We want a simple context + ring to execute the breadcrumb update.
3972 * We cannot rely on the context being intact across the GPU hang,
3973 * so clear it and rebuild just what we need for the breadcrumb.
3974 * All pending requests for this context will be zapped, and any
3975 * future request will be after userspace has had the opportunity
3976 * to recreate its own state.
3979 u32 *regs = ce->lrc_reg_state;
3981 if (engine->pinned_default_state) {
3982 memcpy(regs, /* skip restoring the vanilla PPHWSP */
3983 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
3984 engine->context_size - PAGE_SIZE);
3986 execlists_init_reg_state(regs, ce, engine, ce->ring);
3989 /* Rerun the request; its payload has been neutered (if guilty). */
3990 ce->ring->head = head;
3991 intel_ring_update_space(ce->ring);
3993 __execlists_update_reg_state(ce, engine);
3996 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3997 #include "selftest_lrc.c"