2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include "gem/i915_gem_context.h"
138 #include "i915_drv.h"
139 #include "i915_perf.h"
140 #include "i915_trace.h"
141 #include "i915_vgpu.h"
142 #include "intel_engine_pm.h"
143 #include "intel_gt.h"
144 #include "intel_gt_pm.h"
145 #include "intel_lrc_reg.h"
146 #include "intel_mocs.h"
147 #include "intel_reset.h"
148 #include "intel_workarounds.h"
150 #define RING_EXECLIST_QFULL (1 << 0x2)
151 #define RING_EXECLIST1_VALID (1 << 0x3)
152 #define RING_EXECLIST0_VALID (1 << 0x4)
153 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
154 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
155 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
157 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
158 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
159 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
160 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
161 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
162 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
164 #define GEN8_CTX_STATUS_COMPLETED_MASK \
165 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
167 #define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
169 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
170 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
171 #define WA_TAIL_DWORDS 2
172 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
174 struct virtual_engine {
175 struct intel_engine_cs base;
176 struct intel_context context;
179 * We allow only a single request through the virtual engine at a time
180 * (each request in the timeline waits for the completion fence of
181 * the previous before being submitted). By restricting ourselves to
182 * only submitting a single request, each request is placed on to a
183 * physical to maximise load spreading (by virtue of the late greedy
184 * scheduling -- each real engine takes the next available request
187 struct i915_request *request;
190 * We keep a rbtree of available virtual engines inside each physical
191 * engine, sorted by priority. Here we preallocate the nodes we need
192 * for the virtual engine, indexed by physical_engine->id.
197 } nodes[I915_NUM_ENGINES];
200 * Keep track of bonded pairs -- restrictions upon on our selection
201 * of physical engines any particular request may be submitted to.
202 * If we receive a submit-fence from a master engine, we will only
203 * use one of sibling_mask physical engines.
206 const struct intel_engine_cs *master;
207 intel_engine_mask_t sibling_mask;
209 unsigned int num_bonds;
211 /* And finally, which physical engines this virtual engine maps onto. */
212 unsigned int num_siblings;
213 struct intel_engine_cs *siblings[0];
216 static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine)
218 GEM_BUG_ON(!intel_engine_is_virtual(engine));
219 return container_of(engine, struct virtual_engine, base);
222 static int __execlists_context_alloc(struct intel_context *ce,
223 struct intel_engine_cs *engine);
225 static void execlists_init_reg_state(u32 *reg_state,
226 struct intel_context *ce,
227 struct intel_engine_cs *engine,
228 struct intel_ring *ring);
230 static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
232 return (i915_ggtt_offset(engine->status_page.vma) +
233 I915_GEM_HWS_PREEMPT_ADDR);
237 ring_set_paused(const struct intel_engine_cs *engine, int state)
240 * We inspect HWS_PREEMPT with a semaphore inside
241 * engine->emit_fini_breadcrumb. If the dword is true,
242 * the ring is paused as the semaphore will busywait
243 * until the dword is false.
245 engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
250 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
252 return rb_entry(rb, struct i915_priolist, node);
255 static inline int rq_prio(const struct i915_request *rq)
257 return rq->sched.attr.priority;
260 static int effective_prio(const struct i915_request *rq)
262 int prio = rq_prio(rq);
265 * If this request is special and must not be interrupted at any
266 * cost, so be it. Note we are only checking the most recent request
267 * in the context and so may be masking an earlier vip request. It
268 * is hoped that under the conditions where nopreempt is used, this
269 * will not matter (i.e. all requests to that context will be
270 * nopreempt for as long as desired).
272 if (i915_request_has_nopreempt(rq))
273 prio = I915_PRIORITY_UNPREEMPTABLE;
276 * On unwinding the active request, we give it a priority bump
277 * if it has completed waiting on any semaphore. If we know that
278 * the request has already started, we can prevent an unwanted
279 * preempt-to-idle cycle by taking that into account now.
281 if (__i915_request_has_started(rq))
282 prio |= I915_PRIORITY_NOSEMAPHORE;
284 /* Restrict mere WAIT boosts from triggering preemption */
285 BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
286 return prio | __NO_PREEMPTION;
289 static int queue_prio(const struct intel_engine_execlists *execlists)
291 struct i915_priolist *p;
294 rb = rb_first_cached(&execlists->queue);
299 * As the priolist[] are inverted, with the highest priority in [0],
300 * we have to flip the index value to become priority.
303 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
306 static inline bool need_preempt(const struct intel_engine_cs *engine,
307 const struct i915_request *rq,
312 if (!intel_engine_has_semaphores(engine))
316 * Check if the current priority hint merits a preemption attempt.
318 * We record the highest value priority we saw during rescheduling
319 * prior to this dequeue, therefore we know that if it is strictly
320 * less than the current tail of ESLP[0], we do not need to force
321 * a preempt-to-idle cycle.
323 * However, the priority hint is a mere hint that we may need to
324 * preempt. If that hint is stale or we may be trying to preempt
325 * ourselves, ignore the request.
327 last_prio = effective_prio(rq);
328 if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint,
333 * Check against the first request in ELSP[1], it will, thanks to the
334 * power of PI, be the highest priority of that context.
336 if (!list_is_last(&rq->sched.link, &engine->active.requests) &&
337 rq_prio(list_next_entry(rq, sched.link)) > last_prio)
341 struct virtual_engine *ve =
342 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
343 bool preempt = false;
345 if (engine == ve->siblings[0]) { /* only preempt one sibling */
346 struct i915_request *next;
349 next = READ_ONCE(ve->request);
351 preempt = rq_prio(next) > last_prio;
360 * If the inflight context did not trigger the preemption, then maybe
361 * it was the set of queued requests? Pick the highest priority in
362 * the queue (the first active priolist) and see if it deserves to be
363 * running instead of ELSP[0].
365 * The highest priority request in the queue can not be either
366 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same
367 * context, it's priority would not exceed ELSP[0] aka last_prio.
369 return queue_prio(&engine->execlists) > last_prio;
372 __maybe_unused static inline bool
373 assert_priority_queue(const struct i915_request *prev,
374 const struct i915_request *next)
377 * Without preemption, the prev may refer to the still active element
378 * which we refuse to let go.
380 * Even with preemption, there are times when we think it is better not
381 * to preempt and leave an ostensibly lower priority request in flight.
383 if (i915_request_is_active(prev))
386 return rq_prio(prev) >= rq_prio(next);
390 * The context descriptor encodes various attributes of a context,
391 * including its GTT address and some flags. Because it's fairly
392 * expensive to calculate, we'll just do it once and cache the result,
393 * which remains valid until the context is unpinned.
395 * This is what a descriptor looks like, from LSB to MSB::
397 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
398 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
399 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
400 * bits 53-54: mbz, reserved for use by hardware
401 * bits 55-63: group ID, currently unused and set to 0
403 * Starting from Gen11, the upper dword of the descriptor has a new format:
405 * bits 32-36: reserved
406 * bits 37-47: SW context ID
407 * bits 48:53: engine instance
408 * bit 54: mbz, reserved for use by hardware
409 * bits 55-60: SW counter
410 * bits 61-63: engine class
412 * engine info, SW context ID and SW counter need to form a unique number
413 * (Context ID) per lrc.
416 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
418 struct i915_gem_context *ctx = ce->gem_context;
421 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
422 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
424 desc = INTEL_LEGACY_32B_CONTEXT;
425 if (i915_vm_is_4lvl(ce->vm))
426 desc = INTEL_LEGACY_64B_CONTEXT;
427 desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
429 desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
430 if (IS_GEN(engine->i915, 8))
431 desc |= GEN8_CTX_L3LLC_COHERENT;
433 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
436 * The following 32bits are copied into the OA reports (dword 2).
437 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
440 if (INTEL_GEN(engine->i915) >= 11) {
441 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
442 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
445 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
448 /* TODO: decide what to do with SW counter (bits 55-60) */
450 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
453 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
454 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
460 static void unwind_wa_tail(struct i915_request *rq)
462 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
463 assert_ring_tail_valid(rq->ring, rq->tail);
466 static struct i915_request *
467 __unwind_incomplete_requests(struct intel_engine_cs *engine)
469 struct i915_request *rq, *rn, *active = NULL;
470 struct list_head *uninitialized_var(pl);
471 int prio = I915_PRIORITY_INVALID;
473 lockdep_assert_held(&engine->active.lock);
475 list_for_each_entry_safe_reverse(rq, rn,
476 &engine->active.requests,
478 struct intel_engine_cs *owner;
480 if (i915_request_completed(rq))
483 __i915_request_unsubmit(rq);
487 * Push the request back into the queue for later resubmission.
488 * If this request is not native to this physical engine (i.e.
489 * it came from a virtual source), push it back onto the virtual
490 * engine so that it can be moved across onto another physical
491 * engine as load dictates.
493 owner = rq->hw_context->engine;
494 if (likely(owner == engine)) {
495 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
496 if (rq_prio(rq) != prio) {
498 pl = i915_sched_lookup_priolist(engine, prio);
500 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
502 list_move(&rq->sched.link, pl);
506 * Decouple the virtual breadcrumb before moving it
507 * back to the virtual engine -- we don't want the
508 * request to complete in the background and try
509 * and cancel the breadcrumb on the virtual engine
510 * (instead of the old engine where it is linked)!
512 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
514 spin_lock(&rq->lock);
515 i915_request_cancel_breadcrumb(rq);
516 spin_unlock(&rq->lock);
519 owner->submit_request(rq);
527 struct i915_request *
528 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
530 struct intel_engine_cs *engine =
531 container_of(execlists, typeof(*engine), execlists);
533 return __unwind_incomplete_requests(engine);
537 execlists_context_status_change(struct i915_request *rq, unsigned long status)
540 * Only used when GVT-g is enabled now. When GVT-g is disabled,
541 * The compiler should eliminate this function as dead-code.
543 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
546 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
550 static inline struct i915_request *
551 execlists_schedule_in(struct i915_request *rq, int idx)
553 struct intel_context *ce = rq->hw_context;
556 trace_i915_request_in(rq, idx);
558 count = intel_context_inflight_count(ce);
560 intel_context_get(ce);
561 ce->inflight = rq->engine;
563 intel_gt_pm_get(ce->inflight->gt);
564 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
565 intel_engine_context_in(ce->inflight);
568 intel_context_inflight_inc(ce);
569 GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
571 return i915_request_get(rq);
574 static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
576 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
577 struct i915_request *next = READ_ONCE(ve->request);
579 if (next && next->execution_mask & ~rq->execution_mask)
580 tasklet_schedule(&ve->base.execlists.tasklet);
584 execlists_schedule_out(struct i915_request *rq)
586 struct intel_context *ce = rq->hw_context;
588 GEM_BUG_ON(!intel_context_inflight_count(ce));
590 trace_i915_request_out(rq);
592 intel_context_inflight_dec(ce);
593 if (!intel_context_inflight_count(ce)) {
594 intel_engine_context_out(ce->inflight);
595 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
596 intel_gt_pm_put(ce->inflight->gt);
599 * If this is part of a virtual engine, its next request may
600 * have been blocked waiting for access to the active context.
601 * We have to kick all the siblings again in case we need to
602 * switch (e.g. the next request is not runnable on this
603 * engine). Hopefully, we will already have submitted the next
604 * request before the tasklet runs and do not need to rebuild
605 * each virtual tree and kick everyone again.
608 if (rq->engine != ce->engine)
609 kick_siblings(rq, ce);
611 intel_context_put(ce);
614 i915_request_put(rq);
617 static u64 execlists_update_context(const struct i915_request *rq)
619 struct intel_context *ce = rq->hw_context;
622 ce->lrc_reg_state[CTX_RING_TAIL + 1] =
623 intel_ring_set_tail(rq->ring, rq->tail);
626 * Make sure the context image is complete before we submit it to HW.
628 * Ostensibly, writes (including the WCB) should be flushed prior to
629 * an uncached write such as our mmio register access, the empirical
630 * evidence (esp. on Braswell) suggests that the WC write into memory
631 * may not be visible to the HW prior to the completion of the UC
632 * register write and that we may begin execution from the context
633 * before its image is complete leading to invalid PD chasing.
635 * Furthermore, Braswell, at least, wants a full mb to be sure that
636 * the writes are coherent in memory (visible to the GPU) prior to
637 * execution, and not just visible to other CPUs (as is the result of
643 ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;
648 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
650 if (execlists->ctrl_reg) {
651 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
652 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
654 writel(upper_32_bits(desc), execlists->submit_reg);
655 writel(lower_32_bits(desc), execlists->submit_reg);
659 static __maybe_unused void
660 trace_ports(const struct intel_engine_execlists *execlists,
662 struct i915_request * const *ports)
664 const struct intel_engine_cs *engine =
665 container_of(execlists, typeof(*engine), execlists);
667 GEM_TRACE("%s: %s { %llx:%lld%s, %llx:%lld }\n",
669 ports[0]->fence.context,
670 ports[0]->fence.seqno,
671 i915_request_completed(ports[0]) ? "!" :
672 i915_request_started(ports[0]) ? "*" :
674 ports[1] ? ports[1]->fence.context : 0,
675 ports[1] ? ports[1]->fence.seqno : 0);
678 static __maybe_unused bool
679 assert_pending_valid(const struct intel_engine_execlists *execlists,
682 struct i915_request * const *port, *rq;
683 struct intel_context *ce = NULL;
685 trace_ports(execlists, msg, execlists->pending);
687 if (execlists->pending[execlists_num_ports(execlists)])
690 for (port = execlists->pending; (rq = *port); port++) {
691 if (ce == rq->hw_context)
695 if (i915_request_completed(rq))
698 if (i915_active_is_idle(&ce->active))
701 if (!i915_vma_is_pinned(ce->state))
708 static void execlists_submit_ports(struct intel_engine_cs *engine)
710 struct intel_engine_execlists *execlists = &engine->execlists;
713 GEM_BUG_ON(!assert_pending_valid(execlists, "submit"));
716 * We can skip acquiring intel_runtime_pm_get() here as it was taken
717 * on our behalf by the request (see i915_gem_mark_busy()) and it will
718 * not be relinquished until the device is idle (see
719 * i915_gem_idle_work_handler()). As a precaution, we make sure
720 * that all ELSP are drained i.e. we have processed the CSB,
721 * before allowing ourselves to idle and calling intel_runtime_pm_put().
723 GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
726 * ELSQ note: the submit queue is not cleared after being submitted
727 * to the HW so we need to make sure we always clean it up. This is
728 * currently ensured by the fact that we always write the same number
729 * of elsq entries, keep this in mind before changing the loop below.
731 for (n = execlists_num_ports(execlists); n--; ) {
732 struct i915_request *rq = execlists->pending[n];
734 write_desc(execlists,
735 rq ? execlists_update_context(rq) : 0,
739 /* we need to manually load the submit queue */
740 if (execlists->ctrl_reg)
741 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
744 static bool ctx_single_port_submission(const struct intel_context *ce)
746 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
747 i915_gem_context_force_single_submission(ce->gem_context));
750 static bool can_merge_ctx(const struct intel_context *prev,
751 const struct intel_context *next)
756 if (ctx_single_port_submission(prev))
762 static bool can_merge_rq(const struct i915_request *prev,
763 const struct i915_request *next)
765 GEM_BUG_ON(prev == next);
766 GEM_BUG_ON(!assert_priority_queue(prev, next));
768 if (!can_merge_ctx(prev->hw_context, next->hw_context))
774 static void virtual_update_register_offsets(u32 *regs,
775 struct intel_engine_cs *engine)
777 u32 base = engine->mmio_base;
779 /* Must match execlists_init_reg_state()! */
781 regs[CTX_CONTEXT_CONTROL] =
782 i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base));
783 regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base));
784 regs[CTX_RING_TAIL] = i915_mmio_reg_offset(RING_TAIL(base));
785 regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base));
786 regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base));
788 regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base));
789 regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base));
790 regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base));
791 regs[CTX_SECOND_BB_HEAD_U] =
792 i915_mmio_reg_offset(RING_SBBADDR_UDW(base));
793 regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base));
794 regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base));
796 regs[CTX_CTX_TIMESTAMP] =
797 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base));
798 regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3));
799 regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3));
800 regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2));
801 regs[CTX_PDP2_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 2));
802 regs[CTX_PDP1_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 1));
803 regs[CTX_PDP1_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 1));
804 regs[CTX_PDP0_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
805 regs[CTX_PDP0_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
807 if (engine->class == RENDER_CLASS) {
808 regs[CTX_RCS_INDIRECT_CTX] =
809 i915_mmio_reg_offset(RING_INDIRECT_CTX(base));
810 regs[CTX_RCS_INDIRECT_CTX_OFFSET] =
811 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(base));
812 regs[CTX_BB_PER_CTX_PTR] =
813 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(base));
815 regs[CTX_R_PWR_CLK_STATE] =
816 i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
820 static bool virtual_matches(const struct virtual_engine *ve,
821 const struct i915_request *rq,
822 const struct intel_engine_cs *engine)
824 const struct intel_engine_cs *inflight;
826 if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */
830 * We track when the HW has completed saving the context image
831 * (i.e. when we have seen the final CS event switching out of
832 * the context) and must not overwrite the context image before
833 * then. This restricts us to only using the active engine
834 * while the previous virtualized request is inflight (so
835 * we reuse the register offsets). This is a very small
836 * hystersis on the greedy seelction algorithm.
838 inflight = intel_context_inflight(&ve->context);
839 if (inflight && inflight != engine)
845 static void virtual_xfer_breadcrumbs(struct virtual_engine *ve,
846 struct intel_engine_cs *engine)
848 struct intel_engine_cs *old = ve->siblings[0];
850 /* All unattached (rq->engine == old) must already be completed */
852 spin_lock(&old->breadcrumbs.irq_lock);
853 if (!list_empty(&ve->context.signal_link)) {
854 list_move_tail(&ve->context.signal_link,
855 &engine->breadcrumbs.signalers);
856 intel_engine_queue_breadcrumbs(engine);
858 spin_unlock(&old->breadcrumbs.irq_lock);
861 static struct i915_request *
862 last_active(const struct intel_engine_execlists *execlists)
864 struct i915_request * const *last = execlists->active;
866 while (*last && i915_request_completed(*last))
872 static void defer_request(struct i915_request *rq, struct list_head * const pl)
877 * We want to move the interrupted request to the back of
878 * the round-robin list (i.e. its priority level), but
879 * in doing so, we must then move all requests that were in
880 * flight and were waiting for the interrupted request to
881 * be run after it again.
884 struct i915_dependency *p;
886 GEM_BUG_ON(i915_request_is_active(rq));
887 list_move_tail(&rq->sched.link, pl);
889 list_for_each_entry(p, &rq->sched.waiters_list, wait_link) {
890 struct i915_request *w =
891 container_of(p->waiter, typeof(*w), sched);
893 /* Leave semaphores spinning on the other engines */
894 if (w->engine != rq->engine)
897 /* No waiter should start before its signaler */
898 GEM_BUG_ON(i915_request_started(w) &&
899 !i915_request_completed(rq));
901 GEM_BUG_ON(i915_request_is_active(w));
902 if (list_empty(&w->sched.link))
903 continue; /* Not yet submitted; unready */
905 if (rq_prio(w) < rq_prio(rq))
908 GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
909 list_move_tail(&w->sched.link, &list);
912 rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
916 static void defer_active(struct intel_engine_cs *engine)
918 struct i915_request *rq;
920 rq = __unwind_incomplete_requests(engine);
924 defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
928 need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
932 if (!intel_engine_has_semaphores(engine))
935 if (list_is_last(&rq->sched.link, &engine->active.requests))
938 hint = max(rq_prio(list_next_entry(rq, sched.link)),
939 engine->execlists.queue_priority_hint);
941 return hint >= effective_prio(rq);
945 enable_timeslice(struct intel_engine_cs *engine)
947 struct i915_request *last = last_active(&engine->execlists);
949 return last && need_timeslice(engine, last);
952 static void record_preemption(struct intel_engine_execlists *execlists)
954 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
957 static void execlists_dequeue(struct intel_engine_cs *engine)
959 struct intel_engine_execlists * const execlists = &engine->execlists;
960 struct i915_request **port = execlists->pending;
961 struct i915_request ** const last_port = port + execlists->port_mask;
962 struct i915_request *last;
967 * Hardware submission is through 2 ports. Conceptually each port
968 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
969 * static for a context, and unique to each, so we only execute
970 * requests belonging to a single context from each ring. RING_HEAD
971 * is maintained by the CS in the context image, it marks the place
972 * where it got up to last time, and through RING_TAIL we tell the CS
973 * where we want to execute up to this time.
975 * In this list the requests are in order of execution. Consecutive
976 * requests from the same context are adjacent in the ringbuffer. We
977 * can combine these requests into a single RING_TAIL update:
979 * RING_HEAD...req1...req2
981 * since to execute req2 the CS must first execute req1.
983 * Our goal then is to point each port to the end of a consecutive
984 * sequence of requests as being the most optimal (fewest wake ups
985 * and context switches) submission.
988 for (rb = rb_first_cached(&execlists->virtual); rb; ) {
989 struct virtual_engine *ve =
990 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
991 struct i915_request *rq = READ_ONCE(ve->request);
993 if (!rq) { /* lazily cleanup after another engine handled rq */
994 rb_erase_cached(rb, &execlists->virtual);
996 rb = rb_first_cached(&execlists->virtual);
1000 if (!virtual_matches(ve, rq, engine)) {
1009 * If the queue is higher priority than the last
1010 * request in the currently active context, submit afresh.
1011 * We will resubmit again afterwards in case we need to split
1012 * the active context to interject the preemption request,
1013 * i.e. we will retrigger preemption following the ack in case
1016 last = last_active(execlists);
1018 if (need_preempt(engine, last, rb)) {
1019 GEM_TRACE("%s: preempting last=%llx:%lld, prio=%d, hint=%d\n",
1021 last->fence.context,
1023 last->sched.attr.priority,
1024 execlists->queue_priority_hint);
1025 record_preemption(execlists);
1028 * Don't let the RING_HEAD advance past the breadcrumb
1029 * as we unwind (and until we resubmit) so that we do
1030 * not accidentally tell it to go backwards.
1032 ring_set_paused(engine, 1);
1035 * Note that we have not stopped the GPU at this point,
1036 * so we are unwinding the incomplete requests as they
1037 * remain inflight and so by the time we do complete
1038 * the preemption, some of the unwound requests may
1041 __unwind_incomplete_requests(engine);
1044 * If we need to return to the preempted context, we
1045 * need to skip the lite-restore and force it to
1046 * reload the RING_TAIL. Otherwise, the HW has a
1047 * tendency to ignore us rewinding the TAIL to the
1048 * end of an earlier request.
1050 last->hw_context->lrc_desc |= CTX_DESC_FORCE_RESTORE;
1052 } else if (need_timeslice(engine, last) &&
1053 !timer_pending(&engine->execlists.timer)) {
1054 GEM_TRACE("%s: expired last=%llx:%lld, prio=%d, hint=%d\n",
1056 last->fence.context,
1058 last->sched.attr.priority,
1059 execlists->queue_priority_hint);
1061 ring_set_paused(engine, 1);
1062 defer_active(engine);
1065 * Unlike for preemption, if we rewind and continue
1066 * executing the same context as previously active,
1067 * the order of execution will remain the same and
1068 * the tail will only advance. We do not need to
1069 * force a full context restore, as a lite-restore
1070 * is sufficient to resample the monotonic TAIL.
1072 * If we switch to any other context, similarly we
1073 * will not rewind TAIL of current context, and
1074 * normal save/restore will preserve state and allow
1075 * us to later continue executing the same request.
1080 * Otherwise if we already have a request pending
1081 * for execution after the current one, we can
1082 * just wait until the next CS event before
1083 * queuing more. In either case we will force a
1084 * lite-restore preemption event, but if we wait
1085 * we hopefully coalesce several updates into a single
1088 if (!list_is_last(&last->sched.link,
1089 &engine->active.requests))
1093 * WaIdleLiteRestore:bdw,skl
1094 * Apply the wa NOOPs to prevent
1095 * ring:HEAD == rq:TAIL as we resubmit the
1096 * request. See gen8_emit_fini_breadcrumb() for
1097 * where we prepare the padding after the
1098 * end of the request.
1100 last->tail = last->wa_tail;
1104 while (rb) { /* XXX virtual is always taking precedence */
1105 struct virtual_engine *ve =
1106 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
1107 struct i915_request *rq;
1109 spin_lock(&ve->base.active.lock);
1112 if (unlikely(!rq)) { /* lost the race to a sibling */
1113 spin_unlock(&ve->base.active.lock);
1114 rb_erase_cached(rb, &execlists->virtual);
1116 rb = rb_first_cached(&execlists->virtual);
1120 GEM_BUG_ON(rq != ve->request);
1121 GEM_BUG_ON(rq->engine != &ve->base);
1122 GEM_BUG_ON(rq->hw_context != &ve->context);
1124 if (rq_prio(rq) >= queue_prio(execlists)) {
1125 if (!virtual_matches(ve, rq, engine)) {
1126 spin_unlock(&ve->base.active.lock);
1131 if (i915_request_completed(rq)) {
1133 ve->base.execlists.queue_priority_hint = INT_MIN;
1134 rb_erase_cached(rb, &execlists->virtual);
1137 rq->engine = engine;
1138 __i915_request_submit(rq);
1140 spin_unlock(&ve->base.active.lock);
1142 rb = rb_first_cached(&execlists->virtual);
1146 if (last && !can_merge_rq(last, rq)) {
1147 spin_unlock(&ve->base.active.lock);
1148 return; /* leave this for another */
1151 GEM_TRACE("%s: virtual rq=%llx:%lld%s, new engine? %s\n",
1155 i915_request_completed(rq) ? "!" :
1156 i915_request_started(rq) ? "*" :
1158 yesno(engine != ve->siblings[0]));
1161 ve->base.execlists.queue_priority_hint = INT_MIN;
1162 rb_erase_cached(rb, &execlists->virtual);
1165 GEM_BUG_ON(!(rq->execution_mask & engine->mask));
1166 rq->engine = engine;
1168 if (engine != ve->siblings[0]) {
1169 u32 *regs = ve->context.lrc_reg_state;
1172 GEM_BUG_ON(READ_ONCE(ve->context.inflight));
1173 virtual_update_register_offsets(regs, engine);
1175 if (!list_empty(&ve->context.signals))
1176 virtual_xfer_breadcrumbs(ve, engine);
1179 * Move the bound engine to the top of the list
1180 * for future execution. We then kick this
1181 * tasklet first before checking others, so that
1182 * we preferentially reuse this set of bound
1185 for (n = 1; n < ve->num_siblings; n++) {
1186 if (ve->siblings[n] == engine) {
1187 swap(ve->siblings[n],
1193 GEM_BUG_ON(ve->siblings[0] != engine);
1196 __i915_request_submit(rq);
1197 if (!i915_request_completed(rq)) {
1203 spin_unlock(&ve->base.active.lock);
1207 while ((rb = rb_first_cached(&execlists->queue))) {
1208 struct i915_priolist *p = to_priolist(rb);
1209 struct i915_request *rq, *rn;
1212 priolist_for_each_request_consume(rq, rn, p, i) {
1213 if (i915_request_completed(rq))
1217 * Can we combine this request with the current port?
1218 * It has to be the same context/ringbuffer and not
1219 * have any exceptions (e.g. GVT saying never to
1220 * combine contexts).
1222 * If we can combine the requests, we can execute both
1223 * by updating the RING_TAIL to point to the end of the
1224 * second request, and so we never need to tell the
1225 * hardware about the first.
1227 if (last && !can_merge_rq(last, rq)) {
1229 * If we are on the second port and cannot
1230 * combine this request with the last, then we
1233 if (port == last_port)
1237 * We must not populate both ELSP[] with the
1238 * same LRCA, i.e. we must submit 2 different
1239 * contexts if we submit 2 ELSP.
1241 if (last->hw_context == rq->hw_context)
1245 * If GVT overrides us we only ever submit
1246 * port[0], leaving port[1] empty. Note that we
1247 * also have to be careful that we don't queue
1248 * the same context (even though a different
1249 * request) to the second port.
1251 if (ctx_single_port_submission(last->hw_context) ||
1252 ctx_single_port_submission(rq->hw_context))
1255 *port = execlists_schedule_in(last, port - execlists->pending);
1262 __i915_request_submit(rq);
1265 rb_erase_cached(&p->node, &execlists->queue);
1266 i915_priolist_free(p);
1271 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
1273 * We choose the priority hint such that if we add a request of greater
1274 * priority than this, we kick the submission tasklet to decide on
1275 * the right order of submitting the requests to hardware. We must
1276 * also be prepared to reorder requests as they are in-flight on the
1277 * HW. We derive the priority hint then as the first "hole" in
1278 * the HW submission ports and if there are no available slots,
1279 * the priority of the lowest executing request, i.e. last.
1281 * When we do receive a higher priority request ready to run from the
1282 * user, see queue_request(), the priority hint is bumped to that
1283 * request triggering preemption on the next dequeue (or subsequent
1284 * interrupt for secondary ports).
1286 execlists->queue_priority_hint = queue_prio(execlists);
1287 GEM_TRACE("%s: queue_priority_hint:%d, submit:%s\n",
1288 engine->name, execlists->queue_priority_hint,
1292 *port = execlists_schedule_in(last, port - execlists->pending);
1293 memset(port + 1, 0, (last_port - port) * sizeof(*port));
1294 execlists_submit_ports(engine);
1296 ring_set_paused(engine, 0);
1301 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
1303 struct i915_request * const *port, *rq;
1305 for (port = execlists->pending; (rq = *port); port++)
1306 execlists_schedule_out(rq);
1307 memset(execlists->pending, 0, sizeof(execlists->pending));
1309 for (port = execlists->active; (rq = *port); port++)
1310 execlists_schedule_out(rq);
1312 memset(execlists->inflight, 0, sizeof(execlists->inflight));
1316 invalidate_csb_entries(const u32 *first, const u32 *last)
1318 clflush((void *)first);
1319 clflush((void *)last);
1323 reset_in_progress(const struct intel_engine_execlists *execlists)
1325 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
1335 static inline enum csb_step
1336 csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
1338 unsigned int status = *csb;
1340 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
1343 if (status & GEN8_CTX_STATUS_PREEMPTED)
1346 if (*execlists->active)
1347 return CSB_COMPLETE;
1352 static void process_csb(struct intel_engine_cs *engine)
1354 struct intel_engine_execlists * const execlists = &engine->execlists;
1355 const u32 * const buf = execlists->csb_status;
1356 const u8 num_entries = execlists->csb_size;
1359 lockdep_assert_held(&engine->active.lock);
1360 GEM_BUG_ON(USES_GUC_SUBMISSION(engine->i915));
1363 * Note that csb_write, csb_status may be either in HWSP or mmio.
1364 * When reading from the csb_write mmio register, we have to be
1365 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
1366 * the low 4bits. As it happens we know the next 4bits are always
1367 * zero and so we can simply masked off the low u8 of the register
1368 * and treat it identically to reading from the HWSP (without having
1369 * to use explicit shifting and masking, and probably bifurcating
1370 * the code to handle the legacy mmio read).
1372 head = execlists->csb_head;
1373 tail = READ_ONCE(*execlists->csb_write);
1374 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
1375 if (unlikely(head == tail))
1379 * Hopefully paired with a wmb() in HW!
1381 * We must complete the read of the write pointer before any reads
1382 * from the CSB, so that we do not see stale values. Without an rmb
1383 * (lfence) the HW may speculatively perform the CSB[] reads *before*
1384 * we perform the READ_ONCE(*csb_write).
1389 if (++head == num_entries)
1393 * We are flying near dragons again.
1395 * We hold a reference to the request in execlist_port[]
1396 * but no more than that. We are operating in softirq
1397 * context and so cannot hold any mutex or sleep. That
1398 * prevents us stopping the requests we are processing
1399 * in port[] from being retired simultaneously (the
1400 * breadcrumb will be complete before we see the
1401 * context-switch). As we only hold the reference to the
1402 * request, any pointer chasing underneath the request
1403 * is subject to a potential use-after-free. Thus we
1404 * store all of the bookkeeping within port[] as
1405 * required, and avoid using unguarded pointers beneath
1406 * request itself. The same applies to the atomic
1410 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x\n",
1412 buf[2 * head + 0], buf[2 * head + 1]);
1414 switch (csb_parse(execlists, buf + 2 * head)) {
1415 case CSB_PREEMPT: /* cancel old inflight, prepare for switch */
1416 trace_ports(execlists, "preempted", execlists->active);
1418 while (*execlists->active)
1419 execlists_schedule_out(*execlists->active++);
1422 case CSB_PROMOTE: /* switch pending to inflight */
1423 GEM_BUG_ON(*execlists->active);
1424 GEM_BUG_ON(!assert_pending_valid(execlists, "promote"));
1426 memcpy(execlists->inflight,
1428 execlists_num_ports(execlists) *
1429 sizeof(*execlists->pending));
1430 execlists->pending[0] = NULL;
1432 trace_ports(execlists, "promoted", execlists->active);
1434 if (enable_timeslice(engine))
1435 mod_timer(&execlists->timer, jiffies + 1);
1437 if (!inject_preempt_hang(execlists))
1438 ring_set_paused(engine, 0);
1441 case CSB_COMPLETE: /* port0 completed, advanced to port1 */
1442 trace_ports(execlists, "completed", execlists->active);
1445 * We rely on the hardware being strongly
1446 * ordered, that the breadcrumb write is
1447 * coherent (visible from the CPU) before the
1448 * user interrupt and CSB is processed.
1450 GEM_BUG_ON(!i915_request_completed(*execlists->active) &&
1451 !reset_in_progress(execlists));
1452 execlists_schedule_out(*execlists->active++);
1454 GEM_BUG_ON(execlists->active - execlists->inflight >
1455 execlists_num_ports(execlists));
1461 } while (head != tail);
1463 execlists->csb_head = head;
1466 * Gen11 has proven to fail wrt global observation point between
1467 * entry and tail update, failing on the ordering and thus
1468 * we see an old entry in the context status buffer.
1470 * Forcibly evict out entries for the next gpu csb update,
1471 * to increase the odds that we get a fresh entries with non
1472 * working hardware. The cost for doing so comes out mostly with
1473 * the wash as hardware, working or not, will need to do the
1474 * invalidation before.
1476 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
1479 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
1481 lockdep_assert_held(&engine->active.lock);
1483 process_csb(engine);
1484 if (!engine->execlists.pending[0])
1485 execlists_dequeue(engine);
1489 * Check the unread Context Status Buffers and manage the submission of new
1490 * contexts to the ELSP accordingly.
1492 static void execlists_submission_tasklet(unsigned long data)
1494 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1495 unsigned long flags;
1497 spin_lock_irqsave(&engine->active.lock, flags);
1498 __execlists_submission_tasklet(engine);
1499 spin_unlock_irqrestore(&engine->active.lock, flags);
1502 static void execlists_submission_timer(struct timer_list *timer)
1504 struct intel_engine_cs *engine =
1505 from_timer(engine, timer, execlists.timer);
1507 /* Kick the tasklet for some interrupt coalescing and reset handling */
1508 tasklet_hi_schedule(&engine->execlists.tasklet);
1511 static void queue_request(struct intel_engine_cs *engine,
1512 struct i915_sched_node *node,
1515 GEM_BUG_ON(!list_empty(&node->link));
1516 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio));
1519 static void __submit_queue_imm(struct intel_engine_cs *engine)
1521 struct intel_engine_execlists * const execlists = &engine->execlists;
1523 if (reset_in_progress(execlists))
1524 return; /* defer until we restart the engine following reset */
1526 if (execlists->tasklet.func == execlists_submission_tasklet)
1527 __execlists_submission_tasklet(engine);
1529 tasklet_hi_schedule(&execlists->tasklet);
1532 static void submit_queue(struct intel_engine_cs *engine,
1533 const struct i915_request *rq)
1535 struct intel_engine_execlists *execlists = &engine->execlists;
1537 if (rq_prio(rq) <= execlists->queue_priority_hint)
1540 execlists->queue_priority_hint = rq_prio(rq);
1541 __submit_queue_imm(engine);
1544 static void execlists_submit_request(struct i915_request *request)
1546 struct intel_engine_cs *engine = request->engine;
1547 unsigned long flags;
1549 /* Will be called from irq-context when using foreign fences. */
1550 spin_lock_irqsave(&engine->active.lock, flags);
1552 queue_request(engine, &request->sched, rq_prio(request));
1554 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1555 GEM_BUG_ON(list_empty(&request->sched.link));
1557 submit_queue(engine, request);
1559 spin_unlock_irqrestore(&engine->active.lock, flags);
1562 static void __execlists_context_fini(struct intel_context *ce)
1564 intel_ring_put(ce->ring);
1565 i915_vma_put(ce->state);
1568 static void execlists_context_destroy(struct kref *kref)
1570 struct intel_context *ce = container_of(kref, typeof(*ce), ref);
1572 GEM_BUG_ON(!i915_active_is_idle(&ce->active));
1573 GEM_BUG_ON(intel_context_is_pinned(ce));
1576 __execlists_context_fini(ce);
1578 intel_context_fini(ce);
1579 intel_context_free(ce);
1582 static void execlists_context_unpin(struct intel_context *ce)
1584 i915_gem_context_unpin_hw_id(ce->gem_context);
1585 i915_gem_object_unpin_map(ce->state->obj);
1589 __execlists_update_reg_state(struct intel_context *ce,
1590 struct intel_engine_cs *engine)
1592 struct intel_ring *ring = ce->ring;
1593 u32 *regs = ce->lrc_reg_state;
1595 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
1596 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
1598 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma);
1599 regs[CTX_RING_HEAD + 1] = ring->head;
1600 regs[CTX_RING_TAIL + 1] = ring->tail;
1603 if (engine->class == RENDER_CLASS) {
1604 regs[CTX_R_PWR_CLK_STATE + 1] =
1605 intel_sseu_make_rpcs(engine->i915, &ce->sseu);
1607 i915_oa_init_reg_state(engine, ce, regs);
1612 __execlists_context_pin(struct intel_context *ce,
1613 struct intel_engine_cs *engine)
1618 GEM_BUG_ON(!ce->state);
1620 ret = intel_context_active_acquire(ce);
1623 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
1625 vaddr = i915_gem_object_pin_map(ce->state->obj,
1626 i915_coherent_map_type(engine->i915) |
1628 if (IS_ERR(vaddr)) {
1629 ret = PTR_ERR(vaddr);
1633 ret = i915_gem_context_pin_hw_id(ce->gem_context);
1637 ce->lrc_desc = lrc_descriptor(ce, engine);
1638 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1639 __execlists_update_reg_state(ce, engine);
1644 i915_gem_object_unpin_map(ce->state->obj);
1646 intel_context_active_release(ce);
1651 static int execlists_context_pin(struct intel_context *ce)
1653 return __execlists_context_pin(ce, ce->engine);
1656 static int execlists_context_alloc(struct intel_context *ce)
1658 return __execlists_context_alloc(ce, ce->engine);
1661 static void execlists_context_reset(struct intel_context *ce)
1664 * Because we emit WA_TAIL_DWORDS there may be a disparity
1665 * between our bookkeeping in ce->ring->head and ce->ring->tail and
1666 * that stored in context. As we only write new commands from
1667 * ce->ring->tail onwards, everything before that is junk. If the GPU
1668 * starts reading from its RING_HEAD from the context, it may try to
1669 * execute that junk and die.
1671 * The contexts that are stilled pinned on resume belong to the
1672 * kernel, and are local to each engine. All other contexts will
1673 * have their head/tail sanitized upon pinning before use, so they
1674 * will never see garbage,
1676 * So to avoid that we reset the context images upon resume. For
1677 * simplicity, we just zero everything out.
1679 intel_ring_reset(ce->ring, 0);
1680 __execlists_update_reg_state(ce, ce->engine);
1683 static const struct intel_context_ops execlists_context_ops = {
1684 .alloc = execlists_context_alloc,
1686 .pin = execlists_context_pin,
1687 .unpin = execlists_context_unpin,
1689 .enter = intel_context_enter_engine,
1690 .exit = intel_context_exit_engine,
1692 .reset = execlists_context_reset,
1693 .destroy = execlists_context_destroy,
1696 static int gen8_emit_init_breadcrumb(struct i915_request *rq)
1700 GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb);
1702 cs = intel_ring_begin(rq, 6);
1707 * Check if we have been preempted before we even get started.
1709 * After this point i915_request_started() reports true, even if
1710 * we get preempted and so are no longer running.
1712 *cs++ = MI_ARB_CHECK;
1715 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1716 *cs++ = rq->timeline->hwsp_offset;
1718 *cs++ = rq->fence.seqno - 1;
1720 intel_ring_advance(rq, cs);
1722 /* Record the updated position of the request's payload */
1723 rq->infix = intel_ring_offset(rq, cs);
1728 static int emit_pdps(struct i915_request *rq)
1730 const struct intel_engine_cs * const engine = rq->engine;
1731 struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(rq->hw_context->vm);
1735 GEM_BUG_ON(intel_vgpu_active(rq->i915));
1738 * Beware ye of the dragons, this sequence is magic!
1740 * Small changes to this sequence can cause anything from
1741 * GPU hangs to forcewake errors and machine lockups!
1744 /* Flush any residual operations from the context load */
1745 err = engine->emit_flush(rq, EMIT_FLUSH);
1749 /* Magic required to prevent forcewake errors! */
1750 err = engine->emit_flush(rq, EMIT_INVALIDATE);
1754 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
1758 /* Ensure the LRI have landed before we invalidate & continue */
1759 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
1760 for (i = GEN8_3LVL_PDPES; i--; ) {
1761 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1762 u32 base = engine->mmio_base;
1764 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
1765 *cs++ = upper_32_bits(pd_daddr);
1766 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
1767 *cs++ = lower_32_bits(pd_daddr);
1771 intel_ring_advance(rq, cs);
1773 /* Be doubly sure the LRI have landed before proceeding */
1774 err = engine->emit_flush(rq, EMIT_FLUSH);
1778 /* Re-invalidate the TLB for luck */
1779 return engine->emit_flush(rq, EMIT_INVALIDATE);
1782 static int execlists_request_alloc(struct i915_request *request)
1786 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context));
1789 * Flush enough space to reduce the likelihood of waiting after
1790 * we start building the request - in which case we will just
1791 * have to repeat work.
1793 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1796 * Note that after this point, we have committed to using
1797 * this request as it is being used to both track the
1798 * state of engine initialisation and liveness of the
1799 * golden renderstate above. Think twice before you try
1800 * to cancel/unwind this request now.
1803 /* Unconditionally invalidate GPU caches and TLBs. */
1804 if (i915_vm_is_4lvl(request->hw_context->vm))
1805 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
1807 ret = emit_pdps(request);
1811 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1816 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1817 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1818 * but there is a slight complication as this is applied in WA batch where the
1819 * values are only initialized once so we cannot take register value at the
1820 * beginning and reuse it further; hence we save its value to memory, upload a
1821 * constant value with bit21 set and then we restore it back with the saved value.
1822 * To simplify the WA, a constant value is formed by using the default value
1823 * of this register. This shouldn't be a problem because we are only modifying
1824 * it for a short period and this batch in non-premptible. We can ofcourse
1825 * use additional instructions that read the actual value of the register
1826 * at that time and set our bit of interest but it makes the WA complicated.
1828 * This WA is also required for Gen9 so extracting as a function avoids
1832 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1834 /* NB no one else is allowed to scribble over scratch + 256! */
1835 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1836 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1837 *batch++ = intel_gt_scratch_offset(engine->gt,
1838 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
1841 *batch++ = MI_LOAD_REGISTER_IMM(1);
1842 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1843 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1845 batch = gen8_emit_pipe_control(batch,
1846 PIPE_CONTROL_CS_STALL |
1847 PIPE_CONTROL_DC_FLUSH_ENABLE,
1850 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1851 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1852 *batch++ = intel_gt_scratch_offset(engine->gt,
1853 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
1859 static u32 slm_offset(struct intel_engine_cs *engine)
1861 return intel_gt_scratch_offset(engine->gt,
1862 INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA);
1866 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1867 * initialized at the beginning and shared across all contexts but this field
1868 * helps us to have multiple batches at different offsets and select them based
1869 * on a criteria. At the moment this batch always start at the beginning of the page
1870 * and at this point we don't have multiple wa_ctx batch buffers.
1872 * The number of WA applied are not known at the beginning; we use this field
1873 * to return the no of DWORDS written.
1875 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1876 * so it adds NOOPs as padding to make it cacheline aligned.
1877 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1878 * makes a complete batch buffer.
1880 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1882 /* WaDisableCtxRestoreArbitration:bdw,chv */
1883 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1885 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1886 if (IS_BROADWELL(engine->i915))
1887 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1889 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1890 /* Actual scratch location is at 128 bytes offset */
1891 batch = gen8_emit_pipe_control(batch,
1892 PIPE_CONTROL_FLUSH_L3 |
1893 PIPE_CONTROL_GLOBAL_GTT_IVB |
1894 PIPE_CONTROL_CS_STALL |
1895 PIPE_CONTROL_QW_WRITE,
1896 slm_offset(engine));
1898 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1900 /* Pad to end of cacheline */
1901 while ((unsigned long)batch % CACHELINE_BYTES)
1905 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1906 * execution depends on the length specified in terms of cache lines
1907 * in the register CTX_RCS_INDIRECT_CTX
1918 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1920 GEM_BUG_ON(!count || count > 63);
1922 *batch++ = MI_LOAD_REGISTER_IMM(count);
1924 *batch++ = i915_mmio_reg_offset(lri->reg);
1925 *batch++ = lri->value;
1926 } while (lri++, --count);
1932 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1934 static const struct lri lri[] = {
1935 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1937 COMMON_SLICE_CHICKEN2,
1938 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1945 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1946 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1952 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1953 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1957 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1959 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1960 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1962 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1964 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1965 if (HAS_POOLED_EU(engine->i915)) {
1967 * EU pool configuration is setup along with golden context
1968 * during context initialization. This value depends on
1969 * device type (2x6 or 3x6) and needs to be updated based
1970 * on which subslice is disabled especially for 2x6
1971 * devices, however it is safe to load default
1972 * configuration of 3x6 device instead of masking off
1973 * corresponding bits because HW ignores bits of a disabled
1974 * subslice and drops down to appropriate config. Please
1975 * see render_state_setup() in i915_gem_render_state.c for
1976 * possible configurations, to avoid duplication they are
1977 * not shown here again.
1979 *batch++ = GEN9_MEDIA_POOL_STATE;
1980 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1981 *batch++ = 0x00777000;
1987 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1989 /* Pad to end of cacheline */
1990 while ((unsigned long)batch % CACHELINE_BYTES)
1997 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
2002 * WaPipeControlBefore3DStateSamplePattern: cnl
2004 * Ensure the engine is idle prior to programming a
2005 * 3DSTATE_SAMPLE_PATTERN during a context restore.
2007 batch = gen8_emit_pipe_control(batch,
2008 PIPE_CONTROL_CS_STALL,
2011 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
2012 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
2013 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
2014 * confusing. Since gen8_emit_pipe_control() already advances the
2015 * batch by 6 dwords, we advance the other 10 here, completing a
2016 * cacheline. It's not clear if the workaround requires this padding
2017 * before other commands, or if it's just the regular padding we would
2018 * already have for the workaround bb, so leave it here for now.
2020 for (i = 0; i < 10; i++)
2023 /* Pad to end of cacheline */
2024 while ((unsigned long)batch % CACHELINE_BYTES)
2030 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
2032 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
2034 struct drm_i915_gem_object *obj;
2035 struct i915_vma *vma;
2038 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_OBJ_SIZE);
2040 return PTR_ERR(obj);
2042 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
2048 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
2052 engine->wa_ctx.vma = vma;
2056 i915_gem_object_put(obj);
2060 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
2062 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
2065 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
2067 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
2069 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2070 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
2072 wa_bb_func_t wa_bb_fn[2];
2074 void *batch, *batch_ptr;
2078 if (engine->class != RENDER_CLASS)
2081 switch (INTEL_GEN(engine->i915)) {
2085 wa_bb_fn[0] = gen10_init_indirectctx_bb;
2089 wa_bb_fn[0] = gen9_init_indirectctx_bb;
2093 wa_bb_fn[0] = gen8_init_indirectctx_bb;
2097 MISSING_CASE(INTEL_GEN(engine->i915));
2101 ret = lrc_setup_wa_ctx(engine);
2103 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
2107 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
2108 batch = batch_ptr = kmap_atomic(page);
2111 * Emit the two workaround batch buffers, recording the offset from the
2112 * start of the workaround batch buffer object for each and their
2115 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
2116 wa_bb[i]->offset = batch_ptr - batch;
2117 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
2118 CACHELINE_BYTES))) {
2123 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
2124 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
2127 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
2129 kunmap_atomic(batch);
2131 lrc_destroy_wa_ctx(engine);
2136 static void enable_execlists(struct intel_engine_cs *engine)
2140 assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
2142 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
2144 if (INTEL_GEN(engine->i915) >= 11)
2145 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
2147 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
2148 ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);
2150 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
2152 ENGINE_WRITE_FW(engine,
2154 i915_ggtt_offset(engine->status_page.vma));
2155 ENGINE_POSTING_READ(engine, RING_HWS_PGA);
2158 static bool unexpected_starting_state(struct intel_engine_cs *engine)
2160 bool unexpected = false;
2162 if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
2163 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
2170 static int execlists_resume(struct intel_engine_cs *engine)
2172 intel_engine_apply_workarounds(engine);
2173 intel_engine_apply_whitelist(engine);
2175 intel_mocs_init_engine(engine);
2177 intel_engine_reset_breadcrumbs(engine);
2179 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
2180 struct drm_printer p = drm_debug_printer(__func__);
2182 intel_engine_dump(engine, &p, NULL);
2185 enable_execlists(engine);
2190 static void execlists_reset_prepare(struct intel_engine_cs *engine)
2192 struct intel_engine_execlists * const execlists = &engine->execlists;
2193 unsigned long flags;
2195 GEM_TRACE("%s: depth<-%d\n", engine->name,
2196 atomic_read(&execlists->tasklet.count));
2199 * Prevent request submission to the hardware until we have
2200 * completed the reset in i915_gem_reset_finish(). If a request
2201 * is completed by one engine, it may then queue a request
2202 * to a second via its execlists->tasklet *just* as we are
2203 * calling engine->resume() and also writing the ELSP.
2204 * Turning off the execlists->tasklet until the reset is over
2205 * prevents the race.
2207 __tasklet_disable_sync_once(&execlists->tasklet);
2208 GEM_BUG_ON(!reset_in_progress(execlists));
2210 /* And flush any current direct submission. */
2211 spin_lock_irqsave(&engine->active.lock, flags);
2212 spin_unlock_irqrestore(&engine->active.lock, flags);
2215 * We stop engines, otherwise we might get failed reset and a
2216 * dead gpu (on elk). Also as modern gpu as kbl can suffer
2217 * from system hang if batchbuffer is progressing when
2218 * the reset is issued, regardless of READY_TO_RESET ack.
2219 * Thus assume it is best to stop engines on all gens
2220 * where we have a gpu reset.
2222 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
2224 * FIXME: Wa for more modern gens needs to be validated
2226 intel_engine_stop_cs(engine);
2229 static void reset_csb_pointers(struct intel_engine_cs *engine)
2231 struct intel_engine_execlists * const execlists = &engine->execlists;
2232 const unsigned int reset_value = execlists->csb_size - 1;
2234 ring_set_paused(engine, 0);
2237 * After a reset, the HW starts writing into CSB entry [0]. We
2238 * therefore have to set our HEAD pointer back one entry so that
2239 * the *first* entry we check is entry 0. To complicate this further,
2240 * as we don't wait for the first interrupt after reset, we have to
2241 * fake the HW write to point back to the last entry so that our
2242 * inline comparison of our cached head position against the last HW
2243 * write works even before the first interrupt.
2245 execlists->csb_head = reset_value;
2246 WRITE_ONCE(*execlists->csb_write, reset_value);
2247 wmb(); /* Make sure this is visible to HW (paranoia?) */
2249 invalidate_csb_entries(&execlists->csb_status[0],
2250 &execlists->csb_status[reset_value]);
2253 static struct i915_request *active_request(struct i915_request *rq)
2255 const struct list_head * const list = &rq->timeline->requests;
2256 const struct intel_context * const ce = rq->hw_context;
2257 struct i915_request *active = NULL;
2259 list_for_each_entry_from_reverse(rq, list, link) {
2260 if (i915_request_completed(rq))
2263 if (rq->hw_context != ce)
2272 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
2274 struct intel_engine_execlists * const execlists = &engine->execlists;
2275 struct intel_context *ce;
2276 struct i915_request *rq;
2279 process_csb(engine); /* drain preemption events */
2281 /* Following the reset, we need to reload the CSB read/write pointers */
2282 reset_csb_pointers(engine);
2285 * Save the currently executing context, even if we completed
2286 * its request, it was still running at the time of the
2287 * reset and will have been clobbered.
2289 rq = execlists_active(execlists);
2293 ce = rq->hw_context;
2294 GEM_BUG_ON(i915_active_is_idle(&ce->active));
2295 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
2296 rq = active_request(rq);
2298 ce->ring->head = ce->ring->tail;
2302 ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
2305 * If this request hasn't started yet, e.g. it is waiting on a
2306 * semaphore, we need to avoid skipping the request or else we
2307 * break the signaling chain. However, if the context is corrupt
2308 * the request will not restart and we will be stuck with a wedged
2309 * device. It is quite often the case that if we issue a reset
2310 * while the GPU is loading the context image, that the context
2311 * image becomes corrupt.
2313 * Otherwise, if we have not started yet, the request should replay
2314 * perfectly and we do not need to flag the result as being erroneous.
2316 if (!i915_request_started(rq))
2320 * If the request was innocent, we leave the request in the ELSP
2321 * and will try to replay it on restarting. The context image may
2322 * have been corrupted by the reset, in which case we may have
2323 * to service a new GPU hang, but more likely we can continue on
2326 * If the request was guilty, we presume the context is corrupt
2327 * and have to at least restore the RING register in the context
2328 * image back to the expected values to skip over the guilty request.
2330 __i915_request_reset(rq, stalled);
2335 * We want a simple context + ring to execute the breadcrumb update.
2336 * We cannot rely on the context being intact across the GPU hang,
2337 * so clear it and rebuild just what we need for the breadcrumb.
2338 * All pending requests for this context will be zapped, and any
2339 * future request will be after userspace has had the opportunity
2340 * to recreate its own state.
2342 regs = ce->lrc_reg_state;
2343 if (engine->pinned_default_state) {
2344 memcpy(regs, /* skip restoring the vanilla PPHWSP */
2345 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
2346 engine->context_size - PAGE_SIZE);
2348 execlists_init_reg_state(regs, ce, engine, ce->ring);
2351 GEM_TRACE("%s replay {head:%04x, tail:%04x\n",
2352 engine->name, ce->ring->head, ce->ring->tail);
2353 intel_ring_update_space(ce->ring);
2354 __execlists_update_reg_state(ce, engine);
2357 /* Push back any incomplete requests for replay after the reset. */
2358 execlists_cancel_port_requests(execlists);
2359 __unwind_incomplete_requests(engine);
2362 static void execlists_reset(struct intel_engine_cs *engine, bool stalled)
2364 unsigned long flags;
2366 GEM_TRACE("%s\n", engine->name);
2368 spin_lock_irqsave(&engine->active.lock, flags);
2370 __execlists_reset(engine, stalled);
2372 spin_unlock_irqrestore(&engine->active.lock, flags);
2375 static void nop_submission_tasklet(unsigned long data)
2377 /* The driver is wedged; don't process any more events. */
2380 static void execlists_cancel_requests(struct intel_engine_cs *engine)
2382 struct intel_engine_execlists * const execlists = &engine->execlists;
2383 struct i915_request *rq, *rn;
2385 unsigned long flags;
2387 GEM_TRACE("%s\n", engine->name);
2390 * Before we call engine->cancel_requests(), we should have exclusive
2391 * access to the submission state. This is arranged for us by the
2392 * caller disabling the interrupt generation, the tasklet and other
2393 * threads that may then access the same state, giving us a free hand
2394 * to reset state. However, we still need to let lockdep be aware that
2395 * we know this state may be accessed in hardirq context, so we
2396 * disable the irq around this manipulation and we want to keep
2397 * the spinlock focused on its duties and not accidentally conflate
2398 * coverage to the submission's irq state. (Similarly, although we
2399 * shouldn't need to disable irq around the manipulation of the
2400 * submission's irq state, we also wish to remind ourselves that
2403 spin_lock_irqsave(&engine->active.lock, flags);
2405 __execlists_reset(engine, true);
2407 /* Mark all executing requests as skipped. */
2408 list_for_each_entry(rq, &engine->active.requests, sched.link) {
2409 if (!i915_request_signaled(rq))
2410 dma_fence_set_error(&rq->fence, -EIO);
2412 i915_request_mark_complete(rq);
2415 /* Flush the queued requests to the timeline list (for retiring). */
2416 while ((rb = rb_first_cached(&execlists->queue))) {
2417 struct i915_priolist *p = to_priolist(rb);
2420 priolist_for_each_request_consume(rq, rn, p, i) {
2421 list_del_init(&rq->sched.link);
2422 __i915_request_submit(rq);
2423 dma_fence_set_error(&rq->fence, -EIO);
2424 i915_request_mark_complete(rq);
2427 rb_erase_cached(&p->node, &execlists->queue);
2428 i915_priolist_free(p);
2431 /* Cancel all attached virtual engines */
2432 while ((rb = rb_first_cached(&execlists->virtual))) {
2433 struct virtual_engine *ve =
2434 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
2436 rb_erase_cached(rb, &execlists->virtual);
2439 spin_lock(&ve->base.active.lock);
2441 ve->request->engine = engine;
2442 __i915_request_submit(ve->request);
2443 dma_fence_set_error(&ve->request->fence, -EIO);
2444 i915_request_mark_complete(ve->request);
2445 ve->base.execlists.queue_priority_hint = INT_MIN;
2448 spin_unlock(&ve->base.active.lock);
2451 /* Remaining _unready_ requests will be nop'ed when submitted */
2453 execlists->queue_priority_hint = INT_MIN;
2454 execlists->queue = RB_ROOT_CACHED;
2456 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
2457 execlists->tasklet.func = nop_submission_tasklet;
2459 spin_unlock_irqrestore(&engine->active.lock, flags);
2462 static void execlists_reset_finish(struct intel_engine_cs *engine)
2464 struct intel_engine_execlists * const execlists = &engine->execlists;
2467 * After a GPU reset, we may have requests to replay. Do so now while
2468 * we still have the forcewake to be sure that the GPU is not allowed
2469 * to sleep before we restart and reload a context.
2471 GEM_BUG_ON(!reset_in_progress(execlists));
2472 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
2473 execlists->tasklet.func(execlists->tasklet.data);
2475 if (__tasklet_enable(&execlists->tasklet))
2476 /* And kick in case we missed a new request submission. */
2477 tasklet_hi_schedule(&execlists->tasklet);
2478 GEM_TRACE("%s: depth->%d\n", engine->name,
2479 atomic_read(&execlists->tasklet.count));
2482 static int gen8_emit_bb_start(struct i915_request *rq,
2483 u64 offset, u32 len,
2484 const unsigned int flags)
2488 cs = intel_ring_begin(rq, 4);
2493 * WaDisableCtxRestoreArbitration:bdw,chv
2495 * We don't need to perform MI_ARB_ENABLE as often as we do (in
2496 * particular all the gen that do not need the w/a at all!), if we
2497 * took care to make sure that on every switch into this context
2498 * (both ordinary and for preemption) that arbitrartion was enabled
2499 * we would be fine. However, for gen8 there is another w/a that
2500 * requires us to not preempt inside GPGPU execution, so we keep
2501 * arbitration disabled for gen8 batches. Arbitration will be
2502 * re-enabled before we close the request
2503 * (engine->emit_fini_breadcrumb).
2505 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2507 /* FIXME(BDW+): Address space and security selectors. */
2508 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2509 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
2510 *cs++ = lower_32_bits(offset);
2511 *cs++ = upper_32_bits(offset);
2513 intel_ring_advance(rq, cs);
2518 static int gen9_emit_bb_start(struct i915_request *rq,
2519 u64 offset, u32 len,
2520 const unsigned int flags)
2524 cs = intel_ring_begin(rq, 6);
2528 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2530 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2531 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
2532 *cs++ = lower_32_bits(offset);
2533 *cs++ = upper_32_bits(offset);
2535 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2538 intel_ring_advance(rq, cs);
2543 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
2545 ENGINE_WRITE(engine, RING_IMR,
2546 ~(engine->irq_enable_mask | engine->irq_keep_mask));
2547 ENGINE_POSTING_READ(engine, RING_IMR);
2550 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
2552 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
2555 static int gen8_emit_flush(struct i915_request *request, u32 mode)
2559 cs = intel_ring_begin(request, 4);
2563 cmd = MI_FLUSH_DW + 1;
2565 /* We always require a command barrier so that subsequent
2566 * commands, such as breadcrumb interrupts, are strictly ordered
2567 * wrt the contents of the write cache being flushed to memory
2568 * (and thus being coherent from the CPU).
2570 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2572 if (mode & EMIT_INVALIDATE) {
2573 cmd |= MI_INVALIDATE_TLB;
2574 if (request->engine->class == VIDEO_DECODE_CLASS)
2575 cmd |= MI_INVALIDATE_BSD;
2579 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2580 *cs++ = 0; /* upper addr */
2581 *cs++ = 0; /* value */
2582 intel_ring_advance(request, cs);
2587 static int gen8_emit_flush_render(struct i915_request *request,
2590 struct intel_engine_cs *engine = request->engine;
2592 intel_gt_scratch_offset(engine->gt,
2593 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
2594 bool vf_flush_wa = false, dc_flush_wa = false;
2598 flags |= PIPE_CONTROL_CS_STALL;
2600 if (mode & EMIT_FLUSH) {
2601 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
2602 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
2603 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
2604 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2607 if (mode & EMIT_INVALIDATE) {
2608 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2609 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2610 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2611 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2612 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2613 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2614 flags |= PIPE_CONTROL_QW_WRITE;
2615 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2618 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
2621 if (IS_GEN(request->i915, 9))
2624 /* WaForGAMHang:kbl */
2625 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2637 cs = intel_ring_begin(request, len);
2642 cs = gen8_emit_pipe_control(cs, 0, 0);
2645 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2648 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2651 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2653 intel_ring_advance(request, cs);
2659 * Reserve space for 2 NOOPs at the end of each request to be
2660 * used as a workaround for not being allowed to do lite
2661 * restore with HEAD==TAIL (WaIdleLiteRestore).
2663 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2665 /* Ensure there's always at least one preemption point per-request. */
2666 *cs++ = MI_ARB_CHECK;
2668 request->wa_tail = intel_ring_offset(request, cs);
2673 static u32 *emit_preempt_busywait(struct i915_request *request, u32 *cs)
2675 *cs++ = MI_SEMAPHORE_WAIT |
2676 MI_SEMAPHORE_GLOBAL_GTT |
2678 MI_SEMAPHORE_SAD_EQ_SDD;
2680 *cs++ = intel_hws_preempt_address(request->engine);
2686 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
2688 cs = gen8_emit_ggtt_write(cs,
2689 request->fence.seqno,
2690 request->timeline->hwsp_offset,
2692 *cs++ = MI_USER_INTERRUPT;
2694 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2695 if (intel_engine_has_semaphores(request->engine))
2696 cs = emit_preempt_busywait(request, cs);
2698 request->tail = intel_ring_offset(request, cs);
2699 assert_ring_tail_valid(request->ring, request->tail);
2701 return gen8_emit_wa_tail(request, cs);
2704 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2706 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
2707 cs = gen8_emit_ggtt_write_rcs(cs,
2708 request->fence.seqno,
2709 request->timeline->hwsp_offset,
2710 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
2711 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
2712 PIPE_CONTROL_DC_FLUSH_ENABLE);
2713 cs = gen8_emit_pipe_control(cs,
2714 PIPE_CONTROL_FLUSH_ENABLE |
2715 PIPE_CONTROL_CS_STALL,
2717 *cs++ = MI_USER_INTERRUPT;
2719 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2720 if (intel_engine_has_semaphores(request->engine))
2721 cs = emit_preempt_busywait(request, cs);
2723 request->tail = intel_ring_offset(request, cs);
2724 assert_ring_tail_valid(request->ring, request->tail);
2726 return gen8_emit_wa_tail(request, cs);
2729 static void execlists_park(struct intel_engine_cs *engine)
2731 del_timer(&engine->execlists.timer);
2734 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
2736 engine->submit_request = execlists_submit_request;
2737 engine->cancel_requests = execlists_cancel_requests;
2738 engine->schedule = i915_schedule;
2739 engine->execlists.tasklet.func = execlists_submission_tasklet;
2741 engine->reset.prepare = execlists_reset_prepare;
2742 engine->reset.reset = execlists_reset;
2743 engine->reset.finish = execlists_reset_finish;
2745 engine->park = execlists_park;
2746 engine->unpark = NULL;
2748 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2749 if (!intel_vgpu_active(engine->i915)) {
2750 engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
2751 if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
2752 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
2756 static void execlists_destroy(struct intel_engine_cs *engine)
2758 intel_engine_cleanup_common(engine);
2759 lrc_destroy_wa_ctx(engine);
2764 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2766 /* Default vfuncs which can be overriden by each engine. */
2768 engine->destroy = execlists_destroy;
2769 engine->resume = execlists_resume;
2771 engine->reset.prepare = execlists_reset_prepare;
2772 engine->reset.reset = execlists_reset;
2773 engine->reset.finish = execlists_reset_finish;
2775 engine->cops = &execlists_context_ops;
2776 engine->request_alloc = execlists_request_alloc;
2778 engine->emit_flush = gen8_emit_flush;
2779 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
2780 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
2782 engine->set_default_submission = intel_execlists_set_default_submission;
2784 if (INTEL_GEN(engine->i915) < 11) {
2785 engine->irq_enable = gen8_logical_ring_enable_irq;
2786 engine->irq_disable = gen8_logical_ring_disable_irq;
2789 * TODO: On Gen11 interrupt masks need to be clear
2790 * to allow C6 entry. Keep interrupts enabled at
2791 * and take the hit of generating extra interrupts
2792 * until a more refined solution exists.
2795 if (IS_GEN(engine->i915, 8))
2796 engine->emit_bb_start = gen8_emit_bb_start;
2798 engine->emit_bb_start = gen9_emit_bb_start;
2802 logical_ring_default_irqs(struct intel_engine_cs *engine)
2804 unsigned int shift = 0;
2806 if (INTEL_GEN(engine->i915) < 11) {
2807 const u8 irq_shifts[] = {
2808 [RCS0] = GEN8_RCS_IRQ_SHIFT,
2809 [BCS0] = GEN8_BCS_IRQ_SHIFT,
2810 [VCS0] = GEN8_VCS0_IRQ_SHIFT,
2811 [VCS1] = GEN8_VCS1_IRQ_SHIFT,
2812 [VECS0] = GEN8_VECS_IRQ_SHIFT,
2815 shift = irq_shifts[engine->id];
2818 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2819 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2822 int intel_execlists_submission_setup(struct intel_engine_cs *engine)
2824 tasklet_init(&engine->execlists.tasklet,
2825 execlists_submission_tasklet, (unsigned long)engine);
2826 timer_setup(&engine->execlists.timer, execlists_submission_timer, 0);
2828 logical_ring_default_vfuncs(engine);
2829 logical_ring_default_irqs(engine);
2831 if (engine->class == RENDER_CLASS) {
2832 engine->emit_flush = gen8_emit_flush_render;
2833 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
2839 int intel_execlists_submission_init(struct intel_engine_cs *engine)
2841 struct intel_engine_execlists * const execlists = &engine->execlists;
2842 struct drm_i915_private *i915 = engine->i915;
2843 struct intel_uncore *uncore = engine->uncore;
2844 u32 base = engine->mmio_base;
2847 ret = intel_engine_init_common(engine);
2851 if (intel_init_workaround_bb(engine))
2853 * We continue even if we fail to initialize WA batch
2854 * because we only expect rare glitches but nothing
2855 * critical to prevent us from using GPU
2857 DRM_ERROR("WA batch buffer initialization failed\n");
2859 if (HAS_LOGICAL_RING_ELSQ(i915)) {
2860 execlists->submit_reg = uncore->regs +
2861 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
2862 execlists->ctrl_reg = uncore->regs +
2863 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
2865 execlists->submit_reg = uncore->regs +
2866 i915_mmio_reg_offset(RING_ELSP(base));
2869 execlists->csb_status =
2870 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
2872 execlists->csb_write =
2873 &engine->status_page.addr[intel_hws_csb_write_index(i915)];
2875 if (INTEL_GEN(i915) < 11)
2876 execlists->csb_size = GEN8_CSB_ENTRIES;
2878 execlists->csb_size = GEN11_CSB_ENTRIES;
2880 reset_csb_pointers(engine);
2885 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2887 u32 indirect_ctx_offset;
2889 switch (INTEL_GEN(engine->i915)) {
2891 MISSING_CASE(INTEL_GEN(engine->i915));
2894 indirect_ctx_offset =
2895 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2898 indirect_ctx_offset =
2899 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2902 indirect_ctx_offset =
2903 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2906 indirect_ctx_offset =
2907 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2911 return indirect_ctx_offset;
2914 static void execlists_init_reg_state(u32 *regs,
2915 struct intel_context *ce,
2916 struct intel_engine_cs *engine,
2917 struct intel_ring *ring)
2919 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
2920 bool rcs = engine->class == RENDER_CLASS;
2921 u32 base = engine->mmio_base;
2924 * A context is actually a big batch buffer with several
2925 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2926 * values we are setting here are only for the first context restore:
2927 * on a subsequent save, the GPU will recreate this batchbuffer with new
2928 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2929 * we are not initializing here).
2931 * Must keep consistent with virtual_update_register_offsets().
2933 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2934 MI_LRI_FORCE_POSTED;
2936 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
2937 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
2938 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
2939 if (INTEL_GEN(engine->i915) < 11) {
2940 regs[CTX_CONTEXT_CONTROL + 1] |=
2941 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
2942 CTX_CTRL_RS_CTX_ENABLE);
2944 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2945 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2946 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2947 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2948 RING_CTL_SIZE(ring->size) | RING_VALID);
2949 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2950 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2951 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2952 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2953 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2954 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2956 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2958 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2959 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2960 RING_INDIRECT_CTX_OFFSET(base), 0);
2961 if (wa_ctx->indirect_ctx.size) {
2962 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2964 regs[CTX_RCS_INDIRECT_CTX + 1] =
2965 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2966 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2968 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2969 intel_lr_indirect_ctx_offset(engine) << 6;
2972 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2973 if (wa_ctx->per_ctx.size) {
2974 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2976 regs[CTX_BB_PER_CTX_PTR + 1] =
2977 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2981 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2983 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2984 /* PDP values well be assigned later if needed */
2985 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
2986 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
2987 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0);
2988 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0);
2989 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0);
2990 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0);
2991 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0);
2992 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0);
2994 if (i915_vm_is_4lvl(&ppgtt->vm)) {
2995 /* 64b PPGTT (48bit canonical)
2996 * PDP0_DESCRIPTOR contains the base address to PML4 and
2997 * other PDP Descriptors are ignored.
2999 ASSIGN_CTX_PML4(ppgtt, regs);
3001 ASSIGN_CTX_PDP(ppgtt, regs, 3);
3002 ASSIGN_CTX_PDP(ppgtt, regs, 2);
3003 ASSIGN_CTX_PDP(ppgtt, regs, 1);
3004 ASSIGN_CTX_PDP(ppgtt, regs, 0);
3008 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
3009 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
3012 regs[CTX_END] = MI_BATCH_BUFFER_END;
3013 if (INTEL_GEN(engine->i915) >= 10)
3014 regs[CTX_END] |= BIT(0);
3018 populate_lr_context(struct intel_context *ce,
3019 struct drm_i915_gem_object *ctx_obj,
3020 struct intel_engine_cs *engine,
3021 struct intel_ring *ring)
3027 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
3028 if (IS_ERR(vaddr)) {
3029 ret = PTR_ERR(vaddr);
3030 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
3034 if (engine->default_state) {
3036 * We only want to copy over the template context state;
3037 * skipping over the headers reserved for GuC communication,
3038 * leaving those as zero.
3040 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
3043 defaults = i915_gem_object_pin_map(engine->default_state,
3045 if (IS_ERR(defaults)) {
3046 ret = PTR_ERR(defaults);
3050 memcpy(vaddr + start, defaults + start, engine->context_size);
3051 i915_gem_object_unpin_map(engine->default_state);
3054 /* The second page of the context object contains some fields which must
3055 * be set up prior to the first execution. */
3056 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
3057 execlists_init_reg_state(regs, ce, engine, ring);
3058 if (!engine->default_state)
3059 regs[CTX_CONTEXT_CONTROL + 1] |=
3060 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
3064 __i915_gem_object_flush_map(ctx_obj,
3065 LRC_HEADER_PAGES * PAGE_SIZE,
3066 engine->context_size);
3067 i915_gem_object_unpin_map(ctx_obj);
3071 static int __execlists_context_alloc(struct intel_context *ce,
3072 struct intel_engine_cs *engine)
3074 struct drm_i915_gem_object *ctx_obj;
3075 struct intel_ring *ring;
3076 struct i915_vma *vma;
3080 GEM_BUG_ON(ce->state);
3081 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
3084 * Before the actual start of the context image, we insert a few pages
3085 * for our own use and for sharing with the GuC.
3087 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
3089 ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
3090 if (IS_ERR(ctx_obj))
3091 return PTR_ERR(ctx_obj);
3093 vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
3096 goto error_deref_obj;
3099 if (!ce->timeline) {
3100 struct intel_timeline *tl;
3102 tl = intel_timeline_create(engine->gt, NULL);
3105 goto error_deref_obj;
3111 ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
3113 ret = PTR_ERR(ring);
3114 goto error_deref_obj;
3117 ret = populate_lr_context(ce, ctx_obj, engine, ring);
3119 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
3120 goto error_ring_free;
3129 intel_ring_put(ring);
3131 i915_gem_object_put(ctx_obj);
3135 static struct list_head *virtual_queue(struct virtual_engine *ve)
3137 return &ve->base.execlists.default_priolist.requests[0];
3140 static void virtual_context_destroy(struct kref *kref)
3142 struct virtual_engine *ve =
3143 container_of(kref, typeof(*ve), context.ref);
3146 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
3147 GEM_BUG_ON(ve->request);
3148 GEM_BUG_ON(ve->context.inflight);
3150 for (n = 0; n < ve->num_siblings; n++) {
3151 struct intel_engine_cs *sibling = ve->siblings[n];
3152 struct rb_node *node = &ve->nodes[sibling->id].rb;
3154 if (RB_EMPTY_NODE(node))
3157 spin_lock_irq(&sibling->active.lock);
3159 /* Detachment is lazily performed in the execlists tasklet */
3160 if (!RB_EMPTY_NODE(node))
3161 rb_erase_cached(node, &sibling->execlists.virtual);
3163 spin_unlock_irq(&sibling->active.lock);
3165 GEM_BUG_ON(__tasklet_is_scheduled(&ve->base.execlists.tasklet));
3167 if (ve->context.state)
3168 __execlists_context_fini(&ve->context);
3169 intel_context_fini(&ve->context);
3175 static void virtual_engine_initial_hint(struct virtual_engine *ve)
3180 * Pick a random sibling on starting to help spread the load around.
3182 * New contexts are typically created with exactly the same order
3183 * of siblings, and often started in batches. Due to the way we iterate
3184 * the array of sibling when submitting requests, sibling[0] is
3185 * prioritised for dequeuing. If we make sure that sibling[0] is fairly
3186 * randomised across the system, we also help spread the load by the
3187 * first engine we inspect being different each time.
3189 * NB This does not force us to execute on this engine, it will just
3190 * typically be the first we inspect for submission.
3192 swp = prandom_u32_max(ve->num_siblings);
3196 swap(ve->siblings[swp], ve->siblings[0]);
3197 virtual_update_register_offsets(ve->context.lrc_reg_state,
3201 static int virtual_context_pin(struct intel_context *ce)
3203 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3206 /* Note: we must use a real engine class for setting up reg state */
3207 err = __execlists_context_pin(ce, ve->siblings[0]);
3211 virtual_engine_initial_hint(ve);
3215 static void virtual_context_enter(struct intel_context *ce)
3217 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3220 for (n = 0; n < ve->num_siblings; n++)
3221 intel_engine_pm_get(ve->siblings[n]);
3224 static void virtual_context_exit(struct intel_context *ce)
3226 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
3229 for (n = 0; n < ve->num_siblings; n++)
3230 intel_engine_pm_put(ve->siblings[n]);
3233 static const struct intel_context_ops virtual_context_ops = {
3234 .pin = virtual_context_pin,
3235 .unpin = execlists_context_unpin,
3237 .enter = virtual_context_enter,
3238 .exit = virtual_context_exit,
3240 .destroy = virtual_context_destroy,
3243 static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve)
3245 struct i915_request *rq;
3246 intel_engine_mask_t mask;
3248 rq = READ_ONCE(ve->request);
3252 /* The rq is ready for submission; rq->execution_mask is now stable. */
3253 mask = rq->execution_mask;
3254 if (unlikely(!mask)) {
3255 /* Invalid selection, submit to a random engine in error */
3256 i915_request_skip(rq, -ENODEV);
3257 mask = ve->siblings[0]->mask;
3260 GEM_TRACE("%s: rq=%llx:%lld, mask=%x, prio=%d\n",
3262 rq->fence.context, rq->fence.seqno,
3263 mask, ve->base.execlists.queue_priority_hint);
3268 static void virtual_submission_tasklet(unsigned long data)
3270 struct virtual_engine * const ve = (struct virtual_engine *)data;
3271 const int prio = ve->base.execlists.queue_priority_hint;
3272 intel_engine_mask_t mask;
3276 mask = virtual_submission_mask(ve);
3278 if (unlikely(!mask))
3281 local_irq_disable();
3282 for (n = 0; READ_ONCE(ve->request) && n < ve->num_siblings; n++) {
3283 struct intel_engine_cs *sibling = ve->siblings[n];
3284 struct ve_node * const node = &ve->nodes[sibling->id];
3285 struct rb_node **parent, *rb;
3288 if (unlikely(!(mask & sibling->mask))) {
3289 if (!RB_EMPTY_NODE(&node->rb)) {
3290 spin_lock(&sibling->active.lock);
3291 rb_erase_cached(&node->rb,
3292 &sibling->execlists.virtual);
3293 RB_CLEAR_NODE(&node->rb);
3294 spin_unlock(&sibling->active.lock);
3299 spin_lock(&sibling->active.lock);
3301 if (!RB_EMPTY_NODE(&node->rb)) {
3303 * Cheat and avoid rebalancing the tree if we can
3304 * reuse this node in situ.
3306 first = rb_first_cached(&sibling->execlists.virtual) ==
3308 if (prio == node->prio || (prio > node->prio && first))
3311 rb_erase_cached(&node->rb, &sibling->execlists.virtual);
3316 parent = &sibling->execlists.virtual.rb_root.rb_node;
3318 struct ve_node *other;
3321 other = rb_entry(rb, typeof(*other), rb);
3322 if (prio > other->prio) {
3323 parent = &rb->rb_left;
3325 parent = &rb->rb_right;
3330 rb_link_node(&node->rb, rb, parent);
3331 rb_insert_color_cached(&node->rb,
3332 &sibling->execlists.virtual,
3336 GEM_BUG_ON(RB_EMPTY_NODE(&node->rb));
3338 if (first && prio > sibling->execlists.queue_priority_hint) {
3339 sibling->execlists.queue_priority_hint = prio;
3340 tasklet_hi_schedule(&sibling->execlists.tasklet);
3343 spin_unlock(&sibling->active.lock);
3348 static void virtual_submit_request(struct i915_request *rq)
3350 struct virtual_engine *ve = to_virtual_engine(rq->engine);
3352 GEM_TRACE("%s: rq=%llx:%lld\n",
3357 GEM_BUG_ON(ve->base.submit_request != virtual_submit_request);
3359 GEM_BUG_ON(ve->request);
3360 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
3362 ve->base.execlists.queue_priority_hint = rq_prio(rq);
3363 WRITE_ONCE(ve->request, rq);
3365 list_move_tail(&rq->sched.link, virtual_queue(ve));
3367 tasklet_schedule(&ve->base.execlists.tasklet);
3370 static struct ve_bond *
3371 virtual_find_bond(struct virtual_engine *ve,
3372 const struct intel_engine_cs *master)
3376 for (i = 0; i < ve->num_bonds; i++) {
3377 if (ve->bonds[i].master == master)
3378 return &ve->bonds[i];
3385 virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
3387 struct virtual_engine *ve = to_virtual_engine(rq->engine);
3388 struct ve_bond *bond;
3390 bond = virtual_find_bond(ve, to_request(signal)->engine);
3392 intel_engine_mask_t old, new, cmp;
3394 cmp = READ_ONCE(rq->execution_mask);
3397 new = cmp & bond->sibling_mask;
3398 } while ((cmp = cmpxchg(&rq->execution_mask, old, new)) != old);
3402 struct intel_context *
3403 intel_execlists_create_virtual(struct i915_gem_context *ctx,
3404 struct intel_engine_cs **siblings,
3407 struct virtual_engine *ve;
3412 return ERR_PTR(-EINVAL);
3415 return intel_context_create(ctx, siblings[0]);
3417 ve = kzalloc(struct_size(ve, siblings, count), GFP_KERNEL);
3419 return ERR_PTR(-ENOMEM);
3421 ve->base.i915 = ctx->i915;
3422 ve->base.gt = siblings[0]->gt;
3424 ve->base.class = OTHER_CLASS;
3425 ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
3426 ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
3429 * The decision on whether to submit a request using semaphores
3430 * depends on the saturated state of the engine. We only compute
3431 * this during HW submission of the request, and we need for this
3432 * state to be globally applied to all requests being submitted
3433 * to this engine. Virtual engines encompass more than one physical
3434 * engine and so we cannot accurately tell in advance if one of those
3435 * engines is already saturated and so cannot afford to use a semaphore
3436 * and be pessimized in priority for doing so -- if we are the only
3437 * context using semaphores after all other clients have stopped, we
3438 * will be starved on the saturated system. Such a global switch for
3439 * semaphores is less than ideal, but alas is the current compromise.
3441 ve->base.saturated = ALL_ENGINES;
3443 snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
3445 intel_engine_init_active(&ve->base, ENGINE_VIRTUAL);
3447 intel_engine_init_execlists(&ve->base);
3449 ve->base.cops = &virtual_context_ops;
3450 ve->base.request_alloc = execlists_request_alloc;
3452 ve->base.schedule = i915_schedule;
3453 ve->base.submit_request = virtual_submit_request;
3454 ve->base.bond_execute = virtual_bond_execute;
3456 INIT_LIST_HEAD(virtual_queue(ve));
3457 ve->base.execlists.queue_priority_hint = INT_MIN;
3458 tasklet_init(&ve->base.execlists.tasklet,
3459 virtual_submission_tasklet,
3462 intel_context_init(&ve->context, ctx, &ve->base);
3464 for (n = 0; n < count; n++) {
3465 struct intel_engine_cs *sibling = siblings[n];
3467 GEM_BUG_ON(!is_power_of_2(sibling->mask));
3468 if (sibling->mask & ve->base.mask) {
3469 DRM_DEBUG("duplicate %s entry in load balancer\n",
3476 * The virtual engine implementation is tightly coupled to
3477 * the execlists backend -- we push out request directly
3478 * into a tree inside each physical engine. We could support
3479 * layering if we handle cloning of the requests and
3480 * submitting a copy into each backend.
3482 if (sibling->execlists.tasklet.func !=
3483 execlists_submission_tasklet) {
3488 GEM_BUG_ON(RB_EMPTY_NODE(&ve->nodes[sibling->id].rb));
3489 RB_CLEAR_NODE(&ve->nodes[sibling->id].rb);
3491 ve->siblings[ve->num_siblings++] = sibling;
3492 ve->base.mask |= sibling->mask;
3495 * All physical engines must be compatible for their emission
3496 * functions (as we build the instructions during request
3497 * construction and do not alter them before submission
3498 * on the physical engine). We use the engine class as a guide
3499 * here, although that could be refined.
3501 if (ve->base.class != OTHER_CLASS) {
3502 if (ve->base.class != sibling->class) {
3503 DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
3504 sibling->class, ve->base.class);
3511 ve->base.class = sibling->class;
3512 ve->base.uabi_class = sibling->uabi_class;
3513 snprintf(ve->base.name, sizeof(ve->base.name),
3514 "v%dx%d", ve->base.class, count);
3515 ve->base.context_size = sibling->context_size;
3517 ve->base.emit_bb_start = sibling->emit_bb_start;
3518 ve->base.emit_flush = sibling->emit_flush;
3519 ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb;
3520 ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb;
3521 ve->base.emit_fini_breadcrumb_dw =
3522 sibling->emit_fini_breadcrumb_dw;
3524 ve->base.flags = sibling->flags;
3527 ve->base.flags |= I915_ENGINE_IS_VIRTUAL;
3529 err = __execlists_context_alloc(&ve->context, siblings[0]);
3533 __set_bit(CONTEXT_ALLOC_BIT, &ve->context.flags);
3535 return &ve->context;
3538 intel_context_put(&ve->context);
3539 return ERR_PTR(err);
3542 struct intel_context *
3543 intel_execlists_clone_virtual(struct i915_gem_context *ctx,
3544 struct intel_engine_cs *src)
3546 struct virtual_engine *se = to_virtual_engine(src);
3547 struct intel_context *dst;
3549 dst = intel_execlists_create_virtual(ctx,
3555 if (se->num_bonds) {
3556 struct virtual_engine *de = to_virtual_engine(dst->engine);
3558 de->bonds = kmemdup(se->bonds,
3559 sizeof(*se->bonds) * se->num_bonds,
3562 intel_context_put(dst);
3563 return ERR_PTR(-ENOMEM);
3566 de->num_bonds = se->num_bonds;
3572 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
3573 const struct intel_engine_cs *master,
3574 const struct intel_engine_cs *sibling)
3576 struct virtual_engine *ve = to_virtual_engine(engine);
3577 struct ve_bond *bond;
3580 /* Sanity check the sibling is part of the virtual engine */
3581 for (n = 0; n < ve->num_siblings; n++)
3582 if (sibling == ve->siblings[n])
3584 if (n == ve->num_siblings)
3587 bond = virtual_find_bond(ve, master);
3589 bond->sibling_mask |= sibling->mask;
3593 bond = krealloc(ve->bonds,
3594 sizeof(*bond) * (ve->num_bonds + 1),
3599 bond[ve->num_bonds].master = master;
3600 bond[ve->num_bonds].sibling_mask = sibling->mask;
3608 void intel_execlists_show_requests(struct intel_engine_cs *engine,
3609 struct drm_printer *m,
3610 void (*show_request)(struct drm_printer *m,
3611 struct i915_request *rq,
3612 const char *prefix),
3615 const struct intel_engine_execlists *execlists = &engine->execlists;
3616 struct i915_request *rq, *last;
3617 unsigned long flags;
3621 spin_lock_irqsave(&engine->active.lock, flags);
3625 list_for_each_entry(rq, &engine->active.requests, sched.link) {
3626 if (count++ < max - 1)
3627 show_request(m, rq, "\t\tE ");
3634 "\t\t...skipping %d executing requests...\n",
3637 show_request(m, last, "\t\tE ");
3642 if (execlists->queue_priority_hint != INT_MIN)
3643 drm_printf(m, "\t\tQueue priority hint: %d\n",
3644 execlists->queue_priority_hint);
3645 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
3646 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
3649 priolist_for_each_request(rq, p, i) {
3650 if (count++ < max - 1)
3651 show_request(m, rq, "\t\tQ ");
3659 "\t\t...skipping %d queued requests...\n",
3662 show_request(m, last, "\t\tQ ");
3667 for (rb = rb_first_cached(&execlists->virtual); rb; rb = rb_next(rb)) {
3668 struct virtual_engine *ve =
3669 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
3670 struct i915_request *rq = READ_ONCE(ve->request);
3673 if (count++ < max - 1)
3674 show_request(m, rq, "\t\tV ");
3682 "\t\t...skipping %d virtual requests...\n",
3685 show_request(m, last, "\t\tV ");
3688 spin_unlock_irqrestore(&engine->active.lock, flags);
3691 void intel_lr_context_reset(struct intel_engine_cs *engine,
3692 struct intel_context *ce,
3697 * We want a simple context + ring to execute the breadcrumb update.
3698 * We cannot rely on the context being intact across the GPU hang,
3699 * so clear it and rebuild just what we need for the breadcrumb.
3700 * All pending requests for this context will be zapped, and any
3701 * future request will be after userspace has had the opportunity
3702 * to recreate its own state.
3705 u32 *regs = ce->lrc_reg_state;
3707 if (engine->pinned_default_state) {
3708 memcpy(regs, /* skip restoring the vanilla PPHWSP */
3709 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
3710 engine->context_size - PAGE_SIZE);
3712 execlists_init_reg_state(regs, ce, engine, ce->ring);
3715 /* Rerun the request; its payload has been neutered (if guilty). */
3716 ce->ring->head = head;
3717 intel_ring_update_space(ce->ring);
3719 __execlists_update_reg_state(ce, engine);
3722 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3723 #include "selftest_lrc.c"