2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008-2018 Intel Corporation
7 #include <linux/sched/mm.h>
8 #include <linux/stop_machine.h>
10 #include "display/intel_display_types.h"
11 #include "display/intel_overlay.h"
13 #include "gem/i915_gem_context.h"
16 #include "i915_gpu_error.h"
18 #include "intel_engine_pm.h"
20 #include "intel_gt_pm.h"
21 #include "intel_reset.h"
23 #include "uc/intel_guc.h"
25 #define RESET_MAX_RETRIES 3
27 /* XXX How to handle concurrent GGTT updates using tiling registers? */
28 #define RESET_UNDER_STOP_MACHINE 0
30 static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
32 intel_uncore_rmw_fw(uncore, reg, 0, set);
35 static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
37 intel_uncore_rmw_fw(uncore, reg, clr, 0);
40 static void engine_skip_context(struct i915_request *rq)
42 struct intel_engine_cs *engine = rq->engine;
43 struct i915_gem_context *hung_ctx = rq->gem_context;
45 lockdep_assert_held(&engine->active.lock);
47 if (!i915_request_is_active(rq))
50 list_for_each_entry_continue(rq, &engine->active.requests, sched.link)
51 if (rq->gem_context == hung_ctx)
52 i915_request_skip(rq, -EIO);
55 static void client_mark_guilty(struct drm_i915_file_private *file_priv,
56 const struct i915_gem_context *ctx)
59 unsigned long prev_hang;
61 if (i915_gem_context_is_banned(ctx))
62 score = I915_CLIENT_SCORE_CONTEXT_BAN;
66 prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
67 if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
68 score += I915_CLIENT_SCORE_HANG_FAST;
71 atomic_add(score, &file_priv->ban_score);
73 DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
75 atomic_read(&file_priv->ban_score));
79 static bool context_mark_guilty(struct i915_gem_context *ctx)
81 unsigned long prev_hang;
85 atomic_inc(&ctx->guilty_count);
87 /* Cool contexts are too cool to be banned! (Used for reset testing.) */
88 if (!i915_gem_context_is_bannable(ctx))
91 /* Record the timestamp for the last N hangs */
92 prev_hang = ctx->hang_timestamp[0];
93 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
94 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
95 ctx->hang_timestamp[i] = jiffies;
97 /* If we have hung N+1 times in rapid succession, we ban the context! */
98 banned = !i915_gem_context_is_recoverable(ctx);
99 if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
102 DRM_DEBUG_DRIVER("context %s: guilty %d, banned\n",
103 ctx->name, atomic_read(&ctx->guilty_count));
104 i915_gem_context_set_banned(ctx);
107 if (!IS_ERR_OR_NULL(ctx->file_priv))
108 client_mark_guilty(ctx->file_priv, ctx);
113 static void context_mark_innocent(struct i915_gem_context *ctx)
115 atomic_inc(&ctx->active_count);
118 void __i915_request_reset(struct i915_request *rq, bool guilty)
120 GEM_TRACE("%s rq=%llx:%lld, guilty? %s\n",
126 lockdep_assert_held(&rq->engine->active.lock);
127 GEM_BUG_ON(i915_request_completed(rq));
130 i915_request_skip(rq, -EIO);
131 if (context_mark_guilty(rq->gem_context))
132 engine_skip_context(rq);
134 dma_fence_set_error(&rq->fence, -EAGAIN);
135 context_mark_innocent(rq->gem_context);
139 static bool i915_in_reset(struct pci_dev *pdev)
143 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
144 return gdrst & GRDOM_RESET_STATUS;
147 static int i915_do_reset(struct intel_gt *gt,
148 intel_engine_mask_t engine_mask,
151 struct pci_dev *pdev = gt->i915->drm.pdev;
154 /* Assert reset for at least 20 usec, and wait for acknowledgement. */
155 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
157 err = wait_for_atomic(i915_in_reset(pdev), 50);
159 /* Clear the reset request. */
160 pci_write_config_byte(pdev, I915_GDRST, 0);
163 err = wait_for_atomic(!i915_in_reset(pdev), 50);
168 static bool g4x_reset_complete(struct pci_dev *pdev)
172 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
173 return (gdrst & GRDOM_RESET_ENABLE) == 0;
176 static int g33_do_reset(struct intel_gt *gt,
177 intel_engine_mask_t engine_mask,
180 struct pci_dev *pdev = gt->i915->drm.pdev;
182 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
183 return wait_for_atomic(g4x_reset_complete(pdev), 50);
186 static int g4x_do_reset(struct intel_gt *gt,
187 intel_engine_mask_t engine_mask,
190 struct pci_dev *pdev = gt->i915->drm.pdev;
191 struct intel_uncore *uncore = gt->uncore;
194 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
195 rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
196 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
198 pci_write_config_byte(pdev, I915_GDRST,
199 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
200 ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
202 DRM_DEBUG_DRIVER("Wait for media reset failed\n");
206 pci_write_config_byte(pdev, I915_GDRST,
207 GRDOM_RENDER | GRDOM_RESET_ENABLE);
208 ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
210 DRM_DEBUG_DRIVER("Wait for render reset failed\n");
215 pci_write_config_byte(pdev, I915_GDRST, 0);
217 rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
218 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
223 static int ironlake_do_reset(struct intel_gt *gt,
224 intel_engine_mask_t engine_mask,
227 struct intel_uncore *uncore = gt->uncore;
230 intel_uncore_write_fw(uncore, ILK_GDSR,
231 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
232 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
233 ILK_GRDOM_RESET_ENABLE, 0,
237 DRM_DEBUG_DRIVER("Wait for render reset failed\n");
241 intel_uncore_write_fw(uncore, ILK_GDSR,
242 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
243 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
244 ILK_GRDOM_RESET_ENABLE, 0,
248 DRM_DEBUG_DRIVER("Wait for media reset failed\n");
253 intel_uncore_write_fw(uncore, ILK_GDSR, 0);
254 intel_uncore_posting_read_fw(uncore, ILK_GDSR);
258 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
259 static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
261 struct intel_uncore *uncore = gt->uncore;
265 * GEN6_GDRST is not in the gt power well, no need to check
266 * for fifo space for the write or forcewake the chip for
269 intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
271 /* Wait for the device to ack the reset requests */
272 err = __intel_wait_for_register_fw(uncore,
273 GEN6_GDRST, hw_domain_mask, 0,
277 DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n",
283 static int gen6_reset_engines(struct intel_gt *gt,
284 intel_engine_mask_t engine_mask,
287 struct intel_engine_cs *engine;
288 const u32 hw_engine_mask[] = {
289 [RCS0] = GEN6_GRDOM_RENDER,
290 [BCS0] = GEN6_GRDOM_BLT,
291 [VCS0] = GEN6_GRDOM_MEDIA,
292 [VCS1] = GEN8_GRDOM_MEDIA2,
293 [VECS0] = GEN6_GRDOM_VECS,
297 if (engine_mask == ALL_ENGINES) {
298 hw_mask = GEN6_GRDOM_FULL;
300 intel_engine_mask_t tmp;
303 for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
304 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
305 hw_mask |= hw_engine_mask[engine->id];
309 return gen6_hw_domain_reset(gt, hw_mask);
312 static u32 gen11_lock_sfc(struct intel_engine_cs *engine)
314 struct intel_uncore *uncore = engine->uncore;
315 u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
316 i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
317 u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
318 i915_reg_t sfc_usage;
322 switch (engine->class) {
323 case VIDEO_DECODE_CLASS:
324 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
327 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
328 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
330 sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine);
331 sfc_forced_lock_ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT;
333 sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine);
334 sfc_usage_bit = GEN11_VCS_SFC_USAGE_BIT;
335 sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
338 case VIDEO_ENHANCEMENT_CLASS:
339 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
340 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
342 sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine);
343 sfc_forced_lock_ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT;
345 sfc_usage = GEN11_VECS_SFC_USAGE(engine);
346 sfc_usage_bit = GEN11_VECS_SFC_USAGE_BIT;
347 sfc_reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
355 * Tell the engine that a software reset is going to happen. The engine
356 * will then try to force lock the SFC (if currently locked, it will
357 * remain so until we tell the engine it is safe to unlock; if currently
358 * unlocked, it will ignore this and all new lock requests). If SFC
359 * ends up being locked to the engine we want to reset, we have to reset
360 * it as well (we will unlock it once the reset sequence is completed).
362 rmw_set_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
364 if (__intel_wait_for_register_fw(uncore,
366 sfc_forced_lock_ack_bit,
367 sfc_forced_lock_ack_bit,
369 DRM_DEBUG_DRIVER("Wait for SFC forced lock ack failed\n");
373 if (intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit)
374 return sfc_reset_bit;
379 static void gen11_unlock_sfc(struct intel_engine_cs *engine)
381 struct intel_uncore *uncore = engine->uncore;
382 u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
383 i915_reg_t sfc_forced_lock;
384 u32 sfc_forced_lock_bit;
386 switch (engine->class) {
387 case VIDEO_DECODE_CLASS:
388 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
391 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
392 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
395 case VIDEO_ENHANCEMENT_CLASS:
396 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
397 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
404 rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
407 static int gen11_reset_engines(struct intel_gt *gt,
408 intel_engine_mask_t engine_mask,
411 const u32 hw_engine_mask[] = {
412 [RCS0] = GEN11_GRDOM_RENDER,
413 [BCS0] = GEN11_GRDOM_BLT,
414 [VCS0] = GEN11_GRDOM_MEDIA,
415 [VCS1] = GEN11_GRDOM_MEDIA2,
416 [VCS2] = GEN11_GRDOM_MEDIA3,
417 [VCS3] = GEN11_GRDOM_MEDIA4,
418 [VECS0] = GEN11_GRDOM_VECS,
419 [VECS1] = GEN11_GRDOM_VECS2,
421 struct intel_engine_cs *engine;
422 intel_engine_mask_t tmp;
426 if (engine_mask == ALL_ENGINES) {
427 hw_mask = GEN11_GRDOM_FULL;
430 for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
431 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
432 hw_mask |= hw_engine_mask[engine->id];
433 hw_mask |= gen11_lock_sfc(engine);
437 ret = gen6_hw_domain_reset(gt, hw_mask);
439 if (engine_mask != ALL_ENGINES)
440 for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
441 gen11_unlock_sfc(engine);
446 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
448 struct intel_uncore *uncore = engine->uncore;
449 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
450 u32 request, mask, ack;
453 ack = intel_uncore_read_fw(uncore, reg);
454 if (ack & RESET_CTL_CAT_ERROR) {
456 * For catastrophic errors, ready-for-reset sequence
457 * needs to be bypassed: HAS#396813
459 request = RESET_CTL_CAT_ERROR;
460 mask = RESET_CTL_CAT_ERROR;
462 /* Catastrophic errors need to be cleared by HW */
464 } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
465 request = RESET_CTL_REQUEST_RESET;
466 mask = RESET_CTL_READY_TO_RESET;
467 ack = RESET_CTL_READY_TO_RESET;
472 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
473 ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
476 DRM_ERROR("%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
477 engine->name, request,
478 intel_uncore_read_fw(uncore, reg));
483 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
485 intel_uncore_write_fw(engine->uncore,
486 RING_RESET_CTL(engine->mmio_base),
487 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
490 static int gen8_reset_engines(struct intel_gt *gt,
491 intel_engine_mask_t engine_mask,
494 struct intel_engine_cs *engine;
495 const bool reset_non_ready = retry >= 1;
496 intel_engine_mask_t tmp;
499 for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
500 ret = gen8_engine_reset_prepare(engine);
501 if (ret && !reset_non_ready)
505 * If this is not the first failed attempt to prepare,
506 * we decide to proceed anyway.
508 * By doing so we risk context corruption and with
509 * some gens (kbl), possible system hang if reset
510 * happens during active bb execution.
512 * We rather take context corruption instead of
513 * failed reset with a wedged driver/gpu. And
514 * active bb execution case should be covered by
515 * stop_engines() we have before the reset.
519 if (INTEL_GEN(gt->i915) >= 11)
520 ret = gen11_reset_engines(gt, engine_mask, retry);
522 ret = gen6_reset_engines(gt, engine_mask, retry);
525 for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
526 gen8_engine_reset_cancel(engine);
531 typedef int (*reset_func)(struct intel_gt *,
532 intel_engine_mask_t engine_mask,
535 static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
537 if (INTEL_GEN(i915) >= 8)
538 return gen8_reset_engines;
539 else if (INTEL_GEN(i915) >= 6)
540 return gen6_reset_engines;
541 else if (INTEL_GEN(i915) >= 5)
542 return ironlake_do_reset;
543 else if (IS_G4X(i915))
545 else if (IS_G33(i915) || IS_PINEVIEW(i915))
547 else if (INTEL_GEN(i915) >= 3)
548 return i915_do_reset;
553 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
555 const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
557 int ret = -ETIMEDOUT;
560 reset = intel_get_gpu_reset(gt->i915);
565 * If the power well sleeps during the reset, the reset
566 * request may be dropped and never completes (causing -EIO).
568 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
569 for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
570 GEM_TRACE("engine_mask=%x\n", engine_mask);
572 ret = reset(gt, engine_mask, retry);
575 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
580 bool intel_has_gpu_reset(struct drm_i915_private *i915)
582 if (!i915_modparams.reset)
585 return intel_get_gpu_reset(i915);
588 bool intel_has_reset_engine(struct drm_i915_private *i915)
590 return INTEL_INFO(i915)->has_reset_engine && i915_modparams.reset >= 2;
593 int intel_reset_guc(struct intel_gt *gt)
596 INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
599 GEM_BUG_ON(!HAS_GT_UC(gt->i915));
601 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
602 ret = gen6_hw_domain_reset(gt, guc_domain);
603 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
609 * Ensure irq handler finishes, and not run again.
610 * Also return the active request so that we only search for it once.
612 static void reset_prepare_engine(struct intel_engine_cs *engine)
615 * During the reset sequence, we must prevent the engine from
616 * entering RC6. As the context state is undefined until we restart
617 * the engine, if it does enter RC6 during the reset, the state
618 * written to the powercontext is undefined and so we may lose
619 * GPU state upon resume, i.e. fail to restart after a reset.
621 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
622 engine->reset.prepare(engine);
625 static void revoke_mmaps(struct intel_gt *gt)
629 for (i = 0; i < gt->ggtt->num_fences; i++) {
630 struct drm_vma_offset_node *node;
631 struct i915_vma *vma;
634 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
638 if (!i915_vma_has_userfault(vma))
641 GEM_BUG_ON(vma->fence != >->ggtt->fence_regs[i]);
642 node = &vma->obj->base.vma_node;
643 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
644 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
645 drm_vma_node_offset_addr(node) + vma_offset,
651 static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
653 struct intel_engine_cs *engine;
654 intel_engine_mask_t awake = 0;
655 enum intel_engine_id id;
657 for_each_engine(engine, gt->i915, id) {
658 if (intel_engine_pm_get_if_awake(engine))
659 awake |= engine->mask;
660 reset_prepare_engine(engine);
663 intel_uc_reset_prepare(>->uc);
668 static void gt_revoke(struct intel_gt *gt)
673 static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
675 struct intel_engine_cs *engine;
676 enum intel_engine_id id;
680 * Everything depends on having the GTT running, so we need to start
683 err = i915_ggtt_enable_hw(gt->i915);
687 for_each_engine(engine, gt->i915, id)
688 __intel_engine_reset(engine, stalled_mask & engine->mask);
690 i915_gem_restore_fences(gt->i915);
695 static void reset_finish_engine(struct intel_engine_cs *engine)
697 engine->reset.finish(engine);
698 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
700 intel_engine_signal_breadcrumbs(engine);
703 static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
705 struct intel_engine_cs *engine;
706 enum intel_engine_id id;
708 for_each_engine(engine, gt->i915, id) {
709 reset_finish_engine(engine);
710 if (awake & engine->mask)
711 intel_engine_pm_put(engine);
715 static void nop_submit_request(struct i915_request *request)
717 struct intel_engine_cs *engine = request->engine;
720 GEM_TRACE("%s fence %llx:%lld -> -EIO\n",
721 engine->name, request->fence.context, request->fence.seqno);
722 dma_fence_set_error(&request->fence, -EIO);
724 spin_lock_irqsave(&engine->active.lock, flags);
725 __i915_request_submit(request);
726 i915_request_mark_complete(request);
727 spin_unlock_irqrestore(&engine->active.lock, flags);
729 intel_engine_queue_breadcrumbs(engine);
732 static void __intel_gt_set_wedged(struct intel_gt *gt)
734 struct intel_engine_cs *engine;
735 intel_engine_mask_t awake;
736 enum intel_engine_id id;
738 if (test_bit(I915_WEDGED, >->reset.flags))
741 if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
742 struct drm_printer p = drm_debug_printer(__func__);
744 for_each_engine(engine, gt->i915, id)
745 intel_engine_dump(engine, &p, "%s\n", engine->name);
748 GEM_TRACE("start\n");
751 * First, stop submission to hw, but do not yet complete requests by
752 * rolling the global seqno forward (since this would complete requests
753 * for which we haven't set the fence error to EIO yet).
755 awake = reset_prepare(gt);
757 /* Even if the GPU reset fails, it should still stop the engines */
758 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
759 __intel_gt_reset(gt, ALL_ENGINES);
761 for_each_engine(engine, gt->i915, id)
762 engine->submit_request = nop_submit_request;
765 * Make sure no request can slip through without getting completed by
766 * either this call here to intel_engine_write_global_seqno, or the one
767 * in nop_submit_request.
769 synchronize_rcu_expedited();
770 set_bit(I915_WEDGED, >->reset.flags);
772 /* Mark all executing requests as skipped */
773 for_each_engine(engine, gt->i915, id)
774 engine->cancel_requests(engine);
776 reset_finish(gt, awake);
781 void intel_gt_set_wedged(struct intel_gt *gt)
783 intel_wakeref_t wakeref;
785 mutex_lock(>->reset.mutex);
786 with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
787 __intel_gt_set_wedged(gt);
788 mutex_unlock(>->reset.mutex);
791 static bool __intel_gt_unset_wedged(struct intel_gt *gt)
793 struct intel_gt_timelines *timelines = >->timelines;
794 struct intel_timeline *tl;
796 if (!test_bit(I915_WEDGED, >->reset.flags))
799 if (!gt->scratch) /* Never full initialised, recovery impossible */
802 GEM_TRACE("start\n");
805 * Before unwedging, make sure that all pending operations
806 * are flushed and errored out - we may have requests waiting upon
807 * third party fences. We marked all inflight requests as EIO, and
808 * every execbuf since returned EIO, for consistency we want all
809 * the currently pending requests to also be marked as EIO, which
810 * is done inside our nop_submit_request - and so we must wait.
812 * No more can be submitted until we reset the wedged bit.
814 mutex_lock(&timelines->mutex);
815 list_for_each_entry(tl, &timelines->active_list, link) {
816 struct i915_request *rq;
818 rq = i915_active_request_get_unlocked(&tl->last_request);
823 * All internal dependencies (i915_requests) will have
824 * been flushed by the set-wedge, but we may be stuck waiting
825 * for external fences. These should all be capped to 10s
826 * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
829 dma_fence_default_wait(&rq->fence, false, MAX_SCHEDULE_TIMEOUT);
830 i915_request_put(rq);
832 mutex_unlock(&timelines->mutex);
834 intel_gt_sanitize(gt, false);
837 * Undo nop_submit_request. We prevent all new i915 requests from
838 * being queued (by disallowing execbuf whilst wedged) so having
839 * waited for all active requests above, we know the system is idle
840 * and do not have to worry about a thread being inside
841 * engine->submit_request() as we swap over. So unlike installing
842 * the nop_submit_request on reset, we can do this from normal
843 * context and do not require stop_machine().
845 intel_engines_reset_default_submission(gt);
849 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
850 clear_bit(I915_WEDGED, >->reset.flags);
855 bool intel_gt_unset_wedged(struct intel_gt *gt)
859 mutex_lock(>->reset.mutex);
860 result = __intel_gt_unset_wedged(gt);
861 mutex_unlock(>->reset.mutex);
866 static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
872 err = __intel_gt_reset(gt, ALL_ENGINES);
873 for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
874 msleep(10 * (i + 1));
875 err = __intel_gt_reset(gt, ALL_ENGINES);
880 return gt_reset(gt, stalled_mask);
883 static int resume(struct intel_gt *gt)
885 struct intel_engine_cs *engine;
886 enum intel_engine_id id;
889 for_each_engine(engine, gt->i915, id) {
890 ret = engine->resume(engine);
899 * intel_gt_reset - reset chip after a hang
900 * @gt: #intel_gt to reset
901 * @stalled_mask: mask of the stalled engines with the guilty requests
902 * @reason: user error message for why we are resetting
904 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
907 * Procedure is fairly simple:
908 * - reset the chip using the reset reg
909 * - re-init context state
910 * - re-init hardware status page
911 * - re-init ring buffer
912 * - re-init interrupt state
915 void intel_gt_reset(struct intel_gt *gt,
916 intel_engine_mask_t stalled_mask,
919 intel_engine_mask_t awake;
922 GEM_TRACE("flags=%lx\n", gt->reset.flags);
925 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >->reset.flags));
926 mutex_lock(>->reset.mutex);
928 /* Clear any previous failed attempts at recovery. Time to try again. */
929 if (!__intel_gt_unset_wedged(gt))
933 dev_notice(gt->i915->drm.dev,
934 "Resetting chip for %s\n", reason);
935 atomic_inc(>->i915->gpu_error.reset_count);
937 awake = reset_prepare(gt);
939 if (!intel_has_gpu_reset(gt->i915)) {
940 if (i915_modparams.reset)
941 dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
943 DRM_DEBUG_DRIVER("GPU reset disabled\n");
947 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
948 intel_runtime_pm_disable_interrupts(gt->i915);
950 if (do_reset(gt, stalled_mask)) {
951 dev_err(gt->i915->drm.dev, "Failed to reset chip\n");
955 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
956 intel_runtime_pm_enable_interrupts(gt->i915);
958 intel_overlay_reset(gt->i915);
961 * Next we need to restore the context, but we don't use those
964 * Ring buffer needs to be re-initialized in the KMS case, or if X
965 * was running at the time of the reset (i.e. we weren't VT
968 ret = i915_gem_init_hw(gt->i915);
970 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
979 intel_gt_queue_hangcheck(gt);
982 reset_finish(gt, awake);
984 mutex_unlock(>->reset.mutex);
989 * History tells us that if we cannot reset the GPU now, we
990 * never will. This then impacts everything that is run
991 * subsequently. On failing the reset, we mark the driver
992 * as wedged, preventing further execution on the GPU.
993 * We also want to go one step further and add a taint to the
994 * kernel so that any subsequent faults can be traced back to
995 * this failure. This is important for CI, where if the
996 * GPU/driver fails we would like to reboot and restart testing
997 * rather than continue on into oblivion. For everyone else,
998 * the system should still plod along, but they have been warned!
1000 add_taint_for_CI(TAINT_WARN);
1002 __intel_gt_set_wedged(gt);
1006 static inline int intel_gt_reset_engine(struct intel_engine_cs *engine)
1008 return __intel_gt_reset(engine->gt, engine->mask);
1012 * intel_engine_reset - reset GPU engine to recover from a hang
1013 * @engine: engine to reset
1014 * @msg: reason for GPU reset; or NULL for no dev_notice()
1016 * Reset a specific GPU engine. Useful if a hang is detected.
1017 * Returns zero on successful reset or otherwise an error code.
1020 * - identifies the request that caused the hang and it is dropped
1021 * - reset engine (which will force the engine to idle)
1022 * - re-init/configure engine
1024 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1026 struct intel_gt *gt = engine->gt;
1029 GEM_TRACE("%s flags=%lx\n", engine->name, gt->reset.flags);
1030 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >->reset.flags));
1032 if (!intel_engine_pm_get_if_awake(engine))
1035 reset_prepare_engine(engine);
1038 dev_notice(engine->i915->drm.dev,
1039 "Resetting %s for %s\n", engine->name, msg);
1040 atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1042 if (!engine->gt->uc.guc.execbuf_client)
1043 ret = intel_gt_reset_engine(engine);
1045 ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
1047 /* If we fail here, we expect to fallback to a global reset */
1048 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
1049 engine->gt->uc.guc.execbuf_client ? "GuC " : "",
1055 * The request that caused the hang is stuck on elsp, we know the
1056 * active request and can drop it, adjust head to skip the offending
1057 * request to resume executing remaining requests in the queue.
1059 __intel_engine_reset(engine, true);
1062 * The engine and its registers (and workarounds in case of render)
1063 * have been reset to their default values. Follow the init_ring
1064 * process to program RING_MODE, HWSP and re-enable submission.
1066 ret = engine->resume(engine);
1069 intel_engine_cancel_stop_cs(engine);
1070 reset_finish_engine(engine);
1071 intel_engine_pm_put(engine);
1075 static void intel_gt_reset_global(struct intel_gt *gt,
1079 struct kobject *kobj = >->i915->drm.primary->kdev->kobj;
1080 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1081 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1082 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1083 struct intel_wedge_me w;
1085 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1087 DRM_DEBUG_DRIVER("resetting chip\n");
1088 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1090 /* Use a watchdog to ensure that our reset completes */
1091 intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1092 intel_prepare_reset(gt->i915);
1094 /* Flush everyone using a resource about to be clobbered */
1095 synchronize_srcu_expedited(>->reset.backoff_srcu);
1097 intel_gt_reset(gt, engine_mask, reason);
1099 intel_finish_reset(gt->i915);
1102 if (!test_bit(I915_WEDGED, >->reset.flags))
1103 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1107 * intel_gt_handle_error - handle a gpu error
1109 * @engine_mask: mask representing engines that are hung
1110 * @flags: control flags
1111 * @fmt: Error message format string
1113 * Do some basic checking of register state at error time and
1114 * dump it to the syslog. Also call i915_capture_error_state() to make
1115 * sure we get a record and make it available in debugfs. Fire a uevent
1116 * so userspace knows something bad happened (should trigger collection
1117 * of a ring dump etc.).
1119 void intel_gt_handle_error(struct intel_gt *gt,
1120 intel_engine_mask_t engine_mask,
1121 unsigned long flags,
1122 const char *fmt, ...)
1124 struct intel_engine_cs *engine;
1125 intel_wakeref_t wakeref;
1126 intel_engine_mask_t tmp;
1133 va_start(args, fmt);
1134 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1141 * In most cases it's guaranteed that we get here with an RPM
1142 * reference held, for example because there is a pending GPU
1143 * request that won't finish until the reset is done. This
1144 * isn't the case at least when we get here by doing a
1145 * simulated reset via debugfs, so get an RPM reference.
1147 wakeref = intel_runtime_pm_get(>->i915->runtime_pm);
1149 engine_mask &= INTEL_INFO(gt->i915)->engine_mask;
1151 if (flags & I915_ERROR_CAPTURE) {
1152 i915_capture_error_state(gt->i915, engine_mask, msg);
1153 intel_gt_clear_error_registers(gt, engine_mask);
1157 * Try engine reset when available. We fall back to full reset if
1158 * single reset fails.
1160 if (intel_has_reset_engine(gt->i915) && !intel_gt_is_wedged(gt)) {
1161 for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
1162 BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1163 if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1167 if (intel_engine_reset(engine, msg) == 0)
1168 engine_mask &= ~engine->mask;
1170 clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1178 /* Full reset needs the mutex, stop any other user trying to do so. */
1179 if (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1180 wait_event(gt->reset.queue,
1181 !test_bit(I915_RESET_BACKOFF, >->reset.flags));
1182 goto out; /* piggy-back on the other reset */
1185 /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1186 synchronize_rcu_expedited();
1188 /* Prevent any other reset-engine attempt. */
1189 for_each_engine(engine, gt->i915, tmp) {
1190 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1192 wait_on_bit(>->reset.flags,
1193 I915_RESET_ENGINE + engine->id,
1194 TASK_UNINTERRUPTIBLE);
1197 intel_gt_reset_global(gt, engine_mask, msg);
1199 for_each_engine(engine, gt->i915, tmp)
1200 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1202 clear_bit_unlock(I915_RESET_BACKOFF, >->reset.flags);
1203 smp_mb__after_atomic();
1204 wake_up_all(>->reset.queue);
1207 intel_runtime_pm_put(>->i915->runtime_pm, wakeref);
1210 int intel_gt_reset_trylock(struct intel_gt *gt)
1214 might_lock(>->reset.backoff_srcu);
1218 while (test_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1221 if (wait_event_interruptible(gt->reset.queue,
1222 !test_bit(I915_RESET_BACKOFF,
1228 srcu = srcu_read_lock(>->reset.backoff_srcu);
1234 void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1235 __releases(>->reset.backoff_srcu)
1237 srcu_read_unlock(>->reset.backoff_srcu, tag);
1240 int intel_gt_terminally_wedged(struct intel_gt *gt)
1244 if (!intel_gt_is_wedged(gt))
1247 /* Reset still in progress? Maybe we will recover? */
1248 if (!test_bit(I915_RESET_BACKOFF, >->reset.flags))
1251 /* XXX intel_reset_finish() still takes struct_mutex!!! */
1252 if (mutex_is_locked(>->i915->drm.struct_mutex))
1255 if (wait_event_interruptible(gt->reset.queue,
1256 !test_bit(I915_RESET_BACKOFF,
1260 return intel_gt_is_wedged(gt) ? -EIO : 0;
1263 void intel_gt_init_reset(struct intel_gt *gt)
1265 init_waitqueue_head(>->reset.queue);
1266 mutex_init(>->reset.mutex);
1267 init_srcu_struct(>->reset.backoff_srcu);
1270 void intel_gt_fini_reset(struct intel_gt *gt)
1272 cleanup_srcu_struct(>->reset.backoff_srcu);
1275 static void intel_wedge_me(struct work_struct *work)
1277 struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1279 dev_err(w->gt->i915->drm.dev,
1280 "%s timed out, cancelling all in-flight rendering.\n",
1282 intel_gt_set_wedged(w->gt);
1285 void __intel_init_wedge(struct intel_wedge_me *w,
1286 struct intel_gt *gt,
1293 INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1294 schedule_delayed_work(&w->work, timeout);
1297 void __intel_fini_wedge(struct intel_wedge_me *w)
1299 cancel_delayed_work_sync(&w->work);
1300 destroy_delayed_work_on_stack(&w->work);
1304 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1305 #include "selftest_reset.c"