2 * SPDX-License-Identifier: MIT
4 * Copyright © 2014-2018 Intel Corporation
8 #include "intel_context.h"
9 #include "intel_engine_pm.h"
11 #include "intel_ring.h"
12 #include "intel_workarounds.h"
15 * DOC: Hardware workarounds
17 * This file is intended as a central place to implement most [1]_ of the
18 * required workarounds for hardware to work as originally intended. They fall
19 * in five basic categories depending on how/when they are applied:
21 * - Workarounds that touch registers that are saved/restored to/from the HW
22 * context image. The list is emitted (via Load Register Immediate commands)
23 * everytime a new context is created.
24 * - GT workarounds. The list of these WAs is applied whenever these registers
25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..).
26 * - Display workarounds. The list is applied during display clock-gating
28 * - Workarounds that whitelist a privileged register, so that UMDs can manage
29 * them directly. This is just a special case of a MMMIO workaround (as we
30 * write the list of these to/be-whitelisted registers to some special HW
32 * - Workaround batchbuffers, that get executed automatically by the hardware
33 * on every HW context restore.
35 * .. [1] Please notice that there are other WAs that, due to their nature,
36 * cannot be applied from a central place. Those are peppered around the rest
37 * of the code, as needed.
39 * .. [2] Technically, some registers are powercontext saved & restored, so they
40 * survive a suspend/resume. In practice, writing them again is not too
41 * costly and simplifies things. We can revisit this in the future.
46 * Keep things in this file ordered by WA type, as per the above (context, GT,
47 * display, register whitelist, batchbuffer). Then, inside each type, keep the
50 * - Infrastructure functions and macros
51 * - WAs per platform in standard gen/chrono order
52 * - Public functions to init or apply the given workaround type.
55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
58 wal->engine_name = engine_name;
61 #define WA_LIST_CHUNK (1 << 4)
63 static void wa_init_finish(struct i915_wa_list *wal)
65 /* Trim unused entries. */
66 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
67 struct i915_wa *list = kmemdup(wal->list,
68 wal->count * sizeof(*list),
80 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n",
81 wal->wa_count, wal->name, wal->engine_name);
84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
86 unsigned int addr = i915_mmio_reg_offset(wa->reg);
87 unsigned int start = 0, end = wal->count;
88 const unsigned int grow = WA_LIST_CHUNK;
91 GEM_BUG_ON(!is_power_of_2(grow));
93 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
99 DRM_ERROR("No space for workaround init!\n");
104 memcpy(list, wal->list, sizeof(*wa) * wal->count);
109 while (start < end) {
110 unsigned int mid = start + (end - start) / 2;
112 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
114 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
117 wa_ = &wal->list[mid];
119 if ((wa->mask & ~wa_->mask) == 0) {
120 DRM_ERROR("Discarding overwritten w/a for reg %04x (mask: %08x, value: %08x)\n",
121 i915_mmio_reg_offset(wa_->reg),
122 wa_->mask, wa_->val);
124 wa_->val &= ~wa->mask;
129 wa_->mask |= wa->mask;
130 wa_->read |= wa->read;
136 wa_ = &wal->list[wal->count++];
139 while (wa_-- > wal->list) {
140 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
141 i915_mmio_reg_offset(wa_[1].reg));
142 if (i915_mmio_reg_offset(wa_[1].reg) >
143 i915_mmio_reg_offset(wa_[0].reg))
146 swap(wa_[1], wa_[0]);
150 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
151 u32 val, u32 read_mask)
153 struct i915_wa wa = {
164 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
167 wa_add(wal, reg, mask, val, mask);
171 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
173 wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
177 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
179 wa_write_masked_or(wal, reg, ~0, val);
183 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
185 wa_write_masked_or(wal, reg, val, val);
188 #define WA_SET_BIT_MASKED(addr, mask) \
189 wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
191 #define WA_CLR_BIT_MASKED(addr, mask) \
192 wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask))
194 #define WA_SET_FIELD_MASKED(addr, mask, value) \
195 wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value)))
197 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
198 struct i915_wa_list *wal)
200 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
202 /* WaDisableAsyncFlipPerfMode:bdw,chv */
203 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
205 /* WaDisablePartialInstShootdown:bdw,chv */
206 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
207 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
209 /* Use Force Non-Coherent whenever executing a 3D context. This is a
210 * workaround for for a possible hang in the unlikely event a TLB
211 * invalidation occurs during a PSD flush.
213 /* WaForceEnableNonCoherent:bdw,chv */
214 /* WaHdcDisableFetchWhenMasked:bdw,chv */
215 WA_SET_BIT_MASKED(HDC_CHICKEN0,
216 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
217 HDC_FORCE_NON_COHERENT);
219 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
220 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
221 * polygons in the same 8x4 pixel/sample area to be processed without
222 * stalling waiting for the earlier ones to write to Hierarchical Z
225 * This optimization is off by default for BDW and CHV; turn it on.
227 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
229 /* Wa4x4STCOptimizationDisable:bdw,chv */
230 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
233 * BSpec recommends 8x4 when MSAA is used,
234 * however in practice 16x4 seems fastest.
236 * Note that PS/WM thread counts depend on the WIZ hashing
237 * disable bit, which we don't touch here, but it's good
238 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
240 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
241 GEN6_WIZ_HASHING_MASK,
242 GEN6_WIZ_HASHING_16x4);
245 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
246 struct i915_wa_list *wal)
248 struct drm_i915_private *i915 = engine->i915;
250 gen8_ctx_workarounds_init(engine, wal);
252 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
253 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
255 /* WaDisableDopClockGating:bdw
257 * Also see the related UCGTCL1 write in bdw_init_clock_gating()
258 * to disable EUTC clock gating.
260 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
261 DOP_CLOCK_GATING_DISABLE);
263 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
264 GEN8_SAMPLER_POWER_BYPASS_DIS);
266 WA_SET_BIT_MASKED(HDC_CHICKEN0,
267 /* WaForceContextSaveRestoreNonCoherent:bdw */
268 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
269 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
270 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
273 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
274 struct i915_wa_list *wal)
276 gen8_ctx_workarounds_init(engine, wal);
278 /* WaDisableThreadStallDopClockGating:chv */
279 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
281 /* Improve HiZ throughput on CHV. */
282 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
285 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
286 struct i915_wa_list *wal)
288 struct drm_i915_private *i915 = engine->i915;
291 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
293 * Must match Display Engine. See
294 * WaCompressedResourceDisplayNewHashMode.
296 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
297 GEN9_PBE_COMPRESSED_HASH_SELECTION);
298 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
299 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
302 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
303 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
304 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
305 FLOW_CONTROL_ENABLE |
306 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
308 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
309 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
310 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
311 GEN9_ENABLE_YV12_BUGFIX |
312 GEN9_ENABLE_GPGPU_PREEMPTION);
314 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
315 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
316 WA_SET_BIT_MASKED(CACHE_MODE_1,
317 GEN8_4x4_STC_OPTIMIZATION_DISABLE |
318 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
320 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
321 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
322 GEN9_CCS_TLB_PREFETCH_ENABLE);
324 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
325 WA_SET_BIT_MASKED(HDC_CHICKEN0,
326 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
327 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
329 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
330 * both tied to WaForceContextSaveRestoreNonCoherent
331 * in some hsds for skl. We keep the tie for all gen9. The
332 * documentation is a bit hazy and so we want to get common behaviour,
333 * even though there is no clear evidence we would need both on kbl/bxt.
334 * This area has been source of system hangs so we play it safe
335 * and mimic the skl regardless of what bspec says.
337 * Use Force Non-Coherent whenever executing a 3D context. This
338 * is a workaround for a possible hang in the unlikely event
339 * a TLB invalidation occurs during a PSD flush.
342 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
343 WA_SET_BIT_MASKED(HDC_CHICKEN0,
344 HDC_FORCE_NON_COHERENT);
346 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
347 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915))
348 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
349 GEN8_SAMPLER_POWER_BYPASS_DIS);
351 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
352 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
355 * Supporting preemption with fine-granularity requires changes in the
356 * batch buffer programming. Since we can't break old userspace, we
357 * need to set our default preemption level to safe value. Userspace is
358 * still able to use more fine-grained preemption levels, since in
359 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
360 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
361 * not real HW workarounds, but merely a way to start using preemption
362 * while maintaining old contract with userspace.
365 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
366 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
368 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
369 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
370 GEN9_PREEMPT_GPGPU_LEVEL_MASK,
371 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
373 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
374 if (IS_GEN9_LP(i915))
375 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
378 static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
379 struct i915_wa_list *wal)
381 struct drm_i915_private *i915 = engine->i915;
382 u8 vals[3] = { 0, 0, 0 };
385 for (i = 0; i < 3; i++) {
389 * Only consider slices where one, and only one, subslice has 7
392 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
396 * subslice_7eu[i] != 0 (because of the check above) and
397 * ss_max == 4 (maximum number of subslices possible per slice)
401 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
405 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
408 /* Tune IZ hashing. See intel_device_info_runtime_init() */
409 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
410 GEN9_IZ_HASHING_MASK(2) |
411 GEN9_IZ_HASHING_MASK(1) |
412 GEN9_IZ_HASHING_MASK(0),
413 GEN9_IZ_HASHING(2, vals[2]) |
414 GEN9_IZ_HASHING(1, vals[1]) |
415 GEN9_IZ_HASHING(0, vals[0]));
418 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
419 struct i915_wa_list *wal)
421 gen9_ctx_workarounds_init(engine, wal);
422 skl_tune_iz_hashing(engine, wal);
425 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
426 struct i915_wa_list *wal)
428 gen9_ctx_workarounds_init(engine, wal);
430 /* WaDisableThreadStallDopClockGating:bxt */
431 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
432 STALL_DOP_GATING_DISABLE);
434 /* WaToEnableHwFixForPushConstHWBug:bxt */
435 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
436 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
439 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
440 struct i915_wa_list *wal)
442 struct drm_i915_private *i915 = engine->i915;
444 gen9_ctx_workarounds_init(engine, wal);
446 /* WaToEnableHwFixForPushConstHWBug:kbl */
447 if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER))
448 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
449 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
451 /* WaDisableSbeCacheDispatchPortSharing:kbl */
452 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
453 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
456 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
457 struct i915_wa_list *wal)
459 gen9_ctx_workarounds_init(engine, wal);
461 /* WaToEnableHwFixForPushConstHWBug:glk */
462 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
463 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
466 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
467 struct i915_wa_list *wal)
469 gen9_ctx_workarounds_init(engine, wal);
471 /* WaToEnableHwFixForPushConstHWBug:cfl */
472 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
473 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
475 /* WaDisableSbeCacheDispatchPortSharing:cfl */
476 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
477 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
480 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
481 struct i915_wa_list *wal)
483 struct drm_i915_private *i915 = engine->i915;
485 /* WaForceContextSaveRestoreNonCoherent:cnl */
486 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
487 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
489 /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
490 if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0))
491 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
493 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
494 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
495 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
497 /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
498 if (IS_CNL_REVID(i915, 0, CNL_REVID_B0))
499 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
500 GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
502 /* WaPushConstantDereferenceHoldDisable:cnl */
503 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
505 /* FtrEnableFastAnisoL1BankingFix:cnl */
506 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
508 /* WaDisable3DMidCmdPreemption:cnl */
509 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
511 /* WaDisableGPGPUMidCmdPreemption:cnl */
512 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
513 GEN9_PREEMPT_GPGPU_LEVEL_MASK,
514 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
516 /* WaDisableEarlyEOT:cnl */
517 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
520 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
521 struct i915_wa_list *wal)
523 struct drm_i915_private *i915 = engine->i915;
525 /* WaDisableBankHangMode:icl */
528 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
531 /* Wa_1604370585:icl (pre-prod)
532 * Formerly known as WaPushConstantDereferenceHoldDisable
534 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
535 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
536 PUSH_CONSTANT_DEREF_DISABLE);
538 /* WaForceEnableNonCoherent:icl
539 * This is not the same workaround as in early Gen9 platforms, where
540 * lacking this could cause system hangs, but coherency performance
541 * overhead is high and only a few compute workloads really need it
542 * (the register is whitelisted in hardware now, so UMDs can opt in
543 * for coherency if they have a good reason).
545 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
547 /* Wa_2006611047:icl (pre-prod)
548 * Formerly known as WaDisableImprovedTdlClkGating
550 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
551 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
552 GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
554 /* Wa_2006665173:icl (pre-prod) */
555 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
556 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
557 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
559 /* WaEnableFloatBlendOptimization:icl */
560 wa_write_masked_or(wal,
562 0, /* write-only, so skip validation */
563 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
565 /* WaDisableGPGPUMidThreadPreemption:icl */
566 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
567 GEN9_PREEMPT_GPGPU_LEVEL_MASK,
568 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
570 /* allow headerless messages for preemptible GPGPU context */
571 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
572 GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
575 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
576 struct i915_wa_list *wal)
578 /* Wa_1409142259:tgl */
579 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
580 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
583 * Wa_1604555607:gen12 and Wa_1608008084:gen12
584 * FF_MODE2 register will return the wrong value when read. The default
585 * value for this register is zero for all fields and there are no bit
586 * masks. So instead of doing a RMW we should just write the TDS timer
587 * value for Wa_1604555607.
589 wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
590 FF_MODE2_TDS_TIMER_128, 0);
594 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
595 struct i915_wa_list *wal,
598 struct drm_i915_private *i915 = engine->i915;
600 if (engine->class != RENDER_CLASS)
603 wa_init_start(wal, name, engine->name);
605 if (IS_GEN(i915, 12))
606 tgl_ctx_workarounds_init(engine, wal);
607 else if (IS_GEN(i915, 11))
608 icl_ctx_workarounds_init(engine, wal);
609 else if (IS_CANNONLAKE(i915))
610 cnl_ctx_workarounds_init(engine, wal);
611 else if (IS_COFFEELAKE(i915))
612 cfl_ctx_workarounds_init(engine, wal);
613 else if (IS_GEMINILAKE(i915))
614 glk_ctx_workarounds_init(engine, wal);
615 else if (IS_KABYLAKE(i915))
616 kbl_ctx_workarounds_init(engine, wal);
617 else if (IS_BROXTON(i915))
618 bxt_ctx_workarounds_init(engine, wal);
619 else if (IS_SKYLAKE(i915))
620 skl_ctx_workarounds_init(engine, wal);
621 else if (IS_CHERRYVIEW(i915))
622 chv_ctx_workarounds_init(engine, wal);
623 else if (IS_BROADWELL(i915))
624 bdw_ctx_workarounds_init(engine, wal);
625 else if (INTEL_GEN(i915) < 8)
628 MISSING_CASE(INTEL_GEN(i915));
633 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
635 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
638 int intel_engine_emit_ctx_wa(struct i915_request *rq)
640 struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
649 ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
653 cs = intel_ring_begin(rq, (wal->count * 2 + 2));
657 *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
658 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
659 *cs++ = i915_mmio_reg_offset(wa->reg);
664 intel_ring_advance(rq, cs);
666 ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
674 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
676 /* WaDisableKillLogic:bxt,skl,kbl */
677 if (!IS_COFFEELAKE(i915))
683 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
685 * Must match Display Engine. See
686 * WaCompressedResourceDisplayNewHashMode.
690 MMCD_PCLA | MMCD_HOTSPOT_EN);
693 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
696 BDW_DISABLE_HDC_INVALIDATION);
700 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
702 gen9_gt_workarounds_init(i915, wal);
704 /* WaDisableGafsUnitClkGating:skl */
707 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
709 /* WaInPlaceDecompressionHang:skl */
710 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
712 GEN9_GAMT_ECO_REG_RW_IA,
713 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
717 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
719 gen9_gt_workarounds_init(i915, wal);
721 /* WaInPlaceDecompressionHang:bxt */
723 GEN9_GAMT_ECO_REG_RW_IA,
724 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
728 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
730 gen9_gt_workarounds_init(i915, wal);
732 /* WaDisableDynamicCreditSharing:kbl */
733 if (IS_KBL_REVID(i915, 0, KBL_REVID_B0))
736 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
738 /* WaDisableGafsUnitClkGating:kbl */
741 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
743 /* WaInPlaceDecompressionHang:kbl */
745 GEN9_GAMT_ECO_REG_RW_IA,
746 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
750 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
752 gen9_gt_workarounds_init(i915, wal);
756 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
758 gen9_gt_workarounds_init(i915, wal);
760 /* WaDisableGafsUnitClkGating:cfl */
763 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
765 /* WaInPlaceDecompressionHang:cfl */
767 GEN9_GAMT_ECO_REG_RW_IA,
768 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
772 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
774 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
775 unsigned int slice, subslice;
776 u32 l3_en, mcr, mcr_mask;
778 GEM_BUG_ON(INTEL_GEN(i915) < 10);
781 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
782 * L3Banks could be fused off in single slice scenario. If that is
783 * the case, we might need to program MCR select to a valid L3Bank
784 * by default, to make sure we correctly read certain registers
785 * later on (in the range 0xB100 - 0xB3FF).
787 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
788 * Before any MMIO read into slice/subslice specific registers, MCR
789 * packet control register needs to be programmed to point to any
790 * enabled s/ss pair. Otherwise, incorrect values will be returned.
791 * This means each subsequent MMIO read will be forwarded to an
792 * specific s/ss combination, but this is OK since these registers
793 * are consistent across s/ss in almost all cases. In the rare
794 * occasions, such as INSTDONE, where this value is dependent
795 * on s/ss combo, the read should be done with read_subslice_reg.
797 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both
798 * to which subslice, or to which L3 bank, the respective mmio reads
799 * will go, we have to find a common index which works for both
802 * Case where we cannot find a common index fortunately should not
803 * happen in production hardware, so we only emit a warning instead of
804 * implementing something more complex that requires checking the range
805 * of every MMIO read.
808 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
810 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
813 DRM_DEBUG_DRIVER("L3 fuse = %x\n", l3_fuse);
814 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse);
819 slice = fls(sseu->slice_mask) - 1;
820 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
822 DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
823 intel_sseu_get_subslices(sseu, slice), l3_en);
824 subslice = fls(l3_en);
829 if (INTEL_GEN(i915) >= 11) {
830 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
831 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
833 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
834 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
837 DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
839 wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
843 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
845 wa_init_mcr(i915, wal);
847 /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
848 if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0))
851 GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
853 /* WaInPlaceDecompressionHang:cnl */
855 GEN9_GAMT_ECO_REG_RW_IA,
856 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
860 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
862 wa_init_mcr(i915, wal);
864 /* WaInPlaceDecompressionHang:icl */
866 GEN9_GAMT_ECO_REG_RW_IA,
867 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
869 /* WaModifyGamTlbPartitioning:icl */
870 wa_write_masked_or(wal,
871 GEN11_GACB_PERF_CTRL,
872 GEN11_HASH_CTRL_MASK,
873 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
876 * Formerly known as WaCL2SFHalfMaxAlloc
880 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
881 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
884 * Formerly known as WaDisCtxReload
887 GEN8_GAMW_ECO_DEV_RW_IA,
888 GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
890 /* Wa_1405779004:icl (pre-prod) */
891 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
893 SLICE_UNIT_LEVEL_CLKGATE,
894 MSCUNIT_CLKGATE_DIS);
896 /* Wa_1406680159:icl */
898 SUBSLICE_UNIT_LEVEL_CLKGATE,
901 /* Wa_1406838659:icl (pre-prod) */
902 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
904 INF_UNIT_LEVEL_CLKGATE,
908 * Formerly known as WaGamTlbPendError
912 GAMT_CHKN_DISABLE_L3_COH_PIPE);
914 /* Wa_1607087056:icl */
916 SLICE_UNIT_LEVEL_CLKGATE,
917 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
921 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
923 /* Wa_1409420604:tgl */
924 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
926 SUBSLICE_UNIT_LEVEL_CLKGATE2,
927 CPSSUNIT_CLKGATE_DIS);
929 /* Wa_1409180338:tgl */
930 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
932 SLICE_UNIT_LEVEL_CLKGATE,
933 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
937 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
939 if (IS_GEN(i915, 12))
940 tgl_gt_workarounds_init(i915, wal);
941 else if (IS_GEN(i915, 11))
942 icl_gt_workarounds_init(i915, wal);
943 else if (IS_CANNONLAKE(i915))
944 cnl_gt_workarounds_init(i915, wal);
945 else if (IS_COFFEELAKE(i915))
946 cfl_gt_workarounds_init(i915, wal);
947 else if (IS_GEMINILAKE(i915))
948 glk_gt_workarounds_init(i915, wal);
949 else if (IS_KABYLAKE(i915))
950 kbl_gt_workarounds_init(i915, wal);
951 else if (IS_BROXTON(i915))
952 bxt_gt_workarounds_init(i915, wal);
953 else if (IS_SKYLAKE(i915))
954 skl_gt_workarounds_init(i915, wal);
955 else if (INTEL_GEN(i915) <= 8)
958 MISSING_CASE(INTEL_GEN(i915));
961 void intel_gt_init_workarounds(struct drm_i915_private *i915)
963 struct i915_wa_list *wal = &i915->gt_wa_list;
965 wa_init_start(wal, "GT", "global");
966 gt_init_workarounds(i915, wal);
970 static enum forcewake_domains
971 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
973 enum forcewake_domains fw = 0;
977 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
978 fw |= intel_uncore_forcewake_for_reg(uncore,
987 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
989 if ((cur ^ wa->val) & wa->read) {
990 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x, mask=%x)\n",
991 name, from, i915_mmio_reg_offset(wa->reg),
1002 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1004 enum forcewake_domains fw;
1005 unsigned long flags;
1012 fw = wal_get_fw_for_rmw(uncore, wal);
1014 spin_lock_irqsave(&uncore->lock, flags);
1015 intel_uncore_forcewake_get__locked(uncore, fw);
1017 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1018 intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
1019 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1021 intel_uncore_read_fw(uncore, wa->reg),
1022 wal->name, "application");
1025 intel_uncore_forcewake_put__locked(uncore, fw);
1026 spin_unlock_irqrestore(&uncore->lock, flags);
1029 void intel_gt_apply_workarounds(struct intel_gt *gt)
1031 wa_list_apply(gt->uncore, >->i915->gt_wa_list);
1034 static bool wa_list_verify(struct intel_uncore *uncore,
1035 const struct i915_wa_list *wal,
1042 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1044 intel_uncore_read(uncore, wa->reg),
1050 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1052 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from);
1055 static inline bool is_nonpriv_flags_valid(u32 flags)
1057 /* Check only valid flag bits are set */
1058 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
1061 /* NB: Only 3 out of 4 enum values are valid for access field */
1062 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
1063 RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
1070 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1072 struct i915_wa wa = {
1076 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1079 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1082 wa.reg.reg |= flags;
1087 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1089 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1092 static void gen9_whitelist_build(struct i915_wa_list *w)
1094 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1095 whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
1097 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1098 whitelist_reg(w, GEN8_CS_CHICKEN1);
1100 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1101 whitelist_reg(w, GEN8_HDC_CHICKEN1);
1103 /* WaSendPushConstantsFromMMIO:skl,bxt */
1104 whitelist_reg(w, COMMON_SLICE_CHICKEN2);
1107 static void skl_whitelist_build(struct intel_engine_cs *engine)
1109 struct i915_wa_list *w = &engine->whitelist;
1111 if (engine->class != RENDER_CLASS)
1114 gen9_whitelist_build(w);
1116 /* WaDisableLSQCROPERFforOCL:skl */
1117 whitelist_reg(w, GEN8_L3SQCREG4);
1120 static void bxt_whitelist_build(struct intel_engine_cs *engine)
1122 if (engine->class != RENDER_CLASS)
1125 gen9_whitelist_build(&engine->whitelist);
1128 static void kbl_whitelist_build(struct intel_engine_cs *engine)
1130 struct i915_wa_list *w = &engine->whitelist;
1132 if (engine->class != RENDER_CLASS)
1135 gen9_whitelist_build(w);
1137 /* WaDisableLSQCROPERFforOCL:kbl */
1138 whitelist_reg(w, GEN8_L3SQCREG4);
1141 static void glk_whitelist_build(struct intel_engine_cs *engine)
1143 struct i915_wa_list *w = &engine->whitelist;
1145 if (engine->class != RENDER_CLASS)
1148 gen9_whitelist_build(w);
1150 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
1151 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1154 static void cfl_whitelist_build(struct intel_engine_cs *engine)
1156 struct i915_wa_list *w = &engine->whitelist;
1158 if (engine->class != RENDER_CLASS)
1161 gen9_whitelist_build(w);
1164 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
1166 * This covers 4 register which are next to one another :
1167 * - PS_INVOCATION_COUNT
1168 * - PS_INVOCATION_COUNT_UDW
1170 * - PS_DEPTH_COUNT_UDW
1172 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1173 RING_FORCE_TO_NONPRIV_ACCESS_RD |
1174 RING_FORCE_TO_NONPRIV_RANGE_4);
1177 static void cnl_whitelist_build(struct intel_engine_cs *engine)
1179 struct i915_wa_list *w = &engine->whitelist;
1181 if (engine->class != RENDER_CLASS)
1184 /* WaEnablePreemptionGranularityControlByUMD:cnl */
1185 whitelist_reg(w, GEN8_CS_CHICKEN1);
1188 static void icl_whitelist_build(struct intel_engine_cs *engine)
1190 struct i915_wa_list *w = &engine->whitelist;
1192 switch (engine->class) {
1194 /* WaAllowUMDToModifyHalfSliceChicken7:icl */
1195 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
1197 /* WaAllowUMDToModifySamplerMode:icl */
1198 whitelist_reg(w, GEN10_SAMPLER_MODE);
1200 /* WaEnableStateCacheRedirectToCS:icl */
1201 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1204 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
1206 * This covers 4 register which are next to one another :
1207 * - PS_INVOCATION_COUNT
1208 * - PS_INVOCATION_COUNT_UDW
1210 * - PS_DEPTH_COUNT_UDW
1212 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1213 RING_FORCE_TO_NONPRIV_ACCESS_RD |
1214 RING_FORCE_TO_NONPRIV_RANGE_4);
1217 case VIDEO_DECODE_CLASS:
1218 /* hucStatusRegOffset */
1219 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
1220 RING_FORCE_TO_NONPRIV_ACCESS_RD);
1221 /* hucUKernelHdrInfoRegOffset */
1222 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
1223 RING_FORCE_TO_NONPRIV_ACCESS_RD);
1224 /* hucStatus2RegOffset */
1225 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
1226 RING_FORCE_TO_NONPRIV_ACCESS_RD);
1234 static void tgl_whitelist_build(struct intel_engine_cs *engine)
1236 struct i915_wa_list *w = &engine->whitelist;
1238 switch (engine->class) {
1241 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
1243 * This covers 4 registers which are next to one another :
1244 * - PS_INVOCATION_COUNT
1245 * - PS_INVOCATION_COUNT_UDW
1247 * - PS_DEPTH_COUNT_UDW
1249 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1250 RING_FORCE_TO_NONPRIV_ACCESS_RD |
1251 RING_FORCE_TO_NONPRIV_RANGE_4);
1258 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
1260 struct drm_i915_private *i915 = engine->i915;
1261 struct i915_wa_list *w = &engine->whitelist;
1263 wa_init_start(w, "whitelist", engine->name);
1265 if (IS_GEN(i915, 12))
1266 tgl_whitelist_build(engine);
1267 else if (IS_GEN(i915, 11))
1268 icl_whitelist_build(engine);
1269 else if (IS_CANNONLAKE(i915))
1270 cnl_whitelist_build(engine);
1271 else if (IS_COFFEELAKE(i915))
1272 cfl_whitelist_build(engine);
1273 else if (IS_GEMINILAKE(i915))
1274 glk_whitelist_build(engine);
1275 else if (IS_KABYLAKE(i915))
1276 kbl_whitelist_build(engine);
1277 else if (IS_BROXTON(i915))
1278 bxt_whitelist_build(engine);
1279 else if (IS_SKYLAKE(i915))
1280 skl_whitelist_build(engine);
1281 else if (INTEL_GEN(i915) <= 8)
1284 MISSING_CASE(INTEL_GEN(i915));
1289 void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
1291 const struct i915_wa_list *wal = &engine->whitelist;
1292 struct intel_uncore *uncore = engine->uncore;
1293 const u32 base = engine->mmio_base;
1300 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1301 intel_uncore_write(uncore,
1302 RING_FORCE_TO_NONPRIV(base, i),
1303 i915_mmio_reg_offset(wa->reg));
1305 /* And clear the rest just in case of garbage */
1306 for (; i < RING_MAX_NONPRIV_SLOTS; i++)
1307 intel_uncore_write(uncore,
1308 RING_FORCE_TO_NONPRIV(base, i),
1309 i915_mmio_reg_offset(RING_NOPID(base)));
1313 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1315 struct drm_i915_private *i915 = engine->i915;
1317 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
1318 /* Wa_1606700617:tgl */
1320 GEN9_CS_DEBUG_MODE1,
1321 FF_DOP_CLOCK_GATE_DISABLE);
1323 /* Wa_1607138336:tgl */
1325 GEN9_CTX_PREEMPT_REG,
1326 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
1328 /* Wa_1607030317:tgl */
1329 /* Wa_1607186500:tgl */
1330 /* Wa_1607297627:tgl */
1332 GEN6_RC_SLEEP_PSMI_CONTROL,
1333 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
1334 GEN8_RC_SEMA_IDLE_MSG_DISABLE);
1338 * (see also Wa_1606682166:icl)
1342 GEN7_DISABLE_SAMPLER_PREFETCH);
1345 if (IS_GEN(i915, 11)) {
1346 /* This is not an Wa. Enable for better image quality */
1349 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
1351 /* WaPipelineFlushCoherentLines:icl */
1354 GEN8_LQSC_FLUSH_COHERENT_LINES);
1358 * Formerly known as WaGAPZPriorityScheme
1362 GEN11_ARBITRATION_PRIO_ORDER_MASK);
1366 * Formerly known as WaL3BankAddressHashing
1368 wa_write_masked_or(wal,
1370 GEN11_HASH_CTRL_EXCL_MASK,
1371 GEN11_HASH_CTRL_EXCL_BIT0);
1372 wa_write_masked_or(wal,
1374 GEN11_BANK_HASH_ADDR_EXCL_MASK,
1375 GEN11_BANK_HASH_ADDR_EXCL_BIT0);
1379 * Formerly known as WaDisableCleanEvicts
1383 GEN11_LQSC_CLEAN_EVICT_DISABLE);
1385 /* WaForwardProgressSoftReset:icl */
1387 GEN10_SCRATCH_LNCF2,
1388 PMFLUSHDONE_LNICRSDROP |
1389 PMFLUSH_GAPL3UNBLOCK |
1390 PMFLUSHDONE_LNEBLK);
1392 /* Wa_1406609255:icl (pre-prod) */
1393 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
1396 GEN7_DISABLE_DEMAND_PREFETCH);
1398 /* Wa_1606682166:icl */
1401 GEN7_DISABLE_SAMPLER_PREFETCH);
1403 /* Wa_1409178092:icl */
1404 wa_write_masked_or(wal,
1406 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
1410 if (IS_GEN_RANGE(i915, 9, 11)) {
1411 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
1413 GEN7_FF_SLICE_CS_CHICKEN1,
1414 GEN9_FFSC_PERCTX_PREEMPT_CTRL);
1417 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
1418 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
1421 GEN9_GAPS_TSV_CREDIT_DISABLE);
1424 if (IS_BROXTON(i915)) {
1425 /* WaDisablePooledEuLoadBalancingFix:bxt */
1427 FF_SLICE_CS_CHICKEN2,
1428 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1431 if (IS_GEN(i915, 9)) {
1432 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
1434 GEN9_CSFE_CHICKEN1_RCS,
1435 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
1437 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
1440 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
1442 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
1443 if (IS_GEN9_LP(i915))
1444 wa_write_masked_or(wal,
1446 L3_PRIO_CREDITS_MASK,
1447 L3_GENERAL_PRIO_CREDITS(62) |
1448 L3_HIGH_PRIO_CREDITS(2));
1450 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
1453 GEN8_LQSC_FLUSH_COHERENT_LINES);
1458 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1460 struct drm_i915_private *i915 = engine->i915;
1462 /* WaKBLVECSSemaphoreWaitPoll:kbl */
1463 if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
1465 RING_SEMA_WAIT_POLL(engine->mmio_base),
1471 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1473 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
1476 if (engine->class == RENDER_CLASS)
1477 rcs_engine_wa_init(engine, wal);
1479 xcs_engine_wa_init(engine, wal);
1482 void intel_engine_init_workarounds(struct intel_engine_cs *engine)
1484 struct i915_wa_list *wal = &engine->wa_list;
1486 if (INTEL_GEN(engine->i915) < 8)
1489 wa_init_start(wal, "engine", engine->name);
1490 engine_init_workarounds(engine, wal);
1491 wa_init_finish(wal);
1494 void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
1496 wa_list_apply(engine->uncore, &engine->wa_list);
1499 static struct i915_vma *
1500 create_scratch(struct i915_address_space *vm, int count)
1502 struct drm_i915_gem_object *obj;
1503 struct i915_vma *vma;
1507 size = round_up(count * sizeof(u32), PAGE_SIZE);
1508 obj = i915_gem_object_create_internal(vm->i915, size);
1510 return ERR_CAST(obj);
1512 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1514 vma = i915_vma_instance(obj, vm, NULL);
1520 err = i915_vma_pin(vma, 0, 0,
1521 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
1528 i915_gem_object_put(obj);
1529 return ERR_PTR(err);
1532 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
1535 * Registers in this range are affected by the MCR selector
1536 * which only controls CPU initiated MMIO. Routing does not
1537 * work for CS access so we cannot verify them on this path.
1539 if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
1546 wa_list_srm(struct i915_request *rq,
1547 const struct i915_wa_list *wal,
1548 struct i915_vma *vma)
1550 struct drm_i915_private *i915 = rq->i915;
1551 unsigned int i, count = 0;
1552 const struct i915_wa *wa;
1555 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1556 if (INTEL_GEN(i915) >= 8)
1559 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1560 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
1564 cs = intel_ring_begin(rq, 4 * count);
1568 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1569 u32 offset = i915_mmio_reg_offset(wa->reg);
1571 if (mcr_range(i915, offset))
1576 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
1579 intel_ring_advance(rq, cs);
1584 static int engine_wa_list_verify(struct intel_context *ce,
1585 const struct i915_wa_list * const wal,
1588 const struct i915_wa *wa;
1589 struct i915_request *rq;
1590 struct i915_vma *vma;
1598 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
1600 return PTR_ERR(vma);
1602 intel_engine_pm_get(ce->engine);
1603 rq = intel_context_create_request(ce);
1604 intel_engine_pm_put(ce->engine);
1610 err = wa_list_srm(rq, wal, vma);
1614 i915_request_get(rq);
1615 i915_request_add(rq);
1616 if (i915_request_wait(rq, 0, HZ / 5) < 0) {
1621 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1622 if (IS_ERR(results)) {
1623 err = PTR_ERR(results);
1628 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1629 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
1632 if (!wa_verify(wa, results[i], wal->name, from))
1636 i915_gem_object_unpin_map(vma->obj);
1639 i915_request_put(rq);
1641 i915_vma_unpin(vma);
1646 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
1649 return engine_wa_list_verify(engine->kernel_context,
1654 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1655 #include "selftest_workarounds.c"