drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2016-2019 Intel Corporation
   4  */
   5
   6 #ifndef _INTEL_GUC_CT_H_
   7 #define _INTEL_GUC_CT_H_
   8
   9 #include <linux/spinlock.h>
  10 #include <linux/workqueue.h>
  11
  12 #include "intel_guc_fwif.h"
  13
  14 struct i915_vma;
  15 struct intel_guc;
  16
  17 /**
  18  * DOC: Command Transport (CT).
  19  *
  20  * Buffer based command transport is a replacement for MMIO based mechanism.
  21  * It can be used to perform both host-2-guc and guc-to-host communication.
  22  */
  23
  24 /** Represents single command transport buffer.
  25  *
  26  * A single command transport buffer consists of two parts, the header
  27  * record (command transport buffer descriptor) and the actual buffer which
  28  * holds the commands.
  29  *
  30  * @desc: pointer to the buffer descriptor
  31  * @cmds: pointer to the commands buffer
  32  */
  33 struct intel_guc_ct_buffer {
  34         struct guc_ct_buffer_desc *desc;
  35         u32 *cmds;
  36 };
  37
  38 /** Represents pair of command transport buffers.
  39  *
  40  * Buffers go in pairs to allow bi-directional communication.
  41  * To simplify the code we place both of them in the same vma.
  42  * Buffers from the same pair must share unique owner id.
  43  *
  44  * @vma: pointer to the vma with pair of CT buffers
  45  * @ctbs: buffers for sending(0) and receiving(1) commands
  46  * @owner: unique identifier
  47  * @next_fence: fence to be used with next send command
  48  */
  49 struct intel_guc_ct_channel {
  50         struct i915_vma *vma;
  51         struct intel_guc_ct_buffer ctbs[2];
  52         u32 owner;
  53         u32 next_fence;
  54         bool enabled;
  55 };
  56
  57 /** Holds all command transport channels.
  58  *
  59  * @host_channel: main channel used by the host
  60  */
  61 struct intel_guc_ct {
  62         struct intel_guc_ct_channel host_channel;
  63         /* other channels are tbd */
  64
  65         /** @lock: protects pending requests list */
  66         spinlock_t lock;
  67
  68         /** @pending_requests: list of requests waiting for response */
  69         struct list_head pending_requests;
  70
  71         /** @incoming_requests: list of incoming requests */
  72         struct list_head incoming_requests;
  73
  74         /** @worker: worker for handling incoming requests */
  75         struct work_struct worker;
  76 };
  77
  78 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
  79 int intel_guc_ct_init(struct intel_guc_ct *ct);
  80 void intel_guc_ct_fini(struct intel_guc_ct *ct);
  81 int intel_guc_ct_enable(struct intel_guc_ct *ct);
  82 void intel_guc_ct_disable(struct intel_guc_ct *ct);
  83
  84 static inline void intel_guc_ct_stop(struct intel_guc_ct *ct)
  85 {
  86         ct->host_channel.enabled = false;
  87 }
  88
  89 int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
  90                       u32 *response_buf, u32 response_buf_size);
  91 void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
  92
  93 #endif /* _INTEL_GUC_CT_H_ */