2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #ifndef _INTEL_GUC_FWIF_H
24 #define _INTEL_GUC_FWIF_H
26 #include <linux/bits.h>
27 #include <linux/compiler.h>
28 #include <linux/types.h>
30 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0
31 #define GUC_CLIENT_PRIORITY_HIGH 1
32 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
33 #define GUC_CLIENT_PRIORITY_NORMAL 3
34 #define GUC_CLIENT_PRIORITY_NUM 4
36 #define GUC_MAX_STAGE_DESCRIPTORS 1024
37 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS
39 #define GUC_RENDER_ENGINE 0
40 #define GUC_VIDEO_ENGINE 1
41 #define GUC_BLITTER_ENGINE 2
42 #define GUC_VIDEOENHANCE_ENGINE 3
43 #define GUC_VIDEO_ENGINE2 4
44 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
46 #define GUC_MAX_ENGINE_CLASSES 5
47 #define GUC_MAX_INSTANCES_PER_CLASS 16
49 #define GUC_DOORBELL_INVALID 256
51 #define GUC_DB_SIZE (PAGE_SIZE)
52 #define GUC_WQ_SIZE (PAGE_SIZE * 2)
54 /* Work queue item header definitions */
55 #define WQ_STATUS_ACTIVE 1
56 #define WQ_STATUS_SUSPENDED 2
57 #define WQ_STATUS_CMD_ERROR 3
58 #define WQ_STATUS_ENGINE_ID_NOT_USED 4
59 #define WQ_STATUS_SUSPENDED_FROM_RESET 5
60 #define WQ_TYPE_SHIFT 0
61 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
62 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
63 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
64 #define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
65 #define WQ_TARGET_SHIFT 10
66 #define WQ_LEN_SHIFT 16
67 #define WQ_NO_WCFLUSH_WAIT (1 << 27)
68 #define WQ_PRESENT_WORKLOAD (1 << 28)
70 #define WQ_RING_TAIL_SHIFT 20
71 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */
72 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
74 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
75 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
76 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
77 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
78 #define GUC_STAGE_DESC_ATTR_RESET BIT(4)
79 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
80 #define GUC_STAGE_DESC_ATTR_PCH BIT(6)
81 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
83 /* New GuC control data */
84 #define GUC_CTL_CTXINFO 0
85 #define GUC_CTL_CTXNUM_IN16_SHIFT 0
86 #define GUC_CTL_BASE_ADDR_SHIFT 12
88 #define GUC_CTL_LOG_PARAMS 1
89 #define GUC_LOG_VALID (1 << 0)
90 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
91 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
92 #define GUC_LOG_CRASH_SHIFT 4
93 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
94 #define GUC_LOG_DPC_SHIFT 6
95 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
96 #define GUC_LOG_ISR_SHIFT 9
97 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
98 #define GUC_LOG_BUF_ADDR_SHIFT 12
101 #define GUC_CTL_FEATURE 3
102 #define GUC_CTL_DISABLE_SCHEDULER (1 << 14)
104 #define GUC_CTL_DEBUG 4
105 #define GUC_LOG_VERBOSITY_SHIFT 0
106 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
107 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
108 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
109 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
110 /* Verbosity range-check limits, without the shift */
111 #define GUC_LOG_VERBOSITY_MIN 0
112 #define GUC_LOG_VERBOSITY_MAX 3
113 #define GUC_LOG_VERBOSITY_MASK 0x0000000f
114 #define GUC_LOG_DESTINATION_MASK (3 << 4)
115 #define GUC_LOG_DISABLED (1 << 6)
116 #define GUC_PROFILE_ENABLED (1 << 7)
118 #define GUC_CTL_ADS 5
119 #define GUC_ADS_ADDR_SHIFT 1
120 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
122 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
125 * DOC: GuC Firmware Layout
127 * The GuC firmware layout looks like this:
129 * +-------------------------------+
132 * | contains major/minor version |
133 * +-------------------------------+
135 * +-------------------------------+
137 * +-------------------------------+
139 * +-------------------------------+
141 * +-------------------------------+
143 * The firmware may or may not have modulus key and exponent data. The header,
144 * uCode and RSA signature are must-have components that will be used by driver.
145 * Length of each components, which is all in dwords, can be found in header.
146 * In the case that modulus and exponent are not present in fw, a.k.a truncated
147 * image, the length value still appears in header.
149 * Driver will do some basic fw size validation based on the following rules:
151 * 1. Header, uCode and RSA are must-have components.
152 * 2. All firmware components, if they present, are in the sequence illustrated
153 * in the layout table above.
154 * 3. Length info of each component can be found in header, in dwords.
155 * 4. Modulus and exponent key are not required by driver. They may not appear
156 * in fw. So driver will load a truncated firmware in this case.
158 * HuC firmware layout is same as GuC firmware.
159 * Only HuC version information is saved in a different way.
162 struct uc_css_header {
164 /* header_size includes all non-uCode bits, including css_header, rsa
165 * key, modulus key and exponent data. */
171 #define CSS_DATE_DAY (0xFF << 0)
172 #define CSS_DATE_MONTH (0xFF << 8)
173 #define CSS_DATE_YEAR (0xFFFF << 16)
174 u32 size_dw; /* uCode plus header_size_dw */
177 u32 exponent_size_dw;
179 #define CSS_TIME_HOUR (0xFF << 0)
180 #define CSS_DATE_MIN (0xFF << 8)
181 #define CSS_DATE_SEC (0xFFFF << 16)
183 char buildnumber[12];
185 #define CSS_SW_VERSION_GUC_MAJOR (0xFF << 16)
186 #define CSS_SW_VERSION_GUC_MINOR (0xFF << 8)
187 #define CSS_SW_VERSION_GUC_PATCH (0xFF << 0)
188 #define CSS_SW_VERSION_HUC_MAJOR (0xFFFF << 16)
189 #define CSS_SW_VERSION_HUC_MINOR (0xFFFF << 0)
194 /* Work item for submitting workloads into work queue of GuC. */
198 u32 submit_element_info;
202 struct guc_process_desc {
216 /* engine id and context id is packed into guc_execlist_context.context_id*/
217 #define GUC_ELC_CTXID_OFFSET 0
218 #define GUC_ELC_ENGINE_OFFSET 29
220 /* The execlist context including software and HW information */
221 struct guc_execlist_context {
228 u32 ring_next_free_location;
229 u32 ring_current_tail_pointer_value;
230 u8 engine_state_submit_value;
231 u8 engine_state_wait_value;
233 u16 engine_submit_queue_count;
237 * This structure describes a stage set arranged for a particular communication
238 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a
239 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor"
240 * to avoid confusion with all the other things already named "context" in the
241 * driver. A static pool of these descriptors are stored inside a GEM object
242 * (stage_desc_pool) which is held for the entire lifetime of our interaction
243 * with the GuC, being allocated before the GuC is loaded with its firmware.
245 struct guc_stage_desc {
246 u32 sched_common_area;
255 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
261 u32 wq_sampled_tail_offset;
262 u32 wq_total_submit_enqueues;
279 * DOC: CTB based communication
281 * The CTB (command transport buffer) communication between Host and GuC
282 * is based on u32 data stream written to the shared buffer. One buffer can
283 * be used to transmit data only in one direction (one-directional channel).
285 * Current status of the each buffer is stored in the buffer descriptor.
286 * Buffer descriptor holds tail and head fields that represents active data
287 * stream. The tail field is updated by the data producer (sender), and head
288 * field is updated by the data consumer (receiver)::
291 * | DESCRIPTOR | +=================+============+========+
292 * +============+ | | MESSAGE(s) | |
293 * | address |--------->+=================+============+========+
295 * | head | ^-----head--------^
297 * | tail | ^---------tail-----------------^
299 * | size | ^---------------size--------------------^
302 * Each message in data stream starts with the single u32 treated as a header,
303 * followed by optional set of u32 data that makes message specific payload::
305 * +------------+---------+---------+---------+
307 * +------------+---------+---------+---------+
308 * | msg[0] | [1] | ... | [n-1] |
309 * +------------+---------+---------+---------+
310 * | MESSAGE | MESSAGE PAYLOAD |
311 * + HEADER +---------+---------+---------+
313 * +======+=====+=========+=========+=========+
314 * | 31:16| code| | | |
315 * +------+-----+ | | |
316 * | 15:5|flags| | | |
317 * +------+-----+ | | |
319 * +------+-----+---------+---------+---------+
321 * ^-------------len-------------^
323 * The message header consists of:
325 * - **len**, indicates length of the message payload (in u32)
326 * - **code**, indicates message code
327 * - **flags**, holds various bits to control message handling
331 * Describes single command transport buffer.
332 * Used by both guc-master and clients.
334 struct guc_ct_buffer_desc {
335 u32 addr; /* gfx address */
336 u64 host_private; /* host private data */
337 u32 size; /* size in bytes */
338 u32 head; /* offset updated by GuC*/
339 u32 tail; /* offset updated by owner */
340 u32 is_in_error; /* error indicator */
341 u32 fence; /* fence updated by GuC */
342 u32 status; /* status updated by GuC */
343 u32 owner; /* id of the channel owner */
344 u32 owner_sub_id; /* owner-defined field for extra tracking */
348 /* Type of command transport buffer */
349 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
350 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u
353 * Definition of the command transport message header (DW0)
355 * bit[4..0] message len (in dwords)
357 * bit[8] response (G2H only)
358 * bit[8] write fence to desc (H2G only)
359 * bit[9] write status to H2G buff (H2G only)
360 * bit[10] send status back via G2H (H2G only)
361 * bit[15..11] reserved
362 * bit[31..16] action code
364 #define GUC_CT_MSG_LEN_SHIFT 0
365 #define GUC_CT_MSG_LEN_MASK 0x1F
366 #define GUC_CT_MSG_IS_RESPONSE (1 << 8)
367 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
368 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
369 #define GUC_CT_MSG_SEND_STATUS (1 << 10)
370 #define GUC_CT_MSG_ACTION_SHIFT 16
371 #define GUC_CT_MSG_ACTION_MASK 0xFFFF
373 #define GUC_FORCEWAKE_RENDER (1 << 0)
374 #define GUC_FORCEWAKE_MEDIA (1 << 1)
376 #define GUC_POWER_UNSPECIFIED 0
377 #define GUC_POWER_D0 1
378 #define GUC_POWER_D1 2
379 #define GUC_POWER_D2 3
380 #define GUC_POWER_D3 4
382 /* Scheduling policy settings */
384 /* Reset engine upon preempt failure */
385 #define POLICY_RESET_ENGINE (1<<0)
386 /* Preempt to idle on quantum expiry */
387 #define POLICY_PREEMPT_TO_IDLE (1<<1)
389 #define POLICY_MAX_NUM_WI 15
390 #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
391 #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
392 #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
393 #define POLICY_DEFAULT_FAULT_TIME_US 250000
396 /* Time for one workload to execute. (in micro seconds) */
397 u32 execution_quantum;
398 /* Time to wait for a preemption request to completed before issuing a
399 * reset. (in micro seconds). */
401 /* How much time to allow to run after the first fault is observed.
402 * Then preempt afterwards. (in micro seconds) */
408 struct guc_policies {
409 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
410 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
411 /* In micro seconds. How much time to allow before DPC processing is
412 * called back via interrupt (to prevent DPC queue drain starving).
413 * Typically 1000s of micro seconds (example only, not granularity). */
414 u32 dpc_promote_time;
416 /* Must be set to take these new values. */
419 /* Max number of WIs to process per call. A large value may keep CS
421 u32 max_num_work_items;
426 /* GuC MMIO reg state struct */
429 #define GUC_REGSET_MAX_REGISTERS 64
430 #define GUC_S3_SAVE_SPACE_PAGES 10
432 struct guc_mmio_reg {
436 #define GUC_REGSET_MASKED (1 << 0)
439 struct guc_mmio_regset {
440 struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS];
442 u32 number_of_registers;
445 /* GuC register sets */
446 struct guc_mmio_reg_state {
447 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
452 struct guc_gt_system_info {
457 u32 vdbox_enable_mask;
458 u32 vdbox_sfc_support_mask;
459 u32 vebox_enable_mask;
464 struct guc_ct_pool_entry {
465 struct guc_ct_buffer_desc desc;
469 #define GUC_CT_POOL_SIZE 2
471 struct guc_clients_info {
479 /* GuC Additional Data Struct */
482 u32 reg_state_buffer;
483 u32 scheduler_policies;
487 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
488 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
492 /* GuC logging structures */
494 enum guc_log_buffer_type {
497 GUC_CRASH_DUMP_LOG_BUFFER,
502 * struct guc_log_buffer_state - GuC log buffer state
504 * Below state structure is used for coordination of retrieval of GuC firmware
505 * logs. Separate state is maintained for each log buffer type.
506 * read_ptr points to the location where i915 read last in log buffer and
507 * is read only for GuC firmware. write_ptr is incremented by GuC with number
508 * of bytes written for each log entry and is read only for i915.
509 * When any type of log buffer becomes half full, GuC sends a flush interrupt.
510 * GuC firmware expects that while it is writing to 2nd half of the buffer,
511 * first half would get consumed by Host and then get a flush completed
512 * acknowledgment from Host, so that it does not end up doing any overwrite
513 * causing loss of logs. So when buffer gets half filled & i915 has requested
514 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
515 * to the value of write_ptr and raise the interrupt.
516 * On receiving the interrupt i915 should read the buffer, clear flush_to_file
517 * field and also update read_ptr with the value of sample_write_ptr, before
518 * sending an acknowledgment to GuC. marker & version fields are for internal
519 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
520 * time GuC detects the log buffer overflow.
522 struct guc_log_buffer_state {
527 u32 sampled_write_ptr;
531 u32 buffer_full_cnt:4;
539 struct guc_ctx_report {
540 u32 report_return_status;
546 /* GuC Shared Context Data Struct */
547 struct guc_shared_ctx_data {
548 u32 addr_of_last_preempted_data_low;
549 u32 addr_of_last_preempted_data_high;
550 u32 addr_of_last_preempted_data_high_tmp;
552 u32 is_mapped_to_proxy;
554 u32 engine_reset_ctx_id;
555 u32 media_reset_count;
557 u32 uk_last_ctx_switch_reason;
562 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
566 * DOC: MMIO based communication
568 * The MMIO based communication between Host and GuC uses software scratch
569 * registers, where first register holds data treated as message header,
570 * and other registers are used to hold message payload.
572 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,
573 * but no H2G command takes more than 8 parameters and the GuC FW
574 * itself uses an 8-element array to store the H2G message.
576 * +-----------+---------+---------+---------+
577 * | MMIO[0] | MMIO[1] | ... | MMIO[n] |
578 * +-----------+---------+---------+---------+
579 * | header | optional payload |
580 * +======+====+=========+=========+=========+
581 * | 31:28|type| | | |
582 * +------+----+ | | |
583 * | 27:16|data| | | |
584 * +------+----+ | | |
586 * +------+----+---------+---------+---------+
588 * The message header consists of:
590 * - **type**, indicates message type
591 * - **code**, indicates message code, is specific for **type**
592 * - **data**, indicates message data, optional, depends on **code**
594 * The following message **types** are supported:
596 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
597 * must be priovided in **code** field. Optional action specific parameters
598 * can be provided in remaining payload registers or **data** field.
600 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
601 * action response status will be provided in **code** field. Optional
602 * response data can be returned in remaining payload registers or **data**
606 #define GUC_MAX_MMIO_MSG_LEN 8
608 #define INTEL_GUC_MSG_TYPE_SHIFT 28
609 #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
610 #define INTEL_GUC_MSG_DATA_SHIFT 16
611 #define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
612 #define INTEL_GUC_MSG_CODE_SHIFT 0
613 #define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
615 #define __INTEL_GUC_MSG_GET(T, m) \
616 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
617 #define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m)
618 #define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m)
619 #define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m)
621 enum intel_guc_msg_type {
622 INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
623 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
626 #define __INTEL_GUC_MSG_TYPE_IS(T, m) \
627 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
628 #define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
629 #define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
631 enum intel_guc_action {
632 INTEL_GUC_ACTION_DEFAULT = 0x0,
633 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
634 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
635 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
636 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
637 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
638 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
639 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
640 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
641 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
642 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
643 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
644 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
645 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
646 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
647 INTEL_GUC_ACTION_LIMIT
650 enum intel_guc_preempt_options {
651 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
652 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
655 enum intel_guc_report_status {
656 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
657 INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
658 INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
659 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
662 enum intel_guc_sleep_state_status {
663 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
664 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
665 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
666 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
669 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
670 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
671 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
672 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
674 enum intel_guc_response_status {
675 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
676 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
679 #define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
680 (typecheck(u32, (m)) && \
681 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
682 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
683 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
685 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
686 enum intel_guc_recv_message {
687 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
688 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)