drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38 #include "i915_drv.h"
  39 #include "gvt.h"
  40 #include "i915_pvinfo.h"
  41 #include "trace.h"
  42
  43 #define INVALID_OP    (~0U)
  44
  45 #define OP_LEN_MI           9
  46 #define OP_LEN_2D           10
  47 #define OP_LEN_3D_MEDIA     16
  48 #define OP_LEN_MFX_VC       16
  49 #define OP_LEN_VEBOX        16
  50
  51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  52
  53 struct sub_op_bits {
  54         int hi;
  55         int low;
  56 };
  57 struct decode_info {
  58         char *name;
  59         int op_len;
  60         int nr_sub_op;
  61         struct sub_op_bits *sub_op;
  62 };
  63
  64 #define   MAX_CMD_BUDGET                        0x7fffffff
  65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  68
  69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  72
  73 /* Render Command Map */
  74
  75 /* MI_* command Opcode (28:23) */
  76 #define OP_MI_NOOP                          0x0
  77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  78 #define OP_MI_USER_INTERRUPT                0x2
  79 #define OP_MI_WAIT_FOR_EVENT                0x3
  80 #define OP_MI_FLUSH                         0x4
  81 #define OP_MI_ARB_CHECK                     0x5
  82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  83 #define OP_MI_REPORT_HEAD                   0x7
  84 #define OP_MI_ARB_ON_OFF                    0x8
  85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  86 #define OP_MI_BATCH_BUFFER_END              0xA
  87 #define OP_MI_SUSPEND_FLUSH                 0xB
  88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
  90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
  91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
  92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
  93 #define OP_MI_DISPLAY_FLIP                  0x14
  94 #define OP_MI_SEMAPHORE_MBOX                0x16
  95 #define OP_MI_SET_CONTEXT                   0x18
  96 #define OP_MI_MATH                          0x1A
  97 #define OP_MI_URB_CLEAR                     0x19
  98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
  99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 100
 101 #define OP_MI_STORE_DATA_IMM                0x20
 102 #define OP_MI_STORE_DATA_INDEX              0x21
 103 #define OP_MI_LOAD_REGISTER_IMM             0x22
 104 #define OP_MI_UPDATE_GTT                    0x23
 105 #define OP_MI_STORE_REGISTER_MEM            0x24
 106 #define OP_MI_FLUSH_DW                      0x26
 107 #define OP_MI_CLFLUSH                       0x27
 108 #define OP_MI_REPORT_PERF_COUNT             0x28
 109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 114 #define OP_MI_2E                            0x2E  /* BDW+ */
 115 #define OP_MI_2F                            0x2F  /* BDW+ */
 116 #define OP_MI_BATCH_BUFFER_START            0x31
 117
 118 /* Bit definition for dword 0 */
 119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 120
 121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 122
 123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 127
 128 /* 2D command: Opcode (28:22) */
 129 #define OP_2D(x)    ((2<<7) | x)
 130
 131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 155
 156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 159
 160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 161
 162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 165
 166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 167
 168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 169
 170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 175
 176 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 177 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 178 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 179 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 180
 181 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 182 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 183 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 184 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 185 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 186 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 187 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 188 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 189 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 190 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 192 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 193 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 194 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 195 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 196 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 197 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 198 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 199 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 200 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 201 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 202 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 203 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 204 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 205 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 206 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 207 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 208 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 211 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 223 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 224 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 225 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 226 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 227 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 228 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 229 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 230 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 231 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 232 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 233 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 234 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 235 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 236 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 237 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 247
 248 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 249 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 250 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 251 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 252 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 253 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 254 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 255 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 256 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 257 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 258 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 259
 260 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 262 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 263 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 266 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 267 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 268 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 270 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 271 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 273 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 274 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 280 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 281 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 283 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 285 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 286 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 287 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 288
 289 /* VCCP Command Parser */
 290
 291 /*
 292  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 293  * git://anongit.freedesktop.org/vaapi/intel-driver
 294  * src/i965_defines.h
 295  *
 296  */
 297
 298 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 299         (3 << 13 | \
 300          (pipeline) << 11 | \
 301          (op) << 8 | \
 302          (sub_opa) << 5 | \
 303          (sub_opb))
 304
 305 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 306 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 307 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 310 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 311 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 312 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 313 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 314 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 315 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 316
 317 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 318
 319 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 320 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 321 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 322 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 323 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 324 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 326 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 327 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 328 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 329 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 330 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 331
 332 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 333 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 334 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 335 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 336 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 337
 338 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 339 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 340 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 341 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 342 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 343
 344 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 345 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 346 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 347
 348 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 349 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 350 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 351
 352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 353         (3 << 13 | \
 354          (pipeline) << 11 | \
 355          (op) << 8 | \
 356          (sub_opa) << 5 | \
 357          (sub_opb))
 358
 359 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 360 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 361 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 362
 363 struct parser_exec_state;
 364
 365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 366
 367 #define GVT_CMD_HASH_BITS   7
 368
 369 /* which DWords need address fix */
 370 #define ADDR_FIX_1(x1)                  (1 << (x1))
 371 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 372 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 373 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 374 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 375
 376 struct cmd_info {
 377         char *name;
 378         u32 opcode;
 379
 380 #define F_LEN_MASK      (1U<<0)
 381 #define F_LEN_CONST  1U
 382 #define F_LEN_VAR    0U
 383
 384 /*
 385  * command has its own ip advance logic
 386  * e.g. MI_BATCH_START, MI_BATCH_END
 387  */
 388 #define F_IP_ADVANCE_CUSTOM (1<<1)
 389
 390 #define F_POST_HANDLE   (1<<2)
 391         u32 flag;
 392
 393 #define R_RCS   (1 << RCS)
 394 #define R_VCS1  (1 << VCS)
 395 #define R_VCS2  (1 << VCS2)
 396 #define R_VCS   (R_VCS1 | R_VCS2)
 397 #define R_BCS   (1 << BCS)
 398 #define R_VECS  (1 << VECS)
 399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 400         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 401         uint16_t rings;
 402
 403         /* devices that support this cmd: SNB/IVB/HSW/... */
 404         uint16_t devices;
 405
 406         /* which DWords are address that need fix up.
 407          * bit 0 means a 32-bit non address operand in command
 408          * bit 1 means address operand, which could be 32-bit
 409          * or 64-bit depending on different architectures.(
 410          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 411          * No matter the address length, each address only takes
 412          * one bit in the bitmap.
 413          */
 414         uint16_t addr_bitmap;
 415
 416         /* flag == F_LEN_CONST : command length
 417          * flag == F_LEN_VAR : length bias bits
 418          * Note: length is in DWord
 419          */
 420         uint8_t len;
 421
 422         parser_cmd_handler handler;
 423 };
 424
 425 struct cmd_entry {
 426         struct hlist_node hlist;
 427         struct cmd_info *info;
 428 };
 429
 430 enum {
 431         RING_BUFFER_INSTRUCTION,
 432         BATCH_BUFFER_INSTRUCTION,
 433         BATCH_BUFFER_2ND_LEVEL,
 434 };
 435
 436 enum {
 437         GTT_BUFFER,
 438         PPGTT_BUFFER
 439 };
 440
 441 struct parser_exec_state {
 442         struct intel_vgpu *vgpu;
 443         int ring_id;
 444
 445         int buf_type;
 446
 447         /* batch buffer address type */
 448         int buf_addr_type;
 449
 450         /* graphics memory address of ring buffer start */
 451         unsigned long ring_start;
 452         unsigned long ring_size;
 453         unsigned long ring_head;
 454         unsigned long ring_tail;
 455
 456         /* instruction graphics memory address */
 457         unsigned long ip_gma;
 458
 459         /* mapped va of the instr_gma */
 460         void *ip_va;
 461         void *rb_va;
 462
 463         void *ret_bb_va;
 464         /* next instruction when return from  batch buffer to ring buffer */
 465         unsigned long ret_ip_gma_ring;
 466
 467         /* next instruction when return from 2nd batch buffer to batch buffer */
 468         unsigned long ret_ip_gma_bb;
 469
 470         /* batch buffer address type (GTT or PPGTT)
 471          * used when ret from 2nd level batch buffer
 472          */
 473         int saved_buf_addr_type;
 474
 475         struct cmd_info *info;
 476
 477         struct intel_vgpu_workload *workload;
 478 };
 479
 480 #define gmadr_dw_number(s)      \
 481         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 482
 483 static unsigned long bypass_scan_mask = 0;
 484 static bool bypass_batch_buffer_scan = true;
 485
 486 /* ring ALL, type = 0 */
 487 static struct sub_op_bits sub_op_mi[] = {
 488         {31, 29},
 489         {28, 23},
 490 };
 491
 492 static struct decode_info decode_info_mi = {
 493         "MI",
 494         OP_LEN_MI,
 495         ARRAY_SIZE(sub_op_mi),
 496         sub_op_mi,
 497 };
 498
 499 /* ring RCS, command type 2 */
 500 static struct sub_op_bits sub_op_2d[] = {
 501         {31, 29},
 502         {28, 22},
 503 };
 504
 505 static struct decode_info decode_info_2d = {
 506         "2D",
 507         OP_LEN_2D,
 508         ARRAY_SIZE(sub_op_2d),
 509         sub_op_2d,
 510 };
 511
 512 /* ring RCS, command type 3 */
 513 static struct sub_op_bits sub_op_3d_media[] = {
 514         {31, 29},
 515         {28, 27},
 516         {26, 24},
 517         {23, 16},
 518 };
 519
 520 static struct decode_info decode_info_3d_media = {
 521         "3D_Media",
 522         OP_LEN_3D_MEDIA,
 523         ARRAY_SIZE(sub_op_3d_media),
 524         sub_op_3d_media,
 525 };
 526
 527 /* ring VCS, command type 3 */
 528 static struct sub_op_bits sub_op_mfx_vc[] = {
 529         {31, 29},
 530         {28, 27},
 531         {26, 24},
 532         {23, 21},
 533         {20, 16},
 534 };
 535
 536 static struct decode_info decode_info_mfx_vc = {
 537         "MFX_VC",
 538         OP_LEN_MFX_VC,
 539         ARRAY_SIZE(sub_op_mfx_vc),
 540         sub_op_mfx_vc,
 541 };
 542
 543 /* ring VECS, command type 3 */
 544 static struct sub_op_bits sub_op_vebox[] = {
 545         {31, 29},
 546         {28, 27},
 547         {26, 24},
 548         {23, 21},
 549         {20, 16},
 550 };
 551
 552 static struct decode_info decode_info_vebox = {
 553         "VEBOX",
 554         OP_LEN_VEBOX,
 555         ARRAY_SIZE(sub_op_vebox),
 556         sub_op_vebox,
 557 };
 558
 559 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 560         [RCS] = {
 561                 &decode_info_mi,
 562                 NULL,
 563                 NULL,
 564                 &decode_info_3d_media,
 565                 NULL,
 566                 NULL,
 567                 NULL,
 568                 NULL,
 569         },
 570
 571         [VCS] = {
 572                 &decode_info_mi,
 573                 NULL,
 574                 NULL,
 575                 &decode_info_mfx_vc,
 576                 NULL,
 577                 NULL,
 578                 NULL,
 579                 NULL,
 580         },
 581
 582         [BCS] = {
 583                 &decode_info_mi,
 584                 NULL,
 585                 &decode_info_2d,
 586                 NULL,
 587                 NULL,
 588                 NULL,
 589                 NULL,
 590                 NULL,
 591         },
 592
 593         [VECS] = {
 594                 &decode_info_mi,
 595                 NULL,
 596                 NULL,
 597                 &decode_info_vebox,
 598                 NULL,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602         },
 603
 604         [VCS2] = {
 605                 &decode_info_mi,
 606                 NULL,
 607                 NULL,
 608                 &decode_info_mfx_vc,
 609                 NULL,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613         },
 614 };
 615
 616 static inline u32 get_opcode(u32 cmd, int ring_id)
 617 {
 618         struct decode_info *d_info;
 619
 620         if (ring_id >= I915_NUM_ENGINES)
 621                 return INVALID_OP;
 622
 623         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 624         if (d_info == NULL)
 625                 return INVALID_OP;
 626
 627         return cmd >> (32 - d_info->op_len);
 628 }
 629
 630 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
 631                 unsigned int opcode, int ring_id)
 632 {
 633         struct cmd_entry *e;
 634
 635         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 636                 if ((opcode == e->info->opcode) &&
 637                                 (e->info->rings & (1 << ring_id)))
 638                         return e->info;
 639         }
 640         return NULL;
 641 }
 642
 643 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
 644                 u32 cmd, int ring_id)
 645 {
 646         u32 opcode;
 647
 648         opcode = get_opcode(cmd, ring_id);
 649         if (opcode == INVALID_OP)
 650                 return NULL;
 651
 652         return find_cmd_entry(gvt, opcode, ring_id);
 653 }
 654
 655 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 656 {
 657         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 658 }
 659
 660 static inline void print_opcode(u32 cmd, int ring_id)
 661 {
 662         struct decode_info *d_info;
 663         int i;
 664
 665         if (ring_id >= I915_NUM_ENGINES)
 666                 return;
 667
 668         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 669         if (d_info == NULL)
 670                 return;
 671
 672         gvt_err("opcode=0x%x %s sub_ops:",
 673                         cmd >> (32 - d_info->op_len), d_info->name);
 674
 675         for (i = 0; i < d_info->nr_sub_op; i++)
 676                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 677                                         d_info->sub_op[i].low));
 678
 679         pr_err("\n");
 680 }
 681
 682 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 683 {
 684         return s->ip_va + (index << 2);
 685 }
 686
 687 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 688 {
 689         return *cmd_ptr(s, index);
 690 }
 691
 692 static void parser_exec_state_dump(struct parser_exec_state *s)
 693 {
 694         int cnt = 0;
 695         int i;
 696
 697         gvt_err("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
 698                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
 699                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
 700                         s->ring_head, s->ring_tail);
 701
 702         gvt_err("  %s %s ip_gma(%08lx) ",
 703                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 704                         "RING_BUFFER" : "BATCH_BUFFER",
 705                         s->buf_addr_type == GTT_BUFFER ?
 706                         "GTT" : "PPGTT", s->ip_gma);
 707
 708         if (s->ip_va == NULL) {
 709                 gvt_err(" ip_va(NULL)");
 710                 return;
 711         }
 712
 713         gvt_err("  ip_va=%p: %08x %08x %08x %08x\n",
 714                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 715                         cmd_val(s, 2), cmd_val(s, 3));
 716
 717         print_opcode(cmd_val(s, 0), s->ring_id);
 718
 719         /* print the whole page to trace */
 720         pr_err("    ip_va=%p: %08x %08x %08x %08x\n",
 721                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 722                         cmd_val(s, 2), cmd_val(s, 3));
 723
 724         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 725
 726         while (cnt < 1024) {
 727                 pr_err("ip_va=%p: ", s->ip_va);
 728                 for (i = 0; i < 8; i++)
 729                         pr_err("%08x ", cmd_val(s, i));
 730                 pr_err("\n");
 731
 732                 s->ip_va += 8 * sizeof(u32);
 733                 cnt += 8;
 734         }
 735 }
 736
 737 static inline void update_ip_va(struct parser_exec_state *s)
 738 {
 739         unsigned long len = 0;
 740
 741         if (WARN_ON(s->ring_head == s->ring_tail))
 742                 return;
 743
 744         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 745                 unsigned long ring_top = s->ring_start + s->ring_size;
 746
 747                 if (s->ring_head > s->ring_tail) {
 748                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 749                                 len = (s->ip_gma - s->ring_head);
 750                         else if (s->ip_gma >= s->ring_start &&
 751                                         s->ip_gma <= s->ring_tail)
 752                                 len = (ring_top - s->ring_head) +
 753                                         (s->ip_gma - s->ring_start);
 754                 } else
 755                         len = (s->ip_gma - s->ring_head);
 756
 757                 s->ip_va = s->rb_va + len;
 758         } else {/* shadow batch buffer */
 759                 s->ip_va = s->ret_bb_va;
 760         }
 761 }
 762
 763 static inline int ip_gma_set(struct parser_exec_state *s,
 764                 unsigned long ip_gma)
 765 {
 766         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 767
 768         s->ip_gma = ip_gma;
 769         update_ip_va(s);
 770         return 0;
 771 }
 772
 773 static inline int ip_gma_advance(struct parser_exec_state *s,
 774                 unsigned int dw_len)
 775 {
 776         s->ip_gma += (dw_len << 2);
 777
 778         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 779                 if (s->ip_gma >= s->ring_start + s->ring_size)
 780                         s->ip_gma -= s->ring_size;
 781                 update_ip_va(s);
 782         } else {
 783                 s->ip_va += (dw_len << 2);
 784         }
 785
 786         return 0;
 787 }
 788
 789 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
 790 {
 791         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 792                 return info->len;
 793         else
 794                 return (cmd & ((1U << info->len) - 1)) + 2;
 795         return 0;
 796 }
 797
 798 static inline int cmd_length(struct parser_exec_state *s)
 799 {
 800         return get_cmd_length(s->info, cmd_val(s, 0));
 801 }
 802
 803 /* do not remove this, some platform may need clflush here */
 804 #define patch_value(s, addr, val) do { \
 805         *addr = val; \
 806 } while (0)
 807
 808 static bool is_shadowed_mmio(unsigned int offset)
 809 {
 810         bool ret = false;
 811
 812         if ((offset == 0x2168) || /*BB current head register UDW */
 813             (offset == 0x2140) || /*BB current header register */
 814             (offset == 0x211c) || /*second BB header register UDW */
 815             (offset == 0x2114)) { /*second BB header register UDW */
 816                 ret = true;
 817         }
 818         return ret;
 819 }
 820
 821 static int cmd_reg_handler(struct parser_exec_state *s,
 822         unsigned int offset, unsigned int index, char *cmd)
 823 {
 824         struct intel_vgpu *vgpu = s->vgpu;
 825         struct intel_gvt *gvt = vgpu->gvt;
 826
 827         if (offset + 4 > gvt->device_info.mmio_size) {
 828                 gvt_err("%s access to (%x) outside of MMIO range\n",
 829                                 cmd, offset);
 830                 return -EINVAL;
 831         }
 832
 833         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
 834                 gvt_err("vgpu%d: %s access to non-render register (%x)\n",
 835                                 s->vgpu->id, cmd, offset);
 836                 return 0;
 837         }
 838
 839         if (is_shadowed_mmio(offset)) {
 840                 gvt_err("vgpu%d: found access of shadowed MMIO %x\n",
 841                                 s->vgpu->id, offset);
 842                 return 0;
 843         }
 844
 845         if (offset == i915_mmio_reg_offset(DERRMR) ||
 846                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 847                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 848                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 849         }
 850
 851         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
 852         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
 853         return 0;
 854 }
 855
 856 #define cmd_reg(s, i) \
 857         (cmd_val(s, i) & GENMASK(22, 2))
 858
 859 #define cmd_reg_inhibit(s, i) \
 860         (cmd_val(s, i) & GENMASK(22, 18))
 861
 862 #define cmd_gma(s, i) \
 863         (cmd_val(s, i) & GENMASK(31, 2))
 864
 865 #define cmd_gma_hi(s, i) \
 866         (cmd_val(s, i) & GENMASK(15, 0))
 867
 868 static int cmd_handler_lri(struct parser_exec_state *s)
 869 {
 870         int i, ret = 0;
 871         int cmd_len = cmd_length(s);
 872         struct intel_gvt *gvt = s->vgpu->gvt;
 873
 874         for (i = 1; i < cmd_len; i += 2) {
 875                 if (IS_BROADWELL(gvt->dev_priv) &&
 876                                 (s->ring_id != RCS)) {
 877                         if (s->ring_id == BCS &&
 878                                         cmd_reg(s, i) ==
 879                                         i915_mmio_reg_offset(DERRMR))
 880                                 ret |= 0;
 881                         else
 882                                 ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0;
 883                 }
 884                 if (ret)
 885                         break;
 886                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
 887         }
 888         return ret;
 889 }
 890
 891 static int cmd_handler_lrr(struct parser_exec_state *s)
 892 {
 893         int i, ret = 0;
 894         int cmd_len = cmd_length(s);
 895
 896         for (i = 1; i < cmd_len; i += 2) {
 897                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
 898                         ret |= ((cmd_reg_inhibit(s, i) ||
 899                                         (cmd_reg_inhibit(s, i + 1)))) ?
 900                                 -EINVAL : 0;
 901                 if (ret)
 902                         break;
 903                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
 904                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
 905         }
 906         return ret;
 907 }
 908
 909 static inline int cmd_address_audit(struct parser_exec_state *s,
 910                 unsigned long guest_gma, int op_size, bool index_mode);
 911
 912 static int cmd_handler_lrm(struct parser_exec_state *s)
 913 {
 914         struct intel_gvt *gvt = s->vgpu->gvt;
 915         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 916         unsigned long gma;
 917         int i, ret = 0;
 918         int cmd_len = cmd_length(s);
 919
 920         for (i = 1; i < cmd_len;) {
 921                 if (IS_BROADWELL(gvt->dev_priv))
 922                         ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0;
 923                 if (ret)
 924                         break;
 925                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
 926                 if (cmd_val(s, 0) & (1 << 22)) {
 927                         gma = cmd_gma(s, i + 1);
 928                         if (gmadr_bytes == 8)
 929                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
 930                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
 931                 }
 932                 i += gmadr_dw_number(s) + 1;
 933         }
 934         return ret;
 935 }
 936
 937 static int cmd_handler_srm(struct parser_exec_state *s)
 938 {
 939         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
 940         unsigned long gma;
 941         int i, ret = 0;
 942         int cmd_len = cmd_length(s);
 943
 944         for (i = 1; i < cmd_len;) {
 945                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
 946                 if (cmd_val(s, 0) & (1 << 22)) {
 947                         gma = cmd_gma(s, i + 1);
 948                         if (gmadr_bytes == 8)
 949                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
 950                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
 951                 }
 952                 i += gmadr_dw_number(s) + 1;
 953         }
 954         return ret;
 955 }
 956
 957 struct cmd_interrupt_event {
 958         int pipe_control_notify;
 959         int mi_flush_dw;
 960         int mi_user_interrupt;
 961 };
 962
 963 static struct cmd_interrupt_event cmd_interrupt_events[] = {
 964         [RCS] = {
 965                 .pipe_control_notify = RCS_PIPE_CONTROL,
 966                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
 967                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
 968         },
 969         [BCS] = {
 970                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
 971                 .mi_flush_dw = BCS_MI_FLUSH_DW,
 972                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
 973         },
 974         [VCS] = {
 975                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
 976                 .mi_flush_dw = VCS_MI_FLUSH_DW,
 977                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
 978         },
 979         [VCS2] = {
 980                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
 981                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
 982                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
 983         },
 984         [VECS] = {
 985                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
 986                 .mi_flush_dw = VECS_MI_FLUSH_DW,
 987                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
 988         },
 989 };
 990
 991 static int cmd_handler_pipe_control(struct parser_exec_state *s)
 992 {
 993         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
 994         unsigned long gma;
 995         bool index_mode = false;
 996         unsigned int post_sync;
 997         int ret = 0;
 998
 999         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1000
1001         /* LRI post sync */
1002         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1003                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1004         /* post sync */
1005         else if (post_sync) {
1006                 if (post_sync == 2)
1007                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1008                 else if (post_sync == 3)
1009                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1010                 else if (post_sync == 1) {
1011                         /* check ggtt*/
1012                         if ((cmd_val(s, 2) & (1 << 2))) {
1013                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1014                                 if (gmadr_bytes == 8)
1015                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1016                                 /* Store Data Index */
1017                                 if (cmd_val(s, 1) & (1 << 21))
1018                                         index_mode = true;
1019                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1020                                                 index_mode);
1021                         }
1022                 }
1023         }
1024
1025         if (ret)
1026                 return ret;
1027
1028         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1029                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1030                                 s->workload->pending_events);
1031         return 0;
1032 }
1033
1034 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1035 {
1036         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1037                         s->workload->pending_events);
1038         return 0;
1039 }
1040
1041 static int cmd_advance_default(struct parser_exec_state *s)
1042 {
1043         return ip_gma_advance(s, cmd_length(s));
1044 }
1045
1046 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1047 {
1048         int ret;
1049
1050         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1051                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1052                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1053                 s->buf_addr_type = s->saved_buf_addr_type;
1054         } else {
1055                 s->buf_type = RING_BUFFER_INSTRUCTION;
1056                 s->buf_addr_type = GTT_BUFFER;
1057                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1058                         s->ret_ip_gma_ring -= s->ring_size;
1059                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1060         }
1061         return ret;
1062 }
1063
1064 struct mi_display_flip_command_info {
1065         int pipe;
1066         int plane;
1067         int event;
1068         i915_reg_t stride_reg;
1069         i915_reg_t ctrl_reg;
1070         i915_reg_t surf_reg;
1071         u64 stride_val;
1072         u64 tile_val;
1073         u64 surf_val;
1074         bool async_flip;
1075 };
1076
1077 struct plane_code_mapping {
1078         int pipe;
1079         int plane;
1080         int event;
1081 };
1082
1083 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1084                 struct mi_display_flip_command_info *info)
1085 {
1086         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1087         struct plane_code_mapping gen8_plane_code[] = {
1088                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1089                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1090                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1091                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1092                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1093                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1094         };
1095         u32 dword0, dword1, dword2;
1096         u32 v;
1097
1098         dword0 = cmd_val(s, 0);
1099         dword1 = cmd_val(s, 1);
1100         dword2 = cmd_val(s, 2);
1101
1102         v = (dword0 & GENMASK(21, 19)) >> 19;
1103         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1104                 return -EINVAL;
1105
1106         info->pipe = gen8_plane_code[v].pipe;
1107         info->plane = gen8_plane_code[v].plane;
1108         info->event = gen8_plane_code[v].event;
1109         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1110         info->tile_val = (dword1 & 0x1);
1111         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1112         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1113
1114         if (info->plane == PLANE_A) {
1115                 info->ctrl_reg = DSPCNTR(info->pipe);
1116                 info->stride_reg = DSPSTRIDE(info->pipe);
1117                 info->surf_reg = DSPSURF(info->pipe);
1118         } else if (info->plane == PLANE_B) {
1119                 info->ctrl_reg = SPRCTL(info->pipe);
1120                 info->stride_reg = SPRSTRIDE(info->pipe);
1121                 info->surf_reg = SPRSURF(info->pipe);
1122         } else {
1123                 WARN_ON(1);
1124                 return -EINVAL;
1125         }
1126         return 0;
1127 }
1128
1129 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1130                 struct mi_display_flip_command_info *info)
1131 {
1132         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1133         u32 dword0 = cmd_val(s, 0);
1134         u32 dword1 = cmd_val(s, 1);
1135         u32 dword2 = cmd_val(s, 2);
1136         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1137
1138         switch (plane) {
1139         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1140                 info->pipe = PIPE_A;
1141                 info->event = PRIMARY_A_FLIP_DONE;
1142                 break;
1143         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1144                 info->pipe = PIPE_B;
1145                 info->event = PRIMARY_B_FLIP_DONE;
1146                 break;
1147         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1148                 info->pipe = PIPE_C;
1149                 info->event = PRIMARY_C_FLIP_DONE;
1150                 break;
1151         default:
1152                 gvt_err("unknown plane code %d\n", plane);
1153                 return -EINVAL;
1154         }
1155
1156         info->pipe = PRIMARY_PLANE;
1157         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1158         info->tile_val = (dword1 & GENMASK(2, 0));
1159         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1160         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1161
1162         info->ctrl_reg = DSPCNTR(info->pipe);
1163         info->stride_reg = DSPSTRIDE(info->pipe);
1164         info->surf_reg = DSPSURF(info->pipe);
1165
1166         return 0;
1167 }
1168
1169 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1170                 struct mi_display_flip_command_info *info)
1171 {
1172         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1173         u32 stride, tile;
1174
1175         if (!info->async_flip)
1176                 return 0;
1177
1178         if (IS_SKYLAKE(dev_priv)) {
1179                 stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1180                 tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &
1181                                 GENMASK(12, 10)) >> 10;
1182         } else {
1183                 stride = (vgpu_vreg(s->vgpu, info->stride_reg) &
1184                                 GENMASK(15, 6)) >> 6;
1185                 tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1186         }
1187
1188         if (stride != info->stride_val)
1189                 gvt_dbg_cmd("cannot change stride during async flip\n");
1190
1191         if (tile != info->tile_val)
1192                 gvt_dbg_cmd("cannot change tile during async flip\n");
1193
1194         return 0;
1195 }
1196
1197 static int gen8_update_plane_mmio_from_mi_display_flip(
1198                 struct parser_exec_state *s,
1199                 struct mi_display_flip_command_info *info)
1200 {
1201         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1202         struct intel_vgpu *vgpu = s->vgpu;
1203
1204         set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),
1205                       info->surf_val << 12);
1206         if (IS_SKYLAKE(dev_priv)) {
1207                 set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),
1208                               info->stride_val);
1209                 set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),
1210                               info->tile_val << 10);
1211         } else {
1212                 set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(15, 6),
1213                               info->stride_val << 6);
1214                 set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(10, 10),
1215                               info->tile_val << 10);
1216         }
1217
1218         vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1219         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1220         return 0;
1221 }
1222
1223 static int decode_mi_display_flip(struct parser_exec_state *s,
1224                 struct mi_display_flip_command_info *info)
1225 {
1226         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1227
1228         if (IS_BROADWELL(dev_priv))
1229                 return gen8_decode_mi_display_flip(s, info);
1230         if (IS_SKYLAKE(dev_priv))
1231                 return skl_decode_mi_display_flip(s, info);
1232
1233         return -ENODEV;
1234 }
1235
1236 static int check_mi_display_flip(struct parser_exec_state *s,
1237                 struct mi_display_flip_command_info *info)
1238 {
1239         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1240
1241         if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
1242                 return gen8_check_mi_display_flip(s, info);
1243         return -ENODEV;
1244 }
1245
1246 static int update_plane_mmio_from_mi_display_flip(
1247                 struct parser_exec_state *s,
1248                 struct mi_display_flip_command_info *info)
1249 {
1250         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1251
1252         if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
1253                 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1254         return -ENODEV;
1255 }
1256
1257 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1258 {
1259         struct mi_display_flip_command_info info;
1260         int ret;
1261         int i;
1262         int len = cmd_length(s);
1263
1264         ret = decode_mi_display_flip(s, &info);
1265         if (ret) {
1266                 gvt_err("fail to decode MI display flip command\n");
1267                 return ret;
1268         }
1269
1270         ret = check_mi_display_flip(s, &info);
1271         if (ret) {
1272                 gvt_err("invalid MI display flip command\n");
1273                 return ret;
1274         }
1275
1276         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1277         if (ret) {
1278                 gvt_err("fail to update plane mmio\n");
1279                 return ret;
1280         }
1281
1282         for (i = 0; i < len; i++)
1283                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1284         return 0;
1285 }
1286
1287 static bool is_wait_for_flip_pending(u32 cmd)
1288 {
1289         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1290                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1291                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1292                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1293                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1294                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1295 }
1296
1297 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1298 {
1299         u32 cmd = cmd_val(s, 0);
1300
1301         if (!is_wait_for_flip_pending(cmd))
1302                 return 0;
1303
1304         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1305         return 0;
1306 }
1307
1308 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1309 {
1310         unsigned long addr;
1311         unsigned long gma_high, gma_low;
1312         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1313
1314         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8))
1315                 return INTEL_GVT_INVALID_ADDR;
1316
1317         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1318         if (gmadr_bytes == 4) {
1319                 addr = gma_low;
1320         } else {
1321                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1322                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1323         }
1324         return addr;
1325 }
1326
1327 static inline int cmd_address_audit(struct parser_exec_state *s,
1328                 unsigned long guest_gma, int op_size, bool index_mode)
1329 {
1330         struct intel_vgpu *vgpu = s->vgpu;
1331         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1332         int i;
1333         int ret;
1334
1335         if (op_size > max_surface_size) {
1336                 gvt_err("command address audit fail name %s\n", s->info->name);
1337                 return -EINVAL;
1338         }
1339
1340         if (index_mode) {
1341                 if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) {
1342                         ret = -EINVAL;
1343                         goto err;
1344                 }
1345         } else if ((!vgpu_gmadr_is_valid(s->vgpu, guest_gma)) ||
1346                         (!vgpu_gmadr_is_valid(s->vgpu,
1347                                               guest_gma + op_size - 1))) {
1348                 ret = -EINVAL;
1349                 goto err;
1350         }
1351         return 0;
1352 err:
1353         gvt_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1354                         s->info->name, guest_gma, op_size);
1355
1356         pr_err("cmd dump: ");
1357         for (i = 0; i < cmd_length(s); i++) {
1358                 if (!(i % 4))
1359                         pr_err("\n%08x ", cmd_val(s, i));
1360                 else
1361                         pr_err("%08x ", cmd_val(s, i));
1362         }
1363         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1364                         vgpu->id,
1365                         vgpu_aperture_gmadr_base(vgpu),
1366                         vgpu_aperture_gmadr_end(vgpu),
1367                         vgpu_hidden_gmadr_base(vgpu),
1368                         vgpu_hidden_gmadr_end(vgpu));
1369         return ret;
1370 }
1371
1372 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1373 {
1374         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1375         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1376         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1377         unsigned long gma, gma_low, gma_high;
1378         int ret = 0;
1379
1380         /* check ppggt */
1381         if (!(cmd_val(s, 0) & (1 << 22)))
1382                 return 0;
1383
1384         gma = cmd_val(s, 2) & GENMASK(31, 2);
1385
1386         if (gmadr_bytes == 8) {
1387                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1388                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1389                 gma = (gma_high << 32) | gma_low;
1390                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1391         }
1392         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1393         return ret;
1394 }
1395
1396 static inline int unexpected_cmd(struct parser_exec_state *s)
1397 {
1398         gvt_err("vgpu%d: Unexpected %s in command buffer!\n",
1399                         s->vgpu->id, s->info->name);
1400         return -EINVAL;
1401 }
1402
1403 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1404 {
1405         return unexpected_cmd(s);
1406 }
1407
1408 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1409 {
1410         return unexpected_cmd(s);
1411 }
1412
1413 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1414 {
1415         return unexpected_cmd(s);
1416 }
1417
1418 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1419 {
1420         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1421         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1422                         sizeof(u32);
1423         unsigned long gma, gma_high;
1424         int ret = 0;
1425
1426         if (!(cmd_val(s, 0) & (1 << 22)))
1427                 return ret;
1428
1429         gma = cmd_val(s, 1) & GENMASK(31, 2);
1430         if (gmadr_bytes == 8) {
1431                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1432                 gma = (gma_high << 32) | gma;
1433         }
1434         ret = cmd_address_audit(s, gma, op_size, false);
1435         return ret;
1436 }
1437
1438 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1439 {
1440         return unexpected_cmd(s);
1441 }
1442
1443 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1444 {
1445         return unexpected_cmd(s);
1446 }
1447
1448 static int cmd_handler_mi_conditional_batch_buffer_end(
1449                 struct parser_exec_state *s)
1450 {
1451         return unexpected_cmd(s);
1452 }
1453
1454 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1455 {
1456         return unexpected_cmd(s);
1457 }
1458
1459 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1460 {
1461         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1462         unsigned long gma;
1463         bool index_mode = false;
1464         int ret = 0;
1465
1466         /* Check post-sync and ppgtt bit */
1467         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1468                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1469                 if (gmadr_bytes == 8)
1470                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1471                 /* Store Data Index */
1472                 if (cmd_val(s, 0) & (1 << 21))
1473                         index_mode = true;
1474                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1475         }
1476         /* Check notify bit */
1477         if ((cmd_val(s, 0) & (1 << 8)))
1478                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1479                                 s->workload->pending_events);
1480         return ret;
1481 }
1482
1483 static void addr_type_update_snb(struct parser_exec_state *s)
1484 {
1485         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1486                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1487                 s->buf_addr_type = PPGTT_BUFFER;
1488         }
1489 }
1490
1491
1492 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1493                 unsigned long gma, unsigned long end_gma, void *va)
1494 {
1495         unsigned long copy_len, offset;
1496         unsigned long len = 0;
1497         unsigned long gpa;
1498
1499         while (gma != end_gma) {
1500                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1501                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1502                         gvt_err("invalid gma address: %lx\n", gma);
1503                         return -EFAULT;
1504                 }
1505
1506                 offset = gma & (GTT_PAGE_SIZE - 1);
1507
1508                 copy_len = (end_gma - gma) >= (GTT_PAGE_SIZE - offset) ?
1509                         GTT_PAGE_SIZE - offset : end_gma - gma;
1510
1511                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1512
1513                 len += copy_len;
1514                 gma += copy_len;
1515         }
1516         return 0;
1517 }
1518
1519
1520 /*
1521  * Check whether a batch buffer needs to be scanned. Currently
1522  * the only criteria is based on privilege.
1523  */
1524 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1525 {
1526         struct intel_gvt *gvt = s->vgpu->gvt;
1527
1528         if (bypass_batch_buffer_scan)
1529                 return 0;
1530
1531         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
1532                 /* BDW decides privilege based on address space */
1533                 if (cmd_val(s, 0) & (1 << 8))
1534                         return 0;
1535         }
1536         return 1;
1537 }
1538
1539 static uint32_t find_bb_size(struct parser_exec_state *s)
1540 {
1541         unsigned long gma = 0;
1542         struct cmd_info *info;
1543         uint32_t bb_size = 0;
1544         uint32_t cmd_len = 0;
1545         bool met_bb_end = false;
1546         u32 cmd;
1547
1548         /* get the start gm address of the batch buffer */
1549         gma = get_gma_bb_from_cmd(s, 1);
1550         cmd = cmd_val(s, 0);
1551
1552         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1553         if (info == NULL) {
1554                 gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
1555                                 cmd, get_opcode(cmd, s->ring_id));
1556                 return -EINVAL;
1557         }
1558         do {
1559                 copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1560                                 gma, gma + 4, &cmd);
1561                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1562                 if (info == NULL) {
1563                         gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
1564                                 cmd, get_opcode(cmd, s->ring_id));
1565                         return -EINVAL;
1566                 }
1567
1568                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1569                         met_bb_end = true;
1570                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1571                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) {
1572                                 /* chained batch buffer */
1573                                 met_bb_end = true;
1574                         }
1575                 }
1576                 cmd_len = get_cmd_length(info, cmd) << 2;
1577                 bb_size += cmd_len;
1578                 gma += cmd_len;
1579
1580         } while (!met_bb_end);
1581
1582         return bb_size;
1583 }
1584
1585 static int perform_bb_shadow(struct parser_exec_state *s)
1586 {
1587         struct intel_shadow_bb_entry *entry_obj;
1588         unsigned long gma = 0;
1589         uint32_t bb_size;
1590         void *dst = NULL;
1591         int ret = 0;
1592
1593         /* get the start gm address of the batch buffer */
1594         gma = get_gma_bb_from_cmd(s, 1);
1595
1596         /* get the size of the batch buffer */
1597         bb_size = find_bb_size(s);
1598
1599         /* allocate shadow batch buffer */
1600         entry_obj = kmalloc(sizeof(*entry_obj), GFP_KERNEL);
1601         if (entry_obj == NULL)
1602                 return -ENOMEM;
1603
1604         entry_obj->obj =
1605                 i915_gem_object_create(&(s->vgpu->gvt->dev_priv->drm),
1606                                        roundup(bb_size, PAGE_SIZE));
1607         if (IS_ERR(entry_obj->obj)) {
1608                 ret = PTR_ERR(entry_obj->obj);
1609                 goto free_entry;
1610         }
1611         entry_obj->len = bb_size;
1612         INIT_LIST_HEAD(&entry_obj->list);
1613
1614         dst = i915_gem_object_pin_map(entry_obj->obj, I915_MAP_WB);
1615         if (IS_ERR(dst)) {
1616                 ret = PTR_ERR(dst);
1617                 goto put_obj;
1618         }
1619
1620         ret = i915_gem_object_set_to_cpu_domain(entry_obj->obj, false);
1621         if (ret) {
1622                 gvt_err("failed to set shadow batch to CPU\n");
1623                 goto unmap_src;
1624         }
1625
1626         entry_obj->va = dst;
1627         entry_obj->bb_start_cmd_va = s->ip_va;
1628
1629         /* copy batch buffer to shadow batch buffer*/
1630         ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1631                               gma, gma + bb_size,
1632                               dst);
1633         if (ret) {
1634                 gvt_err("fail to copy guest ring buffer\n");
1635                 goto unmap_src;
1636         }
1637
1638         list_add(&entry_obj->list, &s->workload->shadow_bb);
1639         /*
1640          * ip_va saves the virtual address of the shadow batch buffer, while
1641          * ip_gma saves the graphics address of the original batch buffer.
1642          * As the shadow batch buffer is just a copy from the originial one,
1643          * it should be right to use shadow batch buffer'va and original batch
1644          * buffer's gma in pair. After all, we don't want to pin the shadow
1645          * buffer here (too early).
1646          */
1647         s->ip_va = dst;
1648         s->ip_gma = gma;
1649
1650         return 0;
1651
1652 unmap_src:
1653         i915_gem_object_unpin_map(entry_obj->obj);
1654 put_obj:
1655         i915_gem_object_put(entry_obj->obj);
1656 free_entry:
1657         kfree(entry_obj);
1658         return ret;
1659 }
1660
1661 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1662 {
1663         bool second_level;
1664         int ret = 0;
1665
1666         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1667                 gvt_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1668                 return -EINVAL;
1669         }
1670
1671         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1672         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1673                 gvt_err("Jumping to 2nd level BB from RB is not allowed\n");
1674                 return -EINVAL;
1675         }
1676
1677         s->saved_buf_addr_type = s->buf_addr_type;
1678         addr_type_update_snb(s);
1679         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1680                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1681                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1682         } else if (second_level) {
1683                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1684                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1685                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1686         }
1687
1688         if (batch_buffer_needs_scan(s)) {
1689                 ret = perform_bb_shadow(s);
1690                 if (ret < 0)
1691                         gvt_err("invalid shadow batch buffer\n");
1692         } else {
1693                 /* emulate a batch buffer end to do return right */
1694                 ret = cmd_handler_mi_batch_buffer_end(s);
1695                 if (ret < 0)
1696                         return ret;
1697         }
1698
1699         return ret;
1700 }
1701
1702 static struct cmd_info cmd_info[] = {
1703         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1704
1705         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1706                 0, 1, NULL},
1707
1708         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1709                 0, 1, cmd_handler_mi_user_interrupt},
1710
1711         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1712                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1713
1714         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1715
1716         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1717                 NULL},
1718
1719         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1720                 NULL},
1721
1722         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1723                 NULL},
1724
1725         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1726                 NULL},
1727
1728         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1729                 D_ALL, 0, 1, NULL},
1730
1731         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1732                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1733                 cmd_handler_mi_batch_buffer_end},
1734
1735         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1736                 0, 1, NULL},
1737
1738         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1739                 NULL},
1740
1741         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1742                 D_ALL, 0, 1, NULL},
1743
1744         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1745                 NULL},
1746
1747         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1748                 NULL},
1749
1750         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1751                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1752
1753         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1754                 0, 8, NULL},
1755
1756         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1757
1758         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1759
1760         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1761                 D_BDW_PLUS, 0, 8, NULL},
1762
1763         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1764                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1765
1766         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1767                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1768
1769         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1770                 0, 8, cmd_handler_mi_store_data_index},
1771
1772         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1773                 D_ALL, 0, 8, cmd_handler_lri},
1774
1775         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1776                 cmd_handler_mi_update_gtt},
1777
1778         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1779                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1780
1781         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1782                 cmd_handler_mi_flush_dw},
1783
1784         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1785                 10, cmd_handler_mi_clflush},
1786
1787         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1788                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1789
1790         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1791                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1792
1793         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1794                 D_ALL, 0, 8, cmd_handler_lrr},
1795
1796         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1797                 D_ALL, 0, 8, NULL},
1798
1799         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1800                 ADDR_FIX_1(2), 8, NULL},
1801
1802         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1803                 ADDR_FIX_1(2), 8, NULL},
1804
1805         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1806                 8, cmd_handler_mi_op_2e},
1807
1808         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1809                 8, cmd_handler_mi_op_2f},
1810
1811         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1812                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1813                 cmd_handler_mi_batch_buffer_start},
1814
1815         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1816                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1817                 cmd_handler_mi_conditional_batch_buffer_end},
1818
1819         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1820                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1821
1822         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1823                 ADDR_FIX_2(4, 7), 8, NULL},
1824
1825         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1826                 0, 8, NULL},
1827
1828         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1829                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1830
1831         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1832
1833         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1834                 0, 8, NULL},
1835
1836         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1837                 ADDR_FIX_1(3), 8, NULL},
1838
1839         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1840                 D_ALL, 0, 8, NULL},
1841
1842         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1843                 ADDR_FIX_1(4), 8, NULL},
1844
1845         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1846                 ADDR_FIX_2(4, 5), 8, NULL},
1847
1848         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1849                 ADDR_FIX_1(4), 8, NULL},
1850
1851         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1852                 ADDR_FIX_2(4, 7), 8, NULL},
1853
1854         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1855                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1856
1857         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1858
1859         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1860                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1861
1862         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1863                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1864
1865         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1866                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1867                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1868
1869         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1870                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1871
1872         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
1873                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1874
1875         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
1876                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1877
1878         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
1879                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1880
1881         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
1882                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1883
1884         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
1885                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
1886                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1887
1888         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
1889                 ADDR_FIX_2(4, 5), 8, NULL},
1890
1891         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
1892                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1893
1894         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
1895                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
1896                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1897
1898         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
1899                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
1900                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1901
1902         {"3DSTATE_BLEND_STATE_POINTERS",
1903                 OP_3DSTATE_BLEND_STATE_POINTERS,
1904                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1905
1906         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
1907                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
1908                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1909
1910         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
1911                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
1912                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1913
1914         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
1915                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
1916                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1917
1918         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
1919                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
1920                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1921
1922         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
1923                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
1924                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1925
1926         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
1927                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
1928                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1929
1930         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
1931                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
1932                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1933
1934         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
1935                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
1936                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1937
1938         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
1939                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
1940                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1941
1942         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
1943                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
1944                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1945
1946         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
1947                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
1948                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1949
1950         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
1951                 0, 8, NULL},
1952
1953         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
1954                 0, 8, NULL},
1955
1956         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
1957                 0, 8, NULL},
1958
1959         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
1960                 0, 8, NULL},
1961
1962         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
1963                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1964
1965         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
1966                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1967
1968         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
1969                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1970
1971         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
1972                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1973
1974         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
1975                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1976
1977         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
1978                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
1979
1980         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
1981                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
1982
1983         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
1984                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1985
1986         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
1987                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1988
1989         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
1990                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1991
1992         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
1993                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1994
1995         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
1996                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1997
1998         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
1999                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2000
2001         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2002                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2003
2004         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2005                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2006
2007         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2008                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2009
2010         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2011                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2012
2013         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2014                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2015
2016         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2017                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2018
2019         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2020                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2021
2022         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2023                 D_BDW_PLUS, 0, 8, NULL},
2024
2025         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2026                 NULL},
2027
2028         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2029                 D_BDW_PLUS, 0, 8, NULL},
2030
2031         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2032                 D_BDW_PLUS, 0, 8, NULL},
2033
2034         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2035                 8, NULL},
2036
2037         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2038                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2039
2040         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2041                 8, NULL},
2042
2043         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2044                 NULL},
2045
2046         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2047                 NULL},
2048
2049         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2050                 NULL},
2051
2052         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2053                 D_BDW_PLUS, 0, 8, NULL},
2054
2055         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2056                 R_RCS, D_ALL, 0, 8, NULL},
2057
2058         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2059                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2060
2061         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2062                 R_RCS, D_ALL, 0, 1, NULL},
2063
2064         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2065
2066         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2067                 R_RCS, D_ALL, 0, 8, NULL},
2068
2069         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2070                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2071
2072         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2073
2074         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2075
2076         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2077
2078         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2079                 D_BDW_PLUS, 0, 8, NULL},
2080
2081         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2082                 D_BDW_PLUS, 0, 8, NULL},
2083
2084         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2085                 D_ALL, 0, 8, NULL},
2086
2087         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2088                 D_BDW_PLUS, 0, 8, NULL},
2089
2090         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2091                 D_BDW_PLUS, 0, 8, NULL},
2092
2093         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2094
2095         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2096
2097         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2098
2099         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2100                 D_ALL, 0, 8, NULL},
2101
2102         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2103
2104         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2105
2106         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2107                 R_RCS, D_ALL, 0, 8, NULL},
2108
2109         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2110                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2111
2112         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2113                 0, 8, NULL},
2114
2115         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2116                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2117
2118         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2119                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2120
2121         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2122                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2123
2124         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2125                 D_ALL, 0, 8, NULL},
2126
2127         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2128                 D_ALL, 0, 8, NULL},
2129
2130         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2131                 D_ALL, 0, 8, NULL},
2132
2133         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2134                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2135
2136         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2137                 D_BDW_PLUS, 0, 8, NULL},
2138
2139         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2140                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2141
2142         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2143                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2144
2145         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2146                 R_RCS, D_ALL, 0, 8, NULL},
2147
2148         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2149                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2150
2151         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2152                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2153
2154         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2155                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2156
2157         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2158                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2159
2160         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2161                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2162
2163         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2164                 R_RCS, D_ALL, 0, 8, NULL},
2165
2166         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2167                 D_ALL, 0, 9, NULL},
2168
2169         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2170                 ADDR_FIX_2(2, 4), 8, NULL},
2171
2172         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2173                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2174                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2175
2176         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2177                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2178
2179         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2180                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2181                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2182
2183         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2184                 D_BDW_PLUS, 0, 8, NULL},
2185
2186         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2187                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2188
2189         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2190
2191         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2192                 1, NULL},
2193
2194         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2195                 ADDR_FIX_1(1), 8, NULL},
2196
2197         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2198
2199         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2200                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2201
2202         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2203                 ADDR_FIX_1(1), 8, NULL},
2204
2205         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2206
2207         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2208
2209         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2210                 0, 8, NULL},
2211
2212         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2213                 D_SKL_PLUS, 0, 8, NULL},
2214
2215         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2216                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2217
2218         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2219                 0, 16, NULL},
2220
2221         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2222                 0, 16, NULL},
2223
2224         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2225
2226         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2227                 0, 16, NULL},
2228
2229         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2230                 0, 16, NULL},
2231
2232         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2233                 0, 16, NULL},
2234
2235         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2236                 0, 8, NULL},
2237
2238         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2239                 NULL},
2240
2241         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2242                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2243
2244         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2245                 R_VCS, D_ALL, 0, 12, NULL},
2246
2247         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2248                 R_VCS, D_ALL, 0, 12, NULL},
2249
2250         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2251                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2252
2253         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2254                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2255
2256         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2257                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2258
2259         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2260
2261         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2262                 R_VCS, D_ALL, 0, 12, NULL},
2263
2264         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2265                 R_VCS, D_ALL, 0, 12, NULL},
2266
2267         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2268                 R_VCS, D_ALL, 0, 12, NULL},
2269
2270         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2271                 R_VCS, D_ALL, 0, 12, NULL},
2272
2273         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2274                 R_VCS, D_ALL, 0, 12, NULL},
2275
2276         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2277                 R_VCS, D_ALL, 0, 12, NULL},
2278
2279         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2280                 R_VCS, D_ALL, 0, 6, NULL},
2281
2282         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2283                 R_VCS, D_ALL, 0, 12, NULL},
2284
2285         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2286                 R_VCS, D_ALL, 0, 12, NULL},
2287
2288         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2289                 R_VCS, D_ALL, 0, 12, NULL},
2290
2291         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2292                 R_VCS, D_ALL, 0, 12, NULL},
2293
2294         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2295                 R_VCS, D_ALL, 0, 12, NULL},
2296
2297         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2298                 R_VCS, D_ALL, 0, 12, NULL},
2299
2300         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2301                 R_VCS, D_ALL, 0, 12, NULL},
2302         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2303                 R_VCS, D_ALL, 0, 12, NULL},
2304
2305         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2306                 R_VCS, D_ALL, 0, 12, NULL},
2307
2308         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2309                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2310
2311         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2312                 R_VCS, D_ALL, 0, 12, NULL},
2313
2314         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2315                 R_VCS, D_ALL, 0, 12, NULL},
2316
2317         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2318                 R_VCS, D_ALL, 0, 12, NULL},
2319
2320         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2321                 R_VCS, D_ALL, 0, 12, NULL},
2322
2323         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2324                 R_VCS, D_ALL, 0, 12, NULL},
2325
2326         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2327                 R_VCS, D_ALL, 0, 12, NULL},
2328
2329         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2330                 R_VCS, D_ALL, 0, 12, NULL},
2331
2332         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2333                 R_VCS, D_ALL, 0, 12, NULL},
2334
2335         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2336                 R_VCS, D_ALL, 0, 12, NULL},
2337
2338         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2339                 R_VCS, D_ALL, 0, 12, NULL},
2340
2341         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2342                 R_VCS, D_ALL, 0, 12, NULL},
2343
2344         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2345                 0, 16, NULL},
2346
2347         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2348
2349         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2350
2351         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2352                 R_VCS, D_ALL, 0, 12, NULL},
2353
2354         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2355                 R_VCS, D_ALL, 0, 12, NULL},
2356
2357         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2358                 R_VCS, D_ALL, 0, 12, NULL},
2359
2360         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2361
2362         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2363                 0, 12, NULL},
2364
2365         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2366                 0, 20, NULL},
2367 };
2368
2369 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2370 {
2371         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2372 }
2373
2374 #define GVT_MAX_CMD_LENGTH     20  /* In Dword */
2375
2376 static void trace_cs_command(struct parser_exec_state *s,
2377                 cycles_t cost_pre_cmd_handler, cycles_t cost_cmd_handler)
2378 {
2379         /* This buffer is used by ftrace to store all commands copied from
2380          * guest gma space. Sometimes commands can cross pages, this should
2381          * not be handled in ftrace logic. So this is just used as a
2382          * 'bounce buffer'
2383          */
2384         u32 cmd_trace_buf[GVT_MAX_CMD_LENGTH];
2385         int i;
2386         u32 cmd_len = cmd_length(s);
2387         /* The chosen value of GVT_MAX_CMD_LENGTH are just based on
2388          * following two considerations:
2389          * 1) From observation, most common ring commands is not that long.
2390          *    But there are execeptions. So it indeed makes sence to observe
2391          *    longer commands.
2392          * 2) From the performance and debugging point of view, dumping all
2393          *    contents of very commands is not necessary.
2394          * We mgith shrink GVT_MAX_CMD_LENGTH or remove this trace event in
2395          * future for performance considerations.
2396          */
2397         if (unlikely(cmd_len > GVT_MAX_CMD_LENGTH)) {
2398                 gvt_dbg_cmd("cmd length exceed tracing limitation!\n");
2399                 cmd_len = GVT_MAX_CMD_LENGTH;
2400         }
2401
2402         for (i = 0; i < cmd_len; i++)
2403                 cmd_trace_buf[i] = cmd_val(s, i);
2404
2405         trace_gvt_command(s->vgpu->id, s->ring_id, s->ip_gma, cmd_trace_buf,
2406                         cmd_len, s->buf_type == RING_BUFFER_INSTRUCTION,
2407                         cost_pre_cmd_handler, cost_cmd_handler);
2408 }
2409
2410 /* call the cmd handler, and advance ip */
2411 static int cmd_parser_exec(struct parser_exec_state *s)
2412 {
2413         struct cmd_info *info;
2414         u32 cmd;
2415         int ret = 0;
2416         cycles_t t0, t1, t2;
2417         struct parser_exec_state s_before_advance_custom;
2418
2419         t0 = get_cycles();
2420
2421         cmd = cmd_val(s, 0);
2422
2423         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2424         if (info == NULL) {
2425                 gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
2426                                 cmd, get_opcode(cmd, s->ring_id));
2427                 return -EINVAL;
2428         }
2429
2430         gvt_dbg_cmd("%s\n", info->name);
2431
2432         s->info = info;
2433
2434         t1 = get_cycles();
2435
2436         memcpy(&s_before_advance_custom, s, sizeof(struct parser_exec_state));
2437
2438         if (info->handler) {
2439                 ret = info->handler(s);
2440                 if (ret < 0) {
2441                         gvt_err("%s handler error\n", info->name);
2442                         return ret;
2443                 }
2444         }
2445         t2 = get_cycles();
2446
2447         trace_cs_command(&s_before_advance_custom, t1 - t0, t2 - t1);
2448
2449         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2450                 ret = cmd_advance_default(s);
2451                 if (ret) {
2452                         gvt_err("%s IP advance error\n", info->name);
2453                         return ret;
2454                 }
2455         }
2456         return 0;
2457 }
2458
2459 static inline bool gma_out_of_range(unsigned long gma,
2460                 unsigned long gma_head, unsigned int gma_tail)
2461 {
2462         if (gma_tail >= gma_head)
2463                 return (gma < gma_head) || (gma > gma_tail);
2464         else
2465                 return (gma > gma_tail) && (gma < gma_head);
2466 }
2467
2468 static int command_scan(struct parser_exec_state *s,
2469                 unsigned long rb_head, unsigned long rb_tail,
2470                 unsigned long rb_start, unsigned long rb_len)
2471 {
2472
2473         unsigned long gma_head, gma_tail, gma_bottom;
2474         int ret = 0;
2475
2476         gma_head = rb_start + rb_head;
2477         gma_tail = rb_start + rb_tail;
2478         gma_bottom = rb_start +  rb_len;
2479
2480         gvt_dbg_cmd("scan_start: start=%lx end=%lx\n", gma_head, gma_tail);
2481
2482         while (s->ip_gma != gma_tail) {
2483                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2484                         if (!(s->ip_gma >= rb_start) ||
2485                                 !(s->ip_gma < gma_bottom)) {
2486                                 gvt_err("ip_gma %lx out of ring scope."
2487                                         "(base:0x%lx, bottom: 0x%lx)\n",
2488                                         s->ip_gma, rb_start,
2489                                         gma_bottom);
2490                                 parser_exec_state_dump(s);
2491                                 return -EINVAL;
2492                         }
2493                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2494                                 gvt_err("ip_gma %lx out of range."
2495                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2496                                         s->ip_gma, rb_start,
2497                                         rb_head, rb_tail);
2498                                 parser_exec_state_dump(s);
2499                                 break;
2500                         }
2501                 }
2502                 ret = cmd_parser_exec(s);
2503                 if (ret) {
2504                         gvt_err("cmd parser error\n");
2505                         parser_exec_state_dump(s);
2506                         break;
2507                 }
2508         }
2509
2510         gvt_dbg_cmd("scan_end\n");
2511
2512         return ret;
2513 }
2514
2515 static int scan_workload(struct intel_vgpu_workload *workload)
2516 {
2517         unsigned long gma_head, gma_tail, gma_bottom;
2518         struct parser_exec_state s;
2519         int ret = 0;
2520
2521         /* ring base is page aligned */
2522         if (WARN_ON(!IS_ALIGNED(workload->rb_start, GTT_PAGE_SIZE)))
2523                 return -EINVAL;
2524
2525         gma_head = workload->rb_start + workload->rb_head;
2526         gma_tail = workload->rb_start + workload->rb_tail;
2527         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2528
2529         s.buf_type = RING_BUFFER_INSTRUCTION;
2530         s.buf_addr_type = GTT_BUFFER;
2531         s.vgpu = workload->vgpu;
2532         s.ring_id = workload->ring_id;
2533         s.ring_start = workload->rb_start;
2534         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2535         s.ring_head = gma_head;
2536         s.ring_tail = gma_tail;
2537         s.rb_va = workload->shadow_ring_buffer_va;
2538         s.workload = workload;
2539
2540         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2541                 gma_head == gma_tail)
2542                 return 0;
2543
2544         ret = ip_gma_set(&s, gma_head);
2545         if (ret)
2546                 goto out;
2547
2548         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2549                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2550
2551 out:
2552         return ret;
2553 }
2554
2555 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2556 {
2557
2558         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2559         struct parser_exec_state s;
2560         int ret = 0;
2561
2562         /* ring base is page aligned */
2563         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, GTT_PAGE_SIZE)))
2564                 return -EINVAL;
2565
2566         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2567         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2568                         PAGE_SIZE);
2569         gma_head = wa_ctx->indirect_ctx.guest_gma;
2570         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2571         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2572
2573         s.buf_type = RING_BUFFER_INSTRUCTION;
2574         s.buf_addr_type = GTT_BUFFER;
2575         s.vgpu = wa_ctx->workload->vgpu;
2576         s.ring_id = wa_ctx->workload->ring_id;
2577         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2578         s.ring_size = ring_size;
2579         s.ring_head = gma_head;
2580         s.ring_tail = gma_tail;
2581         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2582         s.workload = wa_ctx->workload;
2583
2584         ret = ip_gma_set(&s, gma_head);
2585         if (ret)
2586                 goto out;
2587
2588         ret = command_scan(&s, 0, ring_tail,
2589                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2590 out:
2591         return ret;
2592 }
2593
2594 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2595 {
2596         struct intel_vgpu *vgpu = workload->vgpu;
2597         int ring_id = workload->ring_id;
2598         struct i915_gem_context *shadow_ctx = vgpu->shadow_ctx;
2599         struct intel_ring *ring = shadow_ctx->engine[ring_id].ring;
2600         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2601         unsigned int copy_len = 0;
2602         int ret;
2603
2604         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2605
2606         /* calculate workload ring buffer size */
2607         workload->rb_len = (workload->rb_tail + guest_rb_size -
2608                         workload->rb_head) % guest_rb_size;
2609
2610         gma_head = workload->rb_start + workload->rb_head;
2611         gma_tail = workload->rb_start + workload->rb_tail;
2612         gma_top = workload->rb_start + guest_rb_size;
2613
2614         /* allocate shadow ring buffer */
2615         ret = intel_ring_begin(workload->req, workload->rb_len / 4);
2616         if (ret)
2617                 return ret;
2618
2619         /* get shadow ring buffer va */
2620         workload->shadow_ring_buffer_va = ring->vaddr + ring->tail;
2621
2622         /* head > tail --> copy head <-> top */
2623         if (gma_head > gma_tail) {
2624                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2625                                 gma_head, gma_top,
2626                                 workload->shadow_ring_buffer_va);
2627                 if (ret) {
2628                         gvt_err("fail to copy guest ring buffer\n");
2629                         return ret;
2630                 }
2631                 copy_len = gma_top - gma_head;
2632                 gma_head = workload->rb_start;
2633         }
2634
2635         /* copy head or start <-> tail */
2636         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2637                         gma_head, gma_tail,
2638                         workload->shadow_ring_buffer_va + copy_len);
2639         if (ret) {
2640                 gvt_err("fail to copy guest ring buffer\n");
2641                 return ret;
2642         }
2643         ring->tail += workload->rb_len;
2644         intel_ring_advance(ring);
2645         return 0;
2646 }
2647
2648 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
2649 {
2650         int ret;
2651
2652         ret = shadow_workload_ring_buffer(workload);
2653         if (ret) {
2654                 gvt_err("fail to shadow workload ring_buffer\n");
2655                 return ret;
2656         }
2657
2658         ret = scan_workload(workload);
2659         if (ret) {
2660                 gvt_err("scan workload error\n");
2661                 return ret;
2662         }
2663         return 0;
2664 }
2665
2666 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2667 {
2668         struct drm_device *dev = &wa_ctx->workload->vgpu->gvt->dev_priv->drm;
2669         int ctx_size = wa_ctx->indirect_ctx.size;
2670         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2671         struct drm_i915_gem_object *obj;
2672         int ret = 0;
2673         void *map;
2674
2675         obj = i915_gem_object_create(dev,
2676                                      roundup(ctx_size + CACHELINE_BYTES,
2677                                              PAGE_SIZE));
2678         if (IS_ERR(obj))
2679                 return PTR_ERR(obj);
2680
2681         /* get the va of the shadow batch buffer */
2682         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2683         if (IS_ERR(map)) {
2684                 gvt_err("failed to vmap shadow indirect ctx\n");
2685                 ret = PTR_ERR(map);
2686                 goto put_obj;
2687         }
2688
2689         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2690         if (ret) {
2691                 gvt_err("failed to set shadow indirect ctx to CPU\n");
2692                 goto unmap_src;
2693         }
2694
2695         ret = copy_gma_to_hva(wa_ctx->workload->vgpu,
2696                                 wa_ctx->workload->vgpu->gtt.ggtt_mm,
2697                                 guest_gma, guest_gma + ctx_size,
2698                                 map);
2699         if (ret) {
2700                 gvt_err("fail to copy guest indirect ctx\n");
2701                 goto unmap_src;
2702         }
2703
2704         wa_ctx->indirect_ctx.obj = obj;
2705         wa_ctx->indirect_ctx.shadow_va = map;
2706         return 0;
2707
2708 unmap_src:
2709         i915_gem_object_unpin_map(obj);
2710 put_obj:
2711         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
2712         return ret;
2713 }
2714
2715 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2716 {
2717         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2718         unsigned char *bb_start_sva;
2719
2720         per_ctx_start[0] = 0x18800001;
2721         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2722
2723         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2724                                 wa_ctx->indirect_ctx.size;
2725
2726         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2727
2728         return 0;
2729 }
2730
2731 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2732 {
2733         int ret;
2734
2735         if (wa_ctx->indirect_ctx.size == 0)
2736                 return 0;
2737
2738         ret = shadow_indirect_ctx(wa_ctx);
2739         if (ret) {
2740                 gvt_err("fail to shadow indirect ctx\n");
2741                 return ret;
2742         }
2743
2744         combine_wa_ctx(wa_ctx);
2745
2746         ret = scan_wa_ctx(wa_ctx);
2747         if (ret) {
2748                 gvt_err("scan wa ctx error\n");
2749                 return ret;
2750         }
2751
2752         return 0;
2753 }
2754
2755 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2756                 unsigned int opcode, int rings)
2757 {
2758         struct cmd_info *info = NULL;
2759         unsigned int ring;
2760
2761         for_each_set_bit(ring, (unsigned long *)&rings, I915_NUM_ENGINES) {
2762                 info = find_cmd_entry(gvt, opcode, ring);
2763                 if (info)
2764                         break;
2765         }
2766         return info;
2767 }
2768
2769 static int init_cmd_table(struct intel_gvt *gvt)
2770 {
2771         int i;
2772         struct cmd_entry *e;
2773         struct cmd_info *info;
2774         unsigned int gen_type;
2775
2776         gen_type = intel_gvt_get_device_type(gvt);
2777
2778         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2779                 if (!(cmd_info[i].devices & gen_type))
2780                         continue;
2781
2782                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2783                 if (!e)
2784                         return -ENOMEM;
2785
2786                 e->info = &cmd_info[i];
2787                 info = find_cmd_entry_any_ring(gvt,
2788                                 e->info->opcode, e->info->rings);
2789                 if (info) {
2790                         gvt_err("%s %s duplicated\n", e->info->name,
2791                                         info->name);
2792                         return -EEXIST;
2793                 }
2794
2795                 INIT_HLIST_NODE(&e->hlist);
2796                 add_cmd_entry(gvt, e);
2797                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2798                                 e->info->name, e->info->opcode, e->info->flag,
2799                                 e->info->devices, e->info->rings);
2800         }
2801         return 0;
2802 }
2803
2804 static void clean_cmd_table(struct intel_gvt *gvt)
2805 {
2806         struct hlist_node *tmp;
2807         struct cmd_entry *e;
2808         int i;
2809
2810         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2811                 kfree(e);
2812
2813         hash_init(gvt->cmd_table);
2814 }
2815
2816 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2817 {
2818         clean_cmd_table(gvt);
2819 }
2820
2821 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2822 {
2823         int ret;
2824
2825         ret = init_cmd_table(gvt);
2826         if (ret) {
2827                 intel_gvt_clean_cmd_parser(gvt);
2828                 return ret;
2829         }
2830         return 0;
2831 }