2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Kevin Tian <kevin.tian@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
29 * Min He <min.he@intel.com>
30 * Ping Gao <ping.a.gao@intel.com>
31 * Tina Zhang <tina.zhang@intel.com>
32 * Yulei Zhang <yulei.zhang@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
37 #include <linux/slab.h>
40 #include "i915_pvinfo.h"
43 #define INVALID_OP (~0U)
47 #define OP_LEN_3D_MEDIA 16
48 #define OP_LEN_MFX_VC 16
49 #define OP_LEN_VEBOX 16
51 #define CMD_TYPE(cmd) (((cmd) >> 29) & 7)
61 struct sub_op_bits *sub_op;
64 #define MAX_CMD_BUDGET 0x7fffffff
65 #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
66 #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
67 #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
69 #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
70 #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
71 #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
73 /* Render Command Map */
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP 0x0
77 #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
78 #define OP_MI_USER_INTERRUPT 0x2
79 #define OP_MI_WAIT_FOR_EVENT 0x3
80 #define OP_MI_FLUSH 0x4
81 #define OP_MI_ARB_CHECK 0x5
82 #define OP_MI_RS_CONTROL 0x6 /* HSW+ */
83 #define OP_MI_REPORT_HEAD 0x7
84 #define OP_MI_ARB_ON_OFF 0x8
85 #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END 0xA
87 #define OP_MI_SUSPEND_FLUSH 0xB
88 #define OP_MI_PREDICATE 0xC /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
90 #define OP_MI_SET_APPID 0xE /* IVB+ */
91 #define OP_MI_RS_CONTEXT 0xF /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP 0x14
94 #define OP_MI_SEMAPHORE_MBOX 0x16
95 #define OP_MI_SET_CONTEXT 0x18
96 #define OP_MI_MATH 0x1A
97 #define OP_MI_URB_CLEAR 0x19
98 #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
101 #define OP_MI_STORE_DATA_IMM 0x20
102 #define OP_MI_STORE_DATA_INDEX 0x21
103 #define OP_MI_LOAD_REGISTER_IMM 0x22
104 #define OP_MI_UPDATE_GTT 0x23
105 #define OP_MI_STORE_REGISTER_MEM 0x24
106 #define OP_MI_FLUSH_DW 0x26
107 #define OP_MI_CLFLUSH 0x27
108 #define OP_MI_REPORT_PERF_COUNT 0x28
109 #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
113 #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
114 #define OP_MI_2E 0x2E /* BDW+ */
115 #define OP_MI_2F 0x2F /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START 0x31
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x) ((2<<7) | x)
131 #define OP_XY_SETUP_BLT OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT OP_2D(0x25)
136 #define OP_XY_TEXT_BLT OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
138 #define OP_XY_COLOR_BLT OP_2D(0x50)
139 #define OP_XY_PAT_BLT OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
143 #define OP_XY_FULL_BLT OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77)
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158 ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
160 #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03)
162 #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04)
166 #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B)
168 #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04)
170 #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4)
176 #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0)
177 #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2)
178 #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3)
179 #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5)
181 #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
182 #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
183 #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
184 #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
185 #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08)
186 #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09)
187 #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A)
188 #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B)
189 #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */
190 #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E)
191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F)
192 #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10)
193 #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11)
194 #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12)
195 #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13)
196 #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14)
197 #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15)
198 #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16)
199 #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17)
200 #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18)
201 #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
202 #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
203 #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
204 #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
205 #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
206 #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
207 #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
208 #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
211 #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
223 #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
224 #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
225 #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
226 #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
227 #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
232 #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
248 #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
249 #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
250 #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
251 #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
252 #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
253 #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
254 #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
255 #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
256 #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
257 #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
258 #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
260 #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02)
262 #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04)
263 #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05)
264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06)
265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07)
266 #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08)
267 #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A)
268 #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B)
269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C)
270 #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D)
271 #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E)
272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F)
273 #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10)
274 #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11)
275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
280 #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17)
281 #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18)
282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
283 #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
285 #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C)
286 #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00)
287 #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00)
289 /* VCCP Command Parser */
292 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
293 * git://anongit.freedesktop.org/vaapi/intel-driver
298 #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
305 #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */
306 #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */
307 #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */
308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */
309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */
310 #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */
311 #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */
312 #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */
313 #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */
314 #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */
315 #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */
317 #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */
319 #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */
320 #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */
321 #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */
322 #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */
323 #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */
324 #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */
325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */
326 #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */
327 #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */
328 #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */
329 #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */
330 #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */
332 #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */
333 #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */
334 #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */
335 #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */
336 #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */
338 #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */
339 #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */
340 #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */
341 #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */
342 #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */
344 #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */
345 #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */
346 #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */
348 #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0)
349 #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2)
350 #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8)
352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
359 #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0)
360 #define OP_VEB_STATE OP_VEB(2, 4, 0, 2)
361 #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3)
363 struct parser_exec_state;
365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
367 #define GVT_CMD_HASH_BITS 7
369 /* which DWords need address fix */
370 #define ADDR_FIX_1(x1) (1 << (x1))
371 #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
372 #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
373 #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
374 #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
380 #define F_LEN_MASK (1U<<0)
381 #define F_LEN_CONST 1U
385 * command has its own ip advance logic
386 * e.g. MI_BATCH_START, MI_BATCH_END
388 #define F_IP_ADVANCE_CUSTOM (1<<1)
390 #define F_POST_HANDLE (1<<2)
393 #define R_RCS (1 << RCS)
394 #define R_VCS1 (1 << VCS)
395 #define R_VCS2 (1 << VCS2)
396 #define R_VCS (R_VCS1 | R_VCS2)
397 #define R_BCS (1 << BCS)
398 #define R_VECS (1 << VECS)
399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
400 /* rings that support this cmd: BLT/RCS/VCS/VECS */
403 /* devices that support this cmd: SNB/IVB/HSW/... */
406 /* which DWords are address that need fix up.
407 * bit 0 means a 32-bit non address operand in command
408 * bit 1 means address operand, which could be 32-bit
409 * or 64-bit depending on different architectures.(
410 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
411 * No matter the address length, each address only takes
412 * one bit in the bitmap.
414 uint16_t addr_bitmap;
416 /* flag == F_LEN_CONST : command length
417 * flag == F_LEN_VAR : length bias bits
418 * Note: length is in DWord
422 parser_cmd_handler handler;
426 struct hlist_node hlist;
427 struct cmd_info *info;
431 RING_BUFFER_INSTRUCTION,
432 BATCH_BUFFER_INSTRUCTION,
433 BATCH_BUFFER_2ND_LEVEL,
441 struct parser_exec_state {
442 struct intel_vgpu *vgpu;
447 /* batch buffer address type */
450 /* graphics memory address of ring buffer start */
451 unsigned long ring_start;
452 unsigned long ring_size;
453 unsigned long ring_head;
454 unsigned long ring_tail;
456 /* instruction graphics memory address */
457 unsigned long ip_gma;
459 /* mapped va of the instr_gma */
464 /* next instruction when return from batch buffer to ring buffer */
465 unsigned long ret_ip_gma_ring;
467 /* next instruction when return from 2nd batch buffer to batch buffer */
468 unsigned long ret_ip_gma_bb;
470 /* batch buffer address type (GTT or PPGTT)
471 * used when ret from 2nd level batch buffer
473 int saved_buf_addr_type;
475 struct cmd_info *info;
477 struct intel_vgpu_workload *workload;
480 #define gmadr_dw_number(s) \
481 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
483 static unsigned long bypass_scan_mask = 0;
485 /* ring ALL, type = 0 */
486 static struct sub_op_bits sub_op_mi[] = {
491 static struct decode_info decode_info_mi = {
494 ARRAY_SIZE(sub_op_mi),
498 /* ring RCS, command type 2 */
499 static struct sub_op_bits sub_op_2d[] = {
504 static struct decode_info decode_info_2d = {
507 ARRAY_SIZE(sub_op_2d),
511 /* ring RCS, command type 3 */
512 static struct sub_op_bits sub_op_3d_media[] = {
519 static struct decode_info decode_info_3d_media = {
522 ARRAY_SIZE(sub_op_3d_media),
526 /* ring VCS, command type 3 */
527 static struct sub_op_bits sub_op_mfx_vc[] = {
535 static struct decode_info decode_info_mfx_vc = {
538 ARRAY_SIZE(sub_op_mfx_vc),
542 /* ring VECS, command type 3 */
543 static struct sub_op_bits sub_op_vebox[] = {
551 static struct decode_info decode_info_vebox = {
554 ARRAY_SIZE(sub_op_vebox),
558 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
563 &decode_info_3d_media,
615 static inline u32 get_opcode(u32 cmd, int ring_id)
617 struct decode_info *d_info;
619 d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
623 return cmd >> (32 - d_info->op_len);
626 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
627 unsigned int opcode, int ring_id)
631 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
632 if ((opcode == e->info->opcode) &&
633 (e->info->rings & (1 << ring_id)))
639 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
640 u32 cmd, int ring_id)
644 opcode = get_opcode(cmd, ring_id);
645 if (opcode == INVALID_OP)
648 return find_cmd_entry(gvt, opcode, ring_id);
651 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
653 return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
656 static inline void print_opcode(u32 cmd, int ring_id)
658 struct decode_info *d_info;
661 d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
665 gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
666 cmd >> (32 - d_info->op_len), d_info->name);
668 for (i = 0; i < d_info->nr_sub_op; i++)
669 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
670 d_info->sub_op[i].low));
675 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
677 return s->ip_va + (index << 2);
680 static inline u32 cmd_val(struct parser_exec_state *s, int index)
682 return *cmd_ptr(s, index);
685 static void parser_exec_state_dump(struct parser_exec_state *s)
690 gvt_dbg_cmd(" vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
691 " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
692 s->ring_id, s->ring_start, s->ring_start + s->ring_size,
693 s->ring_head, s->ring_tail);
695 gvt_dbg_cmd(" %s %s ip_gma(%08lx) ",
696 s->buf_type == RING_BUFFER_INSTRUCTION ?
697 "RING_BUFFER" : "BATCH_BUFFER",
698 s->buf_addr_type == GTT_BUFFER ?
699 "GTT" : "PPGTT", s->ip_gma);
701 if (s->ip_va == NULL) {
702 gvt_dbg_cmd(" ip_va(NULL)");
706 gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n",
707 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
708 cmd_val(s, 2), cmd_val(s, 3));
710 print_opcode(cmd_val(s, 0), s->ring_id);
712 /* print the whole page to trace */
713 pr_err(" ip_va=%p: %08x %08x %08x %08x\n",
714 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
715 cmd_val(s, 2), cmd_val(s, 3));
717 s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
720 pr_err("ip_va=%p: ", s->ip_va);
721 for (i = 0; i < 8; i++)
722 pr_err("%08x ", cmd_val(s, i));
725 s->ip_va += 8 * sizeof(u32);
730 static inline void update_ip_va(struct parser_exec_state *s)
732 unsigned long len = 0;
734 if (WARN_ON(s->ring_head == s->ring_tail))
737 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
738 unsigned long ring_top = s->ring_start + s->ring_size;
740 if (s->ring_head > s->ring_tail) {
741 if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
742 len = (s->ip_gma - s->ring_head);
743 else if (s->ip_gma >= s->ring_start &&
744 s->ip_gma <= s->ring_tail)
745 len = (ring_top - s->ring_head) +
746 (s->ip_gma - s->ring_start);
748 len = (s->ip_gma - s->ring_head);
750 s->ip_va = s->rb_va + len;
751 } else {/* shadow batch buffer */
752 s->ip_va = s->ret_bb_va;
756 static inline int ip_gma_set(struct parser_exec_state *s,
757 unsigned long ip_gma)
759 WARN_ON(!IS_ALIGNED(ip_gma, 4));
766 static inline int ip_gma_advance(struct parser_exec_state *s,
769 s->ip_gma += (dw_len << 2);
771 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
772 if (s->ip_gma >= s->ring_start + s->ring_size)
773 s->ip_gma -= s->ring_size;
776 s->ip_va += (dw_len << 2);
782 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
784 if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
787 return (cmd & ((1U << info->len) - 1)) + 2;
791 static inline int cmd_length(struct parser_exec_state *s)
793 return get_cmd_length(s->info, cmd_val(s, 0));
796 /* do not remove this, some platform may need clflush here */
797 #define patch_value(s, addr, val) do { \
801 static bool is_shadowed_mmio(unsigned int offset)
805 if ((offset == 0x2168) || /*BB current head register UDW */
806 (offset == 0x2140) || /*BB current header register */
807 (offset == 0x211c) || /*second BB header register UDW */
808 (offset == 0x2114)) { /*second BB header register UDW */
814 static inline bool is_force_nonpriv_mmio(unsigned int offset)
816 return (offset >= 0x24d0 && offset < 0x2500);
819 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
820 unsigned int offset, unsigned int index)
822 struct intel_gvt *gvt = s->vgpu->gvt;
823 unsigned int data = cmd_val(s, index + 1);
825 if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
826 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
833 static int cmd_reg_handler(struct parser_exec_state *s,
834 unsigned int offset, unsigned int index, char *cmd)
836 struct intel_vgpu *vgpu = s->vgpu;
837 struct intel_gvt *gvt = vgpu->gvt;
839 if (offset + 4 > gvt->device_info.mmio_size) {
840 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
845 if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
846 gvt_vgpu_err("%s access to non-render register (%x)\n",
851 if (is_shadowed_mmio(offset)) {
852 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
856 if (is_force_nonpriv_mmio(offset) &&
857 force_nonpriv_reg_handler(s, offset, index))
860 if (offset == i915_mmio_reg_offset(DERRMR) ||
861 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
862 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
863 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
866 /* TODO: Update the global mask if this MMIO is a masked-MMIO */
867 intel_gvt_mmio_set_cmd_accessed(gvt, offset);
871 #define cmd_reg(s, i) \
872 (cmd_val(s, i) & GENMASK(22, 2))
874 #define cmd_reg_inhibit(s, i) \
875 (cmd_val(s, i) & GENMASK(22, 18))
877 #define cmd_gma(s, i) \
878 (cmd_val(s, i) & GENMASK(31, 2))
880 #define cmd_gma_hi(s, i) \
881 (cmd_val(s, i) & GENMASK(15, 0))
883 static int cmd_handler_lri(struct parser_exec_state *s)
886 int cmd_len = cmd_length(s);
887 struct intel_gvt *gvt = s->vgpu->gvt;
889 for (i = 1; i < cmd_len; i += 2) {
890 if (IS_BROADWELL(gvt->dev_priv) &&
891 (s->ring_id != RCS)) {
892 if (s->ring_id == BCS &&
894 i915_mmio_reg_offset(DERRMR))
897 ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0;
901 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
906 static int cmd_handler_lrr(struct parser_exec_state *s)
909 int cmd_len = cmd_length(s);
911 for (i = 1; i < cmd_len; i += 2) {
912 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
913 ret |= ((cmd_reg_inhibit(s, i) ||
914 (cmd_reg_inhibit(s, i + 1)))) ?
918 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
919 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
924 static inline int cmd_address_audit(struct parser_exec_state *s,
925 unsigned long guest_gma, int op_size, bool index_mode);
927 static int cmd_handler_lrm(struct parser_exec_state *s)
929 struct intel_gvt *gvt = s->vgpu->gvt;
930 int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
933 int cmd_len = cmd_length(s);
935 for (i = 1; i < cmd_len;) {
936 if (IS_BROADWELL(gvt->dev_priv))
937 ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0;
940 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
941 if (cmd_val(s, 0) & (1 << 22)) {
942 gma = cmd_gma(s, i + 1);
943 if (gmadr_bytes == 8)
944 gma |= (cmd_gma_hi(s, i + 2)) << 32;
945 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
947 i += gmadr_dw_number(s) + 1;
952 static int cmd_handler_srm(struct parser_exec_state *s)
954 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
957 int cmd_len = cmd_length(s);
959 for (i = 1; i < cmd_len;) {
960 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
961 if (cmd_val(s, 0) & (1 << 22)) {
962 gma = cmd_gma(s, i + 1);
963 if (gmadr_bytes == 8)
964 gma |= (cmd_gma_hi(s, i + 2)) << 32;
965 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
967 i += gmadr_dw_number(s) + 1;
972 struct cmd_interrupt_event {
973 int pipe_control_notify;
975 int mi_user_interrupt;
978 static struct cmd_interrupt_event cmd_interrupt_events[] = {
980 .pipe_control_notify = RCS_PIPE_CONTROL,
981 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
982 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
985 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
986 .mi_flush_dw = BCS_MI_FLUSH_DW,
987 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
990 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
991 .mi_flush_dw = VCS_MI_FLUSH_DW,
992 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
995 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
996 .mi_flush_dw = VCS2_MI_FLUSH_DW,
997 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1000 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1001 .mi_flush_dw = VECS_MI_FLUSH_DW,
1002 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1006 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1008 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1010 bool index_mode = false;
1011 unsigned int post_sync;
1014 post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1017 if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1018 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1020 else if (post_sync) {
1022 ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1023 else if (post_sync == 3)
1024 ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1025 else if (post_sync == 1) {
1027 if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1028 gma = cmd_val(s, 2) & GENMASK(31, 3);
1029 if (gmadr_bytes == 8)
1030 gma |= (cmd_gma_hi(s, 3)) << 32;
1031 /* Store Data Index */
1032 if (cmd_val(s, 1) & (1 << 21))
1034 ret |= cmd_address_audit(s, gma, sizeof(u64),
1043 if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1044 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1045 s->workload->pending_events);
1049 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1051 set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1052 s->workload->pending_events);
1056 static int cmd_advance_default(struct parser_exec_state *s)
1058 return ip_gma_advance(s, cmd_length(s));
1061 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1065 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1066 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1067 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1068 s->buf_addr_type = s->saved_buf_addr_type;
1070 s->buf_type = RING_BUFFER_INSTRUCTION;
1071 s->buf_addr_type = GTT_BUFFER;
1072 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1073 s->ret_ip_gma_ring -= s->ring_size;
1074 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1079 struct mi_display_flip_command_info {
1083 i915_reg_t stride_reg;
1084 i915_reg_t ctrl_reg;
1085 i915_reg_t surf_reg;
1092 struct plane_code_mapping {
1098 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1099 struct mi_display_flip_command_info *info)
1101 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1102 struct plane_code_mapping gen8_plane_code[] = {
1103 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1104 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1105 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1106 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1107 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1108 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1110 u32 dword0, dword1, dword2;
1113 dword0 = cmd_val(s, 0);
1114 dword1 = cmd_val(s, 1);
1115 dword2 = cmd_val(s, 2);
1117 v = (dword0 & GENMASK(21, 19)) >> 19;
1118 if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1121 info->pipe = gen8_plane_code[v].pipe;
1122 info->plane = gen8_plane_code[v].plane;
1123 info->event = gen8_plane_code[v].event;
1124 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1125 info->tile_val = (dword1 & 0x1);
1126 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1127 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1129 if (info->plane == PLANE_A) {
1130 info->ctrl_reg = DSPCNTR(info->pipe);
1131 info->stride_reg = DSPSTRIDE(info->pipe);
1132 info->surf_reg = DSPSURF(info->pipe);
1133 } else if (info->plane == PLANE_B) {
1134 info->ctrl_reg = SPRCTL(info->pipe);
1135 info->stride_reg = SPRSTRIDE(info->pipe);
1136 info->surf_reg = SPRSURF(info->pipe);
1144 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1145 struct mi_display_flip_command_info *info)
1147 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1148 struct intel_vgpu *vgpu = s->vgpu;
1149 u32 dword0 = cmd_val(s, 0);
1150 u32 dword1 = cmd_val(s, 1);
1151 u32 dword2 = cmd_val(s, 2);
1152 u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1154 info->plane = PRIMARY_PLANE;
1157 case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1158 info->pipe = PIPE_A;
1159 info->event = PRIMARY_A_FLIP_DONE;
1161 case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1162 info->pipe = PIPE_B;
1163 info->event = PRIMARY_B_FLIP_DONE;
1165 case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1166 info->pipe = PIPE_C;
1167 info->event = PRIMARY_C_FLIP_DONE;
1170 case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1171 info->pipe = PIPE_A;
1172 info->event = SPRITE_A_FLIP_DONE;
1173 info->plane = SPRITE_PLANE;
1175 case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1176 info->pipe = PIPE_B;
1177 info->event = SPRITE_B_FLIP_DONE;
1178 info->plane = SPRITE_PLANE;
1180 case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1181 info->pipe = PIPE_C;
1182 info->event = SPRITE_C_FLIP_DONE;
1183 info->plane = SPRITE_PLANE;
1187 gvt_vgpu_err("unknown plane code %d\n", plane);
1191 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1192 info->tile_val = (dword1 & GENMASK(2, 0));
1193 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1194 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1196 info->ctrl_reg = DSPCNTR(info->pipe);
1197 info->stride_reg = DSPSTRIDE(info->pipe);
1198 info->surf_reg = DSPSURF(info->pipe);
1203 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1204 struct mi_display_flip_command_info *info)
1206 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1209 if (!info->async_flip)
1212 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1213 stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1214 tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &
1215 GENMASK(12, 10)) >> 10;
1217 stride = (vgpu_vreg(s->vgpu, info->stride_reg) &
1218 GENMASK(15, 6)) >> 6;
1219 tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1222 if (stride != info->stride_val)
1223 gvt_dbg_cmd("cannot change stride during async flip\n");
1225 if (tile != info->tile_val)
1226 gvt_dbg_cmd("cannot change tile during async flip\n");
1231 static int gen8_update_plane_mmio_from_mi_display_flip(
1232 struct parser_exec_state *s,
1233 struct mi_display_flip_command_info *info)
1235 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1236 struct intel_vgpu *vgpu = s->vgpu;
1238 set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),
1239 info->surf_val << 12);
1240 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1241 set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),
1243 set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),
1244 info->tile_val << 10);
1246 set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(15, 6),
1247 info->stride_val << 6);
1248 set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(10, 10),
1249 info->tile_val << 10);
1252 vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1253 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1257 static int decode_mi_display_flip(struct parser_exec_state *s,
1258 struct mi_display_flip_command_info *info)
1260 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1262 if (IS_BROADWELL(dev_priv))
1263 return gen8_decode_mi_display_flip(s, info);
1264 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1265 return skl_decode_mi_display_flip(s, info);
1270 static int check_mi_display_flip(struct parser_exec_state *s,
1271 struct mi_display_flip_command_info *info)
1273 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1275 if (IS_BROADWELL(dev_priv)
1276 || IS_SKYLAKE(dev_priv)
1277 || IS_KABYLAKE(dev_priv))
1278 return gen8_check_mi_display_flip(s, info);
1282 static int update_plane_mmio_from_mi_display_flip(
1283 struct parser_exec_state *s,
1284 struct mi_display_flip_command_info *info)
1286 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1288 if (IS_BROADWELL(dev_priv)
1289 || IS_SKYLAKE(dev_priv)
1290 || IS_KABYLAKE(dev_priv))
1291 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1295 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1297 struct mi_display_flip_command_info info;
1298 struct intel_vgpu *vgpu = s->vgpu;
1301 int len = cmd_length(s);
1303 ret = decode_mi_display_flip(s, &info);
1305 gvt_vgpu_err("fail to decode MI display flip command\n");
1309 ret = check_mi_display_flip(s, &info);
1311 gvt_vgpu_err("invalid MI display flip command\n");
1315 ret = update_plane_mmio_from_mi_display_flip(s, &info);
1317 gvt_vgpu_err("fail to update plane mmio\n");
1321 for (i = 0; i < len; i++)
1322 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1326 static bool is_wait_for_flip_pending(u32 cmd)
1328 return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1329 MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1330 MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1331 MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1332 MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1333 MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1336 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1338 u32 cmd = cmd_val(s, 0);
1340 if (!is_wait_for_flip_pending(cmd))
1343 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1347 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1350 unsigned long gma_high, gma_low;
1351 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1353 if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8))
1354 return INTEL_GVT_INVALID_ADDR;
1356 gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1357 if (gmadr_bytes == 4) {
1360 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1361 addr = (((unsigned long)gma_high) << 32) | gma_low;
1366 static inline int cmd_address_audit(struct parser_exec_state *s,
1367 unsigned long guest_gma, int op_size, bool index_mode)
1369 struct intel_vgpu *vgpu = s->vgpu;
1370 u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1374 if (op_size > max_surface_size) {
1375 gvt_vgpu_err("command address audit fail name %s\n",
1381 if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) {
1385 } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1393 gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1394 s->info->name, guest_gma, op_size);
1396 pr_err("cmd dump: ");
1397 for (i = 0; i < cmd_length(s); i++) {
1399 pr_err("\n%08x ", cmd_val(s, i));
1401 pr_err("%08x ", cmd_val(s, i));
1403 pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1405 vgpu_aperture_gmadr_base(vgpu),
1406 vgpu_aperture_gmadr_end(vgpu),
1407 vgpu_hidden_gmadr_base(vgpu),
1408 vgpu_hidden_gmadr_end(vgpu));
1412 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1414 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1415 int op_size = (cmd_length(s) - 3) * sizeof(u32);
1416 int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1417 unsigned long gma, gma_low, gma_high;
1421 if (!(cmd_val(s, 0) & (1 << 22)))
1424 gma = cmd_val(s, 2) & GENMASK(31, 2);
1426 if (gmadr_bytes == 8) {
1427 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1428 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1429 gma = (gma_high << 32) | gma_low;
1430 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1432 ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1436 static inline int unexpected_cmd(struct parser_exec_state *s)
1438 struct intel_vgpu *vgpu = s->vgpu;
1440 gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1445 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1447 return unexpected_cmd(s);
1450 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1452 return unexpected_cmd(s);
1455 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1457 return unexpected_cmd(s);
1460 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1462 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1463 int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1465 unsigned long gma, gma_high;
1468 if (!(cmd_val(s, 0) & (1 << 22)))
1471 gma = cmd_val(s, 1) & GENMASK(31, 2);
1472 if (gmadr_bytes == 8) {
1473 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1474 gma = (gma_high << 32) | gma;
1476 ret = cmd_address_audit(s, gma, op_size, false);
1480 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1482 return unexpected_cmd(s);
1485 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1487 return unexpected_cmd(s);
1490 static int cmd_handler_mi_conditional_batch_buffer_end(
1491 struct parser_exec_state *s)
1493 return unexpected_cmd(s);
1496 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1498 return unexpected_cmd(s);
1501 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1503 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1505 bool index_mode = false;
1508 /* Check post-sync and ppgtt bit */
1509 if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1510 gma = cmd_val(s, 1) & GENMASK(31, 3);
1511 if (gmadr_bytes == 8)
1512 gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1513 /* Store Data Index */
1514 if (cmd_val(s, 0) & (1 << 21))
1516 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1518 /* Check notify bit */
1519 if ((cmd_val(s, 0) & (1 << 8)))
1520 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1521 s->workload->pending_events);
1525 static void addr_type_update_snb(struct parser_exec_state *s)
1527 if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1528 (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1529 s->buf_addr_type = PPGTT_BUFFER;
1534 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1535 unsigned long gma, unsigned long end_gma, void *va)
1537 unsigned long copy_len, offset;
1538 unsigned long len = 0;
1541 while (gma != end_gma) {
1542 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1543 if (gpa == INTEL_GVT_INVALID_ADDR) {
1544 gvt_vgpu_err("invalid gma address: %lx\n", gma);
1548 offset = gma & (GTT_PAGE_SIZE - 1);
1550 copy_len = (end_gma - gma) >= (GTT_PAGE_SIZE - offset) ?
1551 GTT_PAGE_SIZE - offset : end_gma - gma;
1553 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1563 * Check whether a batch buffer needs to be scanned. Currently
1564 * the only criteria is based on privilege.
1566 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1568 struct intel_gvt *gvt = s->vgpu->gvt;
1570 if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
1571 || IS_KABYLAKE(gvt->dev_priv)) {
1572 /* BDW decides privilege based on address space */
1573 if (cmd_val(s, 0) & (1 << 8))
1579 static int find_bb_size(struct parser_exec_state *s)
1581 unsigned long gma = 0;
1582 struct cmd_info *info;
1584 uint32_t cmd_len = 0;
1585 bool met_bb_end = false;
1586 struct intel_vgpu *vgpu = s->vgpu;
1589 /* get the start gm address of the batch buffer */
1590 gma = get_gma_bb_from_cmd(s, 1);
1591 cmd = cmd_val(s, 0);
1593 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1595 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
1596 cmd, get_opcode(cmd, s->ring_id));
1600 copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1601 gma, gma + 4, &cmd);
1602 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1604 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
1605 cmd, get_opcode(cmd, s->ring_id));
1609 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1611 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1612 if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) {
1613 /* chained batch buffer */
1617 cmd_len = get_cmd_length(info, cmd) << 2;
1621 } while (!met_bb_end);
1626 static int perform_bb_shadow(struct parser_exec_state *s)
1628 struct intel_shadow_bb_entry *entry_obj;
1629 struct intel_vgpu *vgpu = s->vgpu;
1630 unsigned long gma = 0;
1635 /* get the start gm address of the batch buffer */
1636 gma = get_gma_bb_from_cmd(s, 1);
1638 /* get the size of the batch buffer */
1639 bb_size = find_bb_size(s);
1643 /* allocate shadow batch buffer */
1644 entry_obj = kmalloc(sizeof(*entry_obj), GFP_KERNEL);
1645 if (entry_obj == NULL)
1649 i915_gem_object_create(s->vgpu->gvt->dev_priv,
1650 roundup(bb_size, PAGE_SIZE));
1651 if (IS_ERR(entry_obj->obj)) {
1652 ret = PTR_ERR(entry_obj->obj);
1655 entry_obj->len = bb_size;
1656 INIT_LIST_HEAD(&entry_obj->list);
1658 dst = i915_gem_object_pin_map(entry_obj->obj, I915_MAP_WB);
1664 ret = i915_gem_object_set_to_cpu_domain(entry_obj->obj, false);
1666 gvt_vgpu_err("failed to set shadow batch to CPU\n");
1670 entry_obj->va = dst;
1671 entry_obj->bb_start_cmd_va = s->ip_va;
1673 /* copy batch buffer to shadow batch buffer*/
1674 ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1678 gvt_vgpu_err("fail to copy guest ring buffer\n");
1682 list_add(&entry_obj->list, &s->workload->shadow_bb);
1684 * ip_va saves the virtual address of the shadow batch buffer, while
1685 * ip_gma saves the graphics address of the original batch buffer.
1686 * As the shadow batch buffer is just a copy from the originial one,
1687 * it should be right to use shadow batch buffer'va and original batch
1688 * buffer's gma in pair. After all, we don't want to pin the shadow
1689 * buffer here (too early).
1697 i915_gem_object_unpin_map(entry_obj->obj);
1699 i915_gem_object_put(entry_obj->obj);
1705 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1709 struct intel_vgpu *vgpu = s->vgpu;
1711 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1712 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1716 second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1717 if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1718 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1722 s->saved_buf_addr_type = s->buf_addr_type;
1723 addr_type_update_snb(s);
1724 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1725 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1726 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1727 } else if (second_level) {
1728 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1729 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1730 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1733 if (batch_buffer_needs_scan(s)) {
1734 ret = perform_bb_shadow(s);
1736 gvt_vgpu_err("invalid shadow batch buffer\n");
1738 /* emulate a batch buffer end to do return right */
1739 ret = cmd_handler_mi_batch_buffer_end(s);
1747 static struct cmd_info cmd_info[] = {
1748 {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1750 {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1753 {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1754 0, 1, cmd_handler_mi_user_interrupt},
1756 {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1757 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1759 {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1761 {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1764 {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1767 {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1770 {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1773 {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1776 {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1777 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1778 cmd_handler_mi_batch_buffer_end},
1780 {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1783 {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1786 {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1789 {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1792 {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1795 {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1796 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1798 {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1801 {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1803 {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1805 {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1806 D_BDW_PLUS, 0, 8, NULL},
1808 {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1809 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1811 {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1812 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1814 {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1815 0, 8, cmd_handler_mi_store_data_index},
1817 {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1818 D_ALL, 0, 8, cmd_handler_lri},
1820 {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1821 cmd_handler_mi_update_gtt},
1823 {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1824 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1826 {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1827 cmd_handler_mi_flush_dw},
1829 {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1830 10, cmd_handler_mi_clflush},
1832 {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1833 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1835 {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1836 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1838 {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1839 D_ALL, 0, 8, cmd_handler_lrr},
1841 {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1844 {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1845 ADDR_FIX_1(2), 8, NULL},
1847 {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1848 ADDR_FIX_1(2), 8, NULL},
1850 {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1851 8, cmd_handler_mi_op_2e},
1853 {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1854 8, cmd_handler_mi_op_2f},
1856 {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1857 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1858 cmd_handler_mi_batch_buffer_start},
1860 {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1861 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1862 cmd_handler_mi_conditional_batch_buffer_end},
1864 {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1865 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1867 {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1868 ADDR_FIX_2(4, 7), 8, NULL},
1870 {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1873 {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1874 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1876 {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1878 {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1881 {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1882 ADDR_FIX_1(3), 8, NULL},
1884 {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1887 {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1888 ADDR_FIX_1(4), 8, NULL},
1890 {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1891 ADDR_FIX_2(4, 5), 8, NULL},
1893 {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1894 ADDR_FIX_1(4), 8, NULL},
1896 {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1897 ADDR_FIX_2(4, 7), 8, NULL},
1899 {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1900 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1902 {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1904 {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1905 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1907 {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1908 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1910 {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1911 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1912 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1914 {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1915 D_ALL, ADDR_FIX_1(4), 8, NULL},
1917 {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
1918 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1920 {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
1921 D_ALL, ADDR_FIX_1(4), 8, NULL},
1923 {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
1924 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1926 {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
1927 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1929 {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
1930 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
1931 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1933 {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
1934 ADDR_FIX_2(4, 5), 8, NULL},
1936 {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
1937 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1939 {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
1940 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
1941 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1943 {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
1944 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
1945 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1947 {"3DSTATE_BLEND_STATE_POINTERS",
1948 OP_3DSTATE_BLEND_STATE_POINTERS,
1949 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1951 {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
1952 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
1953 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1955 {"3DSTATE_BINDING_TABLE_POINTERS_VS",
1956 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
1957 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1959 {"3DSTATE_BINDING_TABLE_POINTERS_HS",
1960 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
1961 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1963 {"3DSTATE_BINDING_TABLE_POINTERS_DS",
1964 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
1965 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1967 {"3DSTATE_BINDING_TABLE_POINTERS_GS",
1968 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
1969 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1971 {"3DSTATE_BINDING_TABLE_POINTERS_PS",
1972 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
1973 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1975 {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
1976 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
1977 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1979 {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
1980 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
1981 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1983 {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
1984 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
1985 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1987 {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
1988 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
1989 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1991 {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
1992 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
1993 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1995 {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
1998 {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2001 {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2004 {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2007 {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2008 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2010 {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2011 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2013 {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2014 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2016 {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2017 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2019 {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2020 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2022 {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2023 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2025 {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2026 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2028 {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2029 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2031 {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2032 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2034 {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2035 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2037 {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2038 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2040 {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2041 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2043 {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2044 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2046 {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2047 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2049 {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2050 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2052 {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2053 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2055 {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2056 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2058 {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2059 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2061 {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2062 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2064 {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2065 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2067 {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2068 D_BDW_PLUS, 0, 8, NULL},
2070 {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2073 {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2074 D_BDW_PLUS, 0, 8, NULL},
2076 {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2077 D_BDW_PLUS, 0, 8, NULL},
2079 {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2082 {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2083 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2085 {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2088 {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2091 {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2094 {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2097 {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2098 D_BDW_PLUS, 0, 8, NULL},
2100 {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2101 R_RCS, D_ALL, 0, 8, NULL},
2103 {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2104 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2106 {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2107 R_RCS, D_ALL, 0, 1, NULL},
2109 {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2111 {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2112 R_RCS, D_ALL, 0, 8, NULL},
2114 {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2115 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2117 {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2119 {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2121 {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2123 {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2124 D_BDW_PLUS, 0, 8, NULL},
2126 {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2127 D_BDW_PLUS, 0, 8, NULL},
2129 {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2132 {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2133 D_BDW_PLUS, 0, 8, NULL},
2135 {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2136 D_BDW_PLUS, 0, 8, NULL},
2138 {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2140 {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2142 {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2144 {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2147 {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2149 {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2151 {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2152 R_RCS, D_ALL, 0, 8, NULL},
2154 {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2155 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2157 {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2160 {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2161 D_ALL, ADDR_FIX_1(2), 8, NULL},
2163 {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2164 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2166 {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2167 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2169 {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2172 {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2175 {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2178 {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2179 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2181 {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2182 D_BDW_PLUS, 0, 8, NULL},
2184 {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2185 D_ALL, ADDR_FIX_1(2), 8, NULL},
2187 {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2188 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2190 {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2191 R_RCS, D_ALL, 0, 8, NULL},
2193 {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2194 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2196 {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2197 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2199 {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2200 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2202 {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2203 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2205 {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2206 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2208 {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2209 R_RCS, D_ALL, 0, 8, NULL},
2211 {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2214 {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2215 ADDR_FIX_2(2, 4), 8, NULL},
2217 {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2218 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2219 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2221 {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2222 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2224 {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2225 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2226 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2228 {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2229 D_BDW_PLUS, 0, 8, NULL},
2231 {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2232 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2234 {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2236 {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2239 {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2240 ADDR_FIX_1(1), 8, NULL},
2242 {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2244 {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2245 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2247 {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2248 ADDR_FIX_1(1), 8, NULL},
2250 {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2252 {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2254 {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2257 {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2258 D_SKL_PLUS, 0, 8, NULL},
2260 {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2261 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2263 {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2266 {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2269 {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2271 {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2274 {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2277 {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2280 {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2283 {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2286 {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2287 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2289 {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2290 R_VCS, D_ALL, 0, 12, NULL},
2292 {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2293 R_VCS, D_ALL, 0, 12, NULL},
2295 {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2296 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2298 {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2299 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2301 {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2302 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2304 {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2306 {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2307 R_VCS, D_ALL, 0, 12, NULL},
2309 {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2310 R_VCS, D_ALL, 0, 12, NULL},
2312 {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2313 R_VCS, D_ALL, 0, 12, NULL},
2315 {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2316 R_VCS, D_ALL, 0, 12, NULL},
2318 {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2319 R_VCS, D_ALL, 0, 12, NULL},
2321 {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2322 R_VCS, D_ALL, 0, 12, NULL},
2324 {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2325 R_VCS, D_ALL, 0, 6, NULL},
2327 {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2328 R_VCS, D_ALL, 0, 12, NULL},
2330 {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2331 R_VCS, D_ALL, 0, 12, NULL},
2333 {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2334 R_VCS, D_ALL, 0, 12, NULL},
2336 {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2337 R_VCS, D_ALL, 0, 12, NULL},
2339 {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2340 R_VCS, D_ALL, 0, 12, NULL},
2342 {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2343 R_VCS, D_ALL, 0, 12, NULL},
2345 {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2346 R_VCS, D_ALL, 0, 12, NULL},
2347 {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2348 R_VCS, D_ALL, 0, 12, NULL},
2350 {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2351 R_VCS, D_ALL, 0, 12, NULL},
2353 {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2354 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2356 {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2357 R_VCS, D_ALL, 0, 12, NULL},
2359 {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2360 R_VCS, D_ALL, 0, 12, NULL},
2362 {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2363 R_VCS, D_ALL, 0, 12, NULL},
2365 {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2366 R_VCS, D_ALL, 0, 12, NULL},
2368 {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2369 R_VCS, D_ALL, 0, 12, NULL},
2371 {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2372 R_VCS, D_ALL, 0, 12, NULL},
2374 {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2375 R_VCS, D_ALL, 0, 12, NULL},
2377 {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2378 R_VCS, D_ALL, 0, 12, NULL},
2380 {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2381 R_VCS, D_ALL, 0, 12, NULL},
2383 {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2384 R_VCS, D_ALL, 0, 12, NULL},
2386 {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2387 R_VCS, D_ALL, 0, 12, NULL},
2389 {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2392 {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2394 {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2396 {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2397 R_VCS, D_ALL, 0, 12, NULL},
2399 {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2400 R_VCS, D_ALL, 0, 12, NULL},
2402 {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2403 R_VCS, D_ALL, 0, 12, NULL},
2405 {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2407 {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2410 {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2414 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2416 hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2419 /* call the cmd handler, and advance ip */
2420 static int cmd_parser_exec(struct parser_exec_state *s)
2422 struct intel_vgpu *vgpu = s->vgpu;
2423 struct cmd_info *info;
2427 cmd = cmd_val(s, 0);
2429 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2431 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
2432 cmd, get_opcode(cmd, s->ring_id));
2438 trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2439 cmd_length(s), s->buf_type);
2441 if (info->handler) {
2442 ret = info->handler(s);
2444 gvt_vgpu_err("%s handler error\n", info->name);
2449 if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2450 ret = cmd_advance_default(s);
2452 gvt_vgpu_err("%s IP advance error\n", info->name);
2459 static inline bool gma_out_of_range(unsigned long gma,
2460 unsigned long gma_head, unsigned int gma_tail)
2462 if (gma_tail >= gma_head)
2463 return (gma < gma_head) || (gma > gma_tail);
2465 return (gma > gma_tail) && (gma < gma_head);
2468 static int command_scan(struct parser_exec_state *s,
2469 unsigned long rb_head, unsigned long rb_tail,
2470 unsigned long rb_start, unsigned long rb_len)
2473 unsigned long gma_head, gma_tail, gma_bottom;
2475 struct intel_vgpu *vgpu = s->vgpu;
2477 gma_head = rb_start + rb_head;
2478 gma_tail = rb_start + rb_tail;
2479 gma_bottom = rb_start + rb_len;
2481 while (s->ip_gma != gma_tail) {
2482 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2483 if (!(s->ip_gma >= rb_start) ||
2484 !(s->ip_gma < gma_bottom)) {
2485 gvt_vgpu_err("ip_gma %lx out of ring scope."
2486 "(base:0x%lx, bottom: 0x%lx)\n",
2487 s->ip_gma, rb_start,
2489 parser_exec_state_dump(s);
2492 if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2493 gvt_vgpu_err("ip_gma %lx out of range."
2494 "base 0x%lx head 0x%lx tail 0x%lx\n",
2495 s->ip_gma, rb_start,
2497 parser_exec_state_dump(s);
2501 ret = cmd_parser_exec(s);
2503 gvt_vgpu_err("cmd parser error\n");
2504 parser_exec_state_dump(s);
2512 static int scan_workload(struct intel_vgpu_workload *workload)
2514 unsigned long gma_head, gma_tail, gma_bottom;
2515 struct parser_exec_state s;
2518 /* ring base is page aligned */
2519 if (WARN_ON(!IS_ALIGNED(workload->rb_start, GTT_PAGE_SIZE)))
2522 gma_head = workload->rb_start + workload->rb_head;
2523 gma_tail = workload->rb_start + workload->rb_tail;
2524 gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl);
2526 s.buf_type = RING_BUFFER_INSTRUCTION;
2527 s.buf_addr_type = GTT_BUFFER;
2528 s.vgpu = workload->vgpu;
2529 s.ring_id = workload->ring_id;
2530 s.ring_start = workload->rb_start;
2531 s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2532 s.ring_head = gma_head;
2533 s.ring_tail = gma_tail;
2534 s.rb_va = workload->shadow_ring_buffer_va;
2535 s.workload = workload;
2537 if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2538 gma_head == gma_tail)
2541 if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2546 ret = ip_gma_set(&s, gma_head);
2550 ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2551 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2557 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2560 unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2561 struct parser_exec_state s;
2563 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2564 struct intel_vgpu_workload,
2567 /* ring base is page aligned */
2568 if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, GTT_PAGE_SIZE)))
2571 ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2572 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2574 gma_head = wa_ctx->indirect_ctx.guest_gma;
2575 gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2576 gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2578 s.buf_type = RING_BUFFER_INSTRUCTION;
2579 s.buf_addr_type = GTT_BUFFER;
2580 s.vgpu = workload->vgpu;
2581 s.ring_id = workload->ring_id;
2582 s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2583 s.ring_size = ring_size;
2584 s.ring_head = gma_head;
2585 s.ring_tail = gma_tail;
2586 s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2587 s.workload = workload;
2589 if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2594 ret = ip_gma_set(&s, gma_head);
2598 ret = command_scan(&s, 0, ring_tail,
2599 wa_ctx->indirect_ctx.guest_gma, ring_size);
2604 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2606 struct intel_vgpu *vgpu = workload->vgpu;
2607 unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2608 void *shadow_ring_buffer_va;
2609 int ring_id = workload->ring_id;
2612 guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2614 /* calculate workload ring buffer size */
2615 workload->rb_len = (workload->rb_tail + guest_rb_size -
2616 workload->rb_head) % guest_rb_size;
2618 gma_head = workload->rb_start + workload->rb_head;
2619 gma_tail = workload->rb_start + workload->rb_tail;
2620 gma_top = workload->rb_start + guest_rb_size;
2622 if (workload->rb_len > vgpu->reserve_ring_buffer_size[ring_id]) {
2623 void *va = vgpu->reserve_ring_buffer_va[ring_id];
2624 /* realloc the new ring buffer if needed */
2625 vgpu->reserve_ring_buffer_va[ring_id] =
2626 krealloc(va, workload->rb_len, GFP_KERNEL);
2627 if (!vgpu->reserve_ring_buffer_va[ring_id]) {
2628 gvt_vgpu_err("fail to alloc reserve ring buffer\n");
2631 vgpu->reserve_ring_buffer_size[ring_id] = workload->rb_len;
2634 shadow_ring_buffer_va = vgpu->reserve_ring_buffer_va[ring_id];
2636 /* get shadow ring buffer va */
2637 workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2639 /* head > tail --> copy head <-> top */
2640 if (gma_head > gma_tail) {
2641 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2642 gma_head, gma_top, shadow_ring_buffer_va);
2644 gvt_vgpu_err("fail to copy guest ring buffer\n");
2647 shadow_ring_buffer_va += ret;
2648 gma_head = workload->rb_start;
2651 /* copy head or start <-> tail */
2652 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2653 shadow_ring_buffer_va);
2655 gvt_vgpu_err("fail to copy guest ring buffer\n");
2661 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2664 struct intel_vgpu *vgpu = workload->vgpu;
2666 ret = shadow_workload_ring_buffer(workload);
2668 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2672 ret = scan_workload(workload);
2674 gvt_vgpu_err("scan workload error\n");
2680 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2682 int ctx_size = wa_ctx->indirect_ctx.size;
2683 unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2684 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2685 struct intel_vgpu_workload,
2687 struct intel_vgpu *vgpu = workload->vgpu;
2688 struct drm_i915_gem_object *obj;
2692 obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2693 roundup(ctx_size + CACHELINE_BYTES,
2696 return PTR_ERR(obj);
2698 /* get the va of the shadow batch buffer */
2699 map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2701 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2706 ret = i915_gem_object_set_to_cpu_domain(obj, false);
2708 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2712 ret = copy_gma_to_hva(workload->vgpu,
2713 workload->vgpu->gtt.ggtt_mm,
2714 guest_gma, guest_gma + ctx_size,
2717 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2721 wa_ctx->indirect_ctx.obj = obj;
2722 wa_ctx->indirect_ctx.shadow_va = map;
2726 i915_gem_object_unpin_map(obj);
2728 i915_gem_object_put(obj);
2732 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2734 uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2735 unsigned char *bb_start_sva;
2737 if (!wa_ctx->per_ctx.valid)
2740 per_ctx_start[0] = 0x18800001;
2741 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2743 bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2744 wa_ctx->indirect_ctx.size;
2746 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2751 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2754 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2755 struct intel_vgpu_workload,
2757 struct intel_vgpu *vgpu = workload->vgpu;
2759 if (wa_ctx->indirect_ctx.size == 0)
2762 ret = shadow_indirect_ctx(wa_ctx);
2764 gvt_vgpu_err("fail to shadow indirect ctx\n");
2768 combine_wa_ctx(wa_ctx);
2770 ret = scan_wa_ctx(wa_ctx);
2772 gvt_vgpu_err("scan wa ctx error\n");
2779 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2780 unsigned int opcode, unsigned long rings)
2782 struct cmd_info *info = NULL;
2785 for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2786 info = find_cmd_entry(gvt, opcode, ring);
2793 static int init_cmd_table(struct intel_gvt *gvt)
2796 struct cmd_entry *e;
2797 struct cmd_info *info;
2798 unsigned int gen_type;
2800 gen_type = intel_gvt_get_device_type(gvt);
2802 for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2803 if (!(cmd_info[i].devices & gen_type))
2806 e = kzalloc(sizeof(*e), GFP_KERNEL);
2810 e->info = &cmd_info[i];
2811 info = find_cmd_entry_any_ring(gvt,
2812 e->info->opcode, e->info->rings);
2814 gvt_err("%s %s duplicated\n", e->info->name,
2819 INIT_HLIST_NODE(&e->hlist);
2820 add_cmd_entry(gvt, e);
2821 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2822 e->info->name, e->info->opcode, e->info->flag,
2823 e->info->devices, e->info->rings);
2828 static void clean_cmd_table(struct intel_gvt *gvt)
2830 struct hlist_node *tmp;
2831 struct cmd_entry *e;
2834 hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2837 hash_init(gvt->cmd_table);
2840 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2842 clean_cmd_table(gvt);
2845 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2849 ret = init_cmd_table(gvt);
2851 intel_gvt_clean_cmd_parser(gvt);