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11 * The above copyright notice and this permission notice (including the next
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28 #include "hypercall.h"
30 #define GVT_MAX_VGPU 8
33 INTEL_GVT_HYPERVISOR_XEN = 0,
34 INTEL_GVT_HYPERVISOR_KVM,
37 struct intel_gvt_host {
40 struct intel_gvt_mpt *mpt;
43 extern struct intel_gvt_host intel_gvt_host;
45 /* Describe per-platform limitations. */
46 struct intel_gvt_device_info {
47 u32 max_support_vgpus;
48 /* This data structure will grow bigger in GVT device model patches */
51 /* GM resources owned by a vGPU */
52 struct intel_vgpu_gm {
55 struct drm_mm_node low_gm_node;
56 struct drm_mm_node high_gm_node;
59 #define INTEL_GVT_MAX_NUM_FENCES 32
61 /* Fences owned by a vGPU */
62 struct intel_vgpu_fence {
63 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
69 struct intel_gvt *gvt;
71 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
73 struct intel_vgpu_fence fence;
74 struct intel_vgpu_gm gm;
78 unsigned long vgpu_allocated_low_gm_size;
79 unsigned long vgpu_allocated_high_gm_size;
82 struct intel_gvt_fence {
83 unsigned long vgpu_allocated_fence_num;
90 struct drm_i915_private *dev_priv;
91 struct idr vgpu_idr; /* vGPU IDR pool */
93 struct intel_gvt_device_info device_info;
94 struct intel_gvt_gm gm;
95 struct intel_gvt_fence fence;
98 /* Aperture/GM space definitions for GVT device */
99 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
100 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
102 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)
103 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
105 #define gvt_aperture_gmadr_base(gvt) (0)
106 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
107 + gvt_aperture_sz(gvt) - 1)
109 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
110 + gvt_aperture_sz(gvt))
111 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
112 + gvt_hidden_sz(gvt) - 1)
114 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)
116 /* Aperture/GM space definitions for vGPU */
117 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
118 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
119 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
120 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
122 #define vgpu_aperture_pa_base(vgpu) \
123 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
125 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
127 #define vgpu_aperture_pa_end(vgpu) \
128 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
130 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
131 #define vgpu_aperture_gmadr_end(vgpu) \
132 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
134 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
135 #define vgpu_hidden_gmadr_end(vgpu) \
136 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
138 #define vgpu_fence_base(vgpu) (vgpu->fence.base)
139 #define vgpu_fence_sz(vgpu) (vgpu->fence.size)
141 struct intel_vgpu_creation_params {
143 __u64 low_gm_sz; /* in MB */
144 __u64 high_gm_sz; /* in MB */
150 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
151 struct intel_vgpu_creation_params *param);
152 void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
153 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
154 u32 fence, u64 value);