drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <zhi.a.wang@intel.com>
  25  *
  26  * Contributors:
  27  *    Ping Gao <ping.a.gao@intel.com>
  28  *    Tina Zhang <tina.zhang@intel.com>
  29  *    Chanbin Du <changbin.du@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Bing Niu <bing.niu@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *
  34  */
  35
  36 #include "i915_drv.h"
  37
  38 #include <linux/kthread.h>
  39
  40 #define RING_CTX_OFF(x) \
  41         offsetof(struct execlist_ring_context, x)
  42
  43 void set_context_pdp_root_pointer(struct execlist_ring_context *ring_context,
  44                 u32 pdp[8])
  45 {
  46         struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW;
  47         int i;
  48
  49         for (i = 0; i < 8; i++)
  50                 pdp_pair[i].val = pdp[7 - i];
  51 }
  52
  53 static int populate_shadow_context(struct intel_vgpu_workload *workload)
  54 {
  55         struct intel_vgpu *vgpu = workload->vgpu;
  56         struct intel_gvt *gvt = vgpu->gvt;
  57         int ring_id = workload->ring_id;
  58         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
  59         struct drm_i915_gem_object *ctx_obj =
  60                 shadow_ctx->engine[ring_id].state->obj;
  61         struct execlist_ring_context *shadow_ring_context;
  62         struct page *page;
  63         void *dst;
  64         unsigned long context_gpa, context_page_num;
  65         int i;
  66
  67         gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
  68                         workload->ctx_desc.lrca);
  69
  70         context_page_num = intel_lr_context_size(
  71                         &gvt->dev_priv->engine[ring_id]);
  72
  73         context_page_num = context_page_num >> PAGE_SHIFT;
  74
  75         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
  76                 context_page_num = 19;
  77
  78         i = 2;
  79
  80         while (i < context_page_num) {
  81                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
  82                                 (u32)((workload->ctx_desc.lrca + i) <<
  83                                 GTT_PAGE_SHIFT));
  84                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
  85                         gvt_err("Invalid guest context descriptor\n");
  86                         return -EINVAL;
  87                 }
  88
  89                 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
  90                 dst = kmap_atomic(page);
  91                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
  92                                 GTT_PAGE_SIZE);
  93                 kunmap_atomic(dst);
  94                 i++;
  95         }
  96
  97         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
  98         shadow_ring_context = kmap_atomic(page);
  99
 100 #define COPY_REG(name) \
 101         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 102                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 103
 104         COPY_REG(ctx_ctrl);
 105         COPY_REG(ctx_timestamp);
 106
 107         if (ring_id == RCS) {
 108                 COPY_REG(bb_per_ctx_ptr);
 109                 COPY_REG(rcs_indirect_ctx);
 110                 COPY_REG(rcs_indirect_ctx_offset);
 111         }
 112 #undef COPY_REG
 113
 114         set_context_pdp_root_pointer(shadow_ring_context,
 115                                      workload->shadow_mm->shadow_page_table);
 116
 117         intel_gvt_hypervisor_read_gpa(vgpu,
 118                         workload->ring_context_gpa +
 119                         sizeof(*shadow_ring_context),
 120                         (void *)shadow_ring_context +
 121                         sizeof(*shadow_ring_context),
 122                         GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 123
 124         kunmap_atomic(shadow_ring_context);
 125         return 0;
 126 }
 127
 128 static int shadow_context_status_change(struct notifier_block *nb,
 129                 unsigned long action, void *data)
 130 {
 131         struct intel_vgpu *vgpu = container_of(nb,
 132                         struct intel_vgpu, shadow_ctx_notifier_block);
 133         struct drm_i915_gem_request *req =
 134                 (struct drm_i915_gem_request *)data;
 135         struct intel_gvt_workload_scheduler *scheduler =
 136                 &vgpu->gvt->scheduler;
 137         struct intel_vgpu_workload *workload =
 138                 scheduler->current_workload[req->engine->id];
 139
 140         switch (action) {
 141         case INTEL_CONTEXT_SCHEDULE_IN:
 142                 intel_gvt_load_render_mmio(workload->vgpu,
 143                                            workload->ring_id);
 144                 atomic_set(&workload->shadow_ctx_active, 1);
 145                 break;
 146         case INTEL_CONTEXT_SCHEDULE_OUT:
 147                 intel_gvt_restore_render_mmio(workload->vgpu,
 148                                               workload->ring_id);
 149                 atomic_set(&workload->shadow_ctx_active, 0);
 150                 break;
 151         default:
 152                 WARN_ON(1);
 153                 return NOTIFY_OK;
 154         }
 155         wake_up(&workload->shadow_ctx_status_wq);
 156         return NOTIFY_OK;
 157 }
 158
 159 static int dispatch_workload(struct intel_vgpu_workload *workload)
 160 {
 161         struct intel_vgpu *vgpu = workload->vgpu;
 162         struct intel_gvt *gvt = vgpu->gvt;
 163         int ring_id = workload->ring_id;
 164         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
 165         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
 166         int ret;
 167
 168         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
 169                 ring_id, workload);
 170
 171         shadow_ctx->desc_template = workload->ctx_desc.addressing_mode <<
 172                                     GEN8_CTX_ADDRESSING_MODE_SHIFT;
 173
 174         workload->req = i915_gem_request_alloc(&dev_priv->engine[ring_id],
 175                                                shadow_ctx);
 176         if (IS_ERR_OR_NULL(workload->req)) {
 177                 gvt_err("fail to allocate gem request\n");
 178                 workload->status = PTR_ERR(workload->req);
 179                 workload->req = NULL;
 180                 return workload->status;
 181         }
 182
 183         gvt_dbg_sched("ring id %d get i915 gem request %p\n",
 184                         ring_id, workload->req);
 185
 186         mutex_lock(&gvt->lock);
 187
 188         ret = populate_shadow_context(workload);
 189         if (ret)
 190                 goto err;
 191
 192         if (workload->prepare) {
 193                 ret = workload->prepare(workload);
 194                 if (ret)
 195                         goto err;
 196         }
 197
 198         mutex_unlock(&gvt->lock);
 199
 200         gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
 201                         ring_id, workload->req);
 202
 203         i915_add_request_no_flush(workload->req);
 204
 205         workload->dispatched = true;
 206         return 0;
 207 err:
 208         workload->status = ret;
 209         if (workload->req)
 210                 workload->req = NULL;
 211
 212         mutex_unlock(&gvt->lock);
 213         return ret;
 214 }
 215
 216 static struct intel_vgpu_workload *pick_next_workload(
 217                 struct intel_gvt *gvt, int ring_id)
 218 {
 219         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 220         struct intel_vgpu_workload *workload = NULL;
 221
 222         mutex_lock(&gvt->lock);
 223
 224         /*
 225          * no current vgpu / will be scheduled out / no workload
 226          * bail out
 227          */
 228         if (!scheduler->current_vgpu) {
 229                 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
 230                 goto out;
 231         }
 232
 233         if (scheduler->need_reschedule) {
 234                 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
 235                 goto out;
 236         }
 237
 238         if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) {
 239                 gvt_dbg_sched("ring id %d stop - no available workload\n",
 240                                 ring_id);
 241                 goto out;
 242         }
 243
 244         /*
 245          * still have current workload, maybe the workload disptacher
 246          * fail to submit it for some reason, resubmit it.
 247          */
 248         if (scheduler->current_workload[ring_id]) {
 249                 workload = scheduler->current_workload[ring_id];
 250                 gvt_dbg_sched("ring id %d still have current workload %p\n",
 251                                 ring_id, workload);
 252                 goto out;
 253         }
 254
 255         /*
 256          * pick a workload as current workload
 257          * once current workload is set, schedule policy routines
 258          * will wait the current workload is finished when trying to
 259          * schedule out a vgpu.
 260          */
 261         scheduler->current_workload[ring_id] = container_of(
 262                         workload_q_head(scheduler->current_vgpu, ring_id)->next,
 263                         struct intel_vgpu_workload, list);
 264
 265         workload = scheduler->current_workload[ring_id];
 266
 267         gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
 268
 269         atomic_inc(&workload->vgpu->running_workload_num);
 270 out:
 271         mutex_unlock(&gvt->lock);
 272         return workload;
 273 }
 274
 275 static void update_guest_context(struct intel_vgpu_workload *workload)
 276 {
 277         struct intel_vgpu *vgpu = workload->vgpu;
 278         struct intel_gvt *gvt = vgpu->gvt;
 279         int ring_id = workload->ring_id;
 280         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
 281         struct drm_i915_gem_object *ctx_obj =
 282                 shadow_ctx->engine[ring_id].state->obj;
 283         struct execlist_ring_context *shadow_ring_context;
 284         struct page *page;
 285         void *src;
 286         unsigned long context_gpa, context_page_num;
 287         int i;
 288
 289         gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
 290                         workload->ctx_desc.lrca);
 291
 292         context_page_num = intel_lr_context_size(
 293                         &gvt->dev_priv->engine[ring_id]);
 294
 295         context_page_num = context_page_num >> PAGE_SHIFT;
 296
 297         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
 298                 context_page_num = 19;
 299
 300         i = 2;
 301
 302         while (i < context_page_num) {
 303                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 304                                 (u32)((workload->ctx_desc.lrca + i) <<
 305                                         GTT_PAGE_SHIFT));
 306                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 307                         gvt_err("invalid guest context descriptor\n");
 308                         return;
 309                 }
 310
 311                 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
 312                 src = kmap_atomic(page);
 313                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
 314                                 GTT_PAGE_SIZE);
 315                 kunmap_atomic(src);
 316                 i++;
 317         }
 318
 319         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
 320                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
 321
 322         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 323         shadow_ring_context = kmap_atomic(page);
 324
 325 #define COPY_REG(name) \
 326         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
 327                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 328
 329         COPY_REG(ctx_ctrl);
 330         COPY_REG(ctx_timestamp);
 331
 332 #undef COPY_REG
 333
 334         intel_gvt_hypervisor_write_gpa(vgpu,
 335                         workload->ring_context_gpa +
 336                         sizeof(*shadow_ring_context),
 337                         (void *)shadow_ring_context +
 338                         sizeof(*shadow_ring_context),
 339                         GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 340
 341         kunmap_atomic(shadow_ring_context);
 342 }
 343
 344 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 345 {
 346         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 347         struct intel_vgpu_workload *workload;
 348
 349         mutex_lock(&gvt->lock);
 350
 351         workload = scheduler->current_workload[ring_id];
 352
 353         if (!workload->status && !workload->vgpu->resetting) {
 354                 wait_event(workload->shadow_ctx_status_wq,
 355                            !atomic_read(&workload->shadow_ctx_active));
 356
 357                 update_guest_context(workload);
 358         }
 359
 360         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
 361                         ring_id, workload, workload->status);
 362
 363         scheduler->current_workload[ring_id] = NULL;
 364
 365         atomic_dec(&workload->vgpu->running_workload_num);
 366
 367         list_del_init(&workload->list);
 368         workload->complete(workload);
 369
 370         wake_up(&scheduler->workload_complete_wq);
 371         mutex_unlock(&gvt->lock);
 372 }
 373
 374 struct workload_thread_param {
 375         struct intel_gvt *gvt;
 376         int ring_id;
 377 };
 378
 379 static int workload_thread(void *priv)
 380 {
 381         struct workload_thread_param *p = (struct workload_thread_param *)priv;
 382         struct intel_gvt *gvt = p->gvt;
 383         int ring_id = p->ring_id;
 384         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 385         struct intel_vgpu_workload *workload = NULL;
 386         int ret;
 387         bool need_force_wake = IS_SKYLAKE(gvt->dev_priv);
 388
 389         kfree(p);
 390
 391         gvt_dbg_core("workload thread for ring %d started\n", ring_id);
 392
 393         while (!kthread_should_stop()) {
 394                 ret = wait_event_interruptible(scheduler->waitq[ring_id],
 395                                 kthread_should_stop() ||
 396                                 (workload = pick_next_workload(gvt, ring_id)));
 397
 398                 WARN_ON_ONCE(ret);
 399
 400                 if (kthread_should_stop())
 401                         break;
 402
 403                 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
 404                                 workload->ring_id, workload,
 405                                 workload->vgpu->id);
 406
 407                 intel_runtime_pm_get(gvt->dev_priv);
 408
 409                 /*
 410                  * Always take i915 big lock first
 411                  */
 412                 ret = i915_mutex_lock_interruptible(&gvt->dev_priv->drm);
 413                 if (ret < 0) {
 414                         gvt_err("i915 submission is not available, retry\n");
 415                         schedule_timeout(1);
 416                         continue;
 417                 }
 418
 419                 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
 420                                 workload->ring_id, workload);
 421
 422                 if (need_force_wake)
 423                         intel_uncore_forcewake_get(gvt->dev_priv,
 424                                         FORCEWAKE_ALL);
 425
 426                 ret = dispatch_workload(workload);
 427                 if (ret) {
 428                         gvt_err("fail to dispatch workload, skip\n");
 429                         goto complete;
 430                 }
 431
 432                 gvt_dbg_sched("ring id %d wait workload %p\n",
 433                                 workload->ring_id, workload);
 434
 435                 workload->status = i915_wait_request(workload->req,
 436                                                      I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
 437                                                      NULL, NULL);
 438                 if (workload->status != 0)
 439                         gvt_err("fail to wait workload, skip\n");
 440
 441 complete:
 442                 gvt_dbg_sched("will complete workload %p\n, status: %d\n",
 443                                 workload, workload->status);
 444
 445                 complete_current_workload(gvt, ring_id);
 446
 447                 if (need_force_wake)
 448                         intel_uncore_forcewake_put(gvt->dev_priv,
 449                                         FORCEWAKE_ALL);
 450
 451                 mutex_unlock(&gvt->dev_priv->drm.struct_mutex);
 452
 453                 intel_runtime_pm_put(gvt->dev_priv);
 454         }
 455         return 0;
 456 }
 457
 458 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
 459 {
 460         struct intel_gvt *gvt = vgpu->gvt;
 461         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 462
 463         if (atomic_read(&vgpu->running_workload_num)) {
 464                 gvt_dbg_sched("wait vgpu idle\n");
 465
 466                 wait_event(scheduler->workload_complete_wq,
 467                                 !atomic_read(&vgpu->running_workload_num));
 468         }
 469 }
 470
 471 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
 472 {
 473         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 474         int i;
 475
 476         gvt_dbg_core("clean workload scheduler\n");
 477
 478         for (i = 0; i < I915_NUM_ENGINES; i++) {
 479                 if (scheduler->thread[i]) {
 480                         kthread_stop(scheduler->thread[i]);
 481                         scheduler->thread[i] = NULL;
 482                 }
 483         }
 484 }
 485
 486 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
 487 {
 488         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 489         struct workload_thread_param *param = NULL;
 490         int ret;
 491         int i;
 492
 493         gvt_dbg_core("init workload scheduler\n");
 494
 495         init_waitqueue_head(&scheduler->workload_complete_wq);
 496
 497         for (i = 0; i < I915_NUM_ENGINES; i++) {
 498                 init_waitqueue_head(&scheduler->waitq[i]);
 499
 500                 param = kzalloc(sizeof(*param), GFP_KERNEL);
 501                 if (!param) {
 502                         ret = -ENOMEM;
 503                         goto err;
 504                 }
 505
 506                 param->gvt = gvt;
 507                 param->ring_id = i;
 508
 509                 scheduler->thread[i] = kthread_run(workload_thread, param,
 510                         "gvt workload %d", i);
 511                 if (IS_ERR(scheduler->thread[i])) {
 512                         gvt_err("fail to create workload thread\n");
 513                         ret = PTR_ERR(scheduler->thread[i]);
 514                         goto err;
 515                 }
 516         }
 517         return 0;
 518 err:
 519         intel_gvt_clean_workload_scheduler(gvt);
 520         kfree(param);
 521         param = NULL;
 522         return ret;
 523 }
 524
 525 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu)
 526 {
 527         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 528
 529         atomic_notifier_chain_unregister(&vgpu->shadow_ctx->status_notifier,
 530                         &vgpu->shadow_ctx_notifier_block);
 531
 532         mutex_lock(&dev_priv->drm.struct_mutex);
 533
 534         /* a little hacky to mark as ctx closed */
 535         vgpu->shadow_ctx->closed = true;
 536         i915_gem_context_put(vgpu->shadow_ctx);
 537
 538         mutex_unlock(&dev_priv->drm.struct_mutex);
 539 }
 540
 541 int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu)
 542 {
 543         atomic_set(&vgpu->running_workload_num, 0);
 544
 545         vgpu->shadow_ctx = i915_gem_context_create_gvt(
 546                         &vgpu->gvt->dev_priv->drm);
 547         if (IS_ERR(vgpu->shadow_ctx))
 548                 return PTR_ERR(vgpu->shadow_ctx);
 549
 550         vgpu->shadow_ctx->engine[RCS].initialised = true;
 551
 552         vgpu->shadow_ctx_notifier_block.notifier_call =
 553                 shadow_context_status_change;
 554
 555         atomic_notifier_chain_register(&vgpu->shadow_ctx->status_notifier,
 556                                        &vgpu->shadow_ctx_notifier_block);
 557         return 0;
 558 }