drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <zhi.a.wang@intel.com>
  25  *
  26  * Contributors:
  27  *    Ping Gao <ping.a.gao@intel.com>
  28  *    Tina Zhang <tina.zhang@intel.com>
  29  *    Chanbin Du <changbin.du@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Bing Niu <bing.niu@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *
  34  */
  35
  36 #include <linux/kthread.h>
  37
  38 #include "i915_drv.h"
  39 #include "gvt.h"
  40
  41 #define RING_CTX_OFF(x) \
  42         offsetof(struct execlist_ring_context, x)
  43
  44 static void set_context_pdp_root_pointer(
  45                 struct execlist_ring_context *ring_context,
  46                 u32 pdp[8])
  47 {
  48         int i;
  49
  50         for (i = 0; i < 8; i++)
  51                 ring_context->pdps[i].val = pdp[7 - i];
  52 }
  53
  54 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
  55 {
  56         struct drm_i915_gem_object *ctx_obj =
  57                 workload->req->hw_context->state->obj;
  58         struct execlist_ring_context *shadow_ring_context;
  59         struct page *page;
  60
  61         if (WARN_ON(!workload->shadow_mm))
  62                 return;
  63
  64         if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
  65                 return;
  66
  67         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
  68         shadow_ring_context = kmap(page);
  69         set_context_pdp_root_pointer(shadow_ring_context,
  70                         (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
  71         kunmap(page);
  72 }
  73
  74 /*
  75  * when populating shadow ctx from guest, we should not overrride oa related
  76  * registers, so that they will not be overlapped by guest oa configs. Thus
  77  * made it possible to capture oa data from host for both host and guests.
  78  */
  79 static void sr_oa_regs(struct intel_vgpu_workload *workload,
  80                 u32 *reg_state, bool save)
  81 {
  82         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
  83         u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
  84         u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
  85         int i = 0;
  86         u32 flex_mmio[] = {
  87                 i915_mmio_reg_offset(EU_PERF_CNTL0),
  88                 i915_mmio_reg_offset(EU_PERF_CNTL1),
  89                 i915_mmio_reg_offset(EU_PERF_CNTL2),
  90                 i915_mmio_reg_offset(EU_PERF_CNTL3),
  91                 i915_mmio_reg_offset(EU_PERF_CNTL4),
  92                 i915_mmio_reg_offset(EU_PERF_CNTL5),
  93                 i915_mmio_reg_offset(EU_PERF_CNTL6),
  94         };
  95
  96         if (workload->ring_id != RCS)
  97                 return;
  98
  99         if (save) {
 100                 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
 101
 102                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 103                         u32 state_offset = ctx_flexeu0 + i * 2;
 104
 105                         workload->flex_mmio[i] = reg_state[state_offset + 1];
 106                 }
 107         } else {
 108                 reg_state[ctx_oactxctrl] =
 109                         i915_mmio_reg_offset(GEN8_OACTXCONTROL);
 110                 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
 111
 112                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 113                         u32 state_offset = ctx_flexeu0 + i * 2;
 114                         u32 mmio = flex_mmio[i];
 115
 116                         reg_state[state_offset] = mmio;
 117                         reg_state[state_offset + 1] = workload->flex_mmio[i];
 118                 }
 119         }
 120 }
 121
 122 static int populate_shadow_context(struct intel_vgpu_workload *workload)
 123 {
 124         struct intel_vgpu *vgpu = workload->vgpu;
 125         struct intel_gvt *gvt = vgpu->gvt;
 126         int ring_id = workload->ring_id;
 127         struct drm_i915_gem_object *ctx_obj =
 128                 workload->req->hw_context->state->obj;
 129         struct execlist_ring_context *shadow_ring_context;
 130         struct page *page;
 131         void *dst;
 132         unsigned long context_gpa, context_page_num;
 133         int i;
 134
 135         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 136         shadow_ring_context = kmap(page);
 137
 138         sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
 139 #define COPY_REG(name) \
 140         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 141                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 142 #define COPY_REG_MASKED(name) {\
 143                 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 144                                               + RING_CTX_OFF(name.val),\
 145                                               &shadow_ring_context->name.val, 4);\
 146                 shadow_ring_context->name.val |= 0xffff << 16;\
 147         }
 148
 149         COPY_REG_MASKED(ctx_ctrl);
 150         COPY_REG(ctx_timestamp);
 151
 152         if (ring_id == RCS) {
 153                 COPY_REG(bb_per_ctx_ptr);
 154                 COPY_REG(rcs_indirect_ctx);
 155                 COPY_REG(rcs_indirect_ctx_offset);
 156         }
 157 #undef COPY_REG
 158 #undef COPY_REG_MASKED
 159
 160         intel_gvt_hypervisor_read_gpa(vgpu,
 161                         workload->ring_context_gpa +
 162                         sizeof(*shadow_ring_context),
 163                         (void *)shadow_ring_context +
 164                         sizeof(*shadow_ring_context),
 165                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 166
 167         sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
 168         kunmap(page);
 169
 170         if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
 171                 return 0;
 172
 173         gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
 174                         workload->ctx_desc.lrca);
 175
 176         context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
 177
 178         context_page_num = context_page_num >> PAGE_SHIFT;
 179
 180         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
 181                 context_page_num = 19;
 182
 183         i = 2;
 184         while (i < context_page_num) {
 185                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 186                                 (u32)((workload->ctx_desc.lrca + i) <<
 187                                 I915_GTT_PAGE_SHIFT));
 188                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 189                         gvt_vgpu_err("Invalid guest context descriptor\n");
 190                         return -EFAULT;
 191                 }
 192
 193                 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
 194                 dst = kmap(page);
 195                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
 196                                 I915_GTT_PAGE_SIZE);
 197                 kunmap(page);
 198                 i++;
 199         }
 200         return 0;
 201 }
 202
 203 static inline bool is_gvt_request(struct i915_request *req)
 204 {
 205         return i915_gem_context_force_single_submission(req->gem_context);
 206 }
 207
 208 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
 209 {
 210         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 211         u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
 212         i915_reg_t reg;
 213
 214         reg = RING_INSTDONE(ring_base);
 215         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 216         reg = RING_ACTHD(ring_base);
 217         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 218         reg = RING_ACTHD_UDW(ring_base);
 219         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 220 }
 221
 222 static int shadow_context_status_change(struct notifier_block *nb,
 223                 unsigned long action, void *data)
 224 {
 225         struct i915_request *req = data;
 226         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
 227                                 shadow_ctx_notifier_block[req->engine->id]);
 228         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 229         enum intel_engine_id ring_id = req->engine->id;
 230         struct intel_vgpu_workload *workload;
 231         unsigned long flags;
 232
 233         if (!is_gvt_request(req)) {
 234                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 235                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
 236                     scheduler->engine_owner[ring_id]) {
 237                         /* Switch ring from vGPU to host. */
 238                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 239                                               NULL, ring_id);
 240                         scheduler->engine_owner[ring_id] = NULL;
 241                 }
 242                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 243
 244                 return NOTIFY_OK;
 245         }
 246
 247         workload = scheduler->current_workload[ring_id];
 248         if (unlikely(!workload))
 249                 return NOTIFY_OK;
 250
 251         switch (action) {
 252         case INTEL_CONTEXT_SCHEDULE_IN:
 253                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 254                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
 255                         /* Switch ring from host to vGPU or vGPU to vGPU. */
 256                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 257                                               workload->vgpu, ring_id);
 258                         scheduler->engine_owner[ring_id] = workload->vgpu;
 259                 } else
 260                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
 261                                       ring_id, workload->vgpu->id);
 262                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 263                 atomic_set(&workload->shadow_ctx_active, 1);
 264                 break;
 265         case INTEL_CONTEXT_SCHEDULE_OUT:
 266                 save_ring_hw_state(workload->vgpu, ring_id);
 267                 atomic_set(&workload->shadow_ctx_active, 0);
 268                 break;
 269         case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
 270                 save_ring_hw_state(workload->vgpu, ring_id);
 271                 break;
 272         default:
 273                 WARN_ON(1);
 274                 return NOTIFY_OK;
 275         }
 276         wake_up(&workload->shadow_ctx_status_wq);
 277         return NOTIFY_OK;
 278 }
 279
 280 static void shadow_context_descriptor_update(struct intel_context *ce)
 281 {
 282         u64 desc = 0;
 283
 284         desc = ce->lrc_desc;
 285
 286         /* Update bits 0-11 of the context descriptor which includes flags
 287          * like GEN8_CTX_* cached in desc_template
 288          */
 289         desc &= U64_MAX << 12;
 290         desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
 291
 292         ce->lrc_desc = desc;
 293 }
 294
 295 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
 296 {
 297         struct intel_vgpu *vgpu = workload->vgpu;
 298         struct i915_request *req = workload->req;
 299         void *shadow_ring_buffer_va;
 300         u32 *cs;
 301
 302         if ((IS_KABYLAKE(req->i915) || IS_BROXTON(req->i915)
 303                 || IS_COFFEELAKE(req->i915))
 304                 && is_inhibit_context(req->hw_context))
 305                 intel_vgpu_restore_inhibit_context(vgpu, req);
 306
 307         /* allocate shadow ring buffer */
 308         cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
 309         if (IS_ERR(cs)) {
 310                 gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
 311                         workload->rb_len);
 312                 return PTR_ERR(cs);
 313         }
 314
 315         shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
 316
 317         /* get shadow ring buffer va */
 318         workload->shadow_ring_buffer_va = cs;
 319
 320         memcpy(cs, shadow_ring_buffer_va,
 321                         workload->rb_len);
 322
 323         cs += workload->rb_len / sizeof(u32);
 324         intel_ring_advance(workload->req, cs);
 325
 326         return 0;
 327 }
 328
 329 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 330 {
 331         if (!wa_ctx->indirect_ctx.obj)
 332                 return;
 333
 334         i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
 335         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
 336 }
 337
 338 static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
 339                                          struct i915_gem_context *ctx)
 340 {
 341         struct intel_vgpu_mm *mm = workload->shadow_mm;
 342         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
 343         int i = 0;
 344
 345         if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed)
 346                 return -1;
 347
 348         if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 349                 px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0];
 350         } else {
 351                 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
 352                         px_dma(ppgtt->pdp.page_directory[i]) =
 353                                 mm->ppgtt_mm.shadow_pdps[i];
 354                 }
 355         }
 356
 357         return 0;
 358 }
 359
 360 /**
 361  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
 362  * shadow it as well, include ringbuffer,wa_ctx and ctx.
 363  * @workload: an abstract entity for each execlist submission.
 364  *
 365  * This function is called before the workload submitting to i915, to make
 366  * sure the content of the workload is valid.
 367  */
 368 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
 369 {
 370         struct intel_vgpu *vgpu = workload->vgpu;
 371         struct intel_vgpu_submission *s = &vgpu->submission;
 372         struct i915_gem_context *shadow_ctx = s->shadow_ctx;
 373         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 374         struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
 375         struct intel_context *ce;
 376         struct i915_request *rq;
 377         int ret;
 378
 379         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 380
 381         if (workload->req)
 382                 return 0;
 383
 384         ret = set_context_ppgtt_from_shadow(workload, shadow_ctx);
 385         if (ret < 0) {
 386                 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
 387                 return ret;
 388         }
 389
 390         /* pin shadow context by gvt even the shadow context will be pinned
 391          * when i915 alloc request. That is because gvt will update the guest
 392          * context from shadow context when workload is completed, and at that
 393          * moment, i915 may already unpined the shadow context to make the
 394          * shadow_ctx pages invalid. So gvt need to pin itself. After update
 395          * the guest context, gvt can unpin the shadow_ctx safely.
 396          */
 397         ce = intel_context_pin(shadow_ctx, engine);
 398         if (IS_ERR(ce)) {
 399                 gvt_vgpu_err("fail to pin shadow context\n");
 400                 return PTR_ERR(ce);
 401         }
 402
 403         shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
 404         shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
 405                                     GEN8_CTX_ADDRESSING_MODE_SHIFT;
 406
 407         if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
 408                 shadow_context_descriptor_update(ce);
 409
 410         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
 411         if (ret)
 412                 goto err_unpin;
 413
 414         if ((workload->ring_id == RCS) &&
 415             (workload->wa_ctx.indirect_ctx.size != 0)) {
 416                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
 417                 if (ret)
 418                         goto err_shadow;
 419         }
 420
 421         rq = i915_request_alloc(engine, shadow_ctx);
 422         if (IS_ERR(rq)) {
 423                 gvt_vgpu_err("fail to allocate gem request\n");
 424                 ret = PTR_ERR(rq);
 425                 goto err_shadow;
 426         }
 427         workload->req = i915_request_get(rq);
 428
 429         ret = populate_shadow_context(workload);
 430         if (ret)
 431                 goto err_req;
 432
 433         return 0;
 434 err_req:
 435         rq = fetch_and_zero(&workload->req);
 436         i915_request_put(rq);
 437 err_shadow:
 438         release_shadow_wa_ctx(&workload->wa_ctx);
 439 err_unpin:
 440         intel_context_unpin(ce);
 441         return ret;
 442 }
 443
 444 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
 445
 446 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 447 {
 448         struct intel_gvt *gvt = workload->vgpu->gvt;
 449         const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 450         struct intel_vgpu_shadow_bb *bb;
 451         int ret;
 452
 453         list_for_each_entry(bb, &workload->shadow_bb, list) {
 454                 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
 455                  * is only updated into ring_scan_buffer, not real ring address
 456                  * allocated in later copy_workload_to_ring_buffer. pls be noted
 457                  * shadow_ring_buffer_va is now pointed to real ring buffer va
 458                  * in copy_workload_to_ring_buffer.
 459                  */
 460
 461                 if (bb->bb_offset)
 462                         bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
 463                                 + bb->bb_offset;
 464
 465                 if (bb->ppgtt) {
 466                         /* for non-priv bb, scan&shadow is only for
 467                          * debugging purpose, so the content of shadow bb
 468                          * is the same as original bb. Therefore,
 469                          * here, rather than switch to shadow bb's gma
 470                          * address, we directly use original batch buffer's
 471                          * gma address, and send original bb to hardware
 472                          * directly
 473                          */
 474                         if (bb->clflush & CLFLUSH_AFTER) {
 475                                 drm_clflush_virt_range(bb->va,
 476                                                 bb->obj->base.size);
 477                                 bb->clflush &= ~CLFLUSH_AFTER;
 478                         }
 479                         i915_gem_obj_finish_shmem_access(bb->obj);
 480                         bb->accessing = false;
 481
 482                 } else {
 483                         bb->vma = i915_gem_object_ggtt_pin(bb->obj,
 484                                         NULL, 0, 0, 0);
 485                         if (IS_ERR(bb->vma)) {
 486                                 ret = PTR_ERR(bb->vma);
 487                                 goto err;
 488                         }
 489
 490                         /* relocate shadow batch buffer */
 491                         bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
 492                         if (gmadr_bytes == 8)
 493                                 bb->bb_start_cmd_va[2] = 0;
 494
 495                         /* No one is going to touch shadow bb from now on. */
 496                         if (bb->clflush & CLFLUSH_AFTER) {
 497                                 drm_clflush_virt_range(bb->va,
 498                                                 bb->obj->base.size);
 499                                 bb->clflush &= ~CLFLUSH_AFTER;
 500                         }
 501
 502                         ret = i915_gem_object_set_to_gtt_domain(bb->obj,
 503                                         false);
 504                         if (ret)
 505                                 goto err;
 506
 507                         i915_gem_obj_finish_shmem_access(bb->obj);
 508                         bb->accessing = false;
 509
 510                         ret = i915_vma_move_to_active(bb->vma,
 511                                                       workload->req,
 512                                                       0);
 513                         if (ret)
 514                                 goto err;
 515                 }
 516         }
 517         return 0;
 518 err:
 519         release_shadow_batch_buffer(workload);
 520         return ret;
 521 }
 522
 523 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 524 {
 525         struct intel_vgpu_workload *workload =
 526                 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
 527         struct i915_request *rq = workload->req;
 528         struct execlist_ring_context *shadow_ring_context =
 529                 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
 530
 531         shadow_ring_context->bb_per_ctx_ptr.val =
 532                 (shadow_ring_context->bb_per_ctx_ptr.val &
 533                 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
 534         shadow_ring_context->rcs_indirect_ctx.val =
 535                 (shadow_ring_context->rcs_indirect_ctx.val &
 536                 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
 537 }
 538
 539 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 540 {
 541         struct i915_vma *vma;
 542         unsigned char *per_ctx_va =
 543                 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
 544                 wa_ctx->indirect_ctx.size;
 545
 546         if (wa_ctx->indirect_ctx.size == 0)
 547                 return 0;
 548
 549         vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
 550                                        0, CACHELINE_BYTES, 0);
 551         if (IS_ERR(vma))
 552                 return PTR_ERR(vma);
 553
 554         /* FIXME: we are not tracking our pinned VMA leaving it
 555          * up to the core to fix up the stray pin_count upon
 556          * free.
 557          */
 558
 559         wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
 560
 561         wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
 562         memset(per_ctx_va, 0, CACHELINE_BYTES);
 563
 564         update_wa_ctx_2_shadow_ctx(wa_ctx);
 565         return 0;
 566 }
 567
 568 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 569 {
 570         struct intel_vgpu *vgpu = workload->vgpu;
 571         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 572         struct intel_vgpu_shadow_bb *bb, *pos;
 573
 574         if (list_empty(&workload->shadow_bb))
 575                 return;
 576
 577         bb = list_first_entry(&workload->shadow_bb,
 578                         struct intel_vgpu_shadow_bb, list);
 579
 580         mutex_lock(&dev_priv->drm.struct_mutex);
 581
 582         list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
 583                 if (bb->obj) {
 584                         if (bb->accessing)
 585                                 i915_gem_obj_finish_shmem_access(bb->obj);
 586
 587                         if (bb->va && !IS_ERR(bb->va))
 588                                 i915_gem_object_unpin_map(bb->obj);
 589
 590                         if (bb->vma && !IS_ERR(bb->vma)) {
 591                                 i915_vma_unpin(bb->vma);
 592                                 i915_vma_close(bb->vma);
 593                         }
 594                         __i915_gem_object_release_unless_active(bb->obj);
 595                 }
 596                 list_del(&bb->list);
 597                 kfree(bb);
 598         }
 599
 600         mutex_unlock(&dev_priv->drm.struct_mutex);
 601 }
 602
 603 static int prepare_workload(struct intel_vgpu_workload *workload)
 604 {
 605         struct intel_vgpu *vgpu = workload->vgpu;
 606         int ret = 0;
 607
 608         ret = intel_vgpu_pin_mm(workload->shadow_mm);
 609         if (ret) {
 610                 gvt_vgpu_err("fail to vgpu pin mm\n");
 611                 return ret;
 612         }
 613
 614         update_shadow_pdps(workload);
 615
 616         ret = intel_vgpu_sync_oos_pages(workload->vgpu);
 617         if (ret) {
 618                 gvt_vgpu_err("fail to vgpu sync oos pages\n");
 619                 goto err_unpin_mm;
 620         }
 621
 622         ret = intel_vgpu_flush_post_shadow(workload->vgpu);
 623         if (ret) {
 624                 gvt_vgpu_err("fail to flush post shadow\n");
 625                 goto err_unpin_mm;
 626         }
 627
 628         ret = copy_workload_to_ring_buffer(workload);
 629         if (ret) {
 630                 gvt_vgpu_err("fail to generate request\n");
 631                 goto err_unpin_mm;
 632         }
 633
 634         ret = prepare_shadow_batch_buffer(workload);
 635         if (ret) {
 636                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
 637                 goto err_unpin_mm;
 638         }
 639
 640         ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
 641         if (ret) {
 642                 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
 643                 goto err_shadow_batch;
 644         }
 645
 646         if (workload->prepare) {
 647                 ret = workload->prepare(workload);
 648                 if (ret)
 649                         goto err_shadow_wa_ctx;
 650         }
 651
 652         return 0;
 653 err_shadow_wa_ctx:
 654         release_shadow_wa_ctx(&workload->wa_ctx);
 655 err_shadow_batch:
 656         release_shadow_batch_buffer(workload);
 657 err_unpin_mm:
 658         intel_vgpu_unpin_mm(workload->shadow_mm);
 659         return ret;
 660 }
 661
 662 static int dispatch_workload(struct intel_vgpu_workload *workload)
 663 {
 664         struct intel_vgpu *vgpu = workload->vgpu;
 665         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 666         int ring_id = workload->ring_id;
 667         int ret;
 668
 669         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
 670                 ring_id, workload);
 671
 672         mutex_lock(&vgpu->vgpu_lock);
 673         mutex_lock(&dev_priv->drm.struct_mutex);
 674
 675         ret = intel_gvt_scan_and_shadow_workload(workload);
 676         if (ret)
 677                 goto out;
 678
 679         ret = prepare_workload(workload);
 680
 681 out:
 682         if (ret)
 683                 workload->status = ret;
 684
 685         if (!IS_ERR_OR_NULL(workload->req)) {
 686                 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
 687                                 ring_id, workload->req);
 688                 i915_request_add(workload->req);
 689                 workload->dispatched = true;
 690         }
 691
 692         mutex_unlock(&dev_priv->drm.struct_mutex);
 693         mutex_unlock(&vgpu->vgpu_lock);
 694         return ret;
 695 }
 696
 697 static struct intel_vgpu_workload *pick_next_workload(
 698                 struct intel_gvt *gvt, int ring_id)
 699 {
 700         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 701         struct intel_vgpu_workload *workload = NULL;
 702
 703         mutex_lock(&gvt->sched_lock);
 704
 705         /*
 706          * no current vgpu / will be scheduled out / no workload
 707          * bail out
 708          */
 709         if (!scheduler->current_vgpu) {
 710                 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
 711                 goto out;
 712         }
 713
 714         if (scheduler->need_reschedule) {
 715                 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
 716                 goto out;
 717         }
 718
 719         if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
 720                 goto out;
 721
 722         /*
 723          * still have current workload, maybe the workload disptacher
 724          * fail to submit it for some reason, resubmit it.
 725          */
 726         if (scheduler->current_workload[ring_id]) {
 727                 workload = scheduler->current_workload[ring_id];
 728                 gvt_dbg_sched("ring id %d still have current workload %p\n",
 729                                 ring_id, workload);
 730                 goto out;
 731         }
 732
 733         /*
 734          * pick a workload as current workload
 735          * once current workload is set, schedule policy routines
 736          * will wait the current workload is finished when trying to
 737          * schedule out a vgpu.
 738          */
 739         scheduler->current_workload[ring_id] = container_of(
 740                         workload_q_head(scheduler->current_vgpu, ring_id)->next,
 741                         struct intel_vgpu_workload, list);
 742
 743         workload = scheduler->current_workload[ring_id];
 744
 745         gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
 746
 747         atomic_inc(&workload->vgpu->submission.running_workload_num);
 748 out:
 749         mutex_unlock(&gvt->sched_lock);
 750         return workload;
 751 }
 752
 753 static void update_guest_context(struct intel_vgpu_workload *workload)
 754 {
 755         struct i915_request *rq = workload->req;
 756         struct intel_vgpu *vgpu = workload->vgpu;
 757         struct intel_gvt *gvt = vgpu->gvt;
 758         struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
 759         struct execlist_ring_context *shadow_ring_context;
 760         struct page *page;
 761         void *src;
 762         unsigned long context_gpa, context_page_num;
 763         int i;
 764
 765         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
 766                       workload->ctx_desc.lrca);
 767
 768         context_page_num = rq->engine->context_size;
 769         context_page_num = context_page_num >> PAGE_SHIFT;
 770
 771         if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS)
 772                 context_page_num = 19;
 773
 774         i = 2;
 775
 776         while (i < context_page_num) {
 777                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 778                                 (u32)((workload->ctx_desc.lrca + i) <<
 779                                         I915_GTT_PAGE_SHIFT));
 780                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 781                         gvt_vgpu_err("invalid guest context descriptor\n");
 782                         return;
 783                 }
 784
 785                 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
 786                 src = kmap(page);
 787                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
 788                                 I915_GTT_PAGE_SIZE);
 789                 kunmap(page);
 790                 i++;
 791         }
 792
 793         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
 794                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
 795
 796         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 797         shadow_ring_context = kmap(page);
 798
 799 #define COPY_REG(name) \
 800         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
 801                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 802
 803         COPY_REG(ctx_ctrl);
 804         COPY_REG(ctx_timestamp);
 805
 806 #undef COPY_REG
 807
 808         intel_gvt_hypervisor_write_gpa(vgpu,
 809                         workload->ring_context_gpa +
 810                         sizeof(*shadow_ring_context),
 811                         (void *)shadow_ring_context +
 812                         sizeof(*shadow_ring_context),
 813                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 814
 815         kunmap(page);
 816 }
 817
 818 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
 819                                 unsigned long engine_mask)
 820 {
 821         struct intel_vgpu_submission *s = &vgpu->submission;
 822         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 823         struct intel_engine_cs *engine;
 824         struct intel_vgpu_workload *pos, *n;
 825         unsigned int tmp;
 826
 827         /* free the unsubmited workloads in the queues. */
 828         for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
 829                 list_for_each_entry_safe(pos, n,
 830                         &s->workload_q_head[engine->id], list) {
 831                         list_del_init(&pos->list);
 832                         intel_vgpu_destroy_workload(pos);
 833                 }
 834                 clear_bit(engine->id, s->shadow_ctx_desc_updated);
 835         }
 836 }
 837
 838 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 839 {
 840         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 841         struct intel_vgpu_workload *workload =
 842                 scheduler->current_workload[ring_id];
 843         struct intel_vgpu *vgpu = workload->vgpu;
 844         struct intel_vgpu_submission *s = &vgpu->submission;
 845         struct i915_request *rq = workload->req;
 846         int event;
 847
 848         mutex_lock(&vgpu->vgpu_lock);
 849         mutex_lock(&gvt->sched_lock);
 850
 851         /* For the workload w/ request, needs to wait for the context
 852          * switch to make sure request is completed.
 853          * For the workload w/o request, directly complete the workload.
 854          */
 855         if (rq) {
 856                 wait_event(workload->shadow_ctx_status_wq,
 857                            !atomic_read(&workload->shadow_ctx_active));
 858
 859                 /* If this request caused GPU hang, req->fence.error will
 860                  * be set to -EIO. Use -EIO to set workload status so
 861                  * that when this request caused GPU hang, didn't trigger
 862                  * context switch interrupt to guest.
 863                  */
 864                 if (likely(workload->status == -EINPROGRESS)) {
 865                         if (workload->req->fence.error == -EIO)
 866                                 workload->status = -EIO;
 867                         else
 868                                 workload->status = 0;
 869                 }
 870
 871                 if (!workload->status && !(vgpu->resetting_eng &
 872                                            ENGINE_MASK(ring_id))) {
 873                         update_guest_context(workload);
 874
 875                         for_each_set_bit(event, workload->pending_events,
 876                                          INTEL_GVT_EVENT_MAX)
 877                                 intel_vgpu_trigger_virtual_event(vgpu, event);
 878                 }
 879
 880                 /* unpin shadow ctx as the shadow_ctx update is done */
 881                 mutex_lock(&rq->i915->drm.struct_mutex);
 882                 intel_context_unpin(rq->hw_context);
 883                 mutex_unlock(&rq->i915->drm.struct_mutex);
 884
 885                 i915_request_put(fetch_and_zero(&workload->req));
 886         }
 887
 888         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
 889                         ring_id, workload, workload->status);
 890
 891         scheduler->current_workload[ring_id] = NULL;
 892
 893         list_del_init(&workload->list);
 894
 895         if (!workload->status) {
 896                 release_shadow_batch_buffer(workload);
 897                 release_shadow_wa_ctx(&workload->wa_ctx);
 898         }
 899
 900         if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
 901                 /* if workload->status is not successful means HW GPU
 902                  * has occurred GPU hang or something wrong with i915/GVT,
 903                  * and GVT won't inject context switch interrupt to guest.
 904                  * So this error is a vGPU hang actually to the guest.
 905                  * According to this we should emunlate a vGPU hang. If
 906                  * there are pending workloads which are already submitted
 907                  * from guest, we should clean them up like HW GPU does.
 908                  *
 909                  * if it is in middle of engine resetting, the pending
 910                  * workloads won't be submitted to HW GPU and will be
 911                  * cleaned up during the resetting process later, so doing
 912                  * the workload clean up here doesn't have any impact.
 913                  **/
 914                 intel_vgpu_clean_workloads(vgpu, ENGINE_MASK(ring_id));
 915         }
 916
 917         workload->complete(workload);
 918
 919         atomic_dec(&s->running_workload_num);
 920         wake_up(&scheduler->workload_complete_wq);
 921
 922         if (gvt->scheduler.need_reschedule)
 923                 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
 924
 925         mutex_unlock(&gvt->sched_lock);
 926         mutex_unlock(&vgpu->vgpu_lock);
 927 }
 928
 929 struct workload_thread_param {
 930         struct intel_gvt *gvt;
 931         int ring_id;
 932 };
 933
 934 static int workload_thread(void *priv)
 935 {
 936         struct workload_thread_param *p = (struct workload_thread_param *)priv;
 937         struct intel_gvt *gvt = p->gvt;
 938         int ring_id = p->ring_id;
 939         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 940         struct intel_vgpu_workload *workload = NULL;
 941         struct intel_vgpu *vgpu = NULL;
 942         int ret;
 943         bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
 944         DEFINE_WAIT_FUNC(wait, woken_wake_function);
 945
 946         kfree(p);
 947
 948         gvt_dbg_core("workload thread for ring %d started\n", ring_id);
 949
 950         while (!kthread_should_stop()) {
 951                 add_wait_queue(&scheduler->waitq[ring_id], &wait);
 952                 do {
 953                         workload = pick_next_workload(gvt, ring_id);
 954                         if (workload)
 955                                 break;
 956                         wait_woken(&wait, TASK_INTERRUPTIBLE,
 957                                    MAX_SCHEDULE_TIMEOUT);
 958                 } while (!kthread_should_stop());
 959                 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
 960
 961                 if (!workload)
 962                         break;
 963
 964                 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
 965                                 workload->ring_id, workload,
 966                                 workload->vgpu->id);
 967
 968                 intel_runtime_pm_get(gvt->dev_priv);
 969
 970                 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
 971                                 workload->ring_id, workload);
 972
 973                 if (need_force_wake)
 974                         intel_uncore_forcewake_get(gvt->dev_priv,
 975                                         FORCEWAKE_ALL);
 976
 977                 ret = dispatch_workload(workload);
 978
 979                 if (ret) {
 980                         vgpu = workload->vgpu;
 981                         gvt_vgpu_err("fail to dispatch workload, skip\n");
 982                         goto complete;
 983                 }
 984
 985                 gvt_dbg_sched("ring id %d wait workload %p\n",
 986                                 workload->ring_id, workload);
 987                 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
 988
 989 complete:
 990                 gvt_dbg_sched("will complete workload %p, status: %d\n",
 991                                 workload, workload->status);
 992
 993                 complete_current_workload(gvt, ring_id);
 994
 995                 if (need_force_wake)
 996                         intel_uncore_forcewake_put(gvt->dev_priv,
 997                                         FORCEWAKE_ALL);
 998
 999                 intel_runtime_pm_put(gvt->dev_priv);
1000                 if (ret && (vgpu_is_vm_unhealthy(ret)))
1001                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1002         }
1003         return 0;
1004 }
1005
1006 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1007 {
1008         struct intel_vgpu_submission *s = &vgpu->submission;
1009         struct intel_gvt *gvt = vgpu->gvt;
1010         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1011
1012         if (atomic_read(&s->running_workload_num)) {
1013                 gvt_dbg_sched("wait vgpu idle\n");
1014
1015                 wait_event(scheduler->workload_complete_wq,
1016                                 !atomic_read(&s->running_workload_num));
1017         }
1018 }
1019
1020 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1021 {
1022         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1023         struct intel_engine_cs *engine;
1024         enum intel_engine_id i;
1025
1026         gvt_dbg_core("clean workload scheduler\n");
1027
1028         for_each_engine(engine, gvt->dev_priv, i) {
1029                 atomic_notifier_chain_unregister(
1030                                         &engine->context_status_notifier,
1031                                         &gvt->shadow_ctx_notifier_block[i]);
1032                 kthread_stop(scheduler->thread[i]);
1033         }
1034 }
1035
1036 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1037 {
1038         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1039         struct workload_thread_param *param = NULL;
1040         struct intel_engine_cs *engine;
1041         enum intel_engine_id i;
1042         int ret;
1043
1044         gvt_dbg_core("init workload scheduler\n");
1045
1046         init_waitqueue_head(&scheduler->workload_complete_wq);
1047
1048         for_each_engine(engine, gvt->dev_priv, i) {
1049                 init_waitqueue_head(&scheduler->waitq[i]);
1050
1051                 param = kzalloc(sizeof(*param), GFP_KERNEL);
1052                 if (!param) {
1053                         ret = -ENOMEM;
1054                         goto err;
1055                 }
1056
1057                 param->gvt = gvt;
1058                 param->ring_id = i;
1059
1060                 scheduler->thread[i] = kthread_run(workload_thread, param,
1061                         "gvt workload %d", i);
1062                 if (IS_ERR(scheduler->thread[i])) {
1063                         gvt_err("fail to create workload thread\n");
1064                         ret = PTR_ERR(scheduler->thread[i]);
1065                         goto err;
1066                 }
1067
1068                 gvt->shadow_ctx_notifier_block[i].notifier_call =
1069                                         shadow_context_status_change;
1070                 atomic_notifier_chain_register(&engine->context_status_notifier,
1071                                         &gvt->shadow_ctx_notifier_block[i]);
1072         }
1073         return 0;
1074 err:
1075         intel_gvt_clean_workload_scheduler(gvt);
1076         kfree(param);
1077         param = NULL;
1078         return ret;
1079 }
1080
1081 static void
1082 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
1083 {
1084         struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1085         int i;
1086
1087         if (i915_vm_is_48bit(&i915_ppgtt->vm))
1088                 px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
1089         else {
1090                 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1091                         px_dma(i915_ppgtt->pdp.page_directory[i]) =
1092                                                 s->i915_context_pdps[i];
1093         }
1094 }
1095
1096 /**
1097  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1098  * @vgpu: a vGPU
1099  *
1100  * This function is called when a vGPU is being destroyed.
1101  *
1102  */
1103 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1104 {
1105         struct intel_vgpu_submission *s = &vgpu->submission;
1106
1107         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1108         i915_context_ppgtt_root_restore(s);
1109         i915_gem_context_put(s->shadow_ctx);
1110         kmem_cache_destroy(s->workloads);
1111 }
1112
1113
1114 /**
1115  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1116  * @vgpu: a vGPU
1117  * @engine_mask: engines expected to be reset
1118  *
1119  * This function is called when a vGPU is being destroyed.
1120  *
1121  */
1122 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1123                 unsigned long engine_mask)
1124 {
1125         struct intel_vgpu_submission *s = &vgpu->submission;
1126
1127         if (!s->active)
1128                 return;
1129
1130         intel_vgpu_clean_workloads(vgpu, engine_mask);
1131         s->ops->reset(vgpu, engine_mask);
1132 }
1133
1134 static void
1135 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
1136 {
1137         struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1138         int i;
1139
1140         if (i915_vm_is_48bit(&i915_ppgtt->vm))
1141                 s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
1142         else {
1143                 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1144                         s->i915_context_pdps[i] =
1145                                 px_dma(i915_ppgtt->pdp.page_directory[i]);
1146         }
1147 }
1148
1149 /**
1150  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1151  * @vgpu: a vGPU
1152  *
1153  * This function is called when a vGPU is being created.
1154  *
1155  * Returns:
1156  * Zero on success, negative error code if failed.
1157  *
1158  */
1159 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1160 {
1161         struct intel_vgpu_submission *s = &vgpu->submission;
1162         enum intel_engine_id i;
1163         struct intel_engine_cs *engine;
1164         int ret;
1165
1166         s->shadow_ctx = i915_gem_context_create_gvt(
1167                         &vgpu->gvt->dev_priv->drm);
1168         if (IS_ERR(s->shadow_ctx))
1169                 return PTR_ERR(s->shadow_ctx);
1170
1171         i915_context_ppgtt_root_save(s);
1172
1173         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1174
1175         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1176                                                   sizeof(struct intel_vgpu_workload), 0,
1177                                                   SLAB_HWCACHE_ALIGN,
1178                                                   offsetof(struct intel_vgpu_workload, rb_tail),
1179                                                   sizeof_field(struct intel_vgpu_workload, rb_tail),
1180                                                   NULL);
1181
1182         if (!s->workloads) {
1183                 ret = -ENOMEM;
1184                 goto out_shadow_ctx;
1185         }
1186
1187         for_each_engine(engine, vgpu->gvt->dev_priv, i)
1188                 INIT_LIST_HEAD(&s->workload_q_head[i]);
1189
1190         atomic_set(&s->running_workload_num, 0);
1191         bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1192
1193         return 0;
1194
1195 out_shadow_ctx:
1196         i915_gem_context_put(s->shadow_ctx);
1197         return ret;
1198 }
1199
1200 /**
1201  * intel_vgpu_select_submission_ops - select virtual submission interface
1202  * @vgpu: a vGPU
1203  * @engine_mask: either ALL_ENGINES or target engine mask
1204  * @interface: expected vGPU virtual submission interface
1205  *
1206  * This function is called when guest configures submission interface.
1207  *
1208  * Returns:
1209  * Zero on success, negative error code if failed.
1210  *
1211  */
1212 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1213                                      unsigned long engine_mask,
1214                                      unsigned int interface)
1215 {
1216         struct intel_vgpu_submission *s = &vgpu->submission;
1217         const struct intel_vgpu_submission_ops *ops[] = {
1218                 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1219                         &intel_vgpu_execlist_submission_ops,
1220         };
1221         int ret;
1222
1223         if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1224                 return -EINVAL;
1225
1226         if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1227                 return -EINVAL;
1228
1229         if (s->active)
1230                 s->ops->clean(vgpu, engine_mask);
1231
1232         if (interface == 0) {
1233                 s->ops = NULL;
1234                 s->virtual_submission_interface = 0;
1235                 s->active = false;
1236                 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1237                 return 0;
1238         }
1239
1240         ret = ops[interface]->init(vgpu, engine_mask);
1241         if (ret)
1242                 return ret;
1243
1244         s->ops = ops[interface];
1245         s->virtual_submission_interface = interface;
1246         s->active = true;
1247
1248         gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1249                         vgpu->id, s->ops->name);
1250
1251         return 0;
1252 }
1253
1254 /**
1255  * intel_vgpu_destroy_workload - destroy a vGPU workload
1256  * @workload: workload to destroy
1257  *
1258  * This function is called when destroy a vGPU workload.
1259  *
1260  */
1261 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1262 {
1263         struct intel_vgpu_submission *s = &workload->vgpu->submission;
1264
1265         if (workload->shadow_mm)
1266                 intel_vgpu_mm_put(workload->shadow_mm);
1267
1268         kmem_cache_free(s->workloads, workload);
1269 }
1270
1271 static struct intel_vgpu_workload *
1272 alloc_workload(struct intel_vgpu *vgpu)
1273 {
1274         struct intel_vgpu_submission *s = &vgpu->submission;
1275         struct intel_vgpu_workload *workload;
1276
1277         workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1278         if (!workload)
1279                 return ERR_PTR(-ENOMEM);
1280
1281         INIT_LIST_HEAD(&workload->list);
1282         INIT_LIST_HEAD(&workload->shadow_bb);
1283
1284         init_waitqueue_head(&workload->shadow_ctx_status_wq);
1285         atomic_set(&workload->shadow_ctx_active, 0);
1286
1287         workload->status = -EINPROGRESS;
1288         workload->vgpu = vgpu;
1289
1290         return workload;
1291 }
1292
1293 #define RING_CTX_OFF(x) \
1294         offsetof(struct execlist_ring_context, x)
1295
1296 static void read_guest_pdps(struct intel_vgpu *vgpu,
1297                 u64 ring_context_gpa, u32 pdp[8])
1298 {
1299         u64 gpa;
1300         int i;
1301
1302         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1303
1304         for (i = 0; i < 8; i++)
1305                 intel_gvt_hypervisor_read_gpa(vgpu,
1306                                 gpa + i * 8, &pdp[7 - i], 4);
1307 }
1308
1309 static int prepare_mm(struct intel_vgpu_workload *workload)
1310 {
1311         struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1312         struct intel_vgpu_mm *mm;
1313         struct intel_vgpu *vgpu = workload->vgpu;
1314         intel_gvt_gtt_type_t root_entry_type;
1315         u64 pdps[GVT_RING_CTX_NR_PDPS];
1316
1317         switch (desc->addressing_mode) {
1318         case 1: /* legacy 32-bit */
1319                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1320                 break;
1321         case 3: /* legacy 64-bit */
1322                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1323                 break;
1324         default:
1325                 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1326                 return -EINVAL;
1327         }
1328
1329         read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1330
1331         mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1332         if (IS_ERR(mm))
1333                 return PTR_ERR(mm);
1334
1335         workload->shadow_mm = mm;
1336         return 0;
1337 }
1338
1339 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1340                 ((a)->lrca == (b)->lrca))
1341
1342 #define get_last_workload(q) \
1343         (list_empty(q) ? NULL : container_of(q->prev, \
1344         struct intel_vgpu_workload, list))
1345 /**
1346  * intel_vgpu_create_workload - create a vGPU workload
1347  * @vgpu: a vGPU
1348  * @ring_id: ring index
1349  * @desc: a guest context descriptor
1350  *
1351  * This function is called when creating a vGPU workload.
1352  *
1353  * Returns:
1354  * struct intel_vgpu_workload * on success, negative error code in
1355  * pointer if failed.
1356  *
1357  */
1358 struct intel_vgpu_workload *
1359 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1360                            struct execlist_ctx_descriptor_format *desc)
1361 {
1362         struct intel_vgpu_submission *s = &vgpu->submission;
1363         struct list_head *q = workload_q_head(vgpu, ring_id);
1364         struct intel_vgpu_workload *last_workload = get_last_workload(q);
1365         struct intel_vgpu_workload *workload = NULL;
1366         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1367         u64 ring_context_gpa;
1368         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1369         int ret;
1370
1371         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1372                         (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1373         if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1374                 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1375                 return ERR_PTR(-EINVAL);
1376         }
1377
1378         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1379                         RING_CTX_OFF(ring_header.val), &head, 4);
1380
1381         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1382                         RING_CTX_OFF(ring_tail.val), &tail, 4);
1383
1384         head &= RB_HEAD_OFF_MASK;
1385         tail &= RB_TAIL_OFF_MASK;
1386
1387         if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
1388                 gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
1389                 gvt_dbg_el("ctx head %x real head %lx\n", head,
1390                                 last_workload->rb_tail);
1391                 /*
1392                  * cannot use guest context head pointer here,
1393                  * as it might not be updated at this time
1394                  */
1395                 head = last_workload->rb_tail;
1396         }
1397
1398         gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1399
1400         /* record some ring buffer register values for scan and shadow */
1401         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1402                         RING_CTX_OFF(rb_start.val), &start, 4);
1403         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1404                         RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1405         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1406                         RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1407
1408         workload = alloc_workload(vgpu);
1409         if (IS_ERR(workload))
1410                 return workload;
1411
1412         workload->ring_id = ring_id;
1413         workload->ctx_desc = *desc;
1414         workload->ring_context_gpa = ring_context_gpa;
1415         workload->rb_head = head;
1416         workload->rb_tail = tail;
1417         workload->rb_start = start;
1418         workload->rb_ctl = ctl;
1419
1420         if (ring_id == RCS) {
1421                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1422                         RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1423                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1424                         RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1425
1426                 workload->wa_ctx.indirect_ctx.guest_gma =
1427                         indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1428                 workload->wa_ctx.indirect_ctx.size =
1429                         (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1430                         CACHELINE_BYTES;
1431                 workload->wa_ctx.per_ctx.guest_gma =
1432                         per_ctx & PER_CTX_ADDR_MASK;
1433                 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1434         }
1435
1436         gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1437                         workload, ring_id, head, tail, start, ctl);
1438
1439         ret = prepare_mm(workload);
1440         if (ret) {
1441                 kmem_cache_free(s->workloads, workload);
1442                 return ERR_PTR(ret);
1443         }
1444
1445         /* Only scan and shadow the first workload in the queue
1446          * as there is only one pre-allocated buf-obj for shadow.
1447          */
1448         if (list_empty(workload_q_head(vgpu, ring_id))) {
1449                 intel_runtime_pm_get(dev_priv);
1450                 mutex_lock(&dev_priv->drm.struct_mutex);
1451                 ret = intel_gvt_scan_and_shadow_workload(workload);
1452                 mutex_unlock(&dev_priv->drm.struct_mutex);
1453                 intel_runtime_pm_put(dev_priv);
1454         }
1455
1456         if (ret && (vgpu_is_vm_unhealthy(ret))) {
1457                 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1458                 intel_vgpu_destroy_workload(workload);
1459                 return ERR_PTR(ret);
1460         }
1461
1462         return workload;
1463 }
1464
1465 /**
1466  * intel_vgpu_queue_workload - Qeue a vGPU workload
1467  * @workload: the workload to queue in
1468  */
1469 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1470 {
1471         list_add_tail(&workload->list,
1472                 workload_q_head(workload->vgpu, workload->ring_id));
1473         intel_gvt_kick_schedule(workload->vgpu->gvt);
1474         wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);
1475 }