2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Zhi Wang <zhi.a.wang@intel.com>
27 * Ping Gao <ping.a.gao@intel.com>
28 * Tina Zhang <tina.zhang@intel.com>
29 * Chanbin Du <changbin.du@intel.com>
30 * Min He <min.he@intel.com>
31 * Bing Niu <bing.niu@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
36 #ifndef _GVT_SCHEDULER_H_
37 #define _GVT_SCHEDULER_H_
39 struct intel_gvt_workload_scheduler {
40 struct intel_vgpu *current_vgpu;
41 struct intel_vgpu *next_vgpu;
42 struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
45 wait_queue_head_t workload_complete_wq;
46 struct task_struct *thread[I915_NUM_ENGINES];
47 wait_queue_head_t waitq[I915_NUM_ENGINES];
50 struct intel_gvt_sched_policy_ops *sched_ops;
53 #define INDIRECT_CTX_ADDR_MASK 0xffffffc0
54 #define INDIRECT_CTX_SIZE_MASK 0x3f
55 struct shadow_indirect_ctx {
56 struct drm_i915_gem_object *obj;
57 unsigned long guest_gma;
58 unsigned long shadow_gma;
63 #define PER_CTX_ADDR_MASK 0xfffff000
64 struct shadow_per_ctx {
65 unsigned long guest_gma;
66 unsigned long shadow_gma;
69 struct intel_shadow_wa_ctx {
70 struct intel_vgpu_workload *workload;
71 struct shadow_indirect_ctx indirect_ctx;
72 struct shadow_per_ctx per_ctx;
76 struct intel_vgpu_workload {
77 struct intel_vgpu *vgpu;
79 struct drm_i915_gem_request *req;
80 /* if this workload has been dispatched to i915? */
84 struct intel_vgpu_mm *shadow_mm;
86 /* different submission model may need different handler */
87 int (*prepare)(struct intel_vgpu_workload *);
88 int (*complete)(struct intel_vgpu_workload *);
89 struct list_head list;
91 DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
92 void *shadow_ring_buffer_va;
94 /* execlist context information */
95 struct execlist_ctx_descriptor_format ctx_desc;
96 struct execlist_ring_context *ring_context;
97 unsigned long rb_head, rb_tail, rb_ctl, rb_start, rb_len;
99 struct intel_vgpu_elsp_dwords elsp_dwords;
100 bool emulate_schedule_in;
101 atomic_t shadow_ctx_active;
102 wait_queue_head_t shadow_ctx_status_wq;
103 u64 ring_context_gpa;
105 /* shadow batch buffer */
106 struct list_head shadow_bb;
107 struct intel_shadow_wa_ctx wa_ctx;
110 /* Intel shadow batch buffer is a i915 gem object */
111 struct intel_shadow_bb_entry {
112 struct list_head list;
113 struct drm_i915_gem_object *obj;
116 u32 *bb_start_cmd_va;
119 #define workload_q_head(vgpu, ring_id) \
120 (&(vgpu->workload_q_head[ring_id]))
122 #define queue_workload(workload) do { \
123 list_add_tail(&workload->list, \
124 workload_q_head(workload->vgpu, workload->ring_id)); \
125 wake_up(&workload->vgpu->gvt-> \
126 scheduler.waitq[workload->ring_id]); \
129 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
131 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
133 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu);
135 int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu);
137 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu);