2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v)
51 return v ? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor *minor,
61 struct drm_info_node *node;
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
71 node->info_ent = (void *) key;
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
80 static int i915_capabilities(struct seq_file *m, void *data)
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
99 if (obj->user_pin_count > 0)
101 else if (i915_gem_obj_is_pinned(obj))
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
109 switch (obj->tiling_mode) {
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
119 return obj->has_global_gtt_mapping ? "g" : " ";
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
125 struct i915_vma *vma;
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
143 seq_printf(m, " (name: %d)", obj->base.name);
144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
164 if (obj->pin_mappable)
166 if (obj->fault_mappable)
169 seq_printf(m, " (%s mappable)", s);
171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
175 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
182 static int i915_gem_object_list_info(struct seq_file *m, void *data)
184 struct drm_info_node *node = (struct drm_info_node *) m->private;
185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
187 struct drm_device *dev = node->minor->dev;
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
190 struct i915_vma *vma;
191 size_t total_obj_size, total_gtt_size;
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
198 /* FIXME: the user of this interface might want more than just GGTT */
201 seq_puts(m, "Active:\n");
202 head = &vm->active_list;
205 seq_puts(m, "Inactive:\n");
206 head = &vm->inactive_list;
209 mutex_unlock(&dev->struct_mutex);
213 total_obj_size = total_gtt_size = count = 0;
214 list_for_each_entry(vma, head, mm_list) {
216 describe_obj(m, vma->obj);
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
222 mutex_unlock(&dev->struct_mutex);
224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
229 static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
232 struct drm_i915_gem_object *a =
233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
234 struct drm_i915_gem_object *b =
235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
237 return a->stolen->start - b->stolen->start;
240 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
259 list_add(&obj->obj_exec_link, &stolen);
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
269 list_add(&obj->obj_exec_link, &stolen);
271 total_obj_size += obj->base.size;
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
279 describe_obj(m, obj);
281 list_del_init(&obj->obj_exec_link);
283 mutex_unlock(&dev->struct_mutex);
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
290 #define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
292 size += i915_gem_obj_ggtt_size(obj); \
294 if (obj->map_and_fenceable) { \
295 mappable_size += i915_gem_obj_ggtt_size(obj); \
302 struct drm_i915_file_private *file_priv;
304 size_t total, unbound;
305 size_t global, shared;
306 size_t active, inactive;
309 static int per_file_stats(int id, void *ptr, void *data)
311 struct drm_i915_gem_object *obj = ptr;
312 struct file_stats *stats = data;
313 struct i915_vma *vma;
316 stats->total += obj->base.size;
318 if (obj->base.name || obj->base.dma_buf)
319 stats->shared += obj->base.size;
321 if (USES_FULL_PPGTT(obj->base.dev)) {
322 list_for_each_entry(vma, &obj->vma_list, vma_link) {
323 struct i915_hw_ppgtt *ppgtt;
325 if (!drm_mm_node_allocated(&vma->node))
328 if (i915_is_ggtt(vma->vm)) {
329 stats->global += obj->base.size;
333 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
334 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
337 if (obj->ring) /* XXX per-vma statistic */
338 stats->active += obj->base.size;
340 stats->inactive += obj->base.size;
345 if (i915_gem_obj_ggtt_bound(obj)) {
346 stats->global += obj->base.size;
348 stats->active += obj->base.size;
350 stats->inactive += obj->base.size;
355 if (!list_empty(&obj->global_list))
356 stats->unbound += obj->base.size;
361 #define count_vmas(list, member) do { \
362 list_for_each_entry(vma, list, member) { \
363 size += i915_gem_obj_ggtt_size(vma->obj); \
365 if (vma->obj->map_and_fenceable) { \
366 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
372 static int i915_gem_object_info(struct seq_file *m, void* data)
374 struct drm_info_node *node = (struct drm_info_node *) m->private;
375 struct drm_device *dev = node->minor->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 u32 count, mappable_count, purgeable_count;
378 size_t size, mappable_size, purgeable_size;
379 struct drm_i915_gem_object *obj;
380 struct i915_address_space *vm = &dev_priv->gtt.base;
381 struct drm_file *file;
382 struct i915_vma *vma;
385 ret = mutex_lock_interruptible(&dev->struct_mutex);
389 seq_printf(m, "%u objects, %zu bytes\n",
390 dev_priv->mm.object_count,
391 dev_priv->mm.object_memory);
393 size = count = mappable_size = mappable_count = 0;
394 count_objects(&dev_priv->mm.bound_list, global_list);
395 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
396 count, mappable_count, size, mappable_size);
398 size = count = mappable_size = mappable_count = 0;
399 count_vmas(&vm->active_list, mm_list);
400 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
401 count, mappable_count, size, mappable_size);
403 size = count = mappable_size = mappable_count = 0;
404 count_vmas(&vm->inactive_list, mm_list);
405 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
406 count, mappable_count, size, mappable_size);
408 size = count = purgeable_size = purgeable_count = 0;
409 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
410 size += obj->base.size, ++count;
411 if (obj->madv == I915_MADV_DONTNEED)
412 purgeable_size += obj->base.size, ++purgeable_count;
414 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
416 size = count = mappable_size = mappable_count = 0;
417 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
418 if (obj->fault_mappable) {
419 size += i915_gem_obj_ggtt_size(obj);
422 if (obj->pin_mappable) {
423 mappable_size += i915_gem_obj_ggtt_size(obj);
426 if (obj->madv == I915_MADV_DONTNEED) {
427 purgeable_size += obj->base.size;
431 seq_printf(m, "%u purgeable objects, %zu bytes\n",
432 purgeable_count, purgeable_size);
433 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
434 mappable_count, mappable_size);
435 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 seq_printf(m, "%zu [%lu] gtt total\n",
439 dev_priv->gtt.base.total,
440 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
443 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
444 struct file_stats stats;
445 struct task_struct *task;
447 memset(&stats, 0, sizeof(stats));
448 stats.file_priv = file->driver_priv;
449 idr_for_each(&file->object_idr, per_file_stats, &stats);
451 * Although we have a valid reference on file->pid, that does
452 * not guarantee that the task_struct who called get_pid() is
453 * still alive (e.g. get_pid(current) => fork() => exit()).
454 * Therefore, we need to protect this ->comm access using RCU.
457 task = pid_task(file->pid, PIDTYPE_PID);
458 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
459 task ? task->comm : "<unknown>",
470 mutex_unlock(&dev->struct_mutex);
475 static int i915_gem_gtt_info(struct seq_file *m, void *data)
477 struct drm_info_node *node = (struct drm_info_node *) m->private;
478 struct drm_device *dev = node->minor->dev;
479 uintptr_t list = (uintptr_t) node->info_ent->data;
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_i915_gem_object *obj;
482 size_t total_obj_size, total_gtt_size;
485 ret = mutex_lock_interruptible(&dev->struct_mutex);
489 total_obj_size = total_gtt_size = count = 0;
490 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
491 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
495 describe_obj(m, obj);
497 total_obj_size += obj->base.size;
498 total_gtt_size += i915_gem_obj_ggtt_size(obj);
502 mutex_unlock(&dev->struct_mutex);
504 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
505 count, total_obj_size, total_gtt_size);
510 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
512 struct drm_info_node *node = (struct drm_info_node *) m->private;
513 struct drm_device *dev = node->minor->dev;
515 struct intel_crtc *crtc;
517 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
518 const char pipe = pipe_name(crtc->pipe);
519 const char plane = plane_name(crtc->plane);
520 struct intel_unpin_work *work;
522 spin_lock_irqsave(&dev->event_lock, flags);
523 work = crtc->unpin_work;
525 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
528 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
529 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
532 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
535 if (work->enable_stall_check)
536 seq_puts(m, "Stall check enabled, ");
538 seq_puts(m, "Stall check waiting for page flip ioctl, ");
539 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
541 if (work->old_fb_obj) {
542 struct drm_i915_gem_object *obj = work->old_fb_obj;
544 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
545 i915_gem_obj_ggtt_offset(obj));
547 if (work->pending_flip_obj) {
548 struct drm_i915_gem_object *obj = work->pending_flip_obj;
550 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
551 i915_gem_obj_ggtt_offset(obj));
554 spin_unlock_irqrestore(&dev->event_lock, flags);
560 static int i915_gem_request_info(struct seq_file *m, void *data)
562 struct drm_info_node *node = (struct drm_info_node *) m->private;
563 struct drm_device *dev = node->minor->dev;
564 struct drm_i915_private *dev_priv = dev->dev_private;
565 struct intel_ring_buffer *ring;
566 struct drm_i915_gem_request *gem_request;
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
574 for_each_ring(ring, dev_priv, i) {
575 if (list_empty(&ring->request_list))
578 seq_printf(m, "%s requests:\n", ring->name);
579 list_for_each_entry(gem_request,
582 seq_printf(m, " %d @ %d\n",
584 (int) (jiffies - gem_request->emitted_jiffies));
588 mutex_unlock(&dev->struct_mutex);
591 seq_puts(m, "No requests\n");
596 static void i915_ring_seqno_info(struct seq_file *m,
597 struct intel_ring_buffer *ring)
599 if (ring->get_seqno) {
600 seq_printf(m, "Current sequence (%s): %u\n",
601 ring->name, ring->get_seqno(ring, false));
605 static int i915_gem_seqno_info(struct seq_file *m, void *data)
607 struct drm_info_node *node = (struct drm_info_node *) m->private;
608 struct drm_device *dev = node->minor->dev;
609 struct drm_i915_private *dev_priv = dev->dev_private;
610 struct intel_ring_buffer *ring;
613 ret = mutex_lock_interruptible(&dev->struct_mutex);
616 intel_runtime_pm_get(dev_priv);
618 for_each_ring(ring, dev_priv, i)
619 i915_ring_seqno_info(m, ring);
621 intel_runtime_pm_put(dev_priv);
622 mutex_unlock(&dev->struct_mutex);
628 static int i915_interrupt_info(struct seq_file *m, void *data)
630 struct drm_info_node *node = (struct drm_info_node *) m->private;
631 struct drm_device *dev = node->minor->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 struct intel_ring_buffer *ring;
636 ret = mutex_lock_interruptible(&dev->struct_mutex);
639 intel_runtime_pm_get(dev_priv);
641 if (INTEL_INFO(dev)->gen >= 8) {
642 seq_printf(m, "Master Interrupt Control:\t%08x\n",
643 I915_READ(GEN8_MASTER_IRQ));
645 for (i = 0; i < 4; i++) {
646 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
647 i, I915_READ(GEN8_GT_IMR(i)));
648 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
649 i, I915_READ(GEN8_GT_IIR(i)));
650 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
651 i, I915_READ(GEN8_GT_IER(i)));
654 for_each_pipe(pipe) {
655 seq_printf(m, "Pipe %c IMR:\t%08x\n",
657 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
658 seq_printf(m, "Pipe %c IIR:\t%08x\n",
660 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
661 seq_printf(m, "Pipe %c IER:\t%08x\n",
663 I915_READ(GEN8_DE_PIPE_IER(pipe)));
666 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
667 I915_READ(GEN8_DE_PORT_IMR));
668 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
669 I915_READ(GEN8_DE_PORT_IIR));
670 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
671 I915_READ(GEN8_DE_PORT_IER));
673 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
674 I915_READ(GEN8_DE_MISC_IMR));
675 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
676 I915_READ(GEN8_DE_MISC_IIR));
677 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
678 I915_READ(GEN8_DE_MISC_IER));
680 seq_printf(m, "PCU interrupt mask:\t%08x\n",
681 I915_READ(GEN8_PCU_IMR));
682 seq_printf(m, "PCU interrupt identity:\t%08x\n",
683 I915_READ(GEN8_PCU_IIR));
684 seq_printf(m, "PCU interrupt enable:\t%08x\n",
685 I915_READ(GEN8_PCU_IER));
686 } else if (IS_VALLEYVIEW(dev)) {
687 seq_printf(m, "Display IER:\t%08x\n",
689 seq_printf(m, "Display IIR:\t%08x\n",
691 seq_printf(m, "Display IIR_RW:\t%08x\n",
692 I915_READ(VLV_IIR_RW));
693 seq_printf(m, "Display IMR:\t%08x\n",
696 seq_printf(m, "Pipe %c stat:\t%08x\n",
698 I915_READ(PIPESTAT(pipe)));
700 seq_printf(m, "Master IER:\t%08x\n",
701 I915_READ(VLV_MASTER_IER));
703 seq_printf(m, "Render IER:\t%08x\n",
705 seq_printf(m, "Render IIR:\t%08x\n",
707 seq_printf(m, "Render IMR:\t%08x\n",
710 seq_printf(m, "PM IER:\t\t%08x\n",
711 I915_READ(GEN6_PMIER));
712 seq_printf(m, "PM IIR:\t\t%08x\n",
713 I915_READ(GEN6_PMIIR));
714 seq_printf(m, "PM IMR:\t\t%08x\n",
715 I915_READ(GEN6_PMIMR));
717 seq_printf(m, "Port hotplug:\t%08x\n",
718 I915_READ(PORT_HOTPLUG_EN));
719 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
720 I915_READ(VLV_DPFLIPSTAT));
721 seq_printf(m, "DPINVGTT:\t%08x\n",
722 I915_READ(DPINVGTT));
724 } else if (!HAS_PCH_SPLIT(dev)) {
725 seq_printf(m, "Interrupt enable: %08x\n",
727 seq_printf(m, "Interrupt identity: %08x\n",
729 seq_printf(m, "Interrupt mask: %08x\n",
732 seq_printf(m, "Pipe %c stat: %08x\n",
734 I915_READ(PIPESTAT(pipe)));
736 seq_printf(m, "North Display Interrupt enable: %08x\n",
738 seq_printf(m, "North Display Interrupt identity: %08x\n",
740 seq_printf(m, "North Display Interrupt mask: %08x\n",
742 seq_printf(m, "South Display Interrupt enable: %08x\n",
744 seq_printf(m, "South Display Interrupt identity: %08x\n",
746 seq_printf(m, "South Display Interrupt mask: %08x\n",
748 seq_printf(m, "Graphics Interrupt enable: %08x\n",
750 seq_printf(m, "Graphics Interrupt identity: %08x\n",
752 seq_printf(m, "Graphics Interrupt mask: %08x\n",
755 for_each_ring(ring, dev_priv, i) {
756 if (INTEL_INFO(dev)->gen >= 6) {
758 "Graphics Interrupt mask (%s): %08x\n",
759 ring->name, I915_READ_IMR(ring));
761 i915_ring_seqno_info(m, ring);
763 intel_runtime_pm_put(dev_priv);
764 mutex_unlock(&dev->struct_mutex);
769 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
771 struct drm_info_node *node = (struct drm_info_node *) m->private;
772 struct drm_device *dev = node->minor->dev;
773 struct drm_i915_private *dev_priv = dev->dev_private;
776 ret = mutex_lock_interruptible(&dev->struct_mutex);
780 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
781 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
782 for (i = 0; i < dev_priv->num_fence_regs; i++) {
783 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
785 seq_printf(m, "Fence %d, pin count = %d, object = ",
786 i, dev_priv->fence_regs[i].pin_count);
788 seq_puts(m, "unused");
790 describe_obj(m, obj);
794 mutex_unlock(&dev->struct_mutex);
798 static int i915_hws_info(struct seq_file *m, void *data)
800 struct drm_info_node *node = (struct drm_info_node *) m->private;
801 struct drm_device *dev = node->minor->dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 struct intel_ring_buffer *ring;
807 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
808 hws = ring->status_page.page_addr;
812 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
813 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
815 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
821 i915_error_state_write(struct file *filp,
822 const char __user *ubuf,
826 struct i915_error_state_file_priv *error_priv = filp->private_data;
827 struct drm_device *dev = error_priv->dev;
830 DRM_DEBUG_DRIVER("Resetting error state\n");
832 ret = mutex_lock_interruptible(&dev->struct_mutex);
836 i915_destroy_error_state(dev);
837 mutex_unlock(&dev->struct_mutex);
842 static int i915_error_state_open(struct inode *inode, struct file *file)
844 struct drm_device *dev = inode->i_private;
845 struct i915_error_state_file_priv *error_priv;
847 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
851 error_priv->dev = dev;
853 i915_error_state_get(dev, error_priv);
855 file->private_data = error_priv;
860 static int i915_error_state_release(struct inode *inode, struct file *file)
862 struct i915_error_state_file_priv *error_priv = file->private_data;
864 i915_error_state_put(error_priv);
870 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
871 size_t count, loff_t *pos)
873 struct i915_error_state_file_priv *error_priv = file->private_data;
874 struct drm_i915_error_state_buf error_str;
876 ssize_t ret_count = 0;
879 ret = i915_error_state_buf_init(&error_str, count, *pos);
883 ret = i915_error_state_to_str(&error_str, error_priv);
887 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
894 *pos = error_str.start + ret_count;
896 i915_error_state_buf_release(&error_str);
897 return ret ?: ret_count;
900 static const struct file_operations i915_error_state_fops = {
901 .owner = THIS_MODULE,
902 .open = i915_error_state_open,
903 .read = i915_error_state_read,
904 .write = i915_error_state_write,
905 .llseek = default_llseek,
906 .release = i915_error_state_release,
910 i915_next_seqno_get(void *data, u64 *val)
912 struct drm_device *dev = data;
913 struct drm_i915_private *dev_priv = dev->dev_private;
916 ret = mutex_lock_interruptible(&dev->struct_mutex);
920 *val = dev_priv->next_seqno;
921 mutex_unlock(&dev->struct_mutex);
927 i915_next_seqno_set(void *data, u64 val)
929 struct drm_device *dev = data;
932 ret = mutex_lock_interruptible(&dev->struct_mutex);
936 ret = i915_gem_set_seqno(dev, val);
937 mutex_unlock(&dev->struct_mutex);
942 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
943 i915_next_seqno_get, i915_next_seqno_set,
946 static int i915_rstdby_delays(struct seq_file *m, void *unused)
948 struct drm_info_node *node = (struct drm_info_node *) m->private;
949 struct drm_device *dev = node->minor->dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
954 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 intel_runtime_pm_get(dev_priv);
959 crstanddelay = I915_READ16(CRSTANDVID);
961 intel_runtime_pm_put(dev_priv);
962 mutex_unlock(&dev->struct_mutex);
964 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
969 static int i915_frequency_info(struct seq_file *m, void *unused)
971 struct drm_info_node *node = (struct drm_info_node *) m->private;
972 struct drm_device *dev = node->minor->dev;
973 struct drm_i915_private *dev_priv = dev->dev_private;
976 intel_runtime_pm_get(dev_priv);
978 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
981 u16 rgvswctl = I915_READ16(MEMSWCTL);
982 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
984 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
985 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
986 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
988 seq_printf(m, "Current P-state: %d\n",
989 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
990 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
991 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
992 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
993 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
994 u32 rpmodectl, rpinclimit, rpdeclimit;
995 u32 rpstat, cagf, reqf;
996 u32 rpupei, rpcurup, rpprevup;
997 u32 rpdownei, rpcurdown, rpprevdown;
1000 /* RPSTAT1 is in the GT power well */
1001 ret = mutex_lock_interruptible(&dev->struct_mutex);
1005 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1007 reqf = I915_READ(GEN6_RPNSWREQ);
1008 reqf &= ~GEN6_TURBO_DISABLE;
1009 if (IS_HASWELL(dev))
1013 reqf *= GT_FREQUENCY_MULTIPLIER;
1015 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1016 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1017 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1019 rpstat = I915_READ(GEN6_RPSTAT1);
1020 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1021 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1022 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1023 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1024 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1025 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1026 if (IS_HASWELL(dev))
1027 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1029 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1030 cagf *= GT_FREQUENCY_MULTIPLIER;
1032 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1033 mutex_unlock(&dev->struct_mutex);
1035 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1036 I915_READ(GEN6_PMIER),
1037 I915_READ(GEN6_PMIMR),
1038 I915_READ(GEN6_PMISR),
1039 I915_READ(GEN6_PMIIR),
1040 I915_READ(GEN6_PMINTRMSK));
1041 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1042 seq_printf(m, "Render p-state ratio: %d\n",
1043 (gt_perf_status & 0xff00) >> 8);
1044 seq_printf(m, "Render p-state VID: %d\n",
1045 gt_perf_status & 0xff);
1046 seq_printf(m, "Render p-state limit: %d\n",
1047 rp_state_limits & 0xff);
1048 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1049 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1050 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1051 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1052 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1053 seq_printf(m, "CAGF: %dMHz\n", cagf);
1054 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1055 GEN6_CURICONT_MASK);
1056 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1057 GEN6_CURBSYTAVG_MASK);
1058 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1059 GEN6_CURBSYTAVG_MASK);
1060 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1062 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1063 GEN6_CURBSYTAVG_MASK);
1064 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1065 GEN6_CURBSYTAVG_MASK);
1067 max_freq = (rp_state_cap & 0xff0000) >> 16;
1068 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1069 max_freq * GT_FREQUENCY_MULTIPLIER);
1071 max_freq = (rp_state_cap & 0xff00) >> 8;
1072 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1073 max_freq * GT_FREQUENCY_MULTIPLIER);
1075 max_freq = rp_state_cap & 0xff;
1076 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1077 max_freq * GT_FREQUENCY_MULTIPLIER);
1079 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1080 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1081 } else if (IS_VALLEYVIEW(dev)) {
1084 mutex_lock(&dev_priv->rps.hw_lock);
1085 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1086 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1087 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1089 val = valleyview_rps_max_freq(dev_priv);
1090 seq_printf(m, "max GPU freq: %d MHz\n",
1091 vlv_gpu_freq(dev_priv, val));
1093 val = valleyview_rps_min_freq(dev_priv);
1094 seq_printf(m, "min GPU freq: %d MHz\n",
1095 vlv_gpu_freq(dev_priv, val));
1097 seq_printf(m, "current GPU freq: %d MHz\n",
1098 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1099 mutex_unlock(&dev_priv->rps.hw_lock);
1101 seq_puts(m, "no P-state info available\n");
1105 intel_runtime_pm_put(dev_priv);
1109 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1111 struct drm_info_node *node = (struct drm_info_node *) m->private;
1112 struct drm_device *dev = node->minor->dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1117 ret = mutex_lock_interruptible(&dev->struct_mutex);
1120 intel_runtime_pm_get(dev_priv);
1122 for (i = 0; i < 16; i++) {
1123 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1124 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1125 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1128 intel_runtime_pm_put(dev_priv);
1130 mutex_unlock(&dev->struct_mutex);
1135 static inline int MAP_TO_MV(int map)
1137 return 1250 - (map * 25);
1140 static int i915_inttoext_table(struct seq_file *m, void *unused)
1142 struct drm_info_node *node = (struct drm_info_node *) m->private;
1143 struct drm_device *dev = node->minor->dev;
1144 struct drm_i915_private *dev_priv = dev->dev_private;
1148 ret = mutex_lock_interruptible(&dev->struct_mutex);
1151 intel_runtime_pm_get(dev_priv);
1153 for (i = 1; i <= 32; i++) {
1154 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1155 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1158 intel_runtime_pm_put(dev_priv);
1159 mutex_unlock(&dev->struct_mutex);
1164 static int ironlake_drpc_info(struct seq_file *m)
1166 struct drm_info_node *node = (struct drm_info_node *) m->private;
1167 struct drm_device *dev = node->minor->dev;
1168 struct drm_i915_private *dev_priv = dev->dev_private;
1169 u32 rgvmodectl, rstdbyctl;
1173 ret = mutex_lock_interruptible(&dev->struct_mutex);
1176 intel_runtime_pm_get(dev_priv);
1178 rgvmodectl = I915_READ(MEMMODECTL);
1179 rstdbyctl = I915_READ(RSTDBYCTL);
1180 crstandvid = I915_READ16(CRSTANDVID);
1182 intel_runtime_pm_put(dev_priv);
1183 mutex_unlock(&dev->struct_mutex);
1185 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1187 seq_printf(m, "Boost freq: %d\n",
1188 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1189 MEMMODE_BOOST_FREQ_SHIFT);
1190 seq_printf(m, "HW control enabled: %s\n",
1191 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1192 seq_printf(m, "SW control enabled: %s\n",
1193 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1194 seq_printf(m, "Gated voltage change: %s\n",
1195 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1196 seq_printf(m, "Starting frequency: P%d\n",
1197 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1198 seq_printf(m, "Max P-state: P%d\n",
1199 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1200 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1201 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1202 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1203 seq_printf(m, "Render standby enabled: %s\n",
1204 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1205 seq_puts(m, "Current RS state: ");
1206 switch (rstdbyctl & RSX_STATUS_MASK) {
1208 seq_puts(m, "on\n");
1210 case RSX_STATUS_RC1:
1211 seq_puts(m, "RC1\n");
1213 case RSX_STATUS_RC1E:
1214 seq_puts(m, "RC1E\n");
1216 case RSX_STATUS_RS1:
1217 seq_puts(m, "RS1\n");
1219 case RSX_STATUS_RS2:
1220 seq_puts(m, "RS2 (RC6)\n");
1222 case RSX_STATUS_RS3:
1223 seq_puts(m, "RC3 (RC6+)\n");
1226 seq_puts(m, "unknown\n");
1233 static int vlv_drpc_info(struct seq_file *m)
1236 struct drm_info_node *node = (struct drm_info_node *) m->private;
1237 struct drm_device *dev = node->minor->dev;
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239 u32 rpmodectl1, rcctl1;
1240 unsigned fw_rendercount = 0, fw_mediacount = 0;
1242 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1243 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1245 seq_printf(m, "Video Turbo Mode: %s\n",
1246 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1247 seq_printf(m, "Turbo enabled: %s\n",
1248 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1249 seq_printf(m, "HW control enabled: %s\n",
1250 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1251 seq_printf(m, "SW control enabled: %s\n",
1252 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1253 GEN6_RP_MEDIA_SW_MODE));
1254 seq_printf(m, "RC6 Enabled: %s\n",
1255 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1256 GEN6_RC_CTL_EI_MODE(1))));
1257 seq_printf(m, "Render Power Well: %s\n",
1258 (I915_READ(VLV_GTLC_PW_STATUS) &
1259 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1260 seq_printf(m, "Media Power Well: %s\n",
1261 (I915_READ(VLV_GTLC_PW_STATUS) &
1262 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1264 spin_lock_irq(&dev_priv->uncore.lock);
1265 fw_rendercount = dev_priv->uncore.fw_rendercount;
1266 fw_mediacount = dev_priv->uncore.fw_mediacount;
1267 spin_unlock_irq(&dev_priv->uncore.lock);
1269 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1270 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1277 static int gen6_drpc_info(struct seq_file *m)
1280 struct drm_info_node *node = (struct drm_info_node *) m->private;
1281 struct drm_device *dev = node->minor->dev;
1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1284 unsigned forcewake_count;
1287 ret = mutex_lock_interruptible(&dev->struct_mutex);
1290 intel_runtime_pm_get(dev_priv);
1292 spin_lock_irq(&dev_priv->uncore.lock);
1293 forcewake_count = dev_priv->uncore.forcewake_count;
1294 spin_unlock_irq(&dev_priv->uncore.lock);
1296 if (forcewake_count) {
1297 seq_puts(m, "RC information inaccurate because somebody "
1298 "holds a forcewake reference \n");
1300 /* NB: we cannot use forcewake, else we read the wrong values */
1301 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1303 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1306 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1307 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1309 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1310 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1311 mutex_unlock(&dev->struct_mutex);
1312 mutex_lock(&dev_priv->rps.hw_lock);
1313 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1314 mutex_unlock(&dev_priv->rps.hw_lock);
1316 intel_runtime_pm_put(dev_priv);
1318 seq_printf(m, "Video Turbo Mode: %s\n",
1319 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1320 seq_printf(m, "HW control enabled: %s\n",
1321 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1322 seq_printf(m, "SW control enabled: %s\n",
1323 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1324 GEN6_RP_MEDIA_SW_MODE));
1325 seq_printf(m, "RC1e Enabled: %s\n",
1326 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1327 seq_printf(m, "RC6 Enabled: %s\n",
1328 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1329 seq_printf(m, "Deep RC6 Enabled: %s\n",
1330 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1331 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1332 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1333 seq_puts(m, "Current RC state: ");
1334 switch (gt_core_status & GEN6_RCn_MASK) {
1336 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1337 seq_puts(m, "Core Power Down\n");
1339 seq_puts(m, "on\n");
1342 seq_puts(m, "RC3\n");
1345 seq_puts(m, "RC6\n");
1348 seq_puts(m, "RC7\n");
1351 seq_puts(m, "Unknown\n");
1355 seq_printf(m, "Core Power Down: %s\n",
1356 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1358 /* Not exactly sure what this is */
1359 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1360 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1361 seq_printf(m, "RC6 residency since boot: %u\n",
1362 I915_READ(GEN6_GT_GFX_RC6));
1363 seq_printf(m, "RC6+ residency since boot: %u\n",
1364 I915_READ(GEN6_GT_GFX_RC6p));
1365 seq_printf(m, "RC6++ residency since boot: %u\n",
1366 I915_READ(GEN6_GT_GFX_RC6pp));
1368 seq_printf(m, "RC6 voltage: %dmV\n",
1369 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1370 seq_printf(m, "RC6+ voltage: %dmV\n",
1371 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1372 seq_printf(m, "RC6++ voltage: %dmV\n",
1373 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1377 static int i915_drpc_info(struct seq_file *m, void *unused)
1379 struct drm_info_node *node = (struct drm_info_node *) m->private;
1380 struct drm_device *dev = node->minor->dev;
1382 if (IS_VALLEYVIEW(dev))
1383 return vlv_drpc_info(m);
1384 else if (IS_GEN6(dev) || IS_GEN7(dev))
1385 return gen6_drpc_info(m);
1387 return ironlake_drpc_info(m);
1390 static int i915_fbc_status(struct seq_file *m, void *unused)
1392 struct drm_info_node *node = (struct drm_info_node *) m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 struct drm_i915_private *dev_priv = dev->dev_private;
1396 if (!HAS_FBC(dev)) {
1397 seq_puts(m, "FBC unsupported on this chipset\n");
1401 intel_runtime_pm_get(dev_priv);
1403 if (intel_fbc_enabled(dev)) {
1404 seq_puts(m, "FBC enabled\n");
1406 seq_puts(m, "FBC disabled: ");
1407 switch (dev_priv->fbc.no_fbc_reason) {
1409 seq_puts(m, "FBC actived, but currently disabled in hardware");
1411 case FBC_UNSUPPORTED:
1412 seq_puts(m, "unsupported by this chipset");
1415 seq_puts(m, "no outputs");
1417 case FBC_STOLEN_TOO_SMALL:
1418 seq_puts(m, "not enough stolen memory");
1420 case FBC_UNSUPPORTED_MODE:
1421 seq_puts(m, "mode not supported");
1423 case FBC_MODE_TOO_LARGE:
1424 seq_puts(m, "mode too large");
1427 seq_puts(m, "FBC unsupported on plane");
1430 seq_puts(m, "scanout buffer not tiled");
1432 case FBC_MULTIPLE_PIPES:
1433 seq_puts(m, "multiple pipes are enabled");
1435 case FBC_MODULE_PARAM:
1436 seq_puts(m, "disabled per module param (default off)");
1438 case FBC_CHIP_DEFAULT:
1439 seq_puts(m, "disabled per chip default");
1442 seq_puts(m, "unknown reason");
1447 intel_runtime_pm_put(dev_priv);
1452 static int i915_ips_status(struct seq_file *m, void *unused)
1454 struct drm_info_node *node = (struct drm_info_node *) m->private;
1455 struct drm_device *dev = node->minor->dev;
1456 struct drm_i915_private *dev_priv = dev->dev_private;
1458 if (!HAS_IPS(dev)) {
1459 seq_puts(m, "not supported\n");
1463 intel_runtime_pm_get(dev_priv);
1465 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1466 seq_puts(m, "enabled\n");
1468 seq_puts(m, "disabled\n");
1470 intel_runtime_pm_put(dev_priv);
1475 static int i915_sr_status(struct seq_file *m, void *unused)
1477 struct drm_info_node *node = (struct drm_info_node *) m->private;
1478 struct drm_device *dev = node->minor->dev;
1479 struct drm_i915_private *dev_priv = dev->dev_private;
1480 bool sr_enabled = false;
1482 intel_runtime_pm_get(dev_priv);
1484 if (HAS_PCH_SPLIT(dev))
1485 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1486 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1487 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1488 else if (IS_I915GM(dev))
1489 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1490 else if (IS_PINEVIEW(dev))
1491 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1493 intel_runtime_pm_put(dev_priv);
1495 seq_printf(m, "self-refresh: %s\n",
1496 sr_enabled ? "enabled" : "disabled");
1501 static int i915_emon_status(struct seq_file *m, void *unused)
1503 struct drm_info_node *node = (struct drm_info_node *) m->private;
1504 struct drm_device *dev = node->minor->dev;
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 unsigned long temp, chipset, gfx;
1512 ret = mutex_lock_interruptible(&dev->struct_mutex);
1516 temp = i915_mch_val(dev_priv);
1517 chipset = i915_chipset_val(dev_priv);
1518 gfx = i915_gfx_val(dev_priv);
1519 mutex_unlock(&dev->struct_mutex);
1521 seq_printf(m, "GMCH temp: %ld\n", temp);
1522 seq_printf(m, "Chipset power: %ld\n", chipset);
1523 seq_printf(m, "GFX power: %ld\n", gfx);
1524 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1529 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1531 struct drm_info_node *node = (struct drm_info_node *) m->private;
1532 struct drm_device *dev = node->minor->dev;
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1535 int gpu_freq, ia_freq;
1537 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1538 seq_puts(m, "unsupported on this chipset\n");
1542 intel_runtime_pm_get(dev_priv);
1544 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1546 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1550 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1552 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1553 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1556 sandybridge_pcode_read(dev_priv,
1557 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1559 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1560 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1561 ((ia_freq >> 0) & 0xff) * 100,
1562 ((ia_freq >> 8) & 0xff) * 100);
1565 mutex_unlock(&dev_priv->rps.hw_lock);
1568 intel_runtime_pm_put(dev_priv);
1572 static int i915_gfxec(struct seq_file *m, void *unused)
1574 struct drm_info_node *node = (struct drm_info_node *) m->private;
1575 struct drm_device *dev = node->minor->dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1579 ret = mutex_lock_interruptible(&dev->struct_mutex);
1582 intel_runtime_pm_get(dev_priv);
1584 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1585 intel_runtime_pm_put(dev_priv);
1587 mutex_unlock(&dev->struct_mutex);
1592 static int i915_opregion(struct seq_file *m, void *unused)
1594 struct drm_info_node *node = (struct drm_info_node *) m->private;
1595 struct drm_device *dev = node->minor->dev;
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597 struct intel_opregion *opregion = &dev_priv->opregion;
1598 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1604 ret = mutex_lock_interruptible(&dev->struct_mutex);
1608 if (opregion->header) {
1609 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1610 seq_write(m, data, OPREGION_SIZE);
1613 mutex_unlock(&dev->struct_mutex);
1620 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1622 struct drm_info_node *node = (struct drm_info_node *) m->private;
1623 struct drm_device *dev = node->minor->dev;
1624 struct intel_fbdev *ifbdev = NULL;
1625 struct intel_framebuffer *fb;
1627 #ifdef CONFIG_DRM_I915_FBDEV
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1633 ifbdev = dev_priv->fbdev;
1634 fb = to_intel_framebuffer(ifbdev->helper.fb);
1636 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1640 fb->base.bits_per_pixel,
1641 atomic_read(&fb->base.refcount.refcount));
1642 describe_obj(m, fb->obj);
1644 mutex_unlock(&dev->mode_config.mutex);
1647 mutex_lock(&dev->mode_config.fb_lock);
1648 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1649 if (ifbdev && &fb->base == ifbdev->helper.fb)
1652 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1656 fb->base.bits_per_pixel,
1657 atomic_read(&fb->base.refcount.refcount));
1658 describe_obj(m, fb->obj);
1661 mutex_unlock(&dev->mode_config.fb_lock);
1666 static int i915_context_status(struct seq_file *m, void *unused)
1668 struct drm_info_node *node = (struct drm_info_node *) m->private;
1669 struct drm_device *dev = node->minor->dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 struct intel_ring_buffer *ring;
1672 struct i915_hw_context *ctx;
1675 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1679 if (dev_priv->ips.pwrctx) {
1680 seq_puts(m, "power context ");
1681 describe_obj(m, dev_priv->ips.pwrctx);
1685 if (dev_priv->ips.renderctx) {
1686 seq_puts(m, "render context ");
1687 describe_obj(m, dev_priv->ips.renderctx);
1691 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1692 seq_puts(m, "HW context ");
1693 describe_ctx(m, ctx);
1694 for_each_ring(ring, dev_priv, i)
1695 if (ring->default_context == ctx)
1696 seq_printf(m, "(default context %s) ", ring->name);
1698 describe_obj(m, ctx->obj);
1702 mutex_unlock(&dev->mode_config.mutex);
1707 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1709 struct drm_info_node *node = (struct drm_info_node *) m->private;
1710 struct drm_device *dev = node->minor->dev;
1711 struct drm_i915_private *dev_priv = dev->dev_private;
1712 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1714 spin_lock_irq(&dev_priv->uncore.lock);
1715 if (IS_VALLEYVIEW(dev)) {
1716 fw_rendercount = dev_priv->uncore.fw_rendercount;
1717 fw_mediacount = dev_priv->uncore.fw_mediacount;
1719 forcewake_count = dev_priv->uncore.forcewake_count;
1720 spin_unlock_irq(&dev_priv->uncore.lock);
1722 if (IS_VALLEYVIEW(dev)) {
1723 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1724 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1726 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1731 static const char *swizzle_string(unsigned swizzle)
1734 case I915_BIT_6_SWIZZLE_NONE:
1736 case I915_BIT_6_SWIZZLE_9:
1738 case I915_BIT_6_SWIZZLE_9_10:
1739 return "bit9/bit10";
1740 case I915_BIT_6_SWIZZLE_9_11:
1741 return "bit9/bit11";
1742 case I915_BIT_6_SWIZZLE_9_10_11:
1743 return "bit9/bit10/bit11";
1744 case I915_BIT_6_SWIZZLE_9_17:
1745 return "bit9/bit17";
1746 case I915_BIT_6_SWIZZLE_9_10_17:
1747 return "bit9/bit10/bit17";
1748 case I915_BIT_6_SWIZZLE_UNKNOWN:
1755 static int i915_swizzle_info(struct seq_file *m, void *data)
1757 struct drm_info_node *node = (struct drm_info_node *) m->private;
1758 struct drm_device *dev = node->minor->dev;
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1762 ret = mutex_lock_interruptible(&dev->struct_mutex);
1765 intel_runtime_pm_get(dev_priv);
1767 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1768 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1769 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1770 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1772 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1773 seq_printf(m, "DDC = 0x%08x\n",
1775 seq_printf(m, "C0DRB3 = 0x%04x\n",
1776 I915_READ16(C0DRB3));
1777 seq_printf(m, "C1DRB3 = 0x%04x\n",
1778 I915_READ16(C1DRB3));
1779 } else if (INTEL_INFO(dev)->gen >= 6) {
1780 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1781 I915_READ(MAD_DIMM_C0));
1782 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1783 I915_READ(MAD_DIMM_C1));
1784 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1785 I915_READ(MAD_DIMM_C2));
1786 seq_printf(m, "TILECTL = 0x%08x\n",
1787 I915_READ(TILECTL));
1789 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1790 I915_READ(GAMTARBMODE));
1792 seq_printf(m, "ARB_MODE = 0x%08x\n",
1793 I915_READ(ARB_MODE));
1794 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1795 I915_READ(DISP_ARB_CTL));
1797 intel_runtime_pm_put(dev_priv);
1798 mutex_unlock(&dev->struct_mutex);
1803 static int per_file_ctx(int id, void *ptr, void *data)
1805 struct i915_hw_context *ctx = ptr;
1806 struct seq_file *m = data;
1807 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1809 ppgtt->debug_dump(ppgtt, m);
1814 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1816 struct drm_i915_private *dev_priv = dev->dev_private;
1817 struct intel_ring_buffer *ring;
1818 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1824 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1825 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1826 for_each_ring(ring, dev_priv, unused) {
1827 seq_printf(m, "%s\n", ring->name);
1828 for (i = 0; i < 4; i++) {
1829 u32 offset = 0x270 + i * 8;
1830 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1832 pdp |= I915_READ(ring->mmio_base + offset);
1833 for (i = 0; i < 4; i++)
1834 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1839 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842 struct intel_ring_buffer *ring;
1843 struct drm_file *file;
1846 if (INTEL_INFO(dev)->gen == 6)
1847 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1849 for_each_ring(ring, dev_priv, i) {
1850 seq_printf(m, "%s\n", ring->name);
1851 if (INTEL_INFO(dev)->gen == 7)
1852 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1853 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1854 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1855 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1857 if (dev_priv->mm.aliasing_ppgtt) {
1858 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1860 seq_puts(m, "aliasing PPGTT:\n");
1861 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1863 ppgtt->debug_dump(ppgtt, m);
1867 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1868 struct drm_i915_file_private *file_priv = file->driver_priv;
1869 struct i915_hw_ppgtt *pvt_ppgtt;
1871 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1872 seq_printf(m, "proc: %s\n",
1873 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1874 seq_puts(m, " default context:\n");
1875 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1877 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1880 static int i915_ppgtt_info(struct seq_file *m, void *data)
1882 struct drm_info_node *node = (struct drm_info_node *) m->private;
1883 struct drm_device *dev = node->minor->dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1886 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1889 intel_runtime_pm_get(dev_priv);
1891 if (INTEL_INFO(dev)->gen >= 8)
1892 gen8_ppgtt_info(m, dev);
1893 else if (INTEL_INFO(dev)->gen >= 6)
1894 gen6_ppgtt_info(m, dev);
1896 intel_runtime_pm_put(dev_priv);
1897 mutex_unlock(&dev->struct_mutex);
1902 static int i915_dpio_info(struct seq_file *m, void *data)
1904 struct drm_info_node *node = (struct drm_info_node *) m->private;
1905 struct drm_device *dev = node->minor->dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1910 if (!IS_VALLEYVIEW(dev)) {
1911 seq_puts(m, "unsupported\n");
1915 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1919 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1921 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1922 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1923 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1924 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1926 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1927 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1928 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1929 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1931 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1932 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1933 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1934 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1936 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1937 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1938 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1939 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
1941 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1942 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
1944 mutex_unlock(&dev_priv->dpio_lock);
1949 static int i915_llc(struct seq_file *m, void *data)
1951 struct drm_info_node *node = (struct drm_info_node *) m->private;
1952 struct drm_device *dev = node->minor->dev;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1955 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1956 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1957 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1962 static int i915_edp_psr_status(struct seq_file *m, void *data)
1964 struct drm_info_node *node = m->private;
1965 struct drm_device *dev = node->minor->dev;
1966 struct drm_i915_private *dev_priv = dev->dev_private;
1968 bool enabled = false;
1970 intel_runtime_pm_get(dev_priv);
1972 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1973 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1975 enabled = HAS_PSR(dev) &&
1976 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1977 seq_printf(m, "Enabled: %s\n", yesno(enabled));
1980 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1981 EDP_PSR_PERF_CNT_MASK;
1982 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1984 intel_runtime_pm_put(dev_priv);
1988 static int i915_sink_crc(struct seq_file *m, void *data)
1990 struct drm_info_node *node = m->private;
1991 struct drm_device *dev = node->minor->dev;
1992 struct intel_encoder *encoder;
1993 struct intel_connector *connector;
1994 struct intel_dp *intel_dp = NULL;
1998 drm_modeset_lock_all(dev);
1999 list_for_each_entry(connector, &dev->mode_config.connector_list,
2002 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2005 if (!connector->base.encoder)
2008 encoder = to_intel_encoder(connector->base.encoder);
2009 if (encoder->type != INTEL_OUTPUT_EDP)
2012 intel_dp = enc_to_intel_dp(&encoder->base);
2014 ret = intel_dp_sink_crc(intel_dp, crc);
2018 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2019 crc[0], crc[1], crc[2],
2020 crc[3], crc[4], crc[5]);
2025 drm_modeset_unlock_all(dev);
2029 static int i915_energy_uJ(struct seq_file *m, void *data)
2031 struct drm_info_node *node = m->private;
2032 struct drm_device *dev = node->minor->dev;
2033 struct drm_i915_private *dev_priv = dev->dev_private;
2037 if (INTEL_INFO(dev)->gen < 6)
2040 intel_runtime_pm_get(dev_priv);
2042 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2043 power = (power & 0x1f00) >> 8;
2044 units = 1000000 / (1 << power); /* convert to uJ */
2045 power = I915_READ(MCH_SECP_NRG_STTS);
2048 intel_runtime_pm_put(dev_priv);
2050 seq_printf(m, "%llu", (long long unsigned)power);
2055 static int i915_pc8_status(struct seq_file *m, void *unused)
2057 struct drm_info_node *node = (struct drm_info_node *) m->private;
2058 struct drm_device *dev = node->minor->dev;
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2061 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2062 seq_puts(m, "not supported\n");
2066 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2067 seq_printf(m, "IRQs disabled: %s\n",
2068 yesno(dev_priv->pm.irqs_disabled));
2073 static const char *power_domain_str(enum intel_display_power_domain domain)
2076 case POWER_DOMAIN_PIPE_A:
2078 case POWER_DOMAIN_PIPE_B:
2080 case POWER_DOMAIN_PIPE_C:
2082 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2083 return "PIPE_A_PANEL_FITTER";
2084 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2085 return "PIPE_B_PANEL_FITTER";
2086 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2087 return "PIPE_C_PANEL_FITTER";
2088 case POWER_DOMAIN_TRANSCODER_A:
2089 return "TRANSCODER_A";
2090 case POWER_DOMAIN_TRANSCODER_B:
2091 return "TRANSCODER_B";
2092 case POWER_DOMAIN_TRANSCODER_C:
2093 return "TRANSCODER_C";
2094 case POWER_DOMAIN_TRANSCODER_EDP:
2095 return "TRANSCODER_EDP";
2096 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2097 return "PORT_DDI_A_2_LANES";
2098 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2099 return "PORT_DDI_A_4_LANES";
2100 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2101 return "PORT_DDI_B_2_LANES";
2102 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2103 return "PORT_DDI_B_4_LANES";
2104 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2105 return "PORT_DDI_C_2_LANES";
2106 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2107 return "PORT_DDI_C_4_LANES";
2108 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2109 return "PORT_DDI_D_2_LANES";
2110 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2111 return "PORT_DDI_D_4_LANES";
2112 case POWER_DOMAIN_PORT_DSI:
2114 case POWER_DOMAIN_PORT_CRT:
2116 case POWER_DOMAIN_PORT_OTHER:
2117 return "PORT_OTHER";
2118 case POWER_DOMAIN_VGA:
2120 case POWER_DOMAIN_AUDIO:
2122 case POWER_DOMAIN_INIT:
2130 static int i915_power_domain_info(struct seq_file *m, void *unused)
2132 struct drm_info_node *node = (struct drm_info_node *) m->private;
2133 struct drm_device *dev = node->minor->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2138 mutex_lock(&power_domains->lock);
2140 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2141 for (i = 0; i < power_domains->power_well_count; i++) {
2142 struct i915_power_well *power_well;
2143 enum intel_display_power_domain power_domain;
2145 power_well = &power_domains->power_wells[i];
2146 seq_printf(m, "%-25s %d\n", power_well->name,
2149 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2151 if (!(BIT(power_domain) & power_well->domains))
2154 seq_printf(m, " %-23s %d\n",
2155 power_domain_str(power_domain),
2156 power_domains->domain_use_count[power_domain]);
2160 mutex_unlock(&power_domains->lock);
2165 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2166 struct drm_display_mode *mode)
2170 for (i = 0; i < tabs; i++)
2173 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2174 mode->base.id, mode->name,
2175 mode->vrefresh, mode->clock,
2176 mode->hdisplay, mode->hsync_start,
2177 mode->hsync_end, mode->htotal,
2178 mode->vdisplay, mode->vsync_start,
2179 mode->vsync_end, mode->vtotal,
2180 mode->type, mode->flags);
2183 static void intel_encoder_info(struct seq_file *m,
2184 struct intel_crtc *intel_crtc,
2185 struct intel_encoder *intel_encoder)
2187 struct drm_info_node *node = (struct drm_info_node *) m->private;
2188 struct drm_device *dev = node->minor->dev;
2189 struct drm_crtc *crtc = &intel_crtc->base;
2190 struct intel_connector *intel_connector;
2191 struct drm_encoder *encoder;
2193 encoder = &intel_encoder->base;
2194 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2195 encoder->base.id, drm_get_encoder_name(encoder));
2196 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2197 struct drm_connector *connector = &intel_connector->base;
2198 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2200 drm_get_connector_name(connector),
2201 drm_get_connector_status_name(connector->status));
2202 if (connector->status == connector_status_connected) {
2203 struct drm_display_mode *mode = &crtc->mode;
2204 seq_printf(m, ", mode:\n");
2205 intel_seq_print_mode(m, 2, mode);
2212 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2214 struct drm_info_node *node = (struct drm_info_node *) m->private;
2215 struct drm_device *dev = node->minor->dev;
2216 struct drm_crtc *crtc = &intel_crtc->base;
2217 struct intel_encoder *intel_encoder;
2219 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2220 crtc->fb->base.id, crtc->x, crtc->y,
2221 crtc->fb->width, crtc->fb->height);
2222 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2223 intel_encoder_info(m, intel_crtc, intel_encoder);
2226 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2228 struct drm_display_mode *mode = panel->fixed_mode;
2230 seq_printf(m, "\tfixed mode:\n");
2231 intel_seq_print_mode(m, 2, mode);
2234 static void intel_dp_info(struct seq_file *m,
2235 struct intel_connector *intel_connector)
2237 struct intel_encoder *intel_encoder = intel_connector->encoder;
2238 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2240 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2241 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2243 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2244 intel_panel_info(m, &intel_connector->panel);
2247 static void intel_hdmi_info(struct seq_file *m,
2248 struct intel_connector *intel_connector)
2250 struct intel_encoder *intel_encoder = intel_connector->encoder;
2251 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2253 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2257 static void intel_lvds_info(struct seq_file *m,
2258 struct intel_connector *intel_connector)
2260 intel_panel_info(m, &intel_connector->panel);
2263 static void intel_connector_info(struct seq_file *m,
2264 struct drm_connector *connector)
2266 struct intel_connector *intel_connector = to_intel_connector(connector);
2267 struct intel_encoder *intel_encoder = intel_connector->encoder;
2268 struct drm_display_mode *mode;
2270 seq_printf(m, "connector %d: type %s, status: %s\n",
2271 connector->base.id, drm_get_connector_name(connector),
2272 drm_get_connector_status_name(connector->status));
2273 if (connector->status == connector_status_connected) {
2274 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2275 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2276 connector->display_info.width_mm,
2277 connector->display_info.height_mm);
2278 seq_printf(m, "\tsubpixel order: %s\n",
2279 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2280 seq_printf(m, "\tCEA rev: %d\n",
2281 connector->display_info.cea_rev);
2283 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2284 intel_encoder->type == INTEL_OUTPUT_EDP)
2285 intel_dp_info(m, intel_connector);
2286 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2287 intel_hdmi_info(m, intel_connector);
2288 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2289 intel_lvds_info(m, intel_connector);
2291 seq_printf(m, "\tmodes:\n");
2292 list_for_each_entry(mode, &connector->modes, head)
2293 intel_seq_print_mode(m, 2, mode);
2296 static bool cursor_active(struct drm_device *dev, int pipe)
2298 struct drm_i915_private *dev_priv = dev->dev_private;
2301 if (IS_845G(dev) || IS_I865G(dev))
2302 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2303 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
2304 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2306 state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
2311 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2316 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
2317 pos = I915_READ(CURPOS_IVB(pipe));
2319 pos = I915_READ(CURPOS(pipe));
2321 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2322 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2325 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2326 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2329 return cursor_active(dev, pipe);
2332 static int i915_display_info(struct seq_file *m, void *unused)
2334 struct drm_info_node *node = (struct drm_info_node *) m->private;
2335 struct drm_device *dev = node->minor->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_crtc *crtc;
2338 struct drm_connector *connector;
2340 intel_runtime_pm_get(dev_priv);
2341 drm_modeset_lock_all(dev);
2342 seq_printf(m, "CRTC info\n");
2343 seq_printf(m, "---------\n");
2344 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2348 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2349 crtc->base.base.id, pipe_name(crtc->pipe),
2350 yesno(crtc->active));
2352 intel_crtc_info(m, crtc);
2354 active = cursor_position(dev, crtc->pipe, &x, &y);
2355 seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2356 yesno(crtc->cursor_visible),
2357 x, y, crtc->cursor_addr,
2362 seq_printf(m, "\n");
2363 seq_printf(m, "Connector info\n");
2364 seq_printf(m, "--------------\n");
2365 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2366 intel_connector_info(m, connector);
2368 drm_modeset_unlock_all(dev);
2369 intel_runtime_pm_put(dev_priv);
2374 struct pipe_crc_info {
2376 struct drm_device *dev;
2380 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2382 struct pipe_crc_info *info = inode->i_private;
2383 struct drm_i915_private *dev_priv = info->dev->dev_private;
2384 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2386 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2389 spin_lock_irq(&pipe_crc->lock);
2391 if (pipe_crc->opened) {
2392 spin_unlock_irq(&pipe_crc->lock);
2393 return -EBUSY; /* already open */
2396 pipe_crc->opened = true;
2397 filep->private_data = inode->i_private;
2399 spin_unlock_irq(&pipe_crc->lock);
2404 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2406 struct pipe_crc_info *info = inode->i_private;
2407 struct drm_i915_private *dev_priv = info->dev->dev_private;
2408 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2410 spin_lock_irq(&pipe_crc->lock);
2411 pipe_crc->opened = false;
2412 spin_unlock_irq(&pipe_crc->lock);
2417 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2418 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2419 /* account for \'0' */
2420 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2422 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2424 assert_spin_locked(&pipe_crc->lock);
2425 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2426 INTEL_PIPE_CRC_ENTRIES_NR);
2430 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2433 struct pipe_crc_info *info = filep->private_data;
2434 struct drm_device *dev = info->dev;
2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2437 char buf[PIPE_CRC_BUFFER_LEN];
2438 int head, tail, n_entries, n;
2442 * Don't allow user space to provide buffers not big enough to hold
2445 if (count < PIPE_CRC_LINE_LEN)
2448 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2451 /* nothing to read */
2452 spin_lock_irq(&pipe_crc->lock);
2453 while (pipe_crc_data_count(pipe_crc) == 0) {
2456 if (filep->f_flags & O_NONBLOCK) {
2457 spin_unlock_irq(&pipe_crc->lock);
2461 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2462 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2464 spin_unlock_irq(&pipe_crc->lock);
2469 /* We now have one or more entries to read */
2470 head = pipe_crc->head;
2471 tail = pipe_crc->tail;
2472 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2473 count / PIPE_CRC_LINE_LEN);
2474 spin_unlock_irq(&pipe_crc->lock);
2479 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2482 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2483 "%8u %8x %8x %8x %8x %8x\n",
2484 entry->frame, entry->crc[0],
2485 entry->crc[1], entry->crc[2],
2486 entry->crc[3], entry->crc[4]);
2488 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2489 buf, PIPE_CRC_LINE_LEN);
2490 if (ret == PIPE_CRC_LINE_LEN)
2493 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2494 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2496 } while (--n_entries);
2498 spin_lock_irq(&pipe_crc->lock);
2499 pipe_crc->tail = tail;
2500 spin_unlock_irq(&pipe_crc->lock);
2505 static const struct file_operations i915_pipe_crc_fops = {
2506 .owner = THIS_MODULE,
2507 .open = i915_pipe_crc_open,
2508 .read = i915_pipe_crc_read,
2509 .release = i915_pipe_crc_release,
2512 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2514 .name = "i915_pipe_A_crc",
2518 .name = "i915_pipe_B_crc",
2522 .name = "i915_pipe_C_crc",
2527 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2530 struct drm_device *dev = minor->dev;
2532 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2535 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2536 &i915_pipe_crc_fops);
2540 return drm_add_fake_info_node(minor, ent, info);
2543 static const char * const pipe_crc_sources[] = {
2556 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2558 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2559 return pipe_crc_sources[source];
2562 static int display_crc_ctl_show(struct seq_file *m, void *data)
2564 struct drm_device *dev = m->private;
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2568 for (i = 0; i < I915_MAX_PIPES; i++)
2569 seq_printf(m, "%c %s\n", pipe_name(i),
2570 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2575 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2577 struct drm_device *dev = inode->i_private;
2579 return single_open(file, display_crc_ctl_show, dev);
2582 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2585 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2586 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2589 case INTEL_PIPE_CRC_SOURCE_PIPE:
2590 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2592 case INTEL_PIPE_CRC_SOURCE_NONE:
2602 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2603 enum intel_pipe_crc_source *source)
2605 struct intel_encoder *encoder;
2606 struct intel_crtc *crtc;
2607 struct intel_digital_port *dig_port;
2610 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2612 mutex_lock(&dev->mode_config.mutex);
2613 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2615 if (!encoder->base.crtc)
2618 crtc = to_intel_crtc(encoder->base.crtc);
2620 if (crtc->pipe != pipe)
2623 switch (encoder->type) {
2624 case INTEL_OUTPUT_TVOUT:
2625 *source = INTEL_PIPE_CRC_SOURCE_TV;
2627 case INTEL_OUTPUT_DISPLAYPORT:
2628 case INTEL_OUTPUT_EDP:
2629 dig_port = enc_to_dig_port(&encoder->base);
2630 switch (dig_port->port) {
2632 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2635 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2638 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2641 WARN(1, "nonexisting DP port %c\n",
2642 port_name(dig_port->port));
2648 mutex_unlock(&dev->mode_config.mutex);
2653 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2655 enum intel_pipe_crc_source *source,
2658 struct drm_i915_private *dev_priv = dev->dev_private;
2659 bool need_stable_symbols = false;
2661 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2662 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2668 case INTEL_PIPE_CRC_SOURCE_PIPE:
2669 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2671 case INTEL_PIPE_CRC_SOURCE_DP_B:
2672 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2673 need_stable_symbols = true;
2675 case INTEL_PIPE_CRC_SOURCE_DP_C:
2676 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2677 need_stable_symbols = true;
2679 case INTEL_PIPE_CRC_SOURCE_NONE:
2687 * When the pipe CRC tap point is after the transcoders we need
2688 * to tweak symbol-level features to produce a deterministic series of
2689 * symbols for a given frame. We need to reset those features only once
2690 * a frame (instead of every nth symbol):
2691 * - DC-balance: used to ensure a better clock recovery from the data
2693 * - DisplayPort scrambling: used for EMI reduction
2695 if (need_stable_symbols) {
2696 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2698 tmp |= DC_BALANCE_RESET_VLV;
2700 tmp |= PIPE_A_SCRAMBLE_RESET;
2702 tmp |= PIPE_B_SCRAMBLE_RESET;
2704 I915_WRITE(PORT_DFT2_G4X, tmp);
2710 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2712 enum intel_pipe_crc_source *source,
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 bool need_stable_symbols = false;
2718 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2719 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2725 case INTEL_PIPE_CRC_SOURCE_PIPE:
2726 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2728 case INTEL_PIPE_CRC_SOURCE_TV:
2729 if (!SUPPORTS_TV(dev))
2731 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2733 case INTEL_PIPE_CRC_SOURCE_DP_B:
2736 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2737 need_stable_symbols = true;
2739 case INTEL_PIPE_CRC_SOURCE_DP_C:
2742 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2743 need_stable_symbols = true;
2745 case INTEL_PIPE_CRC_SOURCE_DP_D:
2748 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2749 need_stable_symbols = true;
2751 case INTEL_PIPE_CRC_SOURCE_NONE:
2759 * When the pipe CRC tap point is after the transcoders we need
2760 * to tweak symbol-level features to produce a deterministic series of
2761 * symbols for a given frame. We need to reset those features only once
2762 * a frame (instead of every nth symbol):
2763 * - DC-balance: used to ensure a better clock recovery from the data
2765 * - DisplayPort scrambling: used for EMI reduction
2767 if (need_stable_symbols) {
2768 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2770 WARN_ON(!IS_G4X(dev));
2772 I915_WRITE(PORT_DFT_I9XX,
2773 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2776 tmp |= PIPE_A_SCRAMBLE_RESET;
2778 tmp |= PIPE_B_SCRAMBLE_RESET;
2780 I915_WRITE(PORT_DFT2_G4X, tmp);
2786 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2793 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2795 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2796 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2797 tmp &= ~DC_BALANCE_RESET_VLV;
2798 I915_WRITE(PORT_DFT2_G4X, tmp);
2802 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2809 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2811 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2812 I915_WRITE(PORT_DFT2_G4X, tmp);
2814 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2815 I915_WRITE(PORT_DFT_I9XX,
2816 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2820 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2823 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2824 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2827 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2828 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2830 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2831 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2833 case INTEL_PIPE_CRC_SOURCE_PIPE:
2834 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2836 case INTEL_PIPE_CRC_SOURCE_NONE:
2846 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2849 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2850 *source = INTEL_PIPE_CRC_SOURCE_PF;
2853 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2854 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2856 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2857 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2859 case INTEL_PIPE_CRC_SOURCE_PF:
2860 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2862 case INTEL_PIPE_CRC_SOURCE_NONE:
2872 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2873 enum intel_pipe_crc_source source)
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2877 u32 val = 0; /* shut up gcc */
2880 if (pipe_crc->source == source)
2883 /* forbid changing the source without going back to 'none' */
2884 if (pipe_crc->source && source)
2888 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2889 else if (INTEL_INFO(dev)->gen < 5)
2890 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2891 else if (IS_VALLEYVIEW(dev))
2892 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2893 else if (IS_GEN5(dev) || IS_GEN6(dev))
2894 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2896 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2901 /* none -> real source transition */
2903 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2904 pipe_name(pipe), pipe_crc_source_name(source));
2906 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2907 INTEL_PIPE_CRC_ENTRIES_NR,
2909 if (!pipe_crc->entries)
2912 spin_lock_irq(&pipe_crc->lock);
2915 spin_unlock_irq(&pipe_crc->lock);
2918 pipe_crc->source = source;
2920 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2921 POSTING_READ(PIPE_CRC_CTL(pipe));
2923 /* real source -> none transition */
2924 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2925 struct intel_pipe_crc_entry *entries;
2927 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2930 intel_wait_for_vblank(dev, pipe);
2932 spin_lock_irq(&pipe_crc->lock);
2933 entries = pipe_crc->entries;
2934 pipe_crc->entries = NULL;
2935 spin_unlock_irq(&pipe_crc->lock);
2940 g4x_undo_pipe_scramble_reset(dev, pipe);
2941 else if (IS_VALLEYVIEW(dev))
2942 vlv_undo_pipe_scramble_reset(dev, pipe);
2949 * Parse pipe CRC command strings:
2950 * command: wsp* object wsp+ name wsp+ source wsp*
2953 * source: (none | plane1 | plane2 | pf)
2954 * wsp: (#0x20 | #0x9 | #0xA)+
2957 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2958 * "pipe A none" -> Stop CRC
2960 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2967 /* skip leading white space */
2968 buf = skip_spaces(buf);
2970 break; /* end of buffer */
2972 /* find end of word */
2973 for (end = buf; *end && !isspace(*end); end++)
2976 if (n_words == max_words) {
2977 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2979 return -EINVAL; /* ran out of words[] before bytes */
2984 words[n_words++] = buf;
2991 enum intel_pipe_crc_object {
2992 PIPE_CRC_OBJECT_PIPE,
2995 static const char * const pipe_crc_objects[] = {
3000 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3004 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3005 if (!strcmp(buf, pipe_crc_objects[i])) {
3013 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3015 const char name = buf[0];
3017 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3026 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3030 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3031 if (!strcmp(buf, pipe_crc_sources[i])) {
3039 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3043 char *words[N_WORDS];
3045 enum intel_pipe_crc_object object;
3046 enum intel_pipe_crc_source source;
3048 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3049 if (n_words != N_WORDS) {
3050 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3055 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3056 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3060 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3061 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3065 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3066 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3070 return pipe_crc_set_source(dev, pipe, source);
3073 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3074 size_t len, loff_t *offp)
3076 struct seq_file *m = file->private_data;
3077 struct drm_device *dev = m->private;
3084 if (len > PAGE_SIZE - 1) {
3085 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3090 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3094 if (copy_from_user(tmpbuf, ubuf, len)) {
3100 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3111 static const struct file_operations i915_display_crc_ctl_fops = {
3112 .owner = THIS_MODULE,
3113 .open = display_crc_ctl_open,
3115 .llseek = seq_lseek,
3116 .release = single_release,
3117 .write = display_crc_ctl_write
3120 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3122 struct drm_device *dev = m->private;
3123 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3126 drm_modeset_lock_all(dev);
3128 for (level = 0; level < num_levels; level++) {
3129 unsigned int latency = wm[level];
3131 /* WM1+ latency values in 0.5us units */
3135 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3137 latency / 10, latency % 10);
3140 drm_modeset_unlock_all(dev);
3143 static int pri_wm_latency_show(struct seq_file *m, void *data)
3145 struct drm_device *dev = m->private;
3147 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3152 static int spr_wm_latency_show(struct seq_file *m, void *data)
3154 struct drm_device *dev = m->private;
3156 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3161 static int cur_wm_latency_show(struct seq_file *m, void *data)
3163 struct drm_device *dev = m->private;
3165 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3170 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3172 struct drm_device *dev = inode->i_private;
3174 if (!HAS_PCH_SPLIT(dev))
3177 return single_open(file, pri_wm_latency_show, dev);
3180 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3182 struct drm_device *dev = inode->i_private;
3184 if (!HAS_PCH_SPLIT(dev))
3187 return single_open(file, spr_wm_latency_show, dev);
3190 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3192 struct drm_device *dev = inode->i_private;
3194 if (!HAS_PCH_SPLIT(dev))
3197 return single_open(file, cur_wm_latency_show, dev);
3200 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3201 size_t len, loff_t *offp, uint16_t wm[5])
3203 struct seq_file *m = file->private_data;
3204 struct drm_device *dev = m->private;
3205 uint16_t new[5] = { 0 };
3206 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3211 if (len >= sizeof(tmp))
3214 if (copy_from_user(tmp, ubuf, len))
3219 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3220 if (ret != num_levels)
3223 drm_modeset_lock_all(dev);
3225 for (level = 0; level < num_levels; level++)
3226 wm[level] = new[level];
3228 drm_modeset_unlock_all(dev);
3234 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3235 size_t len, loff_t *offp)
3237 struct seq_file *m = file->private_data;
3238 struct drm_device *dev = m->private;
3240 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3243 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3244 size_t len, loff_t *offp)
3246 struct seq_file *m = file->private_data;
3247 struct drm_device *dev = m->private;
3249 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3252 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3253 size_t len, loff_t *offp)
3255 struct seq_file *m = file->private_data;
3256 struct drm_device *dev = m->private;
3258 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3261 static const struct file_operations i915_pri_wm_latency_fops = {
3262 .owner = THIS_MODULE,
3263 .open = pri_wm_latency_open,
3265 .llseek = seq_lseek,
3266 .release = single_release,
3267 .write = pri_wm_latency_write
3270 static const struct file_operations i915_spr_wm_latency_fops = {
3271 .owner = THIS_MODULE,
3272 .open = spr_wm_latency_open,
3274 .llseek = seq_lseek,
3275 .release = single_release,
3276 .write = spr_wm_latency_write
3279 static const struct file_operations i915_cur_wm_latency_fops = {
3280 .owner = THIS_MODULE,
3281 .open = cur_wm_latency_open,
3283 .llseek = seq_lseek,
3284 .release = single_release,
3285 .write = cur_wm_latency_write
3289 i915_wedged_get(void *data, u64 *val)
3291 struct drm_device *dev = data;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3294 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3300 i915_wedged_set(void *data, u64 val)
3302 struct drm_device *dev = data;
3304 i915_handle_error(dev, val,
3305 "Manually setting wedged to %llu", val);
3309 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3310 i915_wedged_get, i915_wedged_set,
3314 i915_ring_stop_get(void *data, u64 *val)
3316 struct drm_device *dev = data;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3319 *val = dev_priv->gpu_error.stop_rings;
3325 i915_ring_stop_set(void *data, u64 val)
3327 struct drm_device *dev = data;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3331 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3333 ret = mutex_lock_interruptible(&dev->struct_mutex);
3337 dev_priv->gpu_error.stop_rings = val;
3338 mutex_unlock(&dev->struct_mutex);
3343 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3344 i915_ring_stop_get, i915_ring_stop_set,
3348 i915_ring_missed_irq_get(void *data, u64 *val)
3350 struct drm_device *dev = data;
3351 struct drm_i915_private *dev_priv = dev->dev_private;
3353 *val = dev_priv->gpu_error.missed_irq_rings;
3358 i915_ring_missed_irq_set(void *data, u64 val)
3360 struct drm_device *dev = data;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3364 /* Lock against concurrent debugfs callers */
3365 ret = mutex_lock_interruptible(&dev->struct_mutex);
3368 dev_priv->gpu_error.missed_irq_rings = val;
3369 mutex_unlock(&dev->struct_mutex);
3374 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3375 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3379 i915_ring_test_irq_get(void *data, u64 *val)
3381 struct drm_device *dev = data;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3384 *val = dev_priv->gpu_error.test_irq_rings;
3390 i915_ring_test_irq_set(void *data, u64 val)
3392 struct drm_device *dev = data;
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3396 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3398 /* Lock against concurrent debugfs callers */
3399 ret = mutex_lock_interruptible(&dev->struct_mutex);
3403 dev_priv->gpu_error.test_irq_rings = val;
3404 mutex_unlock(&dev->struct_mutex);
3409 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3410 i915_ring_test_irq_get, i915_ring_test_irq_set,
3413 #define DROP_UNBOUND 0x1
3414 #define DROP_BOUND 0x2
3415 #define DROP_RETIRE 0x4
3416 #define DROP_ACTIVE 0x8
3417 #define DROP_ALL (DROP_UNBOUND | \
3422 i915_drop_caches_get(void *data, u64 *val)
3430 i915_drop_caches_set(void *data, u64 val)
3432 struct drm_device *dev = data;
3433 struct drm_i915_private *dev_priv = dev->dev_private;
3434 struct drm_i915_gem_object *obj, *next;
3435 struct i915_address_space *vm;
3436 struct i915_vma *vma, *x;
3439 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3441 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3442 * on ioctls on -EAGAIN. */
3443 ret = mutex_lock_interruptible(&dev->struct_mutex);
3447 if (val & DROP_ACTIVE) {
3448 ret = i915_gpu_idle(dev);
3453 if (val & (DROP_RETIRE | DROP_ACTIVE))
3454 i915_gem_retire_requests(dev);
3456 if (val & DROP_BOUND) {
3457 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3458 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3463 ret = i915_vma_unbind(vma);
3470 if (val & DROP_UNBOUND) {
3471 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3473 if (obj->pages_pin_count == 0) {
3474 ret = i915_gem_object_put_pages(obj);
3481 mutex_unlock(&dev->struct_mutex);
3486 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3487 i915_drop_caches_get, i915_drop_caches_set,
3491 i915_max_freq_get(void *data, u64 *val)
3493 struct drm_device *dev = data;
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3497 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3500 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3502 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3506 if (IS_VALLEYVIEW(dev))
3507 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3509 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3510 mutex_unlock(&dev_priv->rps.hw_lock);
3516 i915_max_freq_set(void *data, u64 val)
3518 struct drm_device *dev = data;
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 u32 rp_state_cap, hw_max, hw_min;
3523 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3526 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3528 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3530 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3535 * Turbo will still be enabled, but won't go above the set value.
3537 if (IS_VALLEYVIEW(dev)) {
3538 val = vlv_freq_opcode(dev_priv, val);
3540 hw_max = valleyview_rps_max_freq(dev_priv);
3541 hw_min = valleyview_rps_min_freq(dev_priv);
3543 do_div(val, GT_FREQUENCY_MULTIPLIER);
3545 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3546 hw_max = dev_priv->rps.max_freq;
3547 hw_min = (rp_state_cap >> 16) & 0xff;
3550 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3551 mutex_unlock(&dev_priv->rps.hw_lock);
3555 dev_priv->rps.max_freq_softlimit = val;
3557 if (IS_VALLEYVIEW(dev))
3558 valleyview_set_rps(dev, val);
3560 gen6_set_rps(dev, val);
3562 mutex_unlock(&dev_priv->rps.hw_lock);
3567 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3568 i915_max_freq_get, i915_max_freq_set,
3572 i915_min_freq_get(void *data, u64 *val)
3574 struct drm_device *dev = data;
3575 struct drm_i915_private *dev_priv = dev->dev_private;
3578 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3581 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3583 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3587 if (IS_VALLEYVIEW(dev))
3588 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3590 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3591 mutex_unlock(&dev_priv->rps.hw_lock);
3597 i915_min_freq_set(void *data, u64 val)
3599 struct drm_device *dev = data;
3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601 u32 rp_state_cap, hw_max, hw_min;
3604 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3607 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3609 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3611 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3616 * Turbo will still be enabled, but won't go below the set value.
3618 if (IS_VALLEYVIEW(dev)) {
3619 val = vlv_freq_opcode(dev_priv, val);
3621 hw_max = valleyview_rps_max_freq(dev_priv);
3622 hw_min = valleyview_rps_min_freq(dev_priv);
3624 do_div(val, GT_FREQUENCY_MULTIPLIER);
3626 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3627 hw_max = dev_priv->rps.max_freq;
3628 hw_min = (rp_state_cap >> 16) & 0xff;
3631 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3632 mutex_unlock(&dev_priv->rps.hw_lock);
3636 dev_priv->rps.min_freq_softlimit = val;
3638 if (IS_VALLEYVIEW(dev))
3639 valleyview_set_rps(dev, val);
3641 gen6_set_rps(dev, val);
3643 mutex_unlock(&dev_priv->rps.hw_lock);
3648 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3649 i915_min_freq_get, i915_min_freq_set,
3653 i915_cache_sharing_get(void *data, u64 *val)
3655 struct drm_device *dev = data;
3656 struct drm_i915_private *dev_priv = dev->dev_private;
3660 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3663 ret = mutex_lock_interruptible(&dev->struct_mutex);
3666 intel_runtime_pm_get(dev_priv);
3668 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3670 intel_runtime_pm_put(dev_priv);
3671 mutex_unlock(&dev_priv->dev->struct_mutex);
3673 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3679 i915_cache_sharing_set(void *data, u64 val)
3681 struct drm_device *dev = data;
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3685 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3691 intel_runtime_pm_get(dev_priv);
3692 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3694 /* Update the cache sharing policy here as well */
3695 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3696 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3697 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3698 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3700 intel_runtime_pm_put(dev_priv);
3704 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3705 i915_cache_sharing_get, i915_cache_sharing_set,
3708 static int i915_forcewake_open(struct inode *inode, struct file *file)
3710 struct drm_device *dev = inode->i_private;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3713 if (INTEL_INFO(dev)->gen < 6)
3716 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3721 static int i915_forcewake_release(struct inode *inode, struct file *file)
3723 struct drm_device *dev = inode->i_private;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3726 if (INTEL_INFO(dev)->gen < 6)
3729 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3734 static const struct file_operations i915_forcewake_fops = {
3735 .owner = THIS_MODULE,
3736 .open = i915_forcewake_open,
3737 .release = i915_forcewake_release,
3740 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3742 struct drm_device *dev = minor->dev;
3745 ent = debugfs_create_file("i915_forcewake_user",
3748 &i915_forcewake_fops);
3752 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3755 static int i915_debugfs_create(struct dentry *root,
3756 struct drm_minor *minor,
3758 const struct file_operations *fops)
3760 struct drm_device *dev = minor->dev;
3763 ent = debugfs_create_file(name,
3770 return drm_add_fake_info_node(minor, ent, fops);
3773 static const struct drm_info_list i915_debugfs_list[] = {
3774 {"i915_capabilities", i915_capabilities, 0},
3775 {"i915_gem_objects", i915_gem_object_info, 0},
3776 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3777 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3778 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3779 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3780 {"i915_gem_stolen", i915_gem_stolen_list_info },
3781 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3782 {"i915_gem_request", i915_gem_request_info, 0},
3783 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3784 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3785 {"i915_gem_interrupt", i915_interrupt_info, 0},
3786 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3787 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3788 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3789 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3790 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3791 {"i915_frequency_info", i915_frequency_info, 0},
3792 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3793 {"i915_inttoext_table", i915_inttoext_table, 0},
3794 {"i915_drpc_info", i915_drpc_info, 0},
3795 {"i915_emon_status", i915_emon_status, 0},
3796 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3797 {"i915_gfxec", i915_gfxec, 0},
3798 {"i915_fbc_status", i915_fbc_status, 0},
3799 {"i915_ips_status", i915_ips_status, 0},
3800 {"i915_sr_status", i915_sr_status, 0},
3801 {"i915_opregion", i915_opregion, 0},
3802 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3803 {"i915_context_status", i915_context_status, 0},
3804 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3805 {"i915_swizzle_info", i915_swizzle_info, 0},
3806 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3807 {"i915_dpio", i915_dpio_info, 0},
3808 {"i915_llc", i915_llc, 0},
3809 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3810 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3811 {"i915_energy_uJ", i915_energy_uJ, 0},
3812 {"i915_pc8_status", i915_pc8_status, 0},
3813 {"i915_power_domain_info", i915_power_domain_info, 0},
3814 {"i915_display_info", i915_display_info, 0},
3816 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3818 static const struct i915_debugfs_files {
3820 const struct file_operations *fops;
3821 } i915_debugfs_files[] = {
3822 {"i915_wedged", &i915_wedged_fops},
3823 {"i915_max_freq", &i915_max_freq_fops},
3824 {"i915_min_freq", &i915_min_freq_fops},
3825 {"i915_cache_sharing", &i915_cache_sharing_fops},
3826 {"i915_ring_stop", &i915_ring_stop_fops},
3827 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3828 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3829 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3830 {"i915_error_state", &i915_error_state_fops},
3831 {"i915_next_seqno", &i915_next_seqno_fops},
3832 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3833 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3834 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3835 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3838 void intel_display_crc_init(struct drm_device *dev)
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3843 for_each_pipe(pipe) {
3844 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3846 pipe_crc->opened = false;
3847 spin_lock_init(&pipe_crc->lock);
3848 init_waitqueue_head(&pipe_crc->wq);
3852 int i915_debugfs_init(struct drm_minor *minor)
3856 ret = i915_forcewake_create(minor->debugfs_root, minor);
3860 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3861 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3866 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3867 ret = i915_debugfs_create(minor->debugfs_root, minor,
3868 i915_debugfs_files[i].name,
3869 i915_debugfs_files[i].fops);
3874 return drm_debugfs_create_files(i915_debugfs_list,
3875 I915_DEBUGFS_ENTRIES,
3876 minor->debugfs_root, minor);
3879 void i915_debugfs_cleanup(struct drm_minor *minor)
3883 drm_debugfs_remove_files(i915_debugfs_list,
3884 I915_DEBUGFS_ENTRIES, minor);
3886 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3889 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3890 struct drm_info_list *info_list =
3891 (struct drm_info_list *)&i915_pipe_crc_data[i];
3893 drm_debugfs_remove_files(info_list, 1, minor);
3896 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3897 struct drm_info_list *info_list =
3898 (struct drm_info_list *) i915_debugfs_files[i].fops;
3900 drm_debugfs_remove_files(info_list, 1, minor);