drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  83 #undef PRINT_FLAG
  84
  85         return 0;
  86 }
  87
  88 static char get_active_flag(struct drm_i915_gem_object *obj)
  89 {
  90         return i915_gem_object_is_active(obj) ? '*' : ' ';
  91 }
  92
  93 static char get_pin_flag(struct drm_i915_gem_object *obj)
  94 {
  95         return obj->pin_display ? 'p' : ' ';
  96 }
  97
  98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  99 {
 100         switch (i915_gem_object_get_tiling(obj)) {
 101         default:
 102         case I915_TILING_NONE: return ' ';
 103         case I915_TILING_X: return 'X';
 104         case I915_TILING_Y: return 'Y';
 105         }
 106 }
 107
 108 static char get_global_flag(struct drm_i915_gem_object *obj)
 109 {
 110         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 111 }
 112
 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 114 {
 115         return obj->mm.mapping ? 'M' : ' ';
 116 }
 117
 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 119 {
 120         u64 size = 0;
 121         struct i915_vma *vma;
 122
 123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 125                         size += vma->node.size;
 126         }
 127
 128         return size;
 129 }
 130
 131 static void
 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 135         struct intel_engine_cs *engine;
 136         struct i915_vma *vma;
 137         unsigned int frontbuffer_bits;
 138         int pin_count = 0;
 139
 140         lockdep_assert_held(&obj->base.dev->struct_mutex);
 141
 142         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 143                    &obj->base,
 144                    get_active_flag(obj),
 145                    get_pin_flag(obj),
 146                    get_tiling_flag(obj),
 147                    get_global_flag(obj),
 148                    get_pin_mapped_flag(obj),
 149                    obj->base.size / 1024,
 150                    obj->base.read_domains,
 151                    obj->base.write_domain,
 152                    i915_cache_level_str(dev_priv, obj->cache_level),
 153                    obj->mm.dirty ? " dirty" : "",
 154                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 155         if (obj->base.name)
 156                 seq_printf(m, " (name: %d)", obj->base.name);
 157         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 158                 if (i915_vma_is_pinned(vma))
 159                         pin_count++;
 160         }
 161         seq_printf(m, " (pinned x %d)", pin_count);
 162         if (obj->pin_display)
 163                 seq_printf(m, " (display)");
 164         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 165                 if (!drm_mm_node_allocated(&vma->node))
 166                         continue;
 167
 168                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 169                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 170                            vma->node.start, vma->node.size);
 171                 if (i915_vma_is_ggtt(vma))
 172                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 173                 if (vma->fence)
 174                         seq_printf(m, " , fence: %d%s",
 175                                    vma->fence->id,
 176                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 177                 seq_puts(m, ")");
 178         }
 179         if (obj->stolen)
 180                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 181
 182         engine = i915_gem_object_last_write_engine(obj);
 183         if (engine)
 184                 seq_printf(m, " (%s)", engine->name);
 185
 186         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 187         if (frontbuffer_bits)
 188                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 189 }
 190
 191 static int obj_rank_by_stolen(void *priv,
 192                               struct list_head *A, struct list_head *B)
 193 {
 194         struct drm_i915_gem_object *a =
 195                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 196         struct drm_i915_gem_object *b =
 197                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 198
 199         if (a->stolen->start < b->stolen->start)
 200                 return -1;
 201         if (a->stolen->start > b->stolen->start)
 202                 return 1;
 203         return 0;
 204 }
 205
 206 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 207 {
 208         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 209         struct drm_device *dev = &dev_priv->drm;
 210         struct drm_i915_gem_object *obj;
 211         u64 total_obj_size, total_gtt_size;
 212         LIST_HEAD(stolen);
 213         int count, ret;
 214
 215         ret = mutex_lock_interruptible(&dev->struct_mutex);
 216         if (ret)
 217                 return ret;
 218
 219         total_obj_size = total_gtt_size = count = 0;
 220         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 221                 if (obj->stolen == NULL)
 222                         continue;
 223
 224                 list_add(&obj->obj_exec_link, &stolen);
 225
 226                 total_obj_size += obj->base.size;
 227                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 228                 count++;
 229         }
 230         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 231                 if (obj->stolen == NULL)
 232                         continue;
 233
 234                 list_add(&obj->obj_exec_link, &stolen);
 235
 236                 total_obj_size += obj->base.size;
 237                 count++;
 238         }
 239         list_sort(NULL, &stolen, obj_rank_by_stolen);
 240         seq_puts(m, "Stolen:\n");
 241         while (!list_empty(&stolen)) {
 242                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 243                 seq_puts(m, "   ");
 244                 describe_obj(m, obj);
 245                 seq_putc(m, '\n');
 246                 list_del_init(&obj->obj_exec_link);
 247         }
 248         mutex_unlock(&dev->struct_mutex);
 249
 250         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 251                    count, total_obj_size, total_gtt_size);
 252         return 0;
 253 }
 254
 255 struct file_stats {
 256         struct drm_i915_file_private *file_priv;
 257         unsigned long count;
 258         u64 total, unbound;
 259         u64 global, shared;
 260         u64 active, inactive;
 261 };
 262
 263 static int per_file_stats(int id, void *ptr, void *data)
 264 {
 265         struct drm_i915_gem_object *obj = ptr;
 266         struct file_stats *stats = data;
 267         struct i915_vma *vma;
 268
 269         stats->count++;
 270         stats->total += obj->base.size;
 271         if (!obj->bind_count)
 272                 stats->unbound += obj->base.size;
 273         if (obj->base.name || obj->base.dma_buf)
 274                 stats->shared += obj->base.size;
 275
 276         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 277                 if (!drm_mm_node_allocated(&vma->node))
 278                         continue;
 279
 280                 if (i915_vma_is_ggtt(vma)) {
 281                         stats->global += vma->node.size;
 282                 } else {
 283                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 284
 285                         if (ppgtt->base.file != stats->file_priv)
 286                                 continue;
 287                 }
 288
 289                 if (i915_vma_is_active(vma))
 290                         stats->active += vma->node.size;
 291                 else
 292                         stats->inactive += vma->node.size;
 293         }
 294
 295         return 0;
 296 }
 297
 298 #define print_file_stats(m, name, stats) do { \
 299         if (stats.count) \
 300                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 301                            name, \
 302                            stats.count, \
 303                            stats.total, \
 304                            stats.active, \
 305                            stats.inactive, \
 306                            stats.global, \
 307                            stats.shared, \
 308                            stats.unbound); \
 309 } while (0)
 310
 311 static void print_batch_pool_stats(struct seq_file *m,
 312                                    struct drm_i915_private *dev_priv)
 313 {
 314         struct drm_i915_gem_object *obj;
 315         struct file_stats stats;
 316         struct intel_engine_cs *engine;
 317         enum intel_engine_id id;
 318         int j;
 319
 320         memset(&stats, 0, sizeof(stats));
 321
 322         for_each_engine(engine, dev_priv, id) {
 323                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 324                         list_for_each_entry(obj,
 325                                             &engine->batch_pool.cache_list[j],
 326                                             batch_pool_link)
 327                                 per_file_stats(0, obj, &stats);
 328                 }
 329         }
 330
 331         print_file_stats(m, "[k]batch pool", stats);
 332 }
 333
 334 static int per_file_ctx_stats(int id, void *ptr, void *data)
 335 {
 336         struct i915_gem_context *ctx = ptr;
 337         int n;
 338
 339         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 340                 if (ctx->engine[n].state)
 341                         per_file_stats(0, ctx->engine[n].state->obj, data);
 342                 if (ctx->engine[n].ring)
 343                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 344         }
 345
 346         return 0;
 347 }
 348
 349 static void print_context_stats(struct seq_file *m,
 350                                 struct drm_i915_private *dev_priv)
 351 {
 352         struct drm_device *dev = &dev_priv->drm;
 353         struct file_stats stats;
 354         struct drm_file *file;
 355
 356         memset(&stats, 0, sizeof(stats));
 357
 358         mutex_lock(&dev->struct_mutex);
 359         if (dev_priv->kernel_context)
 360                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 361
 362         list_for_each_entry(file, &dev->filelist, lhead) {
 363                 struct drm_i915_file_private *fpriv = file->driver_priv;
 364                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 365         }
 366         mutex_unlock(&dev->struct_mutex);
 367
 368         print_file_stats(m, "[k]contexts", stats);
 369 }
 370
 371 static int i915_gem_object_info(struct seq_file *m, void *data)
 372 {
 373         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 374         struct drm_device *dev = &dev_priv->drm;
 375         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 376         u32 count, mapped_count, purgeable_count, dpy_count;
 377         u64 size, mapped_size, purgeable_size, dpy_size;
 378         struct drm_i915_gem_object *obj;
 379         struct drm_file *file;
 380         int ret;
 381
 382         ret = mutex_lock_interruptible(&dev->struct_mutex);
 383         if (ret)
 384                 return ret;
 385
 386         seq_printf(m, "%u objects, %llu bytes\n",
 387                    dev_priv->mm.object_count,
 388                    dev_priv->mm.object_memory);
 389
 390         size = count = 0;
 391         mapped_size = mapped_count = 0;
 392         purgeable_size = purgeable_count = 0;
 393         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 394                 size += obj->base.size;
 395                 ++count;
 396
 397                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 398                         purgeable_size += obj->base.size;
 399                         ++purgeable_count;
 400                 }
 401
 402                 if (obj->mm.mapping) {
 403                         mapped_count++;
 404                         mapped_size += obj->base.size;
 405                 }
 406         }
 407         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 408
 409         size = count = dpy_size = dpy_count = 0;
 410         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 411                 size += obj->base.size;
 412                 ++count;
 413
 414                 if (obj->pin_display) {
 415                         dpy_size += obj->base.size;
 416                         ++dpy_count;
 417                 }
 418
 419                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 420                         purgeable_size += obj->base.size;
 421                         ++purgeable_count;
 422                 }
 423
 424                 if (obj->mm.mapping) {
 425                         mapped_count++;
 426                         mapped_size += obj->base.size;
 427                 }
 428         }
 429         seq_printf(m, "%u bound objects, %llu bytes\n",
 430                    count, size);
 431         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 432                    purgeable_count, purgeable_size);
 433         seq_printf(m, "%u mapped objects, %llu bytes\n",
 434                    mapped_count, mapped_size);
 435         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 436                    dpy_count, dpy_size);
 437
 438         seq_printf(m, "%llu [%llu] gtt total\n",
 439                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 440
 441         seq_putc(m, '\n');
 442         print_batch_pool_stats(m, dev_priv);
 443         mutex_unlock(&dev->struct_mutex);
 444
 445         mutex_lock(&dev->filelist_mutex);
 446         print_context_stats(m, dev_priv);
 447         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 448                 struct file_stats stats;
 449                 struct drm_i915_file_private *file_priv = file->driver_priv;
 450                 struct drm_i915_gem_request *request;
 451                 struct task_struct *task;
 452
 453                 memset(&stats, 0, sizeof(stats));
 454                 stats.file_priv = file->driver_priv;
 455                 spin_lock(&file->table_lock);
 456                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 457                 spin_unlock(&file->table_lock);
 458                 /*
 459                  * Although we have a valid reference on file->pid, that does
 460                  * not guarantee that the task_struct who called get_pid() is
 461                  * still alive (e.g. get_pid(current) => fork() => exit()).
 462                  * Therefore, we need to protect this ->comm access using RCU.
 463                  */
 464                 mutex_lock(&dev->struct_mutex);
 465                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 466                                                    struct drm_i915_gem_request,
 467                                                    client_list);
 468                 rcu_read_lock();
 469                 task = pid_task(request && request->ctx->pid ?
 470                                 request->ctx->pid : file->pid,
 471                                 PIDTYPE_PID);
 472                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 473                 rcu_read_unlock();
 474                 mutex_unlock(&dev->struct_mutex);
 475         }
 476         mutex_unlock(&dev->filelist_mutex);
 477
 478         return 0;
 479 }
 480
 481 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 482 {
 483         struct drm_info_node *node = m->private;
 484         struct drm_i915_private *dev_priv = node_to_i915(node);
 485         struct drm_device *dev = &dev_priv->drm;
 486         bool show_pin_display_only = !!node->info_ent->data;
 487         struct drm_i915_gem_object *obj;
 488         u64 total_obj_size, total_gtt_size;
 489         int count, ret;
 490
 491         ret = mutex_lock_interruptible(&dev->struct_mutex);
 492         if (ret)
 493                 return ret;
 494
 495         total_obj_size = total_gtt_size = count = 0;
 496         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 497                 if (show_pin_display_only && !obj->pin_display)
 498                         continue;
 499
 500                 seq_puts(m, "   ");
 501                 describe_obj(m, obj);
 502                 seq_putc(m, '\n');
 503                 total_obj_size += obj->base.size;
 504                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 505                 count++;
 506         }
 507
 508         mutex_unlock(&dev->struct_mutex);
 509
 510         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 511                    count, total_obj_size, total_gtt_size);
 512
 513         return 0;
 514 }
 515
 516 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 517 {
 518         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 519         struct drm_device *dev = &dev_priv->drm;
 520         struct intel_crtc *crtc;
 521         int ret;
 522
 523         ret = mutex_lock_interruptible(&dev->struct_mutex);
 524         if (ret)
 525                 return ret;
 526
 527         for_each_intel_crtc(dev, crtc) {
 528                 const char pipe = pipe_name(crtc->pipe);
 529                 const char plane = plane_name(crtc->plane);
 530                 struct intel_flip_work *work;
 531
 532                 spin_lock_irq(&dev->event_lock);
 533                 work = crtc->flip_work;
 534                 if (work == NULL) {
 535                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 536                                    pipe, plane);
 537                 } else {
 538                         u32 pending;
 539                         u32 addr;
 540
 541                         pending = atomic_read(&work->pending);
 542                         if (pending) {
 543                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 544                                            pipe, plane);
 545                         } else {
 546                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 547                                            pipe, plane);
 548                         }
 549                         if (work->flip_queued_req) {
 550                                 struct intel_engine_cs *engine = work->flip_queued_req->engine;
 551
 552                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 553                                            engine->name,
 554                                            work->flip_queued_req->global_seqno,
 555                                            atomic_read(&dev_priv->gt.global_timeline.next_seqno),
 556                                            intel_engine_get_seqno(engine),
 557                                            i915_gem_request_completed(work->flip_queued_req));
 558                         } else
 559                                 seq_printf(m, "Flip not associated with any ring\n");
 560                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 561                                    work->flip_queued_vblank,
 562                                    work->flip_ready_vblank,
 563                                    intel_crtc_get_vblank_counter(crtc));
 564                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 565
 566                         if (INTEL_GEN(dev_priv) >= 4)
 567                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 568                         else
 569                                 addr = I915_READ(DSPADDR(crtc->plane));
 570                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 571
 572                         if (work->pending_flip_obj) {
 573                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 574                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 575                         }
 576                 }
 577                 spin_unlock_irq(&dev->event_lock);
 578         }
 579
 580         mutex_unlock(&dev->struct_mutex);
 581
 582         return 0;
 583 }
 584
 585 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 586 {
 587         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 588         struct drm_device *dev = &dev_priv->drm;
 589         struct drm_i915_gem_object *obj;
 590         struct intel_engine_cs *engine;
 591         enum intel_engine_id id;
 592         int total = 0;
 593         int ret, j;
 594
 595         ret = mutex_lock_interruptible(&dev->struct_mutex);
 596         if (ret)
 597                 return ret;
 598
 599         for_each_engine(engine, dev_priv, id) {
 600                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 601                         int count;
 602
 603                         count = 0;
 604                         list_for_each_entry(obj,
 605                                             &engine->batch_pool.cache_list[j],
 606                                             batch_pool_link)
 607                                 count++;
 608                         seq_printf(m, "%s cache[%d]: %d objects\n",
 609                                    engine->name, j, count);
 610
 611                         list_for_each_entry(obj,
 612                                             &engine->batch_pool.cache_list[j],
 613                                             batch_pool_link) {
 614                                 seq_puts(m, "   ");
 615                                 describe_obj(m, obj);
 616                                 seq_putc(m, '\n');
 617                         }
 618
 619                         total += count;
 620                 }
 621         }
 622
 623         seq_printf(m, "total: %d\n", total);
 624
 625         mutex_unlock(&dev->struct_mutex);
 626
 627         return 0;
 628 }
 629
 630 static void print_request(struct seq_file *m,
 631                           struct drm_i915_gem_request *rq,
 632                           const char *prefix)
 633 {
 634         seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
 635                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 636                    rq->priotree.priority,
 637                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 638                    rq->timeline->common->name);
 639 }
 640
 641 static int i915_gem_request_info(struct seq_file *m, void *data)
 642 {
 643         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 644         struct drm_device *dev = &dev_priv->drm;
 645         struct drm_i915_gem_request *req;
 646         struct intel_engine_cs *engine;
 647         enum intel_engine_id id;
 648         int ret, any;
 649
 650         ret = mutex_lock_interruptible(&dev->struct_mutex);
 651         if (ret)
 652                 return ret;
 653
 654         any = 0;
 655         for_each_engine(engine, dev_priv, id) {
 656                 int count;
 657
 658                 count = 0;
 659                 list_for_each_entry(req, &engine->timeline->requests, link)
 660                         count++;
 661                 if (count == 0)
 662                         continue;
 663
 664                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 665                 list_for_each_entry(req, &engine->timeline->requests, link)
 666                         print_request(m, req, "    ");
 667
 668                 any++;
 669         }
 670         mutex_unlock(&dev->struct_mutex);
 671
 672         if (any == 0)
 673                 seq_puts(m, "No requests\n");
 674
 675         return 0;
 676 }
 677
 678 static void i915_ring_seqno_info(struct seq_file *m,
 679                                  struct intel_engine_cs *engine)
 680 {
 681         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 682         struct rb_node *rb;
 683
 684         seq_printf(m, "Current sequence (%s): %x\n",
 685                    engine->name, intel_engine_get_seqno(engine));
 686
 687         spin_lock_irq(&b->lock);
 688         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 689                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 690
 691                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 692                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 693         }
 694         spin_unlock_irq(&b->lock);
 695 }
 696
 697 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 698 {
 699         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 700         struct intel_engine_cs *engine;
 701         enum intel_engine_id id;
 702
 703         for_each_engine(engine, dev_priv, id)
 704                 i915_ring_seqno_info(m, engine);
 705
 706         return 0;
 707 }
 708
 709
 710 static int i915_interrupt_info(struct seq_file *m, void *data)
 711 {
 712         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 713         struct intel_engine_cs *engine;
 714         enum intel_engine_id id;
 715         int i, pipe;
 716
 717         intel_runtime_pm_get(dev_priv);
 718
 719         if (IS_CHERRYVIEW(dev_priv)) {
 720                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 721                            I915_READ(GEN8_MASTER_IRQ));
 722
 723                 seq_printf(m, "Display IER:\t%08x\n",
 724                            I915_READ(VLV_IER));
 725                 seq_printf(m, "Display IIR:\t%08x\n",
 726                            I915_READ(VLV_IIR));
 727                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 728                            I915_READ(VLV_IIR_RW));
 729                 seq_printf(m, "Display IMR:\t%08x\n",
 730                            I915_READ(VLV_IMR));
 731                 for_each_pipe(dev_priv, pipe) {
 732                         enum intel_display_power_domain power_domain;
 733
 734                         power_domain = POWER_DOMAIN_PIPE(pipe);
 735                         if (!intel_display_power_get_if_enabled(dev_priv,
 736                                                                 power_domain)) {
 737                                 seq_printf(m, "Pipe %c power disabled\n",
 738                                            pipe_name(pipe));
 739                                 continue;
 740                         }
 741
 742                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 743                                    pipe_name(pipe),
 744                                    I915_READ(PIPESTAT(pipe)));
 745
 746                         intel_display_power_put(dev_priv, power_domain);
 747                 }
 748
 749                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 750                 seq_printf(m, "Port hotplug:\t%08x\n",
 751                            I915_READ(PORT_HOTPLUG_EN));
 752                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 753                            I915_READ(VLV_DPFLIPSTAT));
 754                 seq_printf(m, "DPINVGTT:\t%08x\n",
 755                            I915_READ(DPINVGTT));
 756                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 757
 758                 for (i = 0; i < 4; i++) {
 759                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 760                                    i, I915_READ(GEN8_GT_IMR(i)));
 761                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 762                                    i, I915_READ(GEN8_GT_IIR(i)));
 763                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 764                                    i, I915_READ(GEN8_GT_IER(i)));
 765                 }
 766
 767                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 768                            I915_READ(GEN8_PCU_IMR));
 769                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 770                            I915_READ(GEN8_PCU_IIR));
 771                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 772                            I915_READ(GEN8_PCU_IER));
 773         } else if (INTEL_GEN(dev_priv) >= 8) {
 774                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 775                            I915_READ(GEN8_MASTER_IRQ));
 776
 777                 for (i = 0; i < 4; i++) {
 778                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 779                                    i, I915_READ(GEN8_GT_IMR(i)));
 780                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 781                                    i, I915_READ(GEN8_GT_IIR(i)));
 782                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 783                                    i, I915_READ(GEN8_GT_IER(i)));
 784                 }
 785
 786                 for_each_pipe(dev_priv, pipe) {
 787                         enum intel_display_power_domain power_domain;
 788
 789                         power_domain = POWER_DOMAIN_PIPE(pipe);
 790                         if (!intel_display_power_get_if_enabled(dev_priv,
 791                                                                 power_domain)) {
 792                                 seq_printf(m, "Pipe %c power disabled\n",
 793                                            pipe_name(pipe));
 794                                 continue;
 795                         }
 796                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 797                                    pipe_name(pipe),
 798                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 799                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 800                                    pipe_name(pipe),
 801                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 802                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 803                                    pipe_name(pipe),
 804                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 805
 806                         intel_display_power_put(dev_priv, power_domain);
 807                 }
 808
 809                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 810                            I915_READ(GEN8_DE_PORT_IMR));
 811                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 812                            I915_READ(GEN8_DE_PORT_IIR));
 813                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 814                            I915_READ(GEN8_DE_PORT_IER));
 815
 816                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 817                            I915_READ(GEN8_DE_MISC_IMR));
 818                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 819                            I915_READ(GEN8_DE_MISC_IIR));
 820                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 821                            I915_READ(GEN8_DE_MISC_IER));
 822
 823                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 824                            I915_READ(GEN8_PCU_IMR));
 825                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 826                            I915_READ(GEN8_PCU_IIR));
 827                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 828                            I915_READ(GEN8_PCU_IER));
 829         } else if (IS_VALLEYVIEW(dev_priv)) {
 830                 seq_printf(m, "Display IER:\t%08x\n",
 831                            I915_READ(VLV_IER));
 832                 seq_printf(m, "Display IIR:\t%08x\n",
 833                            I915_READ(VLV_IIR));
 834                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 835                            I915_READ(VLV_IIR_RW));
 836                 seq_printf(m, "Display IMR:\t%08x\n",
 837                            I915_READ(VLV_IMR));
 838                 for_each_pipe(dev_priv, pipe)
 839                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 840                                    pipe_name(pipe),
 841                                    I915_READ(PIPESTAT(pipe)));
 842
 843                 seq_printf(m, "Master IER:\t%08x\n",
 844                            I915_READ(VLV_MASTER_IER));
 845
 846                 seq_printf(m, "Render IER:\t%08x\n",
 847                            I915_READ(GTIER));
 848                 seq_printf(m, "Render IIR:\t%08x\n",
 849                            I915_READ(GTIIR));
 850                 seq_printf(m, "Render IMR:\t%08x\n",
 851                            I915_READ(GTIMR));
 852
 853                 seq_printf(m, "PM IER:\t\t%08x\n",
 854                            I915_READ(GEN6_PMIER));
 855                 seq_printf(m, "PM IIR:\t\t%08x\n",
 856                            I915_READ(GEN6_PMIIR));
 857                 seq_printf(m, "PM IMR:\t\t%08x\n",
 858                            I915_READ(GEN6_PMIMR));
 859
 860                 seq_printf(m, "Port hotplug:\t%08x\n",
 861                            I915_READ(PORT_HOTPLUG_EN));
 862                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 863                            I915_READ(VLV_DPFLIPSTAT));
 864                 seq_printf(m, "DPINVGTT:\t%08x\n",
 865                            I915_READ(DPINVGTT));
 866
 867         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 868                 seq_printf(m, "Interrupt enable:    %08x\n",
 869                            I915_READ(IER));
 870                 seq_printf(m, "Interrupt identity:  %08x\n",
 871                            I915_READ(IIR));
 872                 seq_printf(m, "Interrupt mask:      %08x\n",
 873                            I915_READ(IMR));
 874                 for_each_pipe(dev_priv, pipe)
 875                         seq_printf(m, "Pipe %c stat:         %08x\n",
 876                                    pipe_name(pipe),
 877                                    I915_READ(PIPESTAT(pipe)));
 878         } else {
 879                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 880                            I915_READ(DEIER));
 881                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 882                            I915_READ(DEIIR));
 883                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 884                            I915_READ(DEIMR));
 885                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 886                            I915_READ(SDEIER));
 887                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 888                            I915_READ(SDEIIR));
 889                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 890                            I915_READ(SDEIMR));
 891                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 892                            I915_READ(GTIER));
 893                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 894                            I915_READ(GTIIR));
 895                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 896                            I915_READ(GTIMR));
 897         }
 898         for_each_engine(engine, dev_priv, id) {
 899                 if (INTEL_GEN(dev_priv) >= 6) {
 900                         seq_printf(m,
 901                                    "Graphics Interrupt mask (%s):       %08x\n",
 902                                    engine->name, I915_READ_IMR(engine));
 903                 }
 904                 i915_ring_seqno_info(m, engine);
 905         }
 906         intel_runtime_pm_put(dev_priv);
 907
 908         return 0;
 909 }
 910
 911 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 912 {
 913         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 914         struct drm_device *dev = &dev_priv->drm;
 915         int i, ret;
 916
 917         ret = mutex_lock_interruptible(&dev->struct_mutex);
 918         if (ret)
 919                 return ret;
 920
 921         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 922         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 923                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 924
 925                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 926                            i, dev_priv->fence_regs[i].pin_count);
 927                 if (!vma)
 928                         seq_puts(m, "unused");
 929                 else
 930                         describe_obj(m, vma->obj);
 931                 seq_putc(m, '\n');
 932         }
 933
 934         mutex_unlock(&dev->struct_mutex);
 935         return 0;
 936 }
 937
 938 static int i915_hws_info(struct seq_file *m, void *data)
 939 {
 940         struct drm_info_node *node = m->private;
 941         struct drm_i915_private *dev_priv = node_to_i915(node);
 942         struct intel_engine_cs *engine;
 943         const u32 *hws;
 944         int i;
 945
 946         engine = dev_priv->engine[(uintptr_t)node->info_ent->data];
 947         hws = engine->status_page.page_addr;
 948         if (hws == NULL)
 949                 return 0;
 950
 951         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 952                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 953                            i * 4,
 954                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 955         }
 956         return 0;
 957 }
 958
 959 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 960
 961 static ssize_t
 962 i915_error_state_write(struct file *filp,
 963                        const char __user *ubuf,
 964                        size_t cnt,
 965                        loff_t *ppos)
 966 {
 967         struct i915_error_state_file_priv *error_priv = filp->private_data;
 968
 969         DRM_DEBUG_DRIVER("Resetting error state\n");
 970         i915_destroy_error_state(error_priv->dev);
 971
 972         return cnt;
 973 }
 974
 975 static int i915_error_state_open(struct inode *inode, struct file *file)
 976 {
 977         struct drm_i915_private *dev_priv = inode->i_private;
 978         struct i915_error_state_file_priv *error_priv;
 979
 980         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 981         if (!error_priv)
 982                 return -ENOMEM;
 983
 984         error_priv->dev = &dev_priv->drm;
 985
 986         i915_error_state_get(&dev_priv->drm, error_priv);
 987
 988         file->private_data = error_priv;
 989
 990         return 0;
 991 }
 992
 993 static int i915_error_state_release(struct inode *inode, struct file *file)
 994 {
 995         struct i915_error_state_file_priv *error_priv = file->private_data;
 996
 997         i915_error_state_put(error_priv);
 998         kfree(error_priv);
 999
1000         return 0;
1001 }
1002
1003 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1004                                      size_t count, loff_t *pos)
1005 {
1006         struct i915_error_state_file_priv *error_priv = file->private_data;
1007         struct drm_i915_error_state_buf error_str;
1008         loff_t tmp_pos = 0;
1009         ssize_t ret_count = 0;
1010         int ret;
1011
1012         ret = i915_error_state_buf_init(&error_str,
1013                                         to_i915(error_priv->dev), count, *pos);
1014         if (ret)
1015                 return ret;
1016
1017         ret = i915_error_state_to_str(&error_str, error_priv);
1018         if (ret)
1019                 goto out;
1020
1021         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1022                                             error_str.buf,
1023                                             error_str.bytes);
1024
1025         if (ret_count < 0)
1026                 ret = ret_count;
1027         else
1028                 *pos = error_str.start + ret_count;
1029 out:
1030         i915_error_state_buf_release(&error_str);
1031         return ret ?: ret_count;
1032 }
1033
1034 static const struct file_operations i915_error_state_fops = {
1035         .owner = THIS_MODULE,
1036         .open = i915_error_state_open,
1037         .read = i915_error_state_read,
1038         .write = i915_error_state_write,
1039         .llseek = default_llseek,
1040         .release = i915_error_state_release,
1041 };
1042
1043 #endif
1044
1045 static int
1046 i915_next_seqno_get(void *data, u64 *val)
1047 {
1048         struct drm_i915_private *dev_priv = data;
1049
1050         *val = atomic_read(&dev_priv->gt.global_timeline.next_seqno);
1051         return 0;
1052 }
1053
1054 static int
1055 i915_next_seqno_set(void *data, u64 val)
1056 {
1057         struct drm_i915_private *dev_priv = data;
1058         struct drm_device *dev = &dev_priv->drm;
1059         int ret;
1060
1061         ret = mutex_lock_interruptible(&dev->struct_mutex);
1062         if (ret)
1063                 return ret;
1064
1065         ret = i915_gem_set_global_seqno(dev, val);
1066         mutex_unlock(&dev->struct_mutex);
1067
1068         return ret;
1069 }
1070
1071 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1072                         i915_next_seqno_get, i915_next_seqno_set,
1073                         "0x%llx\n");
1074
1075 static int i915_frequency_info(struct seq_file *m, void *unused)
1076 {
1077         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1078         struct drm_device *dev = &dev_priv->drm;
1079         int ret = 0;
1080
1081         intel_runtime_pm_get(dev_priv);
1082
1083         if (IS_GEN5(dev_priv)) {
1084                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1085                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1086
1087                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1088                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1089                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1090                            MEMSTAT_VID_SHIFT);
1091                 seq_printf(m, "Current P-state: %d\n",
1092                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1093         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1094                 u32 freq_sts;
1095
1096                 mutex_lock(&dev_priv->rps.hw_lock);
1097                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1098                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1099                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1100
1101                 seq_printf(m, "actual GPU freq: %d MHz\n",
1102                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1103
1104                 seq_printf(m, "current GPU freq: %d MHz\n",
1105                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1106
1107                 seq_printf(m, "max GPU freq: %d MHz\n",
1108                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1109
1110                 seq_printf(m, "min GPU freq: %d MHz\n",
1111                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1112
1113                 seq_printf(m, "idle GPU freq: %d MHz\n",
1114                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1115
1116                 seq_printf(m,
1117                            "efficient (RPe) frequency: %d MHz\n",
1118                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1119                 mutex_unlock(&dev_priv->rps.hw_lock);
1120         } else if (INTEL_GEN(dev_priv) >= 6) {
1121                 u32 rp_state_limits;
1122                 u32 gt_perf_status;
1123                 u32 rp_state_cap;
1124                 u32 rpmodectl, rpinclimit, rpdeclimit;
1125                 u32 rpstat, cagf, reqf;
1126                 u32 rpupei, rpcurup, rpprevup;
1127                 u32 rpdownei, rpcurdown, rpprevdown;
1128                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1129                 int max_freq;
1130
1131                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1132                 if (IS_BROXTON(dev_priv)) {
1133                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1134                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1135                 } else {
1136                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1137                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1138                 }
1139
1140                 /* RPSTAT1 is in the GT power well */
1141                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1142                 if (ret)
1143                         goto out;
1144
1145                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1146
1147                 reqf = I915_READ(GEN6_RPNSWREQ);
1148                 if (IS_GEN9(dev_priv))
1149                         reqf >>= 23;
1150                 else {
1151                         reqf &= ~GEN6_TURBO_DISABLE;
1152                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1153                                 reqf >>= 24;
1154                         else
1155                                 reqf >>= 25;
1156                 }
1157                 reqf = intel_gpu_freq(dev_priv, reqf);
1158
1159                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1160                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1161                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1162
1163                 rpstat = I915_READ(GEN6_RPSTAT1);
1164                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1165                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1166                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1167                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1168                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1169                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1170                 if (IS_GEN9(dev_priv))
1171                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1172                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1173                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1174                 else
1175                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1176                 cagf = intel_gpu_freq(dev_priv, cagf);
1177
1178                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1179                 mutex_unlock(&dev->struct_mutex);
1180
1181                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1182                         pm_ier = I915_READ(GEN6_PMIER);
1183                         pm_imr = I915_READ(GEN6_PMIMR);
1184                         pm_isr = I915_READ(GEN6_PMISR);
1185                         pm_iir = I915_READ(GEN6_PMIIR);
1186                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1187                 } else {
1188                         pm_ier = I915_READ(GEN8_GT_IER(2));
1189                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1190                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1191                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1192                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1193                 }
1194                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1195                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1196                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1197                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1198                 seq_printf(m, "Render p-state ratio: %d\n",
1199                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1200                 seq_printf(m, "Render p-state VID: %d\n",
1201                            gt_perf_status & 0xff);
1202                 seq_printf(m, "Render p-state limit: %d\n",
1203                            rp_state_limits & 0xff);
1204                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1205                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1206                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1207                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1208                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1209                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1210                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1211                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1212                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1213                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1214                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1215                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1216                 seq_printf(m, "Up threshold: %d%%\n",
1217                            dev_priv->rps.up_threshold);
1218
1219                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1220                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1221                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1222                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1223                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1224                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1225                 seq_printf(m, "Down threshold: %d%%\n",
1226                            dev_priv->rps.down_threshold);
1227
1228                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1229                             rp_state_cap >> 16) & 0xff;
1230                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1231                              GEN9_FREQ_SCALER : 1);
1232                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1233                            intel_gpu_freq(dev_priv, max_freq));
1234
1235                 max_freq = (rp_state_cap & 0xff00) >> 8;
1236                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1237                              GEN9_FREQ_SCALER : 1);
1238                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1239                            intel_gpu_freq(dev_priv, max_freq));
1240
1241                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1242                             rp_state_cap >> 0) & 0xff;
1243                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1244                              GEN9_FREQ_SCALER : 1);
1245                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1246                            intel_gpu_freq(dev_priv, max_freq));
1247                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1248                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1249
1250                 seq_printf(m, "Current freq: %d MHz\n",
1251                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1252                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1253                 seq_printf(m, "Idle freq: %d MHz\n",
1254                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1255                 seq_printf(m, "Min freq: %d MHz\n",
1256                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1257                 seq_printf(m, "Boost freq: %d MHz\n",
1258                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1259                 seq_printf(m, "Max freq: %d MHz\n",
1260                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1261                 seq_printf(m,
1262                            "efficient (RPe) frequency: %d MHz\n",
1263                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1264         } else {
1265                 seq_puts(m, "no P-state info available\n");
1266         }
1267
1268         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1269         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1270         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1271
1272 out:
1273         intel_runtime_pm_put(dev_priv);
1274         return ret;
1275 }
1276
1277 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1278                                struct seq_file *m,
1279                                struct intel_instdone *instdone)
1280 {
1281         int slice;
1282         int subslice;
1283
1284         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1285                    instdone->instdone);
1286
1287         if (INTEL_GEN(dev_priv) <= 3)
1288                 return;
1289
1290         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1291                    instdone->slice_common);
1292
1293         if (INTEL_GEN(dev_priv) <= 6)
1294                 return;
1295
1296         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1297                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1298                            slice, subslice, instdone->sampler[slice][subslice]);
1299
1300         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1301                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1302                            slice, subslice, instdone->row[slice][subslice]);
1303 }
1304
1305 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1306 {
1307         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1308         struct intel_engine_cs *engine;
1309         u64 acthd[I915_NUM_ENGINES];
1310         u32 seqno[I915_NUM_ENGINES];
1311         struct intel_instdone instdone;
1312         enum intel_engine_id id;
1313
1314         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1315                 seq_printf(m, "Wedged\n");
1316         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1317                 seq_printf(m, "Reset in progress\n");
1318         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1319                 seq_printf(m, "Waiter holding struct mutex\n");
1320         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1321                 seq_printf(m, "struct_mutex blocked for reset\n");
1322
1323         if (!i915.enable_hangcheck) {
1324                 seq_printf(m, "Hangcheck disabled\n");
1325                 return 0;
1326         }
1327
1328         intel_runtime_pm_get(dev_priv);
1329
1330         for_each_engine(engine, dev_priv, id) {
1331                 acthd[id] = intel_engine_get_active_head(engine);
1332                 seqno[id] = intel_engine_get_seqno(engine);
1333         }
1334
1335         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1336
1337         intel_runtime_pm_put(dev_priv);
1338
1339         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1340                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1341                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1342                                             jiffies));
1343         } else
1344                 seq_printf(m, "Hangcheck inactive\n");
1345
1346         for_each_engine(engine, dev_priv, id) {
1347                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1348                 struct rb_node *rb;
1349
1350                 seq_printf(m, "%s:\n", engine->name);
1351                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1352                            engine->hangcheck.seqno, seqno[id],
1353                            intel_engine_last_submit(engine));
1354                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1355                            yesno(intel_engine_has_waiter(engine)),
1356                            yesno(test_bit(engine->id,
1357                                           &dev_priv->gpu_error.missed_irq_rings)));
1358                 spin_lock_irq(&b->lock);
1359                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1360                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1361
1362                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1363                                    w->tsk->comm, w->tsk->pid, w->seqno);
1364                 }
1365                 spin_unlock_irq(&b->lock);
1366
1367                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1368                            (long long)engine->hangcheck.acthd,
1369                            (long long)acthd[id]);
1370                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1371                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1372
1373                 if (engine->id == RCS) {
1374                         seq_puts(m, "\tinstdone read =\n");
1375
1376                         i915_instdone_info(dev_priv, m, &instdone);
1377
1378                         seq_puts(m, "\tinstdone accu =\n");
1379
1380                         i915_instdone_info(dev_priv, m,
1381                                            &engine->hangcheck.instdone);
1382                 }
1383         }
1384
1385         return 0;
1386 }
1387
1388 static int ironlake_drpc_info(struct seq_file *m)
1389 {
1390         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1391         u32 rgvmodectl, rstdbyctl;
1392         u16 crstandvid;
1393
1394         intel_runtime_pm_get(dev_priv);
1395
1396         rgvmodectl = I915_READ(MEMMODECTL);
1397         rstdbyctl = I915_READ(RSTDBYCTL);
1398         crstandvid = I915_READ16(CRSTANDVID);
1399
1400         intel_runtime_pm_put(dev_priv);
1401
1402         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1403         seq_printf(m, "Boost freq: %d\n",
1404                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1405                    MEMMODE_BOOST_FREQ_SHIFT);
1406         seq_printf(m, "HW control enabled: %s\n",
1407                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1408         seq_printf(m, "SW control enabled: %s\n",
1409                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1410         seq_printf(m, "Gated voltage change: %s\n",
1411                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1412         seq_printf(m, "Starting frequency: P%d\n",
1413                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1414         seq_printf(m, "Max P-state: P%d\n",
1415                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1416         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1417         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1418         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1419         seq_printf(m, "Render standby enabled: %s\n",
1420                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1421         seq_puts(m, "Current RS state: ");
1422         switch (rstdbyctl & RSX_STATUS_MASK) {
1423         case RSX_STATUS_ON:
1424                 seq_puts(m, "on\n");
1425                 break;
1426         case RSX_STATUS_RC1:
1427                 seq_puts(m, "RC1\n");
1428                 break;
1429         case RSX_STATUS_RC1E:
1430                 seq_puts(m, "RC1E\n");
1431                 break;
1432         case RSX_STATUS_RS1:
1433                 seq_puts(m, "RS1\n");
1434                 break;
1435         case RSX_STATUS_RS2:
1436                 seq_puts(m, "RS2 (RC6)\n");
1437                 break;
1438         case RSX_STATUS_RS3:
1439                 seq_puts(m, "RC3 (RC6+)\n");
1440                 break;
1441         default:
1442                 seq_puts(m, "unknown\n");
1443                 break;
1444         }
1445
1446         return 0;
1447 }
1448
1449 static int i915_forcewake_domains(struct seq_file *m, void *data)
1450 {
1451         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1452         struct intel_uncore_forcewake_domain *fw_domain;
1453
1454         spin_lock_irq(&dev_priv->uncore.lock);
1455         for_each_fw_domain(fw_domain, dev_priv) {
1456                 seq_printf(m, "%s.wake_count = %u\n",
1457                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1458                            fw_domain->wake_count);
1459         }
1460         spin_unlock_irq(&dev_priv->uncore.lock);
1461
1462         return 0;
1463 }
1464
1465 static int vlv_drpc_info(struct seq_file *m)
1466 {
1467         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1468         u32 rpmodectl1, rcctl1, pw_status;
1469
1470         intel_runtime_pm_get(dev_priv);
1471
1472         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1473         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1474         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1475
1476         intel_runtime_pm_put(dev_priv);
1477
1478         seq_printf(m, "Video Turbo Mode: %s\n",
1479                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1480         seq_printf(m, "Turbo enabled: %s\n",
1481                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1482         seq_printf(m, "HW control enabled: %s\n",
1483                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1484         seq_printf(m, "SW control enabled: %s\n",
1485                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1486                           GEN6_RP_MEDIA_SW_MODE));
1487         seq_printf(m, "RC6 Enabled: %s\n",
1488                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1489                                         GEN6_RC_CTL_EI_MODE(1))));
1490         seq_printf(m, "Render Power Well: %s\n",
1491                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1492         seq_printf(m, "Media Power Well: %s\n",
1493                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1494
1495         seq_printf(m, "Render RC6 residency since boot: %u\n",
1496                    I915_READ(VLV_GT_RENDER_RC6));
1497         seq_printf(m, "Media RC6 residency since boot: %u\n",
1498                    I915_READ(VLV_GT_MEDIA_RC6));
1499
1500         return i915_forcewake_domains(m, NULL);
1501 }
1502
1503 static int gen6_drpc_info(struct seq_file *m)
1504 {
1505         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1506         struct drm_device *dev = &dev_priv->drm;
1507         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1508         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1509         unsigned forcewake_count;
1510         int count = 0, ret;
1511
1512         ret = mutex_lock_interruptible(&dev->struct_mutex);
1513         if (ret)
1514                 return ret;
1515         intel_runtime_pm_get(dev_priv);
1516
1517         spin_lock_irq(&dev_priv->uncore.lock);
1518         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1519         spin_unlock_irq(&dev_priv->uncore.lock);
1520
1521         if (forcewake_count) {
1522                 seq_puts(m, "RC information inaccurate because somebody "
1523                             "holds a forcewake reference \n");
1524         } else {
1525                 /* NB: we cannot use forcewake, else we read the wrong values */
1526                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1527                         udelay(10);
1528                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1529         }
1530
1531         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1532         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1533
1534         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1535         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1536         if (INTEL_GEN(dev_priv) >= 9) {
1537                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1538                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1539         }
1540         mutex_unlock(&dev->struct_mutex);
1541         mutex_lock(&dev_priv->rps.hw_lock);
1542         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1543         mutex_unlock(&dev_priv->rps.hw_lock);
1544
1545         intel_runtime_pm_put(dev_priv);
1546
1547         seq_printf(m, "Video Turbo Mode: %s\n",
1548                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1549         seq_printf(m, "HW control enabled: %s\n",
1550                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1551         seq_printf(m, "SW control enabled: %s\n",
1552                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1553                           GEN6_RP_MEDIA_SW_MODE));
1554         seq_printf(m, "RC1e Enabled: %s\n",
1555                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1556         seq_printf(m, "RC6 Enabled: %s\n",
1557                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1558         if (INTEL_GEN(dev_priv) >= 9) {
1559                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1560                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1561                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1562                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1563         }
1564         seq_printf(m, "Deep RC6 Enabled: %s\n",
1565                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1566         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1567                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1568         seq_puts(m, "Current RC state: ");
1569         switch (gt_core_status & GEN6_RCn_MASK) {
1570         case GEN6_RC0:
1571                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1572                         seq_puts(m, "Core Power Down\n");
1573                 else
1574                         seq_puts(m, "on\n");
1575                 break;
1576         case GEN6_RC3:
1577                 seq_puts(m, "RC3\n");
1578                 break;
1579         case GEN6_RC6:
1580                 seq_puts(m, "RC6\n");
1581                 break;
1582         case GEN6_RC7:
1583                 seq_puts(m, "RC7\n");
1584                 break;
1585         default:
1586                 seq_puts(m, "Unknown\n");
1587                 break;
1588         }
1589
1590         seq_printf(m, "Core Power Down: %s\n",
1591                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1592         if (INTEL_GEN(dev_priv) >= 9) {
1593                 seq_printf(m, "Render Power Well: %s\n",
1594                         (gen9_powergate_status &
1595                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1596                 seq_printf(m, "Media Power Well: %s\n",
1597                         (gen9_powergate_status &
1598                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1599         }
1600
1601         /* Not exactly sure what this is */
1602         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1603                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1604         seq_printf(m, "RC6 residency since boot: %u\n",
1605                    I915_READ(GEN6_GT_GFX_RC6));
1606         seq_printf(m, "RC6+ residency since boot: %u\n",
1607                    I915_READ(GEN6_GT_GFX_RC6p));
1608         seq_printf(m, "RC6++ residency since boot: %u\n",
1609                    I915_READ(GEN6_GT_GFX_RC6pp));
1610
1611         seq_printf(m, "RC6   voltage: %dmV\n",
1612                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1613         seq_printf(m, "RC6+  voltage: %dmV\n",
1614                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1615         seq_printf(m, "RC6++ voltage: %dmV\n",
1616                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1617         return i915_forcewake_domains(m, NULL);
1618 }
1619
1620 static int i915_drpc_info(struct seq_file *m, void *unused)
1621 {
1622         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1623
1624         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1625                 return vlv_drpc_info(m);
1626         else if (INTEL_GEN(dev_priv) >= 6)
1627                 return gen6_drpc_info(m);
1628         else
1629                 return ironlake_drpc_info(m);
1630 }
1631
1632 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1633 {
1634         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1635
1636         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1637                    dev_priv->fb_tracking.busy_bits);
1638
1639         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1640                    dev_priv->fb_tracking.flip_bits);
1641
1642         return 0;
1643 }
1644
1645 static int i915_fbc_status(struct seq_file *m, void *unused)
1646 {
1647         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1648
1649         if (!HAS_FBC(dev_priv)) {
1650                 seq_puts(m, "FBC unsupported on this chipset\n");
1651                 return 0;
1652         }
1653
1654         intel_runtime_pm_get(dev_priv);
1655         mutex_lock(&dev_priv->fbc.lock);
1656
1657         if (intel_fbc_is_active(dev_priv))
1658                 seq_puts(m, "FBC enabled\n");
1659         else
1660                 seq_printf(m, "FBC disabled: %s\n",
1661                            dev_priv->fbc.no_fbc_reason);
1662
1663         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1664                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1665                                 BDW_FBC_COMPRESSION_MASK :
1666                                 IVB_FBC_COMPRESSION_MASK;
1667                 seq_printf(m, "Compressing: %s\n",
1668                            yesno(I915_READ(FBC_STATUS2) & mask));
1669         }
1670
1671         mutex_unlock(&dev_priv->fbc.lock);
1672         intel_runtime_pm_put(dev_priv);
1673
1674         return 0;
1675 }
1676
1677 static int i915_fbc_fc_get(void *data, u64 *val)
1678 {
1679         struct drm_i915_private *dev_priv = data;
1680
1681         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1682                 return -ENODEV;
1683
1684         *val = dev_priv->fbc.false_color;
1685
1686         return 0;
1687 }
1688
1689 static int i915_fbc_fc_set(void *data, u64 val)
1690 {
1691         struct drm_i915_private *dev_priv = data;
1692         u32 reg;
1693
1694         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1695                 return -ENODEV;
1696
1697         mutex_lock(&dev_priv->fbc.lock);
1698
1699         reg = I915_READ(ILK_DPFC_CONTROL);
1700         dev_priv->fbc.false_color = val;
1701
1702         I915_WRITE(ILK_DPFC_CONTROL, val ?
1703                    (reg | FBC_CTL_FALSE_COLOR) :
1704                    (reg & ~FBC_CTL_FALSE_COLOR));
1705
1706         mutex_unlock(&dev_priv->fbc.lock);
1707         return 0;
1708 }
1709
1710 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1711                         i915_fbc_fc_get, i915_fbc_fc_set,
1712                         "%llu\n");
1713
1714 static int i915_ips_status(struct seq_file *m, void *unused)
1715 {
1716         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1717
1718         if (!HAS_IPS(dev_priv)) {
1719                 seq_puts(m, "not supported\n");
1720                 return 0;
1721         }
1722
1723         intel_runtime_pm_get(dev_priv);
1724
1725         seq_printf(m, "Enabled by kernel parameter: %s\n",
1726                    yesno(i915.enable_ips));
1727
1728         if (INTEL_GEN(dev_priv) >= 8) {
1729                 seq_puts(m, "Currently: unknown\n");
1730         } else {
1731                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1732                         seq_puts(m, "Currently: enabled\n");
1733                 else
1734                         seq_puts(m, "Currently: disabled\n");
1735         }
1736
1737         intel_runtime_pm_put(dev_priv);
1738
1739         return 0;
1740 }
1741
1742 static int i915_sr_status(struct seq_file *m, void *unused)
1743 {
1744         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1745         bool sr_enabled = false;
1746
1747         intel_runtime_pm_get(dev_priv);
1748         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1749
1750         if (HAS_PCH_SPLIT(dev_priv))
1751                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1752         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1753                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1754                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1755         else if (IS_I915GM(dev_priv))
1756                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1757         else if (IS_PINEVIEW(dev_priv))
1758                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1759         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1760                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1761
1762         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1763         intel_runtime_pm_put(dev_priv);
1764
1765         seq_printf(m, "self-refresh: %s\n",
1766                    sr_enabled ? "enabled" : "disabled");
1767
1768         return 0;
1769 }
1770
1771 static int i915_emon_status(struct seq_file *m, void *unused)
1772 {
1773         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1774         struct drm_device *dev = &dev_priv->drm;
1775         unsigned long temp, chipset, gfx;
1776         int ret;
1777
1778         if (!IS_GEN5(dev_priv))
1779                 return -ENODEV;
1780
1781         ret = mutex_lock_interruptible(&dev->struct_mutex);
1782         if (ret)
1783                 return ret;
1784
1785         temp = i915_mch_val(dev_priv);
1786         chipset = i915_chipset_val(dev_priv);
1787         gfx = i915_gfx_val(dev_priv);
1788         mutex_unlock(&dev->struct_mutex);
1789
1790         seq_printf(m, "GMCH temp: %ld\n", temp);
1791         seq_printf(m, "Chipset power: %ld\n", chipset);
1792         seq_printf(m, "GFX power: %ld\n", gfx);
1793         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1794
1795         return 0;
1796 }
1797
1798 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1799 {
1800         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1801         int ret = 0;
1802         int gpu_freq, ia_freq;
1803         unsigned int max_gpu_freq, min_gpu_freq;
1804
1805         if (!HAS_LLC(dev_priv)) {
1806                 seq_puts(m, "unsupported on this chipset\n");
1807                 return 0;
1808         }
1809
1810         intel_runtime_pm_get(dev_priv);
1811
1812         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1813         if (ret)
1814                 goto out;
1815
1816         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1817                 /* Convert GT frequency to 50 HZ units */
1818                 min_gpu_freq =
1819                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1820                 max_gpu_freq =
1821                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1822         } else {
1823                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1824                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1825         }
1826
1827         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1828
1829         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1830                 ia_freq = gpu_freq;
1831                 sandybridge_pcode_read(dev_priv,
1832                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1833                                        &ia_freq);
1834                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1835                            intel_gpu_freq(dev_priv, (gpu_freq *
1836                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1837                                  GEN9_FREQ_SCALER : 1))),
1838                            ((ia_freq >> 0) & 0xff) * 100,
1839                            ((ia_freq >> 8) & 0xff) * 100);
1840         }
1841
1842         mutex_unlock(&dev_priv->rps.hw_lock);
1843
1844 out:
1845         intel_runtime_pm_put(dev_priv);
1846         return ret;
1847 }
1848
1849 static int i915_opregion(struct seq_file *m, void *unused)
1850 {
1851         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1852         struct drm_device *dev = &dev_priv->drm;
1853         struct intel_opregion *opregion = &dev_priv->opregion;
1854         int ret;
1855
1856         ret = mutex_lock_interruptible(&dev->struct_mutex);
1857         if (ret)
1858                 goto out;
1859
1860         if (opregion->header)
1861                 seq_write(m, opregion->header, OPREGION_SIZE);
1862
1863         mutex_unlock(&dev->struct_mutex);
1864
1865 out:
1866         return 0;
1867 }
1868
1869 static int i915_vbt(struct seq_file *m, void *unused)
1870 {
1871         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1872
1873         if (opregion->vbt)
1874                 seq_write(m, opregion->vbt, opregion->vbt_size);
1875
1876         return 0;
1877 }
1878
1879 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1880 {
1881         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1882         struct drm_device *dev = &dev_priv->drm;
1883         struct intel_framebuffer *fbdev_fb = NULL;
1884         struct drm_framebuffer *drm_fb;
1885         int ret;
1886
1887         ret = mutex_lock_interruptible(&dev->struct_mutex);
1888         if (ret)
1889                 return ret;
1890
1891 #ifdef CONFIG_DRM_FBDEV_EMULATION
1892         if (dev_priv->fbdev) {
1893                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1894
1895                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1896                            fbdev_fb->base.width,
1897                            fbdev_fb->base.height,
1898                            fbdev_fb->base.depth,
1899                            fbdev_fb->base.bits_per_pixel,
1900                            fbdev_fb->base.modifier[0],
1901                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1902                 describe_obj(m, fbdev_fb->obj);
1903                 seq_putc(m, '\n');
1904         }
1905 #endif
1906
1907         mutex_lock(&dev->mode_config.fb_lock);
1908         drm_for_each_fb(drm_fb, dev) {
1909                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1910                 if (fb == fbdev_fb)
1911                         continue;
1912
1913                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1914                            fb->base.width,
1915                            fb->base.height,
1916                            fb->base.depth,
1917                            fb->base.bits_per_pixel,
1918                            fb->base.modifier[0],
1919                            drm_framebuffer_read_refcount(&fb->base));
1920                 describe_obj(m, fb->obj);
1921                 seq_putc(m, '\n');
1922         }
1923         mutex_unlock(&dev->mode_config.fb_lock);
1924         mutex_unlock(&dev->struct_mutex);
1925
1926         return 0;
1927 }
1928
1929 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1930 {
1931         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1932                    ring->space, ring->head, ring->tail,
1933                    ring->last_retired_head);
1934 }
1935
1936 static int i915_context_status(struct seq_file *m, void *unused)
1937 {
1938         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1939         struct drm_device *dev = &dev_priv->drm;
1940         struct intel_engine_cs *engine;
1941         struct i915_gem_context *ctx;
1942         enum intel_engine_id id;
1943         int ret;
1944
1945         ret = mutex_lock_interruptible(&dev->struct_mutex);
1946         if (ret)
1947                 return ret;
1948
1949         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1950                 seq_printf(m, "HW context %u ", ctx->hw_id);
1951                 if (ctx->pid) {
1952                         struct task_struct *task;
1953
1954                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1955                         if (task) {
1956                                 seq_printf(m, "(%s [%d]) ",
1957                                            task->comm, task->pid);
1958                                 put_task_struct(task);
1959                         }
1960                 } else if (IS_ERR(ctx->file_priv)) {
1961                         seq_puts(m, "(deleted) ");
1962                 } else {
1963                         seq_puts(m, "(kernel) ");
1964                 }
1965
1966                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1967                 seq_putc(m, '\n');
1968
1969                 for_each_engine(engine, dev_priv, id) {
1970                         struct intel_context *ce = &ctx->engine[engine->id];
1971
1972                         seq_printf(m, "%s: ", engine->name);
1973                         seq_putc(m, ce->initialised ? 'I' : 'i');
1974                         if (ce->state)
1975                                 describe_obj(m, ce->state->obj);
1976                         if (ce->ring)
1977                                 describe_ctx_ring(m, ce->ring);
1978                         seq_putc(m, '\n');
1979                 }
1980
1981                 seq_putc(m, '\n');
1982         }
1983
1984         mutex_unlock(&dev->struct_mutex);
1985
1986         return 0;
1987 }
1988
1989 static void i915_dump_lrc_obj(struct seq_file *m,
1990                               struct i915_gem_context *ctx,
1991                               struct intel_engine_cs *engine)
1992 {
1993         struct i915_vma *vma = ctx->engine[engine->id].state;
1994         struct page *page;
1995         int j;
1996
1997         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1998
1999         if (!vma) {
2000                 seq_puts(m, "\tFake context\n");
2001                 return;
2002         }
2003
2004         if (vma->flags & I915_VMA_GLOBAL_BIND)
2005                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2006                            i915_ggtt_offset(vma));
2007
2008         if (i915_gem_object_pin_pages(vma->obj)) {
2009                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2010                 return;
2011         }
2012
2013         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2014         if (page) {
2015                 u32 *reg_state = kmap_atomic(page);
2016
2017                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2018                         seq_printf(m,
2019                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2020                                    j * 4,
2021                                    reg_state[j], reg_state[j + 1],
2022                                    reg_state[j + 2], reg_state[j + 3]);
2023                 }
2024                 kunmap_atomic(reg_state);
2025         }
2026
2027         i915_gem_object_unpin_pages(vma->obj);
2028         seq_putc(m, '\n');
2029 }
2030
2031 static int i915_dump_lrc(struct seq_file *m, void *unused)
2032 {
2033         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2034         struct drm_device *dev = &dev_priv->drm;
2035         struct intel_engine_cs *engine;
2036         struct i915_gem_context *ctx;
2037         enum intel_engine_id id;
2038         int ret;
2039
2040         if (!i915.enable_execlists) {
2041                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2042                 return 0;
2043         }
2044
2045         ret = mutex_lock_interruptible(&dev->struct_mutex);
2046         if (ret)
2047                 return ret;
2048
2049         list_for_each_entry(ctx, &dev_priv->context_list, link)
2050                 for_each_engine(engine, dev_priv, id)
2051                         i915_dump_lrc_obj(m, ctx, engine);
2052
2053         mutex_unlock(&dev->struct_mutex);
2054
2055         return 0;
2056 }
2057
2058 static const char *swizzle_string(unsigned swizzle)
2059 {
2060         switch (swizzle) {
2061         case I915_BIT_6_SWIZZLE_NONE:
2062                 return "none";
2063         case I915_BIT_6_SWIZZLE_9:
2064                 return "bit9";
2065         case I915_BIT_6_SWIZZLE_9_10:
2066                 return "bit9/bit10";
2067         case I915_BIT_6_SWIZZLE_9_11:
2068                 return "bit9/bit11";
2069         case I915_BIT_6_SWIZZLE_9_10_11:
2070                 return "bit9/bit10/bit11";
2071         case I915_BIT_6_SWIZZLE_9_17:
2072                 return "bit9/bit17";
2073         case I915_BIT_6_SWIZZLE_9_10_17:
2074                 return "bit9/bit10/bit17";
2075         case I915_BIT_6_SWIZZLE_UNKNOWN:
2076                 return "unknown";
2077         }
2078
2079         return "bug";
2080 }
2081
2082 static int i915_swizzle_info(struct seq_file *m, void *data)
2083 {
2084         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2085
2086         intel_runtime_pm_get(dev_priv);
2087
2088         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2089                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2090         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2091                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2092
2093         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2094                 seq_printf(m, "DDC = 0x%08x\n",
2095                            I915_READ(DCC));
2096                 seq_printf(m, "DDC2 = 0x%08x\n",
2097                            I915_READ(DCC2));
2098                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2099                            I915_READ16(C0DRB3));
2100                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2101                            I915_READ16(C1DRB3));
2102         } else if (INTEL_GEN(dev_priv) >= 6) {
2103                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2104                            I915_READ(MAD_DIMM_C0));
2105                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2106                            I915_READ(MAD_DIMM_C1));
2107                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2108                            I915_READ(MAD_DIMM_C2));
2109                 seq_printf(m, "TILECTL = 0x%08x\n",
2110                            I915_READ(TILECTL));
2111                 if (INTEL_GEN(dev_priv) >= 8)
2112                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2113                                    I915_READ(GAMTARBMODE));
2114                 else
2115                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2116                                    I915_READ(ARB_MODE));
2117                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2118                            I915_READ(DISP_ARB_CTL));
2119         }
2120
2121         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2122                 seq_puts(m, "L-shaped memory detected\n");
2123
2124         intel_runtime_pm_put(dev_priv);
2125
2126         return 0;
2127 }
2128
2129 static int per_file_ctx(int id, void *ptr, void *data)
2130 {
2131         struct i915_gem_context *ctx = ptr;
2132         struct seq_file *m = data;
2133         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2134
2135         if (!ppgtt) {
2136                 seq_printf(m, "  no ppgtt for context %d\n",
2137                            ctx->user_handle);
2138                 return 0;
2139         }
2140
2141         if (i915_gem_context_is_default(ctx))
2142                 seq_puts(m, "  default context:\n");
2143         else
2144                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2145         ppgtt->debug_dump(ppgtt, m);
2146
2147         return 0;
2148 }
2149
2150 static void gen8_ppgtt_info(struct seq_file *m,
2151                             struct drm_i915_private *dev_priv)
2152 {
2153         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2154         struct intel_engine_cs *engine;
2155         enum intel_engine_id id;
2156         int i;
2157
2158         if (!ppgtt)
2159                 return;
2160
2161         for_each_engine(engine, dev_priv, id) {
2162                 seq_printf(m, "%s\n", engine->name);
2163                 for (i = 0; i < 4; i++) {
2164                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2165                         pdp <<= 32;
2166                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2167                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2168                 }
2169         }
2170 }
2171
2172 static void gen6_ppgtt_info(struct seq_file *m,
2173                             struct drm_i915_private *dev_priv)
2174 {
2175         struct intel_engine_cs *engine;
2176         enum intel_engine_id id;
2177
2178         if (IS_GEN6(dev_priv))
2179                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2180
2181         for_each_engine(engine, dev_priv, id) {
2182                 seq_printf(m, "%s\n", engine->name);
2183                 if (IS_GEN7(dev_priv))
2184                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2185                                    I915_READ(RING_MODE_GEN7(engine)));
2186                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2187                            I915_READ(RING_PP_DIR_BASE(engine)));
2188                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2189                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2190                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2191                            I915_READ(RING_PP_DIR_DCLV(engine)));
2192         }
2193         if (dev_priv->mm.aliasing_ppgtt) {
2194                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2195
2196                 seq_puts(m, "aliasing PPGTT:\n");
2197                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2198
2199                 ppgtt->debug_dump(ppgtt, m);
2200         }
2201
2202         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2203 }
2204
2205 static int i915_ppgtt_info(struct seq_file *m, void *data)
2206 {
2207         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2208         struct drm_device *dev = &dev_priv->drm;
2209         struct drm_file *file;
2210         int ret;
2211
2212         mutex_lock(&dev->filelist_mutex);
2213         ret = mutex_lock_interruptible(&dev->struct_mutex);
2214         if (ret)
2215                 goto out_unlock;
2216
2217         intel_runtime_pm_get(dev_priv);
2218
2219         if (INTEL_GEN(dev_priv) >= 8)
2220                 gen8_ppgtt_info(m, dev_priv);
2221         else if (INTEL_GEN(dev_priv) >= 6)
2222                 gen6_ppgtt_info(m, dev_priv);
2223
2224         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2225                 struct drm_i915_file_private *file_priv = file->driver_priv;
2226                 struct task_struct *task;
2227
2228                 task = get_pid_task(file->pid, PIDTYPE_PID);
2229                 if (!task) {
2230                         ret = -ESRCH;
2231                         goto out_rpm;
2232                 }
2233                 seq_printf(m, "\nproc: %s\n", task->comm);
2234                 put_task_struct(task);
2235                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2236                              (void *)(unsigned long)m);
2237         }
2238
2239 out_rpm:
2240         intel_runtime_pm_put(dev_priv);
2241         mutex_unlock(&dev->struct_mutex);
2242 out_unlock:
2243         mutex_unlock(&dev->filelist_mutex);
2244         return ret;
2245 }
2246
2247 static int count_irq_waiters(struct drm_i915_private *i915)
2248 {
2249         struct intel_engine_cs *engine;
2250         enum intel_engine_id id;
2251         int count = 0;
2252
2253         for_each_engine(engine, i915, id)
2254                 count += intel_engine_has_waiter(engine);
2255
2256         return count;
2257 }
2258
2259 static const char *rps_power_to_str(unsigned int power)
2260 {
2261         static const char * const strings[] = {
2262                 [LOW_POWER] = "low power",
2263                 [BETWEEN] = "mixed",
2264                 [HIGH_POWER] = "high power",
2265         };
2266
2267         if (power >= ARRAY_SIZE(strings) || !strings[power])
2268                 return "unknown";
2269
2270         return strings[power];
2271 }
2272
2273 static int i915_rps_boost_info(struct seq_file *m, void *data)
2274 {
2275         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2276         struct drm_device *dev = &dev_priv->drm;
2277         struct drm_file *file;
2278
2279         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2280         seq_printf(m, "GPU busy? %s [%d requests]\n",
2281                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2282         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2283         seq_printf(m, "Frequency requested %d\n",
2284                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2285         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2286                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2287                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2288                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2289                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2290         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2291                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2292                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2293                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2294
2295         mutex_lock(&dev->filelist_mutex);
2296         spin_lock(&dev_priv->rps.client_lock);
2297         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2298                 struct drm_i915_file_private *file_priv = file->driver_priv;
2299                 struct task_struct *task;
2300
2301                 rcu_read_lock();
2302                 task = pid_task(file->pid, PIDTYPE_PID);
2303                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2304                            task ? task->comm : "<unknown>",
2305                            task ? task->pid : -1,
2306                            file_priv->rps.boosts,
2307                            list_empty(&file_priv->rps.link) ? "" : ", active");
2308                 rcu_read_unlock();
2309         }
2310         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2311         spin_unlock(&dev_priv->rps.client_lock);
2312         mutex_unlock(&dev->filelist_mutex);
2313
2314         if (INTEL_GEN(dev_priv) >= 6 &&
2315             dev_priv->rps.enabled &&
2316             dev_priv->gt.active_requests) {
2317                 u32 rpup, rpupei;
2318                 u32 rpdown, rpdownei;
2319
2320                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2321                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2322                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2323                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2324                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2325                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2326
2327                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2328                            rps_power_to_str(dev_priv->rps.power));
2329                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2330                            100 * rpup / rpupei,
2331                            dev_priv->rps.up_threshold);
2332                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2333                            100 * rpdown / rpdownei,
2334                            dev_priv->rps.down_threshold);
2335         } else {
2336                 seq_puts(m, "\nRPS Autotuning inactive\n");
2337         }
2338
2339         return 0;
2340 }
2341
2342 static int i915_llc(struct seq_file *m, void *data)
2343 {
2344         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2345         const bool edram = INTEL_GEN(dev_priv) > 8;
2346
2347         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2348         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2349                    intel_uncore_edram_size(dev_priv)/1024/1024);
2350
2351         return 0;
2352 }
2353
2354 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2355 {
2356         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2357         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2358         u32 tmp, i;
2359
2360         if (!HAS_GUC_UCODE(dev_priv))
2361                 return 0;
2362
2363         seq_printf(m, "GuC firmware status:\n");
2364         seq_printf(m, "\tpath: %s\n",
2365                 guc_fw->guc_fw_path);
2366         seq_printf(m, "\tfetch: %s\n",
2367                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2368         seq_printf(m, "\tload: %s\n",
2369                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2370         seq_printf(m, "\tversion wanted: %d.%d\n",
2371                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2372         seq_printf(m, "\tversion found: %d.%d\n",
2373                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2374         seq_printf(m, "\theader: offset is %d; size = %d\n",
2375                 guc_fw->header_offset, guc_fw->header_size);
2376         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2377                 guc_fw->ucode_offset, guc_fw->ucode_size);
2378         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2379                 guc_fw->rsa_offset, guc_fw->rsa_size);
2380
2381         tmp = I915_READ(GUC_STATUS);
2382
2383         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2384         seq_printf(m, "\tBootrom status = 0x%x\n",
2385                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2386         seq_printf(m, "\tuKernel status = 0x%x\n",
2387                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2388         seq_printf(m, "\tMIA Core status = 0x%x\n",
2389                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2390         seq_puts(m, "\nScratch registers:\n");
2391         for (i = 0; i < 16; i++)
2392                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2393
2394         return 0;
2395 }
2396
2397 static void i915_guc_log_info(struct seq_file *m,
2398                               struct drm_i915_private *dev_priv)
2399 {
2400         struct intel_guc *guc = &dev_priv->guc;
2401
2402         seq_puts(m, "\nGuC logging stats:\n");
2403
2404         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2405                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2406                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2407
2408         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2409                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2410                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2411
2412         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2413                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2414                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2415
2416         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2417                    guc->log.flush_interrupt_count);
2418
2419         seq_printf(m, "\tCapture miss count: %u\n",
2420                    guc->log.capture_miss_count);
2421 }
2422
2423 static void i915_guc_client_info(struct seq_file *m,
2424                                  struct drm_i915_private *dev_priv,
2425                                  struct i915_guc_client *client)
2426 {
2427         struct intel_engine_cs *engine;
2428         enum intel_engine_id id;
2429         uint64_t tot = 0;
2430
2431         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2432                 client->priority, client->ctx_index, client->proc_desc_offset);
2433         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2434                 client->doorbell_id, client->doorbell_offset, client->cookie);
2435         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2436                 client->wq_size, client->wq_offset, client->wq_tail);
2437
2438         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2439         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2440         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2441
2442         for_each_engine(engine, dev_priv, id) {
2443                 u64 submissions = client->submissions[id];
2444                 tot += submissions;
2445                 seq_printf(m, "\tSubmissions: %llu %s\n",
2446                                 submissions, engine->name);
2447         }
2448         seq_printf(m, "\tTotal: %llu\n", tot);
2449 }
2450
2451 static int i915_guc_info(struct seq_file *m, void *data)
2452 {
2453         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2454         struct drm_device *dev = &dev_priv->drm;
2455         struct intel_guc guc;
2456         struct i915_guc_client client = {};
2457         struct intel_engine_cs *engine;
2458         enum intel_engine_id id;
2459         u64 total = 0;
2460
2461         if (!HAS_GUC_SCHED(dev_priv))
2462                 return 0;
2463
2464         if (mutex_lock_interruptible(&dev->struct_mutex))
2465                 return 0;
2466
2467         /* Take a local copy of the GuC data, so we can dump it at leisure */
2468         guc = dev_priv->guc;
2469         if (guc.execbuf_client)
2470                 client = *guc.execbuf_client;
2471
2472         mutex_unlock(&dev->struct_mutex);
2473
2474         seq_printf(m, "Doorbell map:\n");
2475         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2476         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2477
2478         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2479         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2480         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2481         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2482         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2483
2484         seq_printf(m, "\nGuC submissions:\n");
2485         for_each_engine(engine, dev_priv, id) {
2486                 u64 submissions = guc.submissions[id];
2487                 total += submissions;
2488                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2489                         engine->name, submissions, guc.last_seqno[id]);
2490         }
2491         seq_printf(m, "\t%s: %llu\n", "Total", total);
2492
2493         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2494         i915_guc_client_info(m, dev_priv, &client);
2495
2496         i915_guc_log_info(m, dev_priv);
2497
2498         /* Add more as required ... */
2499
2500         return 0;
2501 }
2502
2503 static int i915_guc_log_dump(struct seq_file *m, void *data)
2504 {
2505         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2506         struct drm_i915_gem_object *obj;
2507         int i = 0, pg;
2508
2509         if (!dev_priv->guc.log.vma)
2510                 return 0;
2511
2512         obj = dev_priv->guc.log.vma->obj;
2513         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2514                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2515
2516                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2517                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2518                                    *(log + i), *(log + i + 1),
2519                                    *(log + i + 2), *(log + i + 3));
2520
2521                 kunmap_atomic(log);
2522         }
2523
2524         seq_putc(m, '\n');
2525
2526         return 0;
2527 }
2528
2529 static int i915_guc_log_control_get(void *data, u64 *val)
2530 {
2531         struct drm_device *dev = data;
2532         struct drm_i915_private *dev_priv = to_i915(dev);
2533
2534         if (!dev_priv->guc.log.vma)
2535                 return -EINVAL;
2536
2537         *val = i915.guc_log_level;
2538
2539         return 0;
2540 }
2541
2542 static int i915_guc_log_control_set(void *data, u64 val)
2543 {
2544         struct drm_device *dev = data;
2545         struct drm_i915_private *dev_priv = to_i915(dev);
2546         int ret;
2547
2548         if (!dev_priv->guc.log.vma)
2549                 return -EINVAL;
2550
2551         ret = mutex_lock_interruptible(&dev->struct_mutex);
2552         if (ret)
2553                 return ret;
2554
2555         intel_runtime_pm_get(dev_priv);
2556         ret = i915_guc_log_control(dev_priv, val);
2557         intel_runtime_pm_put(dev_priv);
2558
2559         mutex_unlock(&dev->struct_mutex);
2560         return ret;
2561 }
2562
2563 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2564                         i915_guc_log_control_get, i915_guc_log_control_set,
2565                         "%lld\n");
2566
2567 static int i915_edp_psr_status(struct seq_file *m, void *data)
2568 {
2569         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2570         u32 psrperf = 0;
2571         u32 stat[3];
2572         enum pipe pipe;
2573         bool enabled = false;
2574
2575         if (!HAS_PSR(dev_priv)) {
2576                 seq_puts(m, "PSR not supported\n");
2577                 return 0;
2578         }
2579
2580         intel_runtime_pm_get(dev_priv);
2581
2582         mutex_lock(&dev_priv->psr.lock);
2583         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2584         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2585         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2586         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2587         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2588                    dev_priv->psr.busy_frontbuffer_bits);
2589         seq_printf(m, "Re-enable work scheduled: %s\n",
2590                    yesno(work_busy(&dev_priv->psr.work.work)));
2591
2592         if (HAS_DDI(dev_priv))
2593                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2594         else {
2595                 for_each_pipe(dev_priv, pipe) {
2596                         enum transcoder cpu_transcoder =
2597                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2598                         enum intel_display_power_domain power_domain;
2599
2600                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2601                         if (!intel_display_power_get_if_enabled(dev_priv,
2602                                                                 power_domain))
2603                                 continue;
2604
2605                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2606                                 VLV_EDP_PSR_CURR_STATE_MASK;
2607                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2608                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2609                                 enabled = true;
2610
2611                         intel_display_power_put(dev_priv, power_domain);
2612                 }
2613         }
2614
2615         seq_printf(m, "Main link in standby mode: %s\n",
2616                    yesno(dev_priv->psr.link_standby));
2617
2618         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2619
2620         if (!HAS_DDI(dev_priv))
2621                 for_each_pipe(dev_priv, pipe) {
2622                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2623                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2624                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2625                 }
2626         seq_puts(m, "\n");
2627
2628         /*
2629          * VLV/CHV PSR has no kind of performance counter
2630          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2631          */
2632         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2633                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2634                         EDP_PSR_PERF_CNT_MASK;
2635
2636                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2637         }
2638         mutex_unlock(&dev_priv->psr.lock);
2639
2640         intel_runtime_pm_put(dev_priv);
2641         return 0;
2642 }
2643
2644 static int i915_sink_crc(struct seq_file *m, void *data)
2645 {
2646         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2647         struct drm_device *dev = &dev_priv->drm;
2648         struct intel_connector *connector;
2649         struct intel_dp *intel_dp = NULL;
2650         int ret;
2651         u8 crc[6];
2652
2653         drm_modeset_lock_all(dev);
2654         for_each_intel_connector(dev, connector) {
2655                 struct drm_crtc *crtc;
2656
2657                 if (!connector->base.state->best_encoder)
2658                         continue;
2659
2660                 crtc = connector->base.state->crtc;
2661                 if (!crtc->state->active)
2662                         continue;
2663
2664                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2665                         continue;
2666
2667                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2668
2669                 ret = intel_dp_sink_crc(intel_dp, crc);
2670                 if (ret)
2671                         goto out;
2672
2673                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2674                            crc[0], crc[1], crc[2],
2675                            crc[3], crc[4], crc[5]);
2676                 goto out;
2677         }
2678         ret = -ENODEV;
2679 out:
2680         drm_modeset_unlock_all(dev);
2681         return ret;
2682 }
2683
2684 static int i915_energy_uJ(struct seq_file *m, void *data)
2685 {
2686         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2687         u64 power;
2688         u32 units;
2689
2690         if (INTEL_GEN(dev_priv) < 6)
2691                 return -ENODEV;
2692
2693         intel_runtime_pm_get(dev_priv);
2694
2695         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2696         power = (power & 0x1f00) >> 8;
2697         units = 1000000 / (1 << power); /* convert to uJ */
2698         power = I915_READ(MCH_SECP_NRG_STTS);
2699         power *= units;
2700
2701         intel_runtime_pm_put(dev_priv);
2702
2703         seq_printf(m, "%llu", (long long unsigned)power);
2704
2705         return 0;
2706 }
2707
2708 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2709 {
2710         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2711         struct pci_dev *pdev = dev_priv->drm.pdev;
2712
2713         if (!HAS_RUNTIME_PM(dev_priv))
2714                 seq_puts(m, "Runtime power management not supported\n");
2715
2716         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2717         seq_printf(m, "IRQs disabled: %s\n",
2718                    yesno(!intel_irqs_enabled(dev_priv)));
2719 #ifdef CONFIG_PM
2720         seq_printf(m, "Usage count: %d\n",
2721                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2722 #else
2723         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2724 #endif
2725         seq_printf(m, "PCI device power state: %s [%d]\n",
2726                    pci_power_name(pdev->current_state),
2727                    pdev->current_state);
2728
2729         return 0;
2730 }
2731
2732 static int i915_power_domain_info(struct seq_file *m, void *unused)
2733 {
2734         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2735         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2736         int i;
2737
2738         mutex_lock(&power_domains->lock);
2739
2740         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2741         for (i = 0; i < power_domains->power_well_count; i++) {
2742                 struct i915_power_well *power_well;
2743                 enum intel_display_power_domain power_domain;
2744
2745                 power_well = &power_domains->power_wells[i];
2746                 seq_printf(m, "%-25s %d\n", power_well->name,
2747                            power_well->count);
2748
2749                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2750                      power_domain++) {
2751                         if (!(BIT(power_domain) & power_well->domains))
2752                                 continue;
2753
2754                         seq_printf(m, "  %-23s %d\n",
2755                                  intel_display_power_domain_str(power_domain),
2756                                  power_domains->domain_use_count[power_domain]);
2757                 }
2758         }
2759
2760         mutex_unlock(&power_domains->lock);
2761
2762         return 0;
2763 }
2764
2765 static int i915_dmc_info(struct seq_file *m, void *unused)
2766 {
2767         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2768         struct intel_csr *csr;
2769
2770         if (!HAS_CSR(dev_priv)) {
2771                 seq_puts(m, "not supported\n");
2772                 return 0;
2773         }
2774
2775         csr = &dev_priv->csr;
2776
2777         intel_runtime_pm_get(dev_priv);
2778
2779         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2780         seq_printf(m, "path: %s\n", csr->fw_path);
2781
2782         if (!csr->dmc_payload)
2783                 goto out;
2784
2785         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2786                    CSR_VERSION_MINOR(csr->version));
2787
2788         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2789                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2790                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2791                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2792                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2793         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2794                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2795                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2796         }
2797
2798 out:
2799         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2800         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2801         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2802
2803         intel_runtime_pm_put(dev_priv);
2804
2805         return 0;
2806 }
2807
2808 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2809                                  struct drm_display_mode *mode)
2810 {
2811         int i;
2812
2813         for (i = 0; i < tabs; i++)
2814                 seq_putc(m, '\t');
2815
2816         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2817                    mode->base.id, mode->name,
2818                    mode->vrefresh, mode->clock,
2819                    mode->hdisplay, mode->hsync_start,
2820                    mode->hsync_end, mode->htotal,
2821                    mode->vdisplay, mode->vsync_start,
2822                    mode->vsync_end, mode->vtotal,
2823                    mode->type, mode->flags);
2824 }
2825
2826 static void intel_encoder_info(struct seq_file *m,
2827                                struct intel_crtc *intel_crtc,
2828                                struct intel_encoder *intel_encoder)
2829 {
2830         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2831         struct drm_device *dev = &dev_priv->drm;
2832         struct drm_crtc *crtc = &intel_crtc->base;
2833         struct intel_connector *intel_connector;
2834         struct drm_encoder *encoder;
2835
2836         encoder = &intel_encoder->base;
2837         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2838                    encoder->base.id, encoder->name);
2839         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2840                 struct drm_connector *connector = &intel_connector->base;
2841                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2842                            connector->base.id,
2843                            connector->name,
2844                            drm_get_connector_status_name(connector->status));
2845                 if (connector->status == connector_status_connected) {
2846                         struct drm_display_mode *mode = &crtc->mode;
2847                         seq_printf(m, ", mode:\n");
2848                         intel_seq_print_mode(m, 2, mode);
2849                 } else {
2850                         seq_putc(m, '\n');
2851                 }
2852         }
2853 }
2854
2855 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2856 {
2857         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2858         struct drm_device *dev = &dev_priv->drm;
2859         struct drm_crtc *crtc = &intel_crtc->base;
2860         struct intel_encoder *intel_encoder;
2861         struct drm_plane_state *plane_state = crtc->primary->state;
2862         struct drm_framebuffer *fb = plane_state->fb;
2863
2864         if (fb)
2865                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2866                            fb->base.id, plane_state->src_x >> 16,
2867                            plane_state->src_y >> 16, fb->width, fb->height);
2868         else
2869                 seq_puts(m, "\tprimary plane disabled\n");
2870         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2871                 intel_encoder_info(m, intel_crtc, intel_encoder);
2872 }
2873
2874 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2875 {
2876         struct drm_display_mode *mode = panel->fixed_mode;
2877
2878         seq_printf(m, "\tfixed mode:\n");
2879         intel_seq_print_mode(m, 2, mode);
2880 }
2881
2882 static void intel_dp_info(struct seq_file *m,
2883                           struct intel_connector *intel_connector)
2884 {
2885         struct intel_encoder *intel_encoder = intel_connector->encoder;
2886         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2887
2888         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2889         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2890         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2891                 intel_panel_info(m, &intel_connector->panel);
2892
2893         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2894                                 &intel_dp->aux);
2895 }
2896
2897 static void intel_hdmi_info(struct seq_file *m,
2898                             struct intel_connector *intel_connector)
2899 {
2900         struct intel_encoder *intel_encoder = intel_connector->encoder;
2901         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2902
2903         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2904 }
2905
2906 static void intel_lvds_info(struct seq_file *m,
2907                             struct intel_connector *intel_connector)
2908 {
2909         intel_panel_info(m, &intel_connector->panel);
2910 }
2911
2912 static void intel_connector_info(struct seq_file *m,
2913                                  struct drm_connector *connector)
2914 {
2915         struct intel_connector *intel_connector = to_intel_connector(connector);
2916         struct intel_encoder *intel_encoder = intel_connector->encoder;
2917         struct drm_display_mode *mode;
2918
2919         seq_printf(m, "connector %d: type %s, status: %s\n",
2920                    connector->base.id, connector->name,
2921                    drm_get_connector_status_name(connector->status));
2922         if (connector->status == connector_status_connected) {
2923                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2924                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2925                            connector->display_info.width_mm,
2926                            connector->display_info.height_mm);
2927                 seq_printf(m, "\tsubpixel order: %s\n",
2928                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2929                 seq_printf(m, "\tCEA rev: %d\n",
2930                            connector->display_info.cea_rev);
2931         }
2932
2933         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2934                 return;
2935
2936         switch (connector->connector_type) {
2937         case DRM_MODE_CONNECTOR_DisplayPort:
2938         case DRM_MODE_CONNECTOR_eDP:
2939                 intel_dp_info(m, intel_connector);
2940                 break;
2941         case DRM_MODE_CONNECTOR_LVDS:
2942                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2943                         intel_lvds_info(m, intel_connector);
2944                 break;
2945         case DRM_MODE_CONNECTOR_HDMIA:
2946                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2947                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2948                         intel_hdmi_info(m, intel_connector);
2949                 break;
2950         default:
2951                 break;
2952         }
2953
2954         seq_printf(m, "\tmodes:\n");
2955         list_for_each_entry(mode, &connector->modes, head)
2956                 intel_seq_print_mode(m, 2, mode);
2957 }
2958
2959 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2960 {
2961         u32 state;
2962
2963         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2964                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2965         else
2966                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2967
2968         return state;
2969 }
2970
2971 static bool cursor_position(struct drm_i915_private *dev_priv,
2972                             int pipe, int *x, int *y)
2973 {
2974         u32 pos;
2975
2976         pos = I915_READ(CURPOS(pipe));
2977
2978         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2979         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2980                 *x = -*x;
2981
2982         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2983         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2984                 *y = -*y;
2985
2986         return cursor_active(dev_priv, pipe);
2987 }
2988
2989 static const char *plane_type(enum drm_plane_type type)
2990 {
2991         switch (type) {
2992         case DRM_PLANE_TYPE_OVERLAY:
2993                 return "OVL";
2994         case DRM_PLANE_TYPE_PRIMARY:
2995                 return "PRI";
2996         case DRM_PLANE_TYPE_CURSOR:
2997                 return "CUR";
2998         /*
2999          * Deliberately omitting default: to generate compiler warnings
3000          * when a new drm_plane_type gets added.
3001          */
3002         }
3003
3004         return "unknown";
3005 }
3006
3007 static const char *plane_rotation(unsigned int rotation)
3008 {
3009         static char buf[48];
3010         /*
3011          * According to doc only one DRM_ROTATE_ is allowed but this
3012          * will print them all to visualize if the values are misused
3013          */
3014         snprintf(buf, sizeof(buf),
3015                  "%s%s%s%s%s%s(0x%08x)",
3016                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3017                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3018                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3019                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3020                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3021                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3022                  rotation);
3023
3024         return buf;
3025 }
3026
3027 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3028 {
3029         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3030         struct drm_device *dev = &dev_priv->drm;
3031         struct intel_plane *intel_plane;
3032
3033         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3034                 struct drm_plane_state *state;
3035                 struct drm_plane *plane = &intel_plane->base;
3036                 char *format_name;
3037
3038                 if (!plane->state) {
3039                         seq_puts(m, "plane->state is NULL!\n");
3040                         continue;
3041                 }
3042
3043                 state = plane->state;
3044
3045                 if (state->fb) {
3046                         format_name = drm_get_format_name(state->fb->pixel_format);
3047                 } else {
3048                         format_name = kstrdup("N/A", GFP_KERNEL);
3049                 }
3050
3051                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3052                            plane->base.id,
3053                            plane_type(intel_plane->base.type),
3054                            state->crtc_x, state->crtc_y,
3055                            state->crtc_w, state->crtc_h,
3056                            (state->src_x >> 16),
3057                            ((state->src_x & 0xffff) * 15625) >> 10,
3058                            (state->src_y >> 16),
3059                            ((state->src_y & 0xffff) * 15625) >> 10,
3060                            (state->src_w >> 16),
3061                            ((state->src_w & 0xffff) * 15625) >> 10,
3062                            (state->src_h >> 16),
3063                            ((state->src_h & 0xffff) * 15625) >> 10,
3064                            format_name,
3065                            plane_rotation(state->rotation));
3066
3067                 kfree(format_name);
3068         }
3069 }
3070
3071 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3072 {
3073         struct intel_crtc_state *pipe_config;
3074         int num_scalers = intel_crtc->num_scalers;
3075         int i;
3076
3077         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3078
3079         /* Not all platformas have a scaler */
3080         if (num_scalers) {
3081                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3082                            num_scalers,
3083                            pipe_config->scaler_state.scaler_users,
3084                            pipe_config->scaler_state.scaler_id);
3085
3086                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3087                         struct intel_scaler *sc =
3088                                         &pipe_config->scaler_state.scalers[i];
3089
3090                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3091                                    i, yesno(sc->in_use), sc->mode);
3092                 }
3093                 seq_puts(m, "\n");
3094         } else {
3095                 seq_puts(m, "\tNo scalers available on this platform\n");
3096         }
3097 }
3098
3099 static int i915_display_info(struct seq_file *m, void *unused)
3100 {
3101         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3102         struct drm_device *dev = &dev_priv->drm;
3103         struct intel_crtc *crtc;
3104         struct drm_connector *connector;
3105
3106         intel_runtime_pm_get(dev_priv);
3107         drm_modeset_lock_all(dev);
3108         seq_printf(m, "CRTC info\n");
3109         seq_printf(m, "---------\n");
3110         for_each_intel_crtc(dev, crtc) {
3111                 bool active;
3112                 struct intel_crtc_state *pipe_config;
3113                 int x, y;
3114
3115                 pipe_config = to_intel_crtc_state(crtc->base.state);
3116
3117                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3118                            crtc->base.base.id, pipe_name(crtc->pipe),
3119                            yesno(pipe_config->base.active),
3120                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3121                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3122
3123                 if (pipe_config->base.active) {
3124                         intel_crtc_info(m, crtc);
3125
3126                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3127                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3128                                    yesno(crtc->cursor_base),
3129                                    x, y, crtc->base.cursor->state->crtc_w,
3130                                    crtc->base.cursor->state->crtc_h,
3131                                    crtc->cursor_addr, yesno(active));
3132                         intel_scaler_info(m, crtc);
3133                         intel_plane_info(m, crtc);
3134                 }
3135
3136                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3137                            yesno(!crtc->cpu_fifo_underrun_disabled),
3138                            yesno(!crtc->pch_fifo_underrun_disabled));
3139         }
3140
3141         seq_printf(m, "\n");
3142         seq_printf(m, "Connector info\n");
3143         seq_printf(m, "--------------\n");
3144         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3145                 intel_connector_info(m, connector);
3146         }
3147         drm_modeset_unlock_all(dev);
3148         intel_runtime_pm_put(dev_priv);
3149
3150         return 0;
3151 }
3152
3153 static int i915_engine_info(struct seq_file *m, void *unused)
3154 {
3155         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3156         struct intel_engine_cs *engine;
3157         enum intel_engine_id id;
3158
3159         intel_runtime_pm_get(dev_priv);
3160
3161         for_each_engine(engine, dev_priv, id) {
3162                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3163                 struct drm_i915_gem_request *rq;
3164                 struct rb_node *rb;
3165                 u64 addr;
3166
3167                 seq_printf(m, "%s\n", engine->name);
3168                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3169                            intel_engine_get_seqno(engine),
3170                            intel_engine_last_submit(engine),
3171                            engine->hangcheck.seqno,
3172                            engine->hangcheck.score);
3173
3174                 rcu_read_lock();
3175
3176                 seq_printf(m, "\tRequests:\n");
3177
3178                 rq = list_first_entry(&engine->timeline->requests,
3179                                       struct drm_i915_gem_request, link);
3180                 if (&rq->link != &engine->timeline->requests)
3181                         print_request(m, rq, "\t\tfirst  ");
3182
3183                 rq = list_last_entry(&engine->timeline->requests,
3184                                      struct drm_i915_gem_request, link);
3185                 if (&rq->link != &engine->timeline->requests)
3186                         print_request(m, rq, "\t\tlast   ");
3187
3188                 rq = i915_gem_find_active_request(engine);
3189                 if (rq) {
3190                         print_request(m, rq, "\t\tactive ");
3191                         seq_printf(m,
3192                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3193                                    rq->head, rq->postfix, rq->tail,
3194                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3195                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3196                 }
3197
3198                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3199                            I915_READ(RING_START(engine->mmio_base)),
3200                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3201                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3202                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3203                            rq ? rq->ring->head : 0);
3204                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3205                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3206                            rq ? rq->ring->tail : 0);
3207                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3208                            I915_READ(RING_CTL(engine->mmio_base)),
3209                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3210
3211                 rcu_read_unlock();
3212
3213                 addr = intel_engine_get_active_head(engine);
3214                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3215                            upper_32_bits(addr), lower_32_bits(addr));
3216                 addr = intel_engine_get_last_batch_head(engine);
3217                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3218                            upper_32_bits(addr), lower_32_bits(addr));
3219
3220                 if (i915.enable_execlists) {
3221                         u32 ptr, read, write;
3222                         struct rb_node *rb;
3223
3224                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3225                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3226                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3227
3228                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3229                         read = GEN8_CSB_READ_PTR(ptr);
3230                         write = GEN8_CSB_WRITE_PTR(ptr);
3231                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3232                                    read, write);
3233                         if (read >= GEN8_CSB_ENTRIES)
3234                                 read = 0;
3235                         if (write >= GEN8_CSB_ENTRIES)
3236                                 write = 0;
3237                         if (read > write)
3238                                 write += GEN8_CSB_ENTRIES;
3239                         while (read < write) {
3240                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3241
3242                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3243                                            idx,
3244                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3245                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3246                         }
3247
3248                         rcu_read_lock();
3249                         rq = READ_ONCE(engine->execlist_port[0].request);
3250                         if (rq)
3251                                 print_request(m, rq, "\t\tELSP[0] ");
3252                         else
3253                                 seq_printf(m, "\t\tELSP[0] idle\n");
3254                         rq = READ_ONCE(engine->execlist_port[1].request);
3255                         if (rq)
3256                                 print_request(m, rq, "\t\tELSP[1] ");
3257                         else
3258                                 seq_printf(m, "\t\tELSP[1] idle\n");
3259                         rcu_read_unlock();
3260
3261                         spin_lock_irq(&engine->timeline->lock);
3262                         for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
3263                                 rq = rb_entry(rb, typeof(*rq), priotree.node);
3264                                 print_request(m, rq, "\t\tQ ");
3265                         }
3266                         spin_unlock_irq(&engine->timeline->lock);
3267                 } else if (INTEL_GEN(dev_priv) > 6) {
3268                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3269                                    I915_READ(RING_PP_DIR_BASE(engine)));
3270                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3271                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3272                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3273                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3274                 }
3275
3276                 spin_lock_irq(&b->lock);
3277                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3278                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3279
3280                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3281                                    w->tsk->comm, w->tsk->pid, w->seqno);
3282                 }
3283                 spin_unlock_irq(&b->lock);
3284
3285                 seq_puts(m, "\n");
3286         }
3287
3288         intel_runtime_pm_put(dev_priv);
3289
3290         return 0;
3291 }
3292
3293 static int i915_semaphore_status(struct seq_file *m, void *unused)
3294 {
3295         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3296         struct drm_device *dev = &dev_priv->drm;
3297         struct intel_engine_cs *engine;
3298         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3299         enum intel_engine_id id;
3300         int j, ret;
3301
3302         if (!i915.semaphores) {
3303                 seq_puts(m, "Semaphores are disabled\n");
3304                 return 0;
3305         }
3306
3307         ret = mutex_lock_interruptible(&dev->struct_mutex);
3308         if (ret)
3309                 return ret;
3310         intel_runtime_pm_get(dev_priv);
3311
3312         if (IS_BROADWELL(dev_priv)) {
3313                 struct page *page;
3314                 uint64_t *seqno;
3315
3316                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3317
3318                 seqno = (uint64_t *)kmap_atomic(page);
3319                 for_each_engine(engine, dev_priv, id) {
3320                         uint64_t offset;
3321
3322                         seq_printf(m, "%s\n", engine->name);
3323
3324                         seq_puts(m, "  Last signal:");
3325                         for (j = 0; j < num_rings; j++) {
3326                                 offset = id * I915_NUM_ENGINES + j;
3327                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3328                                            seqno[offset], offset * 8);
3329                         }
3330                         seq_putc(m, '\n');
3331
3332                         seq_puts(m, "  Last wait:  ");
3333                         for (j = 0; j < num_rings; j++) {
3334                                 offset = id + (j * I915_NUM_ENGINES);
3335                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3336                                            seqno[offset], offset * 8);
3337                         }
3338                         seq_putc(m, '\n');
3339
3340                 }
3341                 kunmap_atomic(seqno);
3342         } else {
3343                 seq_puts(m, "  Last signal:");
3344                 for_each_engine(engine, dev_priv, id)
3345                         for (j = 0; j < num_rings; j++)
3346                                 seq_printf(m, "0x%08x\n",
3347                                            I915_READ(engine->semaphore.mbox.signal[j]));
3348                 seq_putc(m, '\n');
3349         }
3350
3351         intel_runtime_pm_put(dev_priv);
3352         mutex_unlock(&dev->struct_mutex);
3353         return 0;
3354 }
3355
3356 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3357 {
3358         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3359         struct drm_device *dev = &dev_priv->drm;
3360         int i;
3361
3362         drm_modeset_lock_all(dev);
3363         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3364                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3365
3366                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3367                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3368                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3369                 seq_printf(m, " tracked hardware state:\n");
3370                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3371                 seq_printf(m, " dpll_md: 0x%08x\n",
3372                            pll->config.hw_state.dpll_md);
3373                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3374                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3375                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3376         }
3377         drm_modeset_unlock_all(dev);
3378
3379         return 0;
3380 }
3381
3382 static int i915_wa_registers(struct seq_file *m, void *unused)
3383 {
3384         int i;
3385         int ret;
3386         struct intel_engine_cs *engine;
3387         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3388         struct drm_device *dev = &dev_priv->drm;
3389         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3390         enum intel_engine_id id;
3391
3392         ret = mutex_lock_interruptible(&dev->struct_mutex);
3393         if (ret)
3394                 return ret;
3395
3396         intel_runtime_pm_get(dev_priv);
3397
3398         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3399         for_each_engine(engine, dev_priv, id)
3400                 seq_printf(m, "HW whitelist count for %s: %d\n",
3401                            engine->name, workarounds->hw_whitelist_count[id]);
3402         for (i = 0; i < workarounds->count; ++i) {
3403                 i915_reg_t addr;
3404                 u32 mask, value, read;
3405                 bool ok;
3406
3407                 addr = workarounds->reg[i].addr;
3408                 mask = workarounds->reg[i].mask;
3409                 value = workarounds->reg[i].value;
3410                 read = I915_READ(addr);
3411                 ok = (value & mask) == (read & mask);
3412                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3413                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3414         }
3415
3416         intel_runtime_pm_put(dev_priv);
3417         mutex_unlock(&dev->struct_mutex);
3418
3419         return 0;
3420 }
3421
3422 static int i915_ddb_info(struct seq_file *m, void *unused)
3423 {
3424         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3425         struct drm_device *dev = &dev_priv->drm;
3426         struct skl_ddb_allocation *ddb;
3427         struct skl_ddb_entry *entry;
3428         enum pipe pipe;
3429         int plane;
3430
3431         if (INTEL_GEN(dev_priv) < 9)
3432                 return 0;
3433
3434         drm_modeset_lock_all(dev);
3435
3436         ddb = &dev_priv->wm.skl_hw.ddb;
3437
3438         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3439
3440         for_each_pipe(dev_priv, pipe) {
3441                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3442
3443                 for_each_universal_plane(dev_priv, pipe, plane) {
3444                         entry = &ddb->plane[pipe][plane];
3445                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3446                                    entry->start, entry->end,
3447                                    skl_ddb_entry_size(entry));
3448                 }
3449
3450                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3451                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3452                            entry->end, skl_ddb_entry_size(entry));
3453         }
3454
3455         drm_modeset_unlock_all(dev);
3456
3457         return 0;
3458 }
3459
3460 static void drrs_status_per_crtc(struct seq_file *m,
3461                                  struct drm_device *dev,
3462                                  struct intel_crtc *intel_crtc)
3463 {
3464         struct drm_i915_private *dev_priv = to_i915(dev);
3465         struct i915_drrs *drrs = &dev_priv->drrs;
3466         int vrefresh = 0;
3467         struct drm_connector *connector;
3468
3469         drm_for_each_connector(connector, dev) {
3470                 if (connector->state->crtc != &intel_crtc->base)
3471                         continue;
3472
3473                 seq_printf(m, "%s:\n", connector->name);
3474         }
3475
3476         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3477                 seq_puts(m, "\tVBT: DRRS_type: Static");
3478         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3479                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3480         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3481                 seq_puts(m, "\tVBT: DRRS_type: None");
3482         else
3483                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3484
3485         seq_puts(m, "\n\n");
3486
3487         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3488                 struct intel_panel *panel;
3489
3490                 mutex_lock(&drrs->mutex);
3491                 /* DRRS Supported */
3492                 seq_puts(m, "\tDRRS Supported: Yes\n");
3493
3494                 /* disable_drrs() will make drrs->dp NULL */
3495                 if (!drrs->dp) {
3496                         seq_puts(m, "Idleness DRRS: Disabled");
3497                         mutex_unlock(&drrs->mutex);
3498                         return;
3499                 }
3500
3501                 panel = &drrs->dp->attached_connector->panel;
3502                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3503                                         drrs->busy_frontbuffer_bits);
3504
3505                 seq_puts(m, "\n\t\t");
3506                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3507                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3508                         vrefresh = panel->fixed_mode->vrefresh;
3509                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3510                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3511                         vrefresh = panel->downclock_mode->vrefresh;
3512                 } else {
3513                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3514                                                 drrs->refresh_rate_type);
3515                         mutex_unlock(&drrs->mutex);
3516                         return;
3517                 }
3518                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3519
3520                 seq_puts(m, "\n\t\t");
3521                 mutex_unlock(&drrs->mutex);
3522         } else {
3523                 /* DRRS not supported. Print the VBT parameter*/
3524                 seq_puts(m, "\tDRRS Supported : No");
3525         }
3526         seq_puts(m, "\n");
3527 }
3528
3529 static int i915_drrs_status(struct seq_file *m, void *unused)
3530 {
3531         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3532         struct drm_device *dev = &dev_priv->drm;
3533         struct intel_crtc *intel_crtc;
3534         int active_crtc_cnt = 0;
3535
3536         drm_modeset_lock_all(dev);
3537         for_each_intel_crtc(dev, intel_crtc) {
3538                 if (intel_crtc->base.state->active) {
3539                         active_crtc_cnt++;
3540                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3541
3542                         drrs_status_per_crtc(m, dev, intel_crtc);
3543                 }
3544         }
3545         drm_modeset_unlock_all(dev);
3546
3547         if (!active_crtc_cnt)
3548                 seq_puts(m, "No active crtc found\n");
3549
3550         return 0;
3551 }
3552
3553 struct pipe_crc_info {
3554         const char *name;
3555         struct drm_i915_private *dev_priv;
3556         enum pipe pipe;
3557 };
3558
3559 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3560 {
3561         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3562         struct drm_device *dev = &dev_priv->drm;
3563         struct intel_encoder *intel_encoder;
3564         struct intel_digital_port *intel_dig_port;
3565         struct drm_connector *connector;
3566
3567         drm_modeset_lock_all(dev);
3568         drm_for_each_connector(connector, dev) {
3569                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3570                         continue;
3571
3572                 intel_encoder = intel_attached_encoder(connector);
3573                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3574                         continue;
3575
3576                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3577                 if (!intel_dig_port->dp.can_mst)
3578                         continue;
3579
3580                 seq_printf(m, "MST Source Port %c\n",
3581                            port_name(intel_dig_port->port));
3582                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3583         }
3584         drm_modeset_unlock_all(dev);
3585         return 0;
3586 }
3587
3588 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3589 {
3590         struct pipe_crc_info *info = inode->i_private;
3591         struct drm_i915_private *dev_priv = info->dev_priv;
3592         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3593
3594         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3595                 return -ENODEV;
3596
3597         spin_lock_irq(&pipe_crc->lock);
3598
3599         if (pipe_crc->opened) {
3600                 spin_unlock_irq(&pipe_crc->lock);
3601                 return -EBUSY; /* already open */
3602         }
3603
3604         pipe_crc->opened = true;
3605         filep->private_data = inode->i_private;
3606
3607         spin_unlock_irq(&pipe_crc->lock);
3608
3609         return 0;
3610 }
3611
3612 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3613 {
3614         struct pipe_crc_info *info = inode->i_private;
3615         struct drm_i915_private *dev_priv = info->dev_priv;
3616         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3617
3618         spin_lock_irq(&pipe_crc->lock);
3619         pipe_crc->opened = false;
3620         spin_unlock_irq(&pipe_crc->lock);
3621
3622         return 0;
3623 }
3624
3625 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3626 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3627 /* account for \'0' */
3628 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3629
3630 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3631 {
3632         assert_spin_locked(&pipe_crc->lock);
3633         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3634                         INTEL_PIPE_CRC_ENTRIES_NR);
3635 }
3636
3637 static ssize_t
3638 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3639                    loff_t *pos)
3640 {
3641         struct pipe_crc_info *info = filep->private_data;
3642         struct drm_i915_private *dev_priv = info->dev_priv;
3643         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3644         char buf[PIPE_CRC_BUFFER_LEN];
3645         int n_entries;
3646         ssize_t bytes_read;
3647
3648         /*
3649          * Don't allow user space to provide buffers not big enough to hold
3650          * a line of data.
3651          */
3652         if (count < PIPE_CRC_LINE_LEN)
3653                 return -EINVAL;
3654
3655         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3656                 return 0;
3657
3658         /* nothing to read */
3659         spin_lock_irq(&pipe_crc->lock);
3660         while (pipe_crc_data_count(pipe_crc) == 0) {
3661                 int ret;
3662
3663                 if (filep->f_flags & O_NONBLOCK) {
3664                         spin_unlock_irq(&pipe_crc->lock);
3665                         return -EAGAIN;
3666                 }
3667
3668                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3669                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3670                 if (ret) {
3671                         spin_unlock_irq(&pipe_crc->lock);
3672                         return ret;
3673                 }
3674         }
3675
3676         /* We now have one or more entries to read */
3677         n_entries = count / PIPE_CRC_LINE_LEN;
3678
3679         bytes_read = 0;
3680         while (n_entries > 0) {
3681                 struct intel_pipe_crc_entry *entry =
3682                         &pipe_crc->entries[pipe_crc->tail];
3683
3684                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3685                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3686                         break;
3687
3688                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3689                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3690
3691                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3692                                        "%8u %8x %8x %8x %8x %8x\n",
3693                                        entry->frame, entry->crc[0],
3694                                        entry->crc[1], entry->crc[2],
3695                                        entry->crc[3], entry->crc[4]);
3696
3697                 spin_unlock_irq(&pipe_crc->lock);
3698
3699                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3700                         return -EFAULT;
3701
3702                 user_buf += PIPE_CRC_LINE_LEN;
3703                 n_entries--;
3704
3705                 spin_lock_irq(&pipe_crc->lock);
3706         }
3707
3708         spin_unlock_irq(&pipe_crc->lock);
3709
3710         return bytes_read;
3711 }
3712
3713 static const struct file_operations i915_pipe_crc_fops = {
3714         .owner = THIS_MODULE,
3715         .open = i915_pipe_crc_open,
3716         .read = i915_pipe_crc_read,
3717         .release = i915_pipe_crc_release,
3718 };
3719
3720 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3721         {
3722                 .name = "i915_pipe_A_crc",
3723                 .pipe = PIPE_A,
3724         },
3725         {
3726                 .name = "i915_pipe_B_crc",
3727                 .pipe = PIPE_B,
3728         },
3729         {
3730                 .name = "i915_pipe_C_crc",
3731                 .pipe = PIPE_C,
3732         },
3733 };
3734
3735 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3736                                 enum pipe pipe)
3737 {
3738         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3739         struct dentry *ent;
3740         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3741
3742         info->dev_priv = dev_priv;
3743         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3744                                   &i915_pipe_crc_fops);
3745         if (!ent)
3746                 return -ENOMEM;
3747
3748         return drm_add_fake_info_node(minor, ent, info);
3749 }
3750
3751 static const char * const pipe_crc_sources[] = {
3752         "none",
3753         "plane1",
3754         "plane2",
3755         "pf",
3756         "pipe",
3757         "TV",
3758         "DP-B",
3759         "DP-C",
3760         "DP-D",
3761         "auto",
3762 };
3763
3764 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3765 {
3766         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3767         return pipe_crc_sources[source];
3768 }
3769
3770 static int display_crc_ctl_show(struct seq_file *m, void *data)
3771 {
3772         struct drm_i915_private *dev_priv = m->private;
3773         int i;
3774
3775         for (i = 0; i < I915_MAX_PIPES; i++)
3776                 seq_printf(m, "%c %s\n", pipe_name(i),
3777                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3778
3779         return 0;
3780 }
3781
3782 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3783 {
3784         return single_open(file, display_crc_ctl_show, inode->i_private);
3785 }
3786
3787 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3788                                  uint32_t *val)
3789 {
3790         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3791                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3792
3793         switch (*source) {
3794         case INTEL_PIPE_CRC_SOURCE_PIPE:
3795                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3796                 break;
3797         case INTEL_PIPE_CRC_SOURCE_NONE:
3798                 *val = 0;
3799                 break;
3800         default:
3801                 return -EINVAL;
3802         }
3803
3804         return 0;
3805 }
3806
3807 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3808                                      enum pipe pipe,
3809                                      enum intel_pipe_crc_source *source)
3810 {
3811         struct drm_device *dev = &dev_priv->drm;
3812         struct intel_encoder *encoder;
3813         struct intel_crtc *crtc;
3814         struct intel_digital_port *dig_port;
3815         int ret = 0;
3816
3817         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3818
3819         drm_modeset_lock_all(dev);
3820         for_each_intel_encoder(dev, encoder) {
3821                 if (!encoder->base.crtc)
3822                         continue;
3823
3824                 crtc = to_intel_crtc(encoder->base.crtc);
3825
3826                 if (crtc->pipe != pipe)
3827                         continue;
3828
3829                 switch (encoder->type) {
3830                 case INTEL_OUTPUT_TVOUT:
3831                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3832                         break;
3833                 case INTEL_OUTPUT_DP:
3834                 case INTEL_OUTPUT_EDP:
3835                         dig_port = enc_to_dig_port(&encoder->base);
3836                         switch (dig_port->port) {
3837                         case PORT_B:
3838                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3839                                 break;
3840                         case PORT_C:
3841                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3842                                 break;
3843                         case PORT_D:
3844                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3845                                 break;
3846                         default:
3847                                 WARN(1, "nonexisting DP port %c\n",
3848                                      port_name(dig_port->port));
3849                                 break;
3850                         }
3851                         break;
3852                 default:
3853                         break;
3854                 }
3855         }
3856         drm_modeset_unlock_all(dev);
3857
3858         return ret;
3859 }
3860
3861 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3862                                 enum pipe pipe,
3863                                 enum intel_pipe_crc_source *source,
3864                                 uint32_t *val)
3865 {
3866         bool need_stable_symbols = false;
3867
3868         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3869                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3870                 if (ret)
3871                         return ret;
3872         }
3873
3874         switch (*source) {
3875         case INTEL_PIPE_CRC_SOURCE_PIPE:
3876                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3877                 break;
3878         case INTEL_PIPE_CRC_SOURCE_DP_B:
3879                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3880                 need_stable_symbols = true;
3881                 break;
3882         case INTEL_PIPE_CRC_SOURCE_DP_C:
3883                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3884                 need_stable_symbols = true;
3885                 break;
3886         case INTEL_PIPE_CRC_SOURCE_DP_D:
3887                 if (!IS_CHERRYVIEW(dev_priv))
3888                         return -EINVAL;
3889                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3890                 need_stable_symbols = true;
3891                 break;
3892         case INTEL_PIPE_CRC_SOURCE_NONE:
3893                 *val = 0;
3894                 break;
3895         default:
3896                 return -EINVAL;
3897         }
3898
3899         /*
3900          * When the pipe CRC tap point is after the transcoders we need
3901          * to tweak symbol-level features to produce a deterministic series of
3902          * symbols for a given frame. We need to reset those features only once
3903          * a frame (instead of every nth symbol):
3904          *   - DC-balance: used to ensure a better clock recovery from the data
3905          *     link (SDVO)
3906          *   - DisplayPort scrambling: used for EMI reduction
3907          */
3908         if (need_stable_symbols) {
3909                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3910
3911                 tmp |= DC_BALANCE_RESET_VLV;
3912                 switch (pipe) {
3913                 case PIPE_A:
3914                         tmp |= PIPE_A_SCRAMBLE_RESET;
3915                         break;
3916                 case PIPE_B:
3917                         tmp |= PIPE_B_SCRAMBLE_RESET;
3918                         break;
3919                 case PIPE_C:
3920                         tmp |= PIPE_C_SCRAMBLE_RESET;
3921                         break;
3922                 default:
3923                         return -EINVAL;
3924                 }
3925                 I915_WRITE(PORT_DFT2_G4X, tmp);
3926         }
3927
3928         return 0;
3929 }
3930
3931 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3932                                  enum pipe pipe,
3933                                  enum intel_pipe_crc_source *source,
3934                                  uint32_t *val)
3935 {
3936         bool need_stable_symbols = false;
3937
3938         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3939                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3940                 if (ret)
3941                         return ret;
3942         }
3943
3944         switch (*source) {
3945         case INTEL_PIPE_CRC_SOURCE_PIPE:
3946                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3947                 break;
3948         case INTEL_PIPE_CRC_SOURCE_TV:
3949                 if (!SUPPORTS_TV(dev_priv))
3950                         return -EINVAL;
3951                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3952                 break;
3953         case INTEL_PIPE_CRC_SOURCE_DP_B:
3954                 if (!IS_G4X(dev_priv))
3955                         return -EINVAL;
3956                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3957                 need_stable_symbols = true;
3958                 break;
3959         case INTEL_PIPE_CRC_SOURCE_DP_C:
3960                 if (!IS_G4X(dev_priv))
3961                         return -EINVAL;
3962                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3963                 need_stable_symbols = true;
3964                 break;
3965         case INTEL_PIPE_CRC_SOURCE_DP_D:
3966                 if (!IS_G4X(dev_priv))
3967                         return -EINVAL;
3968                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3969                 need_stable_symbols = true;
3970                 break;
3971         case INTEL_PIPE_CRC_SOURCE_NONE:
3972                 *val = 0;
3973                 break;
3974         default:
3975                 return -EINVAL;
3976         }
3977
3978         /*
3979          * When the pipe CRC tap point is after the transcoders we need
3980          * to tweak symbol-level features to produce a deterministic series of
3981          * symbols for a given frame. We need to reset those features only once
3982          * a frame (instead of every nth symbol):
3983          *   - DC-balance: used to ensure a better clock recovery from the data
3984          *     link (SDVO)
3985          *   - DisplayPort scrambling: used for EMI reduction
3986          */
3987         if (need_stable_symbols) {
3988                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3989
3990                 WARN_ON(!IS_G4X(dev_priv));
3991
3992                 I915_WRITE(PORT_DFT_I9XX,
3993                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3994
3995                 if (pipe == PIPE_A)
3996                         tmp |= PIPE_A_SCRAMBLE_RESET;
3997                 else
3998                         tmp |= PIPE_B_SCRAMBLE_RESET;
3999
4000                 I915_WRITE(PORT_DFT2_G4X, tmp);
4001         }
4002
4003         return 0;
4004 }
4005
4006 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4007                                          enum pipe pipe)
4008 {
4009         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4010
4011         switch (pipe) {
4012         case PIPE_A:
4013                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4014                 break;
4015         case PIPE_B:
4016                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4017                 break;
4018         case PIPE_C:
4019                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
4020                 break;
4021         default:
4022                 return;
4023         }
4024         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
4025                 tmp &= ~DC_BALANCE_RESET_VLV;
4026         I915_WRITE(PORT_DFT2_G4X, tmp);
4027
4028 }
4029
4030 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4031                                          enum pipe pipe)
4032 {
4033         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4034
4035         if (pipe == PIPE_A)
4036                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4037         else
4038                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4039         I915_WRITE(PORT_DFT2_G4X, tmp);
4040
4041         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
4042                 I915_WRITE(PORT_DFT_I9XX,
4043                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
4044         }
4045 }
4046
4047 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4048                                 uint32_t *val)
4049 {
4050         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4051                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4052
4053         switch (*source) {
4054         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4055                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4056                 break;
4057         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4058                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4059                 break;
4060         case INTEL_PIPE_CRC_SOURCE_PIPE:
4061                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4062                 break;
4063         case INTEL_PIPE_CRC_SOURCE_NONE:
4064                 *val = 0;
4065                 break;
4066         default:
4067                 return -EINVAL;
4068         }
4069
4070         return 0;
4071 }
4072
4073 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4074                                         bool enable)
4075 {
4076         struct drm_device *dev = &dev_priv->drm;
4077         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
4078         struct intel_crtc_state *pipe_config;
4079         struct drm_atomic_state *state;
4080         int ret = 0;
4081
4082         drm_modeset_lock_all(dev);
4083         state = drm_atomic_state_alloc(dev);
4084         if (!state) {
4085                 ret = -ENOMEM;
4086                 goto out;
4087         }
4088
4089         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4090         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4091         if (IS_ERR(pipe_config)) {
4092                 ret = PTR_ERR(pipe_config);
4093                 goto out;
4094         }
4095
4096         pipe_config->pch_pfit.force_thru = enable;
4097         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4098             pipe_config->pch_pfit.enabled != enable)
4099                 pipe_config->base.connectors_changed = true;
4100
4101         ret = drm_atomic_commit(state);
4102 out:
4103         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4104         drm_modeset_unlock_all(dev);
4105         drm_atomic_state_put(state);
4106 }
4107
4108 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4109                                 enum pipe pipe,
4110                                 enum intel_pipe_crc_source *source,
4111                                 uint32_t *val)
4112 {
4113         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4114                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4115
4116         switch (*source) {
4117         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4118                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4119                 break;
4120         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4121                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4122                 break;
4123         case INTEL_PIPE_CRC_SOURCE_PF:
4124                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4125                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4126
4127                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4128                 break;
4129         case INTEL_PIPE_CRC_SOURCE_NONE:
4130                 *val = 0;
4131                 break;
4132         default:
4133                 return -EINVAL;
4134         }
4135
4136         return 0;
4137 }
4138
4139 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4140                                enum pipe pipe,
4141                                enum intel_pipe_crc_source source)
4142 {
4143         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4144         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
4145         enum intel_display_power_domain power_domain;
4146         u32 val = 0; /* shut up gcc */
4147         int ret;
4148
4149         if (pipe_crc->source == source)
4150                 return 0;
4151
4152         /* forbid changing the source without going back to 'none' */
4153         if (pipe_crc->source && source)
4154                 return -EINVAL;
4155
4156         power_domain = POWER_DOMAIN_PIPE(pipe);
4157         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4158                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4159                 return -EIO;
4160         }
4161
4162         if (IS_GEN2(dev_priv))
4163                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4164         else if (INTEL_GEN(dev_priv) < 5)
4165                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4166         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4167                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4168         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4169                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4170         else
4171                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4172
4173         if (ret != 0)
4174                 goto out;
4175
4176         /* none -> real source transition */
4177         if (source) {
4178                 struct intel_pipe_crc_entry *entries;
4179
4180                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4181                                  pipe_name(pipe), pipe_crc_source_name(source));
4182
4183                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4184                                   sizeof(pipe_crc->entries[0]),
4185                                   GFP_KERNEL);
4186                 if (!entries) {
4187                         ret = -ENOMEM;
4188                         goto out;
4189                 }
4190
4191                 /*
4192                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4193                  * enabled and disabled dynamically based on package C states,
4194                  * user space can't make reliable use of the CRCs, so let's just
4195                  * completely disable it.
4196                  */
4197                 hsw_disable_ips(crtc);
4198
4199                 spin_lock_irq(&pipe_crc->lock);
4200                 kfree(pipe_crc->entries);
4201                 pipe_crc->entries = entries;
4202                 pipe_crc->head = 0;
4203                 pipe_crc->tail = 0;
4204                 spin_unlock_irq(&pipe_crc->lock);
4205         }
4206
4207         pipe_crc->source = source;
4208
4209         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4210         POSTING_READ(PIPE_CRC_CTL(pipe));
4211
4212         /* real source -> none transition */
4213         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4214                 struct intel_pipe_crc_entry *entries;
4215                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
4216                                                                   pipe);
4217
4218                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4219                                  pipe_name(pipe));
4220
4221                 drm_modeset_lock(&crtc->base.mutex, NULL);
4222                 if (crtc->base.state->active)
4223                         intel_wait_for_vblank(dev_priv, pipe);
4224                 drm_modeset_unlock(&crtc->base.mutex);
4225
4226                 spin_lock_irq(&pipe_crc->lock);
4227                 entries = pipe_crc->entries;
4228                 pipe_crc->entries = NULL;
4229                 pipe_crc->head = 0;
4230                 pipe_crc->tail = 0;
4231                 spin_unlock_irq(&pipe_crc->lock);
4232
4233                 kfree(entries);
4234
4235                 if (IS_G4X(dev_priv))
4236                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4237                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4238                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4239                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4240                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4241
4242                 hsw_enable_ips(crtc);
4243         }
4244
4245         ret = 0;
4246
4247 out:
4248         intel_display_power_put(dev_priv, power_domain);
4249
4250         return ret;
4251 }
4252
4253 /*
4254  * Parse pipe CRC command strings:
4255  *   command: wsp* object wsp+ name wsp+ source wsp*
4256  *   object: 'pipe'
4257  *   name: (A | B | C)
4258  *   source: (none | plane1 | plane2 | pf)
4259  *   wsp: (#0x20 | #0x9 | #0xA)+
4260  *
4261  * eg.:
4262  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4263  *  "pipe A none"    ->  Stop CRC
4264  */
4265 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4266 {
4267         int n_words = 0;
4268
4269         while (*buf) {
4270                 char *end;
4271
4272                 /* skip leading white space */
4273                 buf = skip_spaces(buf);
4274                 if (!*buf)
4275                         break;  /* end of buffer */
4276
4277                 /* find end of word */
4278                 for (end = buf; *end && !isspace(*end); end++)
4279                         ;
4280
4281                 if (n_words == max_words) {
4282                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4283                                          max_words);
4284                         return -EINVAL; /* ran out of words[] before bytes */
4285                 }
4286
4287                 if (*end)
4288                         *end++ = '\0';
4289                 words[n_words++] = buf;
4290                 buf = end;
4291         }
4292
4293         return n_words;
4294 }
4295
4296 enum intel_pipe_crc_object {
4297         PIPE_CRC_OBJECT_PIPE,
4298 };
4299
4300 static const char * const pipe_crc_objects[] = {
4301         "pipe",
4302 };
4303
4304 static int
4305 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4306 {
4307         int i;
4308
4309         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4310                 if (!strcmp(buf, pipe_crc_objects[i])) {
4311                         *o = i;
4312                         return 0;
4313                     }
4314
4315         return -EINVAL;
4316 }
4317
4318 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4319 {
4320         const char name = buf[0];
4321
4322         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4323                 return -EINVAL;
4324
4325         *pipe = name - 'A';
4326
4327         return 0;
4328 }
4329
4330 static int
4331 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4332 {
4333         int i;
4334
4335         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4336                 if (!strcmp(buf, pipe_crc_sources[i])) {
4337                         *s = i;
4338                         return 0;
4339                     }
4340
4341         return -EINVAL;
4342 }
4343
4344 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4345                                  char *buf, size_t len)
4346 {
4347 #define N_WORDS 3
4348         int n_words;
4349         char *words[N_WORDS];
4350         enum pipe pipe;
4351         enum intel_pipe_crc_object object;
4352         enum intel_pipe_crc_source source;
4353
4354         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4355         if (n_words != N_WORDS) {
4356                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4357                                  N_WORDS);
4358                 return -EINVAL;
4359         }
4360
4361         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4362                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4363                 return -EINVAL;
4364         }
4365
4366         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4367                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4368                 return -EINVAL;
4369         }
4370
4371         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4372                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4373                 return -EINVAL;
4374         }
4375
4376         return pipe_crc_set_source(dev_priv, pipe, source);
4377 }
4378
4379 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4380                                      size_t len, loff_t *offp)
4381 {
4382         struct seq_file *m = file->private_data;
4383         struct drm_i915_private *dev_priv = m->private;
4384         char *tmpbuf;
4385         int ret;
4386
4387         if (len == 0)
4388                 return 0;
4389
4390         if (len > PAGE_SIZE - 1) {
4391                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4392                                  PAGE_SIZE);
4393                 return -E2BIG;
4394         }
4395
4396         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4397         if (!tmpbuf)
4398                 return -ENOMEM;
4399
4400         if (copy_from_user(tmpbuf, ubuf, len)) {
4401                 ret = -EFAULT;
4402                 goto out;
4403         }
4404         tmpbuf[len] = '\0';
4405
4406         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4407
4408 out:
4409         kfree(tmpbuf);
4410         if (ret < 0)
4411                 return ret;
4412
4413         *offp += len;
4414         return len;
4415 }
4416
4417 static const struct file_operations i915_display_crc_ctl_fops = {
4418         .owner = THIS_MODULE,
4419         .open = display_crc_ctl_open,
4420         .read = seq_read,
4421         .llseek = seq_lseek,
4422         .release = single_release,
4423         .write = display_crc_ctl_write
4424 };
4425
4426 static ssize_t i915_displayport_test_active_write(struct file *file,
4427                                                   const char __user *ubuf,
4428                                                   size_t len, loff_t *offp)
4429 {
4430         char *input_buffer;
4431         int status = 0;
4432         struct drm_device *dev;
4433         struct drm_connector *connector;
4434         struct list_head *connector_list;
4435         struct intel_dp *intel_dp;
4436         int val = 0;
4437
4438         dev = ((struct seq_file *)file->private_data)->private;
4439
4440         connector_list = &dev->mode_config.connector_list;
4441
4442         if (len == 0)
4443                 return 0;
4444
4445         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4446         if (!input_buffer)
4447                 return -ENOMEM;
4448
4449         if (copy_from_user(input_buffer, ubuf, len)) {
4450                 status = -EFAULT;
4451                 goto out;
4452         }
4453
4454         input_buffer[len] = '\0';
4455         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4456
4457         list_for_each_entry(connector, connector_list, head) {
4458                 if (connector->connector_type !=
4459                     DRM_MODE_CONNECTOR_DisplayPort)
4460                         continue;
4461
4462                 if (connector->status == connector_status_connected &&
4463                     connector->encoder != NULL) {
4464                         intel_dp = enc_to_intel_dp(connector->encoder);
4465                         status = kstrtoint(input_buffer, 10, &val);
4466                         if (status < 0)
4467                                 goto out;
4468                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4469                         /* To prevent erroneous activation of the compliance
4470                          * testing code, only accept an actual value of 1 here
4471                          */
4472                         if (val == 1)
4473                                 intel_dp->compliance_test_active = 1;
4474                         else
4475                                 intel_dp->compliance_test_active = 0;
4476                 }
4477         }
4478 out:
4479         kfree(input_buffer);
4480         if (status < 0)
4481                 return status;
4482
4483         *offp += len;
4484         return len;
4485 }
4486
4487 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4488 {
4489         struct drm_device *dev = m->private;
4490         struct drm_connector *connector;
4491         struct list_head *connector_list = &dev->mode_config.connector_list;
4492         struct intel_dp *intel_dp;
4493
4494         list_for_each_entry(connector, connector_list, head) {
4495                 if (connector->connector_type !=
4496                     DRM_MODE_CONNECTOR_DisplayPort)
4497                         continue;
4498
4499                 if (connector->status == connector_status_connected &&
4500                     connector->encoder != NULL) {
4501                         intel_dp = enc_to_intel_dp(connector->encoder);
4502                         if (intel_dp->compliance_test_active)
4503                                 seq_puts(m, "1");
4504                         else
4505                                 seq_puts(m, "0");
4506                 } else
4507                         seq_puts(m, "0");
4508         }
4509
4510         return 0;
4511 }
4512
4513 static int i915_displayport_test_active_open(struct inode *inode,
4514                                              struct file *file)
4515 {
4516         struct drm_i915_private *dev_priv = inode->i_private;
4517
4518         return single_open(file, i915_displayport_test_active_show,
4519                            &dev_priv->drm);
4520 }
4521
4522 static const struct file_operations i915_displayport_test_active_fops = {
4523         .owner = THIS_MODULE,
4524         .open = i915_displayport_test_active_open,
4525         .read = seq_read,
4526         .llseek = seq_lseek,
4527         .release = single_release,
4528         .write = i915_displayport_test_active_write
4529 };
4530
4531 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4532 {
4533         struct drm_device *dev = m->private;
4534         struct drm_connector *connector;
4535         struct list_head *connector_list = &dev->mode_config.connector_list;
4536         struct intel_dp *intel_dp;
4537
4538         list_for_each_entry(connector, connector_list, head) {
4539                 if (connector->connector_type !=
4540                     DRM_MODE_CONNECTOR_DisplayPort)
4541                         continue;
4542
4543                 if (connector->status == connector_status_connected &&
4544                     connector->encoder != NULL) {
4545                         intel_dp = enc_to_intel_dp(connector->encoder);
4546                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4547                 } else
4548                         seq_puts(m, "0");
4549         }
4550
4551         return 0;
4552 }
4553 static int i915_displayport_test_data_open(struct inode *inode,
4554                                            struct file *file)
4555 {
4556         struct drm_i915_private *dev_priv = inode->i_private;
4557
4558         return single_open(file, i915_displayport_test_data_show,
4559                            &dev_priv->drm);
4560 }
4561
4562 static const struct file_operations i915_displayport_test_data_fops = {
4563         .owner = THIS_MODULE,
4564         .open = i915_displayport_test_data_open,
4565         .read = seq_read,
4566         .llseek = seq_lseek,
4567         .release = single_release
4568 };
4569
4570 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4571 {
4572         struct drm_device *dev = m->private;
4573         struct drm_connector *connector;
4574         struct list_head *connector_list = &dev->mode_config.connector_list;
4575         struct intel_dp *intel_dp;
4576
4577         list_for_each_entry(connector, connector_list, head) {
4578                 if (connector->connector_type !=
4579                     DRM_MODE_CONNECTOR_DisplayPort)
4580                         continue;
4581
4582                 if (connector->status == connector_status_connected &&
4583                     connector->encoder != NULL) {
4584                         intel_dp = enc_to_intel_dp(connector->encoder);
4585                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4586                 } else
4587                         seq_puts(m, "0");
4588         }
4589
4590         return 0;
4591 }
4592
4593 static int i915_displayport_test_type_open(struct inode *inode,
4594                                        struct file *file)
4595 {
4596         struct drm_i915_private *dev_priv = inode->i_private;
4597
4598         return single_open(file, i915_displayport_test_type_show,
4599                            &dev_priv->drm);
4600 }
4601
4602 static const struct file_operations i915_displayport_test_type_fops = {
4603         .owner = THIS_MODULE,
4604         .open = i915_displayport_test_type_open,
4605         .read = seq_read,
4606         .llseek = seq_lseek,
4607         .release = single_release
4608 };
4609
4610 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4611 {
4612         struct drm_i915_private *dev_priv = m->private;
4613         struct drm_device *dev = &dev_priv->drm;
4614         int level;
4615         int num_levels;
4616
4617         if (IS_CHERRYVIEW(dev_priv))
4618                 num_levels = 3;
4619         else if (IS_VALLEYVIEW(dev_priv))
4620                 num_levels = 1;
4621         else
4622                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4623
4624         drm_modeset_lock_all(dev);
4625
4626         for (level = 0; level < num_levels; level++) {
4627                 unsigned int latency = wm[level];
4628
4629                 /*
4630                  * - WM1+ latency values in 0.5us units
4631                  * - latencies are in us on gen9/vlv/chv
4632                  */
4633                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4634                     IS_CHERRYVIEW(dev_priv))
4635                         latency *= 10;
4636                 else if (level > 0)
4637                         latency *= 5;
4638
4639                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4640                            level, wm[level], latency / 10, latency % 10);
4641         }
4642
4643         drm_modeset_unlock_all(dev);
4644 }
4645
4646 static int pri_wm_latency_show(struct seq_file *m, void *data)
4647 {
4648         struct drm_i915_private *dev_priv = m->private;
4649         const uint16_t *latencies;
4650
4651         if (INTEL_GEN(dev_priv) >= 9)
4652                 latencies = dev_priv->wm.skl_latency;
4653         else
4654                 latencies = dev_priv->wm.pri_latency;
4655
4656         wm_latency_show(m, latencies);
4657
4658         return 0;
4659 }
4660
4661 static int spr_wm_latency_show(struct seq_file *m, void *data)
4662 {
4663         struct drm_i915_private *dev_priv = m->private;
4664         const uint16_t *latencies;
4665
4666         if (INTEL_GEN(dev_priv) >= 9)
4667                 latencies = dev_priv->wm.skl_latency;
4668         else
4669                 latencies = dev_priv->wm.spr_latency;
4670
4671         wm_latency_show(m, latencies);
4672
4673         return 0;
4674 }
4675
4676 static int cur_wm_latency_show(struct seq_file *m, void *data)
4677 {
4678         struct drm_i915_private *dev_priv = m->private;
4679         const uint16_t *latencies;
4680
4681         if (INTEL_GEN(dev_priv) >= 9)
4682                 latencies = dev_priv->wm.skl_latency;
4683         else
4684                 latencies = dev_priv->wm.cur_latency;
4685
4686         wm_latency_show(m, latencies);
4687
4688         return 0;
4689 }
4690
4691 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4692 {
4693         struct drm_i915_private *dev_priv = inode->i_private;
4694
4695         if (INTEL_GEN(dev_priv) < 5)
4696                 return -ENODEV;
4697
4698         return single_open(file, pri_wm_latency_show, dev_priv);
4699 }
4700
4701 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4702 {
4703         struct drm_i915_private *dev_priv = inode->i_private;
4704
4705         if (HAS_GMCH_DISPLAY(dev_priv))
4706                 return -ENODEV;
4707
4708         return single_open(file, spr_wm_latency_show, dev_priv);
4709 }
4710
4711 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4712 {
4713         struct drm_i915_private *dev_priv = inode->i_private;
4714
4715         if (HAS_GMCH_DISPLAY(dev_priv))
4716                 return -ENODEV;
4717
4718         return single_open(file, cur_wm_latency_show, dev_priv);
4719 }
4720
4721 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4722                                 size_t len, loff_t *offp, uint16_t wm[8])
4723 {
4724         struct seq_file *m = file->private_data;
4725         struct drm_i915_private *dev_priv = m->private;
4726         struct drm_device *dev = &dev_priv->drm;
4727         uint16_t new[8] = { 0 };
4728         int num_levels;
4729         int level;
4730         int ret;
4731         char tmp[32];
4732
4733         if (IS_CHERRYVIEW(dev_priv))
4734                 num_levels = 3;
4735         else if (IS_VALLEYVIEW(dev_priv))
4736                 num_levels = 1;
4737         else
4738                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4739
4740         if (len >= sizeof(tmp))
4741                 return -EINVAL;
4742
4743         if (copy_from_user(tmp, ubuf, len))
4744                 return -EFAULT;
4745
4746         tmp[len] = '\0';
4747
4748         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4749                      &new[0], &new[1], &new[2], &new[3],
4750                      &new[4], &new[5], &new[6], &new[7]);
4751         if (ret != num_levels)
4752                 return -EINVAL;
4753
4754         drm_modeset_lock_all(dev);
4755
4756         for (level = 0; level < num_levels; level++)
4757                 wm[level] = new[level];
4758
4759         drm_modeset_unlock_all(dev);
4760
4761         return len;
4762 }
4763
4764
4765 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4766                                     size_t len, loff_t *offp)
4767 {
4768         struct seq_file *m = file->private_data;
4769         struct drm_i915_private *dev_priv = m->private;
4770         uint16_t *latencies;
4771
4772         if (INTEL_GEN(dev_priv) >= 9)
4773                 latencies = dev_priv->wm.skl_latency;
4774         else
4775                 latencies = dev_priv->wm.pri_latency;
4776
4777         return wm_latency_write(file, ubuf, len, offp, latencies);
4778 }
4779
4780 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4781                                     size_t len, loff_t *offp)
4782 {
4783         struct seq_file *m = file->private_data;
4784         struct drm_i915_private *dev_priv = m->private;
4785         uint16_t *latencies;
4786
4787         if (INTEL_GEN(dev_priv) >= 9)
4788                 latencies = dev_priv->wm.skl_latency;
4789         else
4790                 latencies = dev_priv->wm.spr_latency;
4791
4792         return wm_latency_write(file, ubuf, len, offp, latencies);
4793 }
4794
4795 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4796                                     size_t len, loff_t *offp)
4797 {
4798         struct seq_file *m = file->private_data;
4799         struct drm_i915_private *dev_priv = m->private;
4800         uint16_t *latencies;
4801
4802         if (INTEL_GEN(dev_priv) >= 9)
4803                 latencies = dev_priv->wm.skl_latency;
4804         else
4805                 latencies = dev_priv->wm.cur_latency;
4806
4807         return wm_latency_write(file, ubuf, len, offp, latencies);
4808 }
4809
4810 static const struct file_operations i915_pri_wm_latency_fops = {
4811         .owner = THIS_MODULE,
4812         .open = pri_wm_latency_open,
4813         .read = seq_read,
4814         .llseek = seq_lseek,
4815         .release = single_release,
4816         .write = pri_wm_latency_write
4817 };
4818
4819 static const struct file_operations i915_spr_wm_latency_fops = {
4820         .owner = THIS_MODULE,
4821         .open = spr_wm_latency_open,
4822         .read = seq_read,
4823         .llseek = seq_lseek,
4824         .release = single_release,
4825         .write = spr_wm_latency_write
4826 };
4827
4828 static const struct file_operations i915_cur_wm_latency_fops = {
4829         .owner = THIS_MODULE,
4830         .open = cur_wm_latency_open,
4831         .read = seq_read,
4832         .llseek = seq_lseek,
4833         .release = single_release,
4834         .write = cur_wm_latency_write
4835 };
4836
4837 static int
4838 i915_wedged_get(void *data, u64 *val)
4839 {
4840         struct drm_i915_private *dev_priv = data;
4841
4842         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4843
4844         return 0;
4845 }
4846
4847 static int
4848 i915_wedged_set(void *data, u64 val)
4849 {
4850         struct drm_i915_private *dev_priv = data;
4851
4852         /*
4853          * There is no safeguard against this debugfs entry colliding
4854          * with the hangcheck calling same i915_handle_error() in
4855          * parallel, causing an explosion. For now we assume that the
4856          * test harness is responsible enough not to inject gpu hangs
4857          * while it is writing to 'i915_wedged'
4858          */
4859
4860         if (i915_reset_in_progress(&dev_priv->gpu_error))
4861                 return -EAGAIN;
4862
4863         i915_handle_error(dev_priv, val,
4864                           "Manually setting wedged to %llu", val);
4865
4866         return 0;
4867 }
4868
4869 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4870                         i915_wedged_get, i915_wedged_set,
4871                         "%llu\n");
4872
4873 static int
4874 i915_ring_missed_irq_get(void *data, u64 *val)
4875 {
4876         struct drm_i915_private *dev_priv = data;
4877
4878         *val = dev_priv->gpu_error.missed_irq_rings;
4879         return 0;
4880 }
4881
4882 static int
4883 i915_ring_missed_irq_set(void *data, u64 val)
4884 {
4885         struct drm_i915_private *dev_priv = data;
4886         struct drm_device *dev = &dev_priv->drm;
4887         int ret;
4888
4889         /* Lock against concurrent debugfs callers */
4890         ret = mutex_lock_interruptible(&dev->struct_mutex);
4891         if (ret)
4892                 return ret;
4893         dev_priv->gpu_error.missed_irq_rings = val;
4894         mutex_unlock(&dev->struct_mutex);
4895
4896         return 0;
4897 }
4898
4899 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4900                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4901                         "0x%08llx\n");
4902
4903 static int
4904 i915_ring_test_irq_get(void *data, u64 *val)
4905 {
4906         struct drm_i915_private *dev_priv = data;
4907
4908         *val = dev_priv->gpu_error.test_irq_rings;
4909
4910         return 0;
4911 }
4912
4913 static int
4914 i915_ring_test_irq_set(void *data, u64 val)
4915 {
4916         struct drm_i915_private *dev_priv = data;
4917
4918         val &= INTEL_INFO(dev_priv)->ring_mask;
4919         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4920         dev_priv->gpu_error.test_irq_rings = val;
4921
4922         return 0;
4923 }
4924
4925 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4926                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4927                         "0x%08llx\n");
4928
4929 #define DROP_UNBOUND 0x1
4930 #define DROP_BOUND 0x2
4931 #define DROP_RETIRE 0x4
4932 #define DROP_ACTIVE 0x8
4933 #define DROP_FREED 0x10
4934 #define DROP_ALL (DROP_UNBOUND  | \
4935                   DROP_BOUND    | \
4936                   DROP_RETIRE   | \
4937                   DROP_ACTIVE   | \
4938                   DROP_FREED)
4939 static int
4940 i915_drop_caches_get(void *data, u64 *val)
4941 {
4942         *val = DROP_ALL;
4943
4944         return 0;
4945 }
4946
4947 static int
4948 i915_drop_caches_set(void *data, u64 val)
4949 {
4950         struct drm_i915_private *dev_priv = data;
4951         struct drm_device *dev = &dev_priv->drm;
4952         int ret;
4953
4954         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4955
4956         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4957          * on ioctls on -EAGAIN. */
4958         ret = mutex_lock_interruptible(&dev->struct_mutex);
4959         if (ret)
4960                 return ret;
4961
4962         if (val & DROP_ACTIVE) {
4963                 ret = i915_gem_wait_for_idle(dev_priv,
4964                                              I915_WAIT_INTERRUPTIBLE |
4965                                              I915_WAIT_LOCKED);
4966                 if (ret)
4967                         goto unlock;
4968         }
4969
4970         if (val & (DROP_RETIRE | DROP_ACTIVE))
4971                 i915_gem_retire_requests(dev_priv);
4972
4973         if (val & DROP_BOUND)
4974                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4975
4976         if (val & DROP_UNBOUND)
4977                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4978
4979 unlock:
4980         mutex_unlock(&dev->struct_mutex);
4981
4982         if (val & DROP_FREED) {
4983                 synchronize_rcu();
4984                 flush_work(&dev_priv->mm.free_work);
4985         }
4986
4987         return ret;
4988 }
4989
4990 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4991                         i915_drop_caches_get, i915_drop_caches_set,
4992                         "0x%08llx\n");
4993
4994 static int
4995 i915_max_freq_get(void *data, u64 *val)
4996 {
4997         struct drm_i915_private *dev_priv = data;
4998
4999         if (INTEL_GEN(dev_priv) < 6)
5000                 return -ENODEV;
5001
5002         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
5003         return 0;
5004 }
5005
5006 static int
5007 i915_max_freq_set(void *data, u64 val)
5008 {
5009         struct drm_i915_private *dev_priv = data;
5010         u32 hw_max, hw_min;
5011         int ret;
5012
5013         if (INTEL_GEN(dev_priv) < 6)
5014                 return -ENODEV;
5015
5016         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
5017
5018         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5019         if (ret)
5020                 return ret;
5021
5022         /*
5023          * Turbo will still be enabled, but won't go above the set value.
5024          */
5025         val = intel_freq_opcode(dev_priv, val);
5026
5027         hw_max = dev_priv->rps.max_freq;
5028         hw_min = dev_priv->rps.min_freq;
5029
5030         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5031                 mutex_unlock(&dev_priv->rps.hw_lock);
5032                 return -EINVAL;
5033         }
5034
5035         dev_priv->rps.max_freq_softlimit = val;
5036
5037         intel_set_rps(dev_priv, val);
5038
5039         mutex_unlock(&dev_priv->rps.hw_lock);
5040
5041         return 0;
5042 }
5043
5044 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5045                         i915_max_freq_get, i915_max_freq_set,
5046                         "%llu\n");
5047
5048 static int
5049 i915_min_freq_get(void *data, u64 *val)
5050 {
5051         struct drm_i915_private *dev_priv = data;
5052
5053         if (INTEL_GEN(dev_priv) < 6)
5054                 return -ENODEV;
5055
5056         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5057         return 0;
5058 }
5059
5060 static int
5061 i915_min_freq_set(void *data, u64 val)
5062 {
5063         struct drm_i915_private *dev_priv = data;
5064         u32 hw_max, hw_min;
5065         int ret;
5066
5067         if (INTEL_GEN(dev_priv) < 6)
5068                 return -ENODEV;
5069
5070         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5071
5072         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5073         if (ret)
5074                 return ret;
5075
5076         /*
5077          * Turbo will still be enabled, but won't go below the set value.
5078          */
5079         val = intel_freq_opcode(dev_priv, val);
5080
5081         hw_max = dev_priv->rps.max_freq;
5082         hw_min = dev_priv->rps.min_freq;
5083
5084         if (val < hw_min ||
5085             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5086                 mutex_unlock(&dev_priv->rps.hw_lock);
5087                 return -EINVAL;
5088         }
5089
5090         dev_priv->rps.min_freq_softlimit = val;
5091
5092         intel_set_rps(dev_priv, val);
5093
5094         mutex_unlock(&dev_priv->rps.hw_lock);
5095
5096         return 0;
5097 }
5098
5099 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5100                         i915_min_freq_get, i915_min_freq_set,
5101                         "%llu\n");
5102
5103 static int
5104 i915_cache_sharing_get(void *data, u64 *val)
5105 {
5106         struct drm_i915_private *dev_priv = data;
5107         u32 snpcr;
5108
5109         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5110                 return -ENODEV;
5111
5112         intel_runtime_pm_get(dev_priv);
5113
5114         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5115
5116         intel_runtime_pm_put(dev_priv);
5117
5118         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5119
5120         return 0;
5121 }
5122
5123 static int
5124 i915_cache_sharing_set(void *data, u64 val)
5125 {
5126         struct drm_i915_private *dev_priv = data;
5127         u32 snpcr;
5128
5129         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5130                 return -ENODEV;
5131
5132         if (val > 3)
5133                 return -EINVAL;
5134
5135         intel_runtime_pm_get(dev_priv);
5136         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5137
5138         /* Update the cache sharing policy here as well */
5139         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5140         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5141         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5142         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5143
5144         intel_runtime_pm_put(dev_priv);
5145         return 0;
5146 }
5147
5148 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5149                         i915_cache_sharing_get, i915_cache_sharing_set,
5150                         "%llu\n");
5151
5152 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5153                                           struct sseu_dev_info *sseu)
5154 {
5155         int ss_max = 2;
5156         int ss;
5157         u32 sig1[ss_max], sig2[ss_max];
5158
5159         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5160         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5161         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5162         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5163
5164         for (ss = 0; ss < ss_max; ss++) {
5165                 unsigned int eu_cnt;
5166
5167                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5168                         /* skip disabled subslice */
5169                         continue;
5170
5171                 sseu->slice_mask = BIT(0);
5172                 sseu->subslice_mask |= BIT(ss);
5173                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5174                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5175                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5176                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5177                 sseu->eu_total += eu_cnt;
5178                 sseu->eu_per_subslice = max_t(unsigned int,
5179                                               sseu->eu_per_subslice, eu_cnt);
5180         }
5181 }
5182
5183 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5184                                     struct sseu_dev_info *sseu)
5185 {
5186         int s_max = 3, ss_max = 4;
5187         int s, ss;
5188         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5189
5190         /* BXT has a single slice and at most 3 subslices. */
5191         if (IS_BROXTON(dev_priv)) {
5192                 s_max = 1;
5193                 ss_max = 3;
5194         }
5195
5196         for (s = 0; s < s_max; s++) {
5197                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5198                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5199                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5200         }
5201
5202         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5203                      GEN9_PGCTL_SSA_EU19_ACK |
5204                      GEN9_PGCTL_SSA_EU210_ACK |
5205                      GEN9_PGCTL_SSA_EU311_ACK;
5206         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5207                      GEN9_PGCTL_SSB_EU19_ACK |
5208                      GEN9_PGCTL_SSB_EU210_ACK |
5209                      GEN9_PGCTL_SSB_EU311_ACK;
5210
5211         for (s = 0; s < s_max; s++) {
5212                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5213                         /* skip disabled slice */
5214                         continue;
5215
5216                 sseu->slice_mask |= BIT(s);
5217
5218                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5219                         sseu->subslice_mask =
5220                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5221
5222                 for (ss = 0; ss < ss_max; ss++) {
5223                         unsigned int eu_cnt;
5224
5225                         if (IS_BROXTON(dev_priv)) {
5226                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5227                                         /* skip disabled subslice */
5228                                         continue;
5229
5230                                 sseu->subslice_mask |= BIT(ss);
5231                         }
5232
5233                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5234                                                eu_mask[ss%2]);
5235                         sseu->eu_total += eu_cnt;
5236                         sseu->eu_per_subslice = max_t(unsigned int,
5237                                                       sseu->eu_per_subslice,
5238                                                       eu_cnt);
5239                 }
5240         }
5241 }
5242
5243 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5244                                          struct sseu_dev_info *sseu)
5245 {
5246         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5247         int s;
5248
5249         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5250
5251         if (sseu->slice_mask) {
5252                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5253                 sseu->eu_per_subslice =
5254                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5255                 sseu->eu_total = sseu->eu_per_subslice *
5256                                  sseu_subslice_total(sseu);
5257
5258                 /* subtract fused off EU(s) from enabled slice(s) */
5259                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5260                         u8 subslice_7eu =
5261                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5262
5263                         sseu->eu_total -= hweight8(subslice_7eu);
5264                 }
5265         }
5266 }
5267
5268 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5269                                  const struct sseu_dev_info *sseu)
5270 {
5271         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5272         const char *type = is_available_info ? "Available" : "Enabled";
5273
5274         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5275                    sseu->slice_mask);
5276         seq_printf(m, "  %s Slice Total: %u\n", type,
5277                    hweight8(sseu->slice_mask));
5278         seq_printf(m, "  %s Subslice Total: %u\n", type,
5279                    sseu_subslice_total(sseu));
5280         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5281                    sseu->subslice_mask);
5282         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5283                    hweight8(sseu->subslice_mask));
5284         seq_printf(m, "  %s EU Total: %u\n", type,
5285                    sseu->eu_total);
5286         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5287                    sseu->eu_per_subslice);
5288
5289         if (!is_available_info)
5290                 return;
5291
5292         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5293         if (HAS_POOLED_EU(dev_priv))
5294                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5295
5296         seq_printf(m, "  Has Slice Power Gating: %s\n",
5297                    yesno(sseu->has_slice_pg));
5298         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5299                    yesno(sseu->has_subslice_pg));
5300         seq_printf(m, "  Has EU Power Gating: %s\n",
5301                    yesno(sseu->has_eu_pg));
5302 }
5303
5304 static int i915_sseu_status(struct seq_file *m, void *unused)
5305 {
5306         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5307         struct sseu_dev_info sseu;
5308
5309         if (INTEL_GEN(dev_priv) < 8)
5310                 return -ENODEV;
5311
5312         seq_puts(m, "SSEU Device Info\n");
5313         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5314
5315         seq_puts(m, "SSEU Device Status\n");
5316         memset(&sseu, 0, sizeof(sseu));
5317
5318         intel_runtime_pm_get(dev_priv);
5319
5320         if (IS_CHERRYVIEW(dev_priv)) {
5321                 cherryview_sseu_device_status(dev_priv, &sseu);
5322         } else if (IS_BROADWELL(dev_priv)) {
5323                 broadwell_sseu_device_status(dev_priv, &sseu);
5324         } else if (INTEL_GEN(dev_priv) >= 9) {
5325                 gen9_sseu_device_status(dev_priv, &sseu);
5326         }
5327
5328         intel_runtime_pm_put(dev_priv);
5329
5330         i915_print_sseu_info(m, false, &sseu);
5331
5332         return 0;
5333 }
5334
5335 static int i915_forcewake_open(struct inode *inode, struct file *file)
5336 {
5337         struct drm_i915_private *dev_priv = inode->i_private;
5338
5339         if (INTEL_GEN(dev_priv) < 6)
5340                 return 0;
5341
5342         intel_runtime_pm_get(dev_priv);
5343         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5344
5345         return 0;
5346 }
5347
5348 static int i915_forcewake_release(struct inode *inode, struct file *file)
5349 {
5350         struct drm_i915_private *dev_priv = inode->i_private;
5351
5352         if (INTEL_GEN(dev_priv) < 6)
5353                 return 0;
5354
5355         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5356         intel_runtime_pm_put(dev_priv);
5357
5358         return 0;
5359 }
5360
5361 static const struct file_operations i915_forcewake_fops = {
5362         .owner = THIS_MODULE,
5363         .open = i915_forcewake_open,
5364         .release = i915_forcewake_release,
5365 };
5366
5367 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5368 {
5369         struct dentry *ent;
5370
5371         ent = debugfs_create_file("i915_forcewake_user",
5372                                   S_IRUSR,
5373                                   root, to_i915(minor->dev),
5374                                   &i915_forcewake_fops);
5375         if (!ent)
5376                 return -ENOMEM;
5377
5378         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5379 }
5380
5381 static int i915_debugfs_create(struct dentry *root,
5382                                struct drm_minor *minor,
5383                                const char *name,
5384                                const struct file_operations *fops)
5385 {
5386         struct dentry *ent;
5387
5388         ent = debugfs_create_file(name,
5389                                   S_IRUGO | S_IWUSR,
5390                                   root, to_i915(minor->dev),
5391                                   fops);
5392         if (!ent)
5393                 return -ENOMEM;
5394
5395         return drm_add_fake_info_node(minor, ent, fops);
5396 }
5397
5398 static const struct drm_info_list i915_debugfs_list[] = {
5399         {"i915_capabilities", i915_capabilities, 0},
5400         {"i915_gem_objects", i915_gem_object_info, 0},
5401         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5402         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5403         {"i915_gem_stolen", i915_gem_stolen_list_info },
5404         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5405         {"i915_gem_request", i915_gem_request_info, 0},
5406         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5407         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5408         {"i915_gem_interrupt", i915_interrupt_info, 0},
5409         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5410         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5411         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5412         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5413         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5414         {"i915_guc_info", i915_guc_info, 0},
5415         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5416         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5417         {"i915_frequency_info", i915_frequency_info, 0},
5418         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5419         {"i915_drpc_info", i915_drpc_info, 0},
5420         {"i915_emon_status", i915_emon_status, 0},
5421         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5422         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5423         {"i915_fbc_status", i915_fbc_status, 0},
5424         {"i915_ips_status", i915_ips_status, 0},
5425         {"i915_sr_status", i915_sr_status, 0},
5426         {"i915_opregion", i915_opregion, 0},
5427         {"i915_vbt", i915_vbt, 0},
5428         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5429         {"i915_context_status", i915_context_status, 0},
5430         {"i915_dump_lrc", i915_dump_lrc, 0},
5431         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5432         {"i915_swizzle_info", i915_swizzle_info, 0},
5433         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5434         {"i915_llc", i915_llc, 0},
5435         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5436         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5437         {"i915_energy_uJ", i915_energy_uJ, 0},
5438         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5439         {"i915_power_domain_info", i915_power_domain_info, 0},
5440         {"i915_dmc_info", i915_dmc_info, 0},
5441         {"i915_display_info", i915_display_info, 0},
5442         {"i915_engine_info", i915_engine_info, 0},
5443         {"i915_semaphore_status", i915_semaphore_status, 0},
5444         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5445         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5446         {"i915_wa_registers", i915_wa_registers, 0},
5447         {"i915_ddb_info", i915_ddb_info, 0},
5448         {"i915_sseu_status", i915_sseu_status, 0},
5449         {"i915_drrs_status", i915_drrs_status, 0},
5450         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5451 };
5452 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5453
5454 static const struct i915_debugfs_files {
5455         const char *name;
5456         const struct file_operations *fops;
5457 } i915_debugfs_files[] = {
5458         {"i915_wedged", &i915_wedged_fops},
5459         {"i915_max_freq", &i915_max_freq_fops},
5460         {"i915_min_freq", &i915_min_freq_fops},
5461         {"i915_cache_sharing", &i915_cache_sharing_fops},
5462         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5463         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5464         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5465 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5466         {"i915_error_state", &i915_error_state_fops},
5467 #endif
5468         {"i915_next_seqno", &i915_next_seqno_fops},
5469         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5470         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5471         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5472         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5473         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5474         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5475         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5476         {"i915_dp_test_active", &i915_displayport_test_active_fops},
5477         {"i915_guc_log_control", &i915_guc_log_control_fops}
5478 };
5479
5480 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5481 {
5482         enum pipe pipe;
5483
5484         for_each_pipe(dev_priv, pipe) {
5485                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5486
5487                 pipe_crc->opened = false;
5488                 spin_lock_init(&pipe_crc->lock);
5489                 init_waitqueue_head(&pipe_crc->wq);
5490         }
5491 }
5492
5493 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5494 {
5495         struct drm_minor *minor = dev_priv->drm.primary;
5496         int ret, i;
5497
5498         ret = i915_forcewake_create(minor->debugfs_root, minor);
5499         if (ret)
5500                 return ret;
5501
5502         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5503                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5504                 if (ret)
5505                         return ret;
5506         }
5507
5508         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5509                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5510                                           i915_debugfs_files[i].name,
5511                                           i915_debugfs_files[i].fops);
5512                 if (ret)
5513                         return ret;
5514         }
5515
5516         return drm_debugfs_create_files(i915_debugfs_list,
5517                                         I915_DEBUGFS_ENTRIES,
5518                                         minor->debugfs_root, minor);
5519 }
5520
5521 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5522 {
5523         struct drm_minor *minor = dev_priv->drm.primary;
5524         int i;
5525
5526         drm_debugfs_remove_files(i915_debugfs_list,
5527                                  I915_DEBUGFS_ENTRIES, minor);
5528
5529         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5530                                  1, minor);
5531
5532         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5533                 struct drm_info_list *info_list =
5534                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5535
5536                 drm_debugfs_remove_files(info_list, 1, minor);
5537         }
5538
5539         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5540                 struct drm_info_list *info_list =
5541                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5542
5543                 drm_debugfs_remove_files(info_list, 1, minor);
5544         }
5545 }
5546
5547 struct dpcd_block {
5548         /* DPCD dump start address. */
5549         unsigned int offset;
5550         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5551         unsigned int end;
5552         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5553         size_t size;
5554         /* Only valid for eDP. */
5555         bool edp;
5556 };
5557
5558 static const struct dpcd_block i915_dpcd_debug[] = {
5559         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5560         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5561         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5562         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5563         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5564         { .offset = DP_SET_POWER },
5565         { .offset = DP_EDP_DPCD_REV },
5566         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5567         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5568         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5569 };
5570
5571 static int i915_dpcd_show(struct seq_file *m, void *data)
5572 {
5573         struct drm_connector *connector = m->private;
5574         struct intel_dp *intel_dp =
5575                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5576         uint8_t buf[16];
5577         ssize_t err;
5578         int i;
5579
5580         if (connector->status != connector_status_connected)
5581                 return -ENODEV;
5582
5583         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5584                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5585                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5586
5587                 if (b->edp &&
5588                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5589                         continue;
5590
5591                 /* low tech for now */
5592                 if (WARN_ON(size > sizeof(buf)))
5593                         continue;
5594
5595                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5596                 if (err <= 0) {
5597                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5598                                   size, b->offset, err);
5599                         continue;
5600                 }
5601
5602                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5603         }
5604
5605         return 0;
5606 }
5607
5608 static int i915_dpcd_open(struct inode *inode, struct file *file)
5609 {
5610         return single_open(file, i915_dpcd_show, inode->i_private);
5611 }
5612
5613 static const struct file_operations i915_dpcd_fops = {
5614         .owner = THIS_MODULE,
5615         .open = i915_dpcd_open,
5616         .read = seq_read,
5617         .llseek = seq_lseek,
5618         .release = single_release,
5619 };
5620
5621 static int i915_panel_show(struct seq_file *m, void *data)
5622 {
5623         struct drm_connector *connector = m->private;
5624         struct intel_dp *intel_dp =
5625                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5626
5627         if (connector->status != connector_status_connected)
5628                 return -ENODEV;
5629
5630         seq_printf(m, "Panel power up delay: %d\n",
5631                    intel_dp->panel_power_up_delay);
5632         seq_printf(m, "Panel power down delay: %d\n",
5633                    intel_dp->panel_power_down_delay);
5634         seq_printf(m, "Backlight on delay: %d\n",
5635                    intel_dp->backlight_on_delay);
5636         seq_printf(m, "Backlight off delay: %d\n",
5637                    intel_dp->backlight_off_delay);
5638
5639         return 0;
5640 }
5641
5642 static int i915_panel_open(struct inode *inode, struct file *file)
5643 {
5644         return single_open(file, i915_panel_show, inode->i_private);
5645 }
5646
5647 static const struct file_operations i915_panel_fops = {
5648         .owner = THIS_MODULE,
5649         .open = i915_panel_open,
5650         .read = seq_read,
5651         .llseek = seq_lseek,
5652         .release = single_release,
5653 };
5654
5655 /**
5656  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5657  * @connector: pointer to a registered drm_connector
5658  *
5659  * Cleanup will be done by drm_connector_unregister() through a call to
5660  * drm_debugfs_connector_remove().
5661  *
5662  * Returns 0 on success, negative error codes on error.
5663  */
5664 int i915_debugfs_connector_add(struct drm_connector *connector)
5665 {
5666         struct dentry *root = connector->debugfs_entry;
5667
5668         /* The connector must have been registered beforehands. */
5669         if (!root)
5670                 return -ENODEV;
5671
5672         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5673             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5674                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5675                                     connector, &i915_dpcd_fops);
5676
5677         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5678                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5679                                     connector, &i915_panel_fops);
5680
5681         return 0;
5682 }