drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
  70
  71 int i915_enable_fbc __read_mostly = -1;
  72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  73 MODULE_PARM_DESC(i915_enable_fbc,
  74                 "Enable frame buffer compression for power savings "
  75                 "(default: -1 (use per-chip default))");
  76
  77 unsigned int i915_lvds_downclock __read_mostly = 0;
  78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  79 MODULE_PARM_DESC(lvds_downclock,
  80                 "Use panel (LVDS/eDP) downclocking for power savings "
  81                 "(default: false)");
  82
  83 int i915_panel_use_ssc __read_mostly = -1;
  84 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  85 MODULE_PARM_DESC(lvds_use_ssc,
  86                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  87                 "(default: auto from VBT)");
  88
  89 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  90 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  91 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  92                 "Override selection of SDVO panel mode in the VBT "
  93                 "(default: auto)");
  94
  95 static bool i915_try_reset __read_mostly = true;
  96 module_param_named(reset, i915_try_reset, bool, 0600);
  97 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  98
  99 bool i915_enable_hangcheck __read_mostly = true;
 100 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 101 MODULE_PARM_DESC(enable_hangcheck,
 102                 "Periodically check GPU activity for detecting hangs. "
 103                 "WARNING: Disabling this can cause system wide hangs. "
 104                 "(default: true)");
 105
 106 static struct drm_driver driver;
 107 extern int intel_agp_enabled;
 108
 109 #define INTEL_VGA_DEVICE(id, info) {            \
 110         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 111         .class_mask = 0xff0000,                 \
 112         .vendor = 0x8086,                       \
 113         .device = id,                           \
 114         .subvendor = PCI_ANY_ID,                \
 115         .subdevice = PCI_ANY_ID,                \
 116         .driver_data = (unsigned long) info }
 117
 118 static const struct intel_device_info intel_i830_info = {
 119         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 120         .has_overlay = 1, .overlay_needs_physical = 1,
 121 };
 122
 123 static const struct intel_device_info intel_845g_info = {
 124         .gen = 2,
 125         .has_overlay = 1, .overlay_needs_physical = 1,
 126 };
 127
 128 static const struct intel_device_info intel_i85x_info = {
 129         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 130         .cursor_needs_physical = 1,
 131         .has_overlay = 1, .overlay_needs_physical = 1,
 132 };
 133
 134 static const struct intel_device_info intel_i865g_info = {
 135         .gen = 2,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_i915g_info = {
 140         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 141         .has_overlay = 1, .overlay_needs_physical = 1,
 142 };
 143 static const struct intel_device_info intel_i915gm_info = {
 144         .gen = 3, .is_mobile = 1,
 145         .cursor_needs_physical = 1,
 146         .has_overlay = 1, .overlay_needs_physical = 1,
 147         .supports_tv = 1,
 148 };
 149 static const struct intel_device_info intel_i945g_info = {
 150         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152 };
 153 static const struct intel_device_info intel_i945gm_info = {
 154         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 155         .has_hotplug = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157         .supports_tv = 1,
 158 };
 159
 160 static const struct intel_device_info intel_i965g_info = {
 161         .gen = 4, .is_broadwater = 1,
 162         .has_hotplug = 1,
 163         .has_overlay = 1,
 164 };
 165
 166 static const struct intel_device_info intel_i965gm_info = {
 167         .gen = 4, .is_crestline = 1,
 168         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 169         .has_overlay = 1,
 170         .supports_tv = 1,
 171 };
 172
 173 static const struct intel_device_info intel_g33_info = {
 174         .gen = 3, .is_g33 = 1,
 175         .need_gfx_hws = 1, .has_hotplug = 1,
 176         .has_overlay = 1,
 177 };
 178
 179 static const struct intel_device_info intel_g45_info = {
 180         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 181         .has_pipe_cxsr = 1, .has_hotplug = 1,
 182         .has_bsd_ring = 1,
 183 };
 184
 185 static const struct intel_device_info intel_gm45_info = {
 186         .gen = 4, .is_g4x = 1,
 187         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 188         .has_pipe_cxsr = 1, .has_hotplug = 1,
 189         .supports_tv = 1,
 190         .has_bsd_ring = 1,
 191 };
 192
 193 static const struct intel_device_info intel_pineview_info = {
 194         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 195         .need_gfx_hws = 1, .has_hotplug = 1,
 196         .has_overlay = 1,
 197 };
 198
 199 static const struct intel_device_info intel_ironlake_d_info = {
 200         .gen = 5,
 201         .need_gfx_hws = 1, .has_hotplug = 1,
 202         .has_bsd_ring = 1,
 203 };
 204
 205 static const struct intel_device_info intel_ironlake_m_info = {
 206         .gen = 5, .is_mobile = 1,
 207         .need_gfx_hws = 1, .has_hotplug = 1,
 208         .has_fbc = 1,
 209         .has_bsd_ring = 1,
 210 };
 211
 212 static const struct intel_device_info intel_sandybridge_d_info = {
 213         .gen = 6,
 214         .need_gfx_hws = 1, .has_hotplug = 1,
 215         .has_bsd_ring = 1,
 216         .has_blt_ring = 1,
 217         .has_llc = 1,
 218 };
 219
 220 static const struct intel_device_info intel_sandybridge_m_info = {
 221         .gen = 6, .is_mobile = 1,
 222         .need_gfx_hws = 1, .has_hotplug = 1,
 223         .has_fbc = 1,
 224         .has_bsd_ring = 1,
 225         .has_blt_ring = 1,
 226         .has_llc = 1,
 227 };
 228
 229 static const struct intel_device_info intel_ivybridge_d_info = {
 230         .is_ivybridge = 1, .gen = 7,
 231         .need_gfx_hws = 1, .has_hotplug = 1,
 232         .has_bsd_ring = 1,
 233         .has_blt_ring = 1,
 234         .has_llc = 1,
 235 };
 236
 237 static const struct intel_device_info intel_ivybridge_m_info = {
 238         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 239         .need_gfx_hws = 1, .has_hotplug = 1,
 240         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 241         .has_bsd_ring = 1,
 242         .has_blt_ring = 1,
 243         .has_llc = 1,
 244 };
 245
 246 static const struct pci_device_id pciidlist[] = {               /* aka */
 247         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 248         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 249         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 250         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 251         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 252         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 253         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 254         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 255         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 256         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 257         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 258         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 259         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 260         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 261         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 262         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 263         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 264         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 265         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 266         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 267         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 268         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 269         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 270         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 271         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 272         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 273         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 274         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 275         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 276         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 277         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 278         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 279         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 280         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 281         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 282         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 283         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 284         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 285         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 286         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 287         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 288         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 289         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 290         {0, 0, 0}
 291 };
 292
 293 #if defined(CONFIG_DRM_I915_KMS)
 294 MODULE_DEVICE_TABLE(pci, pciidlist);
 295 #endif
 296
 297 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 298 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 299 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 300 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 301
 302 void intel_detect_pch(struct drm_device *dev)
 303 {
 304         struct drm_i915_private *dev_priv = dev->dev_private;
 305         struct pci_dev *pch;
 306
 307         /*
 308          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 309          * make graphics device passthrough work easy for VMM, that only
 310          * need to expose ISA bridge to let driver know the real hardware
 311          * underneath. This is a requirement from virtualization team.
 312          */
 313         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 314         if (pch) {
 315                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 316                         int id;
 317                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 318
 319                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 320                                 dev_priv->pch_type = PCH_IBX;
 321                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 322                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 323                                 dev_priv->pch_type = PCH_CPT;
 324                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 325                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 326                                 /* PantherPoint is CPT compatible */
 327                                 dev_priv->pch_type = PCH_CPT;
 328                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 329                         }
 330                 }
 331                 pci_dev_put(pch);
 332         }
 333 }
 334
 335 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 336 {
 337         int count;
 338
 339         count = 0;
 340         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 341                 udelay(10);
 342
 343         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 344         POSTING_READ(FORCEWAKE);
 345
 346         count = 0;
 347         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 348                 udelay(10);
 349 }
 350
 351 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 352 {
 353         int count;
 354
 355         count = 0;
 356         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 357                 udelay(10);
 358
 359         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 360         POSTING_READ(FORCEWAKE_MT);
 361
 362         count = 0;
 363         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 364                 udelay(10);
 365 }
 366
 367 /*
 368  * Generally this is called implicitly by the register read function. However,
 369  * if some sequence requires the GT to not power down then this function should
 370  * be called at the beginning of the sequence followed by a call to
 371  * gen6_gt_force_wake_put() at the end of the sequence.
 372  */
 373 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 374 {
 375         unsigned long irqflags;
 376
 377         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 378         if (dev_priv->forcewake_count++ == 0)
 379                 dev_priv->display.force_wake_get(dev_priv);
 380         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 381 }
 382
 383 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 384 {
 385         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 386         POSTING_READ(FORCEWAKE);
 387 }
 388
 389 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 390 {
 391         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 392         POSTING_READ(FORCEWAKE_MT);
 393 }
 394
 395 /*
 396  * see gen6_gt_force_wake_get()
 397  */
 398 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 399 {
 400         unsigned long irqflags;
 401
 402         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 403         if (--dev_priv->forcewake_count == 0)
 404                 dev_priv->display.force_wake_put(dev_priv);
 405         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 406 }
 407
 408 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 409 {
 410         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 411                 int loop = 500;
 412                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 413                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 414                         udelay(10);
 415                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 416                 }
 417                 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
 418                 dev_priv->gt_fifo_count = fifo;
 419         }
 420         dev_priv->gt_fifo_count--;
 421 }
 422
 423 static int i915_drm_freeze(struct drm_device *dev)
 424 {
 425         struct drm_i915_private *dev_priv = dev->dev_private;
 426
 427         drm_kms_helper_poll_disable(dev);
 428
 429         pci_save_state(dev->pdev);
 430
 431         /* If KMS is active, we do the leavevt stuff here */
 432         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 433                 int error = i915_gem_idle(dev);
 434                 if (error) {
 435                         dev_err(&dev->pdev->dev,
 436                                 "GEM idle failed, resume might fail\n");
 437                         return error;
 438                 }
 439                 drm_irq_uninstall(dev);
 440         }
 441
 442         i915_save_state(dev);
 443
 444         intel_opregion_fini(dev);
 445
 446         /* Modeset on resume, not lid events */
 447         dev_priv->modeset_on_lid = 0;
 448
 449         return 0;
 450 }
 451
 452 int i915_suspend(struct drm_device *dev, pm_message_t state)
 453 {
 454         int error;
 455
 456         if (!dev || !dev->dev_private) {
 457                 DRM_ERROR("dev: %p\n", dev);
 458                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 459                 return -ENODEV;
 460         }
 461
 462         if (state.event == PM_EVENT_PRETHAW)
 463                 return 0;
 464
 465
 466         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 467                 return 0;
 468
 469         error = i915_drm_freeze(dev);
 470         if (error)
 471                 return error;
 472
 473         if (state.event == PM_EVENT_SUSPEND) {
 474                 /* Shut down the device */
 475                 pci_disable_device(dev->pdev);
 476                 pci_set_power_state(dev->pdev, PCI_D3hot);
 477         }
 478
 479         return 0;
 480 }
 481
 482 static int i915_drm_thaw(struct drm_device *dev)
 483 {
 484         struct drm_i915_private *dev_priv = dev->dev_private;
 485         int error = 0;
 486
 487         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 488                 mutex_lock(&dev->struct_mutex);
 489                 i915_gem_restore_gtt_mappings(dev);
 490                 mutex_unlock(&dev->struct_mutex);
 491         }
 492
 493         i915_restore_state(dev);
 494         intel_opregion_setup(dev);
 495
 496         /* KMS EnterVT equivalent */
 497         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 498                 mutex_lock(&dev->struct_mutex);
 499                 dev_priv->mm.suspended = 0;
 500
 501                 error = i915_gem_init_ringbuffer(dev);
 502                 mutex_unlock(&dev->struct_mutex);
 503
 504                 if (HAS_PCH_SPLIT(dev))
 505                         ironlake_init_pch_refclk(dev);
 506
 507                 drm_mode_config_reset(dev);
 508                 drm_irq_install(dev);
 509
 510                 /* Resume the modeset for every activated CRTC */
 511                 drm_helper_resume_force_mode(dev);
 512
 513                 if (IS_IRONLAKE_M(dev))
 514                         ironlake_enable_rc6(dev);
 515         }
 516
 517         intel_opregion_init(dev);
 518
 519         dev_priv->modeset_on_lid = 0;
 520
 521         return error;
 522 }
 523
 524 int i915_resume(struct drm_device *dev)
 525 {
 526         int ret;
 527
 528         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 529                 return 0;
 530
 531         if (pci_enable_device(dev->pdev))
 532                 return -EIO;
 533
 534         pci_set_master(dev->pdev);
 535
 536         ret = i915_drm_thaw(dev);
 537         if (ret)
 538                 return ret;
 539
 540         drm_kms_helper_poll_enable(dev);
 541         return 0;
 542 }
 543
 544 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 545 {
 546         struct drm_i915_private *dev_priv = dev->dev_private;
 547
 548         if (IS_I85X(dev))
 549                 return -ENODEV;
 550
 551         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 552         POSTING_READ(D_STATE);
 553
 554         if (IS_I830(dev) || IS_845G(dev)) {
 555                 I915_WRITE(DEBUG_RESET_I830,
 556                            DEBUG_RESET_DISPLAY |
 557                            DEBUG_RESET_RENDER |
 558                            DEBUG_RESET_FULL);
 559                 POSTING_READ(DEBUG_RESET_I830);
 560                 msleep(1);
 561
 562                 I915_WRITE(DEBUG_RESET_I830, 0);
 563                 POSTING_READ(DEBUG_RESET_I830);
 564         }
 565
 566         msleep(1);
 567
 568         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 569         POSTING_READ(D_STATE);
 570
 571         return 0;
 572 }
 573
 574 static int i965_reset_complete(struct drm_device *dev)
 575 {
 576         u8 gdrst;
 577         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 578         return gdrst & 0x1;
 579 }
 580
 581 static int i965_do_reset(struct drm_device *dev, u8 flags)
 582 {
 583         u8 gdrst;
 584
 585         /*
 586          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 587          * well as the reset bit (GR/bit 0).  Setting the GR bit
 588          * triggers the reset; when done, the hardware will clear it.
 589          */
 590         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 591         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 592
 593         return wait_for(i965_reset_complete(dev), 500);
 594 }
 595
 596 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 597 {
 598         struct drm_i915_private *dev_priv = dev->dev_private;
 599         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 600         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 601         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 602 }
 603
 604 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 605 {
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         int     ret;
 608         unsigned long irqflags;
 609
 610         /* Hold gt_lock across reset to prevent any register access
 611          * with forcewake not set correctly
 612          */
 613         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 614
 615         /* Reset the chip */
 616
 617         /* GEN6_GDRST is not in the gt power well, no need to check
 618          * for fifo space for the write or forcewake the chip for
 619          * the read
 620          */
 621         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 622
 623         /* Spin waiting for the device to ack the reset request */
 624         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 625
 626         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 627         if (dev_priv->forcewake_count)
 628                 dev_priv->display.force_wake_get(dev_priv);
 629         else
 630                 dev_priv->display.force_wake_put(dev_priv);
 631
 632         /* Restore fifo count */
 633         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 634
 635         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 636         return ret;
 637 }
 638
 639 /**
 640  * i915_reset - reset chip after a hang
 641  * @dev: drm device to reset
 642  * @flags: reset domains
 643  *
 644  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 645  * reset or otherwise an error code.
 646  *
 647  * Procedure is fairly simple:
 648  *   - reset the chip using the reset reg
 649  *   - re-init context state
 650  *   - re-init hardware status page
 651  *   - re-init ring buffer
 652  *   - re-init interrupt state
 653  *   - re-init display
 654  */
 655 int i915_reset(struct drm_device *dev, u8 flags)
 656 {
 657         drm_i915_private_t *dev_priv = dev->dev_private;
 658         /*
 659          * We really should only reset the display subsystem if we actually
 660          * need to
 661          */
 662         bool need_display = true;
 663         int ret;
 664
 665         if (!i915_try_reset)
 666                 return 0;
 667
 668         if (!mutex_trylock(&dev->struct_mutex))
 669                 return -EBUSY;
 670
 671         i915_gem_reset(dev);
 672
 673         ret = -ENODEV;
 674         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 675                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 676         } else switch (INTEL_INFO(dev)->gen) {
 677         case 7:
 678         case 6:
 679                 ret = gen6_do_reset(dev, flags);
 680                 break;
 681         case 5:
 682                 ret = ironlake_do_reset(dev, flags);
 683                 break;
 684         case 4:
 685                 ret = i965_do_reset(dev, flags);
 686                 break;
 687         case 2:
 688                 ret = i8xx_do_reset(dev, flags);
 689                 break;
 690         }
 691         dev_priv->last_gpu_reset = get_seconds();
 692         if (ret) {
 693                 DRM_ERROR("Failed to reset chip.\n");
 694                 mutex_unlock(&dev->struct_mutex);
 695                 return ret;
 696         }
 697
 698         /* Ok, now get things going again... */
 699
 700         /*
 701          * Everything depends on having the GTT running, so we need to start
 702          * there.  Fortunately we don't need to do this unless we reset the
 703          * chip at a PCI level.
 704          *
 705          * Next we need to restore the context, but we don't use those
 706          * yet either...
 707          *
 708          * Ring buffer needs to be re-initialized in the KMS case, or if X
 709          * was running at the time of the reset (i.e. we weren't VT
 710          * switched away).
 711          */
 712         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 713                         !dev_priv->mm.suspended) {
 714                 dev_priv->mm.suspended = 0;
 715
 716                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 717                 if (HAS_BSD(dev))
 718                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 719                 if (HAS_BLT(dev))
 720                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 721
 722                 mutex_unlock(&dev->struct_mutex);
 723                 drm_irq_uninstall(dev);
 724                 drm_mode_config_reset(dev);
 725                 drm_irq_install(dev);
 726                 mutex_lock(&dev->struct_mutex);
 727         }
 728
 729         mutex_unlock(&dev->struct_mutex);
 730
 731         /*
 732          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 733          * need to retrain the display link and cannot just restore the register
 734          * values.
 735          */
 736         if (need_display) {
 737                 mutex_lock(&dev->mode_config.mutex);
 738                 drm_helper_resume_force_mode(dev);
 739                 mutex_unlock(&dev->mode_config.mutex);
 740         }
 741
 742         return 0;
 743 }
 744
 745
 746 static int __devinit
 747 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 748 {
 749         /* Only bind to function 0 of the device. Early generations
 750          * used function 1 as a placeholder for multi-head. This causes
 751          * us confusion instead, especially on the systems where both
 752          * functions have the same PCI-ID!
 753          */
 754         if (PCI_FUNC(pdev->devfn))
 755                 return -ENODEV;
 756
 757         return drm_get_pci_dev(pdev, ent, &driver);
 758 }
 759
 760 static void
 761 i915_pci_remove(struct pci_dev *pdev)
 762 {
 763         struct drm_device *dev = pci_get_drvdata(pdev);
 764
 765         drm_put_dev(dev);
 766 }
 767
 768 static int i915_pm_suspend(struct device *dev)
 769 {
 770         struct pci_dev *pdev = to_pci_dev(dev);
 771         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 772         int error;
 773
 774         if (!drm_dev || !drm_dev->dev_private) {
 775                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 776                 return -ENODEV;
 777         }
 778
 779         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 780                 return 0;
 781
 782         error = i915_drm_freeze(drm_dev);
 783         if (error)
 784                 return error;
 785
 786         pci_disable_device(pdev);
 787         pci_set_power_state(pdev, PCI_D3hot);
 788
 789         return 0;
 790 }
 791
 792 static int i915_pm_resume(struct device *dev)
 793 {
 794         struct pci_dev *pdev = to_pci_dev(dev);
 795         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 796
 797         return i915_resume(drm_dev);
 798 }
 799
 800 static int i915_pm_freeze(struct device *dev)
 801 {
 802         struct pci_dev *pdev = to_pci_dev(dev);
 803         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 804
 805         if (!drm_dev || !drm_dev->dev_private) {
 806                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 807                 return -ENODEV;
 808         }
 809
 810         return i915_drm_freeze(drm_dev);
 811 }
 812
 813 static int i915_pm_thaw(struct device *dev)
 814 {
 815         struct pci_dev *pdev = to_pci_dev(dev);
 816         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 817
 818         return i915_drm_thaw(drm_dev);
 819 }
 820
 821 static int i915_pm_poweroff(struct device *dev)
 822 {
 823         struct pci_dev *pdev = to_pci_dev(dev);
 824         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 825
 826         return i915_drm_freeze(drm_dev);
 827 }
 828
 829 static const struct dev_pm_ops i915_pm_ops = {
 830         .suspend = i915_pm_suspend,
 831         .resume = i915_pm_resume,
 832         .freeze = i915_pm_freeze,
 833         .thaw = i915_pm_thaw,
 834         .poweroff = i915_pm_poweroff,
 835         .restore = i915_pm_resume,
 836 };
 837
 838 static struct vm_operations_struct i915_gem_vm_ops = {
 839         .fault = i915_gem_fault,
 840         .open = drm_gem_vm_open,
 841         .close = drm_gem_vm_close,
 842 };
 843
 844 static const struct file_operations i915_driver_fops = {
 845         .owner = THIS_MODULE,
 846         .open = drm_open,
 847         .release = drm_release,
 848         .unlocked_ioctl = drm_ioctl,
 849         .mmap = drm_gem_mmap,
 850         .poll = drm_poll,
 851         .fasync = drm_fasync,
 852         .read = drm_read,
 853 #ifdef CONFIG_COMPAT
 854         .compat_ioctl = i915_compat_ioctl,
 855 #endif
 856         .llseek = noop_llseek,
 857 };
 858
 859 static struct drm_driver driver = {
 860         /* Don't use MTRRs here; the Xserver or userspace app should
 861          * deal with them for Intel hardware.
 862          */
 863         .driver_features =
 864             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 865             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 866         .load = i915_driver_load,
 867         .unload = i915_driver_unload,
 868         .open = i915_driver_open,
 869         .lastclose = i915_driver_lastclose,
 870         .preclose = i915_driver_preclose,
 871         .postclose = i915_driver_postclose,
 872
 873         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 874         .suspend = i915_suspend,
 875         .resume = i915_resume,
 876
 877         .device_is_agp = i915_driver_device_is_agp,
 878         .reclaim_buffers = drm_core_reclaim_buffers,
 879         .master_create = i915_master_create,
 880         .master_destroy = i915_master_destroy,
 881 #if defined(CONFIG_DEBUG_FS)
 882         .debugfs_init = i915_debugfs_init,
 883         .debugfs_cleanup = i915_debugfs_cleanup,
 884 #endif
 885         .gem_init_object = i915_gem_init_object,
 886         .gem_free_object = i915_gem_free_object,
 887         .gem_vm_ops = &i915_gem_vm_ops,
 888         .dumb_create = i915_gem_dumb_create,
 889         .dumb_map_offset = i915_gem_mmap_gtt,
 890         .dumb_destroy = i915_gem_dumb_destroy,
 891         .ioctls = i915_ioctls,
 892         .fops = &i915_driver_fops,
 893         .name = DRIVER_NAME,
 894         .desc = DRIVER_DESC,
 895         .date = DRIVER_DATE,
 896         .major = DRIVER_MAJOR,
 897         .minor = DRIVER_MINOR,
 898         .patchlevel = DRIVER_PATCHLEVEL,
 899 };
 900
 901 static struct pci_driver i915_pci_driver = {
 902         .name = DRIVER_NAME,
 903         .id_table = pciidlist,
 904         .probe = i915_pci_probe,
 905         .remove = i915_pci_remove,
 906         .driver.pm = &i915_pm_ops,
 907 };
 908
 909 static int __init i915_init(void)
 910 {
 911         if (!intel_agp_enabled) {
 912                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 913                 return -ENODEV;
 914         }
 915
 916         driver.num_ioctls = i915_max_ioctl;
 917
 918         /*
 919          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 920          * explicitly disabled with the module pararmeter.
 921          *
 922          * Otherwise, just follow the parameter (defaulting to off).
 923          *
 924          * Allow optional vga_text_mode_force boot option to override
 925          * the default behavior.
 926          */
 927 #if defined(CONFIG_DRM_I915_KMS)
 928         if (i915_modeset != 0)
 929                 driver.driver_features |= DRIVER_MODESET;
 930 #endif
 931         if (i915_modeset == 1)
 932                 driver.driver_features |= DRIVER_MODESET;
 933
 934 #ifdef CONFIG_VGA_CONSOLE
 935         if (vgacon_text_force() && i915_modeset == -1)
 936                 driver.driver_features &= ~DRIVER_MODESET;
 937 #endif
 938
 939         if (!(driver.driver_features & DRIVER_MODESET))
 940                 driver.get_vblank_timestamp = NULL;
 941
 942         return drm_pci_init(&driver, &i915_pci_driver);
 943 }
 944
 945 static void __exit i915_exit(void)
 946 {
 947         drm_pci_exit(&driver, &i915_pci_driver);
 948 }
 949
 950 module_init(i915_init);
 951 module_exit(i915_exit);
 952
 953 MODULE_AUTHOR(DRIVER_AUTHOR);
 954 MODULE_DESCRIPTION(DRIVER_DESC);
 955 MODULE_LICENSE("GPL and additional rights");
 956
 957 #define __i915_read(x, y) \
 958 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 959         u##x val = 0; \
 960         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 961                 unsigned long irqflags; \
 962                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
 963                 if (dev_priv->forcewake_count == 0) \
 964                         dev_priv->display.force_wake_get(dev_priv); \
 965                 val = read##y(dev_priv->regs + reg); \
 966                 if (dev_priv->forcewake_count == 0) \
 967                         dev_priv->display.force_wake_put(dev_priv); \
 968                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
 969         } else { \
 970                 val = read##y(dev_priv->regs + reg); \
 971         } \
 972         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
 973         return val; \
 974 }
 975
 976 __i915_read(8, b)
 977 __i915_read(16, w)
 978 __i915_read(32, l)
 979 __i915_read(64, q)
 980 #undef __i915_read
 981
 982 #define __i915_write(x, y) \
 983 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 984         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 985         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 986                 __gen6_gt_wait_for_fifo(dev_priv); \
 987         } \
 988         write##y(val, dev_priv->regs + reg); \
 989 }
 990 __i915_write(8, b)
 991 __i915_write(16, w)
 992 __i915_write(32, l)
 993 __i915_write(64, q)
 994 #undef __i915_write