drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *kdev = dev_priv->drm.dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(kdev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev_priv)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = to_i915(dev);
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev_priv));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 182                                         IS_IVYBRIDGE(dev_priv)));
 183                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 184                                 /* PantherPoint is CPT compatible */
 185                                 dev_priv->pch_type = PCH_CPT;
 186                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 187                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 188                                         IS_IVYBRIDGE(dev_priv)));
 189                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 190                                 dev_priv->pch_type = PCH_LPT;
 191                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 192                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 193                                         !IS_BROADWELL(dev_priv));
 194                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 195                                         IS_BDW_ULT(dev_priv));
 196                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 197                                 dev_priv->pch_type = PCH_LPT;
 198                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 199                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 200                                         !IS_BROADWELL(dev_priv));
 201                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 202                                         !IS_BDW_ULT(dev_priv));
 203                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 204                                 dev_priv->pch_type = PCH_SPT;
 205                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 206                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 207                                         !IS_KABYLAKE(dev_priv));
 208                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 209                                 dev_priv->pch_type = PCH_SPT;
 210                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 211                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 212                                         !IS_KABYLAKE(dev_priv));
 213                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 214                                 dev_priv->pch_type = PCH_KBP;
 215                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 216                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 217                                         !IS_KABYLAKE(dev_priv));
 218                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 219                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 220                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 221                                     pch->subsystem_vendor ==
 222                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 223                                     pch->subsystem_device ==
 224                                             PCI_SUBDEVICE_ID_QEMU)) {
 225                                 dev_priv->pch_type =
 226                                         intel_virt_detect_pch(dev_priv);
 227                         } else
 228                                 continue;
 229
 230                         break;
 231                 }
 232         }
 233         if (!pch)
 234                 DRM_DEBUG_KMS("No PCH found.\n");
 235
 236         pci_dev_put(pch);
 237 }
 238
 239 static int i915_getparam(struct drm_device *dev, void *data,
 240                          struct drm_file *file_priv)
 241 {
 242         struct drm_i915_private *dev_priv = to_i915(dev);
 243         struct pci_dev *pdev = dev_priv->drm.pdev;
 244         drm_i915_getparam_t *param = data;
 245         int value;
 246
 247         switch (param->param) {
 248         case I915_PARAM_IRQ_ACTIVE:
 249         case I915_PARAM_ALLOW_BATCHBUFFER:
 250         case I915_PARAM_LAST_DISPATCH:
 251                 /* Reject all old ums/dri params. */
 252                 return -ENODEV;
 253         case I915_PARAM_CHIPSET_ID:
 254                 value = pdev->device;
 255                 break;
 256         case I915_PARAM_REVISION:
 257                 value = pdev->revision;
 258                 break;
 259         case I915_PARAM_NUM_FENCES_AVAIL:
 260                 value = dev_priv->num_fence_regs;
 261                 break;
 262         case I915_PARAM_HAS_OVERLAY:
 263                 value = dev_priv->overlay ? 1 : 0;
 264                 break;
 265         case I915_PARAM_HAS_BSD:
 266                 value = !!dev_priv->engine[VCS];
 267                 break;
 268         case I915_PARAM_HAS_BLT:
 269                 value = !!dev_priv->engine[BCS];
 270                 break;
 271         case I915_PARAM_HAS_VEBOX:
 272                 value = !!dev_priv->engine[VECS];
 273                 break;
 274         case I915_PARAM_HAS_BSD2:
 275                 value = !!dev_priv->engine[VCS2];
 276                 break;
 277         case I915_PARAM_HAS_EXEC_CONSTANTS:
 278                 value = INTEL_GEN(dev_priv) >= 4;
 279                 break;
 280         case I915_PARAM_HAS_LLC:
 281                 value = HAS_LLC(dev_priv);
 282                 break;
 283         case I915_PARAM_HAS_WT:
 284                 value = HAS_WT(dev_priv);
 285                 break;
 286         case I915_PARAM_HAS_ALIASING_PPGTT:
 287                 value = USES_PPGTT(dev_priv);
 288                 break;
 289         case I915_PARAM_HAS_SEMAPHORES:
 290                 value = i915.semaphores;
 291                 break;
 292         case I915_PARAM_HAS_SECURE_BATCHES:
 293                 value = capable(CAP_SYS_ADMIN);
 294                 break;
 295         case I915_PARAM_CMD_PARSER_VERSION:
 296                 value = i915_cmd_parser_get_version(dev_priv);
 297                 break;
 298         case I915_PARAM_SUBSLICE_TOTAL:
 299                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 300                 if (!value)
 301                         return -ENODEV;
 302                 break;
 303         case I915_PARAM_EU_TOTAL:
 304                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 305                 if (!value)
 306                         return -ENODEV;
 307                 break;
 308         case I915_PARAM_HAS_GPU_RESET:
 309                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 310                 break;
 311         case I915_PARAM_HAS_RESOURCE_STREAMER:
 312                 value = HAS_RESOURCE_STREAMER(dev_priv);
 313                 break;
 314         case I915_PARAM_HAS_POOLED_EU:
 315                 value = HAS_POOLED_EU(dev_priv);
 316                 break;
 317         case I915_PARAM_MIN_EU_IN_POOL:
 318                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 319                 break;
 320         case I915_PARAM_MMAP_GTT_VERSION:
 321                 /* Though we've started our numbering from 1, and so class all
 322                  * earlier versions as 0, in effect their value is undefined as
 323                  * the ioctl will report EINVAL for the unknown param!
 324                  */
 325                 value = i915_gem_mmap_gtt_version();
 326                 break;
 327         case I915_PARAM_HAS_SCHEDULER:
 328                 value = dev_priv->engine[RCS] &&
 329                         dev_priv->engine[RCS]->schedule;
 330                 break;
 331         case I915_PARAM_MMAP_VERSION:
 332                 /* Remember to bump this if the version changes! */
 333         case I915_PARAM_HAS_GEM:
 334         case I915_PARAM_HAS_PAGEFLIPPING:
 335         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 336         case I915_PARAM_HAS_RELAXED_FENCING:
 337         case I915_PARAM_HAS_COHERENT_RINGS:
 338         case I915_PARAM_HAS_RELAXED_DELTA:
 339         case I915_PARAM_HAS_GEN7_SOL_RESET:
 340         case I915_PARAM_HAS_WAIT_TIMEOUT:
 341         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 342         case I915_PARAM_HAS_PINNED_BATCHES:
 343         case I915_PARAM_HAS_EXEC_NO_RELOC:
 344         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 345         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 346         case I915_PARAM_HAS_EXEC_SOFTPIN:
 347                 /* For the time being all of these are always true;
 348                  * if some supported hardware does not have one of these
 349                  * features this value needs to be provided from
 350                  * INTEL_INFO(), a feature macro, or similar.
 351                  */
 352                 value = 1;
 353                 break;
 354         default:
 355                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 356                 return -EINVAL;
 357         }
 358
 359         if (put_user(value, param->value))
 360                 return -EFAULT;
 361
 362         return 0;
 363 }
 364
 365 static int i915_get_bridge_dev(struct drm_device *dev)
 366 {
 367         struct drm_i915_private *dev_priv = to_i915(dev);
 368
 369         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 370         if (!dev_priv->bridge_dev) {
 371                 DRM_ERROR("bridge device not found\n");
 372                 return -1;
 373         }
 374         return 0;
 375 }
 376
 377 /* Allocate space for the MCH regs if needed, return nonzero on error */
 378 static int
 379 intel_alloc_mchbar_resource(struct drm_device *dev)
 380 {
 381         struct drm_i915_private *dev_priv = to_i915(dev);
 382         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 383         u32 temp_lo, temp_hi = 0;
 384         u64 mchbar_addr;
 385         int ret;
 386
 387         if (INTEL_GEN(dev_priv) >= 4)
 388                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 389         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 390         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 391
 392         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 393 #ifdef CONFIG_PNP
 394         if (mchbar_addr &&
 395             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 396                 return 0;
 397 #endif
 398
 399         /* Get some space for it */
 400         dev_priv->mch_res.name = "i915 MCHBAR";
 401         dev_priv->mch_res.flags = IORESOURCE_MEM;
 402         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 403                                      &dev_priv->mch_res,
 404                                      MCHBAR_SIZE, MCHBAR_SIZE,
 405                                      PCIBIOS_MIN_MEM,
 406                                      0, pcibios_align_resource,
 407                                      dev_priv->bridge_dev);
 408         if (ret) {
 409                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 410                 dev_priv->mch_res.start = 0;
 411                 return ret;
 412         }
 413
 414         if (INTEL_GEN(dev_priv) >= 4)
 415                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 416                                        upper_32_bits(dev_priv->mch_res.start));
 417
 418         pci_write_config_dword(dev_priv->bridge_dev, reg,
 419                                lower_32_bits(dev_priv->mch_res.start));
 420         return 0;
 421 }
 422
 423 /* Setup MCHBAR if possible, return true if we should disable it again */
 424 static void
 425 intel_setup_mchbar(struct drm_device *dev)
 426 {
 427         struct drm_i915_private *dev_priv = to_i915(dev);
 428         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 429         u32 temp;
 430         bool enabled;
 431
 432         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 433                 return;
 434
 435         dev_priv->mchbar_need_disable = false;
 436
 437         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 438                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 439                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 440         } else {
 441                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 442                 enabled = temp & 1;
 443         }
 444
 445         /* If it's already enabled, don't have to do anything */
 446         if (enabled)
 447                 return;
 448
 449         if (intel_alloc_mchbar_resource(dev))
 450                 return;
 451
 452         dev_priv->mchbar_need_disable = true;
 453
 454         /* Space is allocated or reserved, so enable it. */
 455         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 456                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 457                                        temp | DEVEN_MCHBAR_EN);
 458         } else {
 459                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 460                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 461         }
 462 }
 463
 464 static void
 465 intel_teardown_mchbar(struct drm_device *dev)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(dev);
 468         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 469
 470         if (dev_priv->mchbar_need_disable) {
 471                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 472                         u32 deven_val;
 473
 474                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 475                                               &deven_val);
 476                         deven_val &= ~DEVEN_MCHBAR_EN;
 477                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 478                                                deven_val);
 479                 } else {
 480                         u32 mchbar_val;
 481
 482                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 483                                               &mchbar_val);
 484                         mchbar_val &= ~1;
 485                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 486                                                mchbar_val);
 487                 }
 488         }
 489
 490         if (dev_priv->mch_res.start)
 491                 release_resource(&dev_priv->mch_res);
 492 }
 493
 494 /* true = enable decode, false = disable decoder */
 495 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 496 {
 497         struct drm_device *dev = cookie;
 498
 499         intel_modeset_vga_set_state(to_i915(dev), state);
 500         if (state)
 501                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 502                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 503         else
 504                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 505 }
 506
 507 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 508 {
 509         struct drm_device *dev = pci_get_drvdata(pdev);
 510         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 511
 512         if (state == VGA_SWITCHEROO_ON) {
 513                 pr_info("switched on\n");
 514                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 515                 /* i915 resume handler doesn't set to D0 */
 516                 pci_set_power_state(pdev, PCI_D0);
 517                 i915_resume_switcheroo(dev);
 518                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 519         } else {
 520                 pr_info("switched off\n");
 521                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 522                 i915_suspend_switcheroo(dev, pmm);
 523                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 524         }
 525 }
 526
 527 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 528 {
 529         struct drm_device *dev = pci_get_drvdata(pdev);
 530
 531         /*
 532          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 533          * locking inversion with the driver load path. And the access here is
 534          * completely racy anyway. So don't bother with locking for now.
 535          */
 536         return dev->open_count == 0;
 537 }
 538
 539 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 540         .set_gpu_state = i915_switcheroo_set_state,
 541         .reprobe = NULL,
 542         .can_switch = i915_switcheroo_can_switch,
 543 };
 544
 545 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 546 {
 547         mutex_lock(&dev_priv->drm.struct_mutex);
 548         i915_gem_cleanup_engines(&dev_priv->drm);
 549         i915_gem_context_fini(&dev_priv->drm);
 550         mutex_unlock(&dev_priv->drm.struct_mutex);
 551
 552         rcu_barrier();
 553         flush_work(&dev_priv->mm.free_work);
 554
 555         WARN_ON(!list_empty(&dev_priv->context_list));
 556 }
 557
 558 static int i915_load_modeset_init(struct drm_device *dev)
 559 {
 560         struct drm_i915_private *dev_priv = to_i915(dev);
 561         struct pci_dev *pdev = dev_priv->drm.pdev;
 562         int ret;
 563
 564         if (i915_inject_load_failure())
 565                 return -ENODEV;
 566
 567         ret = intel_bios_init(dev_priv);
 568         if (ret)
 569                 DRM_INFO("failed to find VBIOS tables\n");
 570
 571         /* If we have > 1 VGA cards, then we need to arbitrate access
 572          * to the common VGA resources.
 573          *
 574          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 575          * then we do not take part in VGA arbitration and the
 576          * vga_client_register() fails with -ENODEV.
 577          */
 578         ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
 579         if (ret && ret != -ENODEV)
 580                 goto out;
 581
 582         intel_register_dsm_handler();
 583
 584         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 585         if (ret)
 586                 goto cleanup_vga_client;
 587
 588         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 589         intel_update_rawclk(dev_priv);
 590
 591         intel_power_domains_init_hw(dev_priv, false);
 592
 593         intel_csr_ucode_init(dev_priv);
 594
 595         ret = intel_irq_install(dev_priv);
 596         if (ret)
 597                 goto cleanup_csr;
 598
 599         intel_setup_gmbus(dev);
 600
 601         /* Important: The output setup functions called by modeset_init need
 602          * working irqs for e.g. gmbus and dp aux transfers. */
 603         ret = intel_modeset_init(dev);
 604         if (ret)
 605                 goto cleanup_irq;
 606
 607         intel_guc_init(dev);
 608
 609         ret = i915_gem_init(dev);
 610         if (ret)
 611                 goto cleanup_irq;
 612
 613         intel_modeset_gem_init(dev);
 614
 615         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 616                 return 0;
 617
 618         ret = intel_fbdev_init(dev);
 619         if (ret)
 620                 goto cleanup_gem;
 621
 622         /* Only enable hotplug handling once the fbdev is fully set up. */
 623         intel_hpd_init(dev_priv);
 624
 625         drm_kms_helper_poll_init(dev);
 626
 627         return 0;
 628
 629 cleanup_gem:
 630         if (i915_gem_suspend(dev))
 631                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 632         i915_gem_fini(dev_priv);
 633 cleanup_irq:
 634         intel_guc_fini(dev);
 635         drm_irq_uninstall(dev);
 636         intel_teardown_gmbus(dev);
 637 cleanup_csr:
 638         intel_csr_ucode_fini(dev_priv);
 639         intel_power_domains_fini(dev_priv);
 640         vga_switcheroo_unregister_client(pdev);
 641 cleanup_vga_client:
 642         vga_client_register(pdev, NULL, NULL, NULL);
 643 out:
 644         return ret;
 645 }
 646
 647 #if IS_ENABLED(CONFIG_FB)
 648 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 649 {
 650         struct apertures_struct *ap;
 651         struct pci_dev *pdev = dev_priv->drm.pdev;
 652         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 653         bool primary;
 654         int ret;
 655
 656         ap = alloc_apertures(1);
 657         if (!ap)
 658                 return -ENOMEM;
 659
 660         ap->ranges[0].base = ggtt->mappable_base;
 661         ap->ranges[0].size = ggtt->mappable_end;
 662
 663         primary =
 664                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 665
 666         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 667
 668         kfree(ap);
 669
 670         return ret;
 671 }
 672 #else
 673 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 674 {
 675         return 0;
 676 }
 677 #endif
 678
 679 #if !defined(CONFIG_VGA_CONSOLE)
 680 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 681 {
 682         return 0;
 683 }
 684 #elif !defined(CONFIG_DUMMY_CONSOLE)
 685 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 686 {
 687         return -ENODEV;
 688 }
 689 #else
 690 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 691 {
 692         int ret = 0;
 693
 694         DRM_INFO("Replacing VGA console driver\n");
 695
 696         console_lock();
 697         if (con_is_bound(&vga_con))
 698                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 699         if (ret == 0) {
 700                 ret = do_unregister_con_driver(&vga_con);
 701
 702                 /* Ignore "already unregistered". */
 703                 if (ret == -ENODEV)
 704                         ret = 0;
 705         }
 706         console_unlock();
 707
 708         return ret;
 709 }
 710 #endif
 711
 712 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 713 {
 714         /*
 715          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 716          * CHV x1 PHY (DP/HDMI D)
 717          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 718          */
 719         if (IS_CHERRYVIEW(dev_priv)) {
 720                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 721                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 722         } else if (IS_VALLEYVIEW(dev_priv)) {
 723                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 724         }
 725 }
 726
 727 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 728 {
 729         /*
 730          * The i915 workqueue is primarily used for batched retirement of
 731          * requests (and thus managing bo) once the task has been completed
 732          * by the GPU. i915_gem_retire_requests() is called directly when we
 733          * need high-priority retirement, such as waiting for an explicit
 734          * bo.
 735          *
 736          * It is also used for periodic low-priority events, such as
 737          * idle-timers and recording error state.
 738          *
 739          * All tasks on the workqueue are expected to acquire the dev mutex
 740          * so there is no point in running more than one instance of the
 741          * workqueue at any time.  Use an ordered one.
 742          */
 743         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 744         if (dev_priv->wq == NULL)
 745                 goto out_err;
 746
 747         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 748         if (dev_priv->hotplug.dp_wq == NULL)
 749                 goto out_free_wq;
 750
 751         return 0;
 752
 753 out_free_wq:
 754         destroy_workqueue(dev_priv->wq);
 755 out_err:
 756         DRM_ERROR("Failed to allocate workqueues.\n");
 757
 758         return -ENOMEM;
 759 }
 760
 761 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 762 {
 763         destroy_workqueue(dev_priv->hotplug.dp_wq);
 764         destroy_workqueue(dev_priv->wq);
 765 }
 766
 767 /*
 768  * We don't keep the workarounds for pre-production hardware, so we expect our
 769  * driver to fail on these machines in one way or another. A little warning on
 770  * dmesg may help both the user and the bug triagers.
 771  */
 772 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 773 {
 774         if (IS_HSW_EARLY_SDV(dev_priv) ||
 775             IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
 776                 DRM_ERROR("This is a pre-production stepping. "
 777                           "It may not be fully functional.\n");
 778 }
 779
 780 /**
 781  * i915_driver_init_early - setup state not requiring device access
 782  * @dev_priv: device private
 783  *
 784  * Initialize everything that is a "SW-only" state, that is state not
 785  * requiring accessing the device or exposing the driver via kernel internal
 786  * or userspace interfaces. Example steps belonging here: lock initialization,
 787  * system memory allocation, setting up device specific attributes and
 788  * function hooks not requiring accessing the device.
 789  */
 790 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 791                                   const struct pci_device_id *ent)
 792 {
 793         const struct intel_device_info *match_info =
 794                 (struct intel_device_info *)ent->driver_data;
 795         struct intel_device_info *device_info;
 796         int ret = 0;
 797
 798         if (i915_inject_load_failure())
 799                 return -ENODEV;
 800
 801         /* Setup the write-once "constant" device info */
 802         device_info = mkwrite_device_info(dev_priv);
 803         memcpy(device_info, match_info, sizeof(*device_info));
 804         device_info->device_id = dev_priv->drm.pdev->device;
 805
 806         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 807         device_info->gen_mask = BIT(device_info->gen - 1);
 808
 809         spin_lock_init(&dev_priv->irq_lock);
 810         spin_lock_init(&dev_priv->gpu_error.lock);
 811         mutex_init(&dev_priv->backlight_lock);
 812         spin_lock_init(&dev_priv->uncore.lock);
 813         spin_lock_init(&dev_priv->mm.object_stat_lock);
 814         spin_lock_init(&dev_priv->mmio_flip_lock);
 815         mutex_init(&dev_priv->sb_lock);
 816         mutex_init(&dev_priv->modeset_restore_lock);
 817         mutex_init(&dev_priv->av_mutex);
 818         mutex_init(&dev_priv->wm.wm_mutex);
 819         mutex_init(&dev_priv->pps_mutex);
 820
 821         i915_memcpy_init_early(dev_priv);
 822
 823         ret = i915_workqueues_init(dev_priv);
 824         if (ret < 0)
 825                 return ret;
 826
 827         ret = intel_gvt_init(dev_priv);
 828         if (ret < 0)
 829                 goto err_workqueues;
 830
 831         /* This must be called before any calls to HAS_PCH_* */
 832         intel_detect_pch(&dev_priv->drm);
 833
 834         intel_pm_setup(&dev_priv->drm);
 835         intel_init_dpio(dev_priv);
 836         intel_power_domains_init(dev_priv);
 837         intel_irq_init(dev_priv);
 838         intel_hangcheck_init(dev_priv);
 839         intel_init_display_hooks(dev_priv);
 840         intel_init_clock_gating_hooks(dev_priv);
 841         intel_init_audio_hooks(dev_priv);
 842         ret = i915_gem_load_init(&dev_priv->drm);
 843         if (ret < 0)
 844                 goto err_gvt;
 845
 846         intel_display_crc_init(dev_priv);
 847
 848         intel_device_info_dump(dev_priv);
 849
 850         intel_detect_preproduction_hw(dev_priv);
 851
 852         return 0;
 853
 854 err_gvt:
 855         intel_gvt_cleanup(dev_priv);
 856 err_workqueues:
 857         i915_workqueues_cleanup(dev_priv);
 858         return ret;
 859 }
 860
 861 /**
 862  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 863  * @dev_priv: device private
 864  */
 865 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 866 {
 867         i915_gem_load_cleanup(&dev_priv->drm);
 868         i915_workqueues_cleanup(dev_priv);
 869 }
 870
 871 static int i915_mmio_setup(struct drm_device *dev)
 872 {
 873         struct drm_i915_private *dev_priv = to_i915(dev);
 874         struct pci_dev *pdev = dev_priv->drm.pdev;
 875         int mmio_bar;
 876         int mmio_size;
 877
 878         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 879         /*
 880          * Before gen4, the registers and the GTT are behind different BARs.
 881          * However, from gen4 onwards, the registers and the GTT are shared
 882          * in the same BAR, so we want to restrict this ioremap from
 883          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 884          * the register BAR remains the same size for all the earlier
 885          * generations up to Ironlake.
 886          */
 887         if (INTEL_GEN(dev_priv) < 5)
 888                 mmio_size = 512 * 1024;
 889         else
 890                 mmio_size = 2 * 1024 * 1024;
 891         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 892         if (dev_priv->regs == NULL) {
 893                 DRM_ERROR("failed to map registers\n");
 894
 895                 return -EIO;
 896         }
 897
 898         /* Try to make sure MCHBAR is enabled before poking at it */
 899         intel_setup_mchbar(dev);
 900
 901         return 0;
 902 }
 903
 904 static void i915_mmio_cleanup(struct drm_device *dev)
 905 {
 906         struct drm_i915_private *dev_priv = to_i915(dev);
 907         struct pci_dev *pdev = dev_priv->drm.pdev;
 908
 909         intel_teardown_mchbar(dev);
 910         pci_iounmap(pdev, dev_priv->regs);
 911 }
 912
 913 /**
 914  * i915_driver_init_mmio - setup device MMIO
 915  * @dev_priv: device private
 916  *
 917  * Setup minimal device state necessary for MMIO accesses later in the
 918  * initialization sequence. The setup here should avoid any other device-wide
 919  * side effects or exposing the driver via kernel internal or user space
 920  * interfaces.
 921  */
 922 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 923 {
 924         struct drm_device *dev = &dev_priv->drm;
 925         int ret;
 926
 927         if (i915_inject_load_failure())
 928                 return -ENODEV;
 929
 930         if (i915_get_bridge_dev(dev))
 931                 return -EIO;
 932
 933         ret = i915_mmio_setup(dev);
 934         if (ret < 0)
 935                 goto put_bridge;
 936
 937         intel_uncore_init(dev_priv);
 938
 939         return 0;
 940
 941 put_bridge:
 942         pci_dev_put(dev_priv->bridge_dev);
 943
 944         return ret;
 945 }
 946
 947 /**
 948  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 949  * @dev_priv: device private
 950  */
 951 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 952 {
 953         struct drm_device *dev = &dev_priv->drm;
 954
 955         intel_uncore_fini(dev_priv);
 956         i915_mmio_cleanup(dev);
 957         pci_dev_put(dev_priv->bridge_dev);
 958 }
 959
 960 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 961 {
 962         i915.enable_execlists =
 963                 intel_sanitize_enable_execlists(dev_priv,
 964                                                 i915.enable_execlists);
 965
 966         /*
 967          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 968          * user's requested state against the hardware/driver capabilities.  We
 969          * do this now so that we can print out any log messages once rather
 970          * than every time we check intel_enable_ppgtt().
 971          */
 972         i915.enable_ppgtt =
 973                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 974         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 975
 976         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 977         DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 978 }
 979
 980 /**
 981  * i915_driver_init_hw - setup state requiring device access
 982  * @dev_priv: device private
 983  *
 984  * Setup state that requires accessing the device, but doesn't require
 985  * exposing the driver via kernel internal or userspace interfaces.
 986  */
 987 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 988 {
 989         struct pci_dev *pdev = dev_priv->drm.pdev;
 990         int ret;
 991
 992         if (i915_inject_load_failure())
 993                 return -ENODEV;
 994
 995         intel_device_info_runtime_init(dev_priv);
 996
 997         intel_sanitize_options(dev_priv);
 998
 999         ret = i915_ggtt_probe_hw(dev_priv);
1000         if (ret)
1001                 return ret;
1002
1003         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1004          * otherwise the vga fbdev driver falls over. */
1005         ret = i915_kick_out_firmware_fb(dev_priv);
1006         if (ret) {
1007                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1008                 goto out_ggtt;
1009         }
1010
1011         ret = i915_kick_out_vgacon(dev_priv);
1012         if (ret) {
1013                 DRM_ERROR("failed to remove conflicting VGA console\n");
1014                 goto out_ggtt;
1015         }
1016
1017         ret = i915_ggtt_init_hw(dev_priv);
1018         if (ret)
1019                 return ret;
1020
1021         ret = i915_ggtt_enable_hw(dev_priv);
1022         if (ret) {
1023                 DRM_ERROR("failed to enable GGTT\n");
1024                 goto out_ggtt;
1025         }
1026
1027         pci_set_master(pdev);
1028
1029         /* overlay on gen2 is broken and can't address above 1G */
1030         if (IS_GEN2(dev_priv)) {
1031                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1032                 if (ret) {
1033                         DRM_ERROR("failed to set DMA mask\n");
1034
1035                         goto out_ggtt;
1036                 }
1037         }
1038
1039         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1040          * using 32bit addressing, overwriting memory if HWS is located
1041          * above 4GB.
1042          *
1043          * The documentation also mentions an issue with undefined
1044          * behaviour if any general state is accessed within a page above 4GB,
1045          * which also needs to be handled carefully.
1046          */
1047         if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) {
1048                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1049
1050                 if (ret) {
1051                         DRM_ERROR("failed to set DMA mask\n");
1052
1053                         goto out_ggtt;
1054                 }
1055         }
1056
1057         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1058                            PM_QOS_DEFAULT_VALUE);
1059
1060         intel_uncore_sanitize(dev_priv);
1061
1062         intel_opregion_setup(dev_priv);
1063
1064         i915_gem_load_init_fences(dev_priv);
1065
1066         /* On the 945G/GM, the chipset reports the MSI capability on the
1067          * integrated graphics even though the support isn't actually there
1068          * according to the published specs.  It doesn't appear to function
1069          * correctly in testing on 945G.
1070          * This may be a side effect of MSI having been made available for PEG
1071          * and the registers being closely associated.
1072          *
1073          * According to chipset errata, on the 965GM, MSI interrupts may
1074          * be lost or delayed, but we use them anyways to avoid
1075          * stuck interrupts on some machines.
1076          */
1077         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1078                 if (pci_enable_msi(pdev) < 0)
1079                         DRM_DEBUG_DRIVER("can't enable MSI");
1080         }
1081
1082         return 0;
1083
1084 out_ggtt:
1085         i915_ggtt_cleanup_hw(dev_priv);
1086
1087         return ret;
1088 }
1089
1090 /**
1091  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1092  * @dev_priv: device private
1093  */
1094 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1095 {
1096         struct pci_dev *pdev = dev_priv->drm.pdev;
1097
1098         if (pdev->msi_enabled)
1099                 pci_disable_msi(pdev);
1100
1101         pm_qos_remove_request(&dev_priv->pm_qos);
1102         i915_ggtt_cleanup_hw(dev_priv);
1103 }
1104
1105 /**
1106  * i915_driver_register - register the driver with the rest of the system
1107  * @dev_priv: device private
1108  *
1109  * Perform any steps necessary to make the driver available via kernel
1110  * internal or userspace interfaces.
1111  */
1112 static void i915_driver_register(struct drm_i915_private *dev_priv)
1113 {
1114         struct drm_device *dev = &dev_priv->drm;
1115
1116         i915_gem_shrinker_init(dev_priv);
1117
1118         /*
1119          * Notify a valid surface after modesetting,
1120          * when running inside a VM.
1121          */
1122         if (intel_vgpu_active(dev_priv))
1123                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1124
1125         /* Reveal our presence to userspace */
1126         if (drm_dev_register(dev, 0) == 0) {
1127                 i915_debugfs_register(dev_priv);
1128                 i915_guc_register(dev_priv);
1129                 i915_setup_sysfs(dev_priv);
1130         } else
1131                 DRM_ERROR("Failed to register driver for userspace access!\n");
1132
1133         if (INTEL_INFO(dev_priv)->num_pipes) {
1134                 /* Must be done after probing outputs */
1135                 intel_opregion_register(dev_priv);
1136                 acpi_video_register();
1137         }
1138
1139         if (IS_GEN5(dev_priv))
1140                 intel_gpu_ips_init(dev_priv);
1141
1142         i915_audio_component_init(dev_priv);
1143
1144         /*
1145          * Some ports require correctly set-up hpd registers for detection to
1146          * work properly (leading to ghost connected connector status), e.g. VGA
1147          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1148          * irqs are fully enabled. We do it last so that the async config
1149          * cannot run before the connectors are registered.
1150          */
1151         intel_fbdev_initial_config_async(dev);
1152 }
1153
1154 /**
1155  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1156  * @dev_priv: device private
1157  */
1158 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1159 {
1160         i915_audio_component_cleanup(dev_priv);
1161
1162         intel_gpu_ips_teardown();
1163         acpi_video_unregister();
1164         intel_opregion_unregister(dev_priv);
1165
1166         i915_teardown_sysfs(dev_priv);
1167         i915_guc_unregister(dev_priv);
1168         i915_debugfs_unregister(dev_priv);
1169         drm_dev_unregister(&dev_priv->drm);
1170
1171         i915_gem_shrinker_cleanup(dev_priv);
1172 }
1173
1174 /**
1175  * i915_driver_load - setup chip and create an initial config
1176  * @pdev: PCI device
1177  * @ent: matching PCI ID entry
1178  *
1179  * The driver load routine has to do several things:
1180  *   - drive output discovery via intel_modeset_init()
1181  *   - initialize the memory manager
1182  *   - allocate initial config memory
1183  *   - setup the DRM framebuffer with the allocated memory
1184  */
1185 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1186 {
1187         struct drm_i915_private *dev_priv;
1188         int ret;
1189
1190         if (i915.nuclear_pageflip)
1191                 driver.driver_features |= DRIVER_ATOMIC;
1192
1193         ret = -ENOMEM;
1194         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1195         if (dev_priv)
1196                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1197         if (ret) {
1198                 dev_printk(KERN_ERR, &pdev->dev,
1199                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1200                 kfree(dev_priv);
1201                 return ret;
1202         }
1203
1204         dev_priv->drm.pdev = pdev;
1205         dev_priv->drm.dev_private = dev_priv;
1206
1207         ret = pci_enable_device(pdev);
1208         if (ret)
1209                 goto out_free_priv;
1210
1211         pci_set_drvdata(pdev, &dev_priv->drm);
1212
1213         ret = i915_driver_init_early(dev_priv, ent);
1214         if (ret < 0)
1215                 goto out_pci_disable;
1216
1217         intel_runtime_pm_get(dev_priv);
1218
1219         ret = i915_driver_init_mmio(dev_priv);
1220         if (ret < 0)
1221                 goto out_runtime_pm_put;
1222
1223         ret = i915_driver_init_hw(dev_priv);
1224         if (ret < 0)
1225                 goto out_cleanup_mmio;
1226
1227         /*
1228          * TODO: move the vblank init and parts of modeset init steps into one
1229          * of the i915_driver_init_/i915_driver_register functions according
1230          * to the role/effect of the given init step.
1231          */
1232         if (INTEL_INFO(dev_priv)->num_pipes) {
1233                 ret = drm_vblank_init(&dev_priv->drm,
1234                                       INTEL_INFO(dev_priv)->num_pipes);
1235                 if (ret)
1236                         goto out_cleanup_hw;
1237         }
1238
1239         ret = i915_load_modeset_init(&dev_priv->drm);
1240         if (ret < 0)
1241                 goto out_cleanup_vblank;
1242
1243         i915_driver_register(dev_priv);
1244
1245         intel_runtime_pm_enable(dev_priv);
1246
1247         /* Everything is in place, we can now relax! */
1248         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1249                  driver.name, driver.major, driver.minor, driver.patchlevel,
1250                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1251         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1252                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1253         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1254                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1255
1256         intel_runtime_pm_put(dev_priv);
1257
1258         return 0;
1259
1260 out_cleanup_vblank:
1261         drm_vblank_cleanup(&dev_priv->drm);
1262 out_cleanup_hw:
1263         i915_driver_cleanup_hw(dev_priv);
1264 out_cleanup_mmio:
1265         i915_driver_cleanup_mmio(dev_priv);
1266 out_runtime_pm_put:
1267         intel_runtime_pm_put(dev_priv);
1268         i915_driver_cleanup_early(dev_priv);
1269 out_pci_disable:
1270         pci_disable_device(pdev);
1271 out_free_priv:
1272         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1273         drm_dev_unref(&dev_priv->drm);
1274         return ret;
1275 }
1276
1277 void i915_driver_unload(struct drm_device *dev)
1278 {
1279         struct drm_i915_private *dev_priv = to_i915(dev);
1280         struct pci_dev *pdev = dev_priv->drm.pdev;
1281
1282         intel_fbdev_fini(dev);
1283
1284         if (i915_gem_suspend(dev))
1285                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1286
1287         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1288
1289         i915_driver_unregister(dev_priv);
1290
1291         drm_vblank_cleanup(dev);
1292
1293         intel_modeset_cleanup(dev);
1294
1295         /*
1296          * free the memory space allocated for the child device
1297          * config parsed from VBT
1298          */
1299         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1300                 kfree(dev_priv->vbt.child_dev);
1301                 dev_priv->vbt.child_dev = NULL;
1302                 dev_priv->vbt.child_dev_num = 0;
1303         }
1304         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1305         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1306         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1307         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1308
1309         vga_switcheroo_unregister_client(pdev);
1310         vga_client_register(pdev, NULL, NULL, NULL);
1311
1312         intel_csr_ucode_fini(dev_priv);
1313
1314         /* Free error state after interrupts are fully disabled. */
1315         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1316         i915_destroy_error_state(dev);
1317
1318         /* Flush any outstanding unpin_work. */
1319         drain_workqueue(dev_priv->wq);
1320
1321         intel_guc_fini(dev);
1322         i915_gem_fini(dev_priv);
1323         intel_fbc_cleanup_cfb(dev_priv);
1324
1325         intel_power_domains_fini(dev_priv);
1326
1327         i915_driver_cleanup_hw(dev_priv);
1328         i915_driver_cleanup_mmio(dev_priv);
1329
1330         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1331
1332         i915_driver_cleanup_early(dev_priv);
1333 }
1334
1335 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1336 {
1337         int ret;
1338
1339         ret = i915_gem_open(dev, file);
1340         if (ret)
1341                 return ret;
1342
1343         return 0;
1344 }
1345
1346 /**
1347  * i915_driver_lastclose - clean up after all DRM clients have exited
1348  * @dev: DRM device
1349  *
1350  * Take care of cleaning up after all DRM clients have exited.  In the
1351  * mode setting case, we want to restore the kernel's initial mode (just
1352  * in case the last client left us in a bad state).
1353  *
1354  * Additionally, in the non-mode setting case, we'll tear down the GTT
1355  * and DMA structures, since the kernel won't be using them, and clea
1356  * up any GEM state.
1357  */
1358 static void i915_driver_lastclose(struct drm_device *dev)
1359 {
1360         intel_fbdev_restore_mode(dev);
1361         vga_switcheroo_process_delayed_switch();
1362 }
1363
1364 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1365 {
1366         mutex_lock(&dev->struct_mutex);
1367         i915_gem_context_close(dev, file);
1368         i915_gem_release(dev, file);
1369         mutex_unlock(&dev->struct_mutex);
1370 }
1371
1372 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1373 {
1374         struct drm_i915_file_private *file_priv = file->driver_priv;
1375
1376         kfree(file_priv);
1377 }
1378
1379 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1380 {
1381         struct drm_device *dev = &dev_priv->drm;
1382         struct intel_encoder *encoder;
1383
1384         drm_modeset_lock_all(dev);
1385         for_each_intel_encoder(dev, encoder)
1386                 if (encoder->suspend)
1387                         encoder->suspend(encoder);
1388         drm_modeset_unlock_all(dev);
1389 }
1390
1391 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1392                               bool rpm_resume);
1393 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1394
1395 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1396 {
1397 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1398         if (acpi_target_system_state() < ACPI_STATE_S3)
1399                 return true;
1400 #endif
1401         return false;
1402 }
1403
1404 static int i915_drm_suspend(struct drm_device *dev)
1405 {
1406         struct drm_i915_private *dev_priv = to_i915(dev);
1407         struct pci_dev *pdev = dev_priv->drm.pdev;
1408         pci_power_t opregion_target_state;
1409         int error;
1410
1411         /* ignore lid events during suspend */
1412         mutex_lock(&dev_priv->modeset_restore_lock);
1413         dev_priv->modeset_restore = MODESET_SUSPENDED;
1414         mutex_unlock(&dev_priv->modeset_restore_lock);
1415
1416         disable_rpm_wakeref_asserts(dev_priv);
1417
1418         /* We do a lot of poking in a lot of registers, make sure they work
1419          * properly. */
1420         intel_display_set_init_power(dev_priv, true);
1421
1422         drm_kms_helper_poll_disable(dev);
1423
1424         pci_save_state(pdev);
1425
1426         error = i915_gem_suspend(dev);
1427         if (error) {
1428                 dev_err(&pdev->dev,
1429                         "GEM idle failed, resume might fail\n");
1430                 goto out;
1431         }
1432
1433         intel_guc_suspend(dev);
1434
1435         intel_display_suspend(dev);
1436
1437         intel_dp_mst_suspend(dev);
1438
1439         intel_runtime_pm_disable_interrupts(dev_priv);
1440         intel_hpd_cancel_work(dev_priv);
1441
1442         intel_suspend_encoders(dev_priv);
1443
1444         intel_suspend_hw(dev_priv);
1445
1446         i915_gem_suspend_gtt_mappings(dev_priv);
1447
1448         i915_save_state(dev);
1449
1450         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1451         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1452
1453         intel_uncore_forcewake_reset(dev_priv, false);
1454         intel_opregion_unregister(dev_priv);
1455
1456         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1457
1458         dev_priv->suspend_count++;
1459
1460         intel_csr_ucode_suspend(dev_priv);
1461
1462 out:
1463         enable_rpm_wakeref_asserts(dev_priv);
1464
1465         return error;
1466 }
1467
1468 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1469 {
1470         struct drm_i915_private *dev_priv = to_i915(dev);
1471         struct pci_dev *pdev = dev_priv->drm.pdev;
1472         bool fw_csr;
1473         int ret;
1474
1475         disable_rpm_wakeref_asserts(dev_priv);
1476
1477         intel_display_set_init_power(dev_priv, false);
1478
1479         fw_csr = !IS_BROXTON(dev_priv) &&
1480                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1481         /*
1482          * In case of firmware assisted context save/restore don't manually
1483          * deinit the power domains. This also means the CSR/DMC firmware will
1484          * stay active, it will power down any HW resources as required and
1485          * also enable deeper system power states that would be blocked if the
1486          * firmware was inactive.
1487          */
1488         if (!fw_csr)
1489                 intel_power_domains_suspend(dev_priv);
1490
1491         ret = 0;
1492         if (IS_BROXTON(dev_priv))
1493                 bxt_enable_dc9(dev_priv);
1494         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1495                 hsw_enable_pc8(dev_priv);
1496         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1497                 ret = vlv_suspend_complete(dev_priv);
1498
1499         if (ret) {
1500                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1501                 if (!fw_csr)
1502                         intel_power_domains_init_hw(dev_priv, true);
1503
1504                 goto out;
1505         }
1506
1507         pci_disable_device(pdev);
1508         /*
1509          * During hibernation on some platforms the BIOS may try to access
1510          * the device even though it's already in D3 and hang the machine. So
1511          * leave the device in D0 on those platforms and hope the BIOS will
1512          * power down the device properly. The issue was seen on multiple old
1513          * GENs with different BIOS vendors, so having an explicit blacklist
1514          * is inpractical; apply the workaround on everything pre GEN6. The
1515          * platforms where the issue was seen:
1516          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1517          * Fujitsu FSC S7110
1518          * Acer Aspire 1830T
1519          */
1520         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1521                 pci_set_power_state(pdev, PCI_D3hot);
1522
1523         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1524
1525 out:
1526         enable_rpm_wakeref_asserts(dev_priv);
1527
1528         return ret;
1529 }
1530
1531 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1532 {
1533         int error;
1534
1535         if (!dev) {
1536                 DRM_ERROR("dev: %p\n", dev);
1537                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1538                 return -ENODEV;
1539         }
1540
1541         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1542                          state.event != PM_EVENT_FREEZE))
1543                 return -EINVAL;
1544
1545         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1546                 return 0;
1547
1548         error = i915_drm_suspend(dev);
1549         if (error)
1550                 return error;
1551
1552         return i915_drm_suspend_late(dev, false);
1553 }
1554
1555 static int i915_drm_resume(struct drm_device *dev)
1556 {
1557         struct drm_i915_private *dev_priv = to_i915(dev);
1558         int ret;
1559
1560         disable_rpm_wakeref_asserts(dev_priv);
1561         intel_sanitize_gt_powersave(dev_priv);
1562
1563         ret = i915_ggtt_enable_hw(dev_priv);
1564         if (ret)
1565                 DRM_ERROR("failed to re-enable GGTT\n");
1566
1567         intel_csr_ucode_resume(dev_priv);
1568
1569         i915_gem_resume(dev);
1570
1571         i915_restore_state(dev);
1572         intel_pps_unlock_regs_wa(dev_priv);
1573         intel_opregion_setup(dev_priv);
1574
1575         intel_init_pch_refclk(dev);
1576         drm_mode_config_reset(dev);
1577
1578         /*
1579          * Interrupts have to be enabled before any batches are run. If not the
1580          * GPU will hang. i915_gem_init_hw() will initiate batches to
1581          * update/restore the context.
1582          *
1583          * Modeset enabling in intel_modeset_init_hw() also needs working
1584          * interrupts.
1585          */
1586         intel_runtime_pm_enable_interrupts(dev_priv);
1587
1588         mutex_lock(&dev->struct_mutex);
1589         if (i915_gem_init_hw(dev)) {
1590                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1591                 i915_gem_set_wedged(dev_priv);
1592         }
1593         mutex_unlock(&dev->struct_mutex);
1594
1595         intel_guc_resume(dev);
1596
1597         intel_modeset_init_hw(dev);
1598
1599         spin_lock_irq(&dev_priv->irq_lock);
1600         if (dev_priv->display.hpd_irq_setup)
1601                 dev_priv->display.hpd_irq_setup(dev_priv);
1602         spin_unlock_irq(&dev_priv->irq_lock);
1603
1604         intel_dp_mst_resume(dev);
1605
1606         intel_display_resume(dev);
1607
1608         drm_kms_helper_poll_enable(dev);
1609
1610         /*
1611          * ... but also need to make sure that hotplug processing
1612          * doesn't cause havoc. Like in the driver load code we don't
1613          * bother with the tiny race here where we might loose hotplug
1614          * notifications.
1615          * */
1616         intel_hpd_init(dev_priv);
1617
1618         intel_opregion_register(dev_priv);
1619
1620         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1621
1622         mutex_lock(&dev_priv->modeset_restore_lock);
1623         dev_priv->modeset_restore = MODESET_DONE;
1624         mutex_unlock(&dev_priv->modeset_restore_lock);
1625
1626         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1627
1628         intel_autoenable_gt_powersave(dev_priv);
1629
1630         enable_rpm_wakeref_asserts(dev_priv);
1631
1632         return 0;
1633 }
1634
1635 static int i915_drm_resume_early(struct drm_device *dev)
1636 {
1637         struct drm_i915_private *dev_priv = to_i915(dev);
1638         struct pci_dev *pdev = dev_priv->drm.pdev;
1639         int ret;
1640
1641         /*
1642          * We have a resume ordering issue with the snd-hda driver also
1643          * requiring our device to be power up. Due to the lack of a
1644          * parent/child relationship we currently solve this with an early
1645          * resume hook.
1646          *
1647          * FIXME: This should be solved with a special hdmi sink device or
1648          * similar so that power domains can be employed.
1649          */
1650
1651         /*
1652          * Note that we need to set the power state explicitly, since we
1653          * powered off the device during freeze and the PCI core won't power
1654          * it back up for us during thaw. Powering off the device during
1655          * freeze is not a hard requirement though, and during the
1656          * suspend/resume phases the PCI core makes sure we get here with the
1657          * device powered on. So in case we change our freeze logic and keep
1658          * the device powered we can also remove the following set power state
1659          * call.
1660          */
1661         ret = pci_set_power_state(pdev, PCI_D0);
1662         if (ret) {
1663                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1664                 goto out;
1665         }
1666
1667         /*
1668          * Note that pci_enable_device() first enables any parent bridge
1669          * device and only then sets the power state for this device. The
1670          * bridge enabling is a nop though, since bridge devices are resumed
1671          * first. The order of enabling power and enabling the device is
1672          * imposed by the PCI core as described above, so here we preserve the
1673          * same order for the freeze/thaw phases.
1674          *
1675          * TODO: eventually we should remove pci_disable_device() /
1676          * pci_enable_enable_device() from suspend/resume. Due to how they
1677          * depend on the device enable refcount we can't anyway depend on them
1678          * disabling/enabling the device.
1679          */
1680         if (pci_enable_device(pdev)) {
1681                 ret = -EIO;
1682                 goto out;
1683         }
1684
1685         pci_set_master(pdev);
1686
1687         disable_rpm_wakeref_asserts(dev_priv);
1688
1689         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1690                 ret = vlv_resume_prepare(dev_priv, false);
1691         if (ret)
1692                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1693                           ret);
1694
1695         intel_uncore_early_sanitize(dev_priv, true);
1696
1697         if (IS_BROXTON(dev_priv)) {
1698                 if (!dev_priv->suspended_to_idle)
1699                         gen9_sanitize_dc_state(dev_priv);
1700                 bxt_disable_dc9(dev_priv);
1701         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1702                 hsw_disable_pc8(dev_priv);
1703         }
1704
1705         intel_uncore_sanitize(dev_priv);
1706
1707         if (IS_BROXTON(dev_priv) ||
1708             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1709                 intel_power_domains_init_hw(dev_priv, true);
1710
1711         enable_rpm_wakeref_asserts(dev_priv);
1712
1713 out:
1714         dev_priv->suspended_to_idle = false;
1715
1716         return ret;
1717 }
1718
1719 int i915_resume_switcheroo(struct drm_device *dev)
1720 {
1721         int ret;
1722
1723         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1724                 return 0;
1725
1726         ret = i915_drm_resume_early(dev);
1727         if (ret)
1728                 return ret;
1729
1730         return i915_drm_resume(dev);
1731 }
1732
1733 static void disable_engines_irq(struct drm_i915_private *dev_priv)
1734 {
1735         struct intel_engine_cs *engine;
1736         enum intel_engine_id id;
1737
1738         /* Ensure irq handler finishes, and not run again. */
1739         disable_irq(dev_priv->drm.irq);
1740         for_each_engine(engine, dev_priv, id)
1741                 tasklet_kill(&engine->irq_tasklet);
1742 }
1743
1744 static void enable_engines_irq(struct drm_i915_private *dev_priv)
1745 {
1746         enable_irq(dev_priv->drm.irq);
1747 }
1748
1749 /**
1750  * i915_reset - reset chip after a hang
1751  * @dev: drm device to reset
1752  *
1753  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1754  * on failure.
1755  *
1756  * Caller must hold the struct_mutex.
1757  *
1758  * Procedure is fairly simple:
1759  *   - reset the chip using the reset reg
1760  *   - re-init context state
1761  *   - re-init hardware status page
1762  *   - re-init ring buffer
1763  *   - re-init interrupt state
1764  *   - re-init display
1765  */
1766 void i915_reset(struct drm_i915_private *dev_priv)
1767 {
1768         struct drm_device *dev = &dev_priv->drm;
1769         struct i915_gpu_error *error = &dev_priv->gpu_error;
1770         int ret;
1771
1772         lockdep_assert_held(&dev->struct_mutex);
1773
1774         if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1775                 return;
1776
1777         /* Clear any previous failed attempts at recovery. Time to try again. */
1778         __clear_bit(I915_WEDGED, &error->flags);
1779         error->reset_count++;
1780
1781         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1782
1783         disable_engines_irq(dev_priv);
1784         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1785         enable_engines_irq(dev_priv);
1786
1787         if (ret) {
1788                 if (ret != -ENODEV)
1789                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1790                 else
1791                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1792                 goto error;
1793         }
1794
1795         i915_gem_reset(dev_priv);
1796         intel_overlay_reset(dev_priv);
1797
1798         /* Ok, now get things going again... */
1799
1800         /*
1801          * Everything depends on having the GTT running, so we need to start
1802          * there.  Fortunately we don't need to do this unless we reset the
1803          * chip at a PCI level.
1804          *
1805          * Next we need to restore the context, but we don't use those
1806          * yet either...
1807          *
1808          * Ring buffer needs to be re-initialized in the KMS case, or if X
1809          * was running at the time of the reset (i.e. we weren't VT
1810          * switched away).
1811          */
1812         ret = i915_gem_init_hw(dev);
1813         if (ret) {
1814                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1815                 goto error;
1816         }
1817
1818 wakeup:
1819         wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1820         return;
1821
1822 error:
1823         i915_gem_set_wedged(dev_priv);
1824         goto wakeup;
1825 }
1826
1827 static int i915_pm_suspend(struct device *kdev)
1828 {
1829         struct pci_dev *pdev = to_pci_dev(kdev);
1830         struct drm_device *dev = pci_get_drvdata(pdev);
1831
1832         if (!dev) {
1833                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1834                 return -ENODEV;
1835         }
1836
1837         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1838                 return 0;
1839
1840         return i915_drm_suspend(dev);
1841 }
1842
1843 static int i915_pm_suspend_late(struct device *kdev)
1844 {
1845         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1846
1847         /*
1848          * We have a suspend ordering issue with the snd-hda driver also
1849          * requiring our device to be power up. Due to the lack of a
1850          * parent/child relationship we currently solve this with an late
1851          * suspend hook.
1852          *
1853          * FIXME: This should be solved with a special hdmi sink device or
1854          * similar so that power domains can be employed.
1855          */
1856         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1857                 return 0;
1858
1859         return i915_drm_suspend_late(dev, false);
1860 }
1861
1862 static int i915_pm_poweroff_late(struct device *kdev)
1863 {
1864         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1865
1866         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1867                 return 0;
1868
1869         return i915_drm_suspend_late(dev, true);
1870 }
1871
1872 static int i915_pm_resume_early(struct device *kdev)
1873 {
1874         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1875
1876         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1877                 return 0;
1878
1879         return i915_drm_resume_early(dev);
1880 }
1881
1882 static int i915_pm_resume(struct device *kdev)
1883 {
1884         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1885
1886         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1887                 return 0;
1888
1889         return i915_drm_resume(dev);
1890 }
1891
1892 /* freeze: before creating the hibernation_image */
1893 static int i915_pm_freeze(struct device *kdev)
1894 {
1895         int ret;
1896
1897         ret = i915_pm_suspend(kdev);
1898         if (ret)
1899                 return ret;
1900
1901         ret = i915_gem_freeze(kdev_to_i915(kdev));
1902         if (ret)
1903                 return ret;
1904
1905         return 0;
1906 }
1907
1908 static int i915_pm_freeze_late(struct device *kdev)
1909 {
1910         int ret;
1911
1912         ret = i915_pm_suspend_late(kdev);
1913         if (ret)
1914                 return ret;
1915
1916         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1917         if (ret)
1918                 return ret;
1919
1920         return 0;
1921 }
1922
1923 /* thaw: called after creating the hibernation image, but before turning off. */
1924 static int i915_pm_thaw_early(struct device *kdev)
1925 {
1926         return i915_pm_resume_early(kdev);
1927 }
1928
1929 static int i915_pm_thaw(struct device *kdev)
1930 {
1931         return i915_pm_resume(kdev);
1932 }
1933
1934 /* restore: called after loading the hibernation image. */
1935 static int i915_pm_restore_early(struct device *kdev)
1936 {
1937         return i915_pm_resume_early(kdev);
1938 }
1939
1940 static int i915_pm_restore(struct device *kdev)
1941 {
1942         return i915_pm_resume(kdev);
1943 }
1944
1945 /*
1946  * Save all Gunit registers that may be lost after a D3 and a subsequent
1947  * S0i[R123] transition. The list of registers needing a save/restore is
1948  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1949  * registers in the following way:
1950  * - Driver: saved/restored by the driver
1951  * - Punit : saved/restored by the Punit firmware
1952  * - No, w/o marking: no need to save/restore, since the register is R/O or
1953  *                    used internally by the HW in a way that doesn't depend
1954  *                    keeping the content across a suspend/resume.
1955  * - Debug : used for debugging
1956  *
1957  * We save/restore all registers marked with 'Driver', with the following
1958  * exceptions:
1959  * - Registers out of use, including also registers marked with 'Debug'.
1960  *   These have no effect on the driver's operation, so we don't save/restore
1961  *   them to reduce the overhead.
1962  * - Registers that are fully setup by an initialization function called from
1963  *   the resume path. For example many clock gating and RPS/RC6 registers.
1964  * - Registers that provide the right functionality with their reset defaults.
1965  *
1966  * TODO: Except for registers that based on the above 3 criteria can be safely
1967  * ignored, we save/restore all others, practically treating the HW context as
1968  * a black-box for the driver. Further investigation is needed to reduce the
1969  * saved/restored registers even further, by following the same 3 criteria.
1970  */
1971 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1972 {
1973         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1974         int i;
1975
1976         /* GAM 0x4000-0x4770 */
1977         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1978         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1979         s->arb_mode             = I915_READ(ARB_MODE);
1980         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1981         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1982
1983         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1984                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1985
1986         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1987         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1988
1989         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1990         s->ecochk               = I915_READ(GAM_ECOCHK);
1991         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1992         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1993
1994         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1995
1996         /* MBC 0x9024-0x91D0, 0x8500 */
1997         s->g3dctl               = I915_READ(VLV_G3DCTL);
1998         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1999         s->mbctl                = I915_READ(GEN6_MBCTL);
2000
2001         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2002         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2003         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2004         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2005         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2006         s->rstctl               = I915_READ(GEN6_RSTCTL);
2007         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2008
2009         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2010         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2011         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2012         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2013         s->ecobus               = I915_READ(ECOBUS);
2014         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2015         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2016         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2017         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2018         s->rcedata              = I915_READ(VLV_RCEDATA);
2019         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2020
2021         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2022         s->gt_imr               = I915_READ(GTIMR);
2023         s->gt_ier               = I915_READ(GTIER);
2024         s->pm_imr               = I915_READ(GEN6_PMIMR);
2025         s->pm_ier               = I915_READ(GEN6_PMIER);
2026
2027         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2028                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2029
2030         /* GT SA CZ domain, 0x100000-0x138124 */
2031         s->tilectl              = I915_READ(TILECTL);
2032         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2033         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2034         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2035         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2036
2037         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2038         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2039         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2040         s->pcbr                 = I915_READ(VLV_PCBR);
2041         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2042
2043         /*
2044          * Not saving any of:
2045          * DFT,         0x9800-0x9EC0
2046          * SARB,        0xB000-0xB1FC
2047          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2048          * PCI CFG
2049          */
2050 }
2051
2052 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2053 {
2054         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2055         u32 val;
2056         int i;
2057
2058         /* GAM 0x4000-0x4770 */
2059         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2060         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2061         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2062         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2063         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2064
2065         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2066                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2067
2068         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2069         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2070
2071         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2072         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2073         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2074         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2075
2076         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2077
2078         /* MBC 0x9024-0x91D0, 0x8500 */
2079         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2080         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2081         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2082
2083         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2084         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2085         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2086         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2087         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2088         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2089         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2090
2091         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2092         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2093         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2094         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2095         I915_WRITE(ECOBUS,              s->ecobus);
2096         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2097         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2098         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2099         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2100         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2101         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2102
2103         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2104         I915_WRITE(GTIMR,               s->gt_imr);
2105         I915_WRITE(GTIER,               s->gt_ier);
2106         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2107         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2108
2109         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2110                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2111
2112         /* GT SA CZ domain, 0x100000-0x138124 */
2113         I915_WRITE(TILECTL,                     s->tilectl);
2114         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2115         /*
2116          * Preserve the GT allow wake and GFX force clock bit, they are not
2117          * be restored, as they are used to control the s0ix suspend/resume
2118          * sequence by the caller.
2119          */
2120         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2121         val &= VLV_GTLC_ALLOWWAKEREQ;
2122         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2123         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2124
2125         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2126         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2127         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2128         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2129
2130         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2131
2132         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2133         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2134         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2135         I915_WRITE(VLV_PCBR,                    s->pcbr);
2136         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2137 }
2138
2139 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2140 {
2141         u32 val;
2142         int err;
2143
2144         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2145         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2146         if (force_on)
2147                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2148         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2149
2150         if (!force_on)
2151                 return 0;
2152
2153         err = intel_wait_for_register(dev_priv,
2154                                       VLV_GTLC_SURVIVABILITY_REG,
2155                                       VLV_GFX_CLK_STATUS_BIT,
2156                                       VLV_GFX_CLK_STATUS_BIT,
2157                                       20);
2158         if (err)
2159                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2160                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2161
2162         return err;
2163 }
2164
2165 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2166 {
2167         u32 val;
2168         int err = 0;
2169
2170         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2171         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2172         if (allow)
2173                 val |= VLV_GTLC_ALLOWWAKEREQ;
2174         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2175         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2176
2177         err = intel_wait_for_register(dev_priv,
2178                                       VLV_GTLC_PW_STATUS,
2179                                       VLV_GTLC_ALLOWWAKEACK,
2180                                       allow,
2181                                       1);
2182         if (err)
2183                 DRM_ERROR("timeout disabling GT waking\n");
2184
2185         return err;
2186 }
2187
2188 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2189                                  bool wait_for_on)
2190 {
2191         u32 mask;
2192         u32 val;
2193         int err;
2194
2195         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2196         val = wait_for_on ? mask : 0;
2197         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2198                 return 0;
2199
2200         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2201                       onoff(wait_for_on),
2202                       I915_READ(VLV_GTLC_PW_STATUS));
2203
2204         /*
2205          * RC6 transitioning can be delayed up to 2 msec (see
2206          * valleyview_enable_rps), use 3 msec for safety.
2207          */
2208         err = intel_wait_for_register(dev_priv,
2209                                       VLV_GTLC_PW_STATUS, mask, val,
2210                                       3);
2211         if (err)
2212                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2213                           onoff(wait_for_on));
2214
2215         return err;
2216 }
2217
2218 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2219 {
2220         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2221                 return;
2222
2223         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2224         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2225 }
2226
2227 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2228 {
2229         u32 mask;
2230         int err;
2231
2232         /*
2233          * Bspec defines the following GT well on flags as debug only, so
2234          * don't treat them as hard failures.
2235          */
2236         (void)vlv_wait_for_gt_wells(dev_priv, false);
2237
2238         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2239         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2240
2241         vlv_check_no_gt_access(dev_priv);
2242
2243         err = vlv_force_gfx_clock(dev_priv, true);
2244         if (err)
2245                 goto err1;
2246
2247         err = vlv_allow_gt_wake(dev_priv, false);
2248         if (err)
2249                 goto err2;
2250
2251         if (!IS_CHERRYVIEW(dev_priv))
2252                 vlv_save_gunit_s0ix_state(dev_priv);
2253
2254         err = vlv_force_gfx_clock(dev_priv, false);
2255         if (err)
2256                 goto err2;
2257
2258         return 0;
2259
2260 err2:
2261         /* For safety always re-enable waking and disable gfx clock forcing */
2262         vlv_allow_gt_wake(dev_priv, true);
2263 err1:
2264         vlv_force_gfx_clock(dev_priv, false);
2265
2266         return err;
2267 }
2268
2269 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2270                                 bool rpm_resume)
2271 {
2272         int err;
2273         int ret;
2274
2275         /*
2276          * If any of the steps fail just try to continue, that's the best we
2277          * can do at this point. Return the first error code (which will also
2278          * leave RPM permanently disabled).
2279          */
2280         ret = vlv_force_gfx_clock(dev_priv, true);
2281
2282         if (!IS_CHERRYVIEW(dev_priv))
2283                 vlv_restore_gunit_s0ix_state(dev_priv);
2284
2285         err = vlv_allow_gt_wake(dev_priv, true);
2286         if (!ret)
2287                 ret = err;
2288
2289         err = vlv_force_gfx_clock(dev_priv, false);
2290         if (!ret)
2291                 ret = err;
2292
2293         vlv_check_no_gt_access(dev_priv);
2294
2295         if (rpm_resume)
2296                 intel_init_clock_gating(dev_priv);
2297
2298         return ret;
2299 }
2300
2301 static int intel_runtime_suspend(struct device *kdev)
2302 {
2303         struct pci_dev *pdev = to_pci_dev(kdev);
2304         struct drm_device *dev = pci_get_drvdata(pdev);
2305         struct drm_i915_private *dev_priv = to_i915(dev);
2306         int ret;
2307
2308         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2309                 return -ENODEV;
2310
2311         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2312                 return -ENODEV;
2313
2314         DRM_DEBUG_KMS("Suspending device\n");
2315
2316         disable_rpm_wakeref_asserts(dev_priv);
2317
2318         /*
2319          * We are safe here against re-faults, since the fault handler takes
2320          * an RPM reference.
2321          */
2322         i915_gem_runtime_suspend(dev_priv);
2323
2324         intel_guc_suspend(dev);
2325
2326         intel_runtime_pm_disable_interrupts(dev_priv);
2327
2328         ret = 0;
2329         if (IS_BROXTON(dev_priv)) {
2330                 bxt_display_core_uninit(dev_priv);
2331                 bxt_enable_dc9(dev_priv);
2332         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2333                 hsw_enable_pc8(dev_priv);
2334         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2335                 ret = vlv_suspend_complete(dev_priv);
2336         }
2337
2338         if (ret) {
2339                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2340                 intel_runtime_pm_enable_interrupts(dev_priv);
2341
2342                 enable_rpm_wakeref_asserts(dev_priv);
2343
2344                 return ret;
2345         }
2346
2347         intel_uncore_forcewake_reset(dev_priv, false);
2348
2349         enable_rpm_wakeref_asserts(dev_priv);
2350         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2351
2352         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2353                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2354
2355         dev_priv->pm.suspended = true;
2356
2357         /*
2358          * FIXME: We really should find a document that references the arguments
2359          * used below!
2360          */
2361         if (IS_BROADWELL(dev_priv)) {
2362                 /*
2363                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2364                  * being detected, and the call we do at intel_runtime_resume()
2365                  * won't be able to restore them. Since PCI_D3hot matches the
2366                  * actual specification and appears to be working, use it.
2367                  */
2368                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2369         } else {
2370                 /*
2371                  * current versions of firmware which depend on this opregion
2372                  * notification have repurposed the D1 definition to mean
2373                  * "runtime suspended" vs. what you would normally expect (D3)
2374                  * to distinguish it from notifications that might be sent via
2375                  * the suspend path.
2376                  */
2377                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2378         }
2379
2380         assert_forcewakes_inactive(dev_priv);
2381
2382         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2383                 intel_hpd_poll_init(dev_priv);
2384
2385         DRM_DEBUG_KMS("Device suspended\n");
2386         return 0;
2387 }
2388
2389 static int intel_runtime_resume(struct device *kdev)
2390 {
2391         struct pci_dev *pdev = to_pci_dev(kdev);
2392         struct drm_device *dev = pci_get_drvdata(pdev);
2393         struct drm_i915_private *dev_priv = to_i915(dev);
2394         int ret = 0;
2395
2396         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2397                 return -ENODEV;
2398
2399         DRM_DEBUG_KMS("Resuming device\n");
2400
2401         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2402         disable_rpm_wakeref_asserts(dev_priv);
2403
2404         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2405         dev_priv->pm.suspended = false;
2406         if (intel_uncore_unclaimed_mmio(dev_priv))
2407                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2408
2409         intel_guc_resume(dev);
2410
2411         if (IS_GEN6(dev_priv))
2412                 intel_init_pch_refclk(dev);
2413
2414         if (IS_BROXTON(dev_priv)) {
2415                 bxt_disable_dc9(dev_priv);
2416                 bxt_display_core_init(dev_priv, true);
2417                 if (dev_priv->csr.dmc_payload &&
2418                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2419                         gen9_enable_dc5(dev_priv);
2420         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2421                 hsw_disable_pc8(dev_priv);
2422         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2423                 ret = vlv_resume_prepare(dev_priv, true);
2424         }
2425
2426         /*
2427          * No point of rolling back things in case of an error, as the best
2428          * we can do is to hope that things will still work (and disable RPM).
2429          */
2430         i915_gem_init_swizzling(dev_priv);
2431         i915_gem_restore_fences(dev_priv);
2432
2433         intel_runtime_pm_enable_interrupts(dev_priv);
2434
2435         /*
2436          * On VLV/CHV display interrupts are part of the display
2437          * power well, so hpd is reinitialized from there. For
2438          * everyone else do it here.
2439          */
2440         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2441                 intel_hpd_init(dev_priv);
2442
2443         enable_rpm_wakeref_asserts(dev_priv);
2444
2445         if (ret)
2446                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2447         else
2448                 DRM_DEBUG_KMS("Device resumed\n");
2449
2450         return ret;
2451 }
2452
2453 const struct dev_pm_ops i915_pm_ops = {
2454         /*
2455          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2456          * PMSG_RESUME]
2457          */
2458         .suspend = i915_pm_suspend,
2459         .suspend_late = i915_pm_suspend_late,
2460         .resume_early = i915_pm_resume_early,
2461         .resume = i915_pm_resume,
2462
2463         /*
2464          * S4 event handlers
2465          * @freeze, @freeze_late    : called (1) before creating the
2466          *                            hibernation image [PMSG_FREEZE] and
2467          *                            (2) after rebooting, before restoring
2468          *                            the image [PMSG_QUIESCE]
2469          * @thaw, @thaw_early       : called (1) after creating the hibernation
2470          *                            image, before writing it [PMSG_THAW]
2471          *                            and (2) after failing to create or
2472          *                            restore the image [PMSG_RECOVER]
2473          * @poweroff, @poweroff_late: called after writing the hibernation
2474          *                            image, before rebooting [PMSG_HIBERNATE]
2475          * @restore, @restore_early : called after rebooting and restoring the
2476          *                            hibernation image [PMSG_RESTORE]
2477          */
2478         .freeze = i915_pm_freeze,
2479         .freeze_late = i915_pm_freeze_late,
2480         .thaw_early = i915_pm_thaw_early,
2481         .thaw = i915_pm_thaw,
2482         .poweroff = i915_pm_suspend,
2483         .poweroff_late = i915_pm_poweroff_late,
2484         .restore_early = i915_pm_restore_early,
2485         .restore = i915_pm_restore,
2486
2487         /* S0ix (via runtime suspend) event handlers */
2488         .runtime_suspend = intel_runtime_suspend,
2489         .runtime_resume = intel_runtime_resume,
2490 };
2491
2492 static const struct vm_operations_struct i915_gem_vm_ops = {
2493         .fault = i915_gem_fault,
2494         .open = drm_gem_vm_open,
2495         .close = drm_gem_vm_close,
2496 };
2497
2498 static const struct file_operations i915_driver_fops = {
2499         .owner = THIS_MODULE,
2500         .open = drm_open,
2501         .release = drm_release,
2502         .unlocked_ioctl = drm_ioctl,
2503         .mmap = drm_gem_mmap,
2504         .poll = drm_poll,
2505         .read = drm_read,
2506         .compat_ioctl = i915_compat_ioctl,
2507         .llseek = noop_llseek,
2508 };
2509
2510 static int
2511 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2512                           struct drm_file *file)
2513 {
2514         return -ENODEV;
2515 }
2516
2517 static const struct drm_ioctl_desc i915_ioctls[] = {
2518         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2519         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2520         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2521         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2522         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2523         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2524         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2525         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2526         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2527         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2528         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2529         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2530         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2531         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2532         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2533         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2534         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2535         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2536         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2537         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2538         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2539         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2540         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2541         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2542         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2543         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2544         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2545         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2546         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2547         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2548         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2549         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2550         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2551         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2552         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2553         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2554         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2555         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2556         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2557         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2558         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2559         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2560         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2561         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2562         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2563         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2564         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2565         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2566         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2567         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2568         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2569         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2570 };
2571
2572 static struct drm_driver driver = {
2573         /* Don't use MTRRs here; the Xserver or userspace app should
2574          * deal with them for Intel hardware.
2575          */
2576         .driver_features =
2577             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2578             DRIVER_RENDER | DRIVER_MODESET,
2579         .open = i915_driver_open,
2580         .lastclose = i915_driver_lastclose,
2581         .preclose = i915_driver_preclose,
2582         .postclose = i915_driver_postclose,
2583         .set_busid = drm_pci_set_busid,
2584
2585         .gem_close_object = i915_gem_close_object,
2586         .gem_free_object_unlocked = i915_gem_free_object,
2587         .gem_vm_ops = &i915_gem_vm_ops,
2588
2589         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2590         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2591         .gem_prime_export = i915_gem_prime_export,
2592         .gem_prime_import = i915_gem_prime_import,
2593
2594         .dumb_create = i915_gem_dumb_create,
2595         .dumb_map_offset = i915_gem_mmap_gtt,
2596         .dumb_destroy = drm_gem_dumb_destroy,
2597         .ioctls = i915_ioctls,
2598         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2599         .fops = &i915_driver_fops,
2600         .name = DRIVER_NAME,
2601         .desc = DRIVER_DESC,
2602         .date = DRIVER_DATE,
2603         .major = DRIVER_MAJOR,
2604         .minor = DRIVER_MINOR,
2605         .patchlevel = DRIVER_PATCHLEVEL,
2606 };