drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_irq.h>
  47 #include <drm/drm_probe_helper.h>
  48 #include <drm/i915_drm.h>
  49
  50 #include "gem/i915_gem_ioctls.h"
  51 #include "gt/intel_gt_pm.h"
  52 #include "gt/intel_reset.h"
  53 #include "gt/intel_workarounds.h"
  54
  55 #include "i915_debugfs.h"
  56 #include "i915_drv.h"
  57 #include "i915_irq.h"
  58 #include "i915_pmu.h"
  59 #include "i915_query.h"
  60 #include "i915_trace.h"
  61 #include "i915_vgpu.h"
  62 #include "intel_acpi.h"
  63 #include "intel_audio.h"
  64 #include "intel_bw.h"
  65 #include "intel_cdclk.h"
  66 #include "intel_csr.h"
  67 #include "intel_dp.h"
  68 #include "intel_drv.h"
  69 #include "intel_fbdev.h"
  70 #include "intel_gmbus.h"
  71 #include "intel_hotplug.h"
  72 #include "intel_overlay.h"
  73 #include "intel_pipe_crc.h"
  74 #include "intel_pm.h"
  75 #include "intel_sprite.h"
  76 #include "intel_uc.h"
  77
  78 static struct drm_driver driver;
  79
  80 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  81 static unsigned int i915_load_fail_count;
  82
  83 bool __i915_inject_load_failure(const char *func, int line)
  84 {
  85         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  86                 return false;
  87
  88         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  89                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  90                          i915_modparams.inject_load_failure, func, line);
  91                 i915_modparams.inject_load_failure = 0;
  92                 return true;
  93         }
  94
  95         return false;
  96 }
  97
  98 bool i915_error_injected(void)
  99 {
 100         return i915_load_fail_count && !i915_modparams.inject_load_failure;
 101 }
 102
 103 #endif
 104
 105 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
 106 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
 107                     "providing the dmesg log by booting with drm.debug=0xf"
 108
 109 void
 110 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
 111               const char *fmt, ...)
 112 {
 113         static bool shown_bug_once;
 114         struct device *kdev = dev_priv->drm.dev;
 115         bool is_error = level[1] <= KERN_ERR[1];
 116         bool is_debug = level[1] == KERN_DEBUG[1];
 117         struct va_format vaf;
 118         va_list args;
 119
 120         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
 121                 return;
 122
 123         va_start(args, fmt);
 124
 125         vaf.fmt = fmt;
 126         vaf.va = &args;
 127
 128         if (is_error)
 129                 dev_printk(level, kdev, "%pV", &vaf);
 130         else
 131                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 132                            __builtin_return_address(0), &vaf);
 133
 134         va_end(args);
 135
 136         if (is_error && !shown_bug_once) {
 137                 /*
 138                  * Ask the user to file a bug report for the error, except
 139                  * if they may have caused the bug by fiddling with unsafe
 140                  * module parameters.
 141                  */
 142                 if (!test_taint(TAINT_USER))
 143                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 144                 shown_bug_once = true;
 145         }
 146 }
 147
 148 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 149 static enum intel_pch
 150 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 151 {
 152         switch (id) {
 153         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 154                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 155                 WARN_ON(!IS_GEN(dev_priv, 5));
 156                 return PCH_IBX;
 157         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 158                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 159                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
 160                 return PCH_CPT;
 161         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 162                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 163                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
 164                 /* PantherPoint is CPT compatible */
 165                 return PCH_CPT;
 166         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 167                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 168                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 169                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 170                 return PCH_LPT;
 171         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 172                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 173                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 174                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 175                 return PCH_LPT;
 176         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 177                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 178                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 179                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 180                 /* WildcatPoint is LPT compatible */
 181                 return PCH_LPT;
 182         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 183                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 184                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 185                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 186                 /* WildcatPoint is LPT compatible */
 187                 return PCH_LPT;
 188         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 189                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 190                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 191                 return PCH_SPT;
 192         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 193                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 194                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 195                 return PCH_SPT;
 196         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 197                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 198                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 199                         !IS_COFFEELAKE(dev_priv));
 200                 /* KBP is SPT compatible */
 201                 return PCH_SPT;
 202         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 203                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 204                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 205                 return PCH_CNP;
 206         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 207                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 208                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 209                 return PCH_CNP;
 210         case INTEL_PCH_CMP_DEVICE_ID_TYPE:
 211                 DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
 212                 WARN_ON(!IS_COFFEELAKE(dev_priv));
 213                 /* CometPoint is CNP Compatible */
 214                 return PCH_CNP;
 215         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 216                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 217                 WARN_ON(!IS_ICELAKE(dev_priv));
 218                 return PCH_ICP;
 219         default:
 220                 return PCH_NONE;
 221         }
 222 }
 223
 224 static bool intel_is_virt_pch(unsigned short id,
 225                               unsigned short svendor, unsigned short sdevice)
 226 {
 227         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 228                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 229                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 230                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 231                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 232 }
 233
 234 static unsigned short
 235 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 236 {
 237         unsigned short id = 0;
 238
 239         /*
 240          * In a virtualized passthrough environment we can be in a
 241          * setup where the ISA bridge is not able to be passed through.
 242          * In this case, a south bridge can be emulated and we have to
 243          * make an educated guess as to which PCH is really there.
 244          */
 245
 246         if (IS_ICELAKE(dev_priv))
 247                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 248         else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 249                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 250         else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
 251                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 252         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 253                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 254         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 255                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 256         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
 257                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 258         else if (IS_GEN(dev_priv, 5))
 259                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 260
 261         if (id)
 262                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 263         else
 264                 DRM_DEBUG_KMS("Assuming no PCH\n");
 265
 266         return id;
 267 }
 268
 269 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 270 {
 271         struct pci_dev *pch = NULL;
 272
 273         /*
 274          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 275          * make graphics device passthrough work easy for VMM, that only
 276          * need to expose ISA bridge to let driver know the real hardware
 277          * underneath. This is a requirement from virtualization team.
 278          *
 279          * In some virtualized environments (e.g. XEN), there is irrelevant
 280          * ISA bridge in the system. To work reliably, we should scan trhough
 281          * all the ISA bridge devices and check for the first match, instead
 282          * of only checking the first one.
 283          */
 284         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 285                 unsigned short id;
 286                 enum intel_pch pch_type;
 287
 288                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 289                         continue;
 290
 291                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 292
 293                 pch_type = intel_pch_type(dev_priv, id);
 294                 if (pch_type != PCH_NONE) {
 295                         dev_priv->pch_type = pch_type;
 296                         dev_priv->pch_id = id;
 297                         break;
 298                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 299                                          pch->subsystem_device)) {
 300                         id = intel_virt_detect_pch(dev_priv);
 301                         pch_type = intel_pch_type(dev_priv, id);
 302
 303                         /* Sanity check virtual PCH id */
 304                         if (WARN_ON(id && pch_type == PCH_NONE))
 305                                 id = 0;
 306
 307                         dev_priv->pch_type = pch_type;
 308                         dev_priv->pch_id = id;
 309                         break;
 310                 }
 311         }
 312
 313         /*
 314          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
 315          * display.
 316          */
 317         if (pch && !HAS_DISPLAY(dev_priv)) {
 318                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
 319                 dev_priv->pch_type = PCH_NOP;
 320                 dev_priv->pch_id = 0;
 321         }
 322
 323         if (!pch)
 324                 DRM_DEBUG_KMS("No PCH found.\n");
 325
 326         pci_dev_put(pch);
 327 }
 328
 329 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 330                                struct drm_file *file_priv)
 331 {
 332         struct drm_i915_private *dev_priv = to_i915(dev);
 333         struct pci_dev *pdev = dev_priv->drm.pdev;
 334         drm_i915_getparam_t *param = data;
 335         int value;
 336
 337         switch (param->param) {
 338         case I915_PARAM_IRQ_ACTIVE:
 339         case I915_PARAM_ALLOW_BATCHBUFFER:
 340         case I915_PARAM_LAST_DISPATCH:
 341         case I915_PARAM_HAS_EXEC_CONSTANTS:
 342                 /* Reject all old ums/dri params. */
 343                 return -ENODEV;
 344         case I915_PARAM_CHIPSET_ID:
 345                 value = pdev->device;
 346                 break;
 347         case I915_PARAM_REVISION:
 348                 value = pdev->revision;
 349                 break;
 350         case I915_PARAM_NUM_FENCES_AVAIL:
 351                 value = dev_priv->num_fence_regs;
 352                 break;
 353         case I915_PARAM_HAS_OVERLAY:
 354                 value = dev_priv->overlay ? 1 : 0;
 355                 break;
 356         case I915_PARAM_HAS_BSD:
 357                 value = !!dev_priv->engine[VCS0];
 358                 break;
 359         case I915_PARAM_HAS_BLT:
 360                 value = !!dev_priv->engine[BCS0];
 361                 break;
 362         case I915_PARAM_HAS_VEBOX:
 363                 value = !!dev_priv->engine[VECS0];
 364                 break;
 365         case I915_PARAM_HAS_BSD2:
 366                 value = !!dev_priv->engine[VCS1];
 367                 break;
 368         case I915_PARAM_HAS_LLC:
 369                 value = HAS_LLC(dev_priv);
 370                 break;
 371         case I915_PARAM_HAS_WT:
 372                 value = HAS_WT(dev_priv);
 373                 break;
 374         case I915_PARAM_HAS_ALIASING_PPGTT:
 375                 value = INTEL_PPGTT(dev_priv);
 376                 break;
 377         case I915_PARAM_HAS_SEMAPHORES:
 378                 value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
 379                 break;
 380         case I915_PARAM_HAS_SECURE_BATCHES:
 381                 value = capable(CAP_SYS_ADMIN);
 382                 break;
 383         case I915_PARAM_CMD_PARSER_VERSION:
 384                 value = i915_cmd_parser_get_version(dev_priv);
 385                 break;
 386         case I915_PARAM_SUBSLICE_TOTAL:
 387                 value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
 388                 if (!value)
 389                         return -ENODEV;
 390                 break;
 391         case I915_PARAM_EU_TOTAL:
 392                 value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
 393                 if (!value)
 394                         return -ENODEV;
 395                 break;
 396         case I915_PARAM_HAS_GPU_RESET:
 397                 value = i915_modparams.enable_hangcheck &&
 398                         intel_has_gpu_reset(dev_priv);
 399                 if (value && intel_has_reset_engine(dev_priv))
 400                         value = 2;
 401                 break;
 402         case I915_PARAM_HAS_RESOURCE_STREAMER:
 403                 value = 0;
 404                 break;
 405         case I915_PARAM_HAS_POOLED_EU:
 406                 value = HAS_POOLED_EU(dev_priv);
 407                 break;
 408         case I915_PARAM_MIN_EU_IN_POOL:
 409                 value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
 410                 break;
 411         case I915_PARAM_HUC_STATUS:
 412                 value = intel_huc_check_status(&dev_priv->huc);
 413                 if (value < 0)
 414                         return value;
 415                 break;
 416         case I915_PARAM_MMAP_GTT_VERSION:
 417                 /* Though we've started our numbering from 1, and so class all
 418                  * earlier versions as 0, in effect their value is undefined as
 419                  * the ioctl will report EINVAL for the unknown param!
 420                  */
 421                 value = i915_gem_mmap_gtt_version();
 422                 break;
 423         case I915_PARAM_HAS_SCHEDULER:
 424                 value = dev_priv->caps.scheduler;
 425                 break;
 426
 427         case I915_PARAM_MMAP_VERSION:
 428                 /* Remember to bump this if the version changes! */
 429         case I915_PARAM_HAS_GEM:
 430         case I915_PARAM_HAS_PAGEFLIPPING:
 431         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 432         case I915_PARAM_HAS_RELAXED_FENCING:
 433         case I915_PARAM_HAS_COHERENT_RINGS:
 434         case I915_PARAM_HAS_RELAXED_DELTA:
 435         case I915_PARAM_HAS_GEN7_SOL_RESET:
 436         case I915_PARAM_HAS_WAIT_TIMEOUT:
 437         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 438         case I915_PARAM_HAS_PINNED_BATCHES:
 439         case I915_PARAM_HAS_EXEC_NO_RELOC:
 440         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 441         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 442         case I915_PARAM_HAS_EXEC_SOFTPIN:
 443         case I915_PARAM_HAS_EXEC_ASYNC:
 444         case I915_PARAM_HAS_EXEC_FENCE:
 445         case I915_PARAM_HAS_EXEC_CAPTURE:
 446         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 447         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 448         case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
 449                 /* For the time being all of these are always true;
 450                  * if some supported hardware does not have one of these
 451                  * features this value needs to be provided from
 452                  * INTEL_INFO(), a feature macro, or similar.
 453                  */
 454                 value = 1;
 455                 break;
 456         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 457                 value = intel_engines_has_context_isolation(dev_priv);
 458                 break;
 459         case I915_PARAM_SLICE_MASK:
 460                 value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
 461                 if (!value)
 462                         return -ENODEV;
 463                 break;
 464         case I915_PARAM_SUBSLICE_MASK:
 465                 value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
 466                 if (!value)
 467                         return -ENODEV;
 468                 break;
 469         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 470                 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
 471                 break;
 472         case I915_PARAM_MMAP_GTT_COHERENT:
 473                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
 474                 break;
 475         default:
 476                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 477                 return -EINVAL;
 478         }
 479
 480         if (put_user(value, param->value))
 481                 return -EFAULT;
 482
 483         return 0;
 484 }
 485
 486 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 487 {
 488         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 489
 490         dev_priv->bridge_dev =
 491                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 492         if (!dev_priv->bridge_dev) {
 493                 DRM_ERROR("bridge device not found\n");
 494                 return -1;
 495         }
 496         return 0;
 497 }
 498
 499 /* Allocate space for the MCH regs if needed, return nonzero on error */
 500 static int
 501 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 502 {
 503         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 504         u32 temp_lo, temp_hi = 0;
 505         u64 mchbar_addr;
 506         int ret;
 507
 508         if (INTEL_GEN(dev_priv) >= 4)
 509                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 510         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 511         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 512
 513         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 514 #ifdef CONFIG_PNP
 515         if (mchbar_addr &&
 516             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 517                 return 0;
 518 #endif
 519
 520         /* Get some space for it */
 521         dev_priv->mch_res.name = "i915 MCHBAR";
 522         dev_priv->mch_res.flags = IORESOURCE_MEM;
 523         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 524                                      &dev_priv->mch_res,
 525                                      MCHBAR_SIZE, MCHBAR_SIZE,
 526                                      PCIBIOS_MIN_MEM,
 527                                      0, pcibios_align_resource,
 528                                      dev_priv->bridge_dev);
 529         if (ret) {
 530                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 531                 dev_priv->mch_res.start = 0;
 532                 return ret;
 533         }
 534
 535         if (INTEL_GEN(dev_priv) >= 4)
 536                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 537                                        upper_32_bits(dev_priv->mch_res.start));
 538
 539         pci_write_config_dword(dev_priv->bridge_dev, reg,
 540                                lower_32_bits(dev_priv->mch_res.start));
 541         return 0;
 542 }
 543
 544 /* Setup MCHBAR if possible, return true if we should disable it again */
 545 static void
 546 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 547 {
 548         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 549         u32 temp;
 550         bool enabled;
 551
 552         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 553                 return;
 554
 555         dev_priv->mchbar_need_disable = false;
 556
 557         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 558                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 559                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 560         } else {
 561                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 562                 enabled = temp & 1;
 563         }
 564
 565         /* If it's already enabled, don't have to do anything */
 566         if (enabled)
 567                 return;
 568
 569         if (intel_alloc_mchbar_resource(dev_priv))
 570                 return;
 571
 572         dev_priv->mchbar_need_disable = true;
 573
 574         /* Space is allocated or reserved, so enable it. */
 575         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 576                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 577                                        temp | DEVEN_MCHBAR_EN);
 578         } else {
 579                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 580                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 581         }
 582 }
 583
 584 static void
 585 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 586 {
 587         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 588
 589         if (dev_priv->mchbar_need_disable) {
 590                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 591                         u32 deven_val;
 592
 593                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 594                                               &deven_val);
 595                         deven_val &= ~DEVEN_MCHBAR_EN;
 596                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 597                                                deven_val);
 598                 } else {
 599                         u32 mchbar_val;
 600
 601                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 602                                               &mchbar_val);
 603                         mchbar_val &= ~1;
 604                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 605                                                mchbar_val);
 606                 }
 607         }
 608
 609         if (dev_priv->mch_res.start)
 610                 release_resource(&dev_priv->mch_res);
 611 }
 612
 613 /* true = enable decode, false = disable decoder */
 614 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 615 {
 616         struct drm_i915_private *dev_priv = cookie;
 617
 618         intel_modeset_vga_set_state(dev_priv, state);
 619         if (state)
 620                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 621                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 622         else
 623                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 624 }
 625
 626 static int i915_resume_switcheroo(struct drm_device *dev);
 627 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 628
 629 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 630 {
 631         struct drm_device *dev = pci_get_drvdata(pdev);
 632         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 633
 634         if (state == VGA_SWITCHEROO_ON) {
 635                 pr_info("switched on\n");
 636                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 637                 /* i915 resume handler doesn't set to D0 */
 638                 pci_set_power_state(pdev, PCI_D0);
 639                 i915_resume_switcheroo(dev);
 640                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 641         } else {
 642                 pr_info("switched off\n");
 643                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 644                 i915_suspend_switcheroo(dev, pmm);
 645                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 646         }
 647 }
 648
 649 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 650 {
 651         struct drm_device *dev = pci_get_drvdata(pdev);
 652
 653         /*
 654          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 655          * locking inversion with the driver load path. And the access here is
 656          * completely racy anyway. So don't bother with locking for now.
 657          */
 658         return dev->open_count == 0;
 659 }
 660
 661 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 662         .set_gpu_state = i915_switcheroo_set_state,
 663         .reprobe = NULL,
 664         .can_switch = i915_switcheroo_can_switch,
 665 };
 666
 667 static int i915_load_modeset_init(struct drm_device *dev)
 668 {
 669         struct drm_i915_private *dev_priv = to_i915(dev);
 670         struct pci_dev *pdev = dev_priv->drm.pdev;
 671         int ret;
 672
 673         if (i915_inject_load_failure())
 674                 return -ENODEV;
 675
 676         if (HAS_DISPLAY(dev_priv)) {
 677                 ret = drm_vblank_init(&dev_priv->drm,
 678                                       INTEL_INFO(dev_priv)->num_pipes);
 679                 if (ret)
 680                         goto out;
 681         }
 682
 683         intel_bios_init(dev_priv);
 684
 685         /* If we have > 1 VGA cards, then we need to arbitrate access
 686          * to the common VGA resources.
 687          *
 688          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 689          * then we do not take part in VGA arbitration and the
 690          * vga_client_register() fails with -ENODEV.
 691          */
 692         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 693         if (ret && ret != -ENODEV)
 694                 goto out;
 695
 696         intel_register_dsm_handler();
 697
 698         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 699         if (ret)
 700                 goto cleanup_vga_client;
 701
 702         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 703         intel_update_rawclk(dev_priv);
 704
 705         intel_power_domains_init_hw(dev_priv, false);
 706
 707         intel_csr_ucode_init(dev_priv);
 708
 709         ret = intel_irq_install(dev_priv);
 710         if (ret)
 711                 goto cleanup_csr;
 712
 713         intel_gmbus_setup(dev_priv);
 714
 715         /* Important: The output setup functions called by modeset_init need
 716          * working irqs for e.g. gmbus and dp aux transfers. */
 717         ret = intel_modeset_init(dev);
 718         if (ret)
 719                 goto cleanup_irq;
 720
 721         ret = i915_gem_init(dev_priv);
 722         if (ret)
 723                 goto cleanup_modeset;
 724
 725         intel_overlay_setup(dev_priv);
 726
 727         if (!HAS_DISPLAY(dev_priv))
 728                 return 0;
 729
 730         ret = intel_fbdev_init(dev);
 731         if (ret)
 732                 goto cleanup_gem;
 733
 734         /* Only enable hotplug handling once the fbdev is fully set up. */
 735         intel_hpd_init(dev_priv);
 736
 737         intel_init_ipc(dev_priv);
 738
 739         return 0;
 740
 741 cleanup_gem:
 742         i915_gem_suspend(dev_priv);
 743         i915_gem_fini(dev_priv);
 744 cleanup_modeset:
 745         intel_modeset_cleanup(dev);
 746 cleanup_irq:
 747         drm_irq_uninstall(dev);
 748         intel_gmbus_teardown(dev_priv);
 749 cleanup_csr:
 750         intel_csr_ucode_fini(dev_priv);
 751         intel_power_domains_fini_hw(dev_priv);
 752         vga_switcheroo_unregister_client(pdev);
 753 cleanup_vga_client:
 754         vga_client_register(pdev, NULL, NULL, NULL);
 755 out:
 756         return ret;
 757 }
 758
 759 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 760 {
 761         struct apertures_struct *ap;
 762         struct pci_dev *pdev = dev_priv->drm.pdev;
 763         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 764         bool primary;
 765         int ret;
 766
 767         ap = alloc_apertures(1);
 768         if (!ap)
 769                 return -ENOMEM;
 770
 771         ap->ranges[0].base = ggtt->gmadr.start;
 772         ap->ranges[0].size = ggtt->mappable_end;
 773
 774         primary =
 775                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 776
 777         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 778
 779         kfree(ap);
 780
 781         return ret;
 782 }
 783
 784 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 785 {
 786         /*
 787          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 788          * CHV x1 PHY (DP/HDMI D)
 789          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 790          */
 791         if (IS_CHERRYVIEW(dev_priv)) {
 792                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 793                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 794         } else if (IS_VALLEYVIEW(dev_priv)) {
 795                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 796         }
 797 }
 798
 799 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 800 {
 801         /*
 802          * The i915 workqueue is primarily used for batched retirement of
 803          * requests (and thus managing bo) once the task has been completed
 804          * by the GPU. i915_retire_requests() is called directly when we
 805          * need high-priority retirement, such as waiting for an explicit
 806          * bo.
 807          *
 808          * It is also used for periodic low-priority events, such as
 809          * idle-timers and recording error state.
 810          *
 811          * All tasks on the workqueue are expected to acquire the dev mutex
 812          * so there is no point in running more than one instance of the
 813          * workqueue at any time.  Use an ordered one.
 814          */
 815         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 816         if (dev_priv->wq == NULL)
 817                 goto out_err;
 818
 819         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 820         if (dev_priv->hotplug.dp_wq == NULL)
 821                 goto out_free_wq;
 822
 823         return 0;
 824
 825 out_free_wq:
 826         destroy_workqueue(dev_priv->wq);
 827 out_err:
 828         DRM_ERROR("Failed to allocate workqueues.\n");
 829
 830         return -ENOMEM;
 831 }
 832
 833 static void i915_engines_cleanup(struct drm_i915_private *i915)
 834 {
 835         struct intel_engine_cs *engine;
 836         enum intel_engine_id id;
 837
 838         for_each_engine(engine, i915, id)
 839                 kfree(engine);
 840 }
 841
 842 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 843 {
 844         destroy_workqueue(dev_priv->hotplug.dp_wq);
 845         destroy_workqueue(dev_priv->wq);
 846 }
 847
 848 /*
 849  * We don't keep the workarounds for pre-production hardware, so we expect our
 850  * driver to fail on these machines in one way or another. A little warning on
 851  * dmesg may help both the user and the bug triagers.
 852  *
 853  * Our policy for removing pre-production workarounds is to keep the
 854  * current gen workarounds as a guide to the bring-up of the next gen
 855  * (workarounds have a habit of persisting!). Anything older than that
 856  * should be removed along with the complications they introduce.
 857  */
 858 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 859 {
 860         bool pre = false;
 861
 862         pre |= IS_HSW_EARLY_SDV(dev_priv);
 863         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 864         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 865         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 866
 867         if (pre) {
 868                 DRM_ERROR("This is a pre-production stepping. "
 869                           "It may not be fully functional.\n");
 870                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 871         }
 872 }
 873
 874 /**
 875  * i915_driver_init_early - setup state not requiring device access
 876  * @dev_priv: device private
 877  *
 878  * Initialize everything that is a "SW-only" state, that is state not
 879  * requiring accessing the device or exposing the driver via kernel internal
 880  * or userspace interfaces. Example steps belonging here: lock initialization,
 881  * system memory allocation, setting up device specific attributes and
 882  * function hooks not requiring accessing the device.
 883  */
 884 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 885 {
 886         int ret = 0;
 887
 888         if (i915_inject_load_failure())
 889                 return -ENODEV;
 890
 891         intel_device_info_subplatform_init(dev_priv);
 892
 893         intel_uncore_init_early(&dev_priv->uncore);
 894
 895         spin_lock_init(&dev_priv->irq_lock);
 896         spin_lock_init(&dev_priv->gpu_error.lock);
 897         mutex_init(&dev_priv->backlight_lock);
 898
 899         mutex_init(&dev_priv->sb_lock);
 900         pm_qos_add_request(&dev_priv->sb_qos,
 901                            PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
 902
 903         mutex_init(&dev_priv->av_mutex);
 904         mutex_init(&dev_priv->wm.wm_mutex);
 905         mutex_init(&dev_priv->pps_mutex);
 906         mutex_init(&dev_priv->hdcp_comp_mutex);
 907
 908         i915_memcpy_init_early(dev_priv);
 909         intel_runtime_pm_init_early(dev_priv);
 910
 911         ret = i915_workqueues_init(dev_priv);
 912         if (ret < 0)
 913                 goto err_engines;
 914
 915         ret = i915_gem_init_early(dev_priv);
 916         if (ret < 0)
 917                 goto err_workqueues;
 918
 919         /* This must be called before any calls to HAS_PCH_* */
 920         intel_detect_pch(dev_priv);
 921
 922         intel_wopcm_init_early(&dev_priv->wopcm);
 923         intel_uc_init_early(dev_priv);
 924         intel_pm_setup(dev_priv);
 925         intel_init_dpio(dev_priv);
 926         ret = intel_power_domains_init(dev_priv);
 927         if (ret < 0)
 928                 goto err_uc;
 929         intel_irq_init(dev_priv);
 930         intel_hangcheck_init(dev_priv);
 931         intel_init_display_hooks(dev_priv);
 932         intel_init_clock_gating_hooks(dev_priv);
 933         intel_init_audio_hooks(dev_priv);
 934         intel_display_crc_init(dev_priv);
 935
 936         intel_detect_preproduction_hw(dev_priv);
 937
 938         return 0;
 939
 940 err_uc:
 941         intel_uc_cleanup_early(dev_priv);
 942         i915_gem_cleanup_early(dev_priv);
 943 err_workqueues:
 944         i915_workqueues_cleanup(dev_priv);
 945 err_engines:
 946         i915_engines_cleanup(dev_priv);
 947         return ret;
 948 }
 949
 950 /**
 951  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 952  * @dev_priv: device private
 953  */
 954 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 955 {
 956         intel_irq_fini(dev_priv);
 957         intel_power_domains_cleanup(dev_priv);
 958         intel_uc_cleanup_early(dev_priv);
 959         i915_gem_cleanup_early(dev_priv);
 960         i915_workqueues_cleanup(dev_priv);
 961         i915_engines_cleanup(dev_priv);
 962
 963         pm_qos_remove_request(&dev_priv->sb_qos);
 964         mutex_destroy(&dev_priv->sb_lock);
 965 }
 966
 967 /**
 968  * i915_driver_init_mmio - setup device MMIO
 969  * @dev_priv: device private
 970  *
 971  * Setup minimal device state necessary for MMIO accesses later in the
 972  * initialization sequence. The setup here should avoid any other device-wide
 973  * side effects or exposing the driver via kernel internal or user space
 974  * interfaces.
 975  */
 976 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 977 {
 978         int ret;
 979
 980         if (i915_inject_load_failure())
 981                 return -ENODEV;
 982
 983         if (i915_get_bridge_dev(dev_priv))
 984                 return -EIO;
 985
 986         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 987         if (ret < 0)
 988                 goto err_bridge;
 989
 990         /* Try to make sure MCHBAR is enabled before poking at it */
 991         intel_setup_mchbar(dev_priv);
 992
 993         intel_device_info_init_mmio(dev_priv);
 994
 995         intel_uncore_prune_mmio_domains(&dev_priv->uncore);
 996
 997         intel_uc_init_mmio(dev_priv);
 998
 999         ret = intel_engines_init_mmio(dev_priv);
1000         if (ret)
1001                 goto err_uncore;
1002
1003         i915_gem_init_mmio(dev_priv);
1004
1005         return 0;
1006
1007 err_uncore:
1008         intel_teardown_mchbar(dev_priv);
1009         intel_uncore_fini_mmio(&dev_priv->uncore);
1010 err_bridge:
1011         pci_dev_put(dev_priv->bridge_dev);
1012
1013         return ret;
1014 }
1015
1016 /**
1017  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1018  * @dev_priv: device private
1019  */
1020 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1021 {
1022         intel_teardown_mchbar(dev_priv);
1023         intel_uncore_fini_mmio(&dev_priv->uncore);
1024         pci_dev_put(dev_priv->bridge_dev);
1025 }
1026
1027 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1028 {
1029         intel_gvt_sanitize_options(dev_priv);
1030 }
1031
1032 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
1033
1034 static const char *intel_dram_type_str(enum intel_dram_type type)
1035 {
1036         static const char * const str[] = {
1037                 DRAM_TYPE_STR(UNKNOWN),
1038                 DRAM_TYPE_STR(DDR3),
1039                 DRAM_TYPE_STR(DDR4),
1040                 DRAM_TYPE_STR(LPDDR3),
1041                 DRAM_TYPE_STR(LPDDR4),
1042         };
1043
1044         if (type >= ARRAY_SIZE(str))
1045                 type = INTEL_DRAM_UNKNOWN;
1046
1047         return str[type];
1048 }
1049
1050 #undef DRAM_TYPE_STR
1051
1052 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
1053 {
1054         return dimm->ranks * 64 / (dimm->width ?: 1);
1055 }
1056
1057 /* Returns total GB for the whole DIMM */
1058 static int skl_get_dimm_size(u16 val)
1059 {
1060         return val & SKL_DRAM_SIZE_MASK;
1061 }
1062
1063 static int skl_get_dimm_width(u16 val)
1064 {
1065         if (skl_get_dimm_size(val) == 0)
1066                 return 0;
1067
1068         switch (val & SKL_DRAM_WIDTH_MASK) {
1069         case SKL_DRAM_WIDTH_X8:
1070         case SKL_DRAM_WIDTH_X16:
1071         case SKL_DRAM_WIDTH_X32:
1072                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1073                 return 8 << val;
1074         default:
1075                 MISSING_CASE(val);
1076                 return 0;
1077         }
1078 }
1079
1080 static int skl_get_dimm_ranks(u16 val)
1081 {
1082         if (skl_get_dimm_size(val) == 0)
1083                 return 0;
1084
1085         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
1086
1087         return val + 1;
1088 }
1089
1090 /* Returns total GB for the whole DIMM */
1091 static int cnl_get_dimm_size(u16 val)
1092 {
1093         return (val & CNL_DRAM_SIZE_MASK) / 2;
1094 }
1095
1096 static int cnl_get_dimm_width(u16 val)
1097 {
1098         if (cnl_get_dimm_size(val) == 0)
1099                 return 0;
1100
1101         switch (val & CNL_DRAM_WIDTH_MASK) {
1102         case CNL_DRAM_WIDTH_X8:
1103         case CNL_DRAM_WIDTH_X16:
1104         case CNL_DRAM_WIDTH_X32:
1105                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
1106                 return 8 << val;
1107         default:
1108                 MISSING_CASE(val);
1109                 return 0;
1110         }
1111 }
1112
1113 static int cnl_get_dimm_ranks(u16 val)
1114 {
1115         if (cnl_get_dimm_size(val) == 0)
1116                 return 0;
1117
1118         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
1119
1120         return val + 1;
1121 }
1122
1123 static bool
1124 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
1125 {
1126         /* Convert total GB to Gb per DRAM device */
1127         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
1128 }
1129
1130 static void
1131 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
1132                        struct dram_dimm_info *dimm,
1133                        int channel, char dimm_name, u16 val)
1134 {
1135         if (INTEL_GEN(dev_priv) >= 10) {
1136                 dimm->size = cnl_get_dimm_size(val);
1137                 dimm->width = cnl_get_dimm_width(val);
1138                 dimm->ranks = cnl_get_dimm_ranks(val);
1139         } else {
1140                 dimm->size = skl_get_dimm_size(val);
1141                 dimm->width = skl_get_dimm_width(val);
1142                 dimm->ranks = skl_get_dimm_ranks(val);
1143         }
1144
1145         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
1146                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
1147                       yesno(skl_is_16gb_dimm(dimm)));
1148 }
1149
1150 static int
1151 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
1152                           struct dram_channel_info *ch,
1153                           int channel, u32 val)
1154 {
1155         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
1156                                channel, 'L', val & 0xffff);
1157         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
1158                                channel, 'S', val >> 16);
1159
1160         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
1161                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
1162                 return -EINVAL;
1163         }
1164
1165         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
1166                 ch->ranks = 2;
1167         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
1168                 ch->ranks = 2;
1169         else
1170                 ch->ranks = 1;
1171
1172         ch->is_16gb_dimm =
1173                 skl_is_16gb_dimm(&ch->dimm_l) ||
1174                 skl_is_16gb_dimm(&ch->dimm_s);
1175
1176         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
1177                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
1178
1179         return 0;
1180 }
1181
1182 static bool
1183 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
1184                         const struct dram_channel_info *ch1)
1185 {
1186         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
1187                 (ch0->dimm_s.size == 0 ||
1188                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
1189 }
1190
1191 static int
1192 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1193 {
1194         struct dram_info *dram_info = &dev_priv->dram_info;
1195         struct dram_channel_info ch0 = {}, ch1 = {};
1196         u32 val;
1197         int ret;
1198
1199         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1200         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
1201         if (ret == 0)
1202                 dram_info->num_channels++;
1203
1204         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1205         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
1206         if (ret == 0)
1207                 dram_info->num_channels++;
1208
1209         if (dram_info->num_channels == 0) {
1210                 DRM_INFO("Number of memory channels is zero\n");
1211                 return -EINVAL;
1212         }
1213
1214         /*
1215          * If any of the channel is single rank channel, worst case output
1216          * will be same as if single rank memory, so consider single rank
1217          * memory.
1218          */
1219         if (ch0.ranks == 1 || ch1.ranks == 1)
1220                 dram_info->ranks = 1;
1221         else
1222                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
1223
1224         if (dram_info->ranks == 0) {
1225                 DRM_INFO("couldn't get memory rank information\n");
1226                 return -EINVAL;
1227         }
1228
1229         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1230
1231         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
1232
1233         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
1234                       yesno(dram_info->symmetric_memory));
1235         return 0;
1236 }
1237
1238 static enum intel_dram_type
1239 skl_get_dram_type(struct drm_i915_private *dev_priv)
1240 {
1241         u32 val;
1242
1243         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
1244
1245         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
1246         case SKL_DRAM_DDR_TYPE_DDR3:
1247                 return INTEL_DRAM_DDR3;
1248         case SKL_DRAM_DDR_TYPE_DDR4:
1249                 return INTEL_DRAM_DDR4;
1250         case SKL_DRAM_DDR_TYPE_LPDDR3:
1251                 return INTEL_DRAM_LPDDR3;
1252         case SKL_DRAM_DDR_TYPE_LPDDR4:
1253                 return INTEL_DRAM_LPDDR4;
1254         default:
1255                 MISSING_CASE(val);
1256                 return INTEL_DRAM_UNKNOWN;
1257         }
1258 }
1259
1260 static int
1261 skl_get_dram_info(struct drm_i915_private *dev_priv)
1262 {
1263         struct dram_info *dram_info = &dev_priv->dram_info;
1264         u32 mem_freq_khz, val;
1265         int ret;
1266
1267         dram_info->type = skl_get_dram_type(dev_priv);
1268         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
1269
1270         ret = skl_dram_get_channels_info(dev_priv);
1271         if (ret)
1272                 return ret;
1273
1274         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1275         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1276                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1277
1278         dram_info->bandwidth_kbps = dram_info->num_channels *
1279                                                         mem_freq_khz * 8;
1280
1281         if (dram_info->bandwidth_kbps == 0) {
1282                 DRM_INFO("Couldn't get system memory bandwidth\n");
1283                 return -EINVAL;
1284         }
1285
1286         dram_info->valid = true;
1287         return 0;
1288 }
1289
1290 /* Returns Gb per DRAM device */
1291 static int bxt_get_dimm_size(u32 val)
1292 {
1293         switch (val & BXT_DRAM_SIZE_MASK) {
1294         case BXT_DRAM_SIZE_4GBIT:
1295                 return 4;
1296         case BXT_DRAM_SIZE_6GBIT:
1297                 return 6;
1298         case BXT_DRAM_SIZE_8GBIT:
1299                 return 8;
1300         case BXT_DRAM_SIZE_12GBIT:
1301                 return 12;
1302         case BXT_DRAM_SIZE_16GBIT:
1303                 return 16;
1304         default:
1305                 MISSING_CASE(val);
1306                 return 0;
1307         }
1308 }
1309
1310 static int bxt_get_dimm_width(u32 val)
1311 {
1312         if (!bxt_get_dimm_size(val))
1313                 return 0;
1314
1315         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1316
1317         return 8 << val;
1318 }
1319
1320 static int bxt_get_dimm_ranks(u32 val)
1321 {
1322         if (!bxt_get_dimm_size(val))
1323                 return 0;
1324
1325         switch (val & BXT_DRAM_RANK_MASK) {
1326         case BXT_DRAM_RANK_SINGLE:
1327                 return 1;
1328         case BXT_DRAM_RANK_DUAL:
1329                 return 2;
1330         default:
1331                 MISSING_CASE(val);
1332                 return 0;
1333         }
1334 }
1335
1336 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1337 {
1338         if (!bxt_get_dimm_size(val))
1339                 return INTEL_DRAM_UNKNOWN;
1340
1341         switch (val & BXT_DRAM_TYPE_MASK) {
1342         case BXT_DRAM_TYPE_DDR3:
1343                 return INTEL_DRAM_DDR3;
1344         case BXT_DRAM_TYPE_LPDDR3:
1345                 return INTEL_DRAM_LPDDR3;
1346         case BXT_DRAM_TYPE_DDR4:
1347                 return INTEL_DRAM_DDR4;
1348         case BXT_DRAM_TYPE_LPDDR4:
1349                 return INTEL_DRAM_LPDDR4;
1350         default:
1351                 MISSING_CASE(val);
1352                 return INTEL_DRAM_UNKNOWN;
1353         }
1354 }
1355
1356 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1357                               u32 val)
1358 {
1359         dimm->width = bxt_get_dimm_width(val);
1360         dimm->ranks = bxt_get_dimm_ranks(val);
1361
1362         /*
1363          * Size in register is Gb per DRAM device. Convert to total
1364          * GB to match the way we report this for non-LP platforms.
1365          */
1366         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1367 }
1368
1369 static int
1370 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1371 {
1372         struct dram_info *dram_info = &dev_priv->dram_info;
1373         u32 dram_channels;
1374         u32 mem_freq_khz, val;
1375         u8 num_active_channels;
1376         int i;
1377
1378         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1379         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1380                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1381
1382         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1383         num_active_channels = hweight32(dram_channels);
1384
1385         /* Each active bit represents 4-byte channel */
1386         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1387
1388         if (dram_info->bandwidth_kbps == 0) {
1389                 DRM_INFO("Couldn't get system memory bandwidth\n");
1390                 return -EINVAL;
1391         }
1392
1393         /*
1394          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1395          */
1396         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1397                 struct dram_dimm_info dimm;
1398                 enum intel_dram_type type;
1399
1400                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1401                 if (val == 0xFFFFFFFF)
1402                         continue;
1403
1404                 dram_info->num_channels++;
1405
1406                 bxt_get_dimm_info(&dimm, val);
1407                 type = bxt_get_dimm_type(val);
1408
1409                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1410                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1411                         dram_info->type != type);
1412
1413                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1414                               i - BXT_D_CR_DRP0_DUNIT_START,
1415                               dimm.size, dimm.width, dimm.ranks,
1416                               intel_dram_type_str(type));
1417
1418                 /*
1419                  * If any of the channel is single rank channel,
1420                  * worst case output will be same as if single rank
1421                  * memory, so consider single rank memory.
1422                  */
1423                 if (dram_info->ranks == 0)
1424                         dram_info->ranks = dimm.ranks;
1425                 else if (dimm.ranks == 1)
1426                         dram_info->ranks = 1;
1427
1428                 if (type != INTEL_DRAM_UNKNOWN)
1429                         dram_info->type = type;
1430         }
1431
1432         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1433             dram_info->ranks == 0) {
1434                 DRM_INFO("couldn't get memory information\n");
1435                 return -EINVAL;
1436         }
1437
1438         dram_info->valid = true;
1439         return 0;
1440 }
1441
1442 static void
1443 intel_get_dram_info(struct drm_i915_private *dev_priv)
1444 {
1445         struct dram_info *dram_info = &dev_priv->dram_info;
1446         int ret;
1447
1448         /*
1449          * Assume 16Gb DIMMs are present until proven otherwise.
1450          * This is only used for the level 0 watermark latency
1451          * w/a which does not apply to bxt/glk.
1452          */
1453         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1454
1455         if (INTEL_GEN(dev_priv) < 9)
1456                 return;
1457
1458         if (IS_GEN9_LP(dev_priv))
1459                 ret = bxt_get_dram_info(dev_priv);
1460         else
1461                 ret = skl_get_dram_info(dev_priv);
1462         if (ret)
1463                 return;
1464
1465         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1466                       dram_info->bandwidth_kbps,
1467                       dram_info->num_channels);
1468
1469         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1470                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1471 }
1472
1473 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1474 {
1475         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1476         const unsigned int sets[4] = { 1, 1, 2, 2 };
1477
1478         return EDRAM_NUM_BANKS(cap) *
1479                 ways[EDRAM_WAYS_IDX(cap)] *
1480                 sets[EDRAM_SETS_IDX(cap)];
1481 }
1482
1483 static void edram_detect(struct drm_i915_private *dev_priv)
1484 {
1485         u32 edram_cap = 0;
1486
1487         if (!(IS_HASWELL(dev_priv) ||
1488               IS_BROADWELL(dev_priv) ||
1489               INTEL_GEN(dev_priv) >= 9))
1490                 return;
1491
1492         edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1493
1494         /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1495
1496         if (!(edram_cap & EDRAM_ENABLED))
1497                 return;
1498
1499         /*
1500          * The needed capability bits for size calculation are not there with
1501          * pre gen9 so return 128MB always.
1502          */
1503         if (INTEL_GEN(dev_priv) < 9)
1504                 dev_priv->edram_size_mb = 128;
1505         else
1506                 dev_priv->edram_size_mb =
1507                         gen9_edram_size_mb(dev_priv, edram_cap);
1508
1509         DRM_INFO("Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1510 }
1511
1512 /**
1513  * i915_driver_init_hw - setup state requiring device access
1514  * @dev_priv: device private
1515  *
1516  * Setup state that requires accessing the device, but doesn't require
1517  * exposing the driver via kernel internal or userspace interfaces.
1518  */
1519 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1520 {
1521         struct pci_dev *pdev = dev_priv->drm.pdev;
1522         int ret;
1523
1524         if (i915_inject_load_failure())
1525                 return -ENODEV;
1526
1527         intel_device_info_runtime_init(dev_priv);
1528
1529         if (HAS_PPGTT(dev_priv)) {
1530                 if (intel_vgpu_active(dev_priv) &&
1531                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1532                         i915_report_error(dev_priv,
1533                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1534                         return -ENXIO;
1535                 }
1536         }
1537
1538         if (HAS_EXECLISTS(dev_priv)) {
1539                 /*
1540                  * Older GVT emulation depends upon intercepting CSB mmio,
1541                  * which we no longer use, preferring to use the HWSP cache
1542                  * instead.
1543                  */
1544                 if (intel_vgpu_active(dev_priv) &&
1545                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1546                         i915_report_error(dev_priv,
1547                                           "old vGPU host found, support for HWSP emulation required\n");
1548                         return -ENXIO;
1549                 }
1550         }
1551
1552         intel_sanitize_options(dev_priv);
1553
1554         /* needs to be done before ggtt probe */
1555         edram_detect(dev_priv);
1556
1557         i915_perf_init(dev_priv);
1558
1559         ret = i915_ggtt_probe_hw(dev_priv);
1560         if (ret)
1561                 goto err_perf;
1562
1563         /*
1564          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1565          * otherwise the vga fbdev driver falls over.
1566          */
1567         ret = i915_kick_out_firmware_fb(dev_priv);
1568         if (ret) {
1569                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1570                 goto err_ggtt;
1571         }
1572
1573         ret = vga_remove_vgacon(pdev);
1574         if (ret) {
1575                 DRM_ERROR("failed to remove conflicting VGA console\n");
1576                 goto err_ggtt;
1577         }
1578
1579         ret = i915_ggtt_init_hw(dev_priv);
1580         if (ret)
1581                 goto err_ggtt;
1582
1583         ret = i915_ggtt_enable_hw(dev_priv);
1584         if (ret) {
1585                 DRM_ERROR("failed to enable GGTT\n");
1586                 goto err_ggtt;
1587         }
1588
1589         pci_set_master(pdev);
1590
1591         /* overlay on gen2 is broken and can't address above 1G */
1592         if (IS_GEN(dev_priv, 2)) {
1593                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1594                 if (ret) {
1595                         DRM_ERROR("failed to set DMA mask\n");
1596
1597                         goto err_ggtt;
1598                 }
1599         }
1600
1601         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1602          * using 32bit addressing, overwriting memory if HWS is located
1603          * above 4GB.
1604          *
1605          * The documentation also mentions an issue with undefined
1606          * behaviour if any general state is accessed within a page above 4GB,
1607          * which also needs to be handled carefully.
1608          */
1609         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1610                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1611
1612                 if (ret) {
1613                         DRM_ERROR("failed to set DMA mask\n");
1614
1615                         goto err_ggtt;
1616                 }
1617         }
1618
1619         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1620                            PM_QOS_DEFAULT_VALUE);
1621
1622         intel_uncore_sanitize(dev_priv);
1623
1624         intel_gt_init_workarounds(dev_priv);
1625         i915_gem_load_init_fences(dev_priv);
1626
1627         /* On the 945G/GM, the chipset reports the MSI capability on the
1628          * integrated graphics even though the support isn't actually there
1629          * according to the published specs.  It doesn't appear to function
1630          * correctly in testing on 945G.
1631          * This may be a side effect of MSI having been made available for PEG
1632          * and the registers being closely associated.
1633          *
1634          * According to chipset errata, on the 965GM, MSI interrupts may
1635          * be lost or delayed, and was defeatured. MSI interrupts seem to
1636          * get lost on g4x as well, and interrupt delivery seems to stay
1637          * properly dead afterwards. So we'll just disable them for all
1638          * pre-gen5 chipsets.
1639          *
1640          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1641          * interrupts even when in MSI mode. This results in spurious
1642          * interrupt warnings if the legacy irq no. is shared with another
1643          * device. The kernel then disables that interrupt source and so
1644          * prevents the other device from working properly.
1645          */
1646         if (INTEL_GEN(dev_priv) >= 5) {
1647                 if (pci_enable_msi(pdev) < 0)
1648                         DRM_DEBUG_DRIVER("can't enable MSI");
1649         }
1650
1651         ret = intel_gvt_init(dev_priv);
1652         if (ret)
1653                 goto err_msi;
1654
1655         intel_opregion_setup(dev_priv);
1656         /*
1657          * Fill the dram structure to get the system raw bandwidth and
1658          * dram info. This will be used for memory latency calculation.
1659          */
1660         intel_get_dram_info(dev_priv);
1661
1662         intel_bw_init_hw(dev_priv);
1663
1664         return 0;
1665
1666 err_msi:
1667         if (pdev->msi_enabled)
1668                 pci_disable_msi(pdev);
1669         pm_qos_remove_request(&dev_priv->pm_qos);
1670 err_ggtt:
1671         i915_ggtt_cleanup_hw(dev_priv);
1672 err_perf:
1673         i915_perf_fini(dev_priv);
1674         return ret;
1675 }
1676
1677 /**
1678  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1679  * @dev_priv: device private
1680  */
1681 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1682 {
1683         struct pci_dev *pdev = dev_priv->drm.pdev;
1684
1685         i915_perf_fini(dev_priv);
1686
1687         if (pdev->msi_enabled)
1688                 pci_disable_msi(pdev);
1689
1690         pm_qos_remove_request(&dev_priv->pm_qos);
1691         i915_ggtt_cleanup_hw(dev_priv);
1692 }
1693
1694 /**
1695  * i915_driver_register - register the driver with the rest of the system
1696  * @dev_priv: device private
1697  *
1698  * Perform any steps necessary to make the driver available via kernel
1699  * internal or userspace interfaces.
1700  */
1701 static void i915_driver_register(struct drm_i915_private *dev_priv)
1702 {
1703         struct drm_device *dev = &dev_priv->drm;
1704
1705         i915_gem_shrinker_register(dev_priv);
1706         i915_pmu_register(dev_priv);
1707
1708         /*
1709          * Notify a valid surface after modesetting,
1710          * when running inside a VM.
1711          */
1712         if (intel_vgpu_active(dev_priv))
1713                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1714
1715         /* Reveal our presence to userspace */
1716         if (drm_dev_register(dev, 0) == 0) {
1717                 i915_debugfs_register(dev_priv);
1718                 i915_setup_sysfs(dev_priv);
1719
1720                 /* Depends on sysfs having been initialized */
1721                 i915_perf_register(dev_priv);
1722         } else
1723                 DRM_ERROR("Failed to register driver for userspace access!\n");
1724
1725         if (HAS_DISPLAY(dev_priv)) {
1726                 /* Must be done after probing outputs */
1727                 intel_opregion_register(dev_priv);
1728                 acpi_video_register();
1729         }
1730
1731         if (IS_GEN(dev_priv, 5))
1732                 intel_gpu_ips_init(dev_priv);
1733
1734         intel_audio_init(dev_priv);
1735
1736         /*
1737          * Some ports require correctly set-up hpd registers for detection to
1738          * work properly (leading to ghost connected connector status), e.g. VGA
1739          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1740          * irqs are fully enabled. We do it last so that the async config
1741          * cannot run before the connectors are registered.
1742          */
1743         intel_fbdev_initial_config_async(dev);
1744
1745         /*
1746          * We need to coordinate the hotplugs with the asynchronous fbdev
1747          * configuration, for which we use the fbdev->async_cookie.
1748          */
1749         if (HAS_DISPLAY(dev_priv))
1750                 drm_kms_helper_poll_init(dev);
1751
1752         intel_power_domains_enable(dev_priv);
1753         intel_runtime_pm_enable(dev_priv);
1754 }
1755
1756 /**
1757  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1758  * @dev_priv: device private
1759  */
1760 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1761 {
1762         intel_runtime_pm_disable(dev_priv);
1763         intel_power_domains_disable(dev_priv);
1764
1765         intel_fbdev_unregister(dev_priv);
1766         intel_audio_deinit(dev_priv);
1767
1768         /*
1769          * After flushing the fbdev (incl. a late async config which will
1770          * have delayed queuing of a hotplug event), then flush the hotplug
1771          * events.
1772          */
1773         drm_kms_helper_poll_fini(&dev_priv->drm);
1774
1775         intel_gpu_ips_teardown();
1776         acpi_video_unregister();
1777         intel_opregion_unregister(dev_priv);
1778
1779         i915_perf_unregister(dev_priv);
1780         i915_pmu_unregister(dev_priv);
1781
1782         i915_teardown_sysfs(dev_priv);
1783         drm_dev_unplug(&dev_priv->drm);
1784
1785         i915_gem_shrinker_unregister(dev_priv);
1786 }
1787
1788 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1789 {
1790         if (drm_debug & DRM_UT_DRIVER) {
1791                 struct drm_printer p = drm_debug_printer("i915 device info:");
1792
1793                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1794                            INTEL_DEVID(dev_priv),
1795                            INTEL_REVID(dev_priv),
1796                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1797                            intel_subplatform(RUNTIME_INFO(dev_priv),
1798                                              INTEL_INFO(dev_priv)->platform),
1799                            INTEL_GEN(dev_priv));
1800
1801                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1802                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1803         }
1804
1805         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1806                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1807         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1808                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1809         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1810                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1811 }
1812
1813 static struct drm_i915_private *
1814 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1815 {
1816         const struct intel_device_info *match_info =
1817                 (struct intel_device_info *)ent->driver_data;
1818         struct intel_device_info *device_info;
1819         struct drm_i915_private *i915;
1820         int err;
1821
1822         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1823         if (!i915)
1824                 return ERR_PTR(-ENOMEM);
1825
1826         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1827         if (err) {
1828                 kfree(i915);
1829                 return ERR_PTR(err);
1830         }
1831
1832         i915->drm.pdev = pdev;
1833         i915->drm.dev_private = i915;
1834         pci_set_drvdata(pdev, &i915->drm);
1835
1836         /* Setup the write-once "constant" device info */
1837         device_info = mkwrite_device_info(i915);
1838         memcpy(device_info, match_info, sizeof(*device_info));
1839         RUNTIME_INFO(i915)->device_id = pdev->device;
1840
1841         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1842
1843         return i915;
1844 }
1845
1846 static void i915_driver_destroy(struct drm_i915_private *i915)
1847 {
1848         struct pci_dev *pdev = i915->drm.pdev;
1849
1850         drm_dev_fini(&i915->drm);
1851         kfree(i915);
1852
1853         /* And make sure we never chase our dangling pointer from pci_dev */
1854         pci_set_drvdata(pdev, NULL);
1855 }
1856
1857 /**
1858  * i915_driver_load - setup chip and create an initial config
1859  * @pdev: PCI device
1860  * @ent: matching PCI ID entry
1861  *
1862  * The driver load routine has to do several things:
1863  *   - drive output discovery via intel_modeset_init()
1864  *   - initialize the memory manager
1865  *   - allocate initial config memory
1866  *   - setup the DRM framebuffer with the allocated memory
1867  */
1868 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1869 {
1870         const struct intel_device_info *match_info =
1871                 (struct intel_device_info *)ent->driver_data;
1872         struct drm_i915_private *dev_priv;
1873         int ret;
1874
1875         dev_priv = i915_driver_create(pdev, ent);
1876         if (IS_ERR(dev_priv))
1877                 return PTR_ERR(dev_priv);
1878
1879         /* Disable nuclear pageflip by default on pre-ILK */
1880         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1881                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1882
1883         ret = pci_enable_device(pdev);
1884         if (ret)
1885                 goto out_fini;
1886
1887         ret = i915_driver_init_early(dev_priv);
1888         if (ret < 0)
1889                 goto out_pci_disable;
1890
1891         disable_rpm_wakeref_asserts(dev_priv);
1892
1893         ret = i915_driver_init_mmio(dev_priv);
1894         if (ret < 0)
1895                 goto out_runtime_pm_put;
1896
1897         ret = i915_driver_init_hw(dev_priv);
1898         if (ret < 0)
1899                 goto out_cleanup_mmio;
1900
1901         ret = i915_load_modeset_init(&dev_priv->drm);
1902         if (ret < 0)
1903                 goto out_cleanup_hw;
1904
1905         i915_driver_register(dev_priv);
1906
1907         enable_rpm_wakeref_asserts(dev_priv);
1908
1909         i915_welcome_messages(dev_priv);
1910
1911         return 0;
1912
1913 out_cleanup_hw:
1914         i915_driver_cleanup_hw(dev_priv);
1915 out_cleanup_mmio:
1916         i915_driver_cleanup_mmio(dev_priv);
1917 out_runtime_pm_put:
1918         enable_rpm_wakeref_asserts(dev_priv);
1919         i915_driver_cleanup_early(dev_priv);
1920 out_pci_disable:
1921         pci_disable_device(pdev);
1922 out_fini:
1923         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1924         i915_driver_destroy(dev_priv);
1925         return ret;
1926 }
1927
1928 void i915_driver_unload(struct drm_device *dev)
1929 {
1930         struct drm_i915_private *dev_priv = to_i915(dev);
1931         struct pci_dev *pdev = dev_priv->drm.pdev;
1932
1933         disable_rpm_wakeref_asserts(dev_priv);
1934
1935         i915_driver_unregister(dev_priv);
1936
1937         /*
1938          * After unregistering the device to prevent any new users, cancel
1939          * all in-flight requests so that we can quickly unbind the active
1940          * resources.
1941          */
1942         i915_gem_set_wedged(dev_priv);
1943
1944         /* Flush any external code that still may be under the RCU lock */
1945         synchronize_rcu();
1946
1947         i915_gem_suspend(dev_priv);
1948
1949         drm_atomic_helper_shutdown(dev);
1950
1951         intel_gvt_cleanup(dev_priv);
1952
1953         intel_modeset_cleanup(dev);
1954
1955         intel_bios_cleanup(dev_priv);
1956
1957         vga_switcheroo_unregister_client(pdev);
1958         vga_client_register(pdev, NULL, NULL, NULL);
1959
1960         intel_csr_ucode_fini(dev_priv);
1961
1962         /* Free error state after interrupts are fully disabled. */
1963         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1964         i915_reset_error_state(dev_priv);
1965
1966         i915_gem_fini(dev_priv);
1967
1968         intel_power_domains_fini_hw(dev_priv);
1969
1970         i915_driver_cleanup_hw(dev_priv);
1971         i915_driver_cleanup_mmio(dev_priv);
1972
1973         enable_rpm_wakeref_asserts(dev_priv);
1974         intel_runtime_pm_cleanup(dev_priv);
1975 }
1976
1977 static void i915_driver_release(struct drm_device *dev)
1978 {
1979         struct drm_i915_private *dev_priv = to_i915(dev);
1980
1981         i915_driver_cleanup_early(dev_priv);
1982         i915_driver_destroy(dev_priv);
1983 }
1984
1985 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1986 {
1987         struct drm_i915_private *i915 = to_i915(dev);
1988         int ret;
1989
1990         ret = i915_gem_open(i915, file);
1991         if (ret)
1992                 return ret;
1993
1994         return 0;
1995 }
1996
1997 /**
1998  * i915_driver_lastclose - clean up after all DRM clients have exited
1999  * @dev: DRM device
2000  *
2001  * Take care of cleaning up after all DRM clients have exited.  In the
2002  * mode setting case, we want to restore the kernel's initial mode (just
2003  * in case the last client left us in a bad state).
2004  *
2005  * Additionally, in the non-mode setting case, we'll tear down the GTT
2006  * and DMA structures, since the kernel won't be using them, and clea
2007  * up any GEM state.
2008  */
2009 static void i915_driver_lastclose(struct drm_device *dev)
2010 {
2011         intel_fbdev_restore_mode(dev);
2012         vga_switcheroo_process_delayed_switch();
2013 }
2014
2015 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2016 {
2017         struct drm_i915_file_private *file_priv = file->driver_priv;
2018
2019         mutex_lock(&dev->struct_mutex);
2020         i915_gem_context_close(file);
2021         i915_gem_release(dev, file);
2022         mutex_unlock(&dev->struct_mutex);
2023
2024         kfree(file_priv);
2025 }
2026
2027 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
2028 {
2029         struct drm_device *dev = &dev_priv->drm;
2030         struct intel_encoder *encoder;
2031
2032         drm_modeset_lock_all(dev);
2033         for_each_intel_encoder(dev, encoder)
2034                 if (encoder->suspend)
2035                         encoder->suspend(encoder);
2036         drm_modeset_unlock_all(dev);
2037 }
2038
2039 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2040                               bool rpm_resume);
2041 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
2042
2043 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
2044 {
2045 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
2046         if (acpi_target_system_state() < ACPI_STATE_S3)
2047                 return true;
2048 #endif
2049         return false;
2050 }
2051
2052 static int i915_drm_prepare(struct drm_device *dev)
2053 {
2054         struct drm_i915_private *i915 = to_i915(dev);
2055
2056         /*
2057          * NB intel_display_suspend() may issue new requests after we've
2058          * ostensibly marked the GPU as ready-to-sleep here. We need to
2059          * split out that work and pull it forward so that after point,
2060          * the GPU is not woken again.
2061          */
2062         i915_gem_suspend(i915);
2063
2064         return 0;
2065 }
2066
2067 static int i915_drm_suspend(struct drm_device *dev)
2068 {
2069         struct drm_i915_private *dev_priv = to_i915(dev);
2070         struct pci_dev *pdev = dev_priv->drm.pdev;
2071         pci_power_t opregion_target_state;
2072
2073         disable_rpm_wakeref_asserts(dev_priv);
2074
2075         /* We do a lot of poking in a lot of registers, make sure they work
2076          * properly. */
2077         intel_power_domains_disable(dev_priv);
2078
2079         drm_kms_helper_poll_disable(dev);
2080
2081         pci_save_state(pdev);
2082
2083         intel_display_suspend(dev);
2084
2085         intel_dp_mst_suspend(dev_priv);
2086
2087         intel_runtime_pm_disable_interrupts(dev_priv);
2088         intel_hpd_cancel_work(dev_priv);
2089
2090         intel_suspend_encoders(dev_priv);
2091
2092         intel_suspend_hw(dev_priv);
2093
2094         i915_gem_suspend_gtt_mappings(dev_priv);
2095
2096         i915_save_state(dev_priv);
2097
2098         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
2099         intel_opregion_suspend(dev_priv, opregion_target_state);
2100
2101         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
2102
2103         dev_priv->suspend_count++;
2104
2105         intel_csr_ucode_suspend(dev_priv);
2106
2107         enable_rpm_wakeref_asserts(dev_priv);
2108
2109         return 0;
2110 }
2111
2112 static enum i915_drm_suspend_mode
2113 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
2114 {
2115         if (hibernate)
2116                 return I915_DRM_SUSPEND_HIBERNATE;
2117
2118         if (suspend_to_idle(dev_priv))
2119                 return I915_DRM_SUSPEND_IDLE;
2120
2121         return I915_DRM_SUSPEND_MEM;
2122 }
2123
2124 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
2125 {
2126         struct drm_i915_private *dev_priv = to_i915(dev);
2127         struct pci_dev *pdev = dev_priv->drm.pdev;
2128         int ret;
2129
2130         disable_rpm_wakeref_asserts(dev_priv);
2131
2132         i915_gem_suspend_late(dev_priv);
2133
2134         intel_uncore_suspend(&dev_priv->uncore);
2135
2136         intel_power_domains_suspend(dev_priv,
2137                                     get_suspend_mode(dev_priv, hibernation));
2138
2139         ret = 0;
2140         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
2141                 bxt_enable_dc9(dev_priv);
2142         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2143                 hsw_enable_pc8(dev_priv);
2144         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2145                 ret = vlv_suspend_complete(dev_priv);
2146
2147         if (ret) {
2148                 DRM_ERROR("Suspend complete failed: %d\n", ret);
2149                 intel_power_domains_resume(dev_priv);
2150
2151                 goto out;
2152         }
2153
2154         pci_disable_device(pdev);
2155         /*
2156          * During hibernation on some platforms the BIOS may try to access
2157          * the device even though it's already in D3 and hang the machine. So
2158          * leave the device in D0 on those platforms and hope the BIOS will
2159          * power down the device properly. The issue was seen on multiple old
2160          * GENs with different BIOS vendors, so having an explicit blacklist
2161          * is inpractical; apply the workaround on everything pre GEN6. The
2162          * platforms where the issue was seen:
2163          * Lenovo Thinkpad X301, X61s, X60, T60, X41
2164          * Fujitsu FSC S7110
2165          * Acer Aspire 1830T
2166          */
2167         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
2168                 pci_set_power_state(pdev, PCI_D3hot);
2169
2170 out:
2171         enable_rpm_wakeref_asserts(dev_priv);
2172         if (!dev_priv->uncore.user_forcewake.count)
2173                 intel_runtime_pm_cleanup(dev_priv);
2174
2175         return ret;
2176 }
2177
2178 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2179 {
2180         int error;
2181
2182         if (!dev) {
2183                 DRM_ERROR("dev: %p\n", dev);
2184                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2185                 return -ENODEV;
2186         }
2187
2188         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2189                          state.event != PM_EVENT_FREEZE))
2190                 return -EINVAL;
2191
2192         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2193                 return 0;
2194
2195         error = i915_drm_suspend(dev);
2196         if (error)
2197                 return error;
2198
2199         return i915_drm_suspend_late(dev, false);
2200 }
2201
2202 static int i915_drm_resume(struct drm_device *dev)
2203 {
2204         struct drm_i915_private *dev_priv = to_i915(dev);
2205         int ret;
2206
2207         disable_rpm_wakeref_asserts(dev_priv);
2208         intel_sanitize_gt_powersave(dev_priv);
2209
2210         i915_gem_sanitize(dev_priv);
2211
2212         ret = i915_ggtt_enable_hw(dev_priv);
2213         if (ret)
2214                 DRM_ERROR("failed to re-enable GGTT\n");
2215
2216         intel_csr_ucode_resume(dev_priv);
2217
2218         i915_restore_state(dev_priv);
2219         intel_pps_unlock_regs_wa(dev_priv);
2220
2221         intel_init_pch_refclk(dev_priv);
2222
2223         /*
2224          * Interrupts have to be enabled before any batches are run. If not the
2225          * GPU will hang. i915_gem_init_hw() will initiate batches to
2226          * update/restore the context.
2227          *
2228          * drm_mode_config_reset() needs AUX interrupts.
2229          *
2230          * Modeset enabling in intel_modeset_init_hw() also needs working
2231          * interrupts.
2232          */
2233         intel_runtime_pm_enable_interrupts(dev_priv);
2234
2235         drm_mode_config_reset(dev);
2236
2237         i915_gem_resume(dev_priv);
2238
2239         intel_modeset_init_hw(dev);
2240         intel_init_clock_gating(dev_priv);
2241
2242         spin_lock_irq(&dev_priv->irq_lock);
2243         if (dev_priv->display.hpd_irq_setup)
2244                 dev_priv->display.hpd_irq_setup(dev_priv);
2245         spin_unlock_irq(&dev_priv->irq_lock);
2246
2247         intel_dp_mst_resume(dev_priv);
2248
2249         intel_display_resume(dev);
2250
2251         drm_kms_helper_poll_enable(dev);
2252
2253         /*
2254          * ... but also need to make sure that hotplug processing
2255          * doesn't cause havoc. Like in the driver load code we don't
2256          * bother with the tiny race here where we might lose hotplug
2257          * notifications.
2258          * */
2259         intel_hpd_init(dev_priv);
2260
2261         intel_opregion_resume(dev_priv);
2262
2263         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2264
2265         intel_power_domains_enable(dev_priv);
2266
2267         enable_rpm_wakeref_asserts(dev_priv);
2268
2269         return 0;
2270 }
2271
2272 static int i915_drm_resume_early(struct drm_device *dev)
2273 {
2274         struct drm_i915_private *dev_priv = to_i915(dev);
2275         struct pci_dev *pdev = dev_priv->drm.pdev;
2276         int ret;
2277
2278         /*
2279          * We have a resume ordering issue with the snd-hda driver also
2280          * requiring our device to be power up. Due to the lack of a
2281          * parent/child relationship we currently solve this with an early
2282          * resume hook.
2283          *
2284          * FIXME: This should be solved with a special hdmi sink device or
2285          * similar so that power domains can be employed.
2286          */
2287
2288         /*
2289          * Note that we need to set the power state explicitly, since we
2290          * powered off the device during freeze and the PCI core won't power
2291          * it back up for us during thaw. Powering off the device during
2292          * freeze is not a hard requirement though, and during the
2293          * suspend/resume phases the PCI core makes sure we get here with the
2294          * device powered on. So in case we change our freeze logic and keep
2295          * the device powered we can also remove the following set power state
2296          * call.
2297          */
2298         ret = pci_set_power_state(pdev, PCI_D0);
2299         if (ret) {
2300                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2301                 return ret;
2302         }
2303
2304         /*
2305          * Note that pci_enable_device() first enables any parent bridge
2306          * device and only then sets the power state for this device. The
2307          * bridge enabling is a nop though, since bridge devices are resumed
2308          * first. The order of enabling power and enabling the device is
2309          * imposed by the PCI core as described above, so here we preserve the
2310          * same order for the freeze/thaw phases.
2311          *
2312          * TODO: eventually we should remove pci_disable_device() /
2313          * pci_enable_enable_device() from suspend/resume. Due to how they
2314          * depend on the device enable refcount we can't anyway depend on them
2315          * disabling/enabling the device.
2316          */
2317         if (pci_enable_device(pdev))
2318                 return -EIO;
2319
2320         pci_set_master(pdev);
2321
2322         disable_rpm_wakeref_asserts(dev_priv);
2323
2324         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2325                 ret = vlv_resume_prepare(dev_priv, false);
2326         if (ret)
2327                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2328                           ret);
2329
2330         intel_uncore_resume_early(&dev_priv->uncore);
2331
2332         i915_check_and_clear_faults(dev_priv);
2333
2334         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2335                 gen9_sanitize_dc_state(dev_priv);
2336                 bxt_disable_dc9(dev_priv);
2337         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2338                 hsw_disable_pc8(dev_priv);
2339         }
2340
2341         intel_uncore_sanitize(dev_priv);
2342
2343         intel_power_domains_resume(dev_priv);
2344
2345         intel_gt_sanitize(dev_priv, true);
2346
2347         enable_rpm_wakeref_asserts(dev_priv);
2348
2349         return ret;
2350 }
2351
2352 static int i915_resume_switcheroo(struct drm_device *dev)
2353 {
2354         int ret;
2355
2356         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2357                 return 0;
2358
2359         ret = i915_drm_resume_early(dev);
2360         if (ret)
2361                 return ret;
2362
2363         return i915_drm_resume(dev);
2364 }
2365
2366 static int i915_pm_prepare(struct device *kdev)
2367 {
2368         struct pci_dev *pdev = to_pci_dev(kdev);
2369         struct drm_device *dev = pci_get_drvdata(pdev);
2370
2371         if (!dev) {
2372                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2373                 return -ENODEV;
2374         }
2375
2376         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2377                 return 0;
2378
2379         return i915_drm_prepare(dev);
2380 }
2381
2382 static int i915_pm_suspend(struct device *kdev)
2383 {
2384         struct pci_dev *pdev = to_pci_dev(kdev);
2385         struct drm_device *dev = pci_get_drvdata(pdev);
2386
2387         if (!dev) {
2388                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2389                 return -ENODEV;
2390         }
2391
2392         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2393                 return 0;
2394
2395         return i915_drm_suspend(dev);
2396 }
2397
2398 static int i915_pm_suspend_late(struct device *kdev)
2399 {
2400         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2401
2402         /*
2403          * We have a suspend ordering issue with the snd-hda driver also
2404          * requiring our device to be power up. Due to the lack of a
2405          * parent/child relationship we currently solve this with an late
2406          * suspend hook.
2407          *
2408          * FIXME: This should be solved with a special hdmi sink device or
2409          * similar so that power domains can be employed.
2410          */
2411         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2412                 return 0;
2413
2414         return i915_drm_suspend_late(dev, false);
2415 }
2416
2417 static int i915_pm_poweroff_late(struct device *kdev)
2418 {
2419         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2420
2421         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2422                 return 0;
2423
2424         return i915_drm_suspend_late(dev, true);
2425 }
2426
2427 static int i915_pm_resume_early(struct device *kdev)
2428 {
2429         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2430
2431         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2432                 return 0;
2433
2434         return i915_drm_resume_early(dev);
2435 }
2436
2437 static int i915_pm_resume(struct device *kdev)
2438 {
2439         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2440
2441         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2442                 return 0;
2443
2444         return i915_drm_resume(dev);
2445 }
2446
2447 /* freeze: before creating the hibernation_image */
2448 static int i915_pm_freeze(struct device *kdev)
2449 {
2450         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2451         int ret;
2452
2453         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2454                 ret = i915_drm_suspend(dev);
2455                 if (ret)
2456                         return ret;
2457         }
2458
2459         ret = i915_gem_freeze(kdev_to_i915(kdev));
2460         if (ret)
2461                 return ret;
2462
2463         return 0;
2464 }
2465
2466 static int i915_pm_freeze_late(struct device *kdev)
2467 {
2468         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2469         int ret;
2470
2471         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2472                 ret = i915_drm_suspend_late(dev, true);
2473                 if (ret)
2474                         return ret;
2475         }
2476
2477         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2478         if (ret)
2479                 return ret;
2480
2481         return 0;
2482 }
2483
2484 /* thaw: called after creating the hibernation image, but before turning off. */
2485 static int i915_pm_thaw_early(struct device *kdev)
2486 {
2487         return i915_pm_resume_early(kdev);
2488 }
2489
2490 static int i915_pm_thaw(struct device *kdev)
2491 {
2492         return i915_pm_resume(kdev);
2493 }
2494
2495 /* restore: called after loading the hibernation image. */
2496 static int i915_pm_restore_early(struct device *kdev)
2497 {
2498         return i915_pm_resume_early(kdev);
2499 }
2500
2501 static int i915_pm_restore(struct device *kdev)
2502 {
2503         return i915_pm_resume(kdev);
2504 }
2505
2506 /*
2507  * Save all Gunit registers that may be lost after a D3 and a subsequent
2508  * S0i[R123] transition. The list of registers needing a save/restore is
2509  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2510  * registers in the following way:
2511  * - Driver: saved/restored by the driver
2512  * - Punit : saved/restored by the Punit firmware
2513  * - No, w/o marking: no need to save/restore, since the register is R/O or
2514  *                    used internally by the HW in a way that doesn't depend
2515  *                    keeping the content across a suspend/resume.
2516  * - Debug : used for debugging
2517  *
2518  * We save/restore all registers marked with 'Driver', with the following
2519  * exceptions:
2520  * - Registers out of use, including also registers marked with 'Debug'.
2521  *   These have no effect on the driver's operation, so we don't save/restore
2522  *   them to reduce the overhead.
2523  * - Registers that are fully setup by an initialization function called from
2524  *   the resume path. For example many clock gating and RPS/RC6 registers.
2525  * - Registers that provide the right functionality with their reset defaults.
2526  *
2527  * TODO: Except for registers that based on the above 3 criteria can be safely
2528  * ignored, we save/restore all others, practically treating the HW context as
2529  * a black-box for the driver. Further investigation is needed to reduce the
2530  * saved/restored registers even further, by following the same 3 criteria.
2531  */
2532 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2533 {
2534         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2535         int i;
2536
2537         /* GAM 0x4000-0x4770 */
2538         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2539         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2540         s->arb_mode             = I915_READ(ARB_MODE);
2541         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2542         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2543
2544         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2545                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2546
2547         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2548         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2549
2550         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2551         s->ecochk               = I915_READ(GAM_ECOCHK);
2552         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2553         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2554
2555         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2556
2557         /* MBC 0x9024-0x91D0, 0x8500 */
2558         s->g3dctl               = I915_READ(VLV_G3DCTL);
2559         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2560         s->mbctl                = I915_READ(GEN6_MBCTL);
2561
2562         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2563         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2564         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2565         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2566         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2567         s->rstctl               = I915_READ(GEN6_RSTCTL);
2568         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2569
2570         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2571         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2572         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2573         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2574         s->ecobus               = I915_READ(ECOBUS);
2575         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2576         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2577         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2578         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2579         s->rcedata              = I915_READ(VLV_RCEDATA);
2580         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2581
2582         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2583         s->gt_imr               = I915_READ(GTIMR);
2584         s->gt_ier               = I915_READ(GTIER);
2585         s->pm_imr               = I915_READ(GEN6_PMIMR);
2586         s->pm_ier               = I915_READ(GEN6_PMIER);
2587
2588         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2589                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2590
2591         /* GT SA CZ domain, 0x100000-0x138124 */
2592         s->tilectl              = I915_READ(TILECTL);
2593         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2594         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2595         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2596         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2597
2598         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2599         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2600         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2601         s->pcbr                 = I915_READ(VLV_PCBR);
2602         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2603
2604         /*
2605          * Not saving any of:
2606          * DFT,         0x9800-0x9EC0
2607          * SARB,        0xB000-0xB1FC
2608          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2609          * PCI CFG
2610          */
2611 }
2612
2613 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2614 {
2615         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2616         u32 val;
2617         int i;
2618
2619         /* GAM 0x4000-0x4770 */
2620         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2621         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2622         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2623         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2624         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2625
2626         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2627                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2628
2629         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2630         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2631
2632         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2633         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2634         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2635         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2636
2637         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2638
2639         /* MBC 0x9024-0x91D0, 0x8500 */
2640         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2641         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2642         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2643
2644         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2645         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2646         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2647         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2648         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2649         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2650         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2651
2652         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2653         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2654         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2655         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2656         I915_WRITE(ECOBUS,              s->ecobus);
2657         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2658         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2659         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2660         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2661         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2662         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2663
2664         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2665         I915_WRITE(GTIMR,               s->gt_imr);
2666         I915_WRITE(GTIER,               s->gt_ier);
2667         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2668         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2669
2670         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2671                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2672
2673         /* GT SA CZ domain, 0x100000-0x138124 */
2674         I915_WRITE(TILECTL,                     s->tilectl);
2675         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2676         /*
2677          * Preserve the GT allow wake and GFX force clock bit, they are not
2678          * be restored, as they are used to control the s0ix suspend/resume
2679          * sequence by the caller.
2680          */
2681         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2682         val &= VLV_GTLC_ALLOWWAKEREQ;
2683         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2684         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2685
2686         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2687         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2688         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2689         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2690
2691         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2692
2693         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2694         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2695         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2696         I915_WRITE(VLV_PCBR,                    s->pcbr);
2697         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2698 }
2699
2700 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2701                                   u32 mask, u32 val)
2702 {
2703         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2704         u32 reg_value;
2705         int ret;
2706
2707         /* The HW does not like us polling for PW_STATUS frequently, so
2708          * use the sleeping loop rather than risk the busy spin within
2709          * intel_wait_for_register().
2710          *
2711          * Transitioning between RC6 states should be at most 2ms (see
2712          * valleyview_enable_rps) so use a 3ms timeout.
2713          */
2714         ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);
2715
2716         /* just trace the final value */
2717         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2718
2719         return ret;
2720 }
2721
2722 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2723 {
2724         u32 val;
2725         int err;
2726
2727         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2728         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2729         if (force_on)
2730                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2731         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2732
2733         if (!force_on)
2734                 return 0;
2735
2736         err = intel_wait_for_register(&dev_priv->uncore,
2737                                       VLV_GTLC_SURVIVABILITY_REG,
2738                                       VLV_GFX_CLK_STATUS_BIT,
2739                                       VLV_GFX_CLK_STATUS_BIT,
2740                                       20);
2741         if (err)
2742                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2743                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2744
2745         return err;
2746 }
2747
2748 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2749 {
2750         u32 mask;
2751         u32 val;
2752         int err;
2753
2754         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2755         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2756         if (allow)
2757                 val |= VLV_GTLC_ALLOWWAKEREQ;
2758         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2759         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2760
2761         mask = VLV_GTLC_ALLOWWAKEACK;
2762         val = allow ? mask : 0;
2763
2764         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2765         if (err)
2766                 DRM_ERROR("timeout disabling GT waking\n");
2767
2768         return err;
2769 }
2770
2771 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2772                                   bool wait_for_on)
2773 {
2774         u32 mask;
2775         u32 val;
2776
2777         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2778         val = wait_for_on ? mask : 0;
2779
2780         /*
2781          * RC6 transitioning can be delayed up to 2 msec (see
2782          * valleyview_enable_rps), use 3 msec for safety.
2783          *
2784          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2785          * reset and we are trying to force the machine to sleep.
2786          */
2787         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2788                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2789                                  onoff(wait_for_on));
2790 }
2791
2792 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2793 {
2794         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2795                 return;
2796
2797         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2798         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2799 }
2800
2801 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2802 {
2803         u32 mask;
2804         int err;
2805
2806         /*
2807          * Bspec defines the following GT well on flags as debug only, so
2808          * don't treat them as hard failures.
2809          */
2810         vlv_wait_for_gt_wells(dev_priv, false);
2811
2812         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2813         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2814
2815         vlv_check_no_gt_access(dev_priv);
2816
2817         err = vlv_force_gfx_clock(dev_priv, true);
2818         if (err)
2819                 goto err1;
2820
2821         err = vlv_allow_gt_wake(dev_priv, false);
2822         if (err)
2823                 goto err2;
2824
2825         if (!IS_CHERRYVIEW(dev_priv))
2826                 vlv_save_gunit_s0ix_state(dev_priv);
2827
2828         err = vlv_force_gfx_clock(dev_priv, false);
2829         if (err)
2830                 goto err2;
2831
2832         return 0;
2833
2834 err2:
2835         /* For safety always re-enable waking and disable gfx clock forcing */
2836         vlv_allow_gt_wake(dev_priv, true);
2837 err1:
2838         vlv_force_gfx_clock(dev_priv, false);
2839
2840         return err;
2841 }
2842
2843 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2844                                 bool rpm_resume)
2845 {
2846         int err;
2847         int ret;
2848
2849         /*
2850          * If any of the steps fail just try to continue, that's the best we
2851          * can do at this point. Return the first error code (which will also
2852          * leave RPM permanently disabled).
2853          */
2854         ret = vlv_force_gfx_clock(dev_priv, true);
2855
2856         if (!IS_CHERRYVIEW(dev_priv))
2857                 vlv_restore_gunit_s0ix_state(dev_priv);
2858
2859         err = vlv_allow_gt_wake(dev_priv, true);
2860         if (!ret)
2861                 ret = err;
2862
2863         err = vlv_force_gfx_clock(dev_priv, false);
2864         if (!ret)
2865                 ret = err;
2866
2867         vlv_check_no_gt_access(dev_priv);
2868
2869         if (rpm_resume)
2870                 intel_init_clock_gating(dev_priv);
2871
2872         return ret;
2873 }
2874
2875 static int intel_runtime_suspend(struct device *kdev)
2876 {
2877         struct pci_dev *pdev = to_pci_dev(kdev);
2878         struct drm_device *dev = pci_get_drvdata(pdev);
2879         struct drm_i915_private *dev_priv = to_i915(dev);
2880         int ret;
2881
2882         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2883                 return -ENODEV;
2884
2885         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2886                 return -ENODEV;
2887
2888         DRM_DEBUG_KMS("Suspending device\n");
2889
2890         disable_rpm_wakeref_asserts(dev_priv);
2891
2892         /*
2893          * We are safe here against re-faults, since the fault handler takes
2894          * an RPM reference.
2895          */
2896         i915_gem_runtime_suspend(dev_priv);
2897
2898         intel_uc_runtime_suspend(dev_priv);
2899
2900         intel_runtime_pm_disable_interrupts(dev_priv);
2901
2902         intel_uncore_suspend(&dev_priv->uncore);
2903
2904         ret = 0;
2905         if (INTEL_GEN(dev_priv) >= 11) {
2906                 icl_display_core_uninit(dev_priv);
2907                 bxt_enable_dc9(dev_priv);
2908         } else if (IS_GEN9_LP(dev_priv)) {
2909                 bxt_display_core_uninit(dev_priv);
2910                 bxt_enable_dc9(dev_priv);
2911         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2912                 hsw_enable_pc8(dev_priv);
2913         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2914                 ret = vlv_suspend_complete(dev_priv);
2915         }
2916
2917         if (ret) {
2918                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2919                 intel_uncore_runtime_resume(&dev_priv->uncore);
2920
2921                 intel_runtime_pm_enable_interrupts(dev_priv);
2922
2923                 intel_uc_resume(dev_priv);
2924
2925                 i915_gem_init_swizzling(dev_priv);
2926                 i915_gem_restore_fences(dev_priv);
2927
2928                 enable_rpm_wakeref_asserts(dev_priv);
2929
2930                 return ret;
2931         }
2932
2933         enable_rpm_wakeref_asserts(dev_priv);
2934         intel_runtime_pm_cleanup(dev_priv);
2935
2936         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2937                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2938
2939         dev_priv->runtime_pm.suspended = true;
2940
2941         /*
2942          * FIXME: We really should find a document that references the arguments
2943          * used below!
2944          */
2945         if (IS_BROADWELL(dev_priv)) {
2946                 /*
2947                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2948                  * being detected, and the call we do at intel_runtime_resume()
2949                  * won't be able to restore them. Since PCI_D3hot matches the
2950                  * actual specification and appears to be working, use it.
2951                  */
2952                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2953         } else {
2954                 /*
2955                  * current versions of firmware which depend on this opregion
2956                  * notification have repurposed the D1 definition to mean
2957                  * "runtime suspended" vs. what you would normally expect (D3)
2958                  * to distinguish it from notifications that might be sent via
2959                  * the suspend path.
2960                  */
2961                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2962         }
2963
2964         assert_forcewakes_inactive(&dev_priv->uncore);
2965
2966         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2967                 intel_hpd_poll_init(dev_priv);
2968
2969         DRM_DEBUG_KMS("Device suspended\n");
2970         return 0;
2971 }
2972
2973 static int intel_runtime_resume(struct device *kdev)
2974 {
2975         struct pci_dev *pdev = to_pci_dev(kdev);
2976         struct drm_device *dev = pci_get_drvdata(pdev);
2977         struct drm_i915_private *dev_priv = to_i915(dev);
2978         int ret = 0;
2979
2980         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2981                 return -ENODEV;
2982
2983         DRM_DEBUG_KMS("Resuming device\n");
2984
2985         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2986         disable_rpm_wakeref_asserts(dev_priv);
2987
2988         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2989         dev_priv->runtime_pm.suspended = false;
2990         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2991                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2992
2993         if (INTEL_GEN(dev_priv) >= 11) {
2994                 bxt_disable_dc9(dev_priv);
2995                 icl_display_core_init(dev_priv, true);
2996                 if (dev_priv->csr.dmc_payload) {
2997                         if (dev_priv->csr.allowed_dc_mask &
2998                             DC_STATE_EN_UPTO_DC6)
2999                                 skl_enable_dc6(dev_priv);
3000                         else if (dev_priv->csr.allowed_dc_mask &
3001                                  DC_STATE_EN_UPTO_DC5)
3002                                 gen9_enable_dc5(dev_priv);
3003                 }
3004         } else if (IS_GEN9_LP(dev_priv)) {
3005                 bxt_disable_dc9(dev_priv);
3006                 bxt_display_core_init(dev_priv, true);
3007                 if (dev_priv->csr.dmc_payload &&
3008                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
3009                         gen9_enable_dc5(dev_priv);
3010         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3011                 hsw_disable_pc8(dev_priv);
3012         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3013                 ret = vlv_resume_prepare(dev_priv, true);
3014         }
3015
3016         intel_uncore_runtime_resume(&dev_priv->uncore);
3017
3018         intel_runtime_pm_enable_interrupts(dev_priv);
3019
3020         intel_uc_resume(dev_priv);
3021
3022         /*
3023          * No point of rolling back things in case of an error, as the best
3024          * we can do is to hope that things will still work (and disable RPM).
3025          */
3026         i915_gem_init_swizzling(dev_priv);
3027         i915_gem_restore_fences(dev_priv);
3028
3029         /*
3030          * On VLV/CHV display interrupts are part of the display
3031          * power well, so hpd is reinitialized from there. For
3032          * everyone else do it here.
3033          */
3034         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
3035                 intel_hpd_init(dev_priv);
3036
3037         intel_enable_ipc(dev_priv);
3038
3039         enable_rpm_wakeref_asserts(dev_priv);
3040
3041         if (ret)
3042                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
3043         else
3044                 DRM_DEBUG_KMS("Device resumed\n");
3045
3046         return ret;
3047 }
3048
3049 const struct dev_pm_ops i915_pm_ops = {
3050         /*
3051          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3052          * PMSG_RESUME]
3053          */
3054         .prepare = i915_pm_prepare,
3055         .suspend = i915_pm_suspend,
3056         .suspend_late = i915_pm_suspend_late,
3057         .resume_early = i915_pm_resume_early,
3058         .resume = i915_pm_resume,
3059
3060         /*
3061          * S4 event handlers
3062          * @freeze, @freeze_late    : called (1) before creating the
3063          *                            hibernation image [PMSG_FREEZE] and
3064          *                            (2) after rebooting, before restoring
3065          *                            the image [PMSG_QUIESCE]
3066          * @thaw, @thaw_early       : called (1) after creating the hibernation
3067          *                            image, before writing it [PMSG_THAW]
3068          *                            and (2) after failing to create or
3069          *                            restore the image [PMSG_RECOVER]
3070          * @poweroff, @poweroff_late: called after writing the hibernation
3071          *                            image, before rebooting [PMSG_HIBERNATE]
3072          * @restore, @restore_early : called after rebooting and restoring the
3073          *                            hibernation image [PMSG_RESTORE]
3074          */
3075         .freeze = i915_pm_freeze,
3076         .freeze_late = i915_pm_freeze_late,
3077         .thaw_early = i915_pm_thaw_early,
3078         .thaw = i915_pm_thaw,
3079         .poweroff = i915_pm_suspend,
3080         .poweroff_late = i915_pm_poweroff_late,
3081         .restore_early = i915_pm_restore_early,
3082         .restore = i915_pm_restore,
3083
3084         /* S0ix (via runtime suspend) event handlers */
3085         .runtime_suspend = intel_runtime_suspend,
3086         .runtime_resume = intel_runtime_resume,
3087 };
3088
3089 static const struct vm_operations_struct i915_gem_vm_ops = {
3090         .fault = i915_gem_fault,
3091         .open = drm_gem_vm_open,
3092         .close = drm_gem_vm_close,
3093 };
3094
3095 static const struct file_operations i915_driver_fops = {
3096         .owner = THIS_MODULE,
3097         .open = drm_open,
3098         .release = drm_release,
3099         .unlocked_ioctl = drm_ioctl,
3100         .mmap = drm_gem_mmap,
3101         .poll = drm_poll,
3102         .read = drm_read,
3103         .compat_ioctl = i915_compat_ioctl,
3104         .llseek = noop_llseek,
3105 };
3106
3107 static int
3108 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3109                           struct drm_file *file)
3110 {
3111         return -ENODEV;
3112 }
3113
3114 static const struct drm_ioctl_desc i915_ioctls[] = {
3115         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3116         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3117         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3118         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3119         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3120         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3121         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
3122         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3123         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3124         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3125         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3126         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3127         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3128         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3129         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
3130         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3131         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3132         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3133         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3134         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
3135         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3136         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3137         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
3138         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3139         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3140         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
3141         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3142         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3143         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3144         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3145         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3146         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3147         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3148         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3149         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3150         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3151         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3152         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3153         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3154         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3155         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3156         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3157         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3158         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3159         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
3160         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3161         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3162         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3163         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3164         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3165         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3166         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3167         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3168         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3169         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3170         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3171         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
3172         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
3173 };
3174
3175 static struct drm_driver driver = {
3176         /* Don't use MTRRs here; the Xserver or userspace app should
3177          * deal with them for Intel hardware.
3178          */
3179         .driver_features =
3180             DRIVER_GEM | DRIVER_PRIME |
3181             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3182         .release = i915_driver_release,
3183         .open = i915_driver_open,
3184         .lastclose = i915_driver_lastclose,
3185         .postclose = i915_driver_postclose,
3186
3187         .gem_close_object = i915_gem_close_object,
3188         .gem_free_object_unlocked = i915_gem_free_object,
3189         .gem_vm_ops = &i915_gem_vm_ops,
3190
3191         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3192         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3193         .gem_prime_export = i915_gem_prime_export,
3194         .gem_prime_import = i915_gem_prime_import,
3195
3196         .dumb_create = i915_gem_dumb_create,
3197         .dumb_map_offset = i915_gem_mmap_gtt,
3198         .ioctls = i915_ioctls,
3199         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3200         .fops = &i915_driver_fops,
3201         .name = DRIVER_NAME,
3202         .desc = DRIVER_DESC,
3203         .date = DRIVER_DATE,
3204         .major = DRIVER_MAJOR,
3205         .minor = DRIVER_MINOR,
3206         .patchlevel = DRIVER_PATCHLEVEL,
3207 };
3208
3209 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3210 #include "selftests/mock_drm.c"
3211 #endif