drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915.inject_load_failure &&
 110                i915_load_fail_count == i915.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 139         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 140                 ret = PCH_SPT;
 141                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 142         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 143                 ret = PCH_CNP;
 144                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 145         }
 146
 147         return ret;
 148 }
 149
 150 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 151 {
 152         struct pci_dev *pch = NULL;
 153
 154         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 155          * (which really amounts to a PCH but no South Display).
 156          */
 157         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 158                 dev_priv->pch_type = PCH_NOP;
 159                 return;
 160         }
 161
 162         /*
 163          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 164          * make graphics device passthrough work easy for VMM, that only
 165          * need to expose ISA bridge to let driver know the real hardware
 166          * underneath. This is a requirement from virtualization team.
 167          *
 168          * In some virtualized environments (e.g. XEN), there is irrelevant
 169          * ISA bridge in the system. To work reliably, we should scan trhough
 170          * all the ISA bridge devices and check for the first match, instead
 171          * of only checking the first one.
 172          */
 173         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 174                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 175                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 176                         unsigned short id_ext = pch->device &
 177                                 INTEL_PCH_DEVICE_ID_MASK_EXT;
 178
 179                         dev_priv->pch_id = id;
 180
 181                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 182                                 dev_priv->pch_type = PCH_IBX;
 183                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 184                                 WARN_ON(!IS_GEN5(dev_priv));
 185                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 186                                 dev_priv->pch_type = PCH_CPT;
 187                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 188                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 189                                         IS_IVYBRIDGE(dev_priv)));
 190                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 191                                 /* PantherPoint is CPT compatible */
 192                                 dev_priv->pch_type = PCH_CPT;
 193                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 194                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 195                                         IS_IVYBRIDGE(dev_priv)));
 196                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 197                                 dev_priv->pch_type = PCH_LPT;
 198                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 199                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 200                                         !IS_BROADWELL(dev_priv));
 201                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 202                                         IS_BDW_ULT(dev_priv));
 203                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 204                                 dev_priv->pch_type = PCH_LPT;
 205                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 206                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 207                                         !IS_BROADWELL(dev_priv));
 208                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 209                                         !IS_BDW_ULT(dev_priv));
 210                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 211                                 dev_priv->pch_type = PCH_SPT;
 212                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 213                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 214                                         !IS_KABYLAKE(dev_priv));
 215                         } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 216                                 dev_priv->pch_type = PCH_SPT;
 217                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 218                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 219                                         !IS_KABYLAKE(dev_priv));
 220                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 221                                 dev_priv->pch_type = PCH_KBP;
 222                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 223                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 224                                         !IS_KABYLAKE(dev_priv));
 225                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 226                                 dev_priv->pch_type = PCH_CNP;
 227                                 DRM_DEBUG_KMS("Found CannonPoint PCH\n");
 228                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 229                                         !IS_COFFEELAKE(dev_priv));
 230                         } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 231                                 dev_priv->pch_type = PCH_CNP;
 232                                 DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
 233                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 234                                         !IS_COFFEELAKE(dev_priv));
 235                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 236                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 237                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 238                                     pch->subsystem_vendor ==
 239                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 240                                     pch->subsystem_device ==
 241                                             PCI_SUBDEVICE_ID_QEMU)) {
 242                                 dev_priv->pch_type =
 243                                         intel_virt_detect_pch(dev_priv);
 244                         } else
 245                                 continue;
 246
 247                         break;
 248                 }
 249         }
 250         if (!pch)
 251                 DRM_DEBUG_KMS("No PCH found.\n");
 252
 253         pci_dev_put(pch);
 254 }
 255
 256 static int i915_getparam(struct drm_device *dev, void *data,
 257                          struct drm_file *file_priv)
 258 {
 259         struct drm_i915_private *dev_priv = to_i915(dev);
 260         struct pci_dev *pdev = dev_priv->drm.pdev;
 261         drm_i915_getparam_t *param = data;
 262         int value;
 263
 264         switch (param->param) {
 265         case I915_PARAM_IRQ_ACTIVE:
 266         case I915_PARAM_ALLOW_BATCHBUFFER:
 267         case I915_PARAM_LAST_DISPATCH:
 268         case I915_PARAM_HAS_EXEC_CONSTANTS:
 269                 /* Reject all old ums/dri params. */
 270                 return -ENODEV;
 271         case I915_PARAM_CHIPSET_ID:
 272                 value = pdev->device;
 273                 break;
 274         case I915_PARAM_REVISION:
 275                 value = pdev->revision;
 276                 break;
 277         case I915_PARAM_NUM_FENCES_AVAIL:
 278                 value = dev_priv->num_fence_regs;
 279                 break;
 280         case I915_PARAM_HAS_OVERLAY:
 281                 value = dev_priv->overlay ? 1 : 0;
 282                 break;
 283         case I915_PARAM_HAS_BSD:
 284                 value = !!dev_priv->engine[VCS];
 285                 break;
 286         case I915_PARAM_HAS_BLT:
 287                 value = !!dev_priv->engine[BCS];
 288                 break;
 289         case I915_PARAM_HAS_VEBOX:
 290                 value = !!dev_priv->engine[VECS];
 291                 break;
 292         case I915_PARAM_HAS_BSD2:
 293                 value = !!dev_priv->engine[VCS2];
 294                 break;
 295         case I915_PARAM_HAS_LLC:
 296                 value = HAS_LLC(dev_priv);
 297                 break;
 298         case I915_PARAM_HAS_WT:
 299                 value = HAS_WT(dev_priv);
 300                 break;
 301         case I915_PARAM_HAS_ALIASING_PPGTT:
 302                 value = USES_PPGTT(dev_priv);
 303                 break;
 304         case I915_PARAM_HAS_SEMAPHORES:
 305                 value = i915.semaphores;
 306                 break;
 307         case I915_PARAM_HAS_SECURE_BATCHES:
 308                 value = capable(CAP_SYS_ADMIN);
 309                 break;
 310         case I915_PARAM_CMD_PARSER_VERSION:
 311                 value = i915_cmd_parser_get_version(dev_priv);
 312                 break;
 313         case I915_PARAM_SUBSLICE_TOTAL:
 314                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 315                 if (!value)
 316                         return -ENODEV;
 317                 break;
 318         case I915_PARAM_EU_TOTAL:
 319                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 320                 if (!value)
 321                         return -ENODEV;
 322                 break;
 323         case I915_PARAM_HAS_GPU_RESET:
 324                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 325                 break;
 326         case I915_PARAM_HAS_RESOURCE_STREAMER:
 327                 value = HAS_RESOURCE_STREAMER(dev_priv);
 328                 break;
 329         case I915_PARAM_HAS_POOLED_EU:
 330                 value = HAS_POOLED_EU(dev_priv);
 331                 break;
 332         case I915_PARAM_MIN_EU_IN_POOL:
 333                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 334                 break;
 335         case I915_PARAM_HUC_STATUS:
 336                 intel_runtime_pm_get(dev_priv);
 337                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 338                 intel_runtime_pm_put(dev_priv);
 339                 break;
 340         case I915_PARAM_MMAP_GTT_VERSION:
 341                 /* Though we've started our numbering from 1, and so class all
 342                  * earlier versions as 0, in effect their value is undefined as
 343                  * the ioctl will report EINVAL for the unknown param!
 344                  */
 345                 value = i915_gem_mmap_gtt_version();
 346                 break;
 347         case I915_PARAM_HAS_SCHEDULER:
 348                 value = dev_priv->engine[RCS] &&
 349                         dev_priv->engine[RCS]->schedule;
 350                 break;
 351         case I915_PARAM_MMAP_VERSION:
 352                 /* Remember to bump this if the version changes! */
 353         case I915_PARAM_HAS_GEM:
 354         case I915_PARAM_HAS_PAGEFLIPPING:
 355         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 356         case I915_PARAM_HAS_RELAXED_FENCING:
 357         case I915_PARAM_HAS_COHERENT_RINGS:
 358         case I915_PARAM_HAS_RELAXED_DELTA:
 359         case I915_PARAM_HAS_GEN7_SOL_RESET:
 360         case I915_PARAM_HAS_WAIT_TIMEOUT:
 361         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 362         case I915_PARAM_HAS_PINNED_BATCHES:
 363         case I915_PARAM_HAS_EXEC_NO_RELOC:
 364         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 365         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 366         case I915_PARAM_HAS_EXEC_SOFTPIN:
 367         case I915_PARAM_HAS_EXEC_ASYNC:
 368         case I915_PARAM_HAS_EXEC_FENCE:
 369         case I915_PARAM_HAS_EXEC_CAPTURE:
 370                 /* For the time being all of these are always true;
 371                  * if some supported hardware does not have one of these
 372                  * features this value needs to be provided from
 373                  * INTEL_INFO(), a feature macro, or similar.
 374                  */
 375                 value = 1;
 376                 break;
 377         case I915_PARAM_SLICE_MASK:
 378                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 379                 if (!value)
 380                         return -ENODEV;
 381                 break;
 382         case I915_PARAM_SUBSLICE_MASK:
 383                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 384                 if (!value)
 385                         return -ENODEV;
 386                 break;
 387         default:
 388                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 389                 return -EINVAL;
 390         }
 391
 392         if (put_user(value, param->value))
 393                 return -EFAULT;
 394
 395         return 0;
 396 }
 397
 398 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 399 {
 400         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 401         if (!dev_priv->bridge_dev) {
 402                 DRM_ERROR("bridge device not found\n");
 403                 return -1;
 404         }
 405         return 0;
 406 }
 407
 408 /* Allocate space for the MCH regs if needed, return nonzero on error */
 409 static int
 410 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 411 {
 412         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 413         u32 temp_lo, temp_hi = 0;
 414         u64 mchbar_addr;
 415         int ret;
 416
 417         if (INTEL_GEN(dev_priv) >= 4)
 418                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 419         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 420         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 421
 422         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 423 #ifdef CONFIG_PNP
 424         if (mchbar_addr &&
 425             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 426                 return 0;
 427 #endif
 428
 429         /* Get some space for it */
 430         dev_priv->mch_res.name = "i915 MCHBAR";
 431         dev_priv->mch_res.flags = IORESOURCE_MEM;
 432         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 433                                      &dev_priv->mch_res,
 434                                      MCHBAR_SIZE, MCHBAR_SIZE,
 435                                      PCIBIOS_MIN_MEM,
 436                                      0, pcibios_align_resource,
 437                                      dev_priv->bridge_dev);
 438         if (ret) {
 439                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 440                 dev_priv->mch_res.start = 0;
 441                 return ret;
 442         }
 443
 444         if (INTEL_GEN(dev_priv) >= 4)
 445                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 446                                        upper_32_bits(dev_priv->mch_res.start));
 447
 448         pci_write_config_dword(dev_priv->bridge_dev, reg,
 449                                lower_32_bits(dev_priv->mch_res.start));
 450         return 0;
 451 }
 452
 453 /* Setup MCHBAR if possible, return true if we should disable it again */
 454 static void
 455 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 456 {
 457         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 458         u32 temp;
 459         bool enabled;
 460
 461         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 462                 return;
 463
 464         dev_priv->mchbar_need_disable = false;
 465
 466         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 467                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 468                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 469         } else {
 470                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 471                 enabled = temp & 1;
 472         }
 473
 474         /* If it's already enabled, don't have to do anything */
 475         if (enabled)
 476                 return;
 477
 478         if (intel_alloc_mchbar_resource(dev_priv))
 479                 return;
 480
 481         dev_priv->mchbar_need_disable = true;
 482
 483         /* Space is allocated or reserved, so enable it. */
 484         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 485                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 486                                        temp | DEVEN_MCHBAR_EN);
 487         } else {
 488                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 489                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 490         }
 491 }
 492
 493 static void
 494 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 495 {
 496         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 497
 498         if (dev_priv->mchbar_need_disable) {
 499                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 500                         u32 deven_val;
 501
 502                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 503                                               &deven_val);
 504                         deven_val &= ~DEVEN_MCHBAR_EN;
 505                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 506                                                deven_val);
 507                 } else {
 508                         u32 mchbar_val;
 509
 510                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 511                                               &mchbar_val);
 512                         mchbar_val &= ~1;
 513                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 514                                                mchbar_val);
 515                 }
 516         }
 517
 518         if (dev_priv->mch_res.start)
 519                 release_resource(&dev_priv->mch_res);
 520 }
 521
 522 /* true = enable decode, false = disable decoder */
 523 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 524 {
 525         struct drm_i915_private *dev_priv = cookie;
 526
 527         intel_modeset_vga_set_state(dev_priv, state);
 528         if (state)
 529                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 530                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 531         else
 532                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 533 }
 534
 535 static int i915_resume_switcheroo(struct drm_device *dev);
 536 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 537
 538 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 539 {
 540         struct drm_device *dev = pci_get_drvdata(pdev);
 541         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 542
 543         if (state == VGA_SWITCHEROO_ON) {
 544                 pr_info("switched on\n");
 545                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 546                 /* i915 resume handler doesn't set to D0 */
 547                 pci_set_power_state(pdev, PCI_D0);
 548                 i915_resume_switcheroo(dev);
 549                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 550         } else {
 551                 pr_info("switched off\n");
 552                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 553                 i915_suspend_switcheroo(dev, pmm);
 554                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 555         }
 556 }
 557
 558 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 559 {
 560         struct drm_device *dev = pci_get_drvdata(pdev);
 561
 562         /*
 563          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 564          * locking inversion with the driver load path. And the access here is
 565          * completely racy anyway. So don't bother with locking for now.
 566          */
 567         return dev->open_count == 0;
 568 }
 569
 570 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 571         .set_gpu_state = i915_switcheroo_set_state,
 572         .reprobe = NULL,
 573         .can_switch = i915_switcheroo_can_switch,
 574 };
 575
 576 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 577 {
 578         mutex_lock(&dev_priv->drm.struct_mutex);
 579         intel_uc_fini_hw(dev_priv);
 580         i915_gem_cleanup_engines(dev_priv);
 581         i915_gem_context_fini(dev_priv);
 582         mutex_unlock(&dev_priv->drm.struct_mutex);
 583
 584         i915_gem_drain_freed_objects(dev_priv);
 585
 586         WARN_ON(!list_empty(&dev_priv->context_list));
 587 }
 588
 589 static int i915_load_modeset_init(struct drm_device *dev)
 590 {
 591         struct drm_i915_private *dev_priv = to_i915(dev);
 592         struct pci_dev *pdev = dev_priv->drm.pdev;
 593         int ret;
 594
 595         if (i915_inject_load_failure())
 596                 return -ENODEV;
 597
 598         intel_bios_init(dev_priv);
 599
 600         /* If we have > 1 VGA cards, then we need to arbitrate access
 601          * to the common VGA resources.
 602          *
 603          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 604          * then we do not take part in VGA arbitration and the
 605          * vga_client_register() fails with -ENODEV.
 606          */
 607         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 608         if (ret && ret != -ENODEV)
 609                 goto out;
 610
 611         intel_register_dsm_handler();
 612
 613         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 614         if (ret)
 615                 goto cleanup_vga_client;
 616
 617         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 618         intel_update_rawclk(dev_priv);
 619
 620         intel_power_domains_init_hw(dev_priv, false);
 621
 622         intel_csr_ucode_init(dev_priv);
 623
 624         ret = intel_irq_install(dev_priv);
 625         if (ret)
 626                 goto cleanup_csr;
 627
 628         intel_setup_gmbus(dev_priv);
 629
 630         /* Important: The output setup functions called by modeset_init need
 631          * working irqs for e.g. gmbus and dp aux transfers. */
 632         ret = intel_modeset_init(dev);
 633         if (ret)
 634                 goto cleanup_irq;
 635
 636         intel_uc_init_fw(dev_priv);
 637
 638         ret = i915_gem_init(dev_priv);
 639         if (ret)
 640                 goto cleanup_uc;
 641
 642         intel_modeset_gem_init(dev);
 643
 644         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 645                 return 0;
 646
 647         ret = intel_fbdev_init(dev);
 648         if (ret)
 649                 goto cleanup_gem;
 650
 651         /* Only enable hotplug handling once the fbdev is fully set up. */
 652         intel_hpd_init(dev_priv);
 653
 654         drm_kms_helper_poll_init(dev);
 655
 656         return 0;
 657
 658 cleanup_gem:
 659         if (i915_gem_suspend(dev_priv))
 660                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 661         i915_gem_fini(dev_priv);
 662 cleanup_uc:
 663         intel_uc_fini_fw(dev_priv);
 664 cleanup_irq:
 665         drm_irq_uninstall(dev);
 666         intel_teardown_gmbus(dev_priv);
 667 cleanup_csr:
 668         intel_csr_ucode_fini(dev_priv);
 669         intel_power_domains_fini(dev_priv);
 670         vga_switcheroo_unregister_client(pdev);
 671 cleanup_vga_client:
 672         vga_client_register(pdev, NULL, NULL, NULL);
 673 out:
 674         return ret;
 675 }
 676
 677 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 678 {
 679         struct apertures_struct *ap;
 680         struct pci_dev *pdev = dev_priv->drm.pdev;
 681         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 682         bool primary;
 683         int ret;
 684
 685         ap = alloc_apertures(1);
 686         if (!ap)
 687                 return -ENOMEM;
 688
 689         ap->ranges[0].base = ggtt->mappable_base;
 690         ap->ranges[0].size = ggtt->mappable_end;
 691
 692         primary =
 693                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 694
 695         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 696
 697         kfree(ap);
 698
 699         return ret;
 700 }
 701
 702 #if !defined(CONFIG_VGA_CONSOLE)
 703 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 704 {
 705         return 0;
 706 }
 707 #elif !defined(CONFIG_DUMMY_CONSOLE)
 708 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 709 {
 710         return -ENODEV;
 711 }
 712 #else
 713 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 714 {
 715         int ret = 0;
 716
 717         DRM_INFO("Replacing VGA console driver\n");
 718
 719         console_lock();
 720         if (con_is_bound(&vga_con))
 721                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 722         if (ret == 0) {
 723                 ret = do_unregister_con_driver(&vga_con);
 724
 725                 /* Ignore "already unregistered". */
 726                 if (ret == -ENODEV)
 727                         ret = 0;
 728         }
 729         console_unlock();
 730
 731         return ret;
 732 }
 733 #endif
 734
 735 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 736 {
 737         /*
 738          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 739          * CHV x1 PHY (DP/HDMI D)
 740          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 741          */
 742         if (IS_CHERRYVIEW(dev_priv)) {
 743                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 744                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 745         } else if (IS_VALLEYVIEW(dev_priv)) {
 746                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 747         }
 748 }
 749
 750 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 751 {
 752         /*
 753          * The i915 workqueue is primarily used for batched retirement of
 754          * requests (and thus managing bo) once the task has been completed
 755          * by the GPU. i915_gem_retire_requests() is called directly when we
 756          * need high-priority retirement, such as waiting for an explicit
 757          * bo.
 758          *
 759          * It is also used for periodic low-priority events, such as
 760          * idle-timers and recording error state.
 761          *
 762          * All tasks on the workqueue are expected to acquire the dev mutex
 763          * so there is no point in running more than one instance of the
 764          * workqueue at any time.  Use an ordered one.
 765          */
 766         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 767         if (dev_priv->wq == NULL)
 768                 goto out_err;
 769
 770         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 771         if (dev_priv->hotplug.dp_wq == NULL)
 772                 goto out_free_wq;
 773
 774         return 0;
 775
 776 out_free_wq:
 777         destroy_workqueue(dev_priv->wq);
 778 out_err:
 779         DRM_ERROR("Failed to allocate workqueues.\n");
 780
 781         return -ENOMEM;
 782 }
 783
 784 static void i915_engines_cleanup(struct drm_i915_private *i915)
 785 {
 786         struct intel_engine_cs *engine;
 787         enum intel_engine_id id;
 788
 789         for_each_engine(engine, i915, id)
 790                 kfree(engine);
 791 }
 792
 793 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 794 {
 795         destroy_workqueue(dev_priv->hotplug.dp_wq);
 796         destroy_workqueue(dev_priv->wq);
 797 }
 798
 799 /*
 800  * We don't keep the workarounds for pre-production hardware, so we expect our
 801  * driver to fail on these machines in one way or another. A little warning on
 802  * dmesg may help both the user and the bug triagers.
 803  */
 804 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 805 {
 806         bool pre = false;
 807
 808         pre |= IS_HSW_EARLY_SDV(dev_priv);
 809         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 810         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 811
 812         if (pre) {
 813                 DRM_ERROR("This is a pre-production stepping. "
 814                           "It may not be fully functional.\n");
 815                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 816         }
 817 }
 818
 819 /**
 820  * i915_driver_init_early - setup state not requiring device access
 821  * @dev_priv: device private
 822  *
 823  * Initialize everything that is a "SW-only" state, that is state not
 824  * requiring accessing the device or exposing the driver via kernel internal
 825  * or userspace interfaces. Example steps belonging here: lock initialization,
 826  * system memory allocation, setting up device specific attributes and
 827  * function hooks not requiring accessing the device.
 828  */
 829 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 830                                   const struct pci_device_id *ent)
 831 {
 832         const struct intel_device_info *match_info =
 833                 (struct intel_device_info *)ent->driver_data;
 834         struct intel_device_info *device_info;
 835         int ret = 0;
 836
 837         if (i915_inject_load_failure())
 838                 return -ENODEV;
 839
 840         /* Setup the write-once "constant" device info */
 841         device_info = mkwrite_device_info(dev_priv);
 842         memcpy(device_info, match_info, sizeof(*device_info));
 843         device_info->device_id = dev_priv->drm.pdev->device;
 844
 845         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 846         device_info->gen_mask = BIT(device_info->gen - 1);
 847
 848         spin_lock_init(&dev_priv->irq_lock);
 849         spin_lock_init(&dev_priv->gpu_error.lock);
 850         mutex_init(&dev_priv->backlight_lock);
 851         spin_lock_init(&dev_priv->uncore.lock);
 852
 853         spin_lock_init(&dev_priv->mm.object_stat_lock);
 854         spin_lock_init(&dev_priv->mmio_flip_lock);
 855         mutex_init(&dev_priv->sb_lock);
 856         mutex_init(&dev_priv->modeset_restore_lock);
 857         mutex_init(&dev_priv->av_mutex);
 858         mutex_init(&dev_priv->wm.wm_mutex);
 859         mutex_init(&dev_priv->pps_mutex);
 860
 861         intel_uc_init_early(dev_priv);
 862         i915_memcpy_init_early(dev_priv);
 863
 864         ret = i915_workqueues_init(dev_priv);
 865         if (ret < 0)
 866                 goto err_engines;
 867
 868         /* This must be called before any calls to HAS_PCH_* */
 869         intel_detect_pch(dev_priv);
 870
 871         intel_pm_setup(dev_priv);
 872         intel_init_dpio(dev_priv);
 873         intel_power_domains_init(dev_priv);
 874         intel_irq_init(dev_priv);
 875         intel_hangcheck_init(dev_priv);
 876         intel_init_display_hooks(dev_priv);
 877         intel_init_clock_gating_hooks(dev_priv);
 878         intel_init_audio_hooks(dev_priv);
 879         ret = i915_gem_load_init(dev_priv);
 880         if (ret < 0)
 881                 goto err_irq;
 882
 883         intel_display_crc_init(dev_priv);
 884
 885         intel_device_info_dump(dev_priv);
 886
 887         intel_detect_preproduction_hw(dev_priv);
 888
 889         i915_perf_init(dev_priv);
 890
 891         return 0;
 892
 893 err_irq:
 894         intel_irq_fini(dev_priv);
 895         i915_workqueues_cleanup(dev_priv);
 896 err_engines:
 897         i915_engines_cleanup(dev_priv);
 898         return ret;
 899 }
 900
 901 /**
 902  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 903  * @dev_priv: device private
 904  */
 905 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 906 {
 907         i915_perf_fini(dev_priv);
 908         i915_gem_load_cleanup(dev_priv);
 909         intel_irq_fini(dev_priv);
 910         i915_workqueues_cleanup(dev_priv);
 911         i915_engines_cleanup(dev_priv);
 912 }
 913
 914 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 915 {
 916         struct pci_dev *pdev = dev_priv->drm.pdev;
 917         int mmio_bar;
 918         int mmio_size;
 919
 920         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 921         /*
 922          * Before gen4, the registers and the GTT are behind different BARs.
 923          * However, from gen4 onwards, the registers and the GTT are shared
 924          * in the same BAR, so we want to restrict this ioremap from
 925          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 926          * the register BAR remains the same size for all the earlier
 927          * generations up to Ironlake.
 928          */
 929         if (INTEL_GEN(dev_priv) < 5)
 930                 mmio_size = 512 * 1024;
 931         else
 932                 mmio_size = 2 * 1024 * 1024;
 933         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 934         if (dev_priv->regs == NULL) {
 935                 DRM_ERROR("failed to map registers\n");
 936
 937                 return -EIO;
 938         }
 939
 940         /* Try to make sure MCHBAR is enabled before poking at it */
 941         intel_setup_mchbar(dev_priv);
 942
 943         return 0;
 944 }
 945
 946 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 947 {
 948         struct pci_dev *pdev = dev_priv->drm.pdev;
 949
 950         intel_teardown_mchbar(dev_priv);
 951         pci_iounmap(pdev, dev_priv->regs);
 952 }
 953
 954 /**
 955  * i915_driver_init_mmio - setup device MMIO
 956  * @dev_priv: device private
 957  *
 958  * Setup minimal device state necessary for MMIO accesses later in the
 959  * initialization sequence. The setup here should avoid any other device-wide
 960  * side effects or exposing the driver via kernel internal or user space
 961  * interfaces.
 962  */
 963 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 964 {
 965         int ret;
 966
 967         if (i915_inject_load_failure())
 968                 return -ENODEV;
 969
 970         if (i915_get_bridge_dev(dev_priv))
 971                 return -EIO;
 972
 973         ret = i915_mmio_setup(dev_priv);
 974         if (ret < 0)
 975                 goto err_bridge;
 976
 977         intel_uncore_init(dev_priv);
 978
 979         ret = intel_engines_init_mmio(dev_priv);
 980         if (ret)
 981                 goto err_uncore;
 982
 983         i915_gem_init_mmio(dev_priv);
 984
 985         return 0;
 986
 987 err_uncore:
 988         intel_uncore_fini(dev_priv);
 989 err_bridge:
 990         pci_dev_put(dev_priv->bridge_dev);
 991
 992         return ret;
 993 }
 994
 995 /**
 996  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 997  * @dev_priv: device private
 998  */
 999 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1000 {
1001         intel_uncore_fini(dev_priv);
1002         i915_mmio_cleanup(dev_priv);
1003         pci_dev_put(dev_priv->bridge_dev);
1004 }
1005
1006 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1007 {
1008         i915.enable_execlists =
1009                 intel_sanitize_enable_execlists(dev_priv,
1010                                                 i915.enable_execlists);
1011
1012         /*
1013          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1014          * user's requested state against the hardware/driver capabilities.  We
1015          * do this now so that we can print out any log messages once rather
1016          * than every time we check intel_enable_ppgtt().
1017          */
1018         i915.enable_ppgtt =
1019                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1020         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1021
1022         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1023         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
1024
1025         intel_uc_sanitize_options(dev_priv);
1026
1027         intel_gvt_sanitize_options(dev_priv);
1028 }
1029
1030 /**
1031  * i915_driver_init_hw - setup state requiring device access
1032  * @dev_priv: device private
1033  *
1034  * Setup state that requires accessing the device, but doesn't require
1035  * exposing the driver via kernel internal or userspace interfaces.
1036  */
1037 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1038 {
1039         struct pci_dev *pdev = dev_priv->drm.pdev;
1040         int ret;
1041
1042         if (i915_inject_load_failure())
1043                 return -ENODEV;
1044
1045         intel_device_info_runtime_init(dev_priv);
1046
1047         intel_sanitize_options(dev_priv);
1048
1049         ret = i915_ggtt_probe_hw(dev_priv);
1050         if (ret)
1051                 return ret;
1052
1053         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1054          * otherwise the vga fbdev driver falls over. */
1055         ret = i915_kick_out_firmware_fb(dev_priv);
1056         if (ret) {
1057                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1058                 goto out_ggtt;
1059         }
1060
1061         ret = i915_kick_out_vgacon(dev_priv);
1062         if (ret) {
1063                 DRM_ERROR("failed to remove conflicting VGA console\n");
1064                 goto out_ggtt;
1065         }
1066
1067         ret = i915_ggtt_init_hw(dev_priv);
1068         if (ret)
1069                 return ret;
1070
1071         ret = i915_ggtt_enable_hw(dev_priv);
1072         if (ret) {
1073                 DRM_ERROR("failed to enable GGTT\n");
1074                 goto out_ggtt;
1075         }
1076
1077         pci_set_master(pdev);
1078
1079         /* overlay on gen2 is broken and can't address above 1G */
1080         if (IS_GEN2(dev_priv)) {
1081                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1082                 if (ret) {
1083                         DRM_ERROR("failed to set DMA mask\n");
1084
1085                         goto out_ggtt;
1086                 }
1087         }
1088
1089         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1090          * using 32bit addressing, overwriting memory if HWS is located
1091          * above 4GB.
1092          *
1093          * The documentation also mentions an issue with undefined
1094          * behaviour if any general state is accessed within a page above 4GB,
1095          * which also needs to be handled carefully.
1096          */
1097         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1098                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1099
1100                 if (ret) {
1101                         DRM_ERROR("failed to set DMA mask\n");
1102
1103                         goto out_ggtt;
1104                 }
1105         }
1106
1107         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1108                            PM_QOS_DEFAULT_VALUE);
1109
1110         intel_uncore_sanitize(dev_priv);
1111
1112         intel_opregion_setup(dev_priv);
1113
1114         i915_gem_load_init_fences(dev_priv);
1115
1116         /* On the 945G/GM, the chipset reports the MSI capability on the
1117          * integrated graphics even though the support isn't actually there
1118          * according to the published specs.  It doesn't appear to function
1119          * correctly in testing on 945G.
1120          * This may be a side effect of MSI having been made available for PEG
1121          * and the registers being closely associated.
1122          *
1123          * According to chipset errata, on the 965GM, MSI interrupts may
1124          * be lost or delayed, but we use them anyways to avoid
1125          * stuck interrupts on some machines.
1126          */
1127         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1128                 if (pci_enable_msi(pdev) < 0)
1129                         DRM_DEBUG_DRIVER("can't enable MSI");
1130         }
1131
1132         ret = intel_gvt_init(dev_priv);
1133         if (ret)
1134                 goto out_ggtt;
1135
1136         return 0;
1137
1138 out_ggtt:
1139         i915_ggtt_cleanup_hw(dev_priv);
1140
1141         return ret;
1142 }
1143
1144 /**
1145  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1146  * @dev_priv: device private
1147  */
1148 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1149 {
1150         struct pci_dev *pdev = dev_priv->drm.pdev;
1151
1152         if (pdev->msi_enabled)
1153                 pci_disable_msi(pdev);
1154
1155         pm_qos_remove_request(&dev_priv->pm_qos);
1156         i915_ggtt_cleanup_hw(dev_priv);
1157 }
1158
1159 /**
1160  * i915_driver_register - register the driver with the rest of the system
1161  * @dev_priv: device private
1162  *
1163  * Perform any steps necessary to make the driver available via kernel
1164  * internal or userspace interfaces.
1165  */
1166 static void i915_driver_register(struct drm_i915_private *dev_priv)
1167 {
1168         struct drm_device *dev = &dev_priv->drm;
1169
1170         i915_gem_shrinker_init(dev_priv);
1171
1172         /*
1173          * Notify a valid surface after modesetting,
1174          * when running inside a VM.
1175          */
1176         if (intel_vgpu_active(dev_priv))
1177                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1178
1179         /* Reveal our presence to userspace */
1180         if (drm_dev_register(dev, 0) == 0) {
1181                 i915_debugfs_register(dev_priv);
1182                 i915_guc_log_register(dev_priv);
1183                 i915_setup_sysfs(dev_priv);
1184
1185                 /* Depends on sysfs having been initialized */
1186                 i915_perf_register(dev_priv);
1187         } else
1188                 DRM_ERROR("Failed to register driver for userspace access!\n");
1189
1190         if (INTEL_INFO(dev_priv)->num_pipes) {
1191                 /* Must be done after probing outputs */
1192                 intel_opregion_register(dev_priv);
1193                 acpi_video_register();
1194         }
1195
1196         if (IS_GEN5(dev_priv))
1197                 intel_gpu_ips_init(dev_priv);
1198
1199         intel_audio_init(dev_priv);
1200
1201         /*
1202          * Some ports require correctly set-up hpd registers for detection to
1203          * work properly (leading to ghost connected connector status), e.g. VGA
1204          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1205          * irqs are fully enabled. We do it last so that the async config
1206          * cannot run before the connectors are registered.
1207          */
1208         intel_fbdev_initial_config_async(dev);
1209 }
1210
1211 /**
1212  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1213  * @dev_priv: device private
1214  */
1215 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1216 {
1217         intel_audio_deinit(dev_priv);
1218
1219         intel_gpu_ips_teardown();
1220         acpi_video_unregister();
1221         intel_opregion_unregister(dev_priv);
1222
1223         i915_perf_unregister(dev_priv);
1224
1225         i915_teardown_sysfs(dev_priv);
1226         i915_guc_log_unregister(dev_priv);
1227         drm_dev_unregister(&dev_priv->drm);
1228
1229         i915_gem_shrinker_cleanup(dev_priv);
1230 }
1231
1232 /**
1233  * i915_driver_load - setup chip and create an initial config
1234  * @pdev: PCI device
1235  * @ent: matching PCI ID entry
1236  *
1237  * The driver load routine has to do several things:
1238  *   - drive output discovery via intel_modeset_init()
1239  *   - initialize the memory manager
1240  *   - allocate initial config memory
1241  *   - setup the DRM framebuffer with the allocated memory
1242  */
1243 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1244 {
1245         const struct intel_device_info *match_info =
1246                 (struct intel_device_info *)ent->driver_data;
1247         struct drm_i915_private *dev_priv;
1248         int ret;
1249
1250         /* Enable nuclear pageflip on ILK+ */
1251         if (!i915.nuclear_pageflip && match_info->gen < 5)
1252                 driver.driver_features &= ~DRIVER_ATOMIC;
1253
1254         ret = -ENOMEM;
1255         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1256         if (dev_priv)
1257                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1258         if (ret) {
1259                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1260                 goto out_free;
1261         }
1262
1263         dev_priv->drm.pdev = pdev;
1264         dev_priv->drm.dev_private = dev_priv;
1265
1266         ret = pci_enable_device(pdev);
1267         if (ret)
1268                 goto out_fini;
1269
1270         pci_set_drvdata(pdev, &dev_priv->drm);
1271         /*
1272          * Disable the system suspend direct complete optimization, which can
1273          * leave the device suspended skipping the driver's suspend handlers
1274          * if the device was already runtime suspended. This is needed due to
1275          * the difference in our runtime and system suspend sequence and
1276          * becaue the HDA driver may require us to enable the audio power
1277          * domain during system suspend.
1278          */
1279         pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1280
1281         ret = i915_driver_init_early(dev_priv, ent);
1282         if (ret < 0)
1283                 goto out_pci_disable;
1284
1285         intel_runtime_pm_get(dev_priv);
1286
1287         ret = i915_driver_init_mmio(dev_priv);
1288         if (ret < 0)
1289                 goto out_runtime_pm_put;
1290
1291         ret = i915_driver_init_hw(dev_priv);
1292         if (ret < 0)
1293                 goto out_cleanup_mmio;
1294
1295         /*
1296          * TODO: move the vblank init and parts of modeset init steps into one
1297          * of the i915_driver_init_/i915_driver_register functions according
1298          * to the role/effect of the given init step.
1299          */
1300         if (INTEL_INFO(dev_priv)->num_pipes) {
1301                 ret = drm_vblank_init(&dev_priv->drm,
1302                                       INTEL_INFO(dev_priv)->num_pipes);
1303                 if (ret)
1304                         goto out_cleanup_hw;
1305         }
1306
1307         ret = i915_load_modeset_init(&dev_priv->drm);
1308         if (ret < 0)
1309                 goto out_cleanup_vblank;
1310
1311         i915_driver_register(dev_priv);
1312
1313         intel_runtime_pm_enable(dev_priv);
1314
1315         dev_priv->ipc_enabled = false;
1316
1317         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1318                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1319         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1320                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1321
1322         intel_runtime_pm_put(dev_priv);
1323
1324         return 0;
1325
1326 out_cleanup_vblank:
1327         drm_vblank_cleanup(&dev_priv->drm);
1328 out_cleanup_hw:
1329         i915_driver_cleanup_hw(dev_priv);
1330 out_cleanup_mmio:
1331         i915_driver_cleanup_mmio(dev_priv);
1332 out_runtime_pm_put:
1333         intel_runtime_pm_put(dev_priv);
1334         i915_driver_cleanup_early(dev_priv);
1335 out_pci_disable:
1336         pci_disable_device(pdev);
1337 out_fini:
1338         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1339         drm_dev_fini(&dev_priv->drm);
1340 out_free:
1341         kfree(dev_priv);
1342         return ret;
1343 }
1344
1345 void i915_driver_unload(struct drm_device *dev)
1346 {
1347         struct drm_i915_private *dev_priv = to_i915(dev);
1348         struct pci_dev *pdev = dev_priv->drm.pdev;
1349
1350         intel_fbdev_fini(dev);
1351
1352         if (i915_gem_suspend(dev_priv))
1353                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1354
1355         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1356
1357         drm_atomic_helper_shutdown(dev);
1358
1359         intel_gvt_cleanup(dev_priv);
1360
1361         i915_driver_unregister(dev_priv);
1362
1363         drm_vblank_cleanup(dev);
1364
1365         intel_modeset_cleanup(dev);
1366
1367         /*
1368          * free the memory space allocated for the child device
1369          * config parsed from VBT
1370          */
1371         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1372                 kfree(dev_priv->vbt.child_dev);
1373                 dev_priv->vbt.child_dev = NULL;
1374                 dev_priv->vbt.child_dev_num = 0;
1375         }
1376         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1377         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1378         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1379         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1380
1381         vga_switcheroo_unregister_client(pdev);
1382         vga_client_register(pdev, NULL, NULL, NULL);
1383
1384         intel_csr_ucode_fini(dev_priv);
1385
1386         /* Free error state after interrupts are fully disabled. */
1387         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1388         i915_reset_error_state(dev_priv);
1389
1390         /* Flush any outstanding unpin_work. */
1391         drain_workqueue(dev_priv->wq);
1392
1393         i915_gem_fini(dev_priv);
1394         intel_uc_fini_fw(dev_priv);
1395         intel_fbc_cleanup_cfb(dev_priv);
1396
1397         intel_power_domains_fini(dev_priv);
1398
1399         i915_driver_cleanup_hw(dev_priv);
1400         i915_driver_cleanup_mmio(dev_priv);
1401
1402         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1403 }
1404
1405 static void i915_driver_release(struct drm_device *dev)
1406 {
1407         struct drm_i915_private *dev_priv = to_i915(dev);
1408
1409         i915_driver_cleanup_early(dev_priv);
1410         drm_dev_fini(&dev_priv->drm);
1411
1412         kfree(dev_priv);
1413 }
1414
1415 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1416 {
1417         int ret;
1418
1419         ret = i915_gem_open(dev, file);
1420         if (ret)
1421                 return ret;
1422
1423         return 0;
1424 }
1425
1426 /**
1427  * i915_driver_lastclose - clean up after all DRM clients have exited
1428  * @dev: DRM device
1429  *
1430  * Take care of cleaning up after all DRM clients have exited.  In the
1431  * mode setting case, we want to restore the kernel's initial mode (just
1432  * in case the last client left us in a bad state).
1433  *
1434  * Additionally, in the non-mode setting case, we'll tear down the GTT
1435  * and DMA structures, since the kernel won't be using them, and clea
1436  * up any GEM state.
1437  */
1438 static void i915_driver_lastclose(struct drm_device *dev)
1439 {
1440         intel_fbdev_restore_mode(dev);
1441         vga_switcheroo_process_delayed_switch();
1442 }
1443
1444 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1445 {
1446         struct drm_i915_file_private *file_priv = file->driver_priv;
1447
1448         mutex_lock(&dev->struct_mutex);
1449         i915_gem_context_close(dev, file);
1450         i915_gem_release(dev, file);
1451         mutex_unlock(&dev->struct_mutex);
1452
1453         kfree(file_priv);
1454 }
1455
1456 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1457 {
1458         struct drm_device *dev = &dev_priv->drm;
1459         struct intel_encoder *encoder;
1460
1461         drm_modeset_lock_all(dev);
1462         for_each_intel_encoder(dev, encoder)
1463                 if (encoder->suspend)
1464                         encoder->suspend(encoder);
1465         drm_modeset_unlock_all(dev);
1466 }
1467
1468 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1469                               bool rpm_resume);
1470 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1471
1472 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1473 {
1474 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1475         if (acpi_target_system_state() < ACPI_STATE_S3)
1476                 return true;
1477 #endif
1478         return false;
1479 }
1480
1481 static int i915_drm_suspend(struct drm_device *dev)
1482 {
1483         struct drm_i915_private *dev_priv = to_i915(dev);
1484         struct pci_dev *pdev = dev_priv->drm.pdev;
1485         pci_power_t opregion_target_state;
1486         int error;
1487
1488         /* ignore lid events during suspend */
1489         mutex_lock(&dev_priv->modeset_restore_lock);
1490         dev_priv->modeset_restore = MODESET_SUSPENDED;
1491         mutex_unlock(&dev_priv->modeset_restore_lock);
1492
1493         disable_rpm_wakeref_asserts(dev_priv);
1494
1495         /* We do a lot of poking in a lot of registers, make sure they work
1496          * properly. */
1497         intel_display_set_init_power(dev_priv, true);
1498
1499         drm_kms_helper_poll_disable(dev);
1500
1501         pci_save_state(pdev);
1502
1503         error = i915_gem_suspend(dev_priv);
1504         if (error) {
1505                 dev_err(&pdev->dev,
1506                         "GEM idle failed, resume might fail\n");
1507                 goto out;
1508         }
1509
1510         intel_display_suspend(dev);
1511
1512         intel_dp_mst_suspend(dev);
1513
1514         intel_runtime_pm_disable_interrupts(dev_priv);
1515         intel_hpd_cancel_work(dev_priv);
1516
1517         intel_suspend_encoders(dev_priv);
1518
1519         intel_suspend_hw(dev_priv);
1520
1521         i915_gem_suspend_gtt_mappings(dev_priv);
1522
1523         i915_save_state(dev_priv);
1524
1525         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1526         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1527
1528         intel_uncore_suspend(dev_priv);
1529         intel_opregion_unregister(dev_priv);
1530
1531         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1532
1533         dev_priv->suspend_count++;
1534
1535         intel_csr_ucode_suspend(dev_priv);
1536
1537 out:
1538         enable_rpm_wakeref_asserts(dev_priv);
1539
1540         return error;
1541 }
1542
1543 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1544 {
1545         struct drm_i915_private *dev_priv = to_i915(dev);
1546         struct pci_dev *pdev = dev_priv->drm.pdev;
1547         bool fw_csr;
1548         int ret;
1549
1550         disable_rpm_wakeref_asserts(dev_priv);
1551
1552         intel_display_set_init_power(dev_priv, false);
1553
1554         fw_csr = !IS_GEN9_LP(dev_priv) &&
1555                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1556         /*
1557          * In case of firmware assisted context save/restore don't manually
1558          * deinit the power domains. This also means the CSR/DMC firmware will
1559          * stay active, it will power down any HW resources as required and
1560          * also enable deeper system power states that would be blocked if the
1561          * firmware was inactive.
1562          */
1563         if (!fw_csr)
1564                 intel_power_domains_suspend(dev_priv);
1565
1566         ret = 0;
1567         if (IS_GEN9_LP(dev_priv))
1568                 bxt_enable_dc9(dev_priv);
1569         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1570                 hsw_enable_pc8(dev_priv);
1571         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1572                 ret = vlv_suspend_complete(dev_priv);
1573
1574         if (ret) {
1575                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1576                 if (!fw_csr)
1577                         intel_power_domains_init_hw(dev_priv, true);
1578
1579                 goto out;
1580         }
1581
1582         pci_disable_device(pdev);
1583         /*
1584          * During hibernation on some platforms the BIOS may try to access
1585          * the device even though it's already in D3 and hang the machine. So
1586          * leave the device in D0 on those platforms and hope the BIOS will
1587          * power down the device properly. The issue was seen on multiple old
1588          * GENs with different BIOS vendors, so having an explicit blacklist
1589          * is inpractical; apply the workaround on everything pre GEN6. The
1590          * platforms where the issue was seen:
1591          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1592          * Fujitsu FSC S7110
1593          * Acer Aspire 1830T
1594          */
1595         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1596                 pci_set_power_state(pdev, PCI_D3hot);
1597
1598         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1599
1600 out:
1601         enable_rpm_wakeref_asserts(dev_priv);
1602
1603         return ret;
1604 }
1605
1606 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1607 {
1608         int error;
1609
1610         if (!dev) {
1611                 DRM_ERROR("dev: %p\n", dev);
1612                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1613                 return -ENODEV;
1614         }
1615
1616         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1617                          state.event != PM_EVENT_FREEZE))
1618                 return -EINVAL;
1619
1620         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1621                 return 0;
1622
1623         error = i915_drm_suspend(dev);
1624         if (error)
1625                 return error;
1626
1627         return i915_drm_suspend_late(dev, false);
1628 }
1629
1630 static int i915_drm_resume(struct drm_device *dev)
1631 {
1632         struct drm_i915_private *dev_priv = to_i915(dev);
1633         int ret;
1634
1635         disable_rpm_wakeref_asserts(dev_priv);
1636         intel_sanitize_gt_powersave(dev_priv);
1637
1638         ret = i915_ggtt_enable_hw(dev_priv);
1639         if (ret)
1640                 DRM_ERROR("failed to re-enable GGTT\n");
1641
1642         intel_csr_ucode_resume(dev_priv);
1643
1644         i915_gem_resume(dev_priv);
1645
1646         i915_restore_state(dev_priv);
1647         intel_pps_unlock_regs_wa(dev_priv);
1648         intel_opregion_setup(dev_priv);
1649
1650         intel_init_pch_refclk(dev_priv);
1651
1652         /*
1653          * Interrupts have to be enabled before any batches are run. If not the
1654          * GPU will hang. i915_gem_init_hw() will initiate batches to
1655          * update/restore the context.
1656          *
1657          * drm_mode_config_reset() needs AUX interrupts.
1658          *
1659          * Modeset enabling in intel_modeset_init_hw() also needs working
1660          * interrupts.
1661          */
1662         intel_runtime_pm_enable_interrupts(dev_priv);
1663
1664         drm_mode_config_reset(dev);
1665
1666         mutex_lock(&dev->struct_mutex);
1667         if (i915_gem_init_hw(dev_priv)) {
1668                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1669                 i915_gem_set_wedged(dev_priv);
1670         }
1671         mutex_unlock(&dev->struct_mutex);
1672
1673         intel_guc_resume(dev_priv);
1674
1675         intel_modeset_init_hw(dev);
1676
1677         spin_lock_irq(&dev_priv->irq_lock);
1678         if (dev_priv->display.hpd_irq_setup)
1679                 dev_priv->display.hpd_irq_setup(dev_priv);
1680         spin_unlock_irq(&dev_priv->irq_lock);
1681
1682         intel_dp_mst_resume(dev);
1683
1684         intel_display_resume(dev);
1685
1686         drm_kms_helper_poll_enable(dev);
1687
1688         /*
1689          * ... but also need to make sure that hotplug processing
1690          * doesn't cause havoc. Like in the driver load code we don't
1691          * bother with the tiny race here where we might loose hotplug
1692          * notifications.
1693          * */
1694         intel_hpd_init(dev_priv);
1695
1696         intel_opregion_register(dev_priv);
1697
1698         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1699
1700         mutex_lock(&dev_priv->modeset_restore_lock);
1701         dev_priv->modeset_restore = MODESET_DONE;
1702         mutex_unlock(&dev_priv->modeset_restore_lock);
1703
1704         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1705
1706         intel_autoenable_gt_powersave(dev_priv);
1707
1708         enable_rpm_wakeref_asserts(dev_priv);
1709
1710         return 0;
1711 }
1712
1713 static int i915_drm_resume_early(struct drm_device *dev)
1714 {
1715         struct drm_i915_private *dev_priv = to_i915(dev);
1716         struct pci_dev *pdev = dev_priv->drm.pdev;
1717         int ret;
1718
1719         /*
1720          * We have a resume ordering issue with the snd-hda driver also
1721          * requiring our device to be power up. Due to the lack of a
1722          * parent/child relationship we currently solve this with an early
1723          * resume hook.
1724          *
1725          * FIXME: This should be solved with a special hdmi sink device or
1726          * similar so that power domains can be employed.
1727          */
1728
1729         /*
1730          * Note that we need to set the power state explicitly, since we
1731          * powered off the device during freeze and the PCI core won't power
1732          * it back up for us during thaw. Powering off the device during
1733          * freeze is not a hard requirement though, and during the
1734          * suspend/resume phases the PCI core makes sure we get here with the
1735          * device powered on. So in case we change our freeze logic and keep
1736          * the device powered we can also remove the following set power state
1737          * call.
1738          */
1739         ret = pci_set_power_state(pdev, PCI_D0);
1740         if (ret) {
1741                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1742                 goto out;
1743         }
1744
1745         /*
1746          * Note that pci_enable_device() first enables any parent bridge
1747          * device and only then sets the power state for this device. The
1748          * bridge enabling is a nop though, since bridge devices are resumed
1749          * first. The order of enabling power and enabling the device is
1750          * imposed by the PCI core as described above, so here we preserve the
1751          * same order for the freeze/thaw phases.
1752          *
1753          * TODO: eventually we should remove pci_disable_device() /
1754          * pci_enable_enable_device() from suspend/resume. Due to how they
1755          * depend on the device enable refcount we can't anyway depend on them
1756          * disabling/enabling the device.
1757          */
1758         if (pci_enable_device(pdev)) {
1759                 ret = -EIO;
1760                 goto out;
1761         }
1762
1763         pci_set_master(pdev);
1764
1765         disable_rpm_wakeref_asserts(dev_priv);
1766
1767         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1768                 ret = vlv_resume_prepare(dev_priv, false);
1769         if (ret)
1770                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1771                           ret);
1772
1773         intel_uncore_resume_early(dev_priv);
1774
1775         if (IS_GEN9_LP(dev_priv)) {
1776                 if (!dev_priv->suspended_to_idle)
1777                         gen9_sanitize_dc_state(dev_priv);
1778                 bxt_disable_dc9(dev_priv);
1779         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1780                 hsw_disable_pc8(dev_priv);
1781         }
1782
1783         intel_uncore_sanitize(dev_priv);
1784
1785         if (IS_GEN9_LP(dev_priv) ||
1786             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1787                 intel_power_domains_init_hw(dev_priv, true);
1788
1789         i915_gem_sanitize(dev_priv);
1790
1791         enable_rpm_wakeref_asserts(dev_priv);
1792
1793 out:
1794         dev_priv->suspended_to_idle = false;
1795
1796         return ret;
1797 }
1798
1799 static int i915_resume_switcheroo(struct drm_device *dev)
1800 {
1801         int ret;
1802
1803         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1804                 return 0;
1805
1806         ret = i915_drm_resume_early(dev);
1807         if (ret)
1808                 return ret;
1809
1810         return i915_drm_resume(dev);
1811 }
1812
1813 /**
1814  * i915_reset - reset chip after a hang
1815  * @dev_priv: device private to reset
1816  *
1817  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1818  * on failure.
1819  *
1820  * Caller must hold the struct_mutex.
1821  *
1822  * Procedure is fairly simple:
1823  *   - reset the chip using the reset reg
1824  *   - re-init context state
1825  *   - re-init hardware status page
1826  *   - re-init ring buffer
1827  *   - re-init interrupt state
1828  *   - re-init display
1829  */
1830 void i915_reset(struct drm_i915_private *dev_priv)
1831 {
1832         struct i915_gpu_error *error = &dev_priv->gpu_error;
1833         int ret;
1834
1835         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1836         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1837
1838         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1839                 return;
1840
1841         /* Clear any previous failed attempts at recovery. Time to try again. */
1842         if (!i915_gem_unset_wedged(dev_priv))
1843                 goto wakeup;
1844
1845         error->reset_count++;
1846
1847         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1848         disable_irq(dev_priv->drm.irq);
1849         ret = i915_gem_reset_prepare(dev_priv);
1850         if (ret) {
1851                 DRM_ERROR("GPU recovery failed\n");
1852                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1853                 goto error;
1854         }
1855
1856         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1857         if (ret) {
1858                 if (ret != -ENODEV)
1859                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1860                 else
1861                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1862                 goto error;
1863         }
1864
1865         i915_gem_reset(dev_priv);
1866         intel_overlay_reset(dev_priv);
1867
1868         /* Ok, now get things going again... */
1869
1870         /*
1871          * Everything depends on having the GTT running, so we need to start
1872          * there.  Fortunately we don't need to do this unless we reset the
1873          * chip at a PCI level.
1874          *
1875          * Next we need to restore the context, but we don't use those
1876          * yet either...
1877          *
1878          * Ring buffer needs to be re-initialized in the KMS case, or if X
1879          * was running at the time of the reset (i.e. we weren't VT
1880          * switched away).
1881          */
1882         ret = i915_gem_init_hw(dev_priv);
1883         if (ret) {
1884                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1885                 goto error;
1886         }
1887
1888         i915_queue_hangcheck(dev_priv);
1889
1890 finish:
1891         i915_gem_reset_finish(dev_priv);
1892         enable_irq(dev_priv->drm.irq);
1893
1894 wakeup:
1895         clear_bit(I915_RESET_HANDOFF, &error->flags);
1896         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1897         return;
1898
1899 error:
1900         i915_gem_set_wedged(dev_priv);
1901         goto finish;
1902 }
1903
1904 static int i915_pm_suspend(struct device *kdev)
1905 {
1906         struct pci_dev *pdev = to_pci_dev(kdev);
1907         struct drm_device *dev = pci_get_drvdata(pdev);
1908
1909         if (!dev) {
1910                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1911                 return -ENODEV;
1912         }
1913
1914         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1915                 return 0;
1916
1917         return i915_drm_suspend(dev);
1918 }
1919
1920 static int i915_pm_suspend_late(struct device *kdev)
1921 {
1922         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1923
1924         /*
1925          * We have a suspend ordering issue with the snd-hda driver also
1926          * requiring our device to be power up. Due to the lack of a
1927          * parent/child relationship we currently solve this with an late
1928          * suspend hook.
1929          *
1930          * FIXME: This should be solved with a special hdmi sink device or
1931          * similar so that power domains can be employed.
1932          */
1933         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1934                 return 0;
1935
1936         return i915_drm_suspend_late(dev, false);
1937 }
1938
1939 static int i915_pm_poweroff_late(struct device *kdev)
1940 {
1941         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1942
1943         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1944                 return 0;
1945
1946         return i915_drm_suspend_late(dev, true);
1947 }
1948
1949 static int i915_pm_resume_early(struct device *kdev)
1950 {
1951         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1952
1953         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1954                 return 0;
1955
1956         return i915_drm_resume_early(dev);
1957 }
1958
1959 static int i915_pm_resume(struct device *kdev)
1960 {
1961         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1962
1963         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1964                 return 0;
1965
1966         return i915_drm_resume(dev);
1967 }
1968
1969 /* freeze: before creating the hibernation_image */
1970 static int i915_pm_freeze(struct device *kdev)
1971 {
1972         int ret;
1973
1974         ret = i915_pm_suspend(kdev);
1975         if (ret)
1976                 return ret;
1977
1978         ret = i915_gem_freeze(kdev_to_i915(kdev));
1979         if (ret)
1980                 return ret;
1981
1982         return 0;
1983 }
1984
1985 static int i915_pm_freeze_late(struct device *kdev)
1986 {
1987         int ret;
1988
1989         ret = i915_pm_suspend_late(kdev);
1990         if (ret)
1991                 return ret;
1992
1993         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1994         if (ret)
1995                 return ret;
1996
1997         return 0;
1998 }
1999
2000 /* thaw: called after creating the hibernation image, but before turning off. */
2001 static int i915_pm_thaw_early(struct device *kdev)
2002 {
2003         return i915_pm_resume_early(kdev);
2004 }
2005
2006 static int i915_pm_thaw(struct device *kdev)
2007 {
2008         return i915_pm_resume(kdev);
2009 }
2010
2011 /* restore: called after loading the hibernation image. */
2012 static int i915_pm_restore_early(struct device *kdev)
2013 {
2014         return i915_pm_resume_early(kdev);
2015 }
2016
2017 static int i915_pm_restore(struct device *kdev)
2018 {
2019         return i915_pm_resume(kdev);
2020 }
2021
2022 /*
2023  * Save all Gunit registers that may be lost after a D3 and a subsequent
2024  * S0i[R123] transition. The list of registers needing a save/restore is
2025  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2026  * registers in the following way:
2027  * - Driver: saved/restored by the driver
2028  * - Punit : saved/restored by the Punit firmware
2029  * - No, w/o marking: no need to save/restore, since the register is R/O or
2030  *                    used internally by the HW in a way that doesn't depend
2031  *                    keeping the content across a suspend/resume.
2032  * - Debug : used for debugging
2033  *
2034  * We save/restore all registers marked with 'Driver', with the following
2035  * exceptions:
2036  * - Registers out of use, including also registers marked with 'Debug'.
2037  *   These have no effect on the driver's operation, so we don't save/restore
2038  *   them to reduce the overhead.
2039  * - Registers that are fully setup by an initialization function called from
2040  *   the resume path. For example many clock gating and RPS/RC6 registers.
2041  * - Registers that provide the right functionality with their reset defaults.
2042  *
2043  * TODO: Except for registers that based on the above 3 criteria can be safely
2044  * ignored, we save/restore all others, practically treating the HW context as
2045  * a black-box for the driver. Further investigation is needed to reduce the
2046  * saved/restored registers even further, by following the same 3 criteria.
2047  */
2048 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2049 {
2050         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2051         int i;
2052
2053         /* GAM 0x4000-0x4770 */
2054         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2055         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2056         s->arb_mode             = I915_READ(ARB_MODE);
2057         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2058         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2059
2060         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2061                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2062
2063         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2064         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2065
2066         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2067         s->ecochk               = I915_READ(GAM_ECOCHK);
2068         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2069         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2070
2071         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2072
2073         /* MBC 0x9024-0x91D0, 0x8500 */
2074         s->g3dctl               = I915_READ(VLV_G3DCTL);
2075         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2076         s->mbctl                = I915_READ(GEN6_MBCTL);
2077
2078         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2079         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2080         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2081         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2082         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2083         s->rstctl               = I915_READ(GEN6_RSTCTL);
2084         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2085
2086         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2087         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2088         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2089         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2090         s->ecobus               = I915_READ(ECOBUS);
2091         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2092         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2093         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2094         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2095         s->rcedata              = I915_READ(VLV_RCEDATA);
2096         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2097
2098         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2099         s->gt_imr               = I915_READ(GTIMR);
2100         s->gt_ier               = I915_READ(GTIER);
2101         s->pm_imr               = I915_READ(GEN6_PMIMR);
2102         s->pm_ier               = I915_READ(GEN6_PMIER);
2103
2104         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2105                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2106
2107         /* GT SA CZ domain, 0x100000-0x138124 */
2108         s->tilectl              = I915_READ(TILECTL);
2109         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2110         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2111         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2112         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2113
2114         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2115         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2116         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2117         s->pcbr                 = I915_READ(VLV_PCBR);
2118         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2119
2120         /*
2121          * Not saving any of:
2122          * DFT,         0x9800-0x9EC0
2123          * SARB,        0xB000-0xB1FC
2124          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2125          * PCI CFG
2126          */
2127 }
2128
2129 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2130 {
2131         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2132         u32 val;
2133         int i;
2134
2135         /* GAM 0x4000-0x4770 */
2136         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2137         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2138         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2139         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2140         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2141
2142         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2143                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2144
2145         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2146         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2147
2148         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2149         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2150         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2151         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2152
2153         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2154
2155         /* MBC 0x9024-0x91D0, 0x8500 */
2156         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2157         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2158         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2159
2160         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2161         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2162         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2163         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2164         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2165         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2166         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2167
2168         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2169         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2170         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2171         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2172         I915_WRITE(ECOBUS,              s->ecobus);
2173         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2174         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2175         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2176         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2177         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2178         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2179
2180         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2181         I915_WRITE(GTIMR,               s->gt_imr);
2182         I915_WRITE(GTIER,               s->gt_ier);
2183         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2184         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2185
2186         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2187                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2188
2189         /* GT SA CZ domain, 0x100000-0x138124 */
2190         I915_WRITE(TILECTL,                     s->tilectl);
2191         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2192         /*
2193          * Preserve the GT allow wake and GFX force clock bit, they are not
2194          * be restored, as they are used to control the s0ix suspend/resume
2195          * sequence by the caller.
2196          */
2197         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2198         val &= VLV_GTLC_ALLOWWAKEREQ;
2199         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2200         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2201
2202         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2203         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2204         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2205         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2206
2207         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2208
2209         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2210         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2211         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2212         I915_WRITE(VLV_PCBR,                    s->pcbr);
2213         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2214 }
2215
2216 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2217                                   u32 mask, u32 val)
2218 {
2219         /* The HW does not like us polling for PW_STATUS frequently, so
2220          * use the sleeping loop rather than risk the busy spin within
2221          * intel_wait_for_register().
2222          *
2223          * Transitioning between RC6 states should be at most 2ms (see
2224          * valleyview_enable_rps) so use a 3ms timeout.
2225          */
2226         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2227                         3);
2228 }
2229
2230 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2231 {
2232         u32 val;
2233         int err;
2234
2235         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2236         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2237         if (force_on)
2238                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2239         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2240
2241         if (!force_on)
2242                 return 0;
2243
2244         err = intel_wait_for_register(dev_priv,
2245                                       VLV_GTLC_SURVIVABILITY_REG,
2246                                       VLV_GFX_CLK_STATUS_BIT,
2247                                       VLV_GFX_CLK_STATUS_BIT,
2248                                       20);
2249         if (err)
2250                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2251                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2252
2253         return err;
2254 }
2255
2256 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2257 {
2258         u32 mask;
2259         u32 val;
2260         int err;
2261
2262         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2263         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2264         if (allow)
2265                 val |= VLV_GTLC_ALLOWWAKEREQ;
2266         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2267         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2268
2269         mask = VLV_GTLC_ALLOWWAKEACK;
2270         val = allow ? mask : 0;
2271
2272         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2273         if (err)
2274                 DRM_ERROR("timeout disabling GT waking\n");
2275
2276         return err;
2277 }
2278
2279 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2280                                   bool wait_for_on)
2281 {
2282         u32 mask;
2283         u32 val;
2284
2285         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2286         val = wait_for_on ? mask : 0;
2287
2288         /*
2289          * RC6 transitioning can be delayed up to 2 msec (see
2290          * valleyview_enable_rps), use 3 msec for safety.
2291          */
2292         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2293                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2294                           onoff(wait_for_on));
2295 }
2296
2297 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2298 {
2299         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2300                 return;
2301
2302         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2303         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2304 }
2305
2306 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2307 {
2308         u32 mask;
2309         int err;
2310
2311         /*
2312          * Bspec defines the following GT well on flags as debug only, so
2313          * don't treat them as hard failures.
2314          */
2315         vlv_wait_for_gt_wells(dev_priv, false);
2316
2317         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2318         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2319
2320         vlv_check_no_gt_access(dev_priv);
2321
2322         err = vlv_force_gfx_clock(dev_priv, true);
2323         if (err)
2324                 goto err1;
2325
2326         err = vlv_allow_gt_wake(dev_priv, false);
2327         if (err)
2328                 goto err2;
2329
2330         if (!IS_CHERRYVIEW(dev_priv))
2331                 vlv_save_gunit_s0ix_state(dev_priv);
2332
2333         err = vlv_force_gfx_clock(dev_priv, false);
2334         if (err)
2335                 goto err2;
2336
2337         return 0;
2338
2339 err2:
2340         /* For safety always re-enable waking and disable gfx clock forcing */
2341         vlv_allow_gt_wake(dev_priv, true);
2342 err1:
2343         vlv_force_gfx_clock(dev_priv, false);
2344
2345         return err;
2346 }
2347
2348 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2349                                 bool rpm_resume)
2350 {
2351         int err;
2352         int ret;
2353
2354         /*
2355          * If any of the steps fail just try to continue, that's the best we
2356          * can do at this point. Return the first error code (which will also
2357          * leave RPM permanently disabled).
2358          */
2359         ret = vlv_force_gfx_clock(dev_priv, true);
2360
2361         if (!IS_CHERRYVIEW(dev_priv))
2362                 vlv_restore_gunit_s0ix_state(dev_priv);
2363
2364         err = vlv_allow_gt_wake(dev_priv, true);
2365         if (!ret)
2366                 ret = err;
2367
2368         err = vlv_force_gfx_clock(dev_priv, false);
2369         if (!ret)
2370                 ret = err;
2371
2372         vlv_check_no_gt_access(dev_priv);
2373
2374         if (rpm_resume)
2375                 intel_init_clock_gating(dev_priv);
2376
2377         return ret;
2378 }
2379
2380 static int intel_runtime_suspend(struct device *kdev)
2381 {
2382         struct pci_dev *pdev = to_pci_dev(kdev);
2383         struct drm_device *dev = pci_get_drvdata(pdev);
2384         struct drm_i915_private *dev_priv = to_i915(dev);
2385         int ret;
2386
2387         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2388                 return -ENODEV;
2389
2390         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2391                 return -ENODEV;
2392
2393         DRM_DEBUG_KMS("Suspending device\n");
2394
2395         disable_rpm_wakeref_asserts(dev_priv);
2396
2397         /*
2398          * We are safe here against re-faults, since the fault handler takes
2399          * an RPM reference.
2400          */
2401         i915_gem_runtime_suspend(dev_priv);
2402
2403         intel_guc_suspend(dev_priv);
2404
2405         intel_runtime_pm_disable_interrupts(dev_priv);
2406
2407         ret = 0;
2408         if (IS_GEN9_LP(dev_priv)) {
2409                 bxt_display_core_uninit(dev_priv);
2410                 bxt_enable_dc9(dev_priv);
2411         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2412                 hsw_enable_pc8(dev_priv);
2413         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2414                 ret = vlv_suspend_complete(dev_priv);
2415         }
2416
2417         if (ret) {
2418                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2419                 intel_runtime_pm_enable_interrupts(dev_priv);
2420
2421                 enable_rpm_wakeref_asserts(dev_priv);
2422
2423                 return ret;
2424         }
2425
2426         intel_uncore_suspend(dev_priv);
2427
2428         enable_rpm_wakeref_asserts(dev_priv);
2429         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2430
2431         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2432                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2433
2434         dev_priv->pm.suspended = true;
2435
2436         /*
2437          * FIXME: We really should find a document that references the arguments
2438          * used below!
2439          */
2440         if (IS_BROADWELL(dev_priv)) {
2441                 /*
2442                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2443                  * being detected, and the call we do at intel_runtime_resume()
2444                  * won't be able to restore them. Since PCI_D3hot matches the
2445                  * actual specification and appears to be working, use it.
2446                  */
2447                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2448         } else {
2449                 /*
2450                  * current versions of firmware which depend on this opregion
2451                  * notification have repurposed the D1 definition to mean
2452                  * "runtime suspended" vs. what you would normally expect (D3)
2453                  * to distinguish it from notifications that might be sent via
2454                  * the suspend path.
2455                  */
2456                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2457         }
2458
2459         assert_forcewakes_inactive(dev_priv);
2460
2461         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2462                 intel_hpd_poll_init(dev_priv);
2463
2464         DRM_DEBUG_KMS("Device suspended\n");
2465         return 0;
2466 }
2467
2468 static int intel_runtime_resume(struct device *kdev)
2469 {
2470         struct pci_dev *pdev = to_pci_dev(kdev);
2471         struct drm_device *dev = pci_get_drvdata(pdev);
2472         struct drm_i915_private *dev_priv = to_i915(dev);
2473         int ret = 0;
2474
2475         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2476                 return -ENODEV;
2477
2478         DRM_DEBUG_KMS("Resuming device\n");
2479
2480         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2481         disable_rpm_wakeref_asserts(dev_priv);
2482
2483         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2484         dev_priv->pm.suspended = false;
2485         if (intel_uncore_unclaimed_mmio(dev_priv))
2486                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2487
2488         intel_guc_resume(dev_priv);
2489
2490         if (IS_GEN9_LP(dev_priv)) {
2491                 bxt_disable_dc9(dev_priv);
2492                 bxt_display_core_init(dev_priv, true);
2493                 if (dev_priv->csr.dmc_payload &&
2494                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2495                         gen9_enable_dc5(dev_priv);
2496         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2497                 hsw_disable_pc8(dev_priv);
2498         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2499                 ret = vlv_resume_prepare(dev_priv, true);
2500         }
2501
2502         /*
2503          * No point of rolling back things in case of an error, as the best
2504          * we can do is to hope that things will still work (and disable RPM).
2505          */
2506         i915_gem_init_swizzling(dev_priv);
2507         i915_gem_restore_fences(dev_priv);
2508
2509         intel_runtime_pm_enable_interrupts(dev_priv);
2510
2511         /*
2512          * On VLV/CHV display interrupts are part of the display
2513          * power well, so hpd is reinitialized from there. For
2514          * everyone else do it here.
2515          */
2516         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2517                 intel_hpd_init(dev_priv);
2518
2519         enable_rpm_wakeref_asserts(dev_priv);
2520
2521         if (ret)
2522                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2523         else
2524                 DRM_DEBUG_KMS("Device resumed\n");
2525
2526         return ret;
2527 }
2528
2529 const struct dev_pm_ops i915_pm_ops = {
2530         /*
2531          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2532          * PMSG_RESUME]
2533          */
2534         .suspend = i915_pm_suspend,
2535         .suspend_late = i915_pm_suspend_late,
2536         .resume_early = i915_pm_resume_early,
2537         .resume = i915_pm_resume,
2538
2539         /*
2540          * S4 event handlers
2541          * @freeze, @freeze_late    : called (1) before creating the
2542          *                            hibernation image [PMSG_FREEZE] and
2543          *                            (2) after rebooting, before restoring
2544          *                            the image [PMSG_QUIESCE]
2545          * @thaw, @thaw_early       : called (1) after creating the hibernation
2546          *                            image, before writing it [PMSG_THAW]
2547          *                            and (2) after failing to create or
2548          *                            restore the image [PMSG_RECOVER]
2549          * @poweroff, @poweroff_late: called after writing the hibernation
2550          *                            image, before rebooting [PMSG_HIBERNATE]
2551          * @restore, @restore_early : called after rebooting and restoring the
2552          *                            hibernation image [PMSG_RESTORE]
2553          */
2554         .freeze = i915_pm_freeze,
2555         .freeze_late = i915_pm_freeze_late,
2556         .thaw_early = i915_pm_thaw_early,
2557         .thaw = i915_pm_thaw,
2558         .poweroff = i915_pm_suspend,
2559         .poweroff_late = i915_pm_poweroff_late,
2560         .restore_early = i915_pm_restore_early,
2561         .restore = i915_pm_restore,
2562
2563         /* S0ix (via runtime suspend) event handlers */
2564         .runtime_suspend = intel_runtime_suspend,
2565         .runtime_resume = intel_runtime_resume,
2566 };
2567
2568 static const struct vm_operations_struct i915_gem_vm_ops = {
2569         .fault = i915_gem_fault,
2570         .open = drm_gem_vm_open,
2571         .close = drm_gem_vm_close,
2572 };
2573
2574 static const struct file_operations i915_driver_fops = {
2575         .owner = THIS_MODULE,
2576         .open = drm_open,
2577         .release = drm_release,
2578         .unlocked_ioctl = drm_ioctl,
2579         .mmap = drm_gem_mmap,
2580         .poll = drm_poll,
2581         .read = drm_read,
2582         .compat_ioctl = i915_compat_ioctl,
2583         .llseek = noop_llseek,
2584 };
2585
2586 static int
2587 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2588                           struct drm_file *file)
2589 {
2590         return -ENODEV;
2591 }
2592
2593 static const struct drm_ioctl_desc i915_ioctls[] = {
2594         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2595         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2596         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2597         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2598         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2599         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2600         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2601         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2602         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2603         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2604         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2605         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2606         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2607         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2608         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2609         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2610         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2611         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2612         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2613         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2614         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2615         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2616         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2617         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2618         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2619         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2620         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2621         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2622         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2623         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2624         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2625         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2626         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2627         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2628         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2629         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2630         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2631         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2632         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2633         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2634         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2635         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2636         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2637         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2638         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2639         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2640         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2641         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2642         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2643         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2644         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2645         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2646         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2647 };
2648
2649 static struct drm_driver driver = {
2650         /* Don't use MTRRs here; the Xserver or userspace app should
2651          * deal with them for Intel hardware.
2652          */
2653         .driver_features =
2654             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2655             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2656         .release = i915_driver_release,
2657         .open = i915_driver_open,
2658         .lastclose = i915_driver_lastclose,
2659         .postclose = i915_driver_postclose,
2660         .set_busid = drm_pci_set_busid,
2661
2662         .gem_close_object = i915_gem_close_object,
2663         .gem_free_object_unlocked = i915_gem_free_object,
2664         .gem_vm_ops = &i915_gem_vm_ops,
2665
2666         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2667         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2668         .gem_prime_export = i915_gem_prime_export,
2669         .gem_prime_import = i915_gem_prime_import,
2670
2671         .dumb_create = i915_gem_dumb_create,
2672         .dumb_map_offset = i915_gem_mmap_gtt,
2673         .dumb_destroy = drm_gem_dumb_destroy,
2674         .ioctls = i915_ioctls,
2675         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2676         .fops = &i915_driver_fops,
2677         .name = DRIVER_NAME,
2678         .desc = DRIVER_DESC,
2679         .date = DRIVER_DATE,
2680         .major = DRIVER_MAJOR,
2681         .minor = DRIVER_MINOR,
2682         .patchlevel = DRIVER_PATCHLEVEL,
2683 };
2684
2685 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2686 #include "selftests/mock_drm.c"
2687 #endif