drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_vgpu.h"
  54 #include "intel_drv.h"
  55 #include "intel_uc.h"
  56
  57 static struct drm_driver driver;
  58
  59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  60 static unsigned int i915_load_fail_count;
  61
  62 bool __i915_inject_load_failure(const char *func, int line)
  63 {
  64         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  65                 return false;
  66
  67         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  68                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  69                          i915_modparams.inject_load_failure, func, line);
  70                 i915_modparams.inject_load_failure = 0;
  71                 return true;
  72         }
  73
  74         return false;
  75 }
  76
  77 bool i915_error_injected(void)
  78 {
  79         return i915_load_fail_count && !i915_modparams.inject_load_failure;
  80 }
  81
  82 #endif
  83
  84 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  85 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  86                     "providing the dmesg log by booting with drm.debug=0xf"
  87
  88 void
  89 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  90               const char *fmt, ...)
  91 {
  92         static bool shown_bug_once;
  93         struct device *kdev = dev_priv->drm.dev;
  94         bool is_error = level[1] <= KERN_ERR[1];
  95         bool is_debug = level[1] == KERN_DEBUG[1];
  96         struct va_format vaf;
  97         va_list args;
  98
  99         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
 100                 return;
 101
 102         va_start(args, fmt);
 103
 104         vaf.fmt = fmt;
 105         vaf.va = &args;
 106
 107         if (is_error)
 108                 dev_printk(level, kdev, "%pV", &vaf);
 109         else
 110                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 111                            __builtin_return_address(0), &vaf);
 112
 113         va_end(args);
 114
 115         if (is_error && !shown_bug_once) {
 116                 /*
 117                  * Ask the user to file a bug report for the error, except
 118                  * if they may have caused the bug by fiddling with unsafe
 119                  * module parameters.
 120                  */
 121                 if (!test_taint(TAINT_USER))
 122                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 123                 shown_bug_once = true;
 124         }
 125 }
 126
 127 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 128 static enum intel_pch
 129 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 130 {
 131         switch (id) {
 132         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 133                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 134                 WARN_ON(!IS_GEN5(dev_priv));
 135                 return PCH_IBX;
 136         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 137                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 138                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 139                 return PCH_CPT;
 140         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 141                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 142                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 143                 /* PantherPoint is CPT compatible */
 144                 return PCH_CPT;
 145         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 146                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 147                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 148                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 149                 return PCH_LPT;
 150         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 151                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 152                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 153                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 154                 return PCH_LPT;
 155         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 156                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 157                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 158                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 159                 /* WildcatPoint is LPT compatible */
 160                 return PCH_LPT;
 161         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 162                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 163                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 164                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 165                 /* WildcatPoint is LPT compatible */
 166                 return PCH_LPT;
 167         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 168                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 169                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 170                 return PCH_SPT;
 171         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 172                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 173                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 174                 return PCH_SPT;
 175         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 176                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 177                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 178                         !IS_COFFEELAKE(dev_priv));
 179                 return PCH_KBP;
 180         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 181                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 182                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 183                 return PCH_CNP;
 184         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 185                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 186                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 187                 return PCH_CNP;
 188         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 189                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 190                 WARN_ON(!IS_ICELAKE(dev_priv));
 191                 return PCH_ICP;
 192         default:
 193                 return PCH_NONE;
 194         }
 195 }
 196
 197 static bool intel_is_virt_pch(unsigned short id,
 198                               unsigned short svendor, unsigned short sdevice)
 199 {
 200         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 201                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 202                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 203                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 204                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 205 }
 206
 207 static unsigned short
 208 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 209 {
 210         unsigned short id = 0;
 211
 212         /*
 213          * In a virtualized passthrough environment we can be in a
 214          * setup where the ISA bridge is not able to be passed through.
 215          * In this case, a south bridge can be emulated and we have to
 216          * make an educated guess as to which PCH is really there.
 217          */
 218
 219         if (IS_GEN5(dev_priv))
 220                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 221         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 222                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 223         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 224                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 225         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 226                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 227         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 228                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 229         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 230                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 231         else if (IS_ICELAKE(dev_priv))
 232                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 233
 234         if (id)
 235                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 236         else
 237                 DRM_DEBUG_KMS("Assuming no PCH\n");
 238
 239         return id;
 240 }
 241
 242 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 243 {
 244         struct pci_dev *pch = NULL;
 245
 246         /*
 247          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 248          * make graphics device passthrough work easy for VMM, that only
 249          * need to expose ISA bridge to let driver know the real hardware
 250          * underneath. This is a requirement from virtualization team.
 251          *
 252          * In some virtualized environments (e.g. XEN), there is irrelevant
 253          * ISA bridge in the system. To work reliably, we should scan trhough
 254          * all the ISA bridge devices and check for the first match, instead
 255          * of only checking the first one.
 256          */
 257         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 258                 unsigned short id;
 259                 enum intel_pch pch_type;
 260
 261                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 262                         continue;
 263
 264                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 265
 266                 pch_type = intel_pch_type(dev_priv, id);
 267                 if (pch_type != PCH_NONE) {
 268                         dev_priv->pch_type = pch_type;
 269                         dev_priv->pch_id = id;
 270                         break;
 271                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 272                                          pch->subsystem_device)) {
 273                         id = intel_virt_detect_pch(dev_priv);
 274                         pch_type = intel_pch_type(dev_priv, id);
 275
 276                         /* Sanity check virtual PCH id */
 277                         if (WARN_ON(id && pch_type == PCH_NONE))
 278                                 id = 0;
 279
 280                         dev_priv->pch_type = pch_type;
 281                         dev_priv->pch_id = id;
 282                         break;
 283                 }
 284         }
 285
 286         /*
 287          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
 288          * display.
 289          */
 290         if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
 291                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
 292                 dev_priv->pch_type = PCH_NOP;
 293                 dev_priv->pch_id = 0;
 294         }
 295
 296         if (!pch)
 297                 DRM_DEBUG_KMS("No PCH found.\n");
 298
 299         pci_dev_put(pch);
 300 }
 301
 302 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 303                                struct drm_file *file_priv)
 304 {
 305         struct drm_i915_private *dev_priv = to_i915(dev);
 306         struct pci_dev *pdev = dev_priv->drm.pdev;
 307         drm_i915_getparam_t *param = data;
 308         int value;
 309
 310         switch (param->param) {
 311         case I915_PARAM_IRQ_ACTIVE:
 312         case I915_PARAM_ALLOW_BATCHBUFFER:
 313         case I915_PARAM_LAST_DISPATCH:
 314         case I915_PARAM_HAS_EXEC_CONSTANTS:
 315                 /* Reject all old ums/dri params. */
 316                 return -ENODEV;
 317         case I915_PARAM_CHIPSET_ID:
 318                 value = pdev->device;
 319                 break;
 320         case I915_PARAM_REVISION:
 321                 value = pdev->revision;
 322                 break;
 323         case I915_PARAM_NUM_FENCES_AVAIL:
 324                 value = dev_priv->num_fence_regs;
 325                 break;
 326         case I915_PARAM_HAS_OVERLAY:
 327                 value = dev_priv->overlay ? 1 : 0;
 328                 break;
 329         case I915_PARAM_HAS_BSD:
 330                 value = !!dev_priv->engine[VCS];
 331                 break;
 332         case I915_PARAM_HAS_BLT:
 333                 value = !!dev_priv->engine[BCS];
 334                 break;
 335         case I915_PARAM_HAS_VEBOX:
 336                 value = !!dev_priv->engine[VECS];
 337                 break;
 338         case I915_PARAM_HAS_BSD2:
 339                 value = !!dev_priv->engine[VCS2];
 340                 break;
 341         case I915_PARAM_HAS_LLC:
 342                 value = HAS_LLC(dev_priv);
 343                 break;
 344         case I915_PARAM_HAS_WT:
 345                 value = HAS_WT(dev_priv);
 346                 break;
 347         case I915_PARAM_HAS_ALIASING_PPGTT:
 348                 value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
 349                 break;
 350         case I915_PARAM_HAS_SEMAPHORES:
 351                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 352                 break;
 353         case I915_PARAM_HAS_SECURE_BATCHES:
 354                 value = capable(CAP_SYS_ADMIN);
 355                 break;
 356         case I915_PARAM_CMD_PARSER_VERSION:
 357                 value = i915_cmd_parser_get_version(dev_priv);
 358                 break;
 359         case I915_PARAM_SUBSLICE_TOTAL:
 360                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 361                 if (!value)
 362                         return -ENODEV;
 363                 break;
 364         case I915_PARAM_EU_TOTAL:
 365                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 366                 if (!value)
 367                         return -ENODEV;
 368                 break;
 369         case I915_PARAM_HAS_GPU_RESET:
 370                 value = i915_modparams.enable_hangcheck &&
 371                         intel_has_gpu_reset(dev_priv);
 372                 if (value && intel_has_reset_engine(dev_priv))
 373                         value = 2;
 374                 break;
 375         case I915_PARAM_HAS_RESOURCE_STREAMER:
 376                 value = 0;
 377                 break;
 378         case I915_PARAM_HAS_POOLED_EU:
 379                 value = HAS_POOLED_EU(dev_priv);
 380                 break;
 381         case I915_PARAM_MIN_EU_IN_POOL:
 382                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 383                 break;
 384         case I915_PARAM_HUC_STATUS:
 385                 value = intel_huc_check_status(&dev_priv->huc);
 386                 if (value < 0)
 387                         return value;
 388                 break;
 389         case I915_PARAM_MMAP_GTT_VERSION:
 390                 /* Though we've started our numbering from 1, and so class all
 391                  * earlier versions as 0, in effect their value is undefined as
 392                  * the ioctl will report EINVAL for the unknown param!
 393                  */
 394                 value = i915_gem_mmap_gtt_version();
 395                 break;
 396         case I915_PARAM_HAS_SCHEDULER:
 397                 value = dev_priv->caps.scheduler;
 398                 break;
 399
 400         case I915_PARAM_MMAP_VERSION:
 401                 /* Remember to bump this if the version changes! */
 402         case I915_PARAM_HAS_GEM:
 403         case I915_PARAM_HAS_PAGEFLIPPING:
 404         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 405         case I915_PARAM_HAS_RELAXED_FENCING:
 406         case I915_PARAM_HAS_COHERENT_RINGS:
 407         case I915_PARAM_HAS_RELAXED_DELTA:
 408         case I915_PARAM_HAS_GEN7_SOL_RESET:
 409         case I915_PARAM_HAS_WAIT_TIMEOUT:
 410         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 411         case I915_PARAM_HAS_PINNED_BATCHES:
 412         case I915_PARAM_HAS_EXEC_NO_RELOC:
 413         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 414         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 415         case I915_PARAM_HAS_EXEC_SOFTPIN:
 416         case I915_PARAM_HAS_EXEC_ASYNC:
 417         case I915_PARAM_HAS_EXEC_FENCE:
 418         case I915_PARAM_HAS_EXEC_CAPTURE:
 419         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 420         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 421                 /* For the time being all of these are always true;
 422                  * if some supported hardware does not have one of these
 423                  * features this value needs to be provided from
 424                  * INTEL_INFO(), a feature macro, or similar.
 425                  */
 426                 value = 1;
 427                 break;
 428         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 429                 value = intel_engines_has_context_isolation(dev_priv);
 430                 break;
 431         case I915_PARAM_SLICE_MASK:
 432                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 433                 if (!value)
 434                         return -ENODEV;
 435                 break;
 436         case I915_PARAM_SUBSLICE_MASK:
 437                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 438                 if (!value)
 439                         return -ENODEV;
 440                 break;
 441         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 442                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 443                 break;
 444         case I915_PARAM_MMAP_GTT_COHERENT:
 445                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
 446                 break;
 447         default:
 448                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 449                 return -EINVAL;
 450         }
 451
 452         if (put_user(value, param->value))
 453                 return -EFAULT;
 454
 455         return 0;
 456 }
 457
 458 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 459 {
 460         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 461
 462         dev_priv->bridge_dev =
 463                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 464         if (!dev_priv->bridge_dev) {
 465                 DRM_ERROR("bridge device not found\n");
 466                 return -1;
 467         }
 468         return 0;
 469 }
 470
 471 /* Allocate space for the MCH regs if needed, return nonzero on error */
 472 static int
 473 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 474 {
 475         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 476         u32 temp_lo, temp_hi = 0;
 477         u64 mchbar_addr;
 478         int ret;
 479
 480         if (INTEL_GEN(dev_priv) >= 4)
 481                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 482         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 483         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 484
 485         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 486 #ifdef CONFIG_PNP
 487         if (mchbar_addr &&
 488             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 489                 return 0;
 490 #endif
 491
 492         /* Get some space for it */
 493         dev_priv->mch_res.name = "i915 MCHBAR";
 494         dev_priv->mch_res.flags = IORESOURCE_MEM;
 495         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 496                                      &dev_priv->mch_res,
 497                                      MCHBAR_SIZE, MCHBAR_SIZE,
 498                                      PCIBIOS_MIN_MEM,
 499                                      0, pcibios_align_resource,
 500                                      dev_priv->bridge_dev);
 501         if (ret) {
 502                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 503                 dev_priv->mch_res.start = 0;
 504                 return ret;
 505         }
 506
 507         if (INTEL_GEN(dev_priv) >= 4)
 508                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 509                                        upper_32_bits(dev_priv->mch_res.start));
 510
 511         pci_write_config_dword(dev_priv->bridge_dev, reg,
 512                                lower_32_bits(dev_priv->mch_res.start));
 513         return 0;
 514 }
 515
 516 /* Setup MCHBAR if possible, return true if we should disable it again */
 517 static void
 518 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 519 {
 520         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 521         u32 temp;
 522         bool enabled;
 523
 524         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 525                 return;
 526
 527         dev_priv->mchbar_need_disable = false;
 528
 529         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 530                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 531                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 532         } else {
 533                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 534                 enabled = temp & 1;
 535         }
 536
 537         /* If it's already enabled, don't have to do anything */
 538         if (enabled)
 539                 return;
 540
 541         if (intel_alloc_mchbar_resource(dev_priv))
 542                 return;
 543
 544         dev_priv->mchbar_need_disable = true;
 545
 546         /* Space is allocated or reserved, so enable it. */
 547         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 548                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 549                                        temp | DEVEN_MCHBAR_EN);
 550         } else {
 551                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 552                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 553         }
 554 }
 555
 556 static void
 557 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 558 {
 559         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 560
 561         if (dev_priv->mchbar_need_disable) {
 562                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 563                         u32 deven_val;
 564
 565                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 566                                               &deven_val);
 567                         deven_val &= ~DEVEN_MCHBAR_EN;
 568                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 569                                                deven_val);
 570                 } else {
 571                         u32 mchbar_val;
 572
 573                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 574                                               &mchbar_val);
 575                         mchbar_val &= ~1;
 576                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 577                                                mchbar_val);
 578                 }
 579         }
 580
 581         if (dev_priv->mch_res.start)
 582                 release_resource(&dev_priv->mch_res);
 583 }
 584
 585 /* true = enable decode, false = disable decoder */
 586 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 587 {
 588         struct drm_i915_private *dev_priv = cookie;
 589
 590         intel_modeset_vga_set_state(dev_priv, state);
 591         if (state)
 592                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 593                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 594         else
 595                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 596 }
 597
 598 static int i915_resume_switcheroo(struct drm_device *dev);
 599 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 600
 601 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 602 {
 603         struct drm_device *dev = pci_get_drvdata(pdev);
 604         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 605
 606         if (state == VGA_SWITCHEROO_ON) {
 607                 pr_info("switched on\n");
 608                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 609                 /* i915 resume handler doesn't set to D0 */
 610                 pci_set_power_state(pdev, PCI_D0);
 611                 i915_resume_switcheroo(dev);
 612                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 613         } else {
 614                 pr_info("switched off\n");
 615                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 616                 i915_suspend_switcheroo(dev, pmm);
 617                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 618         }
 619 }
 620
 621 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 622 {
 623         struct drm_device *dev = pci_get_drvdata(pdev);
 624
 625         /*
 626          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 627          * locking inversion with the driver load path. And the access here is
 628          * completely racy anyway. So don't bother with locking for now.
 629          */
 630         return dev->open_count == 0;
 631 }
 632
 633 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 634         .set_gpu_state = i915_switcheroo_set_state,
 635         .reprobe = NULL,
 636         .can_switch = i915_switcheroo_can_switch,
 637 };
 638
 639 static int i915_load_modeset_init(struct drm_device *dev)
 640 {
 641         struct drm_i915_private *dev_priv = to_i915(dev);
 642         struct pci_dev *pdev = dev_priv->drm.pdev;
 643         int ret;
 644
 645         if (i915_inject_load_failure())
 646                 return -ENODEV;
 647
 648         if (INTEL_INFO(dev_priv)->num_pipes) {
 649                 ret = drm_vblank_init(&dev_priv->drm,
 650                                       INTEL_INFO(dev_priv)->num_pipes);
 651                 if (ret)
 652                         goto out;
 653         }
 654
 655         intel_bios_init(dev_priv);
 656
 657         /* If we have > 1 VGA cards, then we need to arbitrate access
 658          * to the common VGA resources.
 659          *
 660          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 661          * then we do not take part in VGA arbitration and the
 662          * vga_client_register() fails with -ENODEV.
 663          */
 664         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 665         if (ret && ret != -ENODEV)
 666                 goto out;
 667
 668         intel_register_dsm_handler();
 669
 670         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 671         if (ret)
 672                 goto cleanup_vga_client;
 673
 674         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 675         intel_update_rawclk(dev_priv);
 676
 677         intel_power_domains_init_hw(dev_priv, false);
 678
 679         intel_csr_ucode_init(dev_priv);
 680
 681         ret = intel_irq_install(dev_priv);
 682         if (ret)
 683                 goto cleanup_csr;
 684
 685         intel_setup_gmbus(dev_priv);
 686
 687         /* Important: The output setup functions called by modeset_init need
 688          * working irqs for e.g. gmbus and dp aux transfers. */
 689         ret = intel_modeset_init(dev);
 690         if (ret)
 691                 goto cleanup_irq;
 692
 693         ret = i915_gem_init(dev_priv);
 694         if (ret)
 695                 goto cleanup_modeset;
 696
 697         intel_overlay_setup(dev_priv);
 698
 699         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 700                 return 0;
 701
 702         ret = intel_fbdev_init(dev);
 703         if (ret)
 704                 goto cleanup_gem;
 705
 706         /* Only enable hotplug handling once the fbdev is fully set up. */
 707         intel_hpd_init(dev_priv);
 708
 709         intel_init_ipc(dev_priv);
 710
 711         return 0;
 712
 713 cleanup_gem:
 714         if (i915_gem_suspend(dev_priv))
 715                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 716         i915_gem_fini(dev_priv);
 717 cleanup_modeset:
 718         intel_modeset_cleanup(dev);
 719 cleanup_irq:
 720         drm_irq_uninstall(dev);
 721         intel_teardown_gmbus(dev_priv);
 722 cleanup_csr:
 723         intel_csr_ucode_fini(dev_priv);
 724         intel_power_domains_fini_hw(dev_priv);
 725         vga_switcheroo_unregister_client(pdev);
 726 cleanup_vga_client:
 727         vga_client_register(pdev, NULL, NULL, NULL);
 728 out:
 729         return ret;
 730 }
 731
 732 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 733 {
 734         struct apertures_struct *ap;
 735         struct pci_dev *pdev = dev_priv->drm.pdev;
 736         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 737         bool primary;
 738         int ret;
 739
 740         ap = alloc_apertures(1);
 741         if (!ap)
 742                 return -ENOMEM;
 743
 744         ap->ranges[0].base = ggtt->gmadr.start;
 745         ap->ranges[0].size = ggtt->mappable_end;
 746
 747         primary =
 748                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 749
 750         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 751
 752         kfree(ap);
 753
 754         return ret;
 755 }
 756
 757 #if !defined(CONFIG_VGA_CONSOLE)
 758 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 759 {
 760         return 0;
 761 }
 762 #elif !defined(CONFIG_DUMMY_CONSOLE)
 763 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 764 {
 765         return -ENODEV;
 766 }
 767 #else
 768 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 769 {
 770         int ret = 0;
 771
 772         DRM_INFO("Replacing VGA console driver\n");
 773
 774         console_lock();
 775         if (con_is_bound(&vga_con))
 776                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 777         if (ret == 0) {
 778                 ret = do_unregister_con_driver(&vga_con);
 779
 780                 /* Ignore "already unregistered". */
 781                 if (ret == -ENODEV)
 782                         ret = 0;
 783         }
 784         console_unlock();
 785
 786         return ret;
 787 }
 788 #endif
 789
 790 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 791 {
 792         /*
 793          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 794          * CHV x1 PHY (DP/HDMI D)
 795          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 796          */
 797         if (IS_CHERRYVIEW(dev_priv)) {
 798                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 799                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 800         } else if (IS_VALLEYVIEW(dev_priv)) {
 801                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 802         }
 803 }
 804
 805 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 806 {
 807         /*
 808          * The i915 workqueue is primarily used for batched retirement of
 809          * requests (and thus managing bo) once the task has been completed
 810          * by the GPU. i915_retire_requests() is called directly when we
 811          * need high-priority retirement, such as waiting for an explicit
 812          * bo.
 813          *
 814          * It is also used for periodic low-priority events, such as
 815          * idle-timers and recording error state.
 816          *
 817          * All tasks on the workqueue are expected to acquire the dev mutex
 818          * so there is no point in running more than one instance of the
 819          * workqueue at any time.  Use an ordered one.
 820          */
 821         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 822         if (dev_priv->wq == NULL)
 823                 goto out_err;
 824
 825         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 826         if (dev_priv->hotplug.dp_wq == NULL)
 827                 goto out_free_wq;
 828
 829         return 0;
 830
 831 out_free_wq:
 832         destroy_workqueue(dev_priv->wq);
 833 out_err:
 834         DRM_ERROR("Failed to allocate workqueues.\n");
 835
 836         return -ENOMEM;
 837 }
 838
 839 static void i915_engines_cleanup(struct drm_i915_private *i915)
 840 {
 841         struct intel_engine_cs *engine;
 842         enum intel_engine_id id;
 843
 844         for_each_engine(engine, i915, id)
 845                 kfree(engine);
 846 }
 847
 848 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 849 {
 850         destroy_workqueue(dev_priv->hotplug.dp_wq);
 851         destroy_workqueue(dev_priv->wq);
 852 }
 853
 854 /*
 855  * We don't keep the workarounds for pre-production hardware, so we expect our
 856  * driver to fail on these machines in one way or another. A little warning on
 857  * dmesg may help both the user and the bug triagers.
 858  *
 859  * Our policy for removing pre-production workarounds is to keep the
 860  * current gen workarounds as a guide to the bring-up of the next gen
 861  * (workarounds have a habit of persisting!). Anything older than that
 862  * should be removed along with the complications they introduce.
 863  */
 864 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 865 {
 866         bool pre = false;
 867
 868         pre |= IS_HSW_EARLY_SDV(dev_priv);
 869         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 870         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 871         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 872
 873         if (pre) {
 874                 DRM_ERROR("This is a pre-production stepping. "
 875                           "It may not be fully functional.\n");
 876                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 877         }
 878 }
 879
 880 /**
 881  * i915_driver_init_early - setup state not requiring device access
 882  * @dev_priv: device private
 883  *
 884  * Initialize everything that is a "SW-only" state, that is state not
 885  * requiring accessing the device or exposing the driver via kernel internal
 886  * or userspace interfaces. Example steps belonging here: lock initialization,
 887  * system memory allocation, setting up device specific attributes and
 888  * function hooks not requiring accessing the device.
 889  */
 890 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 891 {
 892         int ret = 0;
 893
 894         if (i915_inject_load_failure())
 895                 return -ENODEV;
 896
 897         spin_lock_init(&dev_priv->irq_lock);
 898         spin_lock_init(&dev_priv->gpu_error.lock);
 899         mutex_init(&dev_priv->backlight_lock);
 900         spin_lock_init(&dev_priv->uncore.lock);
 901
 902         mutex_init(&dev_priv->sb_lock);
 903         mutex_init(&dev_priv->av_mutex);
 904         mutex_init(&dev_priv->wm.wm_mutex);
 905         mutex_init(&dev_priv->pps_mutex);
 906
 907         i915_memcpy_init_early(dev_priv);
 908
 909         ret = i915_workqueues_init(dev_priv);
 910         if (ret < 0)
 911                 goto err_engines;
 912
 913         ret = i915_gem_init_early(dev_priv);
 914         if (ret < 0)
 915                 goto err_workqueues;
 916
 917         /* This must be called before any calls to HAS_PCH_* */
 918         intel_detect_pch(dev_priv);
 919
 920         intel_wopcm_init_early(&dev_priv->wopcm);
 921         intel_uc_init_early(dev_priv);
 922         intel_pm_setup(dev_priv);
 923         intel_init_dpio(dev_priv);
 924         ret = intel_power_domains_init(dev_priv);
 925         if (ret < 0)
 926                 goto err_uc;
 927         intel_irq_init(dev_priv);
 928         intel_hangcheck_init(dev_priv);
 929         intel_init_display_hooks(dev_priv);
 930         intel_init_clock_gating_hooks(dev_priv);
 931         intel_init_audio_hooks(dev_priv);
 932         intel_display_crc_init(dev_priv);
 933
 934         intel_detect_preproduction_hw(dev_priv);
 935
 936         return 0;
 937
 938 err_uc:
 939         intel_uc_cleanup_early(dev_priv);
 940         i915_gem_cleanup_early(dev_priv);
 941 err_workqueues:
 942         i915_workqueues_cleanup(dev_priv);
 943 err_engines:
 944         i915_engines_cleanup(dev_priv);
 945         return ret;
 946 }
 947
 948 /**
 949  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 950  * @dev_priv: device private
 951  */
 952 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 953 {
 954         intel_irq_fini(dev_priv);
 955         intel_power_domains_cleanup(dev_priv);
 956         intel_uc_cleanup_early(dev_priv);
 957         i915_gem_cleanup_early(dev_priv);
 958         i915_workqueues_cleanup(dev_priv);
 959         i915_engines_cleanup(dev_priv);
 960 }
 961
 962 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 963 {
 964         struct pci_dev *pdev = dev_priv->drm.pdev;
 965         int mmio_bar;
 966         int mmio_size;
 967
 968         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 969         /*
 970          * Before gen4, the registers and the GTT are behind different BARs.
 971          * However, from gen4 onwards, the registers and the GTT are shared
 972          * in the same BAR, so we want to restrict this ioremap from
 973          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 974          * the register BAR remains the same size for all the earlier
 975          * generations up to Ironlake.
 976          */
 977         if (INTEL_GEN(dev_priv) < 5)
 978                 mmio_size = 512 * 1024;
 979         else
 980                 mmio_size = 2 * 1024 * 1024;
 981         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 982         if (dev_priv->regs == NULL) {
 983                 DRM_ERROR("failed to map registers\n");
 984
 985                 return -EIO;
 986         }
 987
 988         /* Try to make sure MCHBAR is enabled before poking at it */
 989         intel_setup_mchbar(dev_priv);
 990
 991         return 0;
 992 }
 993
 994 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 995 {
 996         struct pci_dev *pdev = dev_priv->drm.pdev;
 997
 998         intel_teardown_mchbar(dev_priv);
 999         pci_iounmap(pdev, dev_priv->regs);
1000 }
1001
1002 /**
1003  * i915_driver_init_mmio - setup device MMIO
1004  * @dev_priv: device private
1005  *
1006  * Setup minimal device state necessary for MMIO accesses later in the
1007  * initialization sequence. The setup here should avoid any other device-wide
1008  * side effects or exposing the driver via kernel internal or user space
1009  * interfaces.
1010  */
1011 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1012 {
1013         int ret;
1014
1015         if (i915_inject_load_failure())
1016                 return -ENODEV;
1017
1018         if (i915_get_bridge_dev(dev_priv))
1019                 return -EIO;
1020
1021         ret = i915_mmio_setup(dev_priv);
1022         if (ret < 0)
1023                 goto err_bridge;
1024
1025         intel_uncore_init(dev_priv);
1026
1027         intel_device_info_init_mmio(dev_priv);
1028
1029         intel_uncore_prune(dev_priv);
1030
1031         intel_uc_init_mmio(dev_priv);
1032
1033         ret = intel_engines_init_mmio(dev_priv);
1034         if (ret)
1035                 goto err_uncore;
1036
1037         i915_gem_init_mmio(dev_priv);
1038
1039         return 0;
1040
1041 err_uncore:
1042         intel_uncore_fini(dev_priv);
1043         i915_mmio_cleanup(dev_priv);
1044 err_bridge:
1045         pci_dev_put(dev_priv->bridge_dev);
1046
1047         return ret;
1048 }
1049
1050 /**
1051  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1052  * @dev_priv: device private
1053  */
1054 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1055 {
1056         intel_uncore_fini(dev_priv);
1057         i915_mmio_cleanup(dev_priv);
1058         pci_dev_put(dev_priv->bridge_dev);
1059 }
1060
1061 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1062 {
1063         intel_gvt_sanitize_options(dev_priv);
1064 }
1065
1066 static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
1067 {
1068         if (size == 0)
1069                 return I915_DRAM_RANK_INVALID;
1070         if (rank == SKL_DRAM_RANK_SINGLE)
1071                 return I915_DRAM_RANK_SINGLE;
1072         else if (rank == SKL_DRAM_RANK_DUAL)
1073                 return I915_DRAM_RANK_DUAL;
1074
1075         return I915_DRAM_RANK_INVALID;
1076 }
1077
1078 static bool
1079 skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
1080 {
1081         if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
1082                 return true;
1083         else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
1084                 return true;
1085         else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
1086                 return true;
1087         else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
1088                 return true;
1089
1090         return false;
1091 }
1092
1093 static int
1094 skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
1095 {
1096         u32 tmp_l, tmp_s;
1097         u32 s_val = val >> SKL_DRAM_S_SHIFT;
1098
1099         if (!val)
1100                 return -EINVAL;
1101
1102         tmp_l = val & SKL_DRAM_SIZE_MASK;
1103         tmp_s = s_val & SKL_DRAM_SIZE_MASK;
1104
1105         if (tmp_l == 0 && tmp_s == 0)
1106                 return -EINVAL;
1107
1108         ch->l_info.size = tmp_l;
1109         ch->s_info.size = tmp_s;
1110
1111         tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1112         tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1113         ch->l_info.width = (1 << tmp_l) * 8;
1114         ch->s_info.width = (1 << tmp_s) * 8;
1115
1116         tmp_l = val & SKL_DRAM_RANK_MASK;
1117         tmp_s = s_val & SKL_DRAM_RANK_MASK;
1118         ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);
1119         ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);
1120
1121         if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||
1122             ch->s_info.rank == I915_DRAM_RANK_DUAL)
1123                 ch->rank = I915_DRAM_RANK_DUAL;
1124         else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&
1125                  ch->s_info.rank == I915_DRAM_RANK_SINGLE)
1126                 ch->rank = I915_DRAM_RANK_DUAL;
1127         else
1128                 ch->rank = I915_DRAM_RANK_SINGLE;
1129
1130         ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
1131                                             ch->l_info.width) ||
1132                            skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
1133                                             ch->s_info.width);
1134
1135         DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
1136                       ch->l_info.size, ch->l_info.width,
1137                       ch->l_info.rank ? "dual" : "single",
1138                       ch->s_info.size, ch->s_info.width,
1139                       ch->s_info.rank ? "dual" : "single");
1140
1141         return 0;
1142 }
1143
1144 static bool
1145 intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
1146                         struct dram_channel_info *ch0)
1147 {
1148         return (val_ch0 == val_ch1 &&
1149                 (ch0->s_info.size == 0 ||
1150                  (ch0->l_info.size == ch0->s_info.size &&
1151                   ch0->l_info.width == ch0->s_info.width &&
1152                   ch0->l_info.rank == ch0->s_info.rank)));
1153 }
1154
1155 static int
1156 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1157 {
1158         struct dram_info *dram_info = &dev_priv->dram_info;
1159         struct dram_channel_info ch0, ch1;
1160         u32 val_ch0, val_ch1;
1161         int ret;
1162
1163         val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1164         ret = skl_dram_get_channel_info(&ch0, val_ch0);
1165         if (ret == 0)
1166                 dram_info->num_channels++;
1167
1168         val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1169         ret = skl_dram_get_channel_info(&ch1, val_ch1);
1170         if (ret == 0)
1171                 dram_info->num_channels++;
1172
1173         if (dram_info->num_channels == 0) {
1174                 DRM_INFO("Number of memory channels is zero\n");
1175                 return -EINVAL;
1176         }
1177
1178         /*
1179          * If any of the channel is single rank channel, worst case output
1180          * will be same as if single rank memory, so consider single rank
1181          * memory.
1182          */
1183         if (ch0.rank == I915_DRAM_RANK_SINGLE ||
1184             ch1.rank == I915_DRAM_RANK_SINGLE)
1185                 dram_info->rank = I915_DRAM_RANK_SINGLE;
1186         else
1187                 dram_info->rank = max(ch0.rank, ch1.rank);
1188
1189         if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1190                 DRM_INFO("couldn't get memory rank information\n");
1191                 return -EINVAL;
1192         }
1193
1194         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1195
1196         dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
1197                                                                        val_ch1,
1198                                                                        &ch0);
1199
1200         DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
1201                       dev_priv->dram_info.symmetric_memory ? "" : "not ");
1202         return 0;
1203 }
1204
1205 static int
1206 skl_get_dram_info(struct drm_i915_private *dev_priv)
1207 {
1208         struct dram_info *dram_info = &dev_priv->dram_info;
1209         u32 mem_freq_khz, val;
1210         int ret;
1211
1212         ret = skl_dram_get_channels_info(dev_priv);
1213         if (ret)
1214                 return ret;
1215
1216         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1217         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1218                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1219
1220         dram_info->bandwidth_kbps = dram_info->num_channels *
1221                                                         mem_freq_khz * 8;
1222
1223         if (dram_info->bandwidth_kbps == 0) {
1224                 DRM_INFO("Couldn't get system memory bandwidth\n");
1225                 return -EINVAL;
1226         }
1227
1228         dram_info->valid = true;
1229         return 0;
1230 }
1231
1232 static int
1233 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1234 {
1235         struct dram_info *dram_info = &dev_priv->dram_info;
1236         u32 dram_channels;
1237         u32 mem_freq_khz, val;
1238         u8 num_active_channels;
1239         int i;
1240
1241         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1242         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1243                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1244
1245         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1246         num_active_channels = hweight32(dram_channels);
1247
1248         /* Each active bit represents 4-byte channel */
1249         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1250
1251         if (dram_info->bandwidth_kbps == 0) {
1252                 DRM_INFO("Couldn't get system memory bandwidth\n");
1253                 return -EINVAL;
1254         }
1255
1256         /*
1257          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1258          */
1259         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1260                 u8 size, width;
1261                 enum dram_rank rank;
1262                 u32 tmp;
1263
1264                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1265                 if (val == 0xFFFFFFFF)
1266                         continue;
1267
1268                 dram_info->num_channels++;
1269                 tmp = val & BXT_DRAM_RANK_MASK;
1270
1271                 if (tmp == BXT_DRAM_RANK_SINGLE)
1272                         rank = I915_DRAM_RANK_SINGLE;
1273                 else if (tmp == BXT_DRAM_RANK_DUAL)
1274                         rank = I915_DRAM_RANK_DUAL;
1275                 else
1276                         rank = I915_DRAM_RANK_INVALID;
1277
1278                 tmp = val & BXT_DRAM_SIZE_MASK;
1279                 if (tmp == BXT_DRAM_SIZE_4GB)
1280                         size = 4;
1281                 else if (tmp == BXT_DRAM_SIZE_6GB)
1282                         size = 6;
1283                 else if (tmp == BXT_DRAM_SIZE_8GB)
1284                         size = 8;
1285                 else if (tmp == BXT_DRAM_SIZE_12GB)
1286                         size = 12;
1287                 else if (tmp == BXT_DRAM_SIZE_16GB)
1288                         size = 16;
1289                 else
1290                         size = 0;
1291
1292                 tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1293                 width = (1 << tmp) * 8;
1294                 DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,
1295                               width, rank == I915_DRAM_RANK_SINGLE ? "single" :
1296                               rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");
1297
1298                 /*
1299                  * If any of the channel is single rank channel,
1300                  * worst case output will be same as if single rank
1301                  * memory, so consider single rank memory.
1302                  */
1303                 if (dram_info->rank == I915_DRAM_RANK_INVALID)
1304                         dram_info->rank = rank;
1305                 else if (rank == I915_DRAM_RANK_SINGLE)
1306                         dram_info->rank = I915_DRAM_RANK_SINGLE;
1307         }
1308
1309         if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1310                 DRM_INFO("couldn't get memory rank information\n");
1311                 return -EINVAL;
1312         }
1313
1314         dram_info->valid = true;
1315         return 0;
1316 }
1317
1318 static void
1319 intel_get_dram_info(struct drm_i915_private *dev_priv)
1320 {
1321         struct dram_info *dram_info = &dev_priv->dram_info;
1322         char bandwidth_str[32];
1323         int ret;
1324
1325         dram_info->valid = false;
1326         dram_info->rank = I915_DRAM_RANK_INVALID;
1327         dram_info->bandwidth_kbps = 0;
1328         dram_info->num_channels = 0;
1329
1330         /*
1331          * Assume 16Gb DIMMs are present until proven otherwise.
1332          * This is only used for the level 0 watermark latency
1333          * w/a which does not apply to bxt/glk.
1334          */
1335         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1336
1337         if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
1338                 return;
1339
1340         /* Need to calculate bandwidth only for Gen9 */
1341         if (IS_BROXTON(dev_priv))
1342                 ret = bxt_get_dram_info(dev_priv);
1343         else if (IS_GEN9(dev_priv))
1344                 ret = skl_get_dram_info(dev_priv);
1345         else
1346                 ret = skl_dram_get_channels_info(dev_priv);
1347         if (ret)
1348                 return;
1349
1350         if (dram_info->bandwidth_kbps)
1351                 sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);
1352         else
1353                 sprintf(bandwidth_str, "unknown");
1354         DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
1355                       bandwidth_str, dram_info->num_channels);
1356         DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
1357                       (dram_info->rank == I915_DRAM_RANK_DUAL) ?
1358                       "dual" : "single", yesno(dram_info->is_16gb_dimm));
1359 }
1360
1361 /**
1362  * i915_driver_init_hw - setup state requiring device access
1363  * @dev_priv: device private
1364  *
1365  * Setup state that requires accessing the device, but doesn't require
1366  * exposing the driver via kernel internal or userspace interfaces.
1367  */
1368 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1369 {
1370         struct pci_dev *pdev = dev_priv->drm.pdev;
1371         int ret;
1372
1373         if (i915_inject_load_failure())
1374                 return -ENODEV;
1375
1376         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1377
1378         if (HAS_PPGTT(dev_priv)) {
1379                 if (intel_vgpu_active(dev_priv) &&
1380                     !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
1381                         i915_report_error(dev_priv,
1382                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1383                         return -ENXIO;
1384                 }
1385         }
1386
1387         intel_sanitize_options(dev_priv);
1388
1389         i915_perf_init(dev_priv);
1390
1391         ret = i915_ggtt_probe_hw(dev_priv);
1392         if (ret)
1393                 goto err_perf;
1394
1395         /*
1396          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1397          * otherwise the vga fbdev driver falls over.
1398          */
1399         ret = i915_kick_out_firmware_fb(dev_priv);
1400         if (ret) {
1401                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1402                 goto err_ggtt;
1403         }
1404
1405         ret = i915_kick_out_vgacon(dev_priv);
1406         if (ret) {
1407                 DRM_ERROR("failed to remove conflicting VGA console\n");
1408                 goto err_ggtt;
1409         }
1410
1411         ret = i915_ggtt_init_hw(dev_priv);
1412         if (ret)
1413                 goto err_ggtt;
1414
1415         ret = i915_ggtt_enable_hw(dev_priv);
1416         if (ret) {
1417                 DRM_ERROR("failed to enable GGTT\n");
1418                 goto err_ggtt;
1419         }
1420
1421         pci_set_master(pdev);
1422
1423         /* overlay on gen2 is broken and can't address above 1G */
1424         if (IS_GEN2(dev_priv)) {
1425                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1426                 if (ret) {
1427                         DRM_ERROR("failed to set DMA mask\n");
1428
1429                         goto err_ggtt;
1430                 }
1431         }
1432
1433         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1434          * using 32bit addressing, overwriting memory if HWS is located
1435          * above 4GB.
1436          *
1437          * The documentation also mentions an issue with undefined
1438          * behaviour if any general state is accessed within a page above 4GB,
1439          * which also needs to be handled carefully.
1440          */
1441         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1442                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1443
1444                 if (ret) {
1445                         DRM_ERROR("failed to set DMA mask\n");
1446
1447                         goto err_ggtt;
1448                 }
1449         }
1450
1451         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1452                            PM_QOS_DEFAULT_VALUE);
1453
1454         intel_uncore_sanitize(dev_priv);
1455
1456         i915_gem_load_init_fences(dev_priv);
1457
1458         /* On the 945G/GM, the chipset reports the MSI capability on the
1459          * integrated graphics even though the support isn't actually there
1460          * according to the published specs.  It doesn't appear to function
1461          * correctly in testing on 945G.
1462          * This may be a side effect of MSI having been made available for PEG
1463          * and the registers being closely associated.
1464          *
1465          * According to chipset errata, on the 965GM, MSI interrupts may
1466          * be lost or delayed, and was defeatured. MSI interrupts seem to
1467          * get lost on g4x as well, and interrupt delivery seems to stay
1468          * properly dead afterwards. So we'll just disable them for all
1469          * pre-gen5 chipsets.
1470          *
1471          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1472          * interrupts even when in MSI mode. This results in spurious
1473          * interrupt warnings if the legacy irq no. is shared with another
1474          * device. The kernel then disables that interrupt source and so
1475          * prevents the other device from working properly.
1476          */
1477         if (INTEL_GEN(dev_priv) >= 5) {
1478                 if (pci_enable_msi(pdev) < 0)
1479                         DRM_DEBUG_DRIVER("can't enable MSI");
1480         }
1481
1482         ret = intel_gvt_init(dev_priv);
1483         if (ret)
1484                 goto err_msi;
1485
1486         intel_opregion_setup(dev_priv);
1487         /*
1488          * Fill the dram structure to get the system raw bandwidth and
1489          * dram info. This will be used for memory latency calculation.
1490          */
1491         intel_get_dram_info(dev_priv);
1492
1493
1494         return 0;
1495
1496 err_msi:
1497         if (pdev->msi_enabled)
1498                 pci_disable_msi(pdev);
1499         pm_qos_remove_request(&dev_priv->pm_qos);
1500 err_ggtt:
1501         i915_ggtt_cleanup_hw(dev_priv);
1502 err_perf:
1503         i915_perf_fini(dev_priv);
1504         return ret;
1505 }
1506
1507 /**
1508  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1509  * @dev_priv: device private
1510  */
1511 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1512 {
1513         struct pci_dev *pdev = dev_priv->drm.pdev;
1514
1515         i915_perf_fini(dev_priv);
1516
1517         if (pdev->msi_enabled)
1518                 pci_disable_msi(pdev);
1519
1520         pm_qos_remove_request(&dev_priv->pm_qos);
1521         i915_ggtt_cleanup_hw(dev_priv);
1522 }
1523
1524 /**
1525  * i915_driver_register - register the driver with the rest of the system
1526  * @dev_priv: device private
1527  *
1528  * Perform any steps necessary to make the driver available via kernel
1529  * internal or userspace interfaces.
1530  */
1531 static void i915_driver_register(struct drm_i915_private *dev_priv)
1532 {
1533         struct drm_device *dev = &dev_priv->drm;
1534
1535         i915_gem_shrinker_register(dev_priv);
1536         i915_pmu_register(dev_priv);
1537
1538         /*
1539          * Notify a valid surface after modesetting,
1540          * when running inside a VM.
1541          */
1542         if (intel_vgpu_active(dev_priv))
1543                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1544
1545         /* Reveal our presence to userspace */
1546         if (drm_dev_register(dev, 0) == 0) {
1547                 i915_debugfs_register(dev_priv);
1548                 i915_setup_sysfs(dev_priv);
1549
1550                 /* Depends on sysfs having been initialized */
1551                 i915_perf_register(dev_priv);
1552         } else
1553                 DRM_ERROR("Failed to register driver for userspace access!\n");
1554
1555         if (INTEL_INFO(dev_priv)->num_pipes) {
1556                 /* Must be done after probing outputs */
1557                 intel_opregion_register(dev_priv);
1558                 acpi_video_register();
1559         }
1560
1561         if (IS_GEN5(dev_priv))
1562                 intel_gpu_ips_init(dev_priv);
1563
1564         intel_audio_init(dev_priv);
1565
1566         /*
1567          * Some ports require correctly set-up hpd registers for detection to
1568          * work properly (leading to ghost connected connector status), e.g. VGA
1569          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1570          * irqs are fully enabled. We do it last so that the async config
1571          * cannot run before the connectors are registered.
1572          */
1573         intel_fbdev_initial_config_async(dev);
1574
1575         /*
1576          * We need to coordinate the hotplugs with the asynchronous fbdev
1577          * configuration, for which we use the fbdev->async_cookie.
1578          */
1579         if (INTEL_INFO(dev_priv)->num_pipes)
1580                 drm_kms_helper_poll_init(dev);
1581
1582         intel_power_domains_enable(dev_priv);
1583         intel_runtime_pm_enable(dev_priv);
1584 }
1585
1586 /**
1587  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1588  * @dev_priv: device private
1589  */
1590 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1591 {
1592         intel_runtime_pm_disable(dev_priv);
1593         intel_power_domains_disable(dev_priv);
1594
1595         intel_fbdev_unregister(dev_priv);
1596         intel_audio_deinit(dev_priv);
1597
1598         /*
1599          * After flushing the fbdev (incl. a late async config which will
1600          * have delayed queuing of a hotplug event), then flush the hotplug
1601          * events.
1602          */
1603         drm_kms_helper_poll_fini(&dev_priv->drm);
1604
1605         intel_gpu_ips_teardown();
1606         acpi_video_unregister();
1607         intel_opregion_unregister(dev_priv);
1608
1609         i915_perf_unregister(dev_priv);
1610         i915_pmu_unregister(dev_priv);
1611
1612         i915_teardown_sysfs(dev_priv);
1613         drm_dev_unregister(&dev_priv->drm);
1614
1615         i915_gem_shrinker_unregister(dev_priv);
1616 }
1617
1618 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1619 {
1620         if (drm_debug & DRM_UT_DRIVER) {
1621                 struct drm_printer p = drm_debug_printer("i915 device info:");
1622
1623                 intel_device_info_dump(&dev_priv->info, &p);
1624                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1625         }
1626
1627         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1628                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1629         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1630                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1631         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1632                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1633 }
1634
1635 static struct drm_i915_private *
1636 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1637 {
1638         const struct intel_device_info *match_info =
1639                 (struct intel_device_info *)ent->driver_data;
1640         struct intel_device_info *device_info;
1641         struct drm_i915_private *i915;
1642         int err;
1643
1644         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1645         if (!i915)
1646                 return ERR_PTR(-ENOMEM);
1647
1648         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1649         if (err) {
1650                 kfree(i915);
1651                 return ERR_PTR(err);
1652         }
1653
1654         i915->drm.pdev = pdev;
1655         i915->drm.dev_private = i915;
1656         pci_set_drvdata(pdev, &i915->drm);
1657
1658         /* Setup the write-once "constant" device info */
1659         device_info = mkwrite_device_info(i915);
1660         memcpy(device_info, match_info, sizeof(*device_info));
1661         device_info->device_id = pdev->device;
1662
1663         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1664                      BITS_PER_TYPE(device_info->platform_mask));
1665         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1666
1667         return i915;
1668 }
1669
1670 static void i915_driver_destroy(struct drm_i915_private *i915)
1671 {
1672         struct pci_dev *pdev = i915->drm.pdev;
1673
1674         drm_dev_fini(&i915->drm);
1675         kfree(i915);
1676
1677         /* And make sure we never chase our dangling pointer from pci_dev */
1678         pci_set_drvdata(pdev, NULL);
1679 }
1680
1681 /**
1682  * i915_driver_load - setup chip and create an initial config
1683  * @pdev: PCI device
1684  * @ent: matching PCI ID entry
1685  *
1686  * The driver load routine has to do several things:
1687  *   - drive output discovery via intel_modeset_init()
1688  *   - initialize the memory manager
1689  *   - allocate initial config memory
1690  *   - setup the DRM framebuffer with the allocated memory
1691  */
1692 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1693 {
1694         const struct intel_device_info *match_info =
1695                 (struct intel_device_info *)ent->driver_data;
1696         struct drm_i915_private *dev_priv;
1697         int ret;
1698
1699         dev_priv = i915_driver_create(pdev, ent);
1700         if (IS_ERR(dev_priv))
1701                 return PTR_ERR(dev_priv);
1702
1703         /* Disable nuclear pageflip by default on pre-ILK */
1704         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1705                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1706
1707         ret = pci_enable_device(pdev);
1708         if (ret)
1709                 goto out_fini;
1710
1711         ret = i915_driver_init_early(dev_priv);
1712         if (ret < 0)
1713                 goto out_pci_disable;
1714
1715         disable_rpm_wakeref_asserts(dev_priv);
1716
1717         ret = i915_driver_init_mmio(dev_priv);
1718         if (ret < 0)
1719                 goto out_runtime_pm_put;
1720
1721         ret = i915_driver_init_hw(dev_priv);
1722         if (ret < 0)
1723                 goto out_cleanup_mmio;
1724
1725         ret = i915_load_modeset_init(&dev_priv->drm);
1726         if (ret < 0)
1727                 goto out_cleanup_hw;
1728
1729         i915_driver_register(dev_priv);
1730
1731         enable_rpm_wakeref_asserts(dev_priv);
1732
1733         i915_welcome_messages(dev_priv);
1734
1735         return 0;
1736
1737 out_cleanup_hw:
1738         i915_driver_cleanup_hw(dev_priv);
1739 out_cleanup_mmio:
1740         i915_driver_cleanup_mmio(dev_priv);
1741 out_runtime_pm_put:
1742         enable_rpm_wakeref_asserts(dev_priv);
1743         i915_driver_cleanup_early(dev_priv);
1744 out_pci_disable:
1745         pci_disable_device(pdev);
1746 out_fini:
1747         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1748         i915_driver_destroy(dev_priv);
1749         return ret;
1750 }
1751
1752 void i915_driver_unload(struct drm_device *dev)
1753 {
1754         struct drm_i915_private *dev_priv = to_i915(dev);
1755         struct pci_dev *pdev = dev_priv->drm.pdev;
1756
1757         disable_rpm_wakeref_asserts(dev_priv);
1758
1759         i915_driver_unregister(dev_priv);
1760
1761         if (i915_gem_suspend(dev_priv))
1762                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1763
1764         drm_atomic_helper_shutdown(dev);
1765
1766         intel_gvt_cleanup(dev_priv);
1767
1768         intel_modeset_cleanup(dev);
1769
1770         intel_bios_cleanup(dev_priv);
1771
1772         vga_switcheroo_unregister_client(pdev);
1773         vga_client_register(pdev, NULL, NULL, NULL);
1774
1775         intel_csr_ucode_fini(dev_priv);
1776
1777         /* Free error state after interrupts are fully disabled. */
1778         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1779         i915_reset_error_state(dev_priv);
1780
1781         i915_gem_fini(dev_priv);
1782
1783         intel_power_domains_fini_hw(dev_priv);
1784
1785         i915_driver_cleanup_hw(dev_priv);
1786         i915_driver_cleanup_mmio(dev_priv);
1787
1788         enable_rpm_wakeref_asserts(dev_priv);
1789
1790         WARN_ON(atomic_read(&dev_priv->runtime_pm.wakeref_count));
1791 }
1792
1793 static void i915_driver_release(struct drm_device *dev)
1794 {
1795         struct drm_i915_private *dev_priv = to_i915(dev);
1796
1797         i915_driver_cleanup_early(dev_priv);
1798         i915_driver_destroy(dev_priv);
1799 }
1800
1801 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1802 {
1803         struct drm_i915_private *i915 = to_i915(dev);
1804         int ret;
1805
1806         ret = i915_gem_open(i915, file);
1807         if (ret)
1808                 return ret;
1809
1810         return 0;
1811 }
1812
1813 /**
1814  * i915_driver_lastclose - clean up after all DRM clients have exited
1815  * @dev: DRM device
1816  *
1817  * Take care of cleaning up after all DRM clients have exited.  In the
1818  * mode setting case, we want to restore the kernel's initial mode (just
1819  * in case the last client left us in a bad state).
1820  *
1821  * Additionally, in the non-mode setting case, we'll tear down the GTT
1822  * and DMA structures, since the kernel won't be using them, and clea
1823  * up any GEM state.
1824  */
1825 static void i915_driver_lastclose(struct drm_device *dev)
1826 {
1827         intel_fbdev_restore_mode(dev);
1828         vga_switcheroo_process_delayed_switch();
1829 }
1830
1831 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1832 {
1833         struct drm_i915_file_private *file_priv = file->driver_priv;
1834
1835         mutex_lock(&dev->struct_mutex);
1836         i915_gem_context_close(file);
1837         i915_gem_release(dev, file);
1838         mutex_unlock(&dev->struct_mutex);
1839
1840         kfree(file_priv);
1841 }
1842
1843 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1844 {
1845         struct drm_device *dev = &dev_priv->drm;
1846         struct intel_encoder *encoder;
1847
1848         drm_modeset_lock_all(dev);
1849         for_each_intel_encoder(dev, encoder)
1850                 if (encoder->suspend)
1851                         encoder->suspend(encoder);
1852         drm_modeset_unlock_all(dev);
1853 }
1854
1855 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1856                               bool rpm_resume);
1857 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1858
1859 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1860 {
1861 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1862         if (acpi_target_system_state() < ACPI_STATE_S3)
1863                 return true;
1864 #endif
1865         return false;
1866 }
1867
1868 static int i915_drm_prepare(struct drm_device *dev)
1869 {
1870         struct drm_i915_private *i915 = to_i915(dev);
1871         int err;
1872
1873         /*
1874          * NB intel_display_suspend() may issue new requests after we've
1875          * ostensibly marked the GPU as ready-to-sleep here. We need to
1876          * split out that work and pull it forward so that after point,
1877          * the GPU is not woken again.
1878          */
1879         err = i915_gem_suspend(i915);
1880         if (err)
1881                 dev_err(&i915->drm.pdev->dev,
1882                         "GEM idle failed, suspend/resume might fail\n");
1883
1884         return err;
1885 }
1886
1887 static int i915_drm_suspend(struct drm_device *dev)
1888 {
1889         struct drm_i915_private *dev_priv = to_i915(dev);
1890         struct pci_dev *pdev = dev_priv->drm.pdev;
1891         pci_power_t opregion_target_state;
1892
1893         disable_rpm_wakeref_asserts(dev_priv);
1894
1895         /* We do a lot of poking in a lot of registers, make sure they work
1896          * properly. */
1897         intel_power_domains_disable(dev_priv);
1898
1899         drm_kms_helper_poll_disable(dev);
1900
1901         pci_save_state(pdev);
1902
1903         intel_display_suspend(dev);
1904
1905         intel_dp_mst_suspend(dev_priv);
1906
1907         intel_runtime_pm_disable_interrupts(dev_priv);
1908         intel_hpd_cancel_work(dev_priv);
1909
1910         intel_suspend_encoders(dev_priv);
1911
1912         intel_suspend_hw(dev_priv);
1913
1914         i915_gem_suspend_gtt_mappings(dev_priv);
1915
1916         i915_save_state(dev_priv);
1917
1918         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1919         intel_opregion_suspend(dev_priv, opregion_target_state);
1920
1921         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1922
1923         dev_priv->suspend_count++;
1924
1925         intel_csr_ucode_suspend(dev_priv);
1926
1927         enable_rpm_wakeref_asserts(dev_priv);
1928
1929         return 0;
1930 }
1931
1932 static enum i915_drm_suspend_mode
1933 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1934 {
1935         if (hibernate)
1936                 return I915_DRM_SUSPEND_HIBERNATE;
1937
1938         if (suspend_to_idle(dev_priv))
1939                 return I915_DRM_SUSPEND_IDLE;
1940
1941         return I915_DRM_SUSPEND_MEM;
1942 }
1943
1944 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1945 {
1946         struct drm_i915_private *dev_priv = to_i915(dev);
1947         struct pci_dev *pdev = dev_priv->drm.pdev;
1948         int ret;
1949
1950         disable_rpm_wakeref_asserts(dev_priv);
1951
1952         i915_gem_suspend_late(dev_priv);
1953
1954         intel_uncore_suspend(dev_priv);
1955
1956         intel_power_domains_suspend(dev_priv,
1957                                     get_suspend_mode(dev_priv, hibernation));
1958
1959         ret = 0;
1960         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
1961                 bxt_enable_dc9(dev_priv);
1962         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1963                 hsw_enable_pc8(dev_priv);
1964         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1965                 ret = vlv_suspend_complete(dev_priv);
1966
1967         if (ret) {
1968                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1969                 intel_power_domains_resume(dev_priv);
1970
1971                 goto out;
1972         }
1973
1974         pci_disable_device(pdev);
1975         /*
1976          * During hibernation on some platforms the BIOS may try to access
1977          * the device even though it's already in D3 and hang the machine. So
1978          * leave the device in D0 on those platforms and hope the BIOS will
1979          * power down the device properly. The issue was seen on multiple old
1980          * GENs with different BIOS vendors, so having an explicit blacklist
1981          * is inpractical; apply the workaround on everything pre GEN6. The
1982          * platforms where the issue was seen:
1983          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1984          * Fujitsu FSC S7110
1985          * Acer Aspire 1830T
1986          */
1987         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1988                 pci_set_power_state(pdev, PCI_D3hot);
1989
1990 out:
1991         enable_rpm_wakeref_asserts(dev_priv);
1992
1993         return ret;
1994 }
1995
1996 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1997 {
1998         int error;
1999
2000         if (!dev) {
2001                 DRM_ERROR("dev: %p\n", dev);
2002                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2003                 return -ENODEV;
2004         }
2005
2006         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2007                          state.event != PM_EVENT_FREEZE))
2008                 return -EINVAL;
2009
2010         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2011                 return 0;
2012
2013         error = i915_drm_suspend(dev);
2014         if (error)
2015                 return error;
2016
2017         return i915_drm_suspend_late(dev, false);
2018 }
2019
2020 static int i915_drm_resume(struct drm_device *dev)
2021 {
2022         struct drm_i915_private *dev_priv = to_i915(dev);
2023         int ret;
2024
2025         disable_rpm_wakeref_asserts(dev_priv);
2026         intel_sanitize_gt_powersave(dev_priv);
2027
2028         i915_gem_sanitize(dev_priv);
2029
2030         ret = i915_ggtt_enable_hw(dev_priv);
2031         if (ret)
2032                 DRM_ERROR("failed to re-enable GGTT\n");
2033
2034         intel_csr_ucode_resume(dev_priv);
2035
2036         i915_restore_state(dev_priv);
2037         intel_pps_unlock_regs_wa(dev_priv);
2038
2039         intel_init_pch_refclk(dev_priv);
2040
2041         /*
2042          * Interrupts have to be enabled before any batches are run. If not the
2043          * GPU will hang. i915_gem_init_hw() will initiate batches to
2044          * update/restore the context.
2045          *
2046          * drm_mode_config_reset() needs AUX interrupts.
2047          *
2048          * Modeset enabling in intel_modeset_init_hw() also needs working
2049          * interrupts.
2050          */
2051         intel_runtime_pm_enable_interrupts(dev_priv);
2052
2053         drm_mode_config_reset(dev);
2054
2055         i915_gem_resume(dev_priv);
2056
2057         intel_modeset_init_hw(dev);
2058         intel_init_clock_gating(dev_priv);
2059
2060         spin_lock_irq(&dev_priv->irq_lock);
2061         if (dev_priv->display.hpd_irq_setup)
2062                 dev_priv->display.hpd_irq_setup(dev_priv);
2063         spin_unlock_irq(&dev_priv->irq_lock);
2064
2065         intel_dp_mst_resume(dev_priv);
2066
2067         intel_display_resume(dev);
2068
2069         drm_kms_helper_poll_enable(dev);
2070
2071         /*
2072          * ... but also need to make sure that hotplug processing
2073          * doesn't cause havoc. Like in the driver load code we don't
2074          * bother with the tiny race here where we might lose hotplug
2075          * notifications.
2076          * */
2077         intel_hpd_init(dev_priv);
2078
2079         intel_opregion_resume(dev_priv);
2080
2081         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2082
2083         intel_power_domains_enable(dev_priv);
2084
2085         enable_rpm_wakeref_asserts(dev_priv);
2086
2087         return 0;
2088 }
2089
2090 static int i915_drm_resume_early(struct drm_device *dev)
2091 {
2092         struct drm_i915_private *dev_priv = to_i915(dev);
2093         struct pci_dev *pdev = dev_priv->drm.pdev;
2094         int ret;
2095
2096         /*
2097          * We have a resume ordering issue with the snd-hda driver also
2098          * requiring our device to be power up. Due to the lack of a
2099          * parent/child relationship we currently solve this with an early
2100          * resume hook.
2101          *
2102          * FIXME: This should be solved with a special hdmi sink device or
2103          * similar so that power domains can be employed.
2104          */
2105
2106         /*
2107          * Note that we need to set the power state explicitly, since we
2108          * powered off the device during freeze and the PCI core won't power
2109          * it back up for us during thaw. Powering off the device during
2110          * freeze is not a hard requirement though, and during the
2111          * suspend/resume phases the PCI core makes sure we get here with the
2112          * device powered on. So in case we change our freeze logic and keep
2113          * the device powered we can also remove the following set power state
2114          * call.
2115          */
2116         ret = pci_set_power_state(pdev, PCI_D0);
2117         if (ret) {
2118                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2119                 return ret;
2120         }
2121
2122         /*
2123          * Note that pci_enable_device() first enables any parent bridge
2124          * device and only then sets the power state for this device. The
2125          * bridge enabling is a nop though, since bridge devices are resumed
2126          * first. The order of enabling power and enabling the device is
2127          * imposed by the PCI core as described above, so here we preserve the
2128          * same order for the freeze/thaw phases.
2129          *
2130          * TODO: eventually we should remove pci_disable_device() /
2131          * pci_enable_enable_device() from suspend/resume. Due to how they
2132          * depend on the device enable refcount we can't anyway depend on them
2133          * disabling/enabling the device.
2134          */
2135         if (pci_enable_device(pdev))
2136                 return -EIO;
2137
2138         pci_set_master(pdev);
2139
2140         disable_rpm_wakeref_asserts(dev_priv);
2141
2142         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2143                 ret = vlv_resume_prepare(dev_priv, false);
2144         if (ret)
2145                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2146                           ret);
2147
2148         intel_uncore_resume_early(dev_priv);
2149
2150         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2151                 gen9_sanitize_dc_state(dev_priv);
2152                 bxt_disable_dc9(dev_priv);
2153         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2154                 hsw_disable_pc8(dev_priv);
2155         }
2156
2157         intel_uncore_sanitize(dev_priv);
2158
2159         intel_power_domains_resume(dev_priv);
2160
2161         intel_engines_sanitize(dev_priv);
2162
2163         enable_rpm_wakeref_asserts(dev_priv);
2164
2165         return ret;
2166 }
2167
2168 static int i915_resume_switcheroo(struct drm_device *dev)
2169 {
2170         int ret;
2171
2172         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2173                 return 0;
2174
2175         ret = i915_drm_resume_early(dev);
2176         if (ret)
2177                 return ret;
2178
2179         return i915_drm_resume(dev);
2180 }
2181
2182 /**
2183  * i915_reset - reset chip after a hang
2184  * @i915: #drm_i915_private to reset
2185  * @stalled_mask: mask of the stalled engines with the guilty requests
2186  * @reason: user error message for why we are resetting
2187  *
2188  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
2189  * on failure.
2190  *
2191  * Caller must hold the struct_mutex.
2192  *
2193  * Procedure is fairly simple:
2194  *   - reset the chip using the reset reg
2195  *   - re-init context state
2196  *   - re-init hardware status page
2197  *   - re-init ring buffer
2198  *   - re-init interrupt state
2199  *   - re-init display
2200  */
2201 void i915_reset(struct drm_i915_private *i915,
2202                 unsigned int stalled_mask,
2203                 const char *reason)
2204 {
2205         struct i915_gpu_error *error = &i915->gpu_error;
2206         int ret;
2207         int i;
2208
2209         GEM_TRACE("flags=%lx\n", error->flags);
2210
2211         might_sleep();
2212         lockdep_assert_held(&i915->drm.struct_mutex);
2213         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
2214
2215         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
2216                 return;
2217
2218         /* Clear any previous failed attempts at recovery. Time to try again. */
2219         if (!i915_gem_unset_wedged(i915))
2220                 goto wakeup;
2221
2222         if (reason)
2223                 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
2224         error->reset_count++;
2225
2226         ret = i915_gem_reset_prepare(i915);
2227         if (ret) {
2228                 dev_err(i915->drm.dev, "GPU recovery failed\n");
2229                 goto taint;
2230         }
2231
2232         if (!intel_has_gpu_reset(i915)) {
2233                 if (i915_modparams.reset)
2234                         dev_err(i915->drm.dev, "GPU reset not supported\n");
2235                 else
2236                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
2237                 goto error;
2238         }
2239
2240         for (i = 0; i < 3; i++) {
2241                 ret = intel_gpu_reset(i915, ALL_ENGINES);
2242                 if (ret == 0)
2243                         break;
2244
2245                 msleep(100);
2246         }
2247         if (ret) {
2248                 dev_err(i915->drm.dev, "Failed to reset chip\n");
2249                 goto taint;
2250         }
2251
2252         /* Ok, now get things going again... */
2253
2254         /*
2255          * Everything depends on having the GTT running, so we need to start
2256          * there.
2257          */
2258         ret = i915_ggtt_enable_hw(i915);
2259         if (ret) {
2260                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
2261                           ret);
2262                 goto error;
2263         }
2264
2265         i915_gem_reset(i915, stalled_mask);
2266         intel_overlay_reset(i915);
2267
2268         /*
2269          * Next we need to restore the context, but we don't use those
2270          * yet either...
2271          *
2272          * Ring buffer needs to be re-initialized in the KMS case, or if X
2273          * was running at the time of the reset (i.e. we weren't VT
2274          * switched away).
2275          */
2276         ret = i915_gem_init_hw(i915);
2277         if (ret) {
2278                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
2279                           ret);
2280                 goto error;
2281         }
2282
2283         i915_queue_hangcheck(i915);
2284
2285 finish:
2286         i915_gem_reset_finish(i915);
2287 wakeup:
2288         clear_bit(I915_RESET_HANDOFF, &error->flags);
2289         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
2290         return;
2291
2292 taint:
2293         /*
2294          * History tells us that if we cannot reset the GPU now, we
2295          * never will. This then impacts everything that is run
2296          * subsequently. On failing the reset, we mark the driver
2297          * as wedged, preventing further execution on the GPU.
2298          * We also want to go one step further and add a taint to the
2299          * kernel so that any subsequent faults can be traced back to
2300          * this failure. This is important for CI, where if the
2301          * GPU/driver fails we would like to reboot and restart testing
2302          * rather than continue on into oblivion. For everyone else,
2303          * the system should still plod along, but they have been warned!
2304          */
2305         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
2306 error:
2307         i915_gem_set_wedged(i915);
2308         i915_retire_requests(i915);
2309         goto finish;
2310 }
2311
2312 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2313                                         struct intel_engine_cs *engine)
2314 {
2315         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2316 }
2317
2318 /**
2319  * i915_reset_engine - reset GPU engine to recover from a hang
2320  * @engine: engine to reset
2321  * @msg: reason for GPU reset; or NULL for no dev_notice()
2322  *
2323  * Reset a specific GPU engine. Useful if a hang is detected.
2324  * Returns zero on successful reset or otherwise an error code.
2325  *
2326  * Procedure is:
2327  *  - identifies the request that caused the hang and it is dropped
2328  *  - reset engine (which will force the engine to idle)
2329  *  - re-init/configure engine
2330  */
2331 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2332 {
2333         struct i915_gpu_error *error = &engine->i915->gpu_error;
2334         struct i915_request *active_request;
2335         int ret;
2336
2337         GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2338         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2339
2340         active_request = i915_gem_reset_prepare_engine(engine);
2341         if (IS_ERR_OR_NULL(active_request)) {
2342                 /* Either the previous reset failed, or we pardon the reset. */
2343                 ret = PTR_ERR(active_request);
2344                 goto out;
2345         }
2346
2347         if (msg)
2348                 dev_notice(engine->i915->drm.dev,
2349                            "Resetting %s for %s\n", engine->name, msg);
2350         error->reset_engine_count[engine->id]++;
2351
2352         if (!engine->i915->guc.execbuf_client)
2353                 ret = intel_gt_reset_engine(engine->i915, engine);
2354         else
2355                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2356         if (ret) {
2357                 /* If we fail here, we expect to fallback to a global reset */
2358                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2359                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2360                                  engine->name, ret);
2361                 goto out;
2362         }
2363
2364         /*
2365          * The request that caused the hang is stuck on elsp, we know the
2366          * active request and can drop it, adjust head to skip the offending
2367          * request to resume executing remaining requests in the queue.
2368          */
2369         i915_gem_reset_engine(engine, active_request, true);
2370
2371         /*
2372          * The engine and its registers (and workarounds in case of render)
2373          * have been reset to their default values. Follow the init_ring
2374          * process to program RING_MODE, HWSP and re-enable submission.
2375          */
2376         ret = engine->init_hw(engine);
2377         if (ret)
2378                 goto out;
2379
2380 out:
2381         intel_engine_cancel_stop_cs(engine);
2382         i915_gem_reset_finish_engine(engine);
2383         return ret;
2384 }
2385
2386 static int i915_pm_prepare(struct device *kdev)
2387 {
2388         struct pci_dev *pdev = to_pci_dev(kdev);
2389         struct drm_device *dev = pci_get_drvdata(pdev);
2390
2391         if (!dev) {
2392                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2393                 return -ENODEV;
2394         }
2395
2396         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2397                 return 0;
2398
2399         return i915_drm_prepare(dev);
2400 }
2401
2402 static int i915_pm_suspend(struct device *kdev)
2403 {
2404         struct pci_dev *pdev = to_pci_dev(kdev);
2405         struct drm_device *dev = pci_get_drvdata(pdev);
2406
2407         if (!dev) {
2408                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2409                 return -ENODEV;
2410         }
2411
2412         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2413                 return 0;
2414
2415         return i915_drm_suspend(dev);
2416 }
2417
2418 static int i915_pm_suspend_late(struct device *kdev)
2419 {
2420         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2421
2422         /*
2423          * We have a suspend ordering issue with the snd-hda driver also
2424          * requiring our device to be power up. Due to the lack of a
2425          * parent/child relationship we currently solve this with an late
2426          * suspend hook.
2427          *
2428          * FIXME: This should be solved with a special hdmi sink device or
2429          * similar so that power domains can be employed.
2430          */
2431         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2432                 return 0;
2433
2434         return i915_drm_suspend_late(dev, false);
2435 }
2436
2437 static int i915_pm_poweroff_late(struct device *kdev)
2438 {
2439         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2440
2441         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2442                 return 0;
2443
2444         return i915_drm_suspend_late(dev, true);
2445 }
2446
2447 static int i915_pm_resume_early(struct device *kdev)
2448 {
2449         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2450
2451         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2452                 return 0;
2453
2454         return i915_drm_resume_early(dev);
2455 }
2456
2457 static int i915_pm_resume(struct device *kdev)
2458 {
2459         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2460
2461         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2462                 return 0;
2463
2464         return i915_drm_resume(dev);
2465 }
2466
2467 /* freeze: before creating the hibernation_image */
2468 static int i915_pm_freeze(struct device *kdev)
2469 {
2470         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2471         int ret;
2472
2473         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2474                 ret = i915_drm_suspend(dev);
2475                 if (ret)
2476                         return ret;
2477         }
2478
2479         ret = i915_gem_freeze(kdev_to_i915(kdev));
2480         if (ret)
2481                 return ret;
2482
2483         return 0;
2484 }
2485
2486 static int i915_pm_freeze_late(struct device *kdev)
2487 {
2488         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2489         int ret;
2490
2491         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2492                 ret = i915_drm_suspend_late(dev, true);
2493                 if (ret)
2494                         return ret;
2495         }
2496
2497         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2498         if (ret)
2499                 return ret;
2500
2501         return 0;
2502 }
2503
2504 /* thaw: called after creating the hibernation image, but before turning off. */
2505 static int i915_pm_thaw_early(struct device *kdev)
2506 {
2507         return i915_pm_resume_early(kdev);
2508 }
2509
2510 static int i915_pm_thaw(struct device *kdev)
2511 {
2512         return i915_pm_resume(kdev);
2513 }
2514
2515 /* restore: called after loading the hibernation image. */
2516 static int i915_pm_restore_early(struct device *kdev)
2517 {
2518         return i915_pm_resume_early(kdev);
2519 }
2520
2521 static int i915_pm_restore(struct device *kdev)
2522 {
2523         return i915_pm_resume(kdev);
2524 }
2525
2526 /*
2527  * Save all Gunit registers that may be lost after a D3 and a subsequent
2528  * S0i[R123] transition. The list of registers needing a save/restore is
2529  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2530  * registers in the following way:
2531  * - Driver: saved/restored by the driver
2532  * - Punit : saved/restored by the Punit firmware
2533  * - No, w/o marking: no need to save/restore, since the register is R/O or
2534  *                    used internally by the HW in a way that doesn't depend
2535  *                    keeping the content across a suspend/resume.
2536  * - Debug : used for debugging
2537  *
2538  * We save/restore all registers marked with 'Driver', with the following
2539  * exceptions:
2540  * - Registers out of use, including also registers marked with 'Debug'.
2541  *   These have no effect on the driver's operation, so we don't save/restore
2542  *   them to reduce the overhead.
2543  * - Registers that are fully setup by an initialization function called from
2544  *   the resume path. For example many clock gating and RPS/RC6 registers.
2545  * - Registers that provide the right functionality with their reset defaults.
2546  *
2547  * TODO: Except for registers that based on the above 3 criteria can be safely
2548  * ignored, we save/restore all others, practically treating the HW context as
2549  * a black-box for the driver. Further investigation is needed to reduce the
2550  * saved/restored registers even further, by following the same 3 criteria.
2551  */
2552 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2553 {
2554         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2555         int i;
2556
2557         /* GAM 0x4000-0x4770 */
2558         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2559         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2560         s->arb_mode             = I915_READ(ARB_MODE);
2561         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2562         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2563
2564         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2565                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2566
2567         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2568         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2569
2570         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2571         s->ecochk               = I915_READ(GAM_ECOCHK);
2572         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2573         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2574
2575         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2576
2577         /* MBC 0x9024-0x91D0, 0x8500 */
2578         s->g3dctl               = I915_READ(VLV_G3DCTL);
2579         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2580         s->mbctl                = I915_READ(GEN6_MBCTL);
2581
2582         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2583         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2584         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2585         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2586         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2587         s->rstctl               = I915_READ(GEN6_RSTCTL);
2588         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2589
2590         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2591         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2592         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2593         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2594         s->ecobus               = I915_READ(ECOBUS);
2595         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2596         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2597         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2598         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2599         s->rcedata              = I915_READ(VLV_RCEDATA);
2600         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2601
2602         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2603         s->gt_imr               = I915_READ(GTIMR);
2604         s->gt_ier               = I915_READ(GTIER);
2605         s->pm_imr               = I915_READ(GEN6_PMIMR);
2606         s->pm_ier               = I915_READ(GEN6_PMIER);
2607
2608         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2609                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2610
2611         /* GT SA CZ domain, 0x100000-0x138124 */
2612         s->tilectl              = I915_READ(TILECTL);
2613         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2614         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2615         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2616         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2617
2618         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2619         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2620         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2621         s->pcbr                 = I915_READ(VLV_PCBR);
2622         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2623
2624         /*
2625          * Not saving any of:
2626          * DFT,         0x9800-0x9EC0
2627          * SARB,        0xB000-0xB1FC
2628          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2629          * PCI CFG
2630          */
2631 }
2632
2633 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2634 {
2635         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2636         u32 val;
2637         int i;
2638
2639         /* GAM 0x4000-0x4770 */
2640         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2641         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2642         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2643         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2644         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2645
2646         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2647                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2648
2649         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2650         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2651
2652         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2653         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2654         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2655         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2656
2657         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2658
2659         /* MBC 0x9024-0x91D0, 0x8500 */
2660         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2661         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2662         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2663
2664         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2665         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2666         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2667         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2668         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2669         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2670         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2671
2672         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2673         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2674         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2675         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2676         I915_WRITE(ECOBUS,              s->ecobus);
2677         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2678         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2679         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2680         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2681         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2682         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2683
2684         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2685         I915_WRITE(GTIMR,               s->gt_imr);
2686         I915_WRITE(GTIER,               s->gt_ier);
2687         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2688         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2689
2690         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2691                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2692
2693         /* GT SA CZ domain, 0x100000-0x138124 */
2694         I915_WRITE(TILECTL,                     s->tilectl);
2695         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2696         /*
2697          * Preserve the GT allow wake and GFX force clock bit, they are not
2698          * be restored, as they are used to control the s0ix suspend/resume
2699          * sequence by the caller.
2700          */
2701         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2702         val &= VLV_GTLC_ALLOWWAKEREQ;
2703         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2704         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2705
2706         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2707         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2708         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2709         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2710
2711         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2712
2713         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2714         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2715         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2716         I915_WRITE(VLV_PCBR,                    s->pcbr);
2717         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2718 }
2719
2720 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2721                                   u32 mask, u32 val)
2722 {
2723         /* The HW does not like us polling for PW_STATUS frequently, so
2724          * use the sleeping loop rather than risk the busy spin within
2725          * intel_wait_for_register().
2726          *
2727          * Transitioning between RC6 states should be at most 2ms (see
2728          * valleyview_enable_rps) so use a 3ms timeout.
2729          */
2730         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2731                         3);
2732 }
2733
2734 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2735 {
2736         u32 val;
2737         int err;
2738
2739         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2740         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2741         if (force_on)
2742                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2743         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2744
2745         if (!force_on)
2746                 return 0;
2747
2748         err = intel_wait_for_register(dev_priv,
2749                                       VLV_GTLC_SURVIVABILITY_REG,
2750                                       VLV_GFX_CLK_STATUS_BIT,
2751                                       VLV_GFX_CLK_STATUS_BIT,
2752                                       20);
2753         if (err)
2754                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2755                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2756
2757         return err;
2758 }
2759
2760 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2761 {
2762         u32 mask;
2763         u32 val;
2764         int err;
2765
2766         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2767         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2768         if (allow)
2769                 val |= VLV_GTLC_ALLOWWAKEREQ;
2770         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2771         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2772
2773         mask = VLV_GTLC_ALLOWWAKEACK;
2774         val = allow ? mask : 0;
2775
2776         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2777         if (err)
2778                 DRM_ERROR("timeout disabling GT waking\n");
2779
2780         return err;
2781 }
2782
2783 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2784                                   bool wait_for_on)
2785 {
2786         u32 mask;
2787         u32 val;
2788
2789         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2790         val = wait_for_on ? mask : 0;
2791
2792         /*
2793          * RC6 transitioning can be delayed up to 2 msec (see
2794          * valleyview_enable_rps), use 3 msec for safety.
2795          *
2796          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2797          * reset and we are trying to force the machine to sleep.
2798          */
2799         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2800                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2801                                  onoff(wait_for_on));
2802 }
2803
2804 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2805 {
2806         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2807                 return;
2808
2809         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2810         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2811 }
2812
2813 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2814 {
2815         u32 mask;
2816         int err;
2817
2818         /*
2819          * Bspec defines the following GT well on flags as debug only, so
2820          * don't treat them as hard failures.
2821          */
2822         vlv_wait_for_gt_wells(dev_priv, false);
2823
2824         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2825         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2826
2827         vlv_check_no_gt_access(dev_priv);
2828
2829         err = vlv_force_gfx_clock(dev_priv, true);
2830         if (err)
2831                 goto err1;
2832
2833         err = vlv_allow_gt_wake(dev_priv, false);
2834         if (err)
2835                 goto err2;
2836
2837         if (!IS_CHERRYVIEW(dev_priv))
2838                 vlv_save_gunit_s0ix_state(dev_priv);
2839
2840         err = vlv_force_gfx_clock(dev_priv, false);
2841         if (err)
2842                 goto err2;
2843
2844         return 0;
2845
2846 err2:
2847         /* For safety always re-enable waking and disable gfx clock forcing */
2848         vlv_allow_gt_wake(dev_priv, true);
2849 err1:
2850         vlv_force_gfx_clock(dev_priv, false);
2851
2852         return err;
2853 }
2854
2855 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2856                                 bool rpm_resume)
2857 {
2858         int err;
2859         int ret;
2860
2861         /*
2862          * If any of the steps fail just try to continue, that's the best we
2863          * can do at this point. Return the first error code (which will also
2864          * leave RPM permanently disabled).
2865          */
2866         ret = vlv_force_gfx_clock(dev_priv, true);
2867
2868         if (!IS_CHERRYVIEW(dev_priv))
2869                 vlv_restore_gunit_s0ix_state(dev_priv);
2870
2871         err = vlv_allow_gt_wake(dev_priv, true);
2872         if (!ret)
2873                 ret = err;
2874
2875         err = vlv_force_gfx_clock(dev_priv, false);
2876         if (!ret)
2877                 ret = err;
2878
2879         vlv_check_no_gt_access(dev_priv);
2880
2881         if (rpm_resume)
2882                 intel_init_clock_gating(dev_priv);
2883
2884         return ret;
2885 }
2886
2887 static int intel_runtime_suspend(struct device *kdev)
2888 {
2889         struct pci_dev *pdev = to_pci_dev(kdev);
2890         struct drm_device *dev = pci_get_drvdata(pdev);
2891         struct drm_i915_private *dev_priv = to_i915(dev);
2892         int ret;
2893
2894         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2895                 return -ENODEV;
2896
2897         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2898                 return -ENODEV;
2899
2900         DRM_DEBUG_KMS("Suspending device\n");
2901
2902         disable_rpm_wakeref_asserts(dev_priv);
2903
2904         /*
2905          * We are safe here against re-faults, since the fault handler takes
2906          * an RPM reference.
2907          */
2908         i915_gem_runtime_suspend(dev_priv);
2909
2910         intel_uc_suspend(dev_priv);
2911
2912         intel_runtime_pm_disable_interrupts(dev_priv);
2913
2914         intel_uncore_suspend(dev_priv);
2915
2916         ret = 0;
2917         if (INTEL_GEN(dev_priv) >= 11) {
2918                 icl_display_core_uninit(dev_priv);
2919                 bxt_enable_dc9(dev_priv);
2920         } else if (IS_GEN9_LP(dev_priv)) {
2921                 bxt_display_core_uninit(dev_priv);
2922                 bxt_enable_dc9(dev_priv);
2923         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2924                 hsw_enable_pc8(dev_priv);
2925         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2926                 ret = vlv_suspend_complete(dev_priv);
2927         }
2928
2929         if (ret) {
2930                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2931                 intel_uncore_runtime_resume(dev_priv);
2932
2933                 intel_runtime_pm_enable_interrupts(dev_priv);
2934
2935                 intel_uc_resume(dev_priv);
2936
2937                 i915_gem_init_swizzling(dev_priv);
2938                 i915_gem_restore_fences(dev_priv);
2939
2940                 enable_rpm_wakeref_asserts(dev_priv);
2941
2942                 return ret;
2943         }
2944
2945         enable_rpm_wakeref_asserts(dev_priv);
2946         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2947
2948         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2949                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2950
2951         dev_priv->runtime_pm.suspended = true;
2952
2953         /*
2954          * FIXME: We really should find a document that references the arguments
2955          * used below!
2956          */
2957         if (IS_BROADWELL(dev_priv)) {
2958                 /*
2959                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2960                  * being detected, and the call we do at intel_runtime_resume()
2961                  * won't be able to restore them. Since PCI_D3hot matches the
2962                  * actual specification and appears to be working, use it.
2963                  */
2964                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2965         } else {
2966                 /*
2967                  * current versions of firmware which depend on this opregion
2968                  * notification have repurposed the D1 definition to mean
2969                  * "runtime suspended" vs. what you would normally expect (D3)
2970                  * to distinguish it from notifications that might be sent via
2971                  * the suspend path.
2972                  */
2973                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2974         }
2975
2976         assert_forcewakes_inactive(dev_priv);
2977
2978         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2979                 intel_hpd_poll_init(dev_priv);
2980
2981         DRM_DEBUG_KMS("Device suspended\n");
2982         return 0;
2983 }
2984
2985 static int intel_runtime_resume(struct device *kdev)
2986 {
2987         struct pci_dev *pdev = to_pci_dev(kdev);
2988         struct drm_device *dev = pci_get_drvdata(pdev);
2989         struct drm_i915_private *dev_priv = to_i915(dev);
2990         int ret = 0;
2991
2992         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2993                 return -ENODEV;
2994
2995         DRM_DEBUG_KMS("Resuming device\n");
2996
2997         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2998         disable_rpm_wakeref_asserts(dev_priv);
2999
3000         intel_opregion_notify_adapter(dev_priv, PCI_D0);
3001         dev_priv->runtime_pm.suspended = false;
3002         if (intel_uncore_unclaimed_mmio(dev_priv))
3003                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
3004
3005         if (INTEL_GEN(dev_priv) >= 11) {
3006                 bxt_disable_dc9(dev_priv);
3007                 icl_display_core_init(dev_priv, true);
3008                 if (dev_priv->csr.dmc_payload) {
3009                         if (dev_priv->csr.allowed_dc_mask &
3010                             DC_STATE_EN_UPTO_DC6)
3011                                 skl_enable_dc6(dev_priv);
3012                         else if (dev_priv->csr.allowed_dc_mask &
3013                                  DC_STATE_EN_UPTO_DC5)
3014                                 gen9_enable_dc5(dev_priv);
3015                 }
3016         } else if (IS_GEN9_LP(dev_priv)) {
3017                 bxt_disable_dc9(dev_priv);
3018                 bxt_display_core_init(dev_priv, true);
3019                 if (dev_priv->csr.dmc_payload &&
3020                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
3021                         gen9_enable_dc5(dev_priv);
3022         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3023                 hsw_disable_pc8(dev_priv);
3024         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3025                 ret = vlv_resume_prepare(dev_priv, true);
3026         }
3027
3028         intel_uncore_runtime_resume(dev_priv);
3029
3030         intel_runtime_pm_enable_interrupts(dev_priv);
3031
3032         intel_uc_resume(dev_priv);
3033
3034         /*
3035          * No point of rolling back things in case of an error, as the best
3036          * we can do is to hope that things will still work (and disable RPM).
3037          */
3038         i915_gem_init_swizzling(dev_priv);
3039         i915_gem_restore_fences(dev_priv);
3040
3041         /*
3042          * On VLV/CHV display interrupts are part of the display
3043          * power well, so hpd is reinitialized from there. For
3044          * everyone else do it here.
3045          */
3046         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
3047                 intel_hpd_init(dev_priv);
3048
3049         intel_enable_ipc(dev_priv);
3050
3051         enable_rpm_wakeref_asserts(dev_priv);
3052
3053         if (ret)
3054                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
3055         else
3056                 DRM_DEBUG_KMS("Device resumed\n");
3057
3058         return ret;
3059 }
3060
3061 const struct dev_pm_ops i915_pm_ops = {
3062         /*
3063          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3064          * PMSG_RESUME]
3065          */
3066         .prepare = i915_pm_prepare,
3067         .suspend = i915_pm_suspend,
3068         .suspend_late = i915_pm_suspend_late,
3069         .resume_early = i915_pm_resume_early,
3070         .resume = i915_pm_resume,
3071
3072         /*
3073          * S4 event handlers
3074          * @freeze, @freeze_late    : called (1) before creating the
3075          *                            hibernation image [PMSG_FREEZE] and
3076          *                            (2) after rebooting, before restoring
3077          *                            the image [PMSG_QUIESCE]
3078          * @thaw, @thaw_early       : called (1) after creating the hibernation
3079          *                            image, before writing it [PMSG_THAW]
3080          *                            and (2) after failing to create or
3081          *                            restore the image [PMSG_RECOVER]
3082          * @poweroff, @poweroff_late: called after writing the hibernation
3083          *                            image, before rebooting [PMSG_HIBERNATE]
3084          * @restore, @restore_early : called after rebooting and restoring the
3085          *                            hibernation image [PMSG_RESTORE]
3086          */
3087         .freeze = i915_pm_freeze,
3088         .freeze_late = i915_pm_freeze_late,
3089         .thaw_early = i915_pm_thaw_early,
3090         .thaw = i915_pm_thaw,
3091         .poweroff = i915_pm_suspend,
3092         .poweroff_late = i915_pm_poweroff_late,
3093         .restore_early = i915_pm_restore_early,
3094         .restore = i915_pm_restore,
3095
3096         /* S0ix (via runtime suspend) event handlers */
3097         .runtime_suspend = intel_runtime_suspend,
3098         .runtime_resume = intel_runtime_resume,
3099 };
3100
3101 static const struct vm_operations_struct i915_gem_vm_ops = {
3102         .fault = i915_gem_fault,
3103         .open = drm_gem_vm_open,
3104         .close = drm_gem_vm_close,
3105 };
3106
3107 static const struct file_operations i915_driver_fops = {
3108         .owner = THIS_MODULE,
3109         .open = drm_open,
3110         .release = drm_release,
3111         .unlocked_ioctl = drm_ioctl,
3112         .mmap = drm_gem_mmap,
3113         .poll = drm_poll,
3114         .read = drm_read,
3115         .compat_ioctl = i915_compat_ioctl,
3116         .llseek = noop_llseek,
3117 };
3118
3119 static int
3120 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3121                           struct drm_file *file)
3122 {
3123         return -ENODEV;
3124 }
3125
3126 static const struct drm_ioctl_desc i915_ioctls[] = {
3127         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3128         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3129         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3130         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3131         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3132         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3133         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3134         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3135         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3136         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3137         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3138         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3139         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3140         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3141         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
3142         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3143         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3144         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3145         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3146         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3147         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3148         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3149         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3150         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3151         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3152         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3153         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3154         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3155         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3156         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3157         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3158         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3159         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3160         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3161         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3162         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3163         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3164         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3165         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3166         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3167         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3168         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3169         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3170         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3171         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3172         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3173         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3174         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3175         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3176         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3177         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3178         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3179         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3180         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3181         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3182         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3183 };
3184
3185 static struct drm_driver driver = {
3186         /* Don't use MTRRs here; the Xserver or userspace app should
3187          * deal with them for Intel hardware.
3188          */
3189         .driver_features =
3190             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
3191             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3192         .release = i915_driver_release,
3193         .open = i915_driver_open,
3194         .lastclose = i915_driver_lastclose,
3195         .postclose = i915_driver_postclose,
3196
3197         .gem_close_object = i915_gem_close_object,
3198         .gem_free_object_unlocked = i915_gem_free_object,
3199         .gem_vm_ops = &i915_gem_vm_ops,
3200
3201         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3202         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3203         .gem_prime_export = i915_gem_prime_export,
3204         .gem_prime_import = i915_gem_prime_import,
3205
3206         .dumb_create = i915_gem_dumb_create,
3207         .dumb_map_offset = i915_gem_mmap_gtt,
3208         .ioctls = i915_ioctls,
3209         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3210         .fops = &i915_driver_fops,
3211         .name = DRIVER_NAME,
3212         .desc = DRIVER_DESC,
3213         .date = DRIVER_DATE,
3214         .major = DRIVER_MAJOR,
3215         .minor = DRIVER_MINOR,
3216         .patchlevel = DRIVER_PATCHLEVEL,
3217 };
3218
3219 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3220 #include "selftests/mock_drm.c"
3221 #endif