1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_atomic.h>
58 #include <drm/drm_connector.h>
59 #include <drm/i915_mei_hdcp_interface.h>
61 #include "i915_fixed.h"
62 #include "i915_params.h"
64 #include "i915_utils.h"
66 #include "gt/intel_lrc.h"
67 #include "gt/intel_engine.h"
68 #include "gt/intel_workarounds.h"
70 #include "intel_bios.h"
71 #include "intel_device_info.h"
72 #include "intel_display.h"
73 #include "intel_display_power.h"
74 #include "intel_dpll_mgr.h"
75 #include "intel_frontbuffer.h"
76 #include "intel_opregion.h"
77 #include "intel_runtime_pm.h"
79 #include "intel_uncore.h"
80 #include "intel_wakeref.h"
81 #include "intel_wopcm.h"
84 #include "gem/i915_gem_context_types.h"
85 #include "i915_gem_fence_reg.h"
86 #include "i915_gem_gtt.h"
87 #include "i915_gpu_error.h"
88 #include "i915_request.h"
89 #include "i915_scheduler.h"
90 #include "i915_timeline.h"
93 #include "intel_gvt.h"
95 /* General customization:
98 #define DRIVER_NAME "i915"
99 #define DRIVER_DESC "Intel Graphics"
100 #define DRIVER_DATE "20190524"
101 #define DRIVER_TIMESTAMP 1558719322
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105 * which may not necessarily be a user visible problem. This will either
106 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107 * enable distros and users to tailor their preferred amount of i915 abrt
110 #define I915_STATE_WARN(condition, format...) ({ \
111 int __ret_warn_on = !!(condition); \
112 if (unlikely(__ret_warn_on)) \
113 if (!WARN(i915_modparams.verbose_state_checks, format)) \
115 unlikely(__ret_warn_on); \
118 #define I915_STATE_WARN_ON(x) \
119 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
121 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
123 bool __i915_inject_load_failure(const char *func, int line);
124 #define i915_inject_load_failure() \
125 __i915_inject_load_failure(__func__, __LINE__)
127 bool i915_error_injected(void);
131 #define i915_inject_load_failure() false
132 #define i915_error_injected() false
136 #define i915_load_error(i915, fmt, ...) \
137 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
140 struct drm_i915_gem_object;
144 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
157 #define for_each_hpd_pin(__pin) \
158 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
160 /* Threshold == 5 for long IRQs, 50 for short */
161 #define HPD_STORM_DEFAULT_THRESHOLD 50
163 struct i915_hotplug {
164 struct work_struct hotplug_work;
167 unsigned long last_jiffies;
172 HPD_MARK_DISABLED = 2
174 } stats[HPD_NUM_PINS];
176 struct delayed_work reenable_work;
180 struct work_struct dig_port_work;
182 struct work_struct poll_init_work;
185 unsigned int hpd_storm_threshold;
186 /* Whether or not to count short HPD IRQs in HPD storms */
187 u8 hpd_short_storm_enabled;
190 * if we get a HPD irq from DP and a HPD irq from non-DP
191 * the non-DP HPD could block the workqueue on a mode config
192 * mutex getting, that userspace may have taken. However
193 * userspace is waiting on the DP workqueue to run which is
194 * blocked behind the non-DP one.
196 struct workqueue_struct *dp_wq;
199 #define I915_GEM_GPU_DOMAINS \
200 (I915_GEM_DOMAIN_RENDER | \
201 I915_GEM_DOMAIN_SAMPLER | \
202 I915_GEM_DOMAIN_COMMAND | \
203 I915_GEM_DOMAIN_INSTRUCTION | \
204 I915_GEM_DOMAIN_VERTEX)
206 struct drm_i915_private;
207 struct i915_mm_struct;
208 struct i915_mmu_object;
210 struct drm_i915_file_private {
211 struct drm_i915_private *dev_priv;
212 struct drm_file *file;
216 struct list_head request_list;
219 struct idr context_idr;
220 struct mutex context_idr_lock; /* guards context_idr */
223 struct mutex vm_idr_lock; /* guards vm_idr */
225 unsigned int bsd_engine;
228 * Every context ban increments per client ban score. Also
229 * hangs in short succession increments ban score. If ban threshold
230 * is reached, client is considered banned and submitting more work
231 * will fail. This is a stop gap measure to limit the badly behaving
232 * clients access to gpu. Note that unbannable contexts never increment
233 * the client ban score.
235 #define I915_CLIENT_SCORE_HANG_FAST 1
236 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
237 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
238 #define I915_CLIENT_SCORE_BANNED 9
239 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
241 unsigned long hang_timestamp;
244 /* Interface history:
247 * 1.2: Add Power Management
248 * 1.3: Add vblank support
249 * 1.4: Fix cmdbuffer path, add heap destroy
250 * 1.5: Add vblank pipe configuration
251 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
252 * - Support vertical blank on secondary display pipe
254 #define DRIVER_MAJOR 1
255 #define DRIVER_MINOR 6
256 #define DRIVER_PATCHLEVEL 0
258 struct intel_overlay;
259 struct intel_overlay_error_state;
261 struct sdvo_device_mapping {
270 struct intel_connector;
271 struct intel_encoder;
272 struct intel_atomic_state;
273 struct intel_crtc_state;
274 struct intel_initial_plane_config;
278 struct intel_cdclk_state;
280 struct drm_i915_display_funcs {
281 void (*get_cdclk)(struct drm_i915_private *dev_priv,
282 struct intel_cdclk_state *cdclk_state);
283 void (*set_cdclk)(struct drm_i915_private *dev_priv,
284 const struct intel_cdclk_state *cdclk_state,
286 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
287 enum i9xx_plane_id i9xx_plane);
288 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
289 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
290 void (*initial_watermarks)(struct intel_atomic_state *state,
291 struct intel_crtc_state *cstate);
292 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
293 struct intel_crtc_state *cstate);
294 void (*optimize_watermarks)(struct intel_atomic_state *state,
295 struct intel_crtc_state *cstate);
296 int (*compute_global_watermarks)(struct intel_atomic_state *state);
297 void (*update_wm)(struct intel_crtc *crtc);
298 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
299 /* Returns the active state of the crtc, and if the crtc is active,
300 * fills out the pipe-config with the hw state. */
301 bool (*get_pipe_config)(struct intel_crtc *,
302 struct intel_crtc_state *);
303 void (*get_initial_plane_config)(struct intel_crtc *,
304 struct intel_initial_plane_config *);
305 int (*crtc_compute_clock)(struct intel_crtc *crtc,
306 struct intel_crtc_state *crtc_state);
307 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
308 struct drm_atomic_state *old_state);
309 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
310 struct drm_atomic_state *old_state);
311 void (*update_crtcs)(struct drm_atomic_state *state);
312 void (*audio_codec_enable)(struct intel_encoder *encoder,
313 const struct intel_crtc_state *crtc_state,
314 const struct drm_connector_state *conn_state);
315 void (*audio_codec_disable)(struct intel_encoder *encoder,
316 const struct intel_crtc_state *old_crtc_state,
317 const struct drm_connector_state *old_conn_state);
318 void (*fdi_link_train)(struct intel_crtc *crtc,
319 const struct intel_crtc_state *crtc_state);
320 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
321 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
322 /* clock updates for mode set */
324 /* render clock increase/decrease */
325 /* display clock increase/decrease */
326 /* pll clock increase/decrease */
328 int (*color_check)(struct intel_crtc_state *crtc_state);
330 * Program double buffered color management registers during
331 * vblank evasion. The registers should then latch during the
332 * next vblank start, alongside any other double buffered registers
333 * involved with the same commit.
335 void (*color_commit)(const struct intel_crtc_state *crtc_state);
337 * Load LUTs (and other single buffered color management
338 * registers). Will (hopefully) be called during the vblank
339 * following the latching of any double buffered registers
340 * involved with the same commit.
342 void (*load_luts)(const struct intel_crtc_state *crtc_state);
343 void (*read_luts)(struct intel_crtc_state *crtc_state);
347 struct work_struct work;
349 u32 required_version;
350 u32 max_fw_size; /* bytes */
352 u32 dmc_fw_size; /* dwords */
355 i915_reg_t mmioaddr[8];
359 intel_wakeref_t wakeref;
362 enum i915_cache_level {
364 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
365 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
366 caches, eg sampler/render caches, and the
367 large Last-Level-Cache. LLC is coherent with
368 the CPU, but L3 is only visible to the GPU. */
369 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
372 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
375 /* This is always the inner lock when overlapping with struct_mutex and
376 * it's the outer lock when overlapping with stolen_lock. */
379 unsigned int possible_framebuffer_bits;
380 unsigned int busy_bits;
381 unsigned int visible_pipes_mask;
382 struct intel_crtc *crtc;
384 struct drm_mm_node compressed_fb;
385 struct drm_mm_node *compressed_llb;
393 bool underrun_detected;
394 struct work_struct underrun_work;
397 * Due to the atomic rules we can't access some structures without the
398 * appropriate locking, so we cache information here in order to avoid
401 struct intel_fbc_state_cache {
402 struct i915_vma *vma;
406 unsigned int mode_flags;
407 u32 hsw_bdw_pixel_rate;
411 unsigned int rotation;
416 * Display surface base address adjustement for
417 * pageflips. Note that on gen4+ this only adjusts up
418 * to a tile, offsets within a tile are handled in
419 * the hw itself (with the TILEOFF register).
426 u16 pixel_blend_mode;
430 const struct drm_format_info *format;
436 * This structure contains everything that's relevant to program the
437 * hardware registers. When we want to figure out if we need to disable
438 * and re-enable FBC for a new configuration we just check if there's
439 * something different in the struct. The genx_fbc_activate functions
440 * are supposed to read from it in order to program the registers.
442 struct intel_fbc_reg_params {
443 struct i915_vma *vma;
448 enum i9xx_plane_id i9xx_plane;
449 unsigned int fence_y_offset;
453 const struct drm_format_info *format;
458 unsigned int gen9_wa_cfb_stride;
461 const char *no_fbc_reason;
465 * HIGH_RR is the highest eDP panel refresh rate read from EDID
466 * LOW_RR is the lowest eDP panel refresh rate found from EDID
467 * parsing for same resolution.
469 enum drrs_refresh_rate_type {
472 DRRS_MAX_RR, /* RR count */
475 enum drrs_support_type {
476 DRRS_NOT_SUPPORTED = 0,
477 STATIC_DRRS_SUPPORT = 1,
478 SEAMLESS_DRRS_SUPPORT = 2
484 struct delayed_work work;
486 unsigned busy_frontbuffer_bits;
487 enum drrs_refresh_rate_type refresh_rate_type;
488 enum drrs_support_type type;
494 #define I915_PSR_DEBUG_MODE_MASK 0x0f
495 #define I915_PSR_DEBUG_DEFAULT 0x00
496 #define I915_PSR_DEBUG_DISABLE 0x01
497 #define I915_PSR_DEBUG_ENABLE 0x02
498 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
499 #define I915_PSR_DEBUG_IRQ 0x10
507 struct work_struct work;
508 unsigned busy_frontbuffer_bits;
509 bool sink_psr2_support;
511 bool colorimetry_support;
513 u8 sink_sync_latency;
514 ktime_t last_entry_attempt;
516 bool sink_not_reliable;
518 u16 su_x_granularity;
522 * Sorted by south display engine compatibility.
523 * If the new PCH comes with a south display engine that is not
524 * inherited from the latest item, please do not add it to the
525 * end. Instead, add it right after its "parent" PCH.
528 PCH_NOP = -1, /* PCH without south display */
529 PCH_NONE = 0, /* No PCH present */
530 PCH_IBX, /* Ibexpeak PCH */
531 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
532 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
533 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
534 PCH_CNP, /* Cannon/Comet Lake PCH */
535 PCH_ICP, /* Ice Lake PCH */
538 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
539 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
540 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
541 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
542 #define QUIRK_INCREASE_T12_DELAY (1<<6)
543 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
546 struct intel_fbc_work;
549 struct i2c_adapter adapter;
550 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
554 struct i2c_algo_bit_data bit_algo;
555 struct drm_i915_private *dev_priv;
558 struct i915_suspend_saved_registers {
561 u32 saveCACHE_MODE_0;
562 u32 saveMI_ARB_STATE;
566 u64 saveFENCE[I915_MAX_NUM_FENCES];
567 u32 savePCH_PORT_HOTPLUG;
571 struct vlv_s0ix_state {
578 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
579 u32 media_max_req_count;
580 u32 gfx_max_req_count;
612 /* Display 1 CZ domain */
617 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
619 /* GT SA CZ domain */
626 /* Display 2 CZ domain */
633 struct intel_rps_ei {
640 struct mutex lock; /* protects enabling and the worker */
643 * work, interrupts_enabled and pm_iir are protected by
646 struct work_struct work;
647 bool interrupts_enabled;
650 /* PM interrupt bits that should never be masked */
653 /* Frequencies are stored in potentially platform dependent multiples.
654 * In other words, *_freq needs to be multiplied by X to be interesting.
655 * Soft limits are those which are used for the dynamic reclocking done
656 * by the driver (raise frequencies under heavy loads, and lower for
657 * lighter loads). Hard limits are those imposed by the hardware.
659 * A distinction is made for overclocking, which is never enabled by
660 * default, and is considered to be above the hard limit if it's
663 u8 cur_freq; /* Current frequency (cached, may not == HW) */
664 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
665 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
666 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
667 u8 min_freq; /* AKA RPn. Minimum frequency */
668 u8 boost_freq; /* Frequency to request when wait boosting */
669 u8 idle_freq; /* Frequency to request when we are idle */
670 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
671 u8 rp1_freq; /* "less than" RP0 power/freqency */
672 u8 rp0_freq; /* Non-overclocked max frequency. */
673 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
680 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
681 unsigned int interactive;
683 u8 up_threshold; /* Current %busy required to uplock */
684 u8 down_threshold; /* Current %busy required to downclock */
688 atomic_t num_waiters;
691 /* manual wa residency calculations */
692 struct intel_rps_ei ei;
697 u64 prev_hw_residency[4];
698 u64 cur_residency[4];
701 struct intel_llc_pstate {
705 struct intel_gen6_power_mgmt {
706 struct intel_rps rps;
707 struct intel_rc6 rc6;
708 struct intel_llc_pstate llc_pstate;
711 /* defined intel_pm.c */
712 extern spinlock_t mchdev_lock;
714 struct intel_ilk_power_mgmt {
722 unsigned long last_time1;
723 unsigned long chipset_power;
726 unsigned long gfx_power;
733 #define MAX_L3_SLICES 2
734 struct intel_l3_parity {
735 u32 *remap_info[MAX_L3_SLICES];
736 struct work_struct error_work;
741 /** Memory allocator for GTT stolen memory */
742 struct drm_mm stolen;
743 /** Protects the usage of the GTT stolen memory allocator. This is
744 * always the inner lock when overlapping with struct_mutex. */
745 struct mutex stolen_lock;
747 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
751 * List of objects which are purgeable.
753 struct list_head purge_list;
756 * List of objects which have allocated pages and are shrinkable.
758 struct list_head shrink_list;
761 * List of objects which are pending destruction.
763 struct llist_head free_list;
764 struct work_struct free_work;
765 spinlock_t free_lock;
767 * Count of objects pending destructions. Used to skip needlessly
768 * waiting on an RCU barrier if no objects are waiting to be freed.
773 * Small stash of WC pages
775 struct pagestash wc_stash;
778 * tmpfs instance used for shmem backed objects
780 struct vfsmount *gemfs;
782 /** PPGTT used for aliasing the PPGTT with the GTT */
783 struct i915_ppgtt *aliasing_ppgtt;
785 struct notifier_block oom_notifier;
786 struct notifier_block vmap_notifier;
787 struct shrinker shrinker;
790 * Workqueue to fault in userptr pages, flushed by the execbuf
791 * when required but otherwise left to userspace to try again
794 struct workqueue_struct *userptr_wq;
796 u64 unordered_timeline;
798 /* the indicator for dispatch video commands on two BSD rings */
799 atomic_t bsd_engine_dispatch_index;
801 /** Bit 6 swizzling required for X tiling */
803 /** Bit 6 swizzling required for Y tiling */
806 /* shrinker accounting, also useful for userland debugging */
811 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
813 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
814 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
816 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
817 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
819 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
821 struct ddi_vbt_port_info {
822 /* Non-NULL if port present. */
823 const struct child_device_config *child;
828 * This is an index in the HDMI/DVI DDI buffer translation table.
829 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
830 * populate this field.
832 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
839 u8 supports_typec_usb:1;
842 u8 alternate_aux_channel;
843 u8 alternate_ddc_pin;
847 int dp_max_link_rate; /* 0 for not limited by VBT */
850 enum psr_lines_to_wait {
851 PSR_0_LINES_TO_WAIT = 0,
857 struct intel_vbt_data {
858 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
859 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
862 unsigned int int_tv_support:1;
863 unsigned int lvds_dither:1;
864 unsigned int int_crt_support:1;
865 unsigned int lvds_use_ssc:1;
866 unsigned int int_lvds_support:1;
867 unsigned int display_clock_mode:1;
868 unsigned int fdi_rx_polarity_inverted:1;
869 unsigned int panel_type:4;
871 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
872 enum drm_panel_orientation orientation;
874 enum drrs_support_type drrs_type;
884 struct edp_power_seq pps;
890 bool require_aux_wakeup;
892 enum psr_lines_to_wait lines_to_wait;
893 int tp1_wakeup_time_us;
894 int tp2_tp3_wakeup_time_us;
895 int psr2_tp2_tp3_wakeup_time_us;
902 u8 min_brightness; /* min_brightness/255 of max */
903 u8 controller; /* brightness controller number */
904 enum intel_backlight_type type;
910 struct mipi_config *config;
911 struct mipi_pps_data *pps;
917 const u8 *sequence[MIPI_SEQ_MAX];
918 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
919 enum drm_panel_orientation orientation;
925 struct child_device_config *child_dev;
927 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
928 struct sdvo_device_mapping sdvo_mappings[2];
931 enum intel_ddb_partitioning {
933 INTEL_DDB_PART_5_6, /* IVB+ */
936 struct intel_wm_level {
944 struct ilk_wm_values {
950 enum intel_ddb_partitioning partitioning;
954 u16 plane[I915_MAX_PLANES];
964 struct vlv_wm_ddl_values {
965 u8 plane[I915_MAX_PLANES];
968 struct vlv_wm_values {
969 struct g4x_pipe_wm pipe[3];
971 struct vlv_wm_ddl_values ddl[3];
976 struct g4x_wm_values {
977 struct g4x_pipe_wm pipe[2];
979 struct g4x_sr_wm hpll;
985 struct skl_ddb_entry {
986 u16 start, end; /* in number of blocks, 'end' is exclusive */
989 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
991 return entry->end - entry->start;
994 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
995 const struct skl_ddb_entry *e2)
997 if (e1->start == e2->start && e1->end == e2->end)
1003 struct skl_ddb_allocation {
1004 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1007 struct skl_ddb_values {
1008 unsigned dirty_pipes;
1009 struct skl_ddb_allocation ddb;
1012 struct skl_wm_level {
1020 /* Stores plane specific WM parameters */
1021 struct skl_wm_params {
1022 bool x_tiled, y_tiled;
1027 u32 plane_pixel_rate;
1028 u32 y_min_scanlines;
1029 u32 plane_bytes_per_line;
1030 uint_fixed_16_16_t plane_blocks_per_line;
1031 uint_fixed_16_16_t y_tile_minimum;
1033 u32 dbuf_block_size;
1037 * This struct helps tracking the state needed for runtime PM, which puts the
1038 * device in PCI D3 state. Notice that when this happens, nothing on the
1039 * graphics device works, even register access, so we don't get interrupts nor
1042 * Every piece of our code that needs to actually touch the hardware needs to
1043 * either call intel_runtime_pm_get or call intel_display_power_get with the
1044 * appropriate power domain.
1046 * Our driver uses the autosuspend delay feature, which means we'll only really
1047 * suspend if we stay with zero refcount for a certain amount of time. The
1048 * default value is currently very conservative (see intel_runtime_pm_enable), but
1049 * it can be changed with the standard runtime PM files from sysfs.
1051 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1052 * goes back to false exactly before we reenable the IRQs. We use this variable
1053 * to check if someone is trying to enable/disable IRQs while they're supposed
1054 * to be disabled. This shouldn't happen and we'll print some error messages in
1057 * For more, read the Documentation/power/runtime_pm.txt.
1059 struct i915_runtime_pm {
1060 atomic_t wakeref_count;
1064 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1066 * To aide detection of wakeref leaks and general misuse, we
1067 * track all wakeref holders. With manual markup (i.e. returning
1068 * a cookie to each rpm_get caller which they then supply to their
1069 * paired rpm_put) we can remove corresponding pairs of and keep
1070 * the array trimmed to active wakerefs.
1072 struct intel_runtime_pm_debug {
1075 depot_stack_handle_t last_acquire;
1076 depot_stack_handle_t last_release;
1078 depot_stack_handle_t *owners;
1079 unsigned long count;
1084 enum intel_pipe_crc_source {
1085 INTEL_PIPE_CRC_SOURCE_NONE,
1086 INTEL_PIPE_CRC_SOURCE_PLANE1,
1087 INTEL_PIPE_CRC_SOURCE_PLANE2,
1088 INTEL_PIPE_CRC_SOURCE_PLANE3,
1089 INTEL_PIPE_CRC_SOURCE_PLANE4,
1090 INTEL_PIPE_CRC_SOURCE_PLANE5,
1091 INTEL_PIPE_CRC_SOURCE_PLANE6,
1092 INTEL_PIPE_CRC_SOURCE_PLANE7,
1093 INTEL_PIPE_CRC_SOURCE_PIPE,
1094 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1095 INTEL_PIPE_CRC_SOURCE_TV,
1096 INTEL_PIPE_CRC_SOURCE_DP_B,
1097 INTEL_PIPE_CRC_SOURCE_DP_C,
1098 INTEL_PIPE_CRC_SOURCE_DP_D,
1099 INTEL_PIPE_CRC_SOURCE_AUTO,
1100 INTEL_PIPE_CRC_SOURCE_MAX,
1103 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1104 struct intel_pipe_crc {
1107 enum intel_pipe_crc_source source;
1110 struct i915_frontbuffer_tracking {
1114 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1121 struct i915_virtual_gpu {
1126 /* used in computing the new watermarks state */
1127 struct intel_wm_config {
1128 unsigned int num_pipes_active;
1129 bool sprites_enabled;
1130 bool sprites_scaled;
1133 struct i915_oa_format {
1138 struct i915_oa_reg {
1143 struct i915_oa_config {
1144 char uuid[UUID_STRING_LEN + 1];
1147 const struct i915_oa_reg *mux_regs;
1149 const struct i915_oa_reg *b_counter_regs;
1150 u32 b_counter_regs_len;
1151 const struct i915_oa_reg *flex_regs;
1154 struct attribute_group sysfs_metric;
1155 struct attribute *attrs[2];
1156 struct device_attribute sysfs_metric_id;
1161 struct i915_perf_stream;
1164 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1166 struct i915_perf_stream_ops {
1168 * @enable: Enables the collection of HW samples, either in response to
1169 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1170 * without `I915_PERF_FLAG_DISABLED`.
1172 void (*enable)(struct i915_perf_stream *stream);
1175 * @disable: Disables the collection of HW samples, either in response
1176 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1179 void (*disable)(struct i915_perf_stream *stream);
1182 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1183 * once there is something ready to read() for the stream
1185 void (*poll_wait)(struct i915_perf_stream *stream,
1190 * @wait_unlocked: For handling a blocking read, wait until there is
1191 * something to ready to read() for the stream. E.g. wait on the same
1192 * wait queue that would be passed to poll_wait().
1194 int (*wait_unlocked)(struct i915_perf_stream *stream);
1197 * @read: Copy buffered metrics as records to userspace
1198 * **buf**: the userspace, destination buffer
1199 * **count**: the number of bytes to copy, requested by userspace
1200 * **offset**: zero at the start of the read, updated as the read
1201 * proceeds, it represents how many bytes have been copied so far and
1202 * the buffer offset for copying the next record.
1204 * Copy as many buffered i915 perf samples and records for this stream
1205 * to userspace as will fit in the given buffer.
1207 * Only write complete records; returning -%ENOSPC if there isn't room
1208 * for a complete record.
1210 * Return any error condition that results in a short read such as
1211 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1212 * returning to userspace.
1214 int (*read)(struct i915_perf_stream *stream,
1220 * @destroy: Cleanup any stream specific resources.
1222 * The stream will always be disabled before this is called.
1224 void (*destroy)(struct i915_perf_stream *stream);
1228 * struct i915_perf_stream - state for a single open stream FD
1230 struct i915_perf_stream {
1232 * @dev_priv: i915 drm device
1234 struct drm_i915_private *dev_priv;
1237 * @link: Links the stream into ``&drm_i915_private->streams``
1239 struct list_head link;
1242 * @wakeref: As we keep the device awake while the perf stream is
1243 * active, we track our runtime pm reference for later release.
1245 intel_wakeref_t wakeref;
1248 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1249 * properties given when opening a stream, representing the contents
1250 * of a single sample as read() by userspace.
1255 * @sample_size: Considering the configured contents of a sample
1256 * combined with the required header size, this is the total size
1257 * of a single sample record.
1262 * @ctx: %NULL if measuring system-wide across all contexts or a
1263 * specific context that is being monitored.
1265 struct i915_gem_context *ctx;
1268 * @enabled: Whether the stream is currently enabled, considering
1269 * whether the stream was opened in a disabled state and based
1270 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1275 * @ops: The callbacks providing the implementation of this specific
1276 * type of configured stream.
1278 const struct i915_perf_stream_ops *ops;
1281 * @oa_config: The OA configuration used by the stream.
1283 struct i915_oa_config *oa_config;
1287 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1289 struct i915_oa_ops {
1291 * @is_valid_b_counter_reg: Validates register's address for
1292 * programming boolean counters for a particular platform.
1294 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1298 * @is_valid_mux_reg: Validates register's address for programming mux
1299 * for a particular platform.
1301 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1304 * @is_valid_flex_reg: Validates register's address for programming
1305 * flex EU filtering for a particular platform.
1307 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1310 * @enable_metric_set: Selects and applies any MUX configuration to set
1311 * up the Boolean and Custom (B/C) counters that are part of the
1312 * counter reports being sampled. May apply system constraints such as
1313 * disabling EU clock gating as required.
1315 int (*enable_metric_set)(struct i915_perf_stream *stream);
1318 * @disable_metric_set: Remove system constraints associated with using
1321 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1324 * @oa_enable: Enable periodic sampling
1326 void (*oa_enable)(struct i915_perf_stream *stream);
1329 * @oa_disable: Disable periodic sampling
1331 void (*oa_disable)(struct i915_perf_stream *stream);
1334 * @read: Copy data from the circular OA buffer into a given userspace
1337 int (*read)(struct i915_perf_stream *stream,
1343 * @oa_hw_tail_read: read the OA tail pointer register
1345 * In particular this enables us to share all the fiddly code for
1346 * handling the OA unit tail pointer race that affects multiple
1349 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1352 struct intel_cdclk_state {
1353 unsigned int cdclk, vco, ref, bypass;
1357 struct drm_i915_private {
1358 struct drm_device drm;
1360 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1361 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1362 struct intel_driver_caps caps;
1365 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1366 * end of stolen which we can optionally use to create GEM objects
1367 * backed by stolen memory. Note that stolen_usable_size tells us
1368 * exactly how much of this we are actually allowed to use, given that
1369 * some portion of it is in fact reserved for use by hardware functions.
1371 struct resource dsm;
1373 * Reseved portion of Data Stolen Memory
1375 struct resource dsm_reserved;
1378 * Stolen memory is segmented in hardware with different portions
1379 * offlimits to certain functions.
1381 * The drm_mm is initialised to the total accessible range, as found
1382 * from the PCI config. On Broadwell+, this is further restricted to
1383 * avoid the first page! The upper end of stolen memory is reserved for
1384 * hardware functions and similarly removed from the accessible range.
1386 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1388 struct intel_uncore uncore;
1390 struct i915_virtual_gpu vgpu;
1392 struct intel_gvt *gvt;
1394 struct intel_wopcm wopcm;
1396 struct intel_huc huc;
1397 struct intel_guc guc;
1399 struct intel_csr csr;
1401 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1403 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1404 * controller on different i2c buses. */
1405 struct mutex gmbus_mutex;
1408 * Base address of where the gmbus and gpio blocks are located (either
1409 * on PCH or on SoC for platforms without PCH).
1413 /* MMIO base address for MIPI regs */
1420 wait_queue_head_t gmbus_wait_queue;
1422 struct pci_dev *bridge_dev;
1423 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1424 /* Context used internally to idle the GPU and setup initial state */
1425 struct i915_gem_context *kernel_context;
1426 /* Context only to be used for injecting preemption commands */
1427 struct i915_gem_context *preempt_context;
1428 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1429 [MAX_ENGINE_INSTANCE + 1];
1431 struct resource mch_res;
1433 /* protects the irq masks */
1434 spinlock_t irq_lock;
1436 bool display_irqs_enabled;
1438 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1439 struct pm_qos_request pm_qos;
1441 /* Sideband mailbox protection */
1442 struct mutex sb_lock;
1443 struct pm_qos_request sb_qos;
1445 /** Cached value of IMR to avoid reads in updating the bitfield */
1448 u32 de_irq_mask[I915_MAX_PIPES];
1455 u32 pipestat_irq_mask[I915_MAX_PIPES];
1457 struct i915_hotplug hotplug;
1458 struct intel_fbc fbc;
1459 struct i915_drrs drrs;
1460 struct intel_opregion opregion;
1461 struct intel_vbt_data vbt;
1463 bool preserve_bios_swizzle;
1466 struct intel_overlay *overlay;
1468 /* backlight registers and fields in struct intel_panel */
1469 struct mutex backlight_lock;
1472 bool no_aux_handshake;
1474 /* protects panel power sequencer state */
1475 struct mutex pps_mutex;
1477 unsigned int fsb_freq, mem_freq, is_ddr3;
1478 unsigned int skl_preferred_vco_freq;
1479 unsigned int max_cdclk_freq;
1481 unsigned int max_dotclk_freq;
1482 unsigned int rawclk_freq;
1483 unsigned int hpll_freq;
1484 unsigned int fdi_pll_freq;
1485 unsigned int czclk_freq;
1489 * The current logical cdclk state.
1490 * See intel_atomic_state.cdclk.logical
1492 * For reading holding any crtc lock is sufficient,
1493 * for writing must hold all of them.
1495 struct intel_cdclk_state logical;
1497 * The current actual cdclk state.
1498 * See intel_atomic_state.cdclk.actual
1500 struct intel_cdclk_state actual;
1501 /* The current hardware cdclk state */
1502 struct intel_cdclk_state hw;
1504 int force_min_cdclk;
1508 * wq - Driver workqueue for GEM.
1510 * NOTE: Work items scheduled here are not allowed to grab any modeset
1511 * locks, for otherwise the flushing done in the pageflip code will
1512 * result in deadlocks.
1514 struct workqueue_struct *wq;
1516 /* ordered wq for modesets */
1517 struct workqueue_struct *modeset_wq;
1519 /* Display functions */
1520 struct drm_i915_display_funcs display;
1522 /* PCH chipset type */
1523 enum intel_pch pch_type;
1524 unsigned short pch_id;
1526 unsigned long quirks;
1528 struct drm_atomic_state *modeset_restore_state;
1529 struct drm_modeset_acquire_ctx reset_ctx;
1531 struct i915_ggtt ggtt; /* VM representing the global address space */
1533 struct i915_gem_mm mm;
1534 DECLARE_HASHTABLE(mm_structs, 7);
1535 struct mutex mm_lock;
1537 struct intel_ppat ppat;
1539 /* Kernel Modesetting */
1541 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1542 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1544 #ifdef CONFIG_DEBUG_FS
1545 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1548 /* dpll and cdclk state is protected by connection_mutex */
1549 int num_shared_dpll;
1550 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1551 const struct intel_dpll_mgr *dpll_mgr;
1554 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1555 * Must be global rather than per dpll, because on some platforms
1556 * plls share registers.
1558 struct mutex dpll_lock;
1560 unsigned int active_crtcs;
1561 /* minimum acceptable cdclk for each pipe */
1562 int min_cdclk[I915_MAX_PIPES];
1563 /* minimum acceptable voltage level for each pipe */
1564 u8 min_voltage_level[I915_MAX_PIPES];
1566 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1568 struct i915_wa_list gt_wa_list;
1570 struct i915_frontbuffer_tracking fb_tracking;
1572 struct intel_atomic_helper {
1573 struct llist_head free_list;
1574 struct work_struct free_work;
1579 bool mchbar_need_disable;
1581 struct intel_l3_parity l3_parity;
1585 * Cannot be determined by PCIID. You must always read a register.
1589 /* gen6+ GT PM state */
1590 struct intel_gen6_power_mgmt gt_pm;
1592 /* ilk-only ips/rps state. Everything in here is protected by the global
1593 * mchdev_lock in intel_pm.c */
1594 struct intel_ilk_power_mgmt ips;
1596 struct i915_power_domains power_domains;
1598 struct i915_psr psr;
1600 struct i915_gpu_error gpu_error;
1602 struct drm_i915_gem_object *vlv_pctx;
1604 /* list of fbdev register on this device */
1605 struct intel_fbdev *fbdev;
1606 struct work_struct fbdev_suspend_work;
1608 struct drm_property *broadcast_rgb_property;
1609 struct drm_property *force_audio_property;
1611 /* hda/i915 audio component */
1612 struct i915_audio_component *audio_component;
1613 bool audio_component_registered;
1615 * av_mutex - mutex for audio/video sync
1618 struct mutex av_mutex;
1619 int audio_power_refcount;
1623 struct list_head list;
1624 struct llist_head free_list;
1625 struct work_struct free_work;
1627 /* The hw wants to have a stable context identifier for the
1628 * lifetime of the context (for OA, PASID, faults, etc).
1629 * This is limited in execlists to 21 bits.
1632 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1633 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1634 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1635 struct list_head hw_id_list;
1640 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1641 u32 chv_phy_control;
1643 * Shadows for CHV DPLL_MD regs to keep the state
1644 * checker somewhat working in the presence hardware
1645 * crappiness (can't read out DPLL_MD for pipes B & C).
1647 u32 chv_dpll_md[I915_MAX_PIPES];
1651 bool power_domains_suspended;
1652 struct i915_suspend_saved_registers regfile;
1653 struct vlv_s0ix_state vlv_s0ix_state;
1656 I915_SAGV_UNKNOWN = 0,
1659 I915_SAGV_NOT_CONTROLLED
1664 * Raw watermark latency values:
1665 * in 0.1us units for WM0,
1666 * in 0.5us units for WM1+.
1675 * Raw watermark memory latency values
1676 * for SKL for all 8 levels
1681 /* current hardware state */
1683 struct ilk_wm_values hw;
1684 struct skl_ddb_values skl_hw;
1685 struct vlv_wm_values vlv;
1686 struct g4x_wm_values g4x;
1692 * Should be held around atomic WM register writing; also
1693 * protects * intel_crtc->wm.active and
1694 * cstate->wm.need_postvbl_update.
1696 struct mutex wm_mutex;
1699 * Set during HW readout of watermarks/DDB. Some platforms
1700 * need to know when we're still using BIOS-provided values
1701 * (which we don't fully trust).
1703 bool distrust_bios_wm;
1712 bool symmetric_memory;
1713 enum intel_dram_type {
1722 struct intel_bw_info {
1727 struct drm_private_obj bw_obj;
1729 struct i915_runtime_pm runtime_pm;
1734 struct kobject *metrics_kobj;
1735 struct ctl_table_header *sysctl_header;
1738 * Lock associated with adding/modifying/removing OA configs
1739 * in dev_priv->perf.metrics_idr.
1741 struct mutex metrics_lock;
1744 * List of dynamic configurations, you need to hold
1745 * dev_priv->perf.metrics_lock to access it.
1747 struct idr metrics_idr;
1750 * Lock associated with anything below within this structure
1751 * except exclusive_stream.
1754 struct list_head streams;
1758 * The stream currently using the OA unit. If accessed
1759 * outside a syscall associated to its file
1760 * descriptor, you need to hold
1761 * dev_priv->drm.struct_mutex.
1763 struct i915_perf_stream *exclusive_stream;
1765 struct intel_context *pinned_ctx;
1766 u32 specific_ctx_id;
1767 u32 specific_ctx_id_mask;
1769 struct hrtimer poll_check_timer;
1770 wait_queue_head_t poll_wq;
1774 * For rate limiting any notifications of spurious
1775 * invalid OA reports
1777 struct ratelimit_state spurious_report_rs;
1780 int period_exponent;
1782 struct i915_oa_config test_config;
1785 struct i915_vma *vma;
1792 * Locks reads and writes to all head/tail state
1794 * Consider: the head and tail pointer state
1795 * needs to be read consistently from a hrtimer
1796 * callback (atomic context) and read() fop
1797 * (user context) with tail pointer updates
1798 * happening in atomic context and head updates
1799 * in user context and the (unlikely)
1800 * possibility of read() errors needing to
1801 * reset all head/tail state.
1803 * Note: Contention or performance aren't
1804 * currently a significant concern here
1805 * considering the relatively low frequency of
1806 * hrtimer callbacks (5ms period) and that
1807 * reads typically only happen in response to a
1808 * hrtimer event and likely complete before the
1811 * Note: This lock is not held *while* reading
1812 * and copying data to userspace so the value
1813 * of head observed in htrimer callbacks won't
1814 * represent any partial consumption of data.
1816 spinlock_t ptr_lock;
1819 * One 'aging' tail pointer and one 'aged'
1820 * tail pointer ready to used for reading.
1822 * Initial values of 0xffffffff are invalid
1823 * and imply that an update is required
1824 * (and should be ignored by an attempted
1832 * Index for the aged tail ready to read()
1835 unsigned int aged_tail_idx;
1838 * A monotonic timestamp for when the current
1839 * aging tail pointer was read; used to
1840 * determine when it is old enough to trust.
1842 u64 aging_timestamp;
1845 * Although we can always read back the head
1846 * pointer register, we prefer to avoid
1847 * trusting the HW state, just to avoid any
1848 * risk that some hardware condition could
1849 * somehow bump the head pointer unpredictably
1850 * and cause us to forward the wrong OA buffer
1851 * data to userspace.
1856 u32 gen7_latched_oastatus1;
1857 u32 ctx_oactxctrl_offset;
1858 u32 ctx_flexeu0_offset;
1861 * The RPT_ID/reason field for Gen8+ includes a bit
1862 * to determine if the CTX ID in the report is valid
1863 * but the specific bit differs between Gen 8 and 9
1865 u32 gen8_valid_ctx_bit;
1867 struct i915_oa_ops ops;
1868 const struct i915_oa_format *oa_formats;
1872 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1874 struct i915_gt_timelines {
1875 struct mutex mutex; /* protects list, tainted by GPU */
1876 struct list_head active_list;
1878 /* Pack multiple timelines' seqnos into the same page */
1879 spinlock_t hwsp_lock;
1880 struct list_head hwsp_free_list;
1883 struct list_head active_rings;
1885 struct intel_wakeref wakeref;
1887 struct list_head closed_vma;
1888 spinlock_t closed_lock; /* guards the list of closed_vma */
1891 * Is the GPU currently considered idle, or busy executing
1892 * userspace requests? Whilst idle, we allow runtime power
1893 * management to power down the hardware and display clocks.
1894 * In order to reduce the effect on performance, there
1895 * is a slight delay before we do so.
1897 intel_wakeref_t awake;
1899 struct blocking_notifier_head pm_notifications;
1901 ktime_t last_init_time;
1903 struct i915_vma *scratch;
1907 struct notifier_block pm_notifier;
1910 * We leave the user IRQ off as much as possible,
1911 * but this means that requests will finish and never
1912 * be retired once the system goes idle. Set a timer to
1913 * fire periodically while the ring is running. When it
1914 * fires, go retire requests.
1916 struct delayed_work retire_work;
1919 * When we detect an idle GPU, we want to turn on
1920 * powersaving features. So once we see that there
1921 * are no more requests outstanding and no more
1922 * arrive within a small period of time, we fire
1923 * off the idle_work.
1925 struct work_struct idle_work;
1928 /* For i945gm vblank irq vs. C3 workaround */
1930 struct work_struct work;
1931 struct pm_qos_request pm_qos;
1932 u8 c3_disable_latency;
1936 /* perform PHY state sanity checks? */
1937 bool chv_phy_assert[2];
1941 /* Used to save the pipe-to-encoder mapping for audio */
1942 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1944 /* necessary resource sharing with HDMI LPE audio driver. */
1946 struct platform_device *platdev;
1950 struct i915_pmu pmu;
1952 struct i915_hdcp_comp_master *hdcp_master;
1953 bool hdcp_comp_added;
1955 /* Mutex to protect the above hdcp component related values. */
1956 struct mutex hdcp_comp_mutex;
1959 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1960 * will be rejected. Instead look for a better place.
1964 struct dram_dimm_info {
1965 u8 size, width, ranks;
1968 struct dram_channel_info {
1969 struct dram_dimm_info dimm_l, dimm_s;
1974 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1976 return container_of(dev, struct drm_i915_private, drm);
1979 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1981 return to_i915(dev_get_drvdata(kdev));
1984 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
1986 return container_of(wopcm, struct drm_i915_private, wopcm);
1989 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1991 return container_of(guc, struct drm_i915_private, guc);
1994 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
1996 return container_of(huc, struct drm_i915_private, huc);
1999 static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
2001 return container_of(uncore, struct drm_i915_private, uncore);
2004 /* Simple iterator over all initialised engines */
2005 #define for_each_engine(engine__, dev_priv__, id__) \
2007 (id__) < I915_NUM_ENGINES; \
2009 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2011 /* Iterator over subset of engines selected by mask */
2012 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2013 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
2015 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2018 enum hdmi_force_audio {
2019 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2020 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2021 HDMI_AUDIO_AUTO, /* trust EDID */
2022 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2025 #define I915_GTT_OFFSET_NONE ((u32)-1)
2028 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2029 * considered to be the frontbuffer for the given plane interface-wise. This
2030 * doesn't mean that the hw necessarily already scans it out, but that any
2031 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2033 * We have one bit per pipe and per scanout plane type.
2035 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2036 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2037 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2038 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2039 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2041 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2042 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2043 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2044 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2045 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2047 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
2048 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2049 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2051 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
2052 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2054 #define REVID_FOREVER 0xff
2055 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2057 #define INTEL_GEN_MASK(s, e) ( \
2058 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2059 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2060 GENMASK((e) - 1, (s) - 1))
2062 /* Returns true if Gen is in inclusive range [Start, End] */
2063 #define IS_GEN_RANGE(dev_priv, s, e) \
2064 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2066 #define IS_GEN(dev_priv, n) \
2067 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2068 INTEL_INFO(dev_priv)->gen == (n))
2071 * Return true if revision is in range [since,until] inclusive.
2073 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2075 #define IS_REVID(p, since, until) \
2076 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2078 static __always_inline unsigned int
2079 __platform_mask_index(const struct intel_runtime_info *info,
2080 enum intel_platform p)
2082 const unsigned int pbits =
2083 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2085 /* Expand the platform_mask array if this fails. */
2086 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
2087 pbits * ARRAY_SIZE(info->platform_mask));
2092 static __always_inline unsigned int
2093 __platform_mask_bit(const struct intel_runtime_info *info,
2094 enum intel_platform p)
2096 const unsigned int pbits =
2097 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2099 return p % pbits + INTEL_SUBPLATFORM_BITS;
2103 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
2105 const unsigned int pi = __platform_mask_index(info, p);
2107 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
2110 static __always_inline bool
2111 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
2113 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2114 const unsigned int pi = __platform_mask_index(info, p);
2115 const unsigned int pb = __platform_mask_bit(info, p);
2117 BUILD_BUG_ON(!__builtin_constant_p(p));
2119 return info->platform_mask[pi] & BIT(pb);
2122 static __always_inline bool
2123 IS_SUBPLATFORM(const struct drm_i915_private *i915,
2124 enum intel_platform p, unsigned int s)
2126 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2127 const unsigned int pi = __platform_mask_index(info, p);
2128 const unsigned int pb = __platform_mask_bit(info, p);
2129 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
2130 const u32 mask = info->platform_mask[pi];
2132 BUILD_BUG_ON(!__builtin_constant_p(p));
2133 BUILD_BUG_ON(!__builtin_constant_p(s));
2134 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
2136 /* Shift and test on the MSB position so sign flag can be used. */
2137 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
2140 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
2142 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2143 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2144 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2145 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2146 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2147 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2148 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2149 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2150 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2151 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2152 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2153 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2154 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2155 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2156 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2157 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
2158 #define IS_IRONLAKE_M(dev_priv) \
2159 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
2160 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2161 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2162 INTEL_INFO(dev_priv)->gt == 1)
2163 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2164 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2165 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2166 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2167 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2168 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2169 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2170 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2171 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2172 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2173 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2174 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
2175 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2176 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2177 #define IS_BDW_ULT(dev_priv) \
2178 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
2179 #define IS_BDW_ULX(dev_priv) \
2180 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
2181 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2182 INTEL_INFO(dev_priv)->gt == 3)
2183 #define IS_HSW_ULT(dev_priv) \
2184 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
2185 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2186 INTEL_INFO(dev_priv)->gt == 3)
2187 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2188 INTEL_INFO(dev_priv)->gt == 1)
2189 /* ULX machines are also considered ULT. */
2190 #define IS_HSW_ULX(dev_priv) \
2191 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
2192 #define IS_SKL_ULT(dev_priv) \
2193 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
2194 #define IS_SKL_ULX(dev_priv) \
2195 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
2196 #define IS_KBL_ULT(dev_priv) \
2197 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
2198 #define IS_KBL_ULX(dev_priv) \
2199 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
2200 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2201 INTEL_INFO(dev_priv)->gt == 2)
2202 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2203 INTEL_INFO(dev_priv)->gt == 3)
2204 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2205 INTEL_INFO(dev_priv)->gt == 4)
2206 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2207 INTEL_INFO(dev_priv)->gt == 2)
2208 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2209 INTEL_INFO(dev_priv)->gt == 3)
2210 #define IS_CFL_ULT(dev_priv) \
2211 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2212 #define IS_CFL_ULX(dev_priv) \
2213 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
2214 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2215 INTEL_INFO(dev_priv)->gt == 2)
2216 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2217 INTEL_INFO(dev_priv)->gt == 3)
2218 #define IS_CNL_WITH_PORT_F(dev_priv) \
2219 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2220 #define IS_ICL_WITH_PORT_F(dev_priv) \
2221 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2223 #define SKL_REVID_A0 0x0
2224 #define SKL_REVID_B0 0x1
2225 #define SKL_REVID_C0 0x2
2226 #define SKL_REVID_D0 0x3
2227 #define SKL_REVID_E0 0x4
2228 #define SKL_REVID_F0 0x5
2229 #define SKL_REVID_G0 0x6
2230 #define SKL_REVID_H0 0x7
2232 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2234 #define BXT_REVID_A0 0x0
2235 #define BXT_REVID_A1 0x1
2236 #define BXT_REVID_B0 0x3
2237 #define BXT_REVID_B_LAST 0x8
2238 #define BXT_REVID_C0 0x9
2240 #define IS_BXT_REVID(dev_priv, since, until) \
2241 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2243 #define KBL_REVID_A0 0x0
2244 #define KBL_REVID_B0 0x1
2245 #define KBL_REVID_C0 0x2
2246 #define KBL_REVID_D0 0x3
2247 #define KBL_REVID_E0 0x4
2249 #define IS_KBL_REVID(dev_priv, since, until) \
2250 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2252 #define GLK_REVID_A0 0x0
2253 #define GLK_REVID_A1 0x1
2255 #define IS_GLK_REVID(dev_priv, since, until) \
2256 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2258 #define CNL_REVID_A0 0x0
2259 #define CNL_REVID_B0 0x1
2260 #define CNL_REVID_C0 0x2
2262 #define IS_CNL_REVID(p, since, until) \
2263 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2265 #define ICL_REVID_A0 0x0
2266 #define ICL_REVID_A2 0x1
2267 #define ICL_REVID_B0 0x3
2268 #define ICL_REVID_B2 0x4
2269 #define ICL_REVID_C0 0x5
2271 #define IS_ICL_REVID(p, since, until) \
2272 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2274 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2275 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2276 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2278 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2280 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
2281 unsigned int first__ = (first); \
2282 unsigned int count__ = (count); \
2283 (INTEL_INFO(dev_priv)->engine_mask & \
2284 GENMASK(first__ + count__ - 1, first__)) >> first__; \
2286 #define VDBOX_MASK(dev_priv) \
2287 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2288 #define VEBOX_MASK(dev_priv) \
2289 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2291 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2292 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2293 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
2294 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2295 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2297 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2299 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2300 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2301 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2302 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2303 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2304 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2306 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2308 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2309 #define HAS_PPGTT(dev_priv) \
2310 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2311 #define HAS_FULL_PPGTT(dev_priv) \
2312 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2314 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2315 GEM_BUG_ON((sizes) == 0); \
2316 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2319 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2320 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2321 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2323 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2324 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2326 /* WaRsDisableCoarsePowerGating:skl,cnl */
2327 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2328 (IS_CANNONLAKE(dev_priv) || \
2329 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2331 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2332 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2333 IS_GEMINILAKE(dev_priv) || \
2334 IS_KABYLAKE(dev_priv))
2336 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2337 * rows, which changed the alignment requirements and fence programming.
2339 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2340 !(IS_I915G(dev_priv) || \
2341 IS_I915GM(dev_priv)))
2342 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2343 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2345 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2346 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2347 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2349 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2351 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2353 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2354 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2355 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2356 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2358 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2359 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2360 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2362 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
2364 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2366 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2367 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2369 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2372 * For now, anything with a GuC requires uCode loading, and then supports
2373 * command submission once loaded. But these are logically independent
2374 * properties, so we have separate macros to test them.
2376 #define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
2377 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2378 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2380 /* For now, anything with a GuC has also HuC */
2381 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2382 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2384 /* Having a GuC is not the same as using a GuC */
2385 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2386 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2387 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2389 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2391 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2392 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2393 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2394 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2395 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2396 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2397 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2398 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2399 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2400 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2401 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2402 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2403 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2404 #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
2405 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2406 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2407 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2408 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2410 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2411 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2412 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2413 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2414 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2415 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2416 #define HAS_PCH_LPT_LP(dev_priv) \
2417 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2418 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2419 #define HAS_PCH_LPT_H(dev_priv) \
2420 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2421 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2422 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2423 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2424 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2425 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2427 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2429 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2431 /* DPF == dynamic parity feature */
2432 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2433 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2434 2 : HAS_L3_DPF(dev_priv))
2436 #define GT_FREQUENCY_MULTIPLIER 50
2437 #define GEN9_FREQ_SCALER 3
2439 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2441 #include "i915_trace.h"
2443 static inline bool intel_vtd_active(void)
2445 #ifdef CONFIG_INTEL_IOMMU
2446 if (intel_iommu_gfx_mapped)
2452 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2454 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2458 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2460 return IS_BROXTON(dev_priv) && intel_vtd_active();
2465 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2466 const char *fmt, ...);
2468 #define i915_report_error(dev_priv, fmt, ...) \
2469 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2471 #ifdef CONFIG_COMPAT
2472 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2475 #define i915_compat_ioctl NULL
2477 extern const struct dev_pm_ops i915_pm_ops;
2479 extern int i915_driver_load(struct pci_dev *pdev,
2480 const struct pci_device_id *ent);
2481 extern void i915_driver_unload(struct drm_device *dev);
2483 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2484 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2485 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2487 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2489 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2491 unsigned long delay;
2493 if (unlikely(!i915_modparams.enable_hangcheck))
2496 /* Don't continually defer the hangcheck so that it is always run at
2497 * least once after work has been scheduled on any ring. Otherwise,
2498 * we will ignore a hung ring if a second ring is kept busy.
2501 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2502 queue_delayed_work(system_long_wq,
2503 &dev_priv->gpu_error.hangcheck_work, delay);
2506 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2508 return dev_priv->gvt;
2511 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2513 return dev_priv->vgpu.active;
2517 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2518 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2519 void i915_gem_sanitize(struct drm_i915_private *i915);
2520 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2521 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2522 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2523 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2525 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2527 if (!atomic_read(&i915->mm.free_count))
2530 /* A single pass should suffice to release all the freed objects (along
2531 * most call paths) , but be a little more paranoid in that freeing
2532 * the objects does take a little amount of time, during which the rcu
2533 * callbacks could have added new objects into the freed list, and
2534 * armed the work again.
2538 } while (flush_work(&i915->mm.free_work));
2541 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2544 * Similar to objects above (see i915_gem_drain_freed-objects), in
2545 * general we have workers that are armed by RCU and then rearm
2546 * themselves in their callbacks. To be paranoid, we need to
2547 * drain the workqueue a second time after waiting for the RCU
2548 * grace period so that we catch work queued via RCU from the first
2549 * pass. As neither drain_workqueue() nor flush_workqueue() report
2550 * a result, we make an assumption that we only don't require more
2551 * than 3 passes to catch all _recursive_ RCU delayed work.
2557 i915_gem_drain_freed_objects(i915);
2559 drain_workqueue(i915->wq);
2562 struct i915_vma * __must_check
2563 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2564 const struct i915_ggtt_view *view,
2569 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2571 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2573 static inline int __must_check
2574 i915_mutex_lock_interruptible(struct drm_device *dev)
2576 return mutex_lock_interruptible(&dev->struct_mutex);
2579 int i915_gem_dumb_create(struct drm_file *file_priv,
2580 struct drm_device *dev,
2581 struct drm_mode_create_dumb *args);
2582 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2583 u32 handle, u64 *offset);
2584 int i915_gem_mmap_gtt_version(void);
2586 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2587 struct drm_i915_gem_object *new,
2588 unsigned frontbuffer_bits);
2590 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
2592 static inline bool __i915_wedged(struct i915_gpu_error *error)
2594 return unlikely(test_bit(I915_WEDGED, &error->flags));
2597 static inline bool i915_reset_failed(struct drm_i915_private *i915)
2599 return __i915_wedged(&i915->gpu_error);
2602 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2604 return READ_ONCE(error->reset_count);
2607 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
2608 struct intel_engine_cs *engine)
2610 return READ_ONCE(error->reset_engine_count[engine->id]);
2613 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
2614 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
2616 void i915_gem_init_mmio(struct drm_i915_private *i915);
2617 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
2618 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
2619 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
2620 void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
2621 void i915_gem_fini(struct drm_i915_private *dev_priv);
2622 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
2623 unsigned int flags, long timeout);
2624 void i915_gem_suspend(struct drm_i915_private *dev_priv);
2625 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
2626 void i915_gem_resume(struct drm_i915_private *dev_priv);
2627 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
2629 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
2630 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2632 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2633 enum i915_cache_level cache_level);
2635 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2636 struct dma_buf *dma_buf);
2638 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2639 struct drm_gem_object *gem_obj, int flags);
2641 static inline struct i915_gem_context *
2642 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
2644 return idr_find(&file_priv->context_idr, id);
2647 static inline struct i915_gem_context *
2648 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2650 struct i915_gem_context *ctx;
2653 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
2654 if (ctx && !kref_get_unless_zero(&ctx->ref))
2661 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
2662 struct drm_file *file);
2663 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
2664 struct drm_file *file);
2665 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
2666 struct drm_file *file);
2667 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
2668 struct intel_context *ce,
2671 /* i915_gem_evict.c */
2672 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
2673 u64 min_size, u64 alignment,
2674 unsigned cache_level,
2677 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
2678 struct drm_mm_node *node,
2679 unsigned int flags);
2680 int i915_gem_evict_vm(struct i915_address_space *vm);
2682 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
2684 /* belongs in i915_gem_gtt.h */
2685 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
2688 if (INTEL_GEN(dev_priv) < 6)
2689 intel_gtt_chipset_flush();
2692 /* i915_gem_stolen.c */
2693 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
2694 struct drm_mm_node *node, u64 size,
2695 unsigned alignment);
2696 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
2697 struct drm_mm_node *node, u64 size,
2698 unsigned alignment, u64 start,
2700 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
2701 struct drm_mm_node *node);
2702 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
2703 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
2704 struct drm_i915_gem_object *
2705 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
2706 resource_size_t size);
2707 struct drm_i915_gem_object *
2708 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
2709 resource_size_t stolen_offset,
2710 resource_size_t gtt_offset,
2711 resource_size_t size);
2713 /* i915_gem_internal.c */
2714 struct drm_i915_gem_object *
2715 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2718 /* i915_gem_shrinker.c */
2719 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
2720 unsigned long target,
2721 unsigned long *nr_scanned,
2723 #define I915_SHRINK_UNBOUND BIT(0)
2724 #define I915_SHRINK_BOUND BIT(1)
2725 #define I915_SHRINK_ACTIVE BIT(2)
2726 #define I915_SHRINK_VMAPS BIT(3)
2727 #define I915_SHRINK_WRITEBACK BIT(4)
2729 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
2730 void i915_gem_shrinker_register(struct drm_i915_private *i915);
2731 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
2732 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
2733 struct mutex *mutex);
2735 /* i915_gem_tiling.c */
2736 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2738 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2740 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2741 i915_gem_object_is_tiled(obj);
2744 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2745 unsigned int tiling, unsigned int stride);
2746 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2747 unsigned int tiling, unsigned int stride);
2749 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2751 /* i915_cmd_parser.c */
2752 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2753 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2754 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
2755 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
2756 struct drm_i915_gem_object *batch_obj,
2757 struct drm_i915_gem_object *shadow_batch_obj,
2758 u32 batch_start_offset,
2763 extern void i915_perf_init(struct drm_i915_private *dev_priv);
2764 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
2765 extern void i915_perf_register(struct drm_i915_private *dev_priv);
2766 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
2768 /* i915_suspend.c */
2769 extern int i915_save_state(struct drm_i915_private *dev_priv);
2770 extern int i915_restore_state(struct drm_i915_private *dev_priv);
2773 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
2774 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
2776 /* intel_device_info.c */
2777 static inline struct intel_device_info *
2778 mkwrite_device_info(struct drm_i915_private *dev_priv)
2780 return (struct intel_device_info *)INTEL_INFO(dev_priv);
2784 extern void intel_modeset_init_hw(struct drm_device *dev);
2785 extern int intel_modeset_init(struct drm_device *dev);
2786 extern void intel_modeset_cleanup(struct drm_device *dev);
2787 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
2789 extern void intel_display_resume(struct drm_device *dev);
2790 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
2791 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
2792 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
2794 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2795 struct drm_file *file);
2797 extern struct intel_display_error_state *
2798 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
2799 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2800 struct intel_display_error_state *error);
2802 #define __I915_REG_OP(op__, dev_priv__, ...) \
2803 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2805 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
2806 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2808 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
2810 /* These are untraced mmio-accessors that are only valid to be used inside
2811 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
2814 * Think twice, and think again, before using these.
2816 * As an example, these accessors can possibly be used between:
2818 * spin_lock_irq(&dev_priv->uncore.lock);
2819 * intel_uncore_forcewake_get__locked();
2823 * intel_uncore_forcewake_put__locked();
2824 * spin_unlock_irq(&dev_priv->uncore.lock);
2827 * Note: some registers may not need forcewake held, so
2828 * intel_uncore_forcewake_{get,put} can be omitted, see
2829 * intel_uncore_forcewake_for_reg().
2831 * Certain architectures will die if the same cacheline is concurrently accessed
2832 * by different clients (e.g. on Ivybridge). Access to registers should
2833 * therefore generally be serialised, by either the dev_priv->uncore.lock or
2834 * a more localised lock guarding all access to that bank of registers.
2836 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2837 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2839 /* "Broadcast RGB" property */
2840 #define INTEL_BROADCAST_RGB_AUTO 0
2841 #define INTEL_BROADCAST_RGB_FULL 1
2842 #define INTEL_BROADCAST_RGB_LIMITED 2
2844 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
2845 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
2847 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
2848 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
2849 * perform the operation. To check beforehand, pass in the parameters to
2850 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
2851 * you only need to pass in the minor offsets, page-aligned pointers are
2854 * For just checking for SSE4.1, in the foreknowledge that the future use
2855 * will be correctly aligned, just use i915_has_memcpy_from_wc().
2857 #define i915_can_memcpy_from_wc(dst, src, len) \
2858 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
2860 #define i915_has_memcpy_from_wc() \
2861 i915_memcpy_from_wc(NULL, NULL, 0)
2864 int remap_io_mapping(struct vm_area_struct *vma,
2865 unsigned long addr, unsigned long pfn, unsigned long size,
2866 struct io_mapping *iomap);
2868 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2870 if (INTEL_GEN(i915) >= 10)
2871 return CNL_HWS_CSB_WRITE_INDEX;
2873 return I915_HWS_CSB_WRITE_INDEX;
2876 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
2878 return i915_ggtt_offset(i915->gt.scratch);
2881 static inline enum i915_map_type
2882 i915_coherent_map_type(struct drm_i915_private *i915)
2884 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2887 static inline void add_taint_for_CI(unsigned int taint)
2890 * The system is "ok", just about surviving for the user, but
2891 * CI results are now unreliable as the HW is very suspect.
2892 * CI checks the taint state after every test and will reboot
2893 * the machine if the kernel is tainted.
2895 add_taint(taint, LOCKDEP_STILL_OK);