1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/dma-resv.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_atomic.h>
58 #include <drm/drm_connector.h>
59 #include <drm/i915_mei_hdcp_interface.h>
61 #include "i915_fixed.h"
62 #include "i915_params.h"
64 #include "i915_utils.h"
66 #include "display/intel_bios.h"
67 #include "display/intel_display.h"
68 #include "display/intel_display_power.h"
69 #include "display/intel_dpll_mgr.h"
70 #include "display/intel_dsb.h"
71 #include "display/intel_frontbuffer.h"
72 #include "display/intel_gmbus.h"
73 #include "display/intel_opregion.h"
75 #include "gem/i915_gem_context_types.h"
76 #include "gem/i915_gem_shrinker.h"
77 #include "gem/i915_gem_stolen.h"
79 #include "gt/intel_lrc.h"
80 #include "gt/intel_engine.h"
81 #include "gt/intel_gt_types.h"
82 #include "gt/intel_workarounds.h"
83 #include "gt/uc/intel_uc.h"
85 #include "intel_device_info.h"
86 #include "intel_pch.h"
87 #include "intel_runtime_pm.h"
88 #include "intel_memory_region.h"
89 #include "intel_uncore.h"
90 #include "intel_wakeref.h"
91 #include "intel_wopcm.h"
94 #include "i915_gem_fence_reg.h"
95 #include "i915_gem_gtt.h"
96 #include "i915_gpu_error.h"
97 #include "i915_perf_types.h"
98 #include "i915_request.h"
99 #include "i915_scheduler.h"
100 #include "gt/intel_timeline.h"
101 #include "i915_vma.h"
102 #include "i915_irq.h"
104 #include "intel_region_lmem.h"
106 #include "intel_gvt.h"
108 /* General customization:
111 #define DRIVER_NAME "i915"
112 #define DRIVER_DESC "Intel Graphics"
113 #define DRIVER_DATE "20191101"
114 #define DRIVER_TIMESTAMP 1572604873
116 struct drm_i915_gem_object;
120 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
137 #define for_each_hpd_pin(__pin) \
138 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
140 /* Threshold == 5 for long IRQs, 50 for short */
141 #define HPD_STORM_DEFAULT_THRESHOLD 50
143 struct i915_hotplug {
144 struct delayed_work hotplug_work;
147 unsigned long last_jiffies;
152 HPD_MARK_DISABLED = 2
154 } stats[HPD_NUM_PINS];
157 struct delayed_work reenable_work;
161 struct work_struct dig_port_work;
163 struct work_struct poll_init_work;
166 unsigned int hpd_storm_threshold;
167 /* Whether or not to count short HPD IRQs in HPD storms */
168 u8 hpd_short_storm_enabled;
171 * if we get a HPD irq from DP and a HPD irq from non-DP
172 * the non-DP HPD could block the workqueue on a mode config
173 * mutex getting, that userspace may have taken. However
174 * userspace is waiting on the DP workqueue to run which is
175 * blocked behind the non-DP one.
177 struct workqueue_struct *dp_wq;
180 #define I915_GEM_GPU_DOMAINS \
181 (I915_GEM_DOMAIN_RENDER | \
182 I915_GEM_DOMAIN_SAMPLER | \
183 I915_GEM_DOMAIN_COMMAND | \
184 I915_GEM_DOMAIN_INSTRUCTION | \
185 I915_GEM_DOMAIN_VERTEX)
187 struct drm_i915_private;
188 struct i915_mm_struct;
189 struct i915_mmu_object;
191 struct drm_i915_file_private {
192 struct drm_i915_private *dev_priv;
195 struct drm_file *file;
201 struct list_head request_list;
204 struct idr context_idr;
205 struct mutex context_idr_lock; /* guards context_idr */
208 struct mutex vm_idr_lock; /* guards vm_idr */
210 unsigned int bsd_engine;
213 * Every context ban increments per client ban score. Also
214 * hangs in short succession increments ban score. If ban threshold
215 * is reached, client is considered banned and submitting more work
216 * will fail. This is a stop gap measure to limit the badly behaving
217 * clients access to gpu. Note that unbannable contexts never increment
218 * the client ban score.
220 #define I915_CLIENT_SCORE_HANG_FAST 1
221 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
222 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
223 #define I915_CLIENT_SCORE_BANNED 9
224 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
226 unsigned long hang_timestamp;
229 /* Interface history:
232 * 1.2: Add Power Management
233 * 1.3: Add vblank support
234 * 1.4: Fix cmdbuffer path, add heap destroy
235 * 1.5: Add vblank pipe configuration
236 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
237 * - Support vertical blank on secondary display pipe
239 #define DRIVER_MAJOR 1
240 #define DRIVER_MINOR 6
241 #define DRIVER_PATCHLEVEL 0
243 struct intel_overlay;
244 struct intel_overlay_error_state;
246 struct sdvo_device_mapping {
255 struct intel_connector;
256 struct intel_encoder;
257 struct intel_atomic_state;
258 struct intel_crtc_state;
259 struct intel_initial_plane_config;
263 struct intel_cdclk_state;
265 struct drm_i915_display_funcs {
266 void (*get_cdclk)(struct drm_i915_private *dev_priv,
267 struct intel_cdclk_state *cdclk_state);
268 void (*set_cdclk)(struct drm_i915_private *dev_priv,
269 const struct intel_cdclk_state *cdclk_state,
271 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
272 enum i9xx_plane_id i9xx_plane);
273 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
274 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
275 void (*initial_watermarks)(struct intel_atomic_state *state,
276 struct intel_crtc *crtc);
277 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
278 struct intel_crtc *crtc);
279 void (*optimize_watermarks)(struct intel_atomic_state *state,
280 struct intel_crtc *crtc);
281 int (*compute_global_watermarks)(struct intel_atomic_state *state);
282 void (*update_wm)(struct intel_crtc *crtc);
283 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
284 u8 (*calc_voltage_level)(int cdclk);
285 /* Returns the active state of the crtc, and if the crtc is active,
286 * fills out the pipe-config with the hw state. */
287 bool (*get_pipe_config)(struct intel_crtc *,
288 struct intel_crtc_state *);
289 void (*get_initial_plane_config)(struct intel_crtc *,
290 struct intel_initial_plane_config *);
291 int (*crtc_compute_clock)(struct intel_crtc *crtc,
292 struct intel_crtc_state *crtc_state);
293 void (*crtc_enable)(struct intel_atomic_state *state,
294 struct intel_crtc *crtc);
295 void (*crtc_disable)(struct intel_atomic_state *state,
296 struct intel_crtc *crtc);
297 void (*commit_modeset_enables)(struct intel_atomic_state *state);
298 void (*commit_modeset_disables)(struct intel_atomic_state *state);
299 void (*audio_codec_enable)(struct intel_encoder *encoder,
300 const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 void (*audio_codec_disable)(struct intel_encoder *encoder,
303 const struct intel_crtc_state *old_crtc_state,
304 const struct drm_connector_state *old_conn_state);
305 void (*fdi_link_train)(struct intel_crtc *crtc,
306 const struct intel_crtc_state *crtc_state);
307 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
308 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
309 /* clock updates for mode set */
311 /* render clock increase/decrease */
312 /* display clock increase/decrease */
313 /* pll clock increase/decrease */
315 int (*color_check)(struct intel_crtc_state *crtc_state);
317 * Program double buffered color management registers during
318 * vblank evasion. The registers should then latch during the
319 * next vblank start, alongside any other double buffered registers
320 * involved with the same commit.
322 void (*color_commit)(const struct intel_crtc_state *crtc_state);
324 * Load LUTs (and other single buffered color management
325 * registers). Will (hopefully) be called during the vblank
326 * following the latching of any double buffered registers
327 * involved with the same commit.
329 void (*load_luts)(const struct intel_crtc_state *crtc_state);
330 void (*read_luts)(struct intel_crtc_state *crtc_state);
334 struct work_struct work;
336 u32 required_version;
337 u32 max_fw_size; /* bytes */
339 u32 dmc_fw_size; /* dwords */
342 i915_reg_t mmioaddr[20];
347 intel_wakeref_t wakeref;
350 enum i915_cache_level {
352 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
353 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
354 caches, eg sampler/render caches, and the
355 large Last-Level-Cache. LLC is coherent with
356 the CPU, but L3 is only visible to the GPU. */
357 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
360 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
363 /* This is always the inner lock when overlapping with struct_mutex and
364 * it's the outer lock when overlapping with stolen_lock. */
367 unsigned int possible_framebuffer_bits;
368 unsigned int busy_bits;
369 struct intel_crtc *crtc;
371 struct drm_mm_node compressed_fb;
372 struct drm_mm_node *compressed_llb;
380 bool underrun_detected;
381 struct work_struct underrun_work;
384 * Due to the atomic rules we can't access some structures without the
385 * appropriate locking, so we cache information here in order to avoid
388 struct intel_fbc_state_cache {
390 unsigned int mode_flags;
391 u32 hsw_bdw_pixel_rate;
395 unsigned int rotation;
400 * Display surface base address adjustement for
401 * pageflips. Note that on gen4+ this only adjusts up
402 * to a tile, offsets within a tile are handled in
403 * the hw itself (with the TILEOFF register).
410 u16 pixel_blend_mode;
414 const struct drm_format_info *format;
417 u16 gen9_wa_cfb_stride;
422 * This structure contains everything that's relevant to program the
423 * hardware registers. When we want to figure out if we need to disable
424 * and re-enable FBC for a new configuration we just check if there's
425 * something different in the struct. The genx_fbc_activate functions
426 * are supposed to read from it in order to program the registers.
428 struct intel_fbc_reg_params {
431 enum i9xx_plane_id i9xx_plane;
432 unsigned int fence_y_offset;
436 const struct drm_format_info *format;
441 u16 gen9_wa_cfb_stride;
446 const char *no_fbc_reason;
450 * HIGH_RR is the highest eDP panel refresh rate read from EDID
451 * LOW_RR is the lowest eDP panel refresh rate found from EDID
452 * parsing for same resolution.
454 enum drrs_refresh_rate_type {
457 DRRS_MAX_RR, /* RR count */
460 enum drrs_support_type {
461 DRRS_NOT_SUPPORTED = 0,
462 STATIC_DRRS_SUPPORT = 1,
463 SEAMLESS_DRRS_SUPPORT = 2
469 struct delayed_work work;
471 unsigned busy_frontbuffer_bits;
472 enum drrs_refresh_rate_type refresh_rate_type;
473 enum drrs_support_type type;
479 #define I915_PSR_DEBUG_MODE_MASK 0x0f
480 #define I915_PSR_DEBUG_DEFAULT 0x00
481 #define I915_PSR_DEBUG_DISABLE 0x01
482 #define I915_PSR_DEBUG_ENABLE 0x02
483 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
484 #define I915_PSR_DEBUG_IRQ 0x10
491 enum transcoder transcoder;
493 struct work_struct work;
494 unsigned busy_frontbuffer_bits;
495 bool sink_psr2_support;
497 bool colorimetry_support;
499 u8 sink_sync_latency;
500 ktime_t last_entry_attempt;
502 bool sink_not_reliable;
504 u16 su_x_granularity;
506 u32 dc3co_exit_delay;
507 struct delayed_work idle_work;
510 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
511 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
512 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
513 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
514 #define QUIRK_INCREASE_T12_DELAY (1<<6)
515 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
518 struct intel_fbc_work;
521 struct i2c_adapter adapter;
522 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
526 struct i2c_algo_bit_data bit_algo;
527 struct drm_i915_private *dev_priv;
530 struct i915_suspend_saved_registers {
533 u32 saveCACHE_MODE_0;
534 u32 saveMI_ARB_STATE;
538 u64 saveFENCE[I915_MAX_NUM_FENCES];
539 u32 savePCH_PORT_HOTPLUG;
543 struct vlv_s0ix_state;
545 #define MAX_L3_SLICES 2
546 struct intel_l3_parity {
547 u32 *remap_info[MAX_L3_SLICES];
548 struct work_struct error_work;
553 /** Memory allocator for GTT stolen memory */
554 struct drm_mm stolen;
555 /** Protects the usage of the GTT stolen memory allocator. This is
556 * always the inner lock when overlapping with struct_mutex. */
557 struct mutex stolen_lock;
559 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
563 * List of objects which are purgeable.
565 struct list_head purge_list;
568 * List of objects which have allocated pages and are shrinkable.
570 struct list_head shrink_list;
573 * List of objects which are pending destruction.
575 struct llist_head free_list;
576 struct work_struct free_work;
578 * Count of objects pending destructions. Used to skip needlessly
579 * waiting on an RCU barrier if no objects are waiting to be freed.
584 * Small stash of WC pages
586 struct pagestash wc_stash;
589 * tmpfs instance used for shmem backed objects
591 struct vfsmount *gemfs;
593 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
595 struct notifier_block oom_notifier;
596 struct notifier_block vmap_notifier;
597 struct shrinker shrinker;
600 * Workqueue to fault in userptr pages, flushed by the execbuf
601 * when required but otherwise left to userspace to try again
604 struct workqueue_struct *userptr_wq;
606 /* shrinker accounting, also useful for userland debugging */
611 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
613 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
614 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
616 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
617 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
619 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
621 /* Amount of SAGV/QGV points, BSpec precisely defines this */
622 #define I915_NUM_QGV_POINTS 8
624 struct ddi_vbt_port_info {
625 /* Non-NULL if port present. */
626 const struct child_device_config *child;
630 /* This is an index in the HDMI/DVI DDI buffer translation table. */
632 u8 hdmi_level_shift_set:1;
638 u8 supports_typec_usb:1;
641 u8 alternate_aux_channel;
642 u8 alternate_ddc_pin;
646 int dp_max_link_rate; /* 0 for not limited by VBT */
649 enum psr_lines_to_wait {
650 PSR_0_LINES_TO_WAIT = 0,
656 struct intel_vbt_data {
657 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
658 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
661 unsigned int int_tv_support:1;
662 unsigned int lvds_dither:1;
663 unsigned int int_crt_support:1;
664 unsigned int lvds_use_ssc:1;
665 unsigned int int_lvds_support:1;
666 unsigned int display_clock_mode:1;
667 unsigned int fdi_rx_polarity_inverted:1;
668 unsigned int panel_type:4;
670 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
671 enum drm_panel_orientation orientation;
673 enum drrs_support_type drrs_type;
683 struct edp_power_seq pps;
689 bool require_aux_wakeup;
691 enum psr_lines_to_wait lines_to_wait;
692 int tp1_wakeup_time_us;
693 int tp2_tp3_wakeup_time_us;
694 int psr2_tp2_tp3_wakeup_time_us;
701 u8 min_brightness; /* min_brightness/255 of max */
702 u8 controller; /* brightness controller number */
703 enum intel_backlight_type type;
709 struct mipi_config *config;
710 struct mipi_pps_data *pps;
716 const u8 *sequence[MIPI_SEQ_MAX];
717 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
718 enum drm_panel_orientation orientation;
723 struct list_head display_devices;
725 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
726 struct sdvo_device_mapping sdvo_mappings[2];
729 enum intel_ddb_partitioning {
731 INTEL_DDB_PART_5_6, /* IVB+ */
734 struct intel_wm_level {
742 struct ilk_wm_values {
748 enum intel_ddb_partitioning partitioning;
752 u16 plane[I915_MAX_PLANES];
762 struct vlv_wm_ddl_values {
763 u8 plane[I915_MAX_PLANES];
766 struct vlv_wm_values {
767 struct g4x_pipe_wm pipe[3];
769 struct vlv_wm_ddl_values ddl[3];
774 struct g4x_wm_values {
775 struct g4x_pipe_wm pipe[2];
777 struct g4x_sr_wm hpll;
783 struct skl_ddb_entry {
784 u16 start, end; /* in number of blocks, 'end' is exclusive */
787 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
789 return entry->end - entry->start;
792 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
793 const struct skl_ddb_entry *e2)
795 if (e1->start == e2->start && e1->end == e2->end)
801 struct skl_ddb_allocation {
802 u8 enabled_slices; /* GEN11 has configurable 2 slices */
805 struct skl_ddb_values {
806 unsigned dirty_pipes;
807 struct skl_ddb_allocation ddb;
810 struct skl_wm_level {
818 /* Stores plane specific WM parameters */
819 struct skl_wm_params {
820 bool x_tiled, y_tiled;
825 u32 plane_pixel_rate;
827 u32 plane_bytes_per_line;
828 uint_fixed_16_16_t plane_blocks_per_line;
829 uint_fixed_16_16_t y_tile_minimum;
834 enum intel_pipe_crc_source {
835 INTEL_PIPE_CRC_SOURCE_NONE,
836 INTEL_PIPE_CRC_SOURCE_PLANE1,
837 INTEL_PIPE_CRC_SOURCE_PLANE2,
838 INTEL_PIPE_CRC_SOURCE_PLANE3,
839 INTEL_PIPE_CRC_SOURCE_PLANE4,
840 INTEL_PIPE_CRC_SOURCE_PLANE5,
841 INTEL_PIPE_CRC_SOURCE_PLANE6,
842 INTEL_PIPE_CRC_SOURCE_PLANE7,
843 INTEL_PIPE_CRC_SOURCE_PIPE,
844 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
845 INTEL_PIPE_CRC_SOURCE_TV,
846 INTEL_PIPE_CRC_SOURCE_DP_B,
847 INTEL_PIPE_CRC_SOURCE_DP_C,
848 INTEL_PIPE_CRC_SOURCE_DP_D,
849 INTEL_PIPE_CRC_SOURCE_AUTO,
850 INTEL_PIPE_CRC_SOURCE_MAX,
853 #define INTEL_PIPE_CRC_ENTRIES_NR 128
854 struct intel_pipe_crc {
857 enum intel_pipe_crc_source source;
860 struct i915_frontbuffer_tracking {
864 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
871 struct i915_virtual_gpu {
872 struct mutex lock; /* serialises sending of g2v_notify command pkts */
877 /* used in computing the new watermarks state */
878 struct intel_wm_config {
879 unsigned int num_pipes_active;
880 bool sprites_enabled;
884 struct intel_cdclk_state {
885 unsigned int cdclk, vco, ref, bypass;
889 struct i915_selftest_stash {
893 struct drm_i915_private {
894 struct drm_device drm;
896 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
897 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
898 struct intel_driver_caps caps;
901 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
902 * end of stolen which we can optionally use to create GEM objects
903 * backed by stolen memory. Note that stolen_usable_size tells us
904 * exactly how much of this we are actually allowed to use, given that
905 * some portion of it is in fact reserved for use by hardware functions.
909 * Reseved portion of Data Stolen Memory
911 struct resource dsm_reserved;
914 * Stolen memory is segmented in hardware with different portions
915 * offlimits to certain functions.
917 * The drm_mm is initialised to the total accessible range, as found
918 * from the PCI config. On Broadwell+, this is further restricted to
919 * avoid the first page! The upper end of stolen memory is reserved for
920 * hardware functions and similarly removed from the accessible range.
922 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
924 struct intel_uncore uncore;
925 struct intel_uncore_mmio_debug mmio_debug;
927 struct i915_virtual_gpu vgpu;
929 struct intel_gvt *gvt;
931 struct intel_wopcm wopcm;
933 struct intel_csr csr;
935 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
937 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
938 * controller on different i2c buses. */
939 struct mutex gmbus_mutex;
942 * Base address of where the gmbus and gpio blocks are located (either
943 * on PCH or on SoC for platforms without PCH).
947 u32 hsw_psr_mmio_adjust;
949 /* MMIO base address for MIPI regs */
954 wait_queue_head_t gmbus_wait_queue;
956 struct pci_dev *bridge_dev;
958 /* Context used internally to idle the GPU and setup initial state */
959 struct i915_gem_context *kernel_context;
961 struct intel_engine_cs *engine[I915_NUM_ENGINES];
962 struct rb_root uabi_engines;
964 struct resource mch_res;
966 /* protects the irq masks */
969 bool display_irqs_enabled;
971 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
972 struct pm_qos_request pm_qos;
974 /* Sideband mailbox protection */
975 struct mutex sb_lock;
976 struct pm_qos_request sb_qos;
978 /** Cached value of IMR to avoid reads in updating the bitfield */
981 u32 de_irq_mask[I915_MAX_PIPES];
983 u32 pipestat_irq_mask[I915_MAX_PIPES];
985 struct i915_hotplug hotplug;
986 struct intel_fbc fbc;
987 struct i915_drrs drrs;
988 struct intel_opregion opregion;
989 struct intel_vbt_data vbt;
991 bool preserve_bios_swizzle;
994 struct intel_overlay *overlay;
996 /* backlight registers and fields in struct intel_panel */
997 struct mutex backlight_lock;
999 /* protects panel power sequencer state */
1000 struct mutex pps_mutex;
1002 unsigned int fsb_freq, mem_freq, is_ddr3;
1003 unsigned int skl_preferred_vco_freq;
1004 unsigned int max_cdclk_freq;
1006 unsigned int max_dotclk_freq;
1007 unsigned int rawclk_freq;
1008 unsigned int hpll_freq;
1009 unsigned int fdi_pll_freq;
1010 unsigned int czclk_freq;
1013 * For reading holding any crtc lock is sufficient,
1014 * for writing must hold all of them.
1018 * The current logical cdclk state.
1019 * See intel_atomic_state.cdclk.logical
1021 struct intel_cdclk_state logical;
1023 * The current actual cdclk state.
1024 * See intel_atomic_state.cdclk.actual
1026 struct intel_cdclk_state actual;
1027 /* The current hardware cdclk state */
1028 struct intel_cdclk_state hw;
1030 /* cdclk, divider, and ratio table from bspec */
1031 const struct intel_cdclk_vals *table;
1033 int force_min_cdclk;
1037 * wq - Driver workqueue for GEM.
1039 * NOTE: Work items scheduled here are not allowed to grab any modeset
1040 * locks, for otherwise the flushing done in the pageflip code will
1041 * result in deadlocks.
1043 struct workqueue_struct *wq;
1045 /* ordered wq for modesets */
1046 struct workqueue_struct *modeset_wq;
1047 /* unbound hipri wq for page flips/plane updates */
1048 struct workqueue_struct *flip_wq;
1050 /* Display functions */
1051 struct drm_i915_display_funcs display;
1053 /* PCH chipset type */
1054 enum intel_pch pch_type;
1055 unsigned short pch_id;
1057 unsigned long quirks;
1059 struct drm_atomic_state *modeset_restore_state;
1060 struct drm_modeset_acquire_ctx reset_ctx;
1062 struct i915_ggtt ggtt; /* VM representing the global address space */
1064 struct i915_gem_mm mm;
1065 DECLARE_HASHTABLE(mm_structs, 7);
1066 struct mutex mm_lock;
1068 /* Kernel Modesetting */
1070 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1071 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1073 #ifdef CONFIG_DEBUG_FS
1074 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1077 /* dpll and cdclk state is protected by connection_mutex */
1078 int num_shared_dpll;
1079 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1080 const struct intel_dpll_mgr *dpll_mgr;
1083 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1084 * Must be global rather than per dpll, because on some platforms
1085 * plls share registers.
1087 struct mutex dpll_lock;
1090 * For reading active_pipes, min_cdclk, min_voltage_level holding
1091 * any crtc lock is sufficient, for writing must hold all of them.
1094 /* minimum acceptable cdclk for each pipe */
1095 int min_cdclk[I915_MAX_PIPES];
1096 /* minimum acceptable voltage level for each pipe */
1097 u8 min_voltage_level[I915_MAX_PIPES];
1099 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1101 struct i915_wa_list gt_wa_list;
1103 struct i915_frontbuffer_tracking fb_tracking;
1105 struct intel_atomic_helper {
1106 struct llist_head free_list;
1107 struct work_struct free_work;
1112 bool mchbar_need_disable;
1114 struct intel_l3_parity l3_parity;
1118 * Cannot be determined by PCIID. You must always read a register.
1122 struct i915_power_domains power_domains;
1124 struct i915_psr psr;
1126 struct i915_gpu_error gpu_error;
1128 struct drm_i915_gem_object *vlv_pctx;
1130 /* list of fbdev register on this device */
1131 struct intel_fbdev *fbdev;
1132 struct work_struct fbdev_suspend_work;
1134 struct drm_property *broadcast_rgb_property;
1135 struct drm_property *force_audio_property;
1137 /* hda/i915 audio component */
1138 struct i915_audio_component *audio_component;
1139 bool audio_component_registered;
1141 * av_mutex - mutex for audio/video sync
1144 struct mutex av_mutex;
1145 int audio_power_refcount;
1146 u32 audio_freq_cntrl;
1150 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1151 u32 chv_phy_control;
1153 * Shadows for CHV DPLL_MD regs to keep the state
1154 * checker somewhat working in the presence hardware
1155 * crappiness (can't read out DPLL_MD for pipes B & C).
1157 u32 chv_dpll_md[I915_MAX_PIPES];
1161 bool power_domains_suspended;
1162 struct i915_suspend_saved_registers regfile;
1163 struct vlv_s0ix_state *vlv_s0ix_state;
1166 I915_SAGV_UNKNOWN = 0,
1169 I915_SAGV_NOT_CONTROLLED
1172 u32 sagv_block_time_us;
1176 * Raw watermark latency values:
1177 * in 0.1us units for WM0,
1178 * in 0.5us units for WM1+.
1187 * Raw watermark memory latency values
1188 * for SKL for all 8 levels
1193 /* current hardware state */
1195 struct ilk_wm_values hw;
1196 struct skl_ddb_values skl_hw;
1197 struct vlv_wm_values vlv;
1198 struct g4x_wm_values g4x;
1204 * Should be held around atomic WM register writing; also
1205 * protects * intel_crtc->wm.active and
1206 * crtc_state->wm.need_postvbl_update.
1208 struct mutex wm_mutex;
1211 * Set during HW readout of watermarks/DDB. Some platforms
1212 * need to know when we're still using BIOS-provided values
1213 * (which we don't fully trust).
1215 bool distrust_bios_wm;
1224 bool symmetric_memory;
1225 enum intel_dram_type {
1234 struct intel_bw_info {
1235 /* for each QGV point */
1236 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1241 struct drm_private_obj bw_obj;
1243 struct intel_runtime_pm runtime_pm;
1245 struct i915_perf perf;
1247 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1251 struct i915_gem_contexts {
1252 spinlock_t lock; /* locks list */
1253 struct list_head list;
1255 struct llist_head free_list;
1256 struct work_struct free_work;
1262 /* For i915gm/i945gm vblank irq workaround */
1265 /* perform PHY state sanity checks? */
1266 bool chv_phy_assert[2];
1270 /* Used to save the pipe-to-encoder mapping for audio */
1271 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1273 /* necessary resource sharing with HDMI LPE audio driver. */
1275 struct platform_device *platdev;
1279 struct i915_pmu pmu;
1281 struct i915_hdcp_comp_master *hdcp_master;
1282 bool hdcp_comp_added;
1284 /* Mutex to protect the above hdcp component related values. */
1285 struct mutex hdcp_comp_mutex;
1287 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1290 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1291 * will be rejected. Instead look for a better place.
1295 struct dram_dimm_info {
1296 u8 size, width, ranks;
1299 struct dram_channel_info {
1300 struct dram_dimm_info dimm_l, dimm_s;
1305 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1307 return container_of(dev, struct drm_i915_private, drm);
1310 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1312 return dev_get_drvdata(kdev);
1315 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1317 return pci_get_drvdata(pdev);
1320 /* Simple iterator over all initialised engines */
1321 #define for_each_engine(engine__, dev_priv__, id__) \
1323 (id__) < I915_NUM_ENGINES; \
1325 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1327 /* Iterator over subset of engines selected by mask */
1328 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1329 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1331 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1334 #define rb_to_uabi_engine(rb) \
1335 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1337 #define for_each_uabi_engine(engine__, i915__) \
1338 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1340 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1342 #define I915_GTT_OFFSET_NONE ((u32)-1)
1345 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1346 * considered to be the frontbuffer for the given plane interface-wise. This
1347 * doesn't mean that the hw necessarily already scans it out, but that any
1348 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1350 * We have one bit per pipe and per scanout plane type.
1352 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1353 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1354 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1355 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1356 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1358 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1359 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1360 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1361 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1362 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1364 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1365 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1366 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1368 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
1369 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1371 #define REVID_FOREVER 0xff
1372 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
1374 #define INTEL_GEN_MASK(s, e) ( \
1375 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1376 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1377 GENMASK((e) - 1, (s) - 1))
1379 /* Returns true if Gen is in inclusive range [Start, End] */
1380 #define IS_GEN_RANGE(dev_priv, s, e) \
1381 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1383 #define IS_GEN(dev_priv, n) \
1384 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1385 INTEL_INFO(dev_priv)->gen == (n))
1387 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1390 * Return true if revision is in range [since,until] inclusive.
1392 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1394 #define IS_REVID(p, since, until) \
1395 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1397 static __always_inline unsigned int
1398 __platform_mask_index(const struct intel_runtime_info *info,
1399 enum intel_platform p)
1401 const unsigned int pbits =
1402 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1404 /* Expand the platform_mask array if this fails. */
1405 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1406 pbits * ARRAY_SIZE(info->platform_mask));
1411 static __always_inline unsigned int
1412 __platform_mask_bit(const struct intel_runtime_info *info,
1413 enum intel_platform p)
1415 const unsigned int pbits =
1416 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1418 return p % pbits + INTEL_SUBPLATFORM_BITS;
1422 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1424 const unsigned int pi = __platform_mask_index(info, p);
1426 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1429 static __always_inline bool
1430 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1432 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1433 const unsigned int pi = __platform_mask_index(info, p);
1434 const unsigned int pb = __platform_mask_bit(info, p);
1436 BUILD_BUG_ON(!__builtin_constant_p(p));
1438 return info->platform_mask[pi] & BIT(pb);
1441 static __always_inline bool
1442 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1443 enum intel_platform p, unsigned int s)
1445 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1446 const unsigned int pi = __platform_mask_index(info, p);
1447 const unsigned int pb = __platform_mask_bit(info, p);
1448 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1449 const u32 mask = info->platform_mask[pi];
1451 BUILD_BUG_ON(!__builtin_constant_p(p));
1452 BUILD_BUG_ON(!__builtin_constant_p(s));
1453 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1455 /* Shift and test on the MSB position so sign flag can be used. */
1456 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1459 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1460 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1462 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1463 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1464 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1465 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1466 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1467 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1468 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1469 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1470 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1471 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1472 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1473 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1474 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1475 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1476 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1477 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1478 #define IS_IRONLAKE_M(dev_priv) \
1479 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1480 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1481 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1482 INTEL_INFO(dev_priv)->gt == 1)
1483 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1484 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1485 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1486 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1487 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1488 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1489 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1490 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1491 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1492 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1493 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1494 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1495 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1496 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1497 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1498 #define IS_BDW_ULT(dev_priv) \
1499 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1500 #define IS_BDW_ULX(dev_priv) \
1501 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1502 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1503 INTEL_INFO(dev_priv)->gt == 3)
1504 #define IS_HSW_ULT(dev_priv) \
1505 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1506 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1507 INTEL_INFO(dev_priv)->gt == 3)
1508 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1509 INTEL_INFO(dev_priv)->gt == 1)
1510 /* ULX machines are also considered ULT. */
1511 #define IS_HSW_ULX(dev_priv) \
1512 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1513 #define IS_SKL_ULT(dev_priv) \
1514 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1515 #define IS_SKL_ULX(dev_priv) \
1516 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1517 #define IS_KBL_ULT(dev_priv) \
1518 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1519 #define IS_KBL_ULX(dev_priv) \
1520 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1521 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1522 INTEL_INFO(dev_priv)->gt == 2)
1523 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1524 INTEL_INFO(dev_priv)->gt == 3)
1525 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1526 INTEL_INFO(dev_priv)->gt == 4)
1527 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1528 INTEL_INFO(dev_priv)->gt == 2)
1529 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1530 INTEL_INFO(dev_priv)->gt == 3)
1531 #define IS_CFL_ULT(dev_priv) \
1532 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1533 #define IS_CFL_ULX(dev_priv) \
1534 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1535 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1536 INTEL_INFO(dev_priv)->gt == 2)
1537 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1538 INTEL_INFO(dev_priv)->gt == 3)
1539 #define IS_CNL_WITH_PORT_F(dev_priv) \
1540 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1541 #define IS_ICL_WITH_PORT_F(dev_priv) \
1542 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1544 #define SKL_REVID_A0 0x0
1545 #define SKL_REVID_B0 0x1
1546 #define SKL_REVID_C0 0x2
1547 #define SKL_REVID_D0 0x3
1548 #define SKL_REVID_E0 0x4
1549 #define SKL_REVID_F0 0x5
1550 #define SKL_REVID_G0 0x6
1551 #define SKL_REVID_H0 0x7
1553 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1555 #define BXT_REVID_A0 0x0
1556 #define BXT_REVID_A1 0x1
1557 #define BXT_REVID_B0 0x3
1558 #define BXT_REVID_B_LAST 0x8
1559 #define BXT_REVID_C0 0x9
1561 #define IS_BXT_REVID(dev_priv, since, until) \
1562 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1564 #define KBL_REVID_A0 0x0
1565 #define KBL_REVID_B0 0x1
1566 #define KBL_REVID_C0 0x2
1567 #define KBL_REVID_D0 0x3
1568 #define KBL_REVID_E0 0x4
1570 #define IS_KBL_REVID(dev_priv, since, until) \
1571 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1573 #define GLK_REVID_A0 0x0
1574 #define GLK_REVID_A1 0x1
1576 #define IS_GLK_REVID(dev_priv, since, until) \
1577 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1579 #define CNL_REVID_A0 0x0
1580 #define CNL_REVID_B0 0x1
1581 #define CNL_REVID_C0 0x2
1583 #define IS_CNL_REVID(p, since, until) \
1584 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1586 #define ICL_REVID_A0 0x0
1587 #define ICL_REVID_A2 0x1
1588 #define ICL_REVID_B0 0x3
1589 #define ICL_REVID_B2 0x4
1590 #define ICL_REVID_C0 0x5
1592 #define IS_ICL_REVID(p, since, until) \
1593 (IS_ICELAKE(p) && IS_REVID(p, since, until))
1595 #define TGL_REVID_A0 0x0
1597 #define IS_TGL_REVID(p, since, until) \
1598 (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1600 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1601 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1602 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1604 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1606 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
1607 unsigned int first__ = (first); \
1608 unsigned int count__ = (count); \
1609 (INTEL_INFO(dev_priv)->engine_mask & \
1610 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1612 #define VDBOX_MASK(dev_priv) \
1613 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1614 #define VEBOX_MASK(dev_priv) \
1615 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1618 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1619 * All later gens can run the final buffer from the ppgtt
1621 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1623 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1624 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1625 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1626 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1627 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
1628 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1630 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1632 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1633 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1634 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1635 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1636 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1637 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1639 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1641 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1642 #define HAS_PPGTT(dev_priv) \
1643 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1644 #define HAS_FULL_PPGTT(dev_priv) \
1645 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1647 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1648 GEM_BUG_ON((sizes) == 0); \
1649 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1652 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1653 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1654 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1656 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1657 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1659 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1660 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1662 /* WaRsDisableCoarsePowerGating:skl,cnl */
1663 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1664 IS_GEN_RANGE(dev_priv, 9, 10)
1666 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1667 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1668 IS_GEMINILAKE(dev_priv) || \
1669 IS_KABYLAKE(dev_priv))
1671 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1672 * rows, which changed the alignment requirements and fence programming.
1674 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1675 !(IS_I915G(dev_priv) || \
1676 IS_I915GM(dev_priv)))
1677 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1678 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1680 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
1681 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1682 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1684 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1686 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1688 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1689 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1690 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1691 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
1693 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1694 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1695 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1697 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1699 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
1701 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1702 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1704 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1706 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1707 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1709 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1711 /* Having GuC is not the same as using GuC */
1712 #define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc)
1713 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
1715 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1717 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1720 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1722 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1724 /* DPF == dynamic parity feature */
1725 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1726 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1727 2 : HAS_L3_DPF(dev_priv))
1729 #define GT_FREQUENCY_MULTIPLIER 50
1730 #define GEN9_FREQ_SCALER 3
1732 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1734 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1736 /* Only valid when HAS_DISPLAY() is true */
1737 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1739 static inline bool intel_vtd_active(void)
1741 #ifdef CONFIG_INTEL_IOMMU
1742 if (intel_iommu_gfx_mapped)
1748 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1750 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1754 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1756 return IS_BROXTON(dev_priv) && intel_vtd_active();
1760 #ifdef CONFIG_COMPAT
1761 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
1763 #define i915_compat_ioctl NULL
1765 extern const struct dev_pm_ops i915_pm_ops;
1767 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1768 void i915_driver_remove(struct drm_i915_private *i915);
1770 int i915_resume_switcheroo(struct drm_i915_private *i915);
1771 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1773 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1775 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
1777 return dev_priv->gvt;
1780 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
1782 return dev_priv->vgpu.active;
1785 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1786 struct drm_file *file_priv);
1789 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1790 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1791 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1792 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1793 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1794 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1796 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1798 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1801 * A single pass should suffice to release all the freed objects (along
1802 * most call paths) , but be a little more paranoid in that freeing
1803 * the objects does take a little amount of time, during which the rcu
1804 * callbacks could have added new objects into the freed list, and
1805 * armed the work again.
1807 while (atomic_read(&i915->mm.free_count)) {
1808 flush_work(&i915->mm.free_work);
1813 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1816 * Similar to objects above (see i915_gem_drain_freed-objects), in
1817 * general we have workers that are armed by RCU and then rearm
1818 * themselves in their callbacks. To be paranoid, we need to
1819 * drain the workqueue a second time after waiting for the RCU
1820 * grace period so that we catch work queued via RCU from the first
1821 * pass. As neither drain_workqueue() nor flush_workqueue() report
1822 * a result, we make an assumption that we only don't require more
1823 * than 3 passes to catch all _recursive_ RCU delayed work.
1828 flush_workqueue(i915->wq);
1830 i915_gem_drain_freed_objects(i915);
1832 drain_workqueue(i915->wq);
1835 struct i915_vma * __must_check
1836 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1837 const struct i915_ggtt_view *view,
1842 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1843 unsigned long flags);
1844 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1845 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1847 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1849 static inline int __must_check
1850 i915_mutex_lock_interruptible(struct drm_device *dev)
1852 return mutex_lock_interruptible(&dev->struct_mutex);
1855 int i915_gem_dumb_create(struct drm_file *file_priv,
1856 struct drm_device *dev,
1857 struct drm_mode_create_dumb *args);
1859 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1861 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1863 return atomic_read(&error->reset_count);
1866 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1867 struct intel_engine_cs *engine)
1869 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1872 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1873 void i915_gem_driver_register(struct drm_i915_private *i915);
1874 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1875 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1876 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1877 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1878 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1879 void i915_gem_resume(struct drm_i915_private *dev_priv);
1881 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1882 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1884 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1885 enum i915_cache_level cache_level);
1887 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1888 struct dma_buf *dma_buf);
1890 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1892 static inline struct i915_gem_context *
1893 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1895 return idr_find(&file_priv->context_idr, id);
1898 static inline struct i915_gem_context *
1899 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1901 struct i915_gem_context *ctx;
1904 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1905 if (ctx && !kref_get_unless_zero(&ctx->ref))
1912 /* i915_gem_evict.c */
1913 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1914 u64 min_size, u64 alignment,
1915 unsigned long color,
1918 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1919 struct drm_mm_node *node,
1920 unsigned int flags);
1921 int i915_gem_evict_vm(struct i915_address_space *vm);
1923 /* i915_gem_internal.c */
1924 struct drm_i915_gem_object *
1925 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1928 /* i915_gem_tiling.c */
1929 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1931 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1933 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1934 i915_gem_object_is_tiled(obj);
1937 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1938 unsigned int tiling, unsigned int stride);
1939 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1940 unsigned int tiling, unsigned int stride);
1942 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1944 /* i915_cmd_parser.c */
1945 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1946 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1947 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1948 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1949 struct drm_i915_gem_object *batch_obj,
1950 u64 user_batch_start,
1951 u32 batch_start_offset,
1953 struct drm_i915_gem_object *shadow_batch_obj,
1954 u64 shadow_batch_start);
1956 /* intel_device_info.c */
1957 static inline struct intel_device_info *
1958 mkwrite_device_info(struct drm_i915_private *dev_priv)
1960 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1963 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1964 struct drm_file *file);
1966 #define __I915_REG_OP(op__, dev_priv__, ...) \
1967 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
1969 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
1970 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1972 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
1974 /* These are untraced mmio-accessors that are only valid to be used inside
1975 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
1978 * Think twice, and think again, before using these.
1980 * As an example, these accessors can possibly be used between:
1982 * spin_lock_irq(&dev_priv->uncore.lock);
1983 * intel_uncore_forcewake_get__locked();
1987 * intel_uncore_forcewake_put__locked();
1988 * spin_unlock_irq(&dev_priv->uncore.lock);
1991 * Note: some registers may not need forcewake held, so
1992 * intel_uncore_forcewake_{get,put} can be omitted, see
1993 * intel_uncore_forcewake_for_reg().
1995 * Certain architectures will die if the same cacheline is concurrently accessed
1996 * by different clients (e.g. on Ivybridge). Access to registers should
1997 * therefore generally be serialised, by either the dev_priv->uncore.lock or
1998 * a more localised lock guarding all access to that bank of registers.
2000 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2001 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2003 /* register wait wrappers for display regs */
2004 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
2005 intel_wait_for_register(&(dev_priv_)->uncore, \
2006 (reg_), (mask_), (value_), (timeout_))
2008 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \
2009 u32 mask__ = (mask_); \
2010 intel_de_wait_for_register((dev_priv_), (reg_), \
2011 mask__, mask__, (timeout_)); \
2014 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
2015 intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_))
2018 int remap_io_mapping(struct vm_area_struct *vma,
2019 unsigned long addr, unsigned long pfn, unsigned long size,
2020 struct io_mapping *iomap);
2022 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2024 if (INTEL_GEN(i915) >= 10)
2025 return CNL_HWS_CSB_WRITE_INDEX;
2027 return I915_HWS_CSB_WRITE_INDEX;
2030 static inline enum i915_map_type
2031 i915_coherent_map_type(struct drm_i915_private *i915)
2033 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2036 static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc)
2038 return intel_guc_is_submission_supported(guc) &&
2039 intel_guc_is_running(guc);