1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_atomic.h>
58 #include <drm/drm_connector.h>
59 #include <drm/i915_mei_hdcp_interface.h>
61 #include "i915_fixed.h"
62 #include "i915_params.h"
64 #include "i915_utils.h"
66 #include "gt/intel_lrc.h"
67 #include "gt/intel_engine.h"
68 #include "gt/intel_workarounds.h"
70 #include "intel_bios.h"
71 #include "intel_device_info.h"
72 #include "intel_display.h"
73 #include "intel_display_power.h"
74 #include "intel_dpll_mgr.h"
75 #include "intel_frontbuffer.h"
76 #include "intel_opregion.h"
77 #include "intel_runtime_pm.h"
79 #include "intel_uncore.h"
80 #include "intel_wakeref.h"
81 #include "intel_wopcm.h"
84 #include "gem/i915_gem_context_types.h"
85 #include "i915_gem_fence_reg.h"
86 #include "i915_gem_gtt.h"
87 #include "i915_gpu_error.h"
88 #include "i915_request.h"
89 #include "i915_scheduler.h"
90 #include "i915_timeline.h"
93 #include "intel_gvt.h"
95 /* General customization:
98 #define DRIVER_NAME "i915"
99 #define DRIVER_DESC "Intel Graphics"
100 #define DRIVER_DATE "20190524"
101 #define DRIVER_TIMESTAMP 1558719322
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105 * which may not necessarily be a user visible problem. This will either
106 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107 * enable distros and users to tailor their preferred amount of i915 abrt
110 #define I915_STATE_WARN(condition, format...) ({ \
111 int __ret_warn_on = !!(condition); \
112 if (unlikely(__ret_warn_on)) \
113 if (!WARN(i915_modparams.verbose_state_checks, format)) \
115 unlikely(__ret_warn_on); \
118 #define I915_STATE_WARN_ON(x) \
119 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
121 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
123 bool __i915_inject_load_failure(const char *func, int line);
124 #define i915_inject_load_failure() \
125 __i915_inject_load_failure(__func__, __LINE__)
127 bool i915_error_injected(void);
131 #define i915_inject_load_failure() false
132 #define i915_error_injected() false
136 #define i915_load_error(i915, fmt, ...) \
137 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
140 struct drm_i915_gem_object;
144 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
157 #define for_each_hpd_pin(__pin) \
158 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
160 /* Threshold == 5 for long IRQs, 50 for short */
161 #define HPD_STORM_DEFAULT_THRESHOLD 50
163 struct i915_hotplug {
164 struct work_struct hotplug_work;
167 unsigned long last_jiffies;
172 HPD_MARK_DISABLED = 2
174 } stats[HPD_NUM_PINS];
176 struct delayed_work reenable_work;
180 struct work_struct dig_port_work;
182 struct work_struct poll_init_work;
185 unsigned int hpd_storm_threshold;
186 /* Whether or not to count short HPD IRQs in HPD storms */
187 u8 hpd_short_storm_enabled;
190 * if we get a HPD irq from DP and a HPD irq from non-DP
191 * the non-DP HPD could block the workqueue on a mode config
192 * mutex getting, that userspace may have taken. However
193 * userspace is waiting on the DP workqueue to run which is
194 * blocked behind the non-DP one.
196 struct workqueue_struct *dp_wq;
199 #define I915_GEM_GPU_DOMAINS \
200 (I915_GEM_DOMAIN_RENDER | \
201 I915_GEM_DOMAIN_SAMPLER | \
202 I915_GEM_DOMAIN_COMMAND | \
203 I915_GEM_DOMAIN_INSTRUCTION | \
204 I915_GEM_DOMAIN_VERTEX)
206 struct drm_i915_private;
207 struct i915_mm_struct;
208 struct i915_mmu_object;
210 struct drm_i915_file_private {
211 struct drm_i915_private *dev_priv;
212 struct drm_file *file;
216 struct list_head request_list;
219 struct idr context_idr;
220 struct mutex context_idr_lock; /* guards context_idr */
223 struct mutex vm_idr_lock; /* guards vm_idr */
225 unsigned int bsd_engine;
228 * Every context ban increments per client ban score. Also
229 * hangs in short succession increments ban score. If ban threshold
230 * is reached, client is considered banned and submitting more work
231 * will fail. This is a stop gap measure to limit the badly behaving
232 * clients access to gpu. Note that unbannable contexts never increment
233 * the client ban score.
235 #define I915_CLIENT_SCORE_HANG_FAST 1
236 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
237 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
238 #define I915_CLIENT_SCORE_BANNED 9
239 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
241 unsigned long hang_timestamp;
244 /* Interface history:
247 * 1.2: Add Power Management
248 * 1.3: Add vblank support
249 * 1.4: Fix cmdbuffer path, add heap destroy
250 * 1.5: Add vblank pipe configuration
251 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
252 * - Support vertical blank on secondary display pipe
254 #define DRIVER_MAJOR 1
255 #define DRIVER_MINOR 6
256 #define DRIVER_PATCHLEVEL 0
258 struct intel_overlay;
259 struct intel_overlay_error_state;
261 struct sdvo_device_mapping {
270 struct intel_connector;
271 struct intel_encoder;
272 struct intel_atomic_state;
273 struct intel_crtc_state;
274 struct intel_initial_plane_config;
278 struct intel_cdclk_state;
280 struct drm_i915_display_funcs {
281 void (*get_cdclk)(struct drm_i915_private *dev_priv,
282 struct intel_cdclk_state *cdclk_state);
283 void (*set_cdclk)(struct drm_i915_private *dev_priv,
284 const struct intel_cdclk_state *cdclk_state,
286 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
287 enum i9xx_plane_id i9xx_plane);
288 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
289 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
290 void (*initial_watermarks)(struct intel_atomic_state *state,
291 struct intel_crtc_state *cstate);
292 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
293 struct intel_crtc_state *cstate);
294 void (*optimize_watermarks)(struct intel_atomic_state *state,
295 struct intel_crtc_state *cstate);
296 int (*compute_global_watermarks)(struct intel_atomic_state *state);
297 void (*update_wm)(struct intel_crtc *crtc);
298 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
299 /* Returns the active state of the crtc, and if the crtc is active,
300 * fills out the pipe-config with the hw state. */
301 bool (*get_pipe_config)(struct intel_crtc *,
302 struct intel_crtc_state *);
303 void (*get_initial_plane_config)(struct intel_crtc *,
304 struct intel_initial_plane_config *);
305 int (*crtc_compute_clock)(struct intel_crtc *crtc,
306 struct intel_crtc_state *crtc_state);
307 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
308 struct drm_atomic_state *old_state);
309 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
310 struct drm_atomic_state *old_state);
311 void (*update_crtcs)(struct drm_atomic_state *state);
312 void (*audio_codec_enable)(struct intel_encoder *encoder,
313 const struct intel_crtc_state *crtc_state,
314 const struct drm_connector_state *conn_state);
315 void (*audio_codec_disable)(struct intel_encoder *encoder,
316 const struct intel_crtc_state *old_crtc_state,
317 const struct drm_connector_state *old_conn_state);
318 void (*fdi_link_train)(struct intel_crtc *crtc,
319 const struct intel_crtc_state *crtc_state);
320 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
321 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
322 /* clock updates for mode set */
324 /* render clock increase/decrease */
325 /* display clock increase/decrease */
326 /* pll clock increase/decrease */
328 int (*color_check)(struct intel_crtc_state *crtc_state);
330 * Program double buffered color management registers during
331 * vblank evasion. The registers should then latch during the
332 * next vblank start, alongside any other double buffered registers
333 * involved with the same commit.
335 void (*color_commit)(const struct intel_crtc_state *crtc_state);
337 * Load LUTs (and other single buffered color management
338 * registers). Will (hopefully) be called during the vblank
339 * following the latching of any double buffered registers
340 * involved with the same commit.
342 void (*load_luts)(const struct intel_crtc_state *crtc_state);
343 void (*read_luts)(struct intel_crtc_state *crtc_state);
347 struct work_struct work;
349 u32 required_version;
350 u32 max_fw_size; /* bytes */
352 u32 dmc_fw_size; /* dwords */
355 i915_reg_t mmioaddr[8];
359 intel_wakeref_t wakeref;
362 enum i915_cache_level {
364 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
365 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
366 caches, eg sampler/render caches, and the
367 large Last-Level-Cache. LLC is coherent with
368 the CPU, but L3 is only visible to the GPU. */
369 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
372 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
375 /* This is always the inner lock when overlapping with struct_mutex and
376 * it's the outer lock when overlapping with stolen_lock. */
379 unsigned int possible_framebuffer_bits;
380 unsigned int busy_bits;
381 unsigned int visible_pipes_mask;
382 struct intel_crtc *crtc;
384 struct drm_mm_node compressed_fb;
385 struct drm_mm_node *compressed_llb;
393 bool underrun_detected;
394 struct work_struct underrun_work;
397 * Due to the atomic rules we can't access some structures without the
398 * appropriate locking, so we cache information here in order to avoid
401 struct intel_fbc_state_cache {
402 struct i915_vma *vma;
406 unsigned int mode_flags;
407 u32 hsw_bdw_pixel_rate;
411 unsigned int rotation;
416 * Display surface base address adjustement for
417 * pageflips. Note that on gen4+ this only adjusts up
418 * to a tile, offsets within a tile are handled in
419 * the hw itself (with the TILEOFF register).
426 u16 pixel_blend_mode;
430 const struct drm_format_info *format;
436 * This structure contains everything that's relevant to program the
437 * hardware registers. When we want to figure out if we need to disable
438 * and re-enable FBC for a new configuration we just check if there's
439 * something different in the struct. The genx_fbc_activate functions
440 * are supposed to read from it in order to program the registers.
442 struct intel_fbc_reg_params {
443 struct i915_vma *vma;
448 enum i9xx_plane_id i9xx_plane;
449 unsigned int fence_y_offset;
453 const struct drm_format_info *format;
458 unsigned int gen9_wa_cfb_stride;
461 const char *no_fbc_reason;
465 * HIGH_RR is the highest eDP panel refresh rate read from EDID
466 * LOW_RR is the lowest eDP panel refresh rate found from EDID
467 * parsing for same resolution.
469 enum drrs_refresh_rate_type {
472 DRRS_MAX_RR, /* RR count */
475 enum drrs_support_type {
476 DRRS_NOT_SUPPORTED = 0,
477 STATIC_DRRS_SUPPORT = 1,
478 SEAMLESS_DRRS_SUPPORT = 2
484 struct delayed_work work;
486 unsigned busy_frontbuffer_bits;
487 enum drrs_refresh_rate_type refresh_rate_type;
488 enum drrs_support_type type;
494 #define I915_PSR_DEBUG_MODE_MASK 0x0f
495 #define I915_PSR_DEBUG_DEFAULT 0x00
496 #define I915_PSR_DEBUG_DISABLE 0x01
497 #define I915_PSR_DEBUG_ENABLE 0x02
498 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
499 #define I915_PSR_DEBUG_IRQ 0x10
507 struct work_struct work;
508 unsigned busy_frontbuffer_bits;
509 bool sink_psr2_support;
511 bool colorimetry_support;
513 u8 sink_sync_latency;
514 ktime_t last_entry_attempt;
516 bool sink_not_reliable;
518 u16 su_x_granularity;
522 * Sorted by south display engine compatibility.
523 * If the new PCH comes with a south display engine that is not
524 * inherited from the latest item, please do not add it to the
525 * end. Instead, add it right after its "parent" PCH.
528 PCH_NOP = -1, /* PCH without south display */
529 PCH_NONE = 0, /* No PCH present */
530 PCH_IBX, /* Ibexpeak PCH */
531 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
532 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
533 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
534 PCH_CNP, /* Cannon/Comet Lake PCH */
535 PCH_ICP, /* Ice Lake PCH */
538 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
539 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
540 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
541 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
542 #define QUIRK_INCREASE_T12_DELAY (1<<6)
543 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
546 struct intel_fbc_work;
549 struct i2c_adapter adapter;
550 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
554 struct i2c_algo_bit_data bit_algo;
555 struct drm_i915_private *dev_priv;
558 struct i915_suspend_saved_registers {
561 u32 saveCACHE_MODE_0;
562 u32 saveMI_ARB_STATE;
566 u64 saveFENCE[I915_MAX_NUM_FENCES];
567 u32 savePCH_PORT_HOTPLUG;
571 struct vlv_s0ix_state {
578 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
579 u32 media_max_req_count;
580 u32 gfx_max_req_count;
612 /* Display 1 CZ domain */
617 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
619 /* GT SA CZ domain */
626 /* Display 2 CZ domain */
633 struct intel_rps_ei {
640 struct mutex lock; /* protects enabling and the worker */
643 * work, interrupts_enabled and pm_iir are protected by
646 struct work_struct work;
647 bool interrupts_enabled;
650 /* PM interrupt bits that should never be masked */
653 /* Frequencies are stored in potentially platform dependent multiples.
654 * In other words, *_freq needs to be multiplied by X to be interesting.
655 * Soft limits are those which are used for the dynamic reclocking done
656 * by the driver (raise frequencies under heavy loads, and lower for
657 * lighter loads). Hard limits are those imposed by the hardware.
659 * A distinction is made for overclocking, which is never enabled by
660 * default, and is considered to be above the hard limit if it's
663 u8 cur_freq; /* Current frequency (cached, may not == HW) */
664 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
665 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
666 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
667 u8 min_freq; /* AKA RPn. Minimum frequency */
668 u8 boost_freq; /* Frequency to request when wait boosting */
669 u8 idle_freq; /* Frequency to request when we are idle */
670 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
671 u8 rp1_freq; /* "less than" RP0 power/freqency */
672 u8 rp0_freq; /* Non-overclocked max frequency. */
673 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
680 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
681 unsigned int interactive;
683 u8 up_threshold; /* Current %busy required to uplock */
684 u8 down_threshold; /* Current %busy required to downclock */
688 atomic_t num_waiters;
691 /* manual wa residency calculations */
692 struct intel_rps_ei ei;
697 u64 prev_hw_residency[4];
698 u64 cur_residency[4];
701 struct intel_llc_pstate {
705 struct intel_gen6_power_mgmt {
706 struct intel_rps rps;
707 struct intel_rc6 rc6;
708 struct intel_llc_pstate llc_pstate;
711 /* defined intel_pm.c */
712 extern spinlock_t mchdev_lock;
714 struct intel_ilk_power_mgmt {
722 unsigned long last_time1;
723 unsigned long chipset_power;
726 unsigned long gfx_power;
733 #define MAX_L3_SLICES 2
734 struct intel_l3_parity {
735 u32 *remap_info[MAX_L3_SLICES];
736 struct work_struct error_work;
741 /** Memory allocator for GTT stolen memory */
742 struct drm_mm stolen;
743 /** Protects the usage of the GTT stolen memory allocator. This is
744 * always the inner lock when overlapping with struct_mutex. */
745 struct mutex stolen_lock;
747 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
750 /** List of all objects in gtt_space. Used to restore gtt
751 * mappings on resume */
752 struct list_head bound_list;
754 * List of objects which are not bound to the GTT (thus
755 * are idle and not used by the GPU). These objects may or may
756 * not actually have any pages attached.
758 struct list_head unbound_list;
760 * List of objects which are purgeable. May be active.
762 struct list_head purge_list;
764 /** List of all objects in gtt_space, currently mmaped by userspace.
765 * All objects within this list must also be on bound_list.
767 struct list_head userfault_list;
769 /* Manual runtime pm autosuspend delay for user GGTT mmaps */
770 struct intel_wakeref_auto userfault_wakeref;
773 * List of objects which are pending destruction.
775 struct llist_head free_list;
776 struct work_struct free_work;
777 spinlock_t free_lock;
779 * Count of objects pending destructions. Used to skip needlessly
780 * waiting on an RCU barrier if no objects are waiting to be freed.
785 * Small stash of WC pages
787 struct pagestash wc_stash;
790 * tmpfs instance used for shmem backed objects
792 struct vfsmount *gemfs;
794 /** PPGTT used for aliasing the PPGTT with the GTT */
795 struct i915_ppgtt *aliasing_ppgtt;
797 struct notifier_block oom_notifier;
798 struct notifier_block vmap_notifier;
799 struct shrinker shrinker;
801 /** LRU list of objects with fence regs on them. */
802 struct list_head fence_list;
805 * Workqueue to fault in userptr pages, flushed by the execbuf
806 * when required but otherwise left to userspace to try again
809 struct workqueue_struct *userptr_wq;
811 u64 unordered_timeline;
813 /* the indicator for dispatch video commands on two BSD rings */
814 atomic_t bsd_engine_dispatch_index;
816 /** Bit 6 swizzling required for X tiling */
818 /** Bit 6 swizzling required for Y tiling */
821 /* shrinker accounting, also useful for userland debugging */
826 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
828 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
829 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
831 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
832 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
834 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
836 struct ddi_vbt_port_info {
837 /* Non-NULL if port present. */
838 const struct child_device_config *child;
843 * This is an index in the HDMI/DVI DDI buffer translation table.
844 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
845 * populate this field.
847 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
854 u8 supports_typec_usb:1;
857 u8 alternate_aux_channel;
858 u8 alternate_ddc_pin;
862 int dp_max_link_rate; /* 0 for not limited by VBT */
865 enum psr_lines_to_wait {
866 PSR_0_LINES_TO_WAIT = 0,
872 struct intel_vbt_data {
873 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
874 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
877 unsigned int int_tv_support:1;
878 unsigned int lvds_dither:1;
879 unsigned int int_crt_support:1;
880 unsigned int lvds_use_ssc:1;
881 unsigned int int_lvds_support:1;
882 unsigned int display_clock_mode:1;
883 unsigned int fdi_rx_polarity_inverted:1;
884 unsigned int panel_type:4;
886 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
887 enum drm_panel_orientation orientation;
889 enum drrs_support_type drrs_type;
899 struct edp_power_seq pps;
905 bool require_aux_wakeup;
907 enum psr_lines_to_wait lines_to_wait;
908 int tp1_wakeup_time_us;
909 int tp2_tp3_wakeup_time_us;
910 int psr2_tp2_tp3_wakeup_time_us;
917 u8 min_brightness; /* min_brightness/255 of max */
918 u8 controller; /* brightness controller number */
919 enum intel_backlight_type type;
925 struct mipi_config *config;
926 struct mipi_pps_data *pps;
932 const u8 *sequence[MIPI_SEQ_MAX];
933 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
934 enum drm_panel_orientation orientation;
940 struct child_device_config *child_dev;
942 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
943 struct sdvo_device_mapping sdvo_mappings[2];
946 enum intel_ddb_partitioning {
948 INTEL_DDB_PART_5_6, /* IVB+ */
951 struct intel_wm_level {
959 struct ilk_wm_values {
965 enum intel_ddb_partitioning partitioning;
969 u16 plane[I915_MAX_PLANES];
979 struct vlv_wm_ddl_values {
980 u8 plane[I915_MAX_PLANES];
983 struct vlv_wm_values {
984 struct g4x_pipe_wm pipe[3];
986 struct vlv_wm_ddl_values ddl[3];
991 struct g4x_wm_values {
992 struct g4x_pipe_wm pipe[2];
994 struct g4x_sr_wm hpll;
1000 struct skl_ddb_entry {
1001 u16 start, end; /* in number of blocks, 'end' is exclusive */
1004 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1006 return entry->end - entry->start;
1009 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1010 const struct skl_ddb_entry *e2)
1012 if (e1->start == e2->start && e1->end == e2->end)
1018 struct skl_ddb_allocation {
1019 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1022 struct skl_ddb_values {
1023 unsigned dirty_pipes;
1024 struct skl_ddb_allocation ddb;
1027 struct skl_wm_level {
1035 /* Stores plane specific WM parameters */
1036 struct skl_wm_params {
1037 bool x_tiled, y_tiled;
1042 u32 plane_pixel_rate;
1043 u32 y_min_scanlines;
1044 u32 plane_bytes_per_line;
1045 uint_fixed_16_16_t plane_blocks_per_line;
1046 uint_fixed_16_16_t y_tile_minimum;
1048 u32 dbuf_block_size;
1052 * This struct helps tracking the state needed for runtime PM, which puts the
1053 * device in PCI D3 state. Notice that when this happens, nothing on the
1054 * graphics device works, even register access, so we don't get interrupts nor
1057 * Every piece of our code that needs to actually touch the hardware needs to
1058 * either call intel_runtime_pm_get or call intel_display_power_get with the
1059 * appropriate power domain.
1061 * Our driver uses the autosuspend delay feature, which means we'll only really
1062 * suspend if we stay with zero refcount for a certain amount of time. The
1063 * default value is currently very conservative (see intel_runtime_pm_enable), but
1064 * it can be changed with the standard runtime PM files from sysfs.
1066 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1067 * goes back to false exactly before we reenable the IRQs. We use this variable
1068 * to check if someone is trying to enable/disable IRQs while they're supposed
1069 * to be disabled. This shouldn't happen and we'll print some error messages in
1072 * For more, read the Documentation/power/runtime_pm.txt.
1074 struct i915_runtime_pm {
1075 atomic_t wakeref_count;
1079 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1081 * To aide detection of wakeref leaks and general misuse, we
1082 * track all wakeref holders. With manual markup (i.e. returning
1083 * a cookie to each rpm_get caller which they then supply to their
1084 * paired rpm_put) we can remove corresponding pairs of and keep
1085 * the array trimmed to active wakerefs.
1087 struct intel_runtime_pm_debug {
1090 depot_stack_handle_t last_acquire;
1091 depot_stack_handle_t last_release;
1093 depot_stack_handle_t *owners;
1094 unsigned long count;
1099 enum intel_pipe_crc_source {
1100 INTEL_PIPE_CRC_SOURCE_NONE,
1101 INTEL_PIPE_CRC_SOURCE_PLANE1,
1102 INTEL_PIPE_CRC_SOURCE_PLANE2,
1103 INTEL_PIPE_CRC_SOURCE_PLANE3,
1104 INTEL_PIPE_CRC_SOURCE_PLANE4,
1105 INTEL_PIPE_CRC_SOURCE_PLANE5,
1106 INTEL_PIPE_CRC_SOURCE_PLANE6,
1107 INTEL_PIPE_CRC_SOURCE_PLANE7,
1108 INTEL_PIPE_CRC_SOURCE_PIPE,
1109 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1110 INTEL_PIPE_CRC_SOURCE_TV,
1111 INTEL_PIPE_CRC_SOURCE_DP_B,
1112 INTEL_PIPE_CRC_SOURCE_DP_C,
1113 INTEL_PIPE_CRC_SOURCE_DP_D,
1114 INTEL_PIPE_CRC_SOURCE_AUTO,
1115 INTEL_PIPE_CRC_SOURCE_MAX,
1118 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1119 struct intel_pipe_crc {
1122 enum intel_pipe_crc_source source;
1125 struct i915_frontbuffer_tracking {
1129 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1136 struct i915_virtual_gpu {
1141 /* used in computing the new watermarks state */
1142 struct intel_wm_config {
1143 unsigned int num_pipes_active;
1144 bool sprites_enabled;
1145 bool sprites_scaled;
1148 struct i915_oa_format {
1153 struct i915_oa_reg {
1158 struct i915_oa_config {
1159 char uuid[UUID_STRING_LEN + 1];
1162 const struct i915_oa_reg *mux_regs;
1164 const struct i915_oa_reg *b_counter_regs;
1165 u32 b_counter_regs_len;
1166 const struct i915_oa_reg *flex_regs;
1169 struct attribute_group sysfs_metric;
1170 struct attribute *attrs[2];
1171 struct device_attribute sysfs_metric_id;
1176 struct i915_perf_stream;
1179 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1181 struct i915_perf_stream_ops {
1183 * @enable: Enables the collection of HW samples, either in response to
1184 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1185 * without `I915_PERF_FLAG_DISABLED`.
1187 void (*enable)(struct i915_perf_stream *stream);
1190 * @disable: Disables the collection of HW samples, either in response
1191 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1194 void (*disable)(struct i915_perf_stream *stream);
1197 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1198 * once there is something ready to read() for the stream
1200 void (*poll_wait)(struct i915_perf_stream *stream,
1205 * @wait_unlocked: For handling a blocking read, wait until there is
1206 * something to ready to read() for the stream. E.g. wait on the same
1207 * wait queue that would be passed to poll_wait().
1209 int (*wait_unlocked)(struct i915_perf_stream *stream);
1212 * @read: Copy buffered metrics as records to userspace
1213 * **buf**: the userspace, destination buffer
1214 * **count**: the number of bytes to copy, requested by userspace
1215 * **offset**: zero at the start of the read, updated as the read
1216 * proceeds, it represents how many bytes have been copied so far and
1217 * the buffer offset for copying the next record.
1219 * Copy as many buffered i915 perf samples and records for this stream
1220 * to userspace as will fit in the given buffer.
1222 * Only write complete records; returning -%ENOSPC if there isn't room
1223 * for a complete record.
1225 * Return any error condition that results in a short read such as
1226 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1227 * returning to userspace.
1229 int (*read)(struct i915_perf_stream *stream,
1235 * @destroy: Cleanup any stream specific resources.
1237 * The stream will always be disabled before this is called.
1239 void (*destroy)(struct i915_perf_stream *stream);
1243 * struct i915_perf_stream - state for a single open stream FD
1245 struct i915_perf_stream {
1247 * @dev_priv: i915 drm device
1249 struct drm_i915_private *dev_priv;
1252 * @link: Links the stream into ``&drm_i915_private->streams``
1254 struct list_head link;
1257 * @wakeref: As we keep the device awake while the perf stream is
1258 * active, we track our runtime pm reference for later release.
1260 intel_wakeref_t wakeref;
1263 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1264 * properties given when opening a stream, representing the contents
1265 * of a single sample as read() by userspace.
1270 * @sample_size: Considering the configured contents of a sample
1271 * combined with the required header size, this is the total size
1272 * of a single sample record.
1277 * @ctx: %NULL if measuring system-wide across all contexts or a
1278 * specific context that is being monitored.
1280 struct i915_gem_context *ctx;
1283 * @enabled: Whether the stream is currently enabled, considering
1284 * whether the stream was opened in a disabled state and based
1285 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1290 * @ops: The callbacks providing the implementation of this specific
1291 * type of configured stream.
1293 const struct i915_perf_stream_ops *ops;
1296 * @oa_config: The OA configuration used by the stream.
1298 struct i915_oa_config *oa_config;
1302 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1304 struct i915_oa_ops {
1306 * @is_valid_b_counter_reg: Validates register's address for
1307 * programming boolean counters for a particular platform.
1309 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1313 * @is_valid_mux_reg: Validates register's address for programming mux
1314 * for a particular platform.
1316 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1319 * @is_valid_flex_reg: Validates register's address for programming
1320 * flex EU filtering for a particular platform.
1322 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1325 * @enable_metric_set: Selects and applies any MUX configuration to set
1326 * up the Boolean and Custom (B/C) counters that are part of the
1327 * counter reports being sampled. May apply system constraints such as
1328 * disabling EU clock gating as required.
1330 int (*enable_metric_set)(struct i915_perf_stream *stream);
1333 * @disable_metric_set: Remove system constraints associated with using
1336 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1339 * @oa_enable: Enable periodic sampling
1341 void (*oa_enable)(struct i915_perf_stream *stream);
1344 * @oa_disable: Disable periodic sampling
1346 void (*oa_disable)(struct i915_perf_stream *stream);
1349 * @read: Copy data from the circular OA buffer into a given userspace
1352 int (*read)(struct i915_perf_stream *stream,
1358 * @oa_hw_tail_read: read the OA tail pointer register
1360 * In particular this enables us to share all the fiddly code for
1361 * handling the OA unit tail pointer race that affects multiple
1364 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1367 struct intel_cdclk_state {
1368 unsigned int cdclk, vco, ref, bypass;
1372 struct drm_i915_private {
1373 struct drm_device drm;
1375 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1376 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1377 struct intel_driver_caps caps;
1380 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1381 * end of stolen which we can optionally use to create GEM objects
1382 * backed by stolen memory. Note that stolen_usable_size tells us
1383 * exactly how much of this we are actually allowed to use, given that
1384 * some portion of it is in fact reserved for use by hardware functions.
1386 struct resource dsm;
1388 * Reseved portion of Data Stolen Memory
1390 struct resource dsm_reserved;
1393 * Stolen memory is segmented in hardware with different portions
1394 * offlimits to certain functions.
1396 * The drm_mm is initialised to the total accessible range, as found
1397 * from the PCI config. On Broadwell+, this is further restricted to
1398 * avoid the first page! The upper end of stolen memory is reserved for
1399 * hardware functions and similarly removed from the accessible range.
1401 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1403 struct intel_uncore uncore;
1405 struct i915_virtual_gpu vgpu;
1407 struct intel_gvt *gvt;
1409 struct intel_wopcm wopcm;
1411 struct intel_huc huc;
1412 struct intel_guc guc;
1414 struct intel_csr csr;
1416 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1418 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1419 * controller on different i2c buses. */
1420 struct mutex gmbus_mutex;
1423 * Base address of where the gmbus and gpio blocks are located (either
1424 * on PCH or on SoC for platforms without PCH).
1428 /* MMIO base address for MIPI regs */
1435 wait_queue_head_t gmbus_wait_queue;
1437 struct pci_dev *bridge_dev;
1438 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1439 /* Context used internally to idle the GPU and setup initial state */
1440 struct i915_gem_context *kernel_context;
1441 /* Context only to be used for injecting preemption commands */
1442 struct i915_gem_context *preempt_context;
1443 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1444 [MAX_ENGINE_INSTANCE + 1];
1446 struct resource mch_res;
1448 /* protects the irq masks */
1449 spinlock_t irq_lock;
1451 bool display_irqs_enabled;
1453 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1454 struct pm_qos_request pm_qos;
1456 /* Sideband mailbox protection */
1457 struct mutex sb_lock;
1458 struct pm_qos_request sb_qos;
1460 /** Cached value of IMR to avoid reads in updating the bitfield */
1463 u32 de_irq_mask[I915_MAX_PIPES];
1470 u32 pipestat_irq_mask[I915_MAX_PIPES];
1472 struct i915_hotplug hotplug;
1473 struct intel_fbc fbc;
1474 struct i915_drrs drrs;
1475 struct intel_opregion opregion;
1476 struct intel_vbt_data vbt;
1478 bool preserve_bios_swizzle;
1481 struct intel_overlay *overlay;
1483 /* backlight registers and fields in struct intel_panel */
1484 struct mutex backlight_lock;
1487 bool no_aux_handshake;
1489 /* protects panel power sequencer state */
1490 struct mutex pps_mutex;
1492 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1493 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1495 unsigned int fsb_freq, mem_freq, is_ddr3;
1496 unsigned int skl_preferred_vco_freq;
1497 unsigned int max_cdclk_freq;
1499 unsigned int max_dotclk_freq;
1500 unsigned int rawclk_freq;
1501 unsigned int hpll_freq;
1502 unsigned int fdi_pll_freq;
1503 unsigned int czclk_freq;
1507 * The current logical cdclk state.
1508 * See intel_atomic_state.cdclk.logical
1510 * For reading holding any crtc lock is sufficient,
1511 * for writing must hold all of them.
1513 struct intel_cdclk_state logical;
1515 * The current actual cdclk state.
1516 * See intel_atomic_state.cdclk.actual
1518 struct intel_cdclk_state actual;
1519 /* The current hardware cdclk state */
1520 struct intel_cdclk_state hw;
1522 int force_min_cdclk;
1526 * wq - Driver workqueue for GEM.
1528 * NOTE: Work items scheduled here are not allowed to grab any modeset
1529 * locks, for otherwise the flushing done in the pageflip code will
1530 * result in deadlocks.
1532 struct workqueue_struct *wq;
1534 /* ordered wq for modesets */
1535 struct workqueue_struct *modeset_wq;
1537 /* Display functions */
1538 struct drm_i915_display_funcs display;
1540 /* PCH chipset type */
1541 enum intel_pch pch_type;
1542 unsigned short pch_id;
1544 unsigned long quirks;
1546 struct drm_atomic_state *modeset_restore_state;
1547 struct drm_modeset_acquire_ctx reset_ctx;
1549 struct i915_ggtt ggtt; /* VM representing the global address space */
1551 struct i915_gem_mm mm;
1552 DECLARE_HASHTABLE(mm_structs, 7);
1553 struct mutex mm_lock;
1555 struct intel_ppat ppat;
1557 /* Kernel Modesetting */
1559 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1560 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1562 #ifdef CONFIG_DEBUG_FS
1563 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1566 /* dpll and cdclk state is protected by connection_mutex */
1567 int num_shared_dpll;
1568 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1569 const struct intel_dpll_mgr *dpll_mgr;
1572 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1573 * Must be global rather than per dpll, because on some platforms
1574 * plls share registers.
1576 struct mutex dpll_lock;
1578 unsigned int active_crtcs;
1579 /* minimum acceptable cdclk for each pipe */
1580 int min_cdclk[I915_MAX_PIPES];
1581 /* minimum acceptable voltage level for each pipe */
1582 u8 min_voltage_level[I915_MAX_PIPES];
1584 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1586 struct i915_wa_list gt_wa_list;
1588 struct i915_frontbuffer_tracking fb_tracking;
1590 struct intel_atomic_helper {
1591 struct llist_head free_list;
1592 struct work_struct free_work;
1597 bool mchbar_need_disable;
1599 struct intel_l3_parity l3_parity;
1603 * Cannot be determined by PCIID. You must always read a register.
1607 /* gen6+ GT PM state */
1608 struct intel_gen6_power_mgmt gt_pm;
1610 /* ilk-only ips/rps state. Everything in here is protected by the global
1611 * mchdev_lock in intel_pm.c */
1612 struct intel_ilk_power_mgmt ips;
1614 struct i915_power_domains power_domains;
1616 struct i915_psr psr;
1618 struct i915_gpu_error gpu_error;
1620 struct drm_i915_gem_object *vlv_pctx;
1622 /* list of fbdev register on this device */
1623 struct intel_fbdev *fbdev;
1624 struct work_struct fbdev_suspend_work;
1626 struct drm_property *broadcast_rgb_property;
1627 struct drm_property *force_audio_property;
1629 /* hda/i915 audio component */
1630 struct i915_audio_component *audio_component;
1631 bool audio_component_registered;
1633 * av_mutex - mutex for audio/video sync
1636 struct mutex av_mutex;
1637 int audio_power_refcount;
1641 struct list_head list;
1642 struct llist_head free_list;
1643 struct work_struct free_work;
1645 /* The hw wants to have a stable context identifier for the
1646 * lifetime of the context (for OA, PASID, faults, etc).
1647 * This is limited in execlists to 21 bits.
1650 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1651 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1652 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1653 struct list_head hw_id_list;
1658 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1659 u32 chv_phy_control;
1661 * Shadows for CHV DPLL_MD regs to keep the state
1662 * checker somewhat working in the presence hardware
1663 * crappiness (can't read out DPLL_MD for pipes B & C).
1665 u32 chv_dpll_md[I915_MAX_PIPES];
1669 bool power_domains_suspended;
1670 struct i915_suspend_saved_registers regfile;
1671 struct vlv_s0ix_state vlv_s0ix_state;
1674 I915_SAGV_UNKNOWN = 0,
1677 I915_SAGV_NOT_CONTROLLED
1682 * Raw watermark latency values:
1683 * in 0.1us units for WM0,
1684 * in 0.5us units for WM1+.
1693 * Raw watermark memory latency values
1694 * for SKL for all 8 levels
1699 /* current hardware state */
1701 struct ilk_wm_values hw;
1702 struct skl_ddb_values skl_hw;
1703 struct vlv_wm_values vlv;
1704 struct g4x_wm_values g4x;
1710 * Should be held around atomic WM register writing; also
1711 * protects * intel_crtc->wm.active and
1712 * cstate->wm.need_postvbl_update.
1714 struct mutex wm_mutex;
1717 * Set during HW readout of watermarks/DDB. Some platforms
1718 * need to know when we're still using BIOS-provided values
1719 * (which we don't fully trust).
1721 bool distrust_bios_wm;
1730 bool symmetric_memory;
1731 enum intel_dram_type {
1740 struct intel_bw_info {
1745 struct drm_private_obj bw_obj;
1747 struct i915_runtime_pm runtime_pm;
1752 struct kobject *metrics_kobj;
1753 struct ctl_table_header *sysctl_header;
1756 * Lock associated with adding/modifying/removing OA configs
1757 * in dev_priv->perf.metrics_idr.
1759 struct mutex metrics_lock;
1762 * List of dynamic configurations, you need to hold
1763 * dev_priv->perf.metrics_lock to access it.
1765 struct idr metrics_idr;
1768 * Lock associated with anything below within this structure
1769 * except exclusive_stream.
1772 struct list_head streams;
1776 * The stream currently using the OA unit. If accessed
1777 * outside a syscall associated to its file
1778 * descriptor, you need to hold
1779 * dev_priv->drm.struct_mutex.
1781 struct i915_perf_stream *exclusive_stream;
1783 struct intel_context *pinned_ctx;
1784 u32 specific_ctx_id;
1785 u32 specific_ctx_id_mask;
1787 struct hrtimer poll_check_timer;
1788 wait_queue_head_t poll_wq;
1792 * For rate limiting any notifications of spurious
1793 * invalid OA reports
1795 struct ratelimit_state spurious_report_rs;
1798 int period_exponent;
1800 struct i915_oa_config test_config;
1803 struct i915_vma *vma;
1810 * Locks reads and writes to all head/tail state
1812 * Consider: the head and tail pointer state
1813 * needs to be read consistently from a hrtimer
1814 * callback (atomic context) and read() fop
1815 * (user context) with tail pointer updates
1816 * happening in atomic context and head updates
1817 * in user context and the (unlikely)
1818 * possibility of read() errors needing to
1819 * reset all head/tail state.
1821 * Note: Contention or performance aren't
1822 * currently a significant concern here
1823 * considering the relatively low frequency of
1824 * hrtimer callbacks (5ms period) and that
1825 * reads typically only happen in response to a
1826 * hrtimer event and likely complete before the
1829 * Note: This lock is not held *while* reading
1830 * and copying data to userspace so the value
1831 * of head observed in htrimer callbacks won't
1832 * represent any partial consumption of data.
1834 spinlock_t ptr_lock;
1837 * One 'aging' tail pointer and one 'aged'
1838 * tail pointer ready to used for reading.
1840 * Initial values of 0xffffffff are invalid
1841 * and imply that an update is required
1842 * (and should be ignored by an attempted
1850 * Index for the aged tail ready to read()
1853 unsigned int aged_tail_idx;
1856 * A monotonic timestamp for when the current
1857 * aging tail pointer was read; used to
1858 * determine when it is old enough to trust.
1860 u64 aging_timestamp;
1863 * Although we can always read back the head
1864 * pointer register, we prefer to avoid
1865 * trusting the HW state, just to avoid any
1866 * risk that some hardware condition could
1867 * somehow bump the head pointer unpredictably
1868 * and cause us to forward the wrong OA buffer
1869 * data to userspace.
1874 u32 gen7_latched_oastatus1;
1875 u32 ctx_oactxctrl_offset;
1876 u32 ctx_flexeu0_offset;
1879 * The RPT_ID/reason field for Gen8+ includes a bit
1880 * to determine if the CTX ID in the report is valid
1881 * but the specific bit differs between Gen 8 and 9
1883 u32 gen8_valid_ctx_bit;
1885 struct i915_oa_ops ops;
1886 const struct i915_oa_format *oa_formats;
1890 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1892 struct i915_gt_timelines {
1893 struct mutex mutex; /* protects list, tainted by GPU */
1894 struct list_head active_list;
1896 /* Pack multiple timelines' seqnos into the same page */
1897 spinlock_t hwsp_lock;
1898 struct list_head hwsp_free_list;
1901 struct list_head active_rings;
1903 struct intel_wakeref wakeref;
1905 struct list_head closed_vma;
1906 spinlock_t closed_lock; /* guards the list of closed_vma */
1909 * Is the GPU currently considered idle, or busy executing
1910 * userspace requests? Whilst idle, we allow runtime power
1911 * management to power down the hardware and display clocks.
1912 * In order to reduce the effect on performance, there
1913 * is a slight delay before we do so.
1915 intel_wakeref_t awake;
1917 struct blocking_notifier_head pm_notifications;
1919 ktime_t last_init_time;
1921 struct i915_vma *scratch;
1924 * We must never wait on the GPU while holding a lock as we
1925 * may need to perform a GPU reset. So while we don't need to
1926 * serialise wait/reset with an explicit lock, we do want
1927 * lockdep to detect potential dependency cycles.
1929 struct lockdep_map reset_lockmap;
1933 struct notifier_block pm_notifier;
1936 * We leave the user IRQ off as much as possible,
1937 * but this means that requests will finish and never
1938 * be retired once the system goes idle. Set a timer to
1939 * fire periodically while the ring is running. When it
1940 * fires, go retire requests.
1942 struct delayed_work retire_work;
1945 * When we detect an idle GPU, we want to turn on
1946 * powersaving features. So once we see that there
1947 * are no more requests outstanding and no more
1948 * arrive within a small period of time, we fire
1949 * off the idle_work.
1951 struct work_struct idle_work;
1954 /* For i945gm vblank irq vs. C3 workaround */
1956 struct work_struct work;
1957 struct pm_qos_request pm_qos;
1958 u8 c3_disable_latency;
1962 /* perform PHY state sanity checks? */
1963 bool chv_phy_assert[2];
1967 /* Used to save the pipe-to-encoder mapping for audio */
1968 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1970 /* necessary resource sharing with HDMI LPE audio driver. */
1972 struct platform_device *platdev;
1976 struct i915_pmu pmu;
1978 struct i915_hdcp_comp_master *hdcp_master;
1979 bool hdcp_comp_added;
1981 /* Mutex to protect the above hdcp component related values. */
1982 struct mutex hdcp_comp_mutex;
1985 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1986 * will be rejected. Instead look for a better place.
1990 struct dram_dimm_info {
1991 u8 size, width, ranks;
1994 struct dram_channel_info {
1995 struct dram_dimm_info dimm_l, dimm_s;
2000 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2002 return container_of(dev, struct drm_i915_private, drm);
2005 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2007 return to_i915(dev_get_drvdata(kdev));
2010 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2012 return container_of(wopcm, struct drm_i915_private, wopcm);
2015 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2017 return container_of(guc, struct drm_i915_private, guc);
2020 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2022 return container_of(huc, struct drm_i915_private, huc);
2025 static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
2027 return container_of(uncore, struct drm_i915_private, uncore);
2030 /* Simple iterator over all initialised engines */
2031 #define for_each_engine(engine__, dev_priv__, id__) \
2033 (id__) < I915_NUM_ENGINES; \
2035 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2037 /* Iterator over subset of engines selected by mask */
2038 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2039 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
2041 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2044 enum hdmi_force_audio {
2045 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2046 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2047 HDMI_AUDIO_AUTO, /* trust EDID */
2048 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2051 #define I915_GTT_OFFSET_NONE ((u32)-1)
2054 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2055 * considered to be the frontbuffer for the given plane interface-wise. This
2056 * doesn't mean that the hw necessarily already scans it out, but that any
2057 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2059 * We have one bit per pipe and per scanout plane type.
2061 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2062 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2063 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2064 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2065 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2067 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2068 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2069 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2070 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2071 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2073 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
2074 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2075 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2077 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
2078 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2080 #define REVID_FOREVER 0xff
2081 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2083 #define INTEL_GEN_MASK(s, e) ( \
2084 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2085 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2086 GENMASK((e) - 1, (s) - 1))
2088 /* Returns true if Gen is in inclusive range [Start, End] */
2089 #define IS_GEN_RANGE(dev_priv, s, e) \
2090 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2092 #define IS_GEN(dev_priv, n) \
2093 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2094 INTEL_INFO(dev_priv)->gen == (n))
2097 * Return true if revision is in range [since,until] inclusive.
2099 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2101 #define IS_REVID(p, since, until) \
2102 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2104 static __always_inline unsigned int
2105 __platform_mask_index(const struct intel_runtime_info *info,
2106 enum intel_platform p)
2108 const unsigned int pbits =
2109 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2111 /* Expand the platform_mask array if this fails. */
2112 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
2113 pbits * ARRAY_SIZE(info->platform_mask));
2118 static __always_inline unsigned int
2119 __platform_mask_bit(const struct intel_runtime_info *info,
2120 enum intel_platform p)
2122 const unsigned int pbits =
2123 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2125 return p % pbits + INTEL_SUBPLATFORM_BITS;
2129 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
2131 const unsigned int pi = __platform_mask_index(info, p);
2133 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
2136 static __always_inline bool
2137 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
2139 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2140 const unsigned int pi = __platform_mask_index(info, p);
2141 const unsigned int pb = __platform_mask_bit(info, p);
2143 BUILD_BUG_ON(!__builtin_constant_p(p));
2145 return info->platform_mask[pi] & BIT(pb);
2148 static __always_inline bool
2149 IS_SUBPLATFORM(const struct drm_i915_private *i915,
2150 enum intel_platform p, unsigned int s)
2152 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2153 const unsigned int pi = __platform_mask_index(info, p);
2154 const unsigned int pb = __platform_mask_bit(info, p);
2155 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
2156 const u32 mask = info->platform_mask[pi];
2158 BUILD_BUG_ON(!__builtin_constant_p(p));
2159 BUILD_BUG_ON(!__builtin_constant_p(s));
2160 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
2162 /* Shift and test on the MSB position so sign flag can be used. */
2163 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
2166 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
2168 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2169 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2170 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2171 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2172 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2173 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2174 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2175 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2176 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2177 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2178 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2179 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2180 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2181 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2182 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2183 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
2184 #define IS_IRONLAKE_M(dev_priv) \
2185 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
2186 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2187 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2188 INTEL_INFO(dev_priv)->gt == 1)
2189 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2190 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2191 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2192 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2193 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2194 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2195 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2196 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2197 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2198 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2199 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2200 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
2201 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2202 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2203 #define IS_BDW_ULT(dev_priv) \
2204 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
2205 #define IS_BDW_ULX(dev_priv) \
2206 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
2207 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2208 INTEL_INFO(dev_priv)->gt == 3)
2209 #define IS_HSW_ULT(dev_priv) \
2210 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
2211 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2212 INTEL_INFO(dev_priv)->gt == 3)
2213 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2214 INTEL_INFO(dev_priv)->gt == 1)
2215 /* ULX machines are also considered ULT. */
2216 #define IS_HSW_ULX(dev_priv) \
2217 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
2218 #define IS_SKL_ULT(dev_priv) \
2219 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
2220 #define IS_SKL_ULX(dev_priv) \
2221 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
2222 #define IS_KBL_ULT(dev_priv) \
2223 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
2224 #define IS_KBL_ULX(dev_priv) \
2225 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
2226 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2227 INTEL_INFO(dev_priv)->gt == 2)
2228 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2229 INTEL_INFO(dev_priv)->gt == 3)
2230 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2231 INTEL_INFO(dev_priv)->gt == 4)
2232 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2233 INTEL_INFO(dev_priv)->gt == 2)
2234 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2235 INTEL_INFO(dev_priv)->gt == 3)
2236 #define IS_CFL_ULT(dev_priv) \
2237 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2238 #define IS_CFL_ULX(dev_priv) \
2239 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
2240 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2241 INTEL_INFO(dev_priv)->gt == 2)
2242 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2243 INTEL_INFO(dev_priv)->gt == 3)
2244 #define IS_CNL_WITH_PORT_F(dev_priv) \
2245 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2246 #define IS_ICL_WITH_PORT_F(dev_priv) \
2247 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2249 #define SKL_REVID_A0 0x0
2250 #define SKL_REVID_B0 0x1
2251 #define SKL_REVID_C0 0x2
2252 #define SKL_REVID_D0 0x3
2253 #define SKL_REVID_E0 0x4
2254 #define SKL_REVID_F0 0x5
2255 #define SKL_REVID_G0 0x6
2256 #define SKL_REVID_H0 0x7
2258 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2260 #define BXT_REVID_A0 0x0
2261 #define BXT_REVID_A1 0x1
2262 #define BXT_REVID_B0 0x3
2263 #define BXT_REVID_B_LAST 0x8
2264 #define BXT_REVID_C0 0x9
2266 #define IS_BXT_REVID(dev_priv, since, until) \
2267 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2269 #define KBL_REVID_A0 0x0
2270 #define KBL_REVID_B0 0x1
2271 #define KBL_REVID_C0 0x2
2272 #define KBL_REVID_D0 0x3
2273 #define KBL_REVID_E0 0x4
2275 #define IS_KBL_REVID(dev_priv, since, until) \
2276 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2278 #define GLK_REVID_A0 0x0
2279 #define GLK_REVID_A1 0x1
2281 #define IS_GLK_REVID(dev_priv, since, until) \
2282 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2284 #define CNL_REVID_A0 0x0
2285 #define CNL_REVID_B0 0x1
2286 #define CNL_REVID_C0 0x2
2288 #define IS_CNL_REVID(p, since, until) \
2289 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2291 #define ICL_REVID_A0 0x0
2292 #define ICL_REVID_A2 0x1
2293 #define ICL_REVID_B0 0x3
2294 #define ICL_REVID_B2 0x4
2295 #define ICL_REVID_C0 0x5
2297 #define IS_ICL_REVID(p, since, until) \
2298 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2300 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2301 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2302 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2304 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2306 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
2307 unsigned int first__ = (first); \
2308 unsigned int count__ = (count); \
2309 (INTEL_INFO(dev_priv)->engine_mask & \
2310 GENMASK(first__ + count__ - 1, first__)) >> first__; \
2312 #define VDBOX_MASK(dev_priv) \
2313 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2314 #define VEBOX_MASK(dev_priv) \
2315 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2317 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2318 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2319 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
2320 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2321 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2323 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2325 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2326 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2327 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2328 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2329 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2330 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2332 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2334 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2335 #define HAS_PPGTT(dev_priv) \
2336 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2337 #define HAS_FULL_PPGTT(dev_priv) \
2338 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2340 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2341 GEM_BUG_ON((sizes) == 0); \
2342 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2345 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2346 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2347 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2349 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2350 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2352 /* WaRsDisableCoarsePowerGating:skl,cnl */
2353 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2354 (IS_CANNONLAKE(dev_priv) || \
2355 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2357 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2358 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2359 IS_GEMINILAKE(dev_priv) || \
2360 IS_KABYLAKE(dev_priv))
2362 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2363 * rows, which changed the alignment requirements and fence programming.
2365 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2366 !(IS_I915G(dev_priv) || \
2367 IS_I915GM(dev_priv)))
2368 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2369 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2371 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2372 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2373 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2375 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2377 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2379 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2380 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2381 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2382 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2384 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2385 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2386 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2388 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
2390 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2392 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2393 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2395 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2398 * For now, anything with a GuC requires uCode loading, and then supports
2399 * command submission once loaded. But these are logically independent
2400 * properties, so we have separate macros to test them.
2402 #define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
2403 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2404 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2406 /* For now, anything with a GuC has also HuC */
2407 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2408 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2410 /* Having a GuC is not the same as using a GuC */
2411 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2412 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2413 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2415 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2417 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2418 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2419 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2420 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2421 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2422 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2423 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2424 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2425 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2426 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2427 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2428 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2429 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2430 #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
2431 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2432 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2433 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2434 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2436 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2437 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2438 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2439 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2440 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2441 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2442 #define HAS_PCH_LPT_LP(dev_priv) \
2443 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2444 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2445 #define HAS_PCH_LPT_H(dev_priv) \
2446 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2447 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2448 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2449 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2450 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2451 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2453 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2455 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2457 /* DPF == dynamic parity feature */
2458 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2459 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2460 2 : HAS_L3_DPF(dev_priv))
2462 #define GT_FREQUENCY_MULTIPLIER 50
2463 #define GEN9_FREQ_SCALER 3
2465 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2467 #include "i915_trace.h"
2469 static inline bool intel_vtd_active(void)
2471 #ifdef CONFIG_INTEL_IOMMU
2472 if (intel_iommu_gfx_mapped)
2478 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2480 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2484 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2486 return IS_BROXTON(dev_priv) && intel_vtd_active();
2491 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2492 const char *fmt, ...);
2494 #define i915_report_error(dev_priv, fmt, ...) \
2495 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2497 #ifdef CONFIG_COMPAT
2498 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2501 #define i915_compat_ioctl NULL
2503 extern const struct dev_pm_ops i915_pm_ops;
2505 extern int i915_driver_load(struct pci_dev *pdev,
2506 const struct pci_device_id *ent);
2507 extern void i915_driver_unload(struct drm_device *dev);
2509 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2510 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2511 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2513 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2515 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2517 unsigned long delay;
2519 if (unlikely(!i915_modparams.enable_hangcheck))
2522 /* Don't continually defer the hangcheck so that it is always run at
2523 * least once after work has been scheduled on any ring. Otherwise,
2524 * we will ignore a hung ring if a second ring is kept busy.
2527 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2528 queue_delayed_work(system_long_wq,
2529 &dev_priv->gpu_error.hangcheck_work, delay);
2532 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2534 return dev_priv->gvt;
2537 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2539 return dev_priv->vgpu.active;
2543 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2544 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2545 void i915_gem_sanitize(struct drm_i915_private *i915);
2546 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2547 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2548 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2549 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2550 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2552 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2554 if (!atomic_read(&i915->mm.free_count))
2557 /* A single pass should suffice to release all the freed objects (along
2558 * most call paths) , but be a little more paranoid in that freeing
2559 * the objects does take a little amount of time, during which the rcu
2560 * callbacks could have added new objects into the freed list, and
2561 * armed the work again.
2565 } while (flush_work(&i915->mm.free_work));
2568 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2571 * Similar to objects above (see i915_gem_drain_freed-objects), in
2572 * general we have workers that are armed by RCU and then rearm
2573 * themselves in their callbacks. To be paranoid, we need to
2574 * drain the workqueue a second time after waiting for the RCU
2575 * grace period so that we catch work queued via RCU from the first
2576 * pass. As neither drain_workqueue() nor flush_workqueue() report
2577 * a result, we make an assumption that we only don't require more
2578 * than 3 passes to catch all _recursive_ RCU delayed work.
2584 i915_gem_drain_freed_objects(i915);
2586 drain_workqueue(i915->wq);
2589 struct i915_vma * __must_check
2590 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2591 const struct i915_ggtt_view *view,
2596 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2598 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2600 static inline int __must_check
2601 i915_mutex_lock_interruptible(struct drm_device *dev)
2603 return mutex_lock_interruptible(&dev->struct_mutex);
2606 int i915_gem_dumb_create(struct drm_file *file_priv,
2607 struct drm_device *dev,
2608 struct drm_mode_create_dumb *args);
2609 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2610 u32 handle, u64 *offset);
2611 int i915_gem_mmap_gtt_version(void);
2613 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2614 struct drm_i915_gem_object *new,
2615 unsigned frontbuffer_bits);
2617 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
2619 static inline bool __i915_wedged(struct i915_gpu_error *error)
2621 return unlikely(test_bit(I915_WEDGED, &error->flags));
2624 static inline bool i915_reset_failed(struct drm_i915_private *i915)
2626 return __i915_wedged(&i915->gpu_error);
2629 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2631 return READ_ONCE(error->reset_count);
2634 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
2635 struct intel_engine_cs *engine)
2637 return READ_ONCE(error->reset_engine_count[engine->id]);
2640 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
2641 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
2643 void i915_gem_init_mmio(struct drm_i915_private *i915);
2644 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
2645 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
2646 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
2647 void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
2648 void i915_gem_fini(struct drm_i915_private *dev_priv);
2649 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
2650 unsigned int flags, long timeout);
2651 void i915_gem_suspend(struct drm_i915_private *dev_priv);
2652 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
2653 void i915_gem_resume(struct drm_i915_private *dev_priv);
2654 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
2656 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
2657 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2659 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2660 enum i915_cache_level cache_level);
2662 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2663 struct dma_buf *dma_buf);
2665 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2666 struct drm_gem_object *gem_obj, int flags);
2668 /* i915_gem_fence_reg.c */
2669 struct drm_i915_fence_reg *
2670 i915_reserve_fence(struct drm_i915_private *dev_priv);
2671 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
2673 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
2675 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
2676 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
2677 struct sg_table *pages);
2678 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
2679 struct sg_table *pages);
2681 static inline struct i915_gem_context *
2682 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
2684 return idr_find(&file_priv->context_idr, id);
2687 static inline struct i915_gem_context *
2688 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2690 struct i915_gem_context *ctx;
2693 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
2694 if (ctx && !kref_get_unless_zero(&ctx->ref))
2701 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
2702 struct drm_file *file);
2703 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
2704 struct drm_file *file);
2705 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
2706 struct drm_file *file);
2707 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
2708 struct intel_context *ce,
2711 /* i915_gem_evict.c */
2712 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
2713 u64 min_size, u64 alignment,
2714 unsigned cache_level,
2717 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
2718 struct drm_mm_node *node,
2719 unsigned int flags);
2720 int i915_gem_evict_vm(struct i915_address_space *vm);
2722 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
2724 /* belongs in i915_gem_gtt.h */
2725 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
2728 if (INTEL_GEN(dev_priv) < 6)
2729 intel_gtt_chipset_flush();
2732 /* i915_gem_stolen.c */
2733 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
2734 struct drm_mm_node *node, u64 size,
2735 unsigned alignment);
2736 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
2737 struct drm_mm_node *node, u64 size,
2738 unsigned alignment, u64 start,
2740 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
2741 struct drm_mm_node *node);
2742 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
2743 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
2744 struct drm_i915_gem_object *
2745 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
2746 resource_size_t size);
2747 struct drm_i915_gem_object *
2748 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
2749 resource_size_t stolen_offset,
2750 resource_size_t gtt_offset,
2751 resource_size_t size);
2753 /* i915_gem_internal.c */
2754 struct drm_i915_gem_object *
2755 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2758 /* i915_gem_shrinker.c */
2759 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
2760 unsigned long target,
2761 unsigned long *nr_scanned,
2763 #define I915_SHRINK_UNBOUND BIT(0)
2764 #define I915_SHRINK_BOUND BIT(1)
2765 #define I915_SHRINK_ACTIVE BIT(2)
2766 #define I915_SHRINK_VMAPS BIT(3)
2767 #define I915_SHRINK_WRITEBACK BIT(4)
2769 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
2770 void i915_gem_shrinker_register(struct drm_i915_private *i915);
2771 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
2772 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
2773 struct mutex *mutex);
2775 /* i915_gem_tiling.c */
2776 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2778 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2780 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2781 i915_gem_object_is_tiled(obj);
2784 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2785 unsigned int tiling, unsigned int stride);
2786 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2787 unsigned int tiling, unsigned int stride);
2789 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2791 /* i915_cmd_parser.c */
2792 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2793 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2794 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
2795 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
2796 struct drm_i915_gem_object *batch_obj,
2797 struct drm_i915_gem_object *shadow_batch_obj,
2798 u32 batch_start_offset,
2803 extern void i915_perf_init(struct drm_i915_private *dev_priv);
2804 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
2805 extern void i915_perf_register(struct drm_i915_private *dev_priv);
2806 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
2808 /* i915_suspend.c */
2809 extern int i915_save_state(struct drm_i915_private *dev_priv);
2810 extern int i915_restore_state(struct drm_i915_private *dev_priv);
2813 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
2814 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
2816 /* intel_device_info.c */
2817 static inline struct intel_device_info *
2818 mkwrite_device_info(struct drm_i915_private *dev_priv)
2820 return (struct intel_device_info *)INTEL_INFO(dev_priv);
2824 extern void intel_modeset_init_hw(struct drm_device *dev);
2825 extern int intel_modeset_init(struct drm_device *dev);
2826 extern void intel_modeset_cleanup(struct drm_device *dev);
2827 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
2829 extern void intel_display_resume(struct drm_device *dev);
2830 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
2831 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
2832 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
2834 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2835 struct drm_file *file);
2837 extern struct intel_display_error_state *
2838 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
2839 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2840 struct intel_display_error_state *error);
2842 #define __I915_REG_OP(op__, dev_priv__, ...) \
2843 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2845 #define I915_READ8(reg__) __I915_REG_OP(read8, dev_priv, (reg__))
2847 #define I915_READ16(reg__) __I915_REG_OP(read16, dev_priv, (reg__))
2848 #define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))
2850 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
2851 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2852 #define I915_READ_NOTRACE(reg__) __I915_REG_OP(read_notrace, dev_priv, (reg__))
2853 #define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
2855 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
2856 #define POSTING_READ16(reg__) __I915_REG_OP(posting_read16, dev_priv, (reg__))
2858 /* These are untraced mmio-accessors that are only valid to be used inside
2859 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
2862 * Think twice, and think again, before using these.
2864 * As an example, these accessors can possibly be used between:
2866 * spin_lock_irq(&dev_priv->uncore.lock);
2867 * intel_uncore_forcewake_get__locked();
2871 * intel_uncore_forcewake_put__locked();
2872 * spin_unlock_irq(&dev_priv->uncore.lock);
2875 * Note: some registers may not need forcewake held, so
2876 * intel_uncore_forcewake_{get,put} can be omitted, see
2877 * intel_uncore_forcewake_for_reg().
2879 * Certain architectures will die if the same cacheline is concurrently accessed
2880 * by different clients (e.g. on Ivybridge). Access to registers should
2881 * therefore generally be serialised, by either the dev_priv->uncore.lock or
2882 * a more localised lock guarding all access to that bank of registers.
2884 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2885 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2886 #define POSTING_READ_FW(reg__) __I915_REG_OP(posting_read_fw, dev_priv, (reg__))
2888 /* "Broadcast RGB" property */
2889 #define INTEL_BROADCAST_RGB_AUTO 0
2890 #define INTEL_BROADCAST_RGB_FULL 1
2891 #define INTEL_BROADCAST_RGB_LIMITED 2
2893 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
2894 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
2896 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
2897 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
2898 * perform the operation. To check beforehand, pass in the parameters to
2899 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
2900 * you only need to pass in the minor offsets, page-aligned pointers are
2903 * For just checking for SSE4.1, in the foreknowledge that the future use
2904 * will be correctly aligned, just use i915_has_memcpy_from_wc().
2906 #define i915_can_memcpy_from_wc(dst, src, len) \
2907 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
2909 #define i915_has_memcpy_from_wc() \
2910 i915_memcpy_from_wc(NULL, NULL, 0)
2913 int remap_io_mapping(struct vm_area_struct *vma,
2914 unsigned long addr, unsigned long pfn, unsigned long size,
2915 struct io_mapping *iomap);
2917 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2919 if (INTEL_GEN(i915) >= 10)
2920 return CNL_HWS_CSB_WRITE_INDEX;
2922 return I915_HWS_CSB_WRITE_INDEX;
2925 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
2927 return i915_ggtt_offset(i915->gt.scratch);
2930 static inline enum i915_map_type
2931 i915_coherent_map_type(struct drm_i915_private *i915)
2933 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2936 static inline void add_taint_for_CI(unsigned int taint)
2939 * The system is "ok", just about surviving for the user, but
2940 * CI results are now unreliable as the HW is very suspect.
2941 * CI checks the taint state after every test and will reboot
2942 * the machine if the kernel is tainted.
2944 add_taint(taint, LOCKDEP_STILL_OK);