1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_atomic.h>
58 #include <drm/drm_connector.h>
59 #include <drm/i915_mei_hdcp_interface.h>
61 #include "i915_fixed.h"
62 #include "i915_params.h"
64 #include "i915_utils.h"
66 #include "gt/intel_lrc.h"
67 #include "gt/intel_engine.h"
68 #include "gt/intel_workarounds.h"
70 #include "intel_bios.h"
71 #include "intel_device_info.h"
72 #include "intel_display.h"
73 #include "intel_dpll_mgr.h"
74 #include "intel_frontbuffer.h"
75 #include "intel_opregion.h"
76 #include "intel_runtime_pm.h"
78 #include "intel_uncore.h"
79 #include "intel_wakeref.h"
80 #include "intel_wopcm.h"
83 #include "gem/i915_gem_context_types.h"
84 #include "i915_gem_fence_reg.h"
85 #include "i915_gem_gtt.h"
86 #include "i915_gpu_error.h"
87 #include "i915_request.h"
88 #include "i915_scheduler.h"
89 #include "i915_timeline.h"
92 #include "intel_gvt.h"
94 /* General customization:
97 #define DRIVER_NAME "i915"
98 #define DRIVER_DESC "Intel Graphics"
99 #define DRIVER_DATE "20190524"
100 #define DRIVER_TIMESTAMP 1558719322
102 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
103 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
104 * which may not necessarily be a user visible problem. This will either
105 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
106 * enable distros and users to tailor their preferred amount of i915 abrt
109 #define I915_STATE_WARN(condition, format...) ({ \
110 int __ret_warn_on = !!(condition); \
111 if (unlikely(__ret_warn_on)) \
112 if (!WARN(i915_modparams.verbose_state_checks, format)) \
114 unlikely(__ret_warn_on); \
117 #define I915_STATE_WARN_ON(x) \
118 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
120 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
122 bool __i915_inject_load_failure(const char *func, int line);
123 #define i915_inject_load_failure() \
124 __i915_inject_load_failure(__func__, __LINE__)
126 bool i915_error_injected(void);
130 #define i915_inject_load_failure() false
131 #define i915_error_injected() false
135 #define i915_load_error(i915, fmt, ...) \
136 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
139 struct drm_i915_gem_object;
143 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
156 #define for_each_hpd_pin(__pin) \
157 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
159 /* Threshold == 5 for long IRQs, 50 for short */
160 #define HPD_STORM_DEFAULT_THRESHOLD 50
162 struct i915_hotplug {
163 struct work_struct hotplug_work;
166 unsigned long last_jiffies;
171 HPD_MARK_DISABLED = 2
173 } stats[HPD_NUM_PINS];
175 struct delayed_work reenable_work;
179 struct work_struct dig_port_work;
181 struct work_struct poll_init_work;
184 unsigned int hpd_storm_threshold;
185 /* Whether or not to count short HPD IRQs in HPD storms */
186 u8 hpd_short_storm_enabled;
189 * if we get a HPD irq from DP and a HPD irq from non-DP
190 * the non-DP HPD could block the workqueue on a mode config
191 * mutex getting, that userspace may have taken. However
192 * userspace is waiting on the DP workqueue to run which is
193 * blocked behind the non-DP one.
195 struct workqueue_struct *dp_wq;
198 #define I915_GEM_GPU_DOMAINS \
199 (I915_GEM_DOMAIN_RENDER | \
200 I915_GEM_DOMAIN_SAMPLER | \
201 I915_GEM_DOMAIN_COMMAND | \
202 I915_GEM_DOMAIN_INSTRUCTION | \
203 I915_GEM_DOMAIN_VERTEX)
205 struct drm_i915_private;
206 struct i915_mm_struct;
207 struct i915_mmu_object;
209 struct drm_i915_file_private {
210 struct drm_i915_private *dev_priv;
211 struct drm_file *file;
215 struct list_head request_list;
216 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
217 * chosen to prevent the CPU getting more than a frame ahead of the GPU
218 * (when using lax throttling for the frontbuffer). We also use it to
219 * offer free GPU waitboosts for severely congested workloads.
221 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
224 struct idr context_idr;
225 struct mutex context_idr_lock; /* guards context_idr */
228 struct mutex vm_idr_lock; /* guards vm_idr */
230 unsigned int bsd_engine;
233 * Every context ban increments per client ban score. Also
234 * hangs in short succession increments ban score. If ban threshold
235 * is reached, client is considered banned and submitting more work
236 * will fail. This is a stop gap measure to limit the badly behaving
237 * clients access to gpu. Note that unbannable contexts never increment
238 * the client ban score.
240 #define I915_CLIENT_SCORE_HANG_FAST 1
241 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
242 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
243 #define I915_CLIENT_SCORE_BANNED 9
244 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
246 unsigned long hang_timestamp;
249 /* Interface history:
252 * 1.2: Add Power Management
253 * 1.3: Add vblank support
254 * 1.4: Fix cmdbuffer path, add heap destroy
255 * 1.5: Add vblank pipe configuration
256 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
257 * - Support vertical blank on secondary display pipe
259 #define DRIVER_MAJOR 1
260 #define DRIVER_MINOR 6
261 #define DRIVER_PATCHLEVEL 0
263 struct intel_overlay;
264 struct intel_overlay_error_state;
266 struct sdvo_device_mapping {
275 struct intel_connector;
276 struct intel_encoder;
277 struct intel_atomic_state;
278 struct intel_crtc_state;
279 struct intel_initial_plane_config;
283 struct intel_cdclk_state;
285 struct drm_i915_display_funcs {
286 void (*get_cdclk)(struct drm_i915_private *dev_priv,
287 struct intel_cdclk_state *cdclk_state);
288 void (*set_cdclk)(struct drm_i915_private *dev_priv,
289 const struct intel_cdclk_state *cdclk_state,
291 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
292 enum i9xx_plane_id i9xx_plane);
293 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
294 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
295 void (*initial_watermarks)(struct intel_atomic_state *state,
296 struct intel_crtc_state *cstate);
297 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
298 struct intel_crtc_state *cstate);
299 void (*optimize_watermarks)(struct intel_atomic_state *state,
300 struct intel_crtc_state *cstate);
301 int (*compute_global_watermarks)(struct intel_atomic_state *state);
302 void (*update_wm)(struct intel_crtc *crtc);
303 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
304 /* Returns the active state of the crtc, and if the crtc is active,
305 * fills out the pipe-config with the hw state. */
306 bool (*get_pipe_config)(struct intel_crtc *,
307 struct intel_crtc_state *);
308 void (*get_initial_plane_config)(struct intel_crtc *,
309 struct intel_initial_plane_config *);
310 int (*crtc_compute_clock)(struct intel_crtc *crtc,
311 struct intel_crtc_state *crtc_state);
312 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
313 struct drm_atomic_state *old_state);
314 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
315 struct drm_atomic_state *old_state);
316 void (*update_crtcs)(struct drm_atomic_state *state);
317 void (*audio_codec_enable)(struct intel_encoder *encoder,
318 const struct intel_crtc_state *crtc_state,
319 const struct drm_connector_state *conn_state);
320 void (*audio_codec_disable)(struct intel_encoder *encoder,
321 const struct intel_crtc_state *old_crtc_state,
322 const struct drm_connector_state *old_conn_state);
323 void (*fdi_link_train)(struct intel_crtc *crtc,
324 const struct intel_crtc_state *crtc_state);
325 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
326 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
327 /* clock updates for mode set */
329 /* render clock increase/decrease */
330 /* display clock increase/decrease */
331 /* pll clock increase/decrease */
333 int (*color_check)(struct intel_crtc_state *crtc_state);
335 * Program double buffered color management registers during
336 * vblank evasion. The registers should then latch during the
337 * next vblank start, alongside any other double buffered registers
338 * involved with the same commit.
340 void (*color_commit)(const struct intel_crtc_state *crtc_state);
342 * Load LUTs (and other single buffered color management
343 * registers). Will (hopefully) be called during the vblank
344 * following the latching of any double buffered registers
345 * involved with the same commit.
347 void (*load_luts)(const struct intel_crtc_state *crtc_state);
351 struct work_struct work;
353 u32 required_version;
354 u32 max_fw_size; /* bytes */
356 u32 dmc_fw_size; /* dwords */
359 i915_reg_t mmioaddr[8];
363 intel_wakeref_t wakeref;
366 enum i915_cache_level {
368 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
369 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
370 caches, eg sampler/render caches, and the
371 large Last-Level-Cache. LLC is coherent with
372 the CPU, but L3 is only visible to the GPU. */
373 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
376 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
379 /* This is always the inner lock when overlapping with struct_mutex and
380 * it's the outer lock when overlapping with stolen_lock. */
383 unsigned int possible_framebuffer_bits;
384 unsigned int busy_bits;
385 unsigned int visible_pipes_mask;
386 struct intel_crtc *crtc;
388 struct drm_mm_node compressed_fb;
389 struct drm_mm_node *compressed_llb;
397 bool underrun_detected;
398 struct work_struct underrun_work;
401 * Due to the atomic rules we can't access some structures without the
402 * appropriate locking, so we cache information here in order to avoid
405 struct intel_fbc_state_cache {
406 struct i915_vma *vma;
410 unsigned int mode_flags;
411 u32 hsw_bdw_pixel_rate;
415 unsigned int rotation;
420 * Display surface base address adjustement for
421 * pageflips. Note that on gen4+ this only adjusts up
422 * to a tile, offsets within a tile are handled in
423 * the hw itself (with the TILEOFF register).
430 u16 pixel_blend_mode;
434 const struct drm_format_info *format;
440 * This structure contains everything that's relevant to program the
441 * hardware registers. When we want to figure out if we need to disable
442 * and re-enable FBC for a new configuration we just check if there's
443 * something different in the struct. The genx_fbc_activate functions
444 * are supposed to read from it in order to program the registers.
446 struct intel_fbc_reg_params {
447 struct i915_vma *vma;
452 enum i9xx_plane_id i9xx_plane;
453 unsigned int fence_y_offset;
457 const struct drm_format_info *format;
462 unsigned int gen9_wa_cfb_stride;
465 const char *no_fbc_reason;
469 * HIGH_RR is the highest eDP panel refresh rate read from EDID
470 * LOW_RR is the lowest eDP panel refresh rate found from EDID
471 * parsing for same resolution.
473 enum drrs_refresh_rate_type {
476 DRRS_MAX_RR, /* RR count */
479 enum drrs_support_type {
480 DRRS_NOT_SUPPORTED = 0,
481 STATIC_DRRS_SUPPORT = 1,
482 SEAMLESS_DRRS_SUPPORT = 2
488 struct delayed_work work;
490 unsigned busy_frontbuffer_bits;
491 enum drrs_refresh_rate_type refresh_rate_type;
492 enum drrs_support_type type;
498 #define I915_PSR_DEBUG_MODE_MASK 0x0f
499 #define I915_PSR_DEBUG_DEFAULT 0x00
500 #define I915_PSR_DEBUG_DISABLE 0x01
501 #define I915_PSR_DEBUG_ENABLE 0x02
502 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
503 #define I915_PSR_DEBUG_IRQ 0x10
511 struct work_struct work;
512 unsigned busy_frontbuffer_bits;
513 bool sink_psr2_support;
515 bool colorimetry_support;
517 u8 sink_sync_latency;
518 ktime_t last_entry_attempt;
520 bool sink_not_reliable;
522 u16 su_x_granularity;
526 * Sorted by south display engine compatibility.
527 * If the new PCH comes with a south display engine that is not
528 * inherited from the latest item, please do not add it to the
529 * end. Instead, add it right after its "parent" PCH.
532 PCH_NOP = -1, /* PCH without south display */
533 PCH_NONE = 0, /* No PCH present */
534 PCH_IBX, /* Ibexpeak PCH */
535 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
536 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
537 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
538 PCH_CNP, /* Cannon/Comet Lake PCH */
539 PCH_ICP, /* Ice Lake PCH */
542 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
543 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
544 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
545 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
546 #define QUIRK_INCREASE_T12_DELAY (1<<6)
547 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
550 struct intel_fbc_work;
553 struct i2c_adapter adapter;
554 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
558 struct i2c_algo_bit_data bit_algo;
559 struct drm_i915_private *dev_priv;
562 struct i915_suspend_saved_registers {
565 u32 saveCACHE_MODE_0;
566 u32 saveMI_ARB_STATE;
570 u64 saveFENCE[I915_MAX_NUM_FENCES];
571 u32 savePCH_PORT_HOTPLUG;
575 struct vlv_s0ix_state {
582 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
583 u32 media_max_req_count;
584 u32 gfx_max_req_count;
616 /* Display 1 CZ domain */
621 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
623 /* GT SA CZ domain */
630 /* Display 2 CZ domain */
637 struct intel_rps_ei {
644 struct mutex lock; /* protects enabling and the worker */
647 * work, interrupts_enabled and pm_iir are protected by
650 struct work_struct work;
651 bool interrupts_enabled;
654 /* PM interrupt bits that should never be masked */
657 /* Frequencies are stored in potentially platform dependent multiples.
658 * In other words, *_freq needs to be multiplied by X to be interesting.
659 * Soft limits are those which are used for the dynamic reclocking done
660 * by the driver (raise frequencies under heavy loads, and lower for
661 * lighter loads). Hard limits are those imposed by the hardware.
663 * A distinction is made for overclocking, which is never enabled by
664 * default, and is considered to be above the hard limit if it's
667 u8 cur_freq; /* Current frequency (cached, may not == HW) */
668 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
669 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
670 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
671 u8 min_freq; /* AKA RPn. Minimum frequency */
672 u8 boost_freq; /* Frequency to request when wait boosting */
673 u8 idle_freq; /* Frequency to request when we are idle */
674 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
675 u8 rp1_freq; /* "less than" RP0 power/freqency */
676 u8 rp0_freq; /* Non-overclocked max frequency. */
677 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
684 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
685 unsigned int interactive;
687 u8 up_threshold; /* Current %busy required to uplock */
688 u8 down_threshold; /* Current %busy required to downclock */
692 atomic_t num_waiters;
695 /* manual wa residency calculations */
696 struct intel_rps_ei ei;
701 u64 prev_hw_residency[4];
702 u64 cur_residency[4];
705 struct intel_llc_pstate {
709 struct intel_gen6_power_mgmt {
710 struct intel_rps rps;
711 struct intel_rc6 rc6;
712 struct intel_llc_pstate llc_pstate;
715 /* defined intel_pm.c */
716 extern spinlock_t mchdev_lock;
718 struct intel_ilk_power_mgmt {
726 unsigned long last_time1;
727 unsigned long chipset_power;
730 unsigned long gfx_power;
737 struct drm_i915_private;
738 struct i915_power_well;
740 struct i915_power_well_ops {
742 * Synchronize the well's hw state to match the current sw state, for
743 * example enable/disable it based on the current refcount. Called
744 * during driver init and resume time, possibly after first calling
745 * the enable/disable handlers.
747 void (*sync_hw)(struct drm_i915_private *dev_priv,
748 struct i915_power_well *power_well);
750 * Enable the well and resources that depend on it (for example
751 * interrupts located on the well). Called after the 0->1 refcount
754 void (*enable)(struct drm_i915_private *dev_priv,
755 struct i915_power_well *power_well);
757 * Disable the well and resources that depend on it. Called after
758 * the 1->0 refcount transition.
760 void (*disable)(struct drm_i915_private *dev_priv,
761 struct i915_power_well *power_well);
762 /* Returns the hw enabled state. */
763 bool (*is_enabled)(struct drm_i915_private *dev_priv,
764 struct i915_power_well *power_well);
767 struct i915_power_well_regs {
774 /* Power well structure for haswell */
775 struct i915_power_well_desc {
779 /* unique identifier for this power well */
780 enum i915_power_well_id id;
782 * Arbitraty data associated with this power well. Platform and power
788 * request/status flag index in the PUNIT power well
789 * control/status registers.
797 const struct i915_power_well_regs *regs;
799 * request/status flag index in the power well
800 * constrol/status registers.
803 /* Mask of pipes whose IRQ logic is backed by the pw */
805 /* The pw is backing the VGA functionality */
809 * The pw is for an ICL+ TypeC PHY port in
815 const struct i915_power_well_ops *ops;
818 struct i915_power_well {
819 const struct i915_power_well_desc *desc;
820 /* power well enable/disable usage count */
822 /* cached hw enabled state */
826 struct i915_power_domains {
828 * Power wells needed for initialization at driver init and suspend
829 * time are on. They are kept on until after the first modeset.
832 bool display_core_suspended;
833 int power_well_count;
835 intel_wakeref_t wakeref;
838 int domain_use_count[POWER_DOMAIN_NUM];
840 struct delayed_work async_put_work;
841 intel_wakeref_t async_put_wakeref;
842 u64 async_put_domains[2];
844 struct i915_power_well *power_wells;
847 #define MAX_L3_SLICES 2
848 struct intel_l3_parity {
849 u32 *remap_info[MAX_L3_SLICES];
850 struct work_struct error_work;
855 /** Memory allocator for GTT stolen memory */
856 struct drm_mm stolen;
857 /** Protects the usage of the GTT stolen memory allocator. This is
858 * always the inner lock when overlapping with struct_mutex. */
859 struct mutex stolen_lock;
861 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
864 /** List of all objects in gtt_space. Used to restore gtt
865 * mappings on resume */
866 struct list_head bound_list;
868 * List of objects which are not bound to the GTT (thus
869 * are idle and not used by the GPU). These objects may or may
870 * not actually have any pages attached.
872 struct list_head unbound_list;
874 /** List of all objects in gtt_space, currently mmaped by userspace.
875 * All objects within this list must also be on bound_list.
877 struct list_head userfault_list;
879 /* Manual runtime pm autosuspend delay for user GGTT mmaps */
880 struct intel_wakeref_auto userfault_wakeref;
883 * List of objects which are pending destruction.
885 struct llist_head free_list;
886 struct work_struct free_work;
887 spinlock_t free_lock;
889 * Count of objects pending destructions. Used to skip needlessly
890 * waiting on an RCU barrier if no objects are waiting to be freed.
895 * Small stash of WC pages
897 struct pagestash wc_stash;
900 * tmpfs instance used for shmem backed objects
902 struct vfsmount *gemfs;
904 /** PPGTT used for aliasing the PPGTT with the GTT */
905 struct i915_hw_ppgtt *aliasing_ppgtt;
907 struct notifier_block oom_notifier;
908 struct notifier_block vmap_notifier;
909 struct shrinker shrinker;
911 /** LRU list of objects with fence regs on them. */
912 struct list_head fence_list;
915 * Workqueue to fault in userptr pages, flushed by the execbuf
916 * when required but otherwise left to userspace to try again
919 struct workqueue_struct *userptr_wq;
921 u64 unordered_timeline;
923 /* the indicator for dispatch video commands on two BSD rings */
924 atomic_t bsd_engine_dispatch_index;
926 /** Bit 6 swizzling required for X tiling */
928 /** Bit 6 swizzling required for Y tiling */
931 /* accounting, useful for userland debugging */
932 spinlock_t object_stat_lock;
937 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
939 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
940 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
942 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
943 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
945 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
947 struct ddi_vbt_port_info {
951 * This is an index in the HDMI/DVI DDI buffer translation table.
952 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
953 * populate this field.
955 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
963 u8 supports_typec_usb:1;
966 u8 alternate_aux_channel;
967 u8 alternate_ddc_pin;
971 int dp_max_link_rate; /* 0 for not limited by VBT */
974 enum psr_lines_to_wait {
975 PSR_0_LINES_TO_WAIT = 0,
981 struct intel_vbt_data {
982 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
983 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
986 unsigned int int_tv_support:1;
987 unsigned int lvds_dither:1;
988 unsigned int int_crt_support:1;
989 unsigned int lvds_use_ssc:1;
990 unsigned int int_lvds_support:1;
991 unsigned int display_clock_mode:1;
992 unsigned int fdi_rx_polarity_inverted:1;
993 unsigned int panel_type:4;
995 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
996 enum drm_panel_orientation orientation;
998 enum drrs_support_type drrs_type;
1008 struct edp_power_seq pps;
1014 bool require_aux_wakeup;
1016 enum psr_lines_to_wait lines_to_wait;
1017 int tp1_wakeup_time_us;
1018 int tp2_tp3_wakeup_time_us;
1019 int psr2_tp2_tp3_wakeup_time_us;
1025 bool active_low_pwm;
1026 u8 min_brightness; /* min_brightness/255 of max */
1027 u8 controller; /* brightness controller number */
1028 enum intel_backlight_type type;
1034 struct mipi_config *config;
1035 struct mipi_pps_data *pps;
1041 const u8 *sequence[MIPI_SEQ_MAX];
1042 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1043 enum drm_panel_orientation orientation;
1049 struct child_device_config *child_dev;
1051 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1052 struct sdvo_device_mapping sdvo_mappings[2];
1055 enum intel_ddb_partitioning {
1057 INTEL_DDB_PART_5_6, /* IVB+ */
1060 struct intel_wm_level {
1068 struct ilk_wm_values {
1074 enum intel_ddb_partitioning partitioning;
1077 struct g4x_pipe_wm {
1078 u16 plane[I915_MAX_PLANES];
1088 struct vlv_wm_ddl_values {
1089 u8 plane[I915_MAX_PLANES];
1092 struct vlv_wm_values {
1093 struct g4x_pipe_wm pipe[3];
1094 struct g4x_sr_wm sr;
1095 struct vlv_wm_ddl_values ddl[3];
1100 struct g4x_wm_values {
1101 struct g4x_pipe_wm pipe[2];
1102 struct g4x_sr_wm sr;
1103 struct g4x_sr_wm hpll;
1109 struct skl_ddb_entry {
1110 u16 start, end; /* in number of blocks, 'end' is exclusive */
1113 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1115 return entry->end - entry->start;
1118 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1119 const struct skl_ddb_entry *e2)
1121 if (e1->start == e2->start && e1->end == e2->end)
1127 struct skl_ddb_allocation {
1128 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1131 struct skl_ddb_values {
1132 unsigned dirty_pipes;
1133 struct skl_ddb_allocation ddb;
1136 struct skl_wm_level {
1144 /* Stores plane specific WM parameters */
1145 struct skl_wm_params {
1146 bool x_tiled, y_tiled;
1151 u32 plane_pixel_rate;
1152 u32 y_min_scanlines;
1153 u32 plane_bytes_per_line;
1154 uint_fixed_16_16_t plane_blocks_per_line;
1155 uint_fixed_16_16_t y_tile_minimum;
1157 u32 dbuf_block_size;
1161 * This struct helps tracking the state needed for runtime PM, which puts the
1162 * device in PCI D3 state. Notice that when this happens, nothing on the
1163 * graphics device works, even register access, so we don't get interrupts nor
1166 * Every piece of our code that needs to actually touch the hardware needs to
1167 * either call intel_runtime_pm_get or call intel_display_power_get with the
1168 * appropriate power domain.
1170 * Our driver uses the autosuspend delay feature, which means we'll only really
1171 * suspend if we stay with zero refcount for a certain amount of time. The
1172 * default value is currently very conservative (see intel_runtime_pm_enable), but
1173 * it can be changed with the standard runtime PM files from sysfs.
1175 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1176 * goes back to false exactly before we reenable the IRQs. We use this variable
1177 * to check if someone is trying to enable/disable IRQs while they're supposed
1178 * to be disabled. This shouldn't happen and we'll print some error messages in
1181 * For more, read the Documentation/power/runtime_pm.txt.
1183 struct i915_runtime_pm {
1184 atomic_t wakeref_count;
1188 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1190 * To aide detection of wakeref leaks and general misuse, we
1191 * track all wakeref holders. With manual markup (i.e. returning
1192 * a cookie to each rpm_get caller which they then supply to their
1193 * paired rpm_put) we can remove corresponding pairs of and keep
1194 * the array trimmed to active wakerefs.
1196 struct intel_runtime_pm_debug {
1199 depot_stack_handle_t last_acquire;
1200 depot_stack_handle_t last_release;
1202 depot_stack_handle_t *owners;
1203 unsigned long count;
1208 enum intel_pipe_crc_source {
1209 INTEL_PIPE_CRC_SOURCE_NONE,
1210 INTEL_PIPE_CRC_SOURCE_PLANE1,
1211 INTEL_PIPE_CRC_SOURCE_PLANE2,
1212 INTEL_PIPE_CRC_SOURCE_PLANE3,
1213 INTEL_PIPE_CRC_SOURCE_PLANE4,
1214 INTEL_PIPE_CRC_SOURCE_PLANE5,
1215 INTEL_PIPE_CRC_SOURCE_PLANE6,
1216 INTEL_PIPE_CRC_SOURCE_PLANE7,
1217 INTEL_PIPE_CRC_SOURCE_PIPE,
1218 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1219 INTEL_PIPE_CRC_SOURCE_TV,
1220 INTEL_PIPE_CRC_SOURCE_DP_B,
1221 INTEL_PIPE_CRC_SOURCE_DP_C,
1222 INTEL_PIPE_CRC_SOURCE_DP_D,
1223 INTEL_PIPE_CRC_SOURCE_AUTO,
1224 INTEL_PIPE_CRC_SOURCE_MAX,
1227 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1228 struct intel_pipe_crc {
1231 enum intel_pipe_crc_source source;
1234 struct i915_frontbuffer_tracking {
1238 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1245 struct i915_virtual_gpu {
1250 /* used in computing the new watermarks state */
1251 struct intel_wm_config {
1252 unsigned int num_pipes_active;
1253 bool sprites_enabled;
1254 bool sprites_scaled;
1257 struct i915_oa_format {
1262 struct i915_oa_reg {
1267 struct i915_oa_config {
1268 char uuid[UUID_STRING_LEN + 1];
1271 const struct i915_oa_reg *mux_regs;
1273 const struct i915_oa_reg *b_counter_regs;
1274 u32 b_counter_regs_len;
1275 const struct i915_oa_reg *flex_regs;
1278 struct attribute_group sysfs_metric;
1279 struct attribute *attrs[2];
1280 struct device_attribute sysfs_metric_id;
1285 struct i915_perf_stream;
1288 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1290 struct i915_perf_stream_ops {
1292 * @enable: Enables the collection of HW samples, either in response to
1293 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1294 * without `I915_PERF_FLAG_DISABLED`.
1296 void (*enable)(struct i915_perf_stream *stream);
1299 * @disable: Disables the collection of HW samples, either in response
1300 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1303 void (*disable)(struct i915_perf_stream *stream);
1306 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1307 * once there is something ready to read() for the stream
1309 void (*poll_wait)(struct i915_perf_stream *stream,
1314 * @wait_unlocked: For handling a blocking read, wait until there is
1315 * something to ready to read() for the stream. E.g. wait on the same
1316 * wait queue that would be passed to poll_wait().
1318 int (*wait_unlocked)(struct i915_perf_stream *stream);
1321 * @read: Copy buffered metrics as records to userspace
1322 * **buf**: the userspace, destination buffer
1323 * **count**: the number of bytes to copy, requested by userspace
1324 * **offset**: zero at the start of the read, updated as the read
1325 * proceeds, it represents how many bytes have been copied so far and
1326 * the buffer offset for copying the next record.
1328 * Copy as many buffered i915 perf samples and records for this stream
1329 * to userspace as will fit in the given buffer.
1331 * Only write complete records; returning -%ENOSPC if there isn't room
1332 * for a complete record.
1334 * Return any error condition that results in a short read such as
1335 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1336 * returning to userspace.
1338 int (*read)(struct i915_perf_stream *stream,
1344 * @destroy: Cleanup any stream specific resources.
1346 * The stream will always be disabled before this is called.
1348 void (*destroy)(struct i915_perf_stream *stream);
1352 * struct i915_perf_stream - state for a single open stream FD
1354 struct i915_perf_stream {
1356 * @dev_priv: i915 drm device
1358 struct drm_i915_private *dev_priv;
1361 * @link: Links the stream into ``&drm_i915_private->streams``
1363 struct list_head link;
1366 * @wakeref: As we keep the device awake while the perf stream is
1367 * active, we track our runtime pm reference for later release.
1369 intel_wakeref_t wakeref;
1372 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1373 * properties given when opening a stream, representing the contents
1374 * of a single sample as read() by userspace.
1379 * @sample_size: Considering the configured contents of a sample
1380 * combined with the required header size, this is the total size
1381 * of a single sample record.
1386 * @ctx: %NULL if measuring system-wide across all contexts or a
1387 * specific context that is being monitored.
1389 struct i915_gem_context *ctx;
1392 * @enabled: Whether the stream is currently enabled, considering
1393 * whether the stream was opened in a disabled state and based
1394 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1399 * @ops: The callbacks providing the implementation of this specific
1400 * type of configured stream.
1402 const struct i915_perf_stream_ops *ops;
1405 * @oa_config: The OA configuration used by the stream.
1407 struct i915_oa_config *oa_config;
1411 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1413 struct i915_oa_ops {
1415 * @is_valid_b_counter_reg: Validates register's address for
1416 * programming boolean counters for a particular platform.
1418 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1422 * @is_valid_mux_reg: Validates register's address for programming mux
1423 * for a particular platform.
1425 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1428 * @is_valid_flex_reg: Validates register's address for programming
1429 * flex EU filtering for a particular platform.
1431 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1434 * @enable_metric_set: Selects and applies any MUX configuration to set
1435 * up the Boolean and Custom (B/C) counters that are part of the
1436 * counter reports being sampled. May apply system constraints such as
1437 * disabling EU clock gating as required.
1439 int (*enable_metric_set)(struct i915_perf_stream *stream);
1442 * @disable_metric_set: Remove system constraints associated with using
1445 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1448 * @oa_enable: Enable periodic sampling
1450 void (*oa_enable)(struct i915_perf_stream *stream);
1453 * @oa_disable: Disable periodic sampling
1455 void (*oa_disable)(struct i915_perf_stream *stream);
1458 * @read: Copy data from the circular OA buffer into a given userspace
1461 int (*read)(struct i915_perf_stream *stream,
1467 * @oa_hw_tail_read: read the OA tail pointer register
1469 * In particular this enables us to share all the fiddly code for
1470 * handling the OA unit tail pointer race that affects multiple
1473 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1476 struct intel_cdclk_state {
1477 unsigned int cdclk, vco, ref, bypass;
1481 struct drm_i915_private {
1482 struct drm_device drm;
1484 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1485 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1486 struct intel_driver_caps caps;
1489 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1490 * end of stolen which we can optionally use to create GEM objects
1491 * backed by stolen memory. Note that stolen_usable_size tells us
1492 * exactly how much of this we are actually allowed to use, given that
1493 * some portion of it is in fact reserved for use by hardware functions.
1495 struct resource dsm;
1497 * Reseved portion of Data Stolen Memory
1499 struct resource dsm_reserved;
1502 * Stolen memory is segmented in hardware with different portions
1503 * offlimits to certain functions.
1505 * The drm_mm is initialised to the total accessible range, as found
1506 * from the PCI config. On Broadwell+, this is further restricted to
1507 * avoid the first page! The upper end of stolen memory is reserved for
1508 * hardware functions and similarly removed from the accessible range.
1510 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1512 struct intel_uncore uncore;
1514 struct i915_virtual_gpu vgpu;
1516 struct intel_gvt *gvt;
1518 struct intel_wopcm wopcm;
1520 struct intel_huc huc;
1521 struct intel_guc guc;
1523 struct intel_csr csr;
1525 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1527 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1528 * controller on different i2c buses. */
1529 struct mutex gmbus_mutex;
1532 * Base address of where the gmbus and gpio blocks are located (either
1533 * on PCH or on SoC for platforms without PCH).
1537 /* MMIO base address for MIPI regs */
1544 wait_queue_head_t gmbus_wait_queue;
1546 struct pci_dev *bridge_dev;
1547 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1548 /* Context used internally to idle the GPU and setup initial state */
1549 struct i915_gem_context *kernel_context;
1550 /* Context only to be used for injecting preemption commands */
1551 struct i915_gem_context *preempt_context;
1552 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1553 [MAX_ENGINE_INSTANCE + 1];
1555 struct resource mch_res;
1557 /* protects the irq masks */
1558 spinlock_t irq_lock;
1560 bool display_irqs_enabled;
1562 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1563 struct pm_qos_request pm_qos;
1565 /* Sideband mailbox protection */
1566 struct mutex sb_lock;
1567 struct pm_qos_request sb_qos;
1569 /** Cached value of IMR to avoid reads in updating the bitfield */
1572 u32 de_irq_mask[I915_MAX_PIPES];
1579 u32 pipestat_irq_mask[I915_MAX_PIPES];
1581 struct i915_hotplug hotplug;
1582 struct intel_fbc fbc;
1583 struct i915_drrs drrs;
1584 struct intel_opregion opregion;
1585 struct intel_vbt_data vbt;
1587 bool preserve_bios_swizzle;
1590 struct intel_overlay *overlay;
1592 /* backlight registers and fields in struct intel_panel */
1593 struct mutex backlight_lock;
1596 bool no_aux_handshake;
1598 /* protects panel power sequencer state */
1599 struct mutex pps_mutex;
1601 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1602 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1604 unsigned int fsb_freq, mem_freq, is_ddr3;
1605 unsigned int skl_preferred_vco_freq;
1606 unsigned int max_cdclk_freq;
1608 unsigned int max_dotclk_freq;
1609 unsigned int rawclk_freq;
1610 unsigned int hpll_freq;
1611 unsigned int fdi_pll_freq;
1612 unsigned int czclk_freq;
1616 * The current logical cdclk state.
1617 * See intel_atomic_state.cdclk.logical
1619 * For reading holding any crtc lock is sufficient,
1620 * for writing must hold all of them.
1622 struct intel_cdclk_state logical;
1624 * The current actual cdclk state.
1625 * See intel_atomic_state.cdclk.actual
1627 struct intel_cdclk_state actual;
1628 /* The current hardware cdclk state */
1629 struct intel_cdclk_state hw;
1631 int force_min_cdclk;
1635 * wq - Driver workqueue for GEM.
1637 * NOTE: Work items scheduled here are not allowed to grab any modeset
1638 * locks, for otherwise the flushing done in the pageflip code will
1639 * result in deadlocks.
1641 struct workqueue_struct *wq;
1643 /* ordered wq for modesets */
1644 struct workqueue_struct *modeset_wq;
1646 /* Display functions */
1647 struct drm_i915_display_funcs display;
1649 /* PCH chipset type */
1650 enum intel_pch pch_type;
1651 unsigned short pch_id;
1653 unsigned long quirks;
1655 struct drm_atomic_state *modeset_restore_state;
1656 struct drm_modeset_acquire_ctx reset_ctx;
1658 struct i915_ggtt ggtt; /* VM representing the global address space */
1660 struct i915_gem_mm mm;
1661 DECLARE_HASHTABLE(mm_structs, 7);
1662 struct mutex mm_lock;
1664 struct intel_ppat ppat;
1666 /* Kernel Modesetting */
1668 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1669 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1671 #ifdef CONFIG_DEBUG_FS
1672 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1675 /* dpll and cdclk state is protected by connection_mutex */
1676 int num_shared_dpll;
1677 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1678 const struct intel_dpll_mgr *dpll_mgr;
1681 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1682 * Must be global rather than per dpll, because on some platforms
1683 * plls share registers.
1685 struct mutex dpll_lock;
1687 unsigned int active_crtcs;
1688 /* minimum acceptable cdclk for each pipe */
1689 int min_cdclk[I915_MAX_PIPES];
1690 /* minimum acceptable voltage level for each pipe */
1691 u8 min_voltage_level[I915_MAX_PIPES];
1693 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1695 struct i915_wa_list gt_wa_list;
1697 struct i915_frontbuffer_tracking fb_tracking;
1699 struct intel_atomic_helper {
1700 struct llist_head free_list;
1701 struct work_struct free_work;
1706 bool mchbar_need_disable;
1708 struct intel_l3_parity l3_parity;
1712 * Cannot be determined by PCIID. You must always read a register.
1716 /* gen6+ GT PM state */
1717 struct intel_gen6_power_mgmt gt_pm;
1719 /* ilk-only ips/rps state. Everything in here is protected by the global
1720 * mchdev_lock in intel_pm.c */
1721 struct intel_ilk_power_mgmt ips;
1723 struct i915_power_domains power_domains;
1725 struct i915_psr psr;
1727 struct i915_gpu_error gpu_error;
1729 struct drm_i915_gem_object *vlv_pctx;
1731 /* list of fbdev register on this device */
1732 struct intel_fbdev *fbdev;
1733 struct work_struct fbdev_suspend_work;
1735 struct drm_property *broadcast_rgb_property;
1736 struct drm_property *force_audio_property;
1738 /* hda/i915 audio component */
1739 struct i915_audio_component *audio_component;
1740 bool audio_component_registered;
1742 * av_mutex - mutex for audio/video sync
1745 struct mutex av_mutex;
1746 int audio_power_refcount;
1750 struct list_head list;
1751 struct llist_head free_list;
1752 struct work_struct free_work;
1754 /* The hw wants to have a stable context identifier for the
1755 * lifetime of the context (for OA, PASID, faults, etc).
1756 * This is limited in execlists to 21 bits.
1759 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1760 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1761 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1762 struct list_head hw_id_list;
1767 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1768 u32 chv_phy_control;
1770 * Shadows for CHV DPLL_MD regs to keep the state
1771 * checker somewhat working in the presence hardware
1772 * crappiness (can't read out DPLL_MD for pipes B & C).
1774 u32 chv_dpll_md[I915_MAX_PIPES];
1778 bool power_domains_suspended;
1779 struct i915_suspend_saved_registers regfile;
1780 struct vlv_s0ix_state vlv_s0ix_state;
1783 I915_SAGV_UNKNOWN = 0,
1786 I915_SAGV_NOT_CONTROLLED
1791 * Raw watermark latency values:
1792 * in 0.1us units for WM0,
1793 * in 0.5us units for WM1+.
1802 * Raw watermark memory latency values
1803 * for SKL for all 8 levels
1808 /* current hardware state */
1810 struct ilk_wm_values hw;
1811 struct skl_ddb_values skl_hw;
1812 struct vlv_wm_values vlv;
1813 struct g4x_wm_values g4x;
1819 * Should be held around atomic WM register writing; also
1820 * protects * intel_crtc->wm.active and
1821 * cstate->wm.need_postvbl_update.
1823 struct mutex wm_mutex;
1826 * Set during HW readout of watermarks/DDB. Some platforms
1827 * need to know when we're still using BIOS-provided values
1828 * (which we don't fully trust).
1830 bool distrust_bios_wm;
1839 bool symmetric_memory;
1840 enum intel_dram_type {
1849 struct intel_bw_info {
1854 struct drm_private_obj bw_obj;
1856 struct i915_runtime_pm runtime_pm;
1861 struct kobject *metrics_kobj;
1862 struct ctl_table_header *sysctl_header;
1865 * Lock associated with adding/modifying/removing OA configs
1866 * in dev_priv->perf.metrics_idr.
1868 struct mutex metrics_lock;
1871 * List of dynamic configurations, you need to hold
1872 * dev_priv->perf.metrics_lock to access it.
1874 struct idr metrics_idr;
1877 * Lock associated with anything below within this structure
1878 * except exclusive_stream.
1881 struct list_head streams;
1885 * The stream currently using the OA unit. If accessed
1886 * outside a syscall associated to its file
1887 * descriptor, you need to hold
1888 * dev_priv->drm.struct_mutex.
1890 struct i915_perf_stream *exclusive_stream;
1892 struct intel_context *pinned_ctx;
1893 u32 specific_ctx_id;
1894 u32 specific_ctx_id_mask;
1896 struct hrtimer poll_check_timer;
1897 wait_queue_head_t poll_wq;
1901 * For rate limiting any notifications of spurious
1902 * invalid OA reports
1904 struct ratelimit_state spurious_report_rs;
1907 int period_exponent;
1909 struct i915_oa_config test_config;
1912 struct i915_vma *vma;
1919 * Locks reads and writes to all head/tail state
1921 * Consider: the head and tail pointer state
1922 * needs to be read consistently from a hrtimer
1923 * callback (atomic context) and read() fop
1924 * (user context) with tail pointer updates
1925 * happening in atomic context and head updates
1926 * in user context and the (unlikely)
1927 * possibility of read() errors needing to
1928 * reset all head/tail state.
1930 * Note: Contention or performance aren't
1931 * currently a significant concern here
1932 * considering the relatively low frequency of
1933 * hrtimer callbacks (5ms period) and that
1934 * reads typically only happen in response to a
1935 * hrtimer event and likely complete before the
1938 * Note: This lock is not held *while* reading
1939 * and copying data to userspace so the value
1940 * of head observed in htrimer callbacks won't
1941 * represent any partial consumption of data.
1943 spinlock_t ptr_lock;
1946 * One 'aging' tail pointer and one 'aged'
1947 * tail pointer ready to used for reading.
1949 * Initial values of 0xffffffff are invalid
1950 * and imply that an update is required
1951 * (and should be ignored by an attempted
1959 * Index for the aged tail ready to read()
1962 unsigned int aged_tail_idx;
1965 * A monotonic timestamp for when the current
1966 * aging tail pointer was read; used to
1967 * determine when it is old enough to trust.
1969 u64 aging_timestamp;
1972 * Although we can always read back the head
1973 * pointer register, we prefer to avoid
1974 * trusting the HW state, just to avoid any
1975 * risk that some hardware condition could
1976 * somehow bump the head pointer unpredictably
1977 * and cause us to forward the wrong OA buffer
1978 * data to userspace.
1983 u32 gen7_latched_oastatus1;
1984 u32 ctx_oactxctrl_offset;
1985 u32 ctx_flexeu0_offset;
1988 * The RPT_ID/reason field for Gen8+ includes a bit
1989 * to determine if the CTX ID in the report is valid
1990 * but the specific bit differs between Gen 8 and 9
1992 u32 gen8_valid_ctx_bit;
1994 struct i915_oa_ops ops;
1995 const struct i915_oa_format *oa_formats;
1999 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2001 struct i915_gt_timelines {
2002 struct mutex mutex; /* protects list, tainted by GPU */
2003 struct list_head active_list;
2005 /* Pack multiple timelines' seqnos into the same page */
2006 spinlock_t hwsp_lock;
2007 struct list_head hwsp_free_list;
2010 struct list_head active_rings;
2011 struct list_head closed_vma;
2013 struct intel_wakeref wakeref;
2016 * Is the GPU currently considered idle, or busy executing
2017 * userspace requests? Whilst idle, we allow runtime power
2018 * management to power down the hardware and display clocks.
2019 * In order to reduce the effect on performance, there
2020 * is a slight delay before we do so.
2022 intel_wakeref_t awake;
2024 struct blocking_notifier_head pm_notifications;
2026 ktime_t last_init_time;
2028 struct i915_vma *scratch;
2032 struct notifier_block pm_notifier;
2035 * We leave the user IRQ off as much as possible,
2036 * but this means that requests will finish and never
2037 * be retired once the system goes idle. Set a timer to
2038 * fire periodically while the ring is running. When it
2039 * fires, go retire requests.
2041 struct delayed_work retire_work;
2044 * When we detect an idle GPU, we want to turn on
2045 * powersaving features. So once we see that there
2046 * are no more requests outstanding and no more
2047 * arrive within a small period of time, we fire
2048 * off the idle_work.
2050 struct work_struct idle_work;
2053 /* For i945gm vblank irq vs. C3 workaround */
2055 struct work_struct work;
2056 struct pm_qos_request pm_qos;
2057 u8 c3_disable_latency;
2061 /* perform PHY state sanity checks? */
2062 bool chv_phy_assert[2];
2066 /* Used to save the pipe-to-encoder mapping for audio */
2067 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2069 /* necessary resource sharing with HDMI LPE audio driver. */
2071 struct platform_device *platdev;
2075 struct i915_pmu pmu;
2077 struct i915_hdcp_comp_master *hdcp_master;
2078 bool hdcp_comp_added;
2080 /* Mutex to protect the above hdcp component related values. */
2081 struct mutex hdcp_comp_mutex;
2084 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2085 * will be rejected. Instead look for a better place.
2089 struct dram_dimm_info {
2090 u8 size, width, ranks;
2093 struct dram_channel_info {
2094 struct dram_dimm_info dimm_l, dimm_s;
2099 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2101 return container_of(dev, struct drm_i915_private, drm);
2104 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2106 return to_i915(dev_get_drvdata(kdev));
2109 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2111 return container_of(wopcm, struct drm_i915_private, wopcm);
2114 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2116 return container_of(guc, struct drm_i915_private, guc);
2119 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2121 return container_of(huc, struct drm_i915_private, huc);
2124 static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
2126 return container_of(uncore, struct drm_i915_private, uncore);
2129 /* Simple iterator over all initialised engines */
2130 #define for_each_engine(engine__, dev_priv__, id__) \
2132 (id__) < I915_NUM_ENGINES; \
2134 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2136 /* Iterator over subset of engines selected by mask */
2137 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2138 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
2140 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2143 enum hdmi_force_audio {
2144 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2145 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2146 HDMI_AUDIO_AUTO, /* trust EDID */
2147 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2150 #define I915_GTT_OFFSET_NONE ((u32)-1)
2153 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2154 * considered to be the frontbuffer for the given plane interface-wise. This
2155 * doesn't mean that the hw necessarily already scans it out, but that any
2156 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2158 * We have one bit per pipe and per scanout plane type.
2160 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2161 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2162 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2163 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2164 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2166 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2167 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2168 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2169 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2170 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2172 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
2173 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2174 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2176 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
2177 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2179 #define REVID_FOREVER 0xff
2180 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2182 #define INTEL_GEN_MASK(s, e) ( \
2183 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2184 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2185 GENMASK((e) - 1, (s) - 1))
2187 /* Returns true if Gen is in inclusive range [Start, End] */
2188 #define IS_GEN_RANGE(dev_priv, s, e) \
2189 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2191 #define IS_GEN(dev_priv, n) \
2192 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2193 INTEL_INFO(dev_priv)->gen == (n))
2196 * Return true if revision is in range [since,until] inclusive.
2198 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2200 #define IS_REVID(p, since, until) \
2201 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2203 static __always_inline unsigned int
2204 __platform_mask_index(const struct intel_runtime_info *info,
2205 enum intel_platform p)
2207 const unsigned int pbits =
2208 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2210 /* Expand the platform_mask array if this fails. */
2211 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
2212 pbits * ARRAY_SIZE(info->platform_mask));
2217 static __always_inline unsigned int
2218 __platform_mask_bit(const struct intel_runtime_info *info,
2219 enum intel_platform p)
2221 const unsigned int pbits =
2222 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2224 return p % pbits + INTEL_SUBPLATFORM_BITS;
2228 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
2230 const unsigned int pi = __platform_mask_index(info, p);
2232 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
2235 static __always_inline bool
2236 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
2238 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2239 const unsigned int pi = __platform_mask_index(info, p);
2240 const unsigned int pb = __platform_mask_bit(info, p);
2242 BUILD_BUG_ON(!__builtin_constant_p(p));
2244 return info->platform_mask[pi] & BIT(pb);
2247 static __always_inline bool
2248 IS_SUBPLATFORM(const struct drm_i915_private *i915,
2249 enum intel_platform p, unsigned int s)
2251 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2252 const unsigned int pi = __platform_mask_index(info, p);
2253 const unsigned int pb = __platform_mask_bit(info, p);
2254 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
2255 const u32 mask = info->platform_mask[pi];
2257 BUILD_BUG_ON(!__builtin_constant_p(p));
2258 BUILD_BUG_ON(!__builtin_constant_p(s));
2259 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
2261 /* Shift and test on the MSB position so sign flag can be used. */
2262 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
2265 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
2267 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2268 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2269 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2270 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2271 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2272 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2273 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2274 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2275 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2276 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2277 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2278 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2279 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2280 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2281 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2282 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
2283 #define IS_IRONLAKE_M(dev_priv) \
2284 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
2285 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2286 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2287 INTEL_INFO(dev_priv)->gt == 1)
2288 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2289 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2290 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2291 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2292 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2293 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2294 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2295 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2296 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2297 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2298 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2299 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
2300 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2301 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2302 #define IS_BDW_ULT(dev_priv) \
2303 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
2304 #define IS_BDW_ULX(dev_priv) \
2305 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
2306 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2307 INTEL_INFO(dev_priv)->gt == 3)
2308 #define IS_HSW_ULT(dev_priv) \
2309 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
2310 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2311 INTEL_INFO(dev_priv)->gt == 3)
2312 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2313 INTEL_INFO(dev_priv)->gt == 1)
2314 /* ULX machines are also considered ULT. */
2315 #define IS_HSW_ULX(dev_priv) \
2316 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
2317 #define IS_SKL_ULT(dev_priv) \
2318 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
2319 #define IS_SKL_ULX(dev_priv) \
2320 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
2321 #define IS_KBL_ULT(dev_priv) \
2322 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
2323 #define IS_KBL_ULX(dev_priv) \
2324 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
2325 #define IS_AML_ULX(dev_priv) \
2326 (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
2327 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
2328 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2329 INTEL_INFO(dev_priv)->gt == 2)
2330 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2331 INTEL_INFO(dev_priv)->gt == 3)
2332 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2333 INTEL_INFO(dev_priv)->gt == 4)
2334 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2335 INTEL_INFO(dev_priv)->gt == 2)
2336 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2337 INTEL_INFO(dev_priv)->gt == 3)
2338 #define IS_CFL_ULT(dev_priv) \
2339 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2340 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2341 INTEL_INFO(dev_priv)->gt == 2)
2342 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2343 INTEL_INFO(dev_priv)->gt == 3)
2344 #define IS_CNL_WITH_PORT_F(dev_priv) \
2345 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2346 #define IS_ICL_WITH_PORT_F(dev_priv) \
2347 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2349 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2351 #define SKL_REVID_A0 0x0
2352 #define SKL_REVID_B0 0x1
2353 #define SKL_REVID_C0 0x2
2354 #define SKL_REVID_D0 0x3
2355 #define SKL_REVID_E0 0x4
2356 #define SKL_REVID_F0 0x5
2357 #define SKL_REVID_G0 0x6
2358 #define SKL_REVID_H0 0x7
2360 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2362 #define BXT_REVID_A0 0x0
2363 #define BXT_REVID_A1 0x1
2364 #define BXT_REVID_B0 0x3
2365 #define BXT_REVID_B_LAST 0x8
2366 #define BXT_REVID_C0 0x9
2368 #define IS_BXT_REVID(dev_priv, since, until) \
2369 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2371 #define KBL_REVID_A0 0x0
2372 #define KBL_REVID_B0 0x1
2373 #define KBL_REVID_C0 0x2
2374 #define KBL_REVID_D0 0x3
2375 #define KBL_REVID_E0 0x4
2377 #define IS_KBL_REVID(dev_priv, since, until) \
2378 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2380 #define GLK_REVID_A0 0x0
2381 #define GLK_REVID_A1 0x1
2383 #define IS_GLK_REVID(dev_priv, since, until) \
2384 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2386 #define CNL_REVID_A0 0x0
2387 #define CNL_REVID_B0 0x1
2388 #define CNL_REVID_C0 0x2
2390 #define IS_CNL_REVID(p, since, until) \
2391 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2393 #define ICL_REVID_A0 0x0
2394 #define ICL_REVID_A2 0x1
2395 #define ICL_REVID_B0 0x3
2396 #define ICL_REVID_B2 0x4
2397 #define ICL_REVID_C0 0x5
2399 #define IS_ICL_REVID(p, since, until) \
2400 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2402 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2403 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2404 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2406 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2408 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
2409 unsigned int first__ = (first); \
2410 unsigned int count__ = (count); \
2411 (INTEL_INFO(dev_priv)->engine_mask & \
2412 GENMASK(first__ + count__ - 1, first__)) >> first__; \
2414 #define VDBOX_MASK(dev_priv) \
2415 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2416 #define VEBOX_MASK(dev_priv) \
2417 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2419 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2420 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2421 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
2422 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2423 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2425 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2427 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2428 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2429 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2430 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2431 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2432 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2434 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2436 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2437 #define HAS_PPGTT(dev_priv) \
2438 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2439 #define HAS_FULL_PPGTT(dev_priv) \
2440 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2442 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2443 GEM_BUG_ON((sizes) == 0); \
2444 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2447 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2448 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2449 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2451 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2452 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2454 /* WaRsDisableCoarsePowerGating:skl,cnl */
2455 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2456 (IS_CANNONLAKE(dev_priv) || \
2457 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2459 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2460 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2461 IS_GEMINILAKE(dev_priv) || \
2462 IS_KABYLAKE(dev_priv))
2464 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2465 * rows, which changed the alignment requirements and fence programming.
2467 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2468 !(IS_I915G(dev_priv) || \
2469 IS_I915GM(dev_priv)))
2470 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2471 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2473 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2474 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2475 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2477 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2479 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2481 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2482 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2483 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2484 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2486 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2487 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2488 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2490 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
2492 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2494 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2495 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2497 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2500 * For now, anything with a GuC requires uCode loading, and then supports
2501 * command submission once loaded. But these are logically independent
2502 * properties, so we have separate macros to test them.
2504 #define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
2505 #define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
2506 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2507 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2509 /* For now, anything with a GuC has also HuC */
2510 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2511 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2513 /* Having a GuC is not the same as using a GuC */
2514 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2515 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2516 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2518 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2520 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2521 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2522 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2523 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2524 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2525 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2526 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2527 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2528 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2529 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2530 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2531 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2532 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2533 #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
2534 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2535 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2536 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2537 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2539 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2540 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2541 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2542 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2543 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2544 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2545 #define HAS_PCH_LPT_LP(dev_priv) \
2546 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2547 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2548 #define HAS_PCH_LPT_H(dev_priv) \
2549 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2550 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2551 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2552 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2553 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2554 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2556 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2558 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2560 /* DPF == dynamic parity feature */
2561 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2562 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2563 2 : HAS_L3_DPF(dev_priv))
2565 #define GT_FREQUENCY_MULTIPLIER 50
2566 #define GEN9_FREQ_SCALER 3
2568 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2570 #include "i915_trace.h"
2572 static inline bool intel_vtd_active(void)
2574 #ifdef CONFIG_INTEL_IOMMU
2575 if (intel_iommu_gfx_mapped)
2581 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2583 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2587 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2589 return IS_BROXTON(dev_priv) && intel_vtd_active();
2594 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2595 const char *fmt, ...);
2597 #define i915_report_error(dev_priv, fmt, ...) \
2598 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2600 #ifdef CONFIG_COMPAT
2601 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2604 #define i915_compat_ioctl NULL
2606 extern const struct dev_pm_ops i915_pm_ops;
2608 extern int i915_driver_load(struct pci_dev *pdev,
2609 const struct pci_device_id *ent);
2610 extern void i915_driver_unload(struct drm_device *dev);
2612 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2613 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2614 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2615 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2616 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2617 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2618 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2620 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2622 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2624 unsigned long delay;
2626 if (unlikely(!i915_modparams.enable_hangcheck))
2629 /* Don't continually defer the hangcheck so that it is always run at
2630 * least once after work has been scheduled on any ring. Otherwise,
2631 * we will ignore a hung ring if a second ring is kept busy.
2634 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2635 queue_delayed_work(system_long_wq,
2636 &dev_priv->gpu_error.hangcheck_work, delay);
2639 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2641 return dev_priv->gvt;
2644 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2646 return dev_priv->vgpu.active;
2650 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2651 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2652 void i915_gem_sanitize(struct drm_i915_private *i915);
2653 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2654 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2655 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2656 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2657 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2659 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2661 if (!atomic_read(&i915->mm.free_count))
2664 /* A single pass should suffice to release all the freed objects (along
2665 * most call paths) , but be a little more paranoid in that freeing
2666 * the objects does take a little amount of time, during which the rcu
2667 * callbacks could have added new objects into the freed list, and
2668 * armed the work again.
2672 } while (flush_work(&i915->mm.free_work));
2675 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2678 * Similar to objects above (see i915_gem_drain_freed-objects), in
2679 * general we have workers that are armed by RCU and then rearm
2680 * themselves in their callbacks. To be paranoid, we need to
2681 * drain the workqueue a second time after waiting for the RCU
2682 * grace period so that we catch work queued via RCU from the first
2683 * pass. As neither drain_workqueue() nor flush_workqueue() report
2684 * a result, we make an assumption that we only don't require more
2685 * than 3 passes to catch all _recursive_ RCU delayed work.
2691 i915_gem_drain_freed_objects(i915);
2693 drain_workqueue(i915->wq);
2696 struct i915_vma * __must_check
2697 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2698 const struct i915_ggtt_view *view,
2703 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2705 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2707 static inline int __must_check
2708 i915_mutex_lock_interruptible(struct drm_device *dev)
2710 return mutex_lock_interruptible(&dev->struct_mutex);
2713 int i915_gem_dumb_create(struct drm_file *file_priv,
2714 struct drm_device *dev,
2715 struct drm_mode_create_dumb *args);
2716 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2717 u32 handle, u64 *offset);
2718 int i915_gem_mmap_gtt_version(void);
2720 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2721 struct drm_i915_gem_object *new,
2722 unsigned frontbuffer_bits);
2724 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
2726 static inline bool __i915_wedged(struct i915_gpu_error *error)
2728 return unlikely(test_bit(I915_WEDGED, &error->flags));
2731 static inline bool i915_reset_failed(struct drm_i915_private *i915)
2733 return __i915_wedged(&i915->gpu_error);
2736 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2738 return READ_ONCE(error->reset_count);
2741 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
2742 struct intel_engine_cs *engine)
2744 return READ_ONCE(error->reset_engine_count[engine->id]);
2747 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
2748 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
2750 void i915_gem_init_mmio(struct drm_i915_private *i915);
2751 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
2752 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
2753 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
2754 void i915_gem_fini(struct drm_i915_private *dev_priv);
2755 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
2756 unsigned int flags, long timeout);
2757 void i915_gem_suspend(struct drm_i915_private *dev_priv);
2758 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
2759 void i915_gem_resume(struct drm_i915_private *dev_priv);
2760 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
2761 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
2764 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
2766 const struct i915_sched_attr *attr);
2767 #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
2769 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
2770 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2772 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2773 enum i915_cache_level cache_level);
2775 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2776 struct dma_buf *dma_buf);
2778 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2779 struct drm_gem_object *gem_obj, int flags);
2781 static inline struct i915_hw_ppgtt *
2782 i915_vm_to_ppgtt(struct i915_address_space *vm)
2784 return container_of(vm, struct i915_hw_ppgtt, vm);
2787 /* i915_gem_fence_reg.c */
2788 struct drm_i915_fence_reg *
2789 i915_reserve_fence(struct drm_i915_private *dev_priv);
2790 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
2792 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
2794 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
2795 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
2796 struct sg_table *pages);
2797 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
2798 struct sg_table *pages);
2800 static inline struct i915_gem_context *
2801 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
2803 return idr_find(&file_priv->context_idr, id);
2806 static inline struct i915_gem_context *
2807 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2809 struct i915_gem_context *ctx;
2812 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
2813 if (ctx && !kref_get_unless_zero(&ctx->ref))
2820 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
2821 struct drm_file *file);
2822 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
2823 struct drm_file *file);
2824 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
2825 struct drm_file *file);
2826 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
2827 struct intel_context *ce,
2830 /* i915_gem_evict.c */
2831 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
2832 u64 min_size, u64 alignment,
2833 unsigned cache_level,
2836 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
2837 struct drm_mm_node *node,
2838 unsigned int flags);
2839 int i915_gem_evict_vm(struct i915_address_space *vm);
2841 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
2843 /* belongs in i915_gem_gtt.h */
2844 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
2847 if (INTEL_GEN(dev_priv) < 6)
2848 intel_gtt_chipset_flush();
2851 /* i915_gem_stolen.c */
2852 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
2853 struct drm_mm_node *node, u64 size,
2854 unsigned alignment);
2855 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
2856 struct drm_mm_node *node, u64 size,
2857 unsigned alignment, u64 start,
2859 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
2860 struct drm_mm_node *node);
2861 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
2862 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
2863 struct drm_i915_gem_object *
2864 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
2865 resource_size_t size);
2866 struct drm_i915_gem_object *
2867 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
2868 resource_size_t stolen_offset,
2869 resource_size_t gtt_offset,
2870 resource_size_t size);
2872 /* i915_gem_internal.c */
2873 struct drm_i915_gem_object *
2874 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2877 /* i915_gem_shrinker.c */
2878 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
2879 unsigned long target,
2880 unsigned long *nr_scanned,
2882 #define I915_SHRINK_PURGEABLE BIT(0)
2883 #define I915_SHRINK_UNBOUND BIT(1)
2884 #define I915_SHRINK_BOUND BIT(2)
2885 #define I915_SHRINK_ACTIVE BIT(3)
2886 #define I915_SHRINK_VMAPS BIT(4)
2887 #define I915_SHRINK_WRITEBACK BIT(5)
2888 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
2889 void i915_gem_shrinker_register(struct drm_i915_private *i915);
2890 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
2891 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
2892 struct mutex *mutex);
2894 /* i915_gem_tiling.c */
2895 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2897 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2899 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2900 i915_gem_object_is_tiled(obj);
2903 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2904 unsigned int tiling, unsigned int stride);
2905 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2906 unsigned int tiling, unsigned int stride);
2908 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2910 /* i915_cmd_parser.c */
2911 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2912 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2913 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
2914 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
2915 struct drm_i915_gem_object *batch_obj,
2916 struct drm_i915_gem_object *shadow_batch_obj,
2917 u32 batch_start_offset,
2922 extern void i915_perf_init(struct drm_i915_private *dev_priv);
2923 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
2924 extern void i915_perf_register(struct drm_i915_private *dev_priv);
2925 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
2927 /* i915_suspend.c */
2928 extern int i915_save_state(struct drm_i915_private *dev_priv);
2929 extern int i915_restore_state(struct drm_i915_private *dev_priv);
2932 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
2933 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
2935 /* intel_device_info.c */
2936 static inline struct intel_device_info *
2937 mkwrite_device_info(struct drm_i915_private *dev_priv)
2939 return (struct intel_device_info *)INTEL_INFO(dev_priv);
2943 extern void intel_modeset_init_hw(struct drm_device *dev);
2944 extern int intel_modeset_init(struct drm_device *dev);
2945 extern void intel_modeset_cleanup(struct drm_device *dev);
2946 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
2948 extern void intel_display_resume(struct drm_device *dev);
2949 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
2950 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
2951 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
2952 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
2953 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
2954 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
2956 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2959 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2960 struct drm_file *file);
2962 extern struct intel_display_error_state *
2963 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
2964 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2965 struct intel_display_error_state *error);
2967 #define __I915_REG_OP(op__, dev_priv__, ...) \
2968 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2970 #define I915_READ8(reg__) __I915_REG_OP(read8, dev_priv, (reg__))
2971 #define I915_WRITE8(reg__, val__) __I915_REG_OP(write8, dev_priv, (reg__), (val__))
2973 #define I915_READ16(reg__) __I915_REG_OP(read16, dev_priv, (reg__))
2974 #define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))
2975 #define I915_READ16_NOTRACE(reg__) __I915_REG_OP(read16_notrace, dev_priv, (reg__))
2976 #define I915_WRITE16_NOTRACE(reg__, val__) __I915_REG_OP(write16_notrace, dev_priv, (reg__), (val__))
2978 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
2979 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2980 #define I915_READ_NOTRACE(reg__) __I915_REG_OP(read_notrace, dev_priv, (reg__))
2981 #define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
2983 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2984 * will be implemented using 2 32-bit writes in an arbitrary order with
2985 * an arbitrary delay between them. This can cause the hardware to
2986 * act upon the intermediate value, possibly leading to corruption and
2987 * machine death. For this reason we do not support I915_WRITE64, or
2988 * dev_priv->uncore.funcs.mmio_writeq.
2990 * When reading a 64-bit value as two 32-bit values, the delay may cause
2991 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
2992 * occasionally a 64-bit register does not actualy support a full readq
2993 * and must be read using two 32-bit reads.
2995 * You have been warned.
2997 #define I915_READ64(reg__) __I915_REG_OP(read64, dev_priv, (reg__))
2998 #define I915_READ64_2x32(lower_reg__, upper_reg__) \
2999 __I915_REG_OP(read64_2x32, dev_priv, (lower_reg__), (upper_reg__))
3001 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
3002 #define POSTING_READ16(reg__) __I915_REG_OP(posting_read16, dev_priv, (reg__))
3004 /* These are untraced mmio-accessors that are only valid to be used inside
3005 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3008 * Think twice, and think again, before using these.
3010 * As an example, these accessors can possibly be used between:
3012 * spin_lock_irq(&dev_priv->uncore.lock);
3013 * intel_uncore_forcewake_get__locked();
3017 * intel_uncore_forcewake_put__locked();
3018 * spin_unlock_irq(&dev_priv->uncore.lock);
3021 * Note: some registers may not need forcewake held, so
3022 * intel_uncore_forcewake_{get,put} can be omitted, see
3023 * intel_uncore_forcewake_for_reg().
3025 * Certain architectures will die if the same cacheline is concurrently accessed
3026 * by different clients (e.g. on Ivybridge). Access to registers should
3027 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3028 * a more localised lock guarding all access to that bank of registers.
3030 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
3031 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
3032 #define I915_WRITE64_FW(reg__, val__) __I915_REG_OP(write64_fw, dev_priv, (reg__), (val__))
3033 #define POSTING_READ_FW(reg__) __I915_REG_OP(posting_read_fw, dev_priv, (reg__))
3035 /* "Broadcast RGB" property */
3036 #define INTEL_BROADCAST_RGB_AUTO 0
3037 #define INTEL_BROADCAST_RGB_FULL 1
3038 #define INTEL_BROADCAST_RGB_LIMITED 2
3040 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3041 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3043 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3044 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3045 * perform the operation. To check beforehand, pass in the parameters to
3046 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3047 * you only need to pass in the minor offsets, page-aligned pointers are
3050 * For just checking for SSE4.1, in the foreknowledge that the future use
3051 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3053 #define i915_can_memcpy_from_wc(dst, src, len) \
3054 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3056 #define i915_has_memcpy_from_wc() \
3057 i915_memcpy_from_wc(NULL, NULL, 0)
3060 int remap_io_mapping(struct vm_area_struct *vma,
3061 unsigned long addr, unsigned long pfn, unsigned long size,
3062 struct io_mapping *iomap);
3064 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3066 if (INTEL_GEN(i915) >= 10)
3067 return CNL_HWS_CSB_WRITE_INDEX;
3069 return I915_HWS_CSB_WRITE_INDEX;
3072 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
3074 return i915_ggtt_offset(i915->gt.scratch);
3077 static inline enum i915_map_type
3078 i915_coherent_map_type(struct drm_i915_private *i915)
3080 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
3083 static inline void add_taint_for_CI(unsigned int taint)
3086 * The system is "ok", just about surviving for the user, but
3087 * CI results are now unreliable as the HW is very suspect.
3088 * CI checks the taint state after every test and will reboot
3089 * the machine if the kernel is tainted.
3091 add_taint(taint, LOCKDEP_STILL_OK);