1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20170717"
84 #define DRIVER_TIMESTAMP 1500275179
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func, int line);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
125 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
127 uint_fixed_16_16_t fp;
135 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
137 return DIV_ROUND_UP(fp.val, 1 << 16);
140 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
145 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
146 uint_fixed_16_16_t min2)
148 uint_fixed_16_16_t min;
150 min.val = min(min1.val, min2.val);
154 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
155 uint_fixed_16_16_t max2)
157 uint_fixed_16_16_t max;
159 max.val = max(max1.val, max2.val);
163 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
165 uint_fixed_16_16_t fp;
167 fp.val = clamp_t(uint32_t, val, 0, ~0);
171 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
172 uint_fixed_16_16_t d)
174 return DIV_ROUND_UP(val.val, d.val);
177 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
178 uint_fixed_16_16_t mul)
180 uint64_t intermediate_val;
182 intermediate_val = (uint64_t) val * mul.val;
183 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
184 WARN_ON(intermediate_val >> 32);
185 return clamp_t(uint32_t, intermediate_val, 0, ~0);
188 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
189 uint_fixed_16_16_t mul)
191 uint64_t intermediate_val;
193 intermediate_val = (uint64_t) val.val * mul.val;
194 intermediate_val = intermediate_val >> 16;
195 return clamp_u64_to_fixed16(intermediate_val);
198 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
202 interm_val = (uint64_t)val << 16;
203 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
204 return clamp_u64_to_fixed16(interm_val);
207 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
208 uint_fixed_16_16_t d)
212 interm_val = (uint64_t)val << 16;
213 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
214 WARN_ON(interm_val >> 32);
215 return clamp_t(uint32_t, interm_val, 0, ~0);
218 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
219 uint_fixed_16_16_t mul)
221 uint64_t intermediate_val;
223 intermediate_val = (uint64_t) val * mul.val;
224 return clamp_u64_to_fixed16(intermediate_val);
227 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
228 uint_fixed_16_16_t add2)
232 interm_sum = (uint64_t) add1.val + add2.val;
233 return clamp_u64_to_fixed16(interm_sum);
236 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
240 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
242 interm_sum = (uint64_t) add1.val + interm_add2.val;
243 return clamp_u64_to_fixed16(interm_sum);
246 static inline const char *yesno(bool v)
248 return v ? "yes" : "no";
251 static inline const char *onoff(bool v)
253 return v ? "on" : "off";
256 static inline const char *enableddisabled(bool v)
258 return v ? "enabled" : "disabled";
267 I915_MAX_PIPES = _PIPE_EDP
269 #define pipe_name(p) ((p) + 'A')
281 static inline const char *transcoder_name(enum transcoder transcoder)
283 switch (transcoder) {
292 case TRANSCODER_DSI_A:
294 case TRANSCODER_DSI_C:
301 static inline bool transcoder_is_dsi(enum transcoder transcoder)
303 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
307 * Global legacy plane identifier. Valid only for primary/sprite
308 * planes on pre-g4x, and only for primary planes on g4x+.
315 #define plane_name(p) ((p) + 'A')
317 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
320 * Per-pipe plane identifier.
321 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
322 * number of planes per CRTC. Not all platforms really have this many planes,
323 * which means some arrays of size I915_MAX_PLANES may have unused entries
324 * between the topmost sprite plane and the cursor plane.
326 * This is expected to be passed to various register macros
327 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
338 #define for_each_plane_id_on_crtc(__crtc, __p) \
339 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
340 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
351 #define port_name(p) ((p) + 'A')
353 #define I915_NUM_PHYS_VLV 2
366 enum intel_display_power_domain {
370 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
371 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
372 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
373 POWER_DOMAIN_TRANSCODER_A,
374 POWER_DOMAIN_TRANSCODER_B,
375 POWER_DOMAIN_TRANSCODER_C,
376 POWER_DOMAIN_TRANSCODER_EDP,
377 POWER_DOMAIN_TRANSCODER_DSI_A,
378 POWER_DOMAIN_TRANSCODER_DSI_C,
379 POWER_DOMAIN_PORT_DDI_A_LANES,
380 POWER_DOMAIN_PORT_DDI_B_LANES,
381 POWER_DOMAIN_PORT_DDI_C_LANES,
382 POWER_DOMAIN_PORT_DDI_D_LANES,
383 POWER_DOMAIN_PORT_DDI_E_LANES,
384 POWER_DOMAIN_PORT_DDI_A_IO,
385 POWER_DOMAIN_PORT_DDI_B_IO,
386 POWER_DOMAIN_PORT_DDI_C_IO,
387 POWER_DOMAIN_PORT_DDI_D_IO,
388 POWER_DOMAIN_PORT_DDI_E_IO,
389 POWER_DOMAIN_PORT_DSI,
390 POWER_DOMAIN_PORT_CRT,
391 POWER_DOMAIN_PORT_OTHER,
400 POWER_DOMAIN_MODESET,
406 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
407 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
408 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
409 #define POWER_DOMAIN_TRANSCODER(tran) \
410 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
411 (tran) + POWER_DOMAIN_TRANSCODER_A)
415 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
427 #define for_each_hpd_pin(__pin) \
428 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
430 #define HPD_STORM_DEFAULT_THRESHOLD 5
432 struct i915_hotplug {
433 struct work_struct hotplug_work;
436 unsigned long last_jiffies;
441 HPD_MARK_DISABLED = 2
443 } stats[HPD_NUM_PINS];
445 struct delayed_work reenable_work;
447 struct intel_digital_port *irq_port[I915_MAX_PORTS];
450 struct work_struct dig_port_work;
452 struct work_struct poll_init_work;
455 unsigned int hpd_storm_threshold;
458 * if we get a HPD irq from DP and a HPD irq from non-DP
459 * the non-DP HPD could block the workqueue on a mode config
460 * mutex getting, that userspace may have taken. However
461 * userspace is waiting on the DP workqueue to run which is
462 * blocked behind the non-DP one.
464 struct workqueue_struct *dp_wq;
467 #define I915_GEM_GPU_DOMAINS \
468 (I915_GEM_DOMAIN_RENDER | \
469 I915_GEM_DOMAIN_SAMPLER | \
470 I915_GEM_DOMAIN_COMMAND | \
471 I915_GEM_DOMAIN_INSTRUCTION | \
472 I915_GEM_DOMAIN_VERTEX)
474 #define for_each_pipe(__dev_priv, __p) \
475 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
476 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
477 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
478 for_each_if ((__mask) & (1 << (__p)))
479 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
481 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
483 #define for_each_sprite(__dev_priv, __p, __s) \
485 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
488 #define for_each_port_masked(__port, __ports_mask) \
489 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
490 for_each_if ((__ports_mask) & (1 << (__port)))
492 #define for_each_crtc(dev, crtc) \
493 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
495 #define for_each_intel_plane(dev, intel_plane) \
496 list_for_each_entry(intel_plane, \
497 &(dev)->mode_config.plane_list, \
500 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
501 list_for_each_entry(intel_plane, \
502 &(dev)->mode_config.plane_list, \
504 for_each_if ((plane_mask) & \
505 (1 << drm_plane_index(&intel_plane->base)))
507 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
508 list_for_each_entry(intel_plane, \
509 &(dev)->mode_config.plane_list, \
511 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
513 #define for_each_intel_crtc(dev, intel_crtc) \
514 list_for_each_entry(intel_crtc, \
515 &(dev)->mode_config.crtc_list, \
518 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
519 list_for_each_entry(intel_crtc, \
520 &(dev)->mode_config.crtc_list, \
522 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
524 #define for_each_intel_encoder(dev, intel_encoder) \
525 list_for_each_entry(intel_encoder, \
526 &(dev)->mode_config.encoder_list, \
529 #define for_each_intel_connector_iter(intel_connector, iter) \
530 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
532 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
533 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
534 for_each_if ((intel_encoder)->base.crtc == (__crtc))
536 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
537 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
538 for_each_if ((intel_connector)->base.encoder == (__encoder))
540 #define for_each_power_domain(domain, mask) \
541 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
542 for_each_if (BIT_ULL(domain) & (mask))
544 #define for_each_power_well(__dev_priv, __power_well) \
545 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
546 (__power_well) - (__dev_priv)->power_domains.power_wells < \
547 (__dev_priv)->power_domains.power_well_count; \
550 #define for_each_power_well_rev(__dev_priv, __power_well) \
551 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
552 (__dev_priv)->power_domains.power_well_count - 1; \
553 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
556 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
557 for_each_power_well(__dev_priv, __power_well) \
558 for_each_if ((__power_well)->domains & (__domain_mask))
560 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
561 for_each_power_well_rev(__dev_priv, __power_well) \
562 for_each_if ((__power_well)->domains & (__domain_mask))
564 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
566 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
567 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
568 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
570 for_each_if (plane_state)
572 struct drm_i915_private;
573 struct i915_mm_struct;
574 struct i915_mmu_object;
576 struct drm_i915_file_private {
577 struct drm_i915_private *dev_priv;
578 struct drm_file *file;
582 struct list_head request_list;
583 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
584 * chosen to prevent the CPU getting more than a frame ahead of the GPU
585 * (when using lax throttling for the frontbuffer). We also use it to
586 * offer free GPU waitboosts for severely congested workloads.
588 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
590 struct idr context_idr;
592 struct intel_rps_client {
596 unsigned int bsd_engine;
598 /* Client can have a maximum of 3 contexts banned before
599 * it is denied of creating new contexts. As one context
600 * ban needs 4 consecutive hangs, and more if there is
601 * progress in between, this is a last resort stop gap measure
602 * to limit the badly behaving clients access to gpu.
604 #define I915_MAX_CLIENT_CONTEXT_BANS 3
608 /* Used by dp and fdi links */
609 struct intel_link_m_n {
617 void intel_link_compute_m_n(int bpp, int nlanes,
618 int pixel_clock, int link_clock,
619 struct intel_link_m_n *m_n,
622 /* Interface history:
625 * 1.2: Add Power Management
626 * 1.3: Add vblank support
627 * 1.4: Fix cmdbuffer path, add heap destroy
628 * 1.5: Add vblank pipe configuration
629 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
630 * - Support vertical blank on secondary display pipe
632 #define DRIVER_MAJOR 1
633 #define DRIVER_MINOR 6
634 #define DRIVER_PATCHLEVEL 0
636 struct opregion_header;
637 struct opregion_acpi;
638 struct opregion_swsci;
639 struct opregion_asle;
641 struct intel_opregion {
642 struct opregion_header *header;
643 struct opregion_acpi *acpi;
644 struct opregion_swsci *swsci;
645 u32 swsci_gbda_sub_functions;
646 u32 swsci_sbcb_sub_functions;
647 struct opregion_asle *asle;
652 struct work_struct asle_work;
654 #define OPREGION_SIZE (8*1024)
656 struct intel_overlay;
657 struct intel_overlay_error_state;
659 struct sdvo_device_mapping {
668 struct intel_connector;
669 struct intel_encoder;
670 struct intel_atomic_state;
671 struct intel_crtc_state;
672 struct intel_initial_plane_config;
676 struct intel_cdclk_state;
678 struct drm_i915_display_funcs {
679 void (*get_cdclk)(struct drm_i915_private *dev_priv,
680 struct intel_cdclk_state *cdclk_state);
681 void (*set_cdclk)(struct drm_i915_private *dev_priv,
682 const struct intel_cdclk_state *cdclk_state);
683 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
684 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
685 int (*compute_intermediate_wm)(struct drm_device *dev,
686 struct intel_crtc *intel_crtc,
687 struct intel_crtc_state *newstate);
688 void (*initial_watermarks)(struct intel_atomic_state *state,
689 struct intel_crtc_state *cstate);
690 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
691 struct intel_crtc_state *cstate);
692 void (*optimize_watermarks)(struct intel_atomic_state *state,
693 struct intel_crtc_state *cstate);
694 int (*compute_global_watermarks)(struct drm_atomic_state *state);
695 void (*update_wm)(struct intel_crtc *crtc);
696 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
697 /* Returns the active state of the crtc, and if the crtc is active,
698 * fills out the pipe-config with the hw state. */
699 bool (*get_pipe_config)(struct intel_crtc *,
700 struct intel_crtc_state *);
701 void (*get_initial_plane_config)(struct intel_crtc *,
702 struct intel_initial_plane_config *);
703 int (*crtc_compute_clock)(struct intel_crtc *crtc,
704 struct intel_crtc_state *crtc_state);
705 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
706 struct drm_atomic_state *old_state);
707 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
708 struct drm_atomic_state *old_state);
709 void (*update_crtcs)(struct drm_atomic_state *state,
710 unsigned int *crtc_vblank_mask);
711 void (*audio_codec_enable)(struct drm_connector *connector,
712 struct intel_encoder *encoder,
713 const struct drm_display_mode *adjusted_mode);
714 void (*audio_codec_disable)(struct intel_encoder *encoder);
715 void (*fdi_link_train)(struct intel_crtc *crtc,
716 const struct intel_crtc_state *crtc_state);
717 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
718 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
719 struct drm_framebuffer *fb,
720 struct drm_i915_gem_object *obj,
721 struct drm_i915_gem_request *req,
723 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
724 /* clock updates for mode set */
726 /* render clock increase/decrease */
727 /* display clock increase/decrease */
728 /* pll clock increase/decrease */
730 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
731 void (*load_luts)(struct drm_crtc_state *crtc_state);
734 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
735 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
736 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
739 struct work_struct work;
741 uint32_t *dmc_payload;
742 uint32_t dmc_fw_size;
745 i915_reg_t mmioaddr[8];
746 uint32_t mmiodata[8];
748 uint32_t allowed_dc_mask;
751 #define DEV_INFO_FOR_EACH_FLAG(func) \
754 func(is_alpha_support); \
755 /* Keep has_* in alphabetical order */ \
756 func(has_64bit_reloc); \
757 func(has_aliasing_ppgtt); \
761 func(has_reset_engine); \
763 func(has_fpga_dbg); \
764 func(has_full_ppgtt); \
765 func(has_full_48bit_ppgtt); \
766 func(has_gmbus_irq); \
767 func(has_gmch_display); \
773 func(has_logical_ring_contexts); \
775 func(has_pipe_cxsr); \
776 func(has_pooled_eu); \
780 func(has_resource_streamer); \
781 func(has_runtime_pm); \
783 func(unfenced_needs_alignment); \
784 func(cursor_needs_physical); \
785 func(hws_needs_physical); \
786 func(overlay_needs_physical); \
789 struct sseu_dev_info {
795 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
798 u8 has_subslice_pg:1;
802 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
804 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
807 /* Keep in gen based order, and chronological order within a gen */
808 enum intel_platform {
809 INTEL_PLATFORM_UNINITIALIZED = 0,
840 struct intel_device_info {
841 u32 display_mmio_offset;
844 u8 num_sprites[I915_MAX_PIPES];
845 u8 num_scalers[I915_MAX_PIPES];
848 enum intel_platform platform;
849 u8 ring_mask; /* Rings supported by the HW */
851 #define DEFINE_FLAG(name) u8 name:1
852 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
854 u16 ddb_size; /* in blocks */
855 /* Register offsets for the various display pipes and transcoders */
856 int pipe_offsets[I915_MAX_TRANSCODERS];
857 int trans_offsets[I915_MAX_TRANSCODERS];
858 int palette_offsets[I915_MAX_PIPES];
859 int cursor_offsets[I915_MAX_PIPES];
861 /* Slice/subslice/EU info */
862 struct sseu_dev_info sseu;
865 u16 degamma_lut_size;
870 struct intel_display_error_state;
872 struct i915_gpu_state {
875 struct timeval boottime;
876 struct timeval uptime;
878 struct drm_i915_private *i915;
888 struct intel_device_info device_info;
889 struct i915_params params;
891 /* Generic register state */
895 u32 gtier[4], ngtier;
899 u32 error; /* gen6+ */
900 u32 err_int; /* gen7 */
901 u32 fault_data0; /* gen8, gen9 */
902 u32 fault_data1; /* gen8, gen9 */
910 u64 fence[I915_MAX_NUM_FENCES];
911 struct intel_overlay_error_state *overlay;
912 struct intel_display_error_state *display;
913 struct drm_i915_error_object *semaphore;
914 struct drm_i915_error_object *guc_log;
916 struct drm_i915_error_engine {
918 /* Software tracked state */
921 unsigned long hangcheck_timestamp;
922 bool hangcheck_stalled;
923 enum intel_engine_hangcheck_action hangcheck_action;
924 struct i915_address_space *vm;
928 /* position of active request inside the ring */
929 u32 rq_head, rq_post, rq_tail;
931 /* our own tracking of ring head and tail */
954 u32 rc_psmi; /* sleep state */
955 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
956 struct intel_instdone instdone;
958 struct drm_i915_error_context {
959 char comm[TASK_COMM_LEN];
968 struct drm_i915_error_object {
974 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
976 struct drm_i915_error_object **user_bo;
979 struct drm_i915_error_object *wa_ctx;
981 struct drm_i915_error_request {
989 } *requests, execlist[2];
991 struct drm_i915_error_waiter {
992 char comm[TASK_COMM_LEN];
1004 } engine[I915_NUM_ENGINES];
1006 struct drm_i915_error_buffer {
1009 u32 rseqno[I915_NUM_ENGINES], wseqno;
1013 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1020 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1021 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1022 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1025 enum i915_cache_level {
1026 I915_CACHE_NONE = 0,
1027 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1028 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1029 caches, eg sampler/render caches, and the
1030 large Last-Level-Cache. LLC is coherent with
1031 the CPU, but L3 is only visible to the GPU. */
1032 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1035 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1046 /* This is always the inner lock when overlapping with struct_mutex and
1047 * it's the outer lock when overlapping with stolen_lock. */
1050 unsigned int possible_framebuffer_bits;
1051 unsigned int busy_bits;
1052 unsigned int visible_pipes_mask;
1053 struct intel_crtc *crtc;
1055 struct drm_mm_node compressed_fb;
1056 struct drm_mm_node *compressed_llb;
1063 bool underrun_detected;
1064 struct work_struct underrun_work;
1066 struct intel_fbc_state_cache {
1067 struct i915_vma *vma;
1070 unsigned int mode_flags;
1071 uint32_t hsw_bdw_pixel_rate;
1075 unsigned int rotation;
1082 const struct drm_format_info *format;
1083 unsigned int stride;
1087 struct intel_fbc_reg_params {
1088 struct i915_vma *vma;
1093 unsigned int fence_y_offset;
1097 const struct drm_format_info *format;
1098 unsigned int stride;
1104 struct intel_fbc_work {
1106 u32 scheduled_vblank;
1107 struct work_struct work;
1110 const char *no_fbc_reason;
1114 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1115 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1116 * parsing for same resolution.
1118 enum drrs_refresh_rate_type {
1121 DRRS_MAX_RR, /* RR count */
1124 enum drrs_support_type {
1125 DRRS_NOT_SUPPORTED = 0,
1126 STATIC_DRRS_SUPPORT = 1,
1127 SEAMLESS_DRRS_SUPPORT = 2
1133 struct delayed_work work;
1134 struct intel_dp *dp;
1135 unsigned busy_frontbuffer_bits;
1136 enum drrs_refresh_rate_type refresh_rate_type;
1137 enum drrs_support_type type;
1144 struct intel_dp *enabled;
1146 struct delayed_work work;
1147 unsigned busy_frontbuffer_bits;
1149 bool aux_frame_sync;
1151 bool y_cord_support;
1152 bool colorimetry_support;
1157 PCH_NONE = 0, /* No PCH present */
1158 PCH_IBX, /* Ibexpeak PCH */
1159 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
1160 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
1161 PCH_SPT, /* Sunrisepoint PCH */
1162 PCH_KBP, /* Kabypoint PCH */
1163 PCH_CNP, /* Cannonpoint PCH */
1167 enum intel_sbi_destination {
1172 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1173 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1174 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1175 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1176 #define QUIRK_INCREASE_T12_DELAY (1<<6)
1179 struct intel_fbc_work;
1181 struct intel_gmbus {
1182 struct i2c_adapter adapter;
1183 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1186 i915_reg_t gpio_reg;
1187 struct i2c_algo_bit_data bit_algo;
1188 struct drm_i915_private *dev_priv;
1191 struct i915_suspend_saved_registers {
1193 u32 saveFBC_CONTROL;
1194 u32 saveCACHE_MODE_0;
1195 u32 saveMI_ARB_STATE;
1199 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1200 u32 savePCH_PORT_HOTPLUG;
1204 struct vlv_s0ix_state {
1211 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1212 u32 media_max_req_count;
1213 u32 gfx_max_req_count;
1239 u32 rp_down_timeout;
1245 /* Display 1 CZ domain */
1250 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1252 /* GT SA CZ domain */
1259 /* Display 2 CZ domain */
1263 u32 clock_gate_dis2;
1266 struct intel_rps_ei {
1272 struct intel_gen6_power_mgmt {
1274 * work, interrupts_enabled and pm_iir are protected by
1275 * dev_priv->irq_lock
1277 struct work_struct work;
1278 bool interrupts_enabled;
1281 /* PM interrupt bits that should never be masked */
1284 /* Frequencies are stored in potentially platform dependent multiples.
1285 * In other words, *_freq needs to be multiplied by X to be interesting.
1286 * Soft limits are those which are used for the dynamic reclocking done
1287 * by the driver (raise frequencies under heavy loads, and lower for
1288 * lighter loads). Hard limits are those imposed by the hardware.
1290 * A distinction is made for overclocking, which is never enabled by
1291 * default, and is considered to be above the hard limit if it's
1294 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1295 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1296 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1297 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1298 u8 min_freq; /* AKA RPn. Minimum frequency */
1299 u8 boost_freq; /* Frequency to request when wait boosting */
1300 u8 idle_freq; /* Frequency to request when we are idle */
1301 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1302 u8 rp1_freq; /* "less than" RP0 power/freqency */
1303 u8 rp0_freq; /* Non-overclocked max frequency. */
1304 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1306 u8 up_threshold; /* Current %busy required to uplock */
1307 u8 down_threshold; /* Current %busy required to downclock */
1310 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1313 struct delayed_work autoenable_work;
1314 atomic_t num_waiters;
1317 /* manual wa residency calculations */
1318 struct intel_rps_ei ei;
1321 * Protects RPS/RC6 register access and PCU communication.
1322 * Must be taken after struct_mutex if nested. Note that
1323 * this lock may be held for long periods of time when
1324 * talking to hw - so only take it when talking to hw!
1326 struct mutex hw_lock;
1329 /* defined intel_pm.c */
1330 extern spinlock_t mchdev_lock;
1332 struct intel_ilk_power_mgmt {
1340 unsigned long last_time1;
1341 unsigned long chipset_power;
1344 unsigned long gfx_power;
1351 struct drm_i915_private;
1352 struct i915_power_well;
1354 struct i915_power_well_ops {
1356 * Synchronize the well's hw state to match the current sw state, for
1357 * example enable/disable it based on the current refcount. Called
1358 * during driver init and resume time, possibly after first calling
1359 * the enable/disable handlers.
1361 void (*sync_hw)(struct drm_i915_private *dev_priv,
1362 struct i915_power_well *power_well);
1364 * Enable the well and resources that depend on it (for example
1365 * interrupts located on the well). Called after the 0->1 refcount
1368 void (*enable)(struct drm_i915_private *dev_priv,
1369 struct i915_power_well *power_well);
1371 * Disable the well and resources that depend on it. Called after
1372 * the 1->0 refcount transition.
1374 void (*disable)(struct drm_i915_private *dev_priv,
1375 struct i915_power_well *power_well);
1376 /* Returns the hw enabled state. */
1377 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1378 struct i915_power_well *power_well);
1381 /* Power well structure for haswell */
1382 struct i915_power_well {
1385 /* power well enable/disable usage count */
1387 /* cached hw enabled state */
1390 /* unique identifier for this power well */
1393 * Arbitraty data associated with this power well. Platform and power
1397 const struct i915_power_well_ops *ops;
1400 struct i915_power_domains {
1402 * Power wells needed for initialization at driver init and suspend
1403 * time are on. They are kept on until after the first modeset.
1407 int power_well_count;
1410 int domain_use_count[POWER_DOMAIN_NUM];
1411 struct i915_power_well *power_wells;
1414 #define MAX_L3_SLICES 2
1415 struct intel_l3_parity {
1416 u32 *remap_info[MAX_L3_SLICES];
1417 struct work_struct error_work;
1421 struct i915_gem_mm {
1422 /** Memory allocator for GTT stolen memory */
1423 struct drm_mm stolen;
1424 /** Protects the usage of the GTT stolen memory allocator. This is
1425 * always the inner lock when overlapping with struct_mutex. */
1426 struct mutex stolen_lock;
1428 /** List of all objects in gtt_space. Used to restore gtt
1429 * mappings on resume */
1430 struct list_head bound_list;
1432 * List of objects which are not bound to the GTT (thus
1433 * are idle and not used by the GPU). These objects may or may
1434 * not actually have any pages attached.
1436 struct list_head unbound_list;
1438 /** List of all objects in gtt_space, currently mmaped by userspace.
1439 * All objects within this list must also be on bound_list.
1441 struct list_head userfault_list;
1444 * List of objects which are pending destruction.
1446 struct llist_head free_list;
1447 struct work_struct free_work;
1449 /** Usable portion of the GTT for GEM */
1450 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1452 /** PPGTT used for aliasing the PPGTT with the GTT */
1453 struct i915_hw_ppgtt *aliasing_ppgtt;
1455 struct notifier_block oom_notifier;
1456 struct notifier_block vmap_notifier;
1457 struct shrinker shrinker;
1459 /** LRU list of objects with fence regs on them. */
1460 struct list_head fence_list;
1463 * Workqueue to fault in userptr pages, flushed by the execbuf
1464 * when required but otherwise left to userspace to try again
1467 struct workqueue_struct *userptr_wq;
1469 u64 unordered_timeline;
1471 /* the indicator for dispatch video commands on two BSD rings */
1472 atomic_t bsd_engine_dispatch_index;
1474 /** Bit 6 swizzling required for X tiling */
1475 uint32_t bit_6_swizzle_x;
1476 /** Bit 6 swizzling required for Y tiling */
1477 uint32_t bit_6_swizzle_y;
1479 /* accounting, useful for userland debugging */
1480 spinlock_t object_stat_lock;
1485 struct drm_i915_error_state_buf {
1486 struct drm_i915_private *i915;
1495 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1496 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1498 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1499 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1501 struct i915_gpu_error {
1502 /* For hangcheck timer */
1503 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1504 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1506 struct delayed_work hangcheck_work;
1508 /* For reset and error_state handling. */
1510 /* Protected by the above dev->gpu_error.lock. */
1511 struct i915_gpu_state *first_error;
1513 unsigned long missed_irq_rings;
1516 * State variable controlling the reset flow and count
1518 * This is a counter which gets incremented when reset is triggered,
1520 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1521 * meaning that any waiters holding onto the struct_mutex should
1522 * relinquish the lock immediately in order for the reset to start.
1524 * If reset is not completed succesfully, the I915_WEDGE bit is
1525 * set meaning that hardware is terminally sour and there is no
1526 * recovery. All waiters on the reset_queue will be woken when
1529 * This counter is used by the wait_seqno code to notice that reset
1530 * event happened and it needs to restart the entire ioctl (since most
1531 * likely the seqno it waited for won't ever signal anytime soon).
1533 * This is important for lock-free wait paths, where no contended lock
1534 * naturally enforces the correct ordering between the bail-out of the
1535 * waiter and the gpu reset work code.
1537 unsigned long reset_count;
1540 * flags: Control various stages of the GPU reset
1542 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1543 * other users acquiring the struct_mutex. To do this we set the
1544 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1545 * and then check for that bit before acquiring the struct_mutex (in
1546 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1547 * secondary role in preventing two concurrent global reset attempts.
1549 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1550 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1551 * but it may be held by some long running waiter (that we cannot
1552 * interrupt without causing trouble). Once we are ready to do the GPU
1553 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1554 * they already hold the struct_mutex and want to participate they can
1555 * inspect the bit and do the reset directly, otherwise the worker
1556 * waits for the struct_mutex.
1558 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1559 * acquire the struct_mutex to reset an engine, we need an explicit
1560 * flag to prevent two concurrent reset attempts in the same engine.
1561 * As the number of engines continues to grow, allocate the flags from
1562 * the most significant bits.
1564 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1565 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1566 * i915_gem_request_alloc(), this bit is checked and the sequence
1567 * aborted (with -EIO reported to userspace) if set.
1569 unsigned long flags;
1570 #define I915_RESET_BACKOFF 0
1571 #define I915_RESET_HANDOFF 1
1572 #define I915_WEDGED (BITS_PER_LONG - 1)
1573 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1575 /** Number of times an engine has been reset */
1576 u32 reset_engine_count[I915_NUM_ENGINES];
1579 * Waitqueue to signal when a hang is detected. Used to for waiters
1580 * to release the struct_mutex for the reset to procede.
1582 wait_queue_head_t wait_queue;
1585 * Waitqueue to signal when the reset has completed. Used by clients
1586 * that wait for dev_priv->mm.wedged to settle.
1588 wait_queue_head_t reset_queue;
1590 /* For missed irq/seqno simulation. */
1591 unsigned long test_irq_rings;
1594 enum modeset_restore {
1595 MODESET_ON_LID_OPEN,
1600 #define DP_AUX_A 0x40
1601 #define DP_AUX_B 0x10
1602 #define DP_AUX_C 0x20
1603 #define DP_AUX_D 0x30
1605 #define DDC_PIN_B 0x05
1606 #define DDC_PIN_C 0x04
1607 #define DDC_PIN_D 0x06
1609 struct ddi_vbt_port_info {
1611 * This is an index in the HDMI/DVI DDI buffer translation table.
1612 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1613 * populate this field.
1615 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1616 uint8_t hdmi_level_shift;
1618 uint8_t supports_dvi:1;
1619 uint8_t supports_hdmi:1;
1620 uint8_t supports_dp:1;
1621 uint8_t supports_edp:1;
1623 uint8_t alternate_aux_channel;
1624 uint8_t alternate_ddc_pin;
1626 uint8_t dp_boost_level;
1627 uint8_t hdmi_boost_level;
1630 enum psr_lines_to_wait {
1631 PSR_0_LINES_TO_WAIT = 0,
1633 PSR_4_LINES_TO_WAIT,
1637 struct intel_vbt_data {
1638 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1639 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1642 unsigned int int_tv_support:1;
1643 unsigned int lvds_dither:1;
1644 unsigned int lvds_vbt:1;
1645 unsigned int int_crt_support:1;
1646 unsigned int lvds_use_ssc:1;
1647 unsigned int display_clock_mode:1;
1648 unsigned int fdi_rx_polarity_inverted:1;
1649 unsigned int panel_type:4;
1651 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1653 enum drrs_support_type drrs_type;
1664 struct edp_power_seq pps;
1669 bool require_aux_wakeup;
1671 enum psr_lines_to_wait lines_to_wait;
1672 int tp1_wakeup_time;
1673 int tp2_tp3_wakeup_time;
1679 bool active_low_pwm;
1680 u8 min_brightness; /* min_brightness/255 of max */
1681 u8 controller; /* brightness controller number */
1682 enum intel_backlight_type type;
1688 struct mipi_config *config;
1689 struct mipi_pps_data *pps;
1693 const u8 *sequence[MIPI_SEQ_MAX];
1699 union child_device_config *child_dev;
1701 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1702 struct sdvo_device_mapping sdvo_mappings[2];
1705 enum intel_ddb_partitioning {
1707 INTEL_DDB_PART_5_6, /* IVB+ */
1710 struct intel_wm_level {
1718 struct ilk_wm_values {
1719 uint32_t wm_pipe[3];
1721 uint32_t wm_lp_spr[3];
1722 uint32_t wm_linetime[3];
1724 enum intel_ddb_partitioning partitioning;
1727 struct g4x_pipe_wm {
1728 uint16_t plane[I915_MAX_PLANES];
1738 struct vlv_wm_ddl_values {
1739 uint8_t plane[I915_MAX_PLANES];
1742 struct vlv_wm_values {
1743 struct g4x_pipe_wm pipe[3];
1744 struct g4x_sr_wm sr;
1745 struct vlv_wm_ddl_values ddl[3];
1750 struct g4x_wm_values {
1751 struct g4x_pipe_wm pipe[2];
1752 struct g4x_sr_wm sr;
1753 struct g4x_sr_wm hpll;
1759 struct skl_ddb_entry {
1760 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1763 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1765 return entry->end - entry->start;
1768 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1769 const struct skl_ddb_entry *e2)
1771 if (e1->start == e2->start && e1->end == e2->end)
1777 struct skl_ddb_allocation {
1778 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1779 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1782 struct skl_wm_values {
1783 unsigned dirty_pipes;
1784 struct skl_ddb_allocation ddb;
1787 struct skl_wm_level {
1789 uint16_t plane_res_b;
1790 uint8_t plane_res_l;
1794 * This struct helps tracking the state needed for runtime PM, which puts the
1795 * device in PCI D3 state. Notice that when this happens, nothing on the
1796 * graphics device works, even register access, so we don't get interrupts nor
1799 * Every piece of our code that needs to actually touch the hardware needs to
1800 * either call intel_runtime_pm_get or call intel_display_power_get with the
1801 * appropriate power domain.
1803 * Our driver uses the autosuspend delay feature, which means we'll only really
1804 * suspend if we stay with zero refcount for a certain amount of time. The
1805 * default value is currently very conservative (see intel_runtime_pm_enable), but
1806 * it can be changed with the standard runtime PM files from sysfs.
1808 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1809 * goes back to false exactly before we reenable the IRQs. We use this variable
1810 * to check if someone is trying to enable/disable IRQs while they're supposed
1811 * to be disabled. This shouldn't happen and we'll print some error messages in
1814 * For more, read the Documentation/power/runtime_pm.txt.
1816 struct i915_runtime_pm {
1817 atomic_t wakeref_count;
1822 enum intel_pipe_crc_source {
1823 INTEL_PIPE_CRC_SOURCE_NONE,
1824 INTEL_PIPE_CRC_SOURCE_PLANE1,
1825 INTEL_PIPE_CRC_SOURCE_PLANE2,
1826 INTEL_PIPE_CRC_SOURCE_PF,
1827 INTEL_PIPE_CRC_SOURCE_PIPE,
1828 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1829 INTEL_PIPE_CRC_SOURCE_TV,
1830 INTEL_PIPE_CRC_SOURCE_DP_B,
1831 INTEL_PIPE_CRC_SOURCE_DP_C,
1832 INTEL_PIPE_CRC_SOURCE_DP_D,
1833 INTEL_PIPE_CRC_SOURCE_AUTO,
1834 INTEL_PIPE_CRC_SOURCE_MAX,
1837 struct intel_pipe_crc_entry {
1842 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1843 struct intel_pipe_crc {
1845 bool opened; /* exclusive access to the result file */
1846 struct intel_pipe_crc_entry *entries;
1847 enum intel_pipe_crc_source source;
1849 wait_queue_head_t wq;
1853 struct i915_frontbuffer_tracking {
1857 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1864 struct i915_wa_reg {
1867 /* bitmask representing WA bits */
1872 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1873 * allowing it for RCS as we don't foresee any requirement of having
1874 * a whitelist for other engines. When it is really required for
1875 * other engines then the limit need to be increased.
1877 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1879 struct i915_workarounds {
1880 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1882 u32 hw_whitelist_count[I915_NUM_ENGINES];
1885 struct i915_virtual_gpu {
1889 /* used in computing the new watermarks state */
1890 struct intel_wm_config {
1891 unsigned int num_pipes_active;
1892 bool sprites_enabled;
1893 bool sprites_scaled;
1896 struct i915_oa_format {
1901 struct i915_oa_reg {
1906 struct i915_perf_stream;
1909 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1911 struct i915_perf_stream_ops {
1913 * @enable: Enables the collection of HW samples, either in response to
1914 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1915 * without `I915_PERF_FLAG_DISABLED`.
1917 void (*enable)(struct i915_perf_stream *stream);
1920 * @disable: Disables the collection of HW samples, either in response
1921 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1924 void (*disable)(struct i915_perf_stream *stream);
1927 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1928 * once there is something ready to read() for the stream
1930 void (*poll_wait)(struct i915_perf_stream *stream,
1935 * @wait_unlocked: For handling a blocking read, wait until there is
1936 * something to ready to read() for the stream. E.g. wait on the same
1937 * wait queue that would be passed to poll_wait().
1939 int (*wait_unlocked)(struct i915_perf_stream *stream);
1942 * @read: Copy buffered metrics as records to userspace
1943 * **buf**: the userspace, destination buffer
1944 * **count**: the number of bytes to copy, requested by userspace
1945 * **offset**: zero at the start of the read, updated as the read
1946 * proceeds, it represents how many bytes have been copied so far and
1947 * the buffer offset for copying the next record.
1949 * Copy as many buffered i915 perf samples and records for this stream
1950 * to userspace as will fit in the given buffer.
1952 * Only write complete records; returning -%ENOSPC if there isn't room
1953 * for a complete record.
1955 * Return any error condition that results in a short read such as
1956 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1957 * returning to userspace.
1959 int (*read)(struct i915_perf_stream *stream,
1965 * @destroy: Cleanup any stream specific resources.
1967 * The stream will always be disabled before this is called.
1969 void (*destroy)(struct i915_perf_stream *stream);
1973 * struct i915_perf_stream - state for a single open stream FD
1975 struct i915_perf_stream {
1977 * @dev_priv: i915 drm device
1979 struct drm_i915_private *dev_priv;
1982 * @link: Links the stream into ``&drm_i915_private->streams``
1984 struct list_head link;
1987 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1988 * properties given when opening a stream, representing the contents
1989 * of a single sample as read() by userspace.
1994 * @sample_size: Considering the configured contents of a sample
1995 * combined with the required header size, this is the total size
1996 * of a single sample record.
2001 * @ctx: %NULL if measuring system-wide across all contexts or a
2002 * specific context that is being monitored.
2004 struct i915_gem_context *ctx;
2007 * @enabled: Whether the stream is currently enabled, considering
2008 * whether the stream was opened in a disabled state and based
2009 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2014 * @ops: The callbacks providing the implementation of this specific
2015 * type of configured stream.
2017 const struct i915_perf_stream_ops *ops;
2021 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2023 struct i915_oa_ops {
2025 * @init_oa_buffer: Resets the head and tail pointers of the
2026 * circular buffer for periodic OA reports.
2028 * Called when first opening a stream for OA metrics, but also may be
2029 * called in response to an OA buffer overflow or other error
2032 * Note it may be necessary to clear the full OA buffer here as part of
2033 * maintaining the invariable that new reports must be written to
2034 * zeroed memory for us to be able to reliable detect if an expected
2035 * report has not yet landed in memory. (At least on Haswell the OA
2036 * buffer tail pointer is not synchronized with reports being visible
2039 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2042 * @select_metric_set: The auto generated code that checks whether a
2043 * requested OA config is applicable to the system and if so sets up
2044 * the mux, oa and flex eu register config pointers according to the
2045 * current dev_priv->perf.oa.metrics_set.
2047 int (*select_metric_set)(struct drm_i915_private *dev_priv);
2050 * @enable_metric_set: Selects and applies any MUX configuration to set
2051 * up the Boolean and Custom (B/C) counters that are part of the
2052 * counter reports being sampled. May apply system constraints such as
2053 * disabling EU clock gating as required.
2055 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2058 * @disable_metric_set: Remove system constraints associated with using
2061 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2064 * @oa_enable: Enable periodic sampling
2066 void (*oa_enable)(struct drm_i915_private *dev_priv);
2069 * @oa_disable: Disable periodic sampling
2071 void (*oa_disable)(struct drm_i915_private *dev_priv);
2074 * @read: Copy data from the circular OA buffer into a given userspace
2077 int (*read)(struct i915_perf_stream *stream,
2083 * @oa_hw_tail_read: read the OA tail pointer register
2085 * In particular this enables us to share all the fiddly code for
2086 * handling the OA unit tail pointer race that affects multiple
2089 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
2092 struct intel_cdclk_state {
2093 unsigned int cdclk, vco, ref;
2096 struct drm_i915_private {
2097 struct drm_device drm;
2099 struct kmem_cache *objects;
2100 struct kmem_cache *vmas;
2101 struct kmem_cache *requests;
2102 struct kmem_cache *dependencies;
2103 struct kmem_cache *priorities;
2105 const struct intel_device_info info;
2109 struct intel_uncore uncore;
2111 struct i915_virtual_gpu vgpu;
2113 struct intel_gvt *gvt;
2115 struct intel_huc huc;
2116 struct intel_guc guc;
2118 struct intel_csr csr;
2120 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2122 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2123 * controller on different i2c buses. */
2124 struct mutex gmbus_mutex;
2127 * Base address of the gmbus and gpio block.
2129 uint32_t gpio_mmio_base;
2131 /* MMIO base address for MIPI regs */
2132 uint32_t mipi_mmio_base;
2134 uint32_t psr_mmio_base;
2136 uint32_t pps_mmio_base;
2138 wait_queue_head_t gmbus_wait_queue;
2140 struct pci_dev *bridge_dev;
2141 struct i915_gem_context *kernel_context;
2142 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2143 struct i915_vma *semaphore;
2145 struct drm_dma_handle *status_page_dmah;
2146 struct resource mch_res;
2148 /* protects the irq masks */
2149 spinlock_t irq_lock;
2151 /* protects the mmio flip data */
2152 spinlock_t mmio_flip_lock;
2154 bool display_irqs_enabled;
2156 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2157 struct pm_qos_request pm_qos;
2159 /* Sideband mailbox protection */
2160 struct mutex sb_lock;
2162 /** Cached value of IMR to avoid reads in updating the bitfield */
2165 u32 de_irq_mask[I915_MAX_PIPES];
2172 u32 pipestat_irq_mask[I915_MAX_PIPES];
2174 struct i915_hotplug hotplug;
2175 struct intel_fbc fbc;
2176 struct i915_drrs drrs;
2177 struct intel_opregion opregion;
2178 struct intel_vbt_data vbt;
2180 bool preserve_bios_swizzle;
2183 struct intel_overlay *overlay;
2185 /* backlight registers and fields in struct intel_panel */
2186 struct mutex backlight_lock;
2189 bool no_aux_handshake;
2191 /* protects panel power sequencer state */
2192 struct mutex pps_mutex;
2194 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2195 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2197 unsigned int fsb_freq, mem_freq, is_ddr3;
2198 unsigned int skl_preferred_vco_freq;
2199 unsigned int max_cdclk_freq;
2201 unsigned int max_dotclk_freq;
2202 unsigned int rawclk_freq;
2203 unsigned int hpll_freq;
2204 unsigned int czclk_freq;
2208 * The current logical cdclk state.
2209 * See intel_atomic_state.cdclk.logical
2211 * For reading holding any crtc lock is sufficient,
2212 * for writing must hold all of them.
2214 struct intel_cdclk_state logical;
2216 * The current actual cdclk state.
2217 * See intel_atomic_state.cdclk.actual
2219 struct intel_cdclk_state actual;
2220 /* The current hardware cdclk state */
2221 struct intel_cdclk_state hw;
2225 * wq - Driver workqueue for GEM.
2227 * NOTE: Work items scheduled here are not allowed to grab any modeset
2228 * locks, for otherwise the flushing done in the pageflip code will
2229 * result in deadlocks.
2231 struct workqueue_struct *wq;
2233 /* Display functions */
2234 struct drm_i915_display_funcs display;
2236 /* PCH chipset type */
2237 enum intel_pch pch_type;
2238 unsigned short pch_id;
2240 unsigned long quirks;
2242 enum modeset_restore modeset_restore;
2243 struct mutex modeset_restore_lock;
2244 struct drm_atomic_state *modeset_restore_state;
2245 struct drm_modeset_acquire_ctx reset_ctx;
2247 struct list_head vm_list; /* Global list of all address spaces */
2248 struct i915_ggtt ggtt; /* VM representing the global address space */
2250 struct i915_gem_mm mm;
2251 DECLARE_HASHTABLE(mm_structs, 7);
2252 struct mutex mm_lock;
2254 /* Kernel Modesetting */
2256 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2257 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2258 wait_queue_head_t pending_flip_queue;
2260 #ifdef CONFIG_DEBUG_FS
2261 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2264 /* dpll and cdclk state is protected by connection_mutex */
2265 int num_shared_dpll;
2266 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2267 const struct intel_dpll_mgr *dpll_mgr;
2270 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2271 * Must be global rather than per dpll, because on some platforms
2272 * plls share registers.
2274 struct mutex dpll_lock;
2276 unsigned int active_crtcs;
2277 unsigned int min_pixclk[I915_MAX_PIPES];
2279 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2281 struct i915_workarounds workarounds;
2283 struct i915_frontbuffer_tracking fb_tracking;
2285 struct intel_atomic_helper {
2286 struct llist_head free_list;
2287 struct work_struct free_work;
2292 bool mchbar_need_disable;
2294 struct intel_l3_parity l3_parity;
2296 /* Cannot be determined by PCIID. You must always read a register. */
2299 /* gen6+ rps state */
2300 struct intel_gen6_power_mgmt rps;
2302 /* ilk-only ips/rps state. Everything in here is protected by the global
2303 * mchdev_lock in intel_pm.c */
2304 struct intel_ilk_power_mgmt ips;
2306 struct i915_power_domains power_domains;
2308 struct i915_psr psr;
2310 struct i915_gpu_error gpu_error;
2312 struct drm_i915_gem_object *vlv_pctx;
2314 /* list of fbdev register on this device */
2315 struct intel_fbdev *fbdev;
2316 struct work_struct fbdev_suspend_work;
2318 struct drm_property *broadcast_rgb_property;
2319 struct drm_property *force_audio_property;
2321 /* hda/i915 audio component */
2322 struct i915_audio_component *audio_component;
2323 bool audio_component_registered;
2325 * av_mutex - mutex for audio/video sync
2328 struct mutex av_mutex;
2331 struct list_head list;
2332 struct llist_head free_list;
2333 struct work_struct free_work;
2335 /* The hw wants to have a stable context identifier for the
2336 * lifetime of the context (for OA, PASID, faults, etc).
2337 * This is limited in execlists to 21 bits.
2340 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2345 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2346 u32 chv_phy_control;
2348 * Shadows for CHV DPLL_MD regs to keep the state
2349 * checker somewhat working in the presence hardware
2350 * crappiness (can't read out DPLL_MD for pipes B & C).
2352 u32 chv_dpll_md[I915_MAX_PIPES];
2356 bool suspended_to_idle;
2357 struct i915_suspend_saved_registers regfile;
2358 struct vlv_s0ix_state vlv_s0ix_state;
2361 I915_SAGV_UNKNOWN = 0,
2364 I915_SAGV_NOT_CONTROLLED
2369 * Raw watermark latency values:
2370 * in 0.1us units for WM0,
2371 * in 0.5us units for WM1+.
2374 uint16_t pri_latency[5];
2376 uint16_t spr_latency[5];
2378 uint16_t cur_latency[5];
2380 * Raw watermark memory latency values
2381 * for SKL for all 8 levels
2384 uint16_t skl_latency[8];
2386 /* current hardware state */
2388 struct ilk_wm_values hw;
2389 struct skl_wm_values skl_hw;
2390 struct vlv_wm_values vlv;
2391 struct g4x_wm_values g4x;
2397 * Should be held around atomic WM register writing; also
2398 * protects * intel_crtc->wm.active and
2399 * cstate->wm.need_postvbl_update.
2401 struct mutex wm_mutex;
2404 * Set during HW readout of watermarks/DDB. Some platforms
2405 * need to know when we're still using BIOS-provided values
2406 * (which we don't fully trust).
2408 bool distrust_bios_wm;
2411 struct i915_runtime_pm pm;
2416 struct kobject *metrics_kobj;
2417 struct ctl_table_header *sysctl_header;
2420 struct list_head streams;
2423 struct i915_perf_stream *exclusive_stream;
2425 u32 specific_ctx_id;
2427 struct hrtimer poll_check_timer;
2428 wait_queue_head_t poll_wq;
2432 * For rate limiting any notifications of spurious
2433 * invalid OA reports
2435 struct ratelimit_state spurious_report_rs;
2438 int period_exponent;
2439 int timestamp_frequency;
2443 const struct i915_oa_reg *mux_regs[6];
2444 int mux_regs_lens[6];
2447 const struct i915_oa_reg *b_counter_regs;
2448 int b_counter_regs_len;
2449 const struct i915_oa_reg *flex_regs;
2453 struct i915_vma *vma;
2460 * Locks reads and writes to all head/tail state
2462 * Consider: the head and tail pointer state
2463 * needs to be read consistently from a hrtimer
2464 * callback (atomic context) and read() fop
2465 * (user context) with tail pointer updates
2466 * happening in atomic context and head updates
2467 * in user context and the (unlikely)
2468 * possibility of read() errors needing to
2469 * reset all head/tail state.
2471 * Note: Contention or performance aren't
2472 * currently a significant concern here
2473 * considering the relatively low frequency of
2474 * hrtimer callbacks (5ms period) and that
2475 * reads typically only happen in response to a
2476 * hrtimer event and likely complete before the
2479 * Note: This lock is not held *while* reading
2480 * and copying data to userspace so the value
2481 * of head observed in htrimer callbacks won't
2482 * represent any partial consumption of data.
2484 spinlock_t ptr_lock;
2487 * One 'aging' tail pointer and one 'aged'
2488 * tail pointer ready to used for reading.
2490 * Initial values of 0xffffffff are invalid
2491 * and imply that an update is required
2492 * (and should be ignored by an attempted
2500 * Index for the aged tail ready to read()
2503 unsigned int aged_tail_idx;
2506 * A monotonic timestamp for when the current
2507 * aging tail pointer was read; used to
2508 * determine when it is old enough to trust.
2510 u64 aging_timestamp;
2513 * Although we can always read back the head
2514 * pointer register, we prefer to avoid
2515 * trusting the HW state, just to avoid any
2516 * risk that some hardware condition could
2517 * somehow bump the head pointer unpredictably
2518 * and cause us to forward the wrong OA buffer
2519 * data to userspace.
2524 u32 gen7_latched_oastatus1;
2525 u32 ctx_oactxctrl_offset;
2526 u32 ctx_flexeu0_offset;
2529 * The RPT_ID/reason field for Gen8+ includes a bit
2530 * to determine if the CTX ID in the report is valid
2531 * but the specific bit differs between Gen 8 and 9
2533 u32 gen8_valid_ctx_bit;
2535 struct i915_oa_ops ops;
2536 const struct i915_oa_format *oa_formats;
2541 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2543 void (*resume)(struct drm_i915_private *);
2544 void (*cleanup_engine)(struct intel_engine_cs *engine);
2546 struct list_head timelines;
2547 struct i915_gem_timeline global_timeline;
2548 u32 active_requests;
2551 * Is the GPU currently considered idle, or busy executing
2552 * userspace requests? Whilst idle, we allow runtime power
2553 * management to power down the hardware and display clocks.
2554 * In order to reduce the effect on performance, there
2555 * is a slight delay before we do so.
2560 * We leave the user IRQ off as much as possible,
2561 * but this means that requests will finish and never
2562 * be retired once the system goes idle. Set a timer to
2563 * fire periodically while the ring is running. When it
2564 * fires, go retire requests.
2566 struct delayed_work retire_work;
2569 * When we detect an idle GPU, we want to turn on
2570 * powersaving features. So once we see that there
2571 * are no more requests outstanding and no more
2572 * arrive within a small period of time, we fire
2573 * off the idle_work.
2575 struct delayed_work idle_work;
2577 ktime_t last_init_time;
2580 /* perform PHY state sanity checks? */
2581 bool chv_phy_assert[2];
2585 /* Used to save the pipe-to-encoder mapping for audio */
2586 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2588 /* necessary resource sharing with HDMI LPE audio driver. */
2590 struct platform_device *platdev;
2595 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2596 * will be rejected. Instead look for a better place.
2600 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2602 return container_of(dev, struct drm_i915_private, drm);
2605 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2607 return to_i915(dev_get_drvdata(kdev));
2610 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2612 return container_of(guc, struct drm_i915_private, guc);
2615 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2617 return container_of(huc, struct drm_i915_private, huc);
2620 /* Simple iterator over all initialised engines */
2621 #define for_each_engine(engine__, dev_priv__, id__) \
2623 (id__) < I915_NUM_ENGINES; \
2625 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2627 /* Iterator over subset of engines selected by mask */
2628 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2629 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2630 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2632 enum hdmi_force_audio {
2633 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2634 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2635 HDMI_AUDIO_AUTO, /* trust EDID */
2636 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2639 #define I915_GTT_OFFSET_NONE ((u32)-1)
2642 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2643 * considered to be the frontbuffer for the given plane interface-wise. This
2644 * doesn't mean that the hw necessarily already scans it out, but that any
2645 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2647 * We have one bit per pipe and per scanout plane type.
2649 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2650 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2651 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2652 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2653 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2654 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2655 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2656 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2657 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2658 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2659 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2660 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2663 * Optimised SGL iterator for GEM objects
2665 static __always_inline struct sgt_iter {
2666 struct scatterlist *sgp;
2673 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2674 struct sgt_iter s = { .sgp = sgl };
2677 s.max = s.curr = s.sgp->offset;
2678 s.max += s.sgp->length;
2680 s.dma = sg_dma_address(s.sgp);
2682 s.pfn = page_to_pfn(sg_page(s.sgp));
2688 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2691 if (unlikely(sg_is_chain(sg)))
2692 sg = sg_chain_ptr(sg);
2697 * __sg_next - return the next scatterlist entry in a list
2698 * @sg: The current sg entry
2701 * If the entry is the last, return NULL; otherwise, step to the next
2702 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2703 * otherwise just return the pointer to the current element.
2705 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2707 #ifdef CONFIG_DEBUG_SG
2708 BUG_ON(sg->sg_magic != SG_MAGIC);
2710 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2714 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2715 * @__dmap: DMA address (output)
2716 * @__iter: 'struct sgt_iter' (iterator state, internal)
2717 * @__sgt: sg_table to iterate over (input)
2719 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2720 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2721 ((__dmap) = (__iter).dma + (__iter).curr); \
2722 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2723 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2726 * for_each_sgt_page - iterate over the pages of the given sg_table
2727 * @__pp: page pointer (output)
2728 * @__iter: 'struct sgt_iter' (iterator state, internal)
2729 * @__sgt: sg_table to iterate over (input)
2731 #define for_each_sgt_page(__pp, __iter, __sgt) \
2732 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2733 ((__pp) = (__iter).pfn == 0 ? NULL : \
2734 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2735 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2736 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2738 static inline const struct intel_device_info *
2739 intel_info(const struct drm_i915_private *dev_priv)
2741 return &dev_priv->info;
2744 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2746 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2747 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2749 #define REVID_FOREVER 0xff
2750 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2752 #define GEN_FOREVER (0)
2754 * Returns true if Gen is in inclusive range [Start, End].
2756 * Use GEN_FOREVER for unbound start and or end.
2758 #define IS_GEN(dev_priv, s, e) ({ \
2759 unsigned int __s = (s), __e = (e); \
2760 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2761 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2762 if ((__s) != GEN_FOREVER) \
2764 if ((__e) == GEN_FOREVER) \
2765 __e = BITS_PER_LONG - 1; \
2768 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2772 * Return true if revision is in range [since,until] inclusive.
2774 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2776 #define IS_REVID(p, since, until) \
2777 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2779 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2780 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2781 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2782 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2783 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2784 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2785 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2786 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2787 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2788 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2789 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2790 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2791 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2792 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2793 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2794 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2795 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2796 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2797 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2798 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2799 INTEL_DEVID(dev_priv) == 0x0152 || \
2800 INTEL_DEVID(dev_priv) == 0x015a)
2801 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2802 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2803 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2804 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2805 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2806 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2807 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2808 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2809 #define IS_COFFEELAKE(dev_priv) ((dev_priv)->info.platform == INTEL_COFFEELAKE)
2810 #define IS_CANNONLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_CANNONLAKE)
2811 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2812 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2813 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2814 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2815 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2816 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2817 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2818 /* ULX machines are also considered ULT. */
2819 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2820 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2821 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2822 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2823 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2824 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2825 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2826 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2827 /* ULX machines are also considered ULT. */
2828 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2829 INTEL_DEVID(dev_priv) == 0x0A1E)
2830 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2831 INTEL_DEVID(dev_priv) == 0x1913 || \
2832 INTEL_DEVID(dev_priv) == 0x1916 || \
2833 INTEL_DEVID(dev_priv) == 0x1921 || \
2834 INTEL_DEVID(dev_priv) == 0x1926)
2835 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2836 INTEL_DEVID(dev_priv) == 0x1915 || \
2837 INTEL_DEVID(dev_priv) == 0x191E)
2838 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2839 INTEL_DEVID(dev_priv) == 0x5913 || \
2840 INTEL_DEVID(dev_priv) == 0x5916 || \
2841 INTEL_DEVID(dev_priv) == 0x5921 || \
2842 INTEL_DEVID(dev_priv) == 0x5926)
2843 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2844 INTEL_DEVID(dev_priv) == 0x5915 || \
2845 INTEL_DEVID(dev_priv) == 0x591E)
2846 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2847 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
2848 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2849 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2850 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2851 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2852 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2853 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
2854 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2855 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2856 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2857 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2859 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2861 #define SKL_REVID_A0 0x0
2862 #define SKL_REVID_B0 0x1
2863 #define SKL_REVID_C0 0x2
2864 #define SKL_REVID_D0 0x3
2865 #define SKL_REVID_E0 0x4
2866 #define SKL_REVID_F0 0x5
2867 #define SKL_REVID_G0 0x6
2868 #define SKL_REVID_H0 0x7
2870 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2872 #define BXT_REVID_A0 0x0
2873 #define BXT_REVID_A1 0x1
2874 #define BXT_REVID_B0 0x3
2875 #define BXT_REVID_B_LAST 0x8
2876 #define BXT_REVID_C0 0x9
2878 #define IS_BXT_REVID(dev_priv, since, until) \
2879 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2881 #define KBL_REVID_A0 0x0
2882 #define KBL_REVID_B0 0x1
2883 #define KBL_REVID_C0 0x2
2884 #define KBL_REVID_D0 0x3
2885 #define KBL_REVID_E0 0x4
2887 #define IS_KBL_REVID(dev_priv, since, until) \
2888 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2890 #define GLK_REVID_A0 0x0
2891 #define GLK_REVID_A1 0x1
2893 #define IS_GLK_REVID(dev_priv, since, until) \
2894 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2896 #define CNL_REVID_A0 0x0
2897 #define CNL_REVID_B0 0x1
2899 #define IS_CNL_REVID(p, since, until) \
2900 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2903 * The genX designation typically refers to the render engine, so render
2904 * capability related checks should use IS_GEN, while display and other checks
2905 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2908 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2909 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2910 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2911 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2912 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2913 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2914 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2915 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2916 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2918 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2919 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2920 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2922 #define ENGINE_MASK(id) BIT(id)
2923 #define RENDER_RING ENGINE_MASK(RCS)
2924 #define BSD_RING ENGINE_MASK(VCS)
2925 #define BLT_RING ENGINE_MASK(BCS)
2926 #define VEBOX_RING ENGINE_MASK(VECS)
2927 #define BSD2_RING ENGINE_MASK(VCS2)
2928 #define ALL_ENGINES (~0)
2930 #define HAS_ENGINE(dev_priv, id) \
2931 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2933 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2934 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2935 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2936 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2938 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2939 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2940 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2941 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2942 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2944 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2946 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2947 ((dev_priv)->info.has_logical_ring_contexts)
2948 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2949 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2950 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2952 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2953 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2954 ((dev_priv)->info.overlay_needs_physical)
2956 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2957 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2959 /* WaRsDisableCoarsePowerGating:skl,bxt */
2960 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2961 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2964 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2965 * even when in MSI mode. This results in spurious interrupt warnings if the
2966 * legacy irq no. is shared with another device. The kernel then disables that
2967 * interrupt source and so prevents the other device from working properly.
2969 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2970 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2972 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2973 * rows, which changed the alignment requirements and fence programming.
2975 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2976 !(IS_I915G(dev_priv) || \
2977 IS_I915GM(dev_priv)))
2978 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2979 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2981 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2982 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2983 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2984 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2986 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2988 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2990 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2991 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2992 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2993 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2994 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2996 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2998 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2999 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
3002 * For now, anything with a GuC requires uCode loading, and then supports
3003 * command submission once loaded. But these are logically independent
3004 * properties, so we have separate macros to test them.
3006 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
3007 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
3008 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3009 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
3010 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3012 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
3014 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
3016 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
3017 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3018 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
3019 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3020 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3021 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
3022 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
3023 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
3024 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
3025 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
3026 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
3027 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
3028 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
3029 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
3030 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
3031 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3033 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3034 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3035 #define HAS_PCH_CNP_LP(dev_priv) \
3036 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3037 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
3038 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
3039 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3040 #define HAS_PCH_LPT_LP(dev_priv) \
3041 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
3042 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
3043 #define HAS_PCH_LPT_H(dev_priv) \
3044 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
3045 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
3046 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3047 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3048 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3049 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3051 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3053 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3055 /* DPF == dynamic parity feature */
3056 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3057 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3058 2 : HAS_L3_DPF(dev_priv))
3060 #define GT_FREQUENCY_MULTIPLIER 50
3061 #define GEN9_FREQ_SCALER 3
3063 #include "i915_trace.h"
3065 static inline bool intel_vtd_active(void)
3067 #ifdef CONFIG_INTEL_IOMMU
3068 if (intel_iommu_gfx_mapped)
3074 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
3076 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
3080 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
3082 return IS_BROXTON(dev_priv) && intel_vtd_active();
3085 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
3088 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
3092 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
3093 const char *fmt, ...);
3095 #define i915_report_error(dev_priv, fmt, ...) \
3096 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3098 #ifdef CONFIG_COMPAT
3099 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
3102 #define i915_compat_ioctl NULL
3104 extern const struct dev_pm_ops i915_pm_ops;
3106 extern int i915_driver_load(struct pci_dev *pdev,
3107 const struct pci_device_id *ent);
3108 extern void i915_driver_unload(struct drm_device *dev);
3109 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3110 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3111 extern void i915_reset(struct drm_i915_private *dev_priv);
3112 extern int i915_reset_engine(struct intel_engine_cs *engine);
3113 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
3114 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3115 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3116 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3117 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3118 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3119 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3120 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3121 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3123 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
3124 int intel_engines_init(struct drm_i915_private *dev_priv);
3126 /* intel_hotplug.c */
3127 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3128 u32 pin_mask, u32 long_mask);
3129 void intel_hpd_init(struct drm_i915_private *dev_priv);
3130 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3131 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3132 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3133 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3134 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3137 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3139 unsigned long delay;
3141 if (unlikely(!i915.enable_hangcheck))
3144 /* Don't continually defer the hangcheck so that it is always run at
3145 * least once after work has been scheduled on any ring. Otherwise,
3146 * we will ignore a hung ring if a second ring is kept busy.
3149 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3150 queue_delayed_work(system_long_wq,
3151 &dev_priv->gpu_error.hangcheck_work, delay);
3155 void i915_handle_error(struct drm_i915_private *dev_priv,
3157 const char *fmt, ...);
3159 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3160 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
3161 int intel_irq_install(struct drm_i915_private *dev_priv);
3162 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3164 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3166 return dev_priv->gvt;
3169 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3171 return dev_priv->vgpu.active;
3175 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3179 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3182 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3183 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3184 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3187 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3188 uint32_t interrupt_mask,
3189 uint32_t enabled_irq_mask);
3191 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3193 ilk_update_display_irq(dev_priv, bits, bits);
3196 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3198 ilk_update_display_irq(dev_priv, bits, 0);
3200 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3202 uint32_t interrupt_mask,
3203 uint32_t enabled_irq_mask);
3204 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3205 enum pipe pipe, uint32_t bits)
3207 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3209 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3210 enum pipe pipe, uint32_t bits)
3212 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3214 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3215 uint32_t interrupt_mask,
3216 uint32_t enabled_irq_mask);
3218 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3220 ibx_display_interrupt_update(dev_priv, bits, bits);
3223 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3225 ibx_display_interrupt_update(dev_priv, bits, 0);
3229 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3230 struct drm_file *file_priv);
3231 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3232 struct drm_file *file_priv);
3233 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3234 struct drm_file *file_priv);
3235 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3236 struct drm_file *file_priv);
3237 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3238 struct drm_file *file_priv);
3239 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3240 struct drm_file *file_priv);
3241 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3242 struct drm_file *file_priv);
3243 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3244 struct drm_file *file_priv);
3245 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3246 struct drm_file *file_priv);
3247 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3248 struct drm_file *file_priv);
3249 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3250 struct drm_file *file);
3251 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3252 struct drm_file *file);
3253 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3254 struct drm_file *file_priv);
3255 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3256 struct drm_file *file_priv);
3257 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3258 struct drm_file *file_priv);
3259 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3260 struct drm_file *file_priv);
3261 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3262 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
3263 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3264 struct drm_file *file);
3265 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3266 struct drm_file *file_priv);
3267 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3268 struct drm_file *file_priv);
3269 void i915_gem_sanitize(struct drm_i915_private *i915);
3270 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3271 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3272 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3273 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3274 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3276 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3277 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3278 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3279 const struct drm_i915_gem_object_ops *ops);
3280 struct drm_i915_gem_object *
3281 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3282 struct drm_i915_gem_object *
3283 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3284 const void *data, size_t size);
3285 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3286 void i915_gem_free_object(struct drm_gem_object *obj);
3288 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3290 /* A single pass should suffice to release all the freed objects (along
3291 * most call paths) , but be a little more paranoid in that freeing
3292 * the objects does take a little amount of time, during which the rcu
3293 * callbacks could have added new objects into the freed list, and
3294 * armed the work again.
3298 } while (flush_work(&i915->mm.free_work));
3301 struct i915_vma * __must_check
3302 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3303 const struct i915_ggtt_view *view,
3308 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3309 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3311 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3313 static inline int __sg_page_count(const struct scatterlist *sg)
3315 return sg->length >> PAGE_SHIFT;
3318 struct scatterlist *
3319 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3320 unsigned int n, unsigned int *offset);
3323 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3327 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3331 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3334 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3335 struct sg_table *pages);
3336 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3338 static inline int __must_check
3339 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3341 might_lock(&obj->mm.lock);
3343 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3346 return __i915_gem_object_get_pages(obj);
3350 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3352 GEM_BUG_ON(!obj->mm.pages);
3354 atomic_inc(&obj->mm.pages_pin_count);
3358 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3360 return atomic_read(&obj->mm.pages_pin_count);
3364 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3366 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3367 GEM_BUG_ON(!obj->mm.pages);
3369 atomic_dec(&obj->mm.pages_pin_count);
3373 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3375 __i915_gem_object_unpin_pages(obj);
3378 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3383 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3384 enum i915_mm_subclass subclass);
3385 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3387 enum i915_map_type {
3393 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3394 * @obj: the object to map into kernel address space
3395 * @type: the type of mapping, used to select pgprot_t
3397 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3398 * pages and then returns a contiguous mapping of the backing storage into
3399 * the kernel address space. Based on the @type of mapping, the PTE will be
3400 * set to either WriteBack or WriteCombine (via pgprot_t).
3402 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3403 * mapping is no longer required.
3405 * Returns the pointer through which to access the mapped object, or an
3406 * ERR_PTR() on error.
3408 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3409 enum i915_map_type type);
3412 * i915_gem_object_unpin_map - releases an earlier mapping
3413 * @obj: the object to unmap
3415 * After pinning the object and mapping its pages, once you are finished
3416 * with your access, call i915_gem_object_unpin_map() to release the pin
3417 * upon the mapping. Once the pin count reaches zero, that mapping may be
3420 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3422 i915_gem_object_unpin_pages(obj);
3425 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3426 unsigned int *needs_clflush);
3427 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3428 unsigned int *needs_clflush);
3429 #define CLFLUSH_BEFORE BIT(0)
3430 #define CLFLUSH_AFTER BIT(1)
3431 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3434 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3436 i915_gem_object_unpin_pages(obj);
3439 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3440 void i915_vma_move_to_active(struct i915_vma *vma,
3441 struct drm_i915_gem_request *req,
3442 unsigned int flags);
3443 int i915_gem_dumb_create(struct drm_file *file_priv,
3444 struct drm_device *dev,
3445 struct drm_mode_create_dumb *args);
3446 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3447 uint32_t handle, uint64_t *offset);
3448 int i915_gem_mmap_gtt_version(void);
3450 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3451 struct drm_i915_gem_object *new,
3452 unsigned frontbuffer_bits);
3454 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3456 struct drm_i915_gem_request *
3457 i915_gem_find_active_request(struct intel_engine_cs *engine);
3459 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3461 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3463 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3466 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3468 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3471 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3473 return unlikely(test_bit(I915_WEDGED, &error->flags));
3476 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3478 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3481 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3483 return READ_ONCE(error->reset_count);
3486 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3487 struct intel_engine_cs *engine)
3489 return READ_ONCE(error->reset_engine_count[engine->id]);
3492 struct drm_i915_gem_request *
3493 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3494 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3495 void i915_gem_reset(struct drm_i915_private *dev_priv);
3496 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3497 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3498 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3499 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3500 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3501 struct drm_i915_gem_request *request);
3503 void i915_gem_init_mmio(struct drm_i915_private *i915);
3504 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3505 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3506 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3507 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3508 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3509 unsigned int flags);
3510 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3511 void i915_gem_resume(struct drm_i915_private *dev_priv);
3512 int i915_gem_fault(struct vm_fault *vmf);
3513 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3516 struct intel_rps_client *rps);
3517 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3520 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3523 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3525 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3527 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3528 struct i915_vma * __must_check
3529 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3531 const struct i915_ggtt_view *view);
3532 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3533 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3535 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3536 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3538 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3539 enum i915_cache_level cache_level);
3541 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3542 struct dma_buf *dma_buf);
3544 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3545 struct drm_gem_object *gem_obj, int flags);
3547 static inline struct i915_hw_ppgtt *
3548 i915_vm_to_ppgtt(struct i915_address_space *vm)
3550 return container_of(vm, struct i915_hw_ppgtt, base);
3553 /* i915_gem_fence_reg.c */
3554 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3555 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3557 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3558 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3560 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3561 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3562 struct sg_table *pages);
3563 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3564 struct sg_table *pages);
3566 static inline struct i915_gem_context *
3567 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3569 return idr_find(&file_priv->context_idr, id);
3572 static inline struct i915_gem_context *
3573 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3575 struct i915_gem_context *ctx;
3578 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3579 if (ctx && !kref_get_unless_zero(&ctx->ref))
3586 static inline struct intel_timeline *
3587 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3588 struct intel_engine_cs *engine)
3590 struct i915_address_space *vm;
3592 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3593 return &vm->timeline.engine[engine->id];
3596 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3597 struct drm_file *file);
3598 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3599 struct i915_gem_context *ctx,
3600 uint32_t *reg_state);
3602 /* i915_gem_evict.c */
3603 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3604 u64 min_size, u64 alignment,
3605 unsigned cache_level,
3608 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3609 struct drm_mm_node *node,
3610 unsigned int flags);
3611 int i915_gem_evict_vm(struct i915_address_space *vm);
3613 /* belongs in i915_gem_gtt.h */
3614 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3617 if (INTEL_GEN(dev_priv) < 6)
3618 intel_gtt_chipset_flush();
3621 /* i915_gem_stolen.c */
3622 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3623 struct drm_mm_node *node, u64 size,
3624 unsigned alignment);
3625 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3626 struct drm_mm_node *node, u64 size,
3627 unsigned alignment, u64 start,
3629 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3630 struct drm_mm_node *node);
3631 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3632 void i915_gem_cleanup_stolen(struct drm_device *dev);
3633 struct drm_i915_gem_object *
3634 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3635 struct drm_i915_gem_object *
3636 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3641 /* i915_gem_internal.c */
3642 struct drm_i915_gem_object *
3643 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3646 /* i915_gem_shrinker.c */
3647 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3648 unsigned long target,
3650 #define I915_SHRINK_PURGEABLE 0x1
3651 #define I915_SHRINK_UNBOUND 0x2
3652 #define I915_SHRINK_BOUND 0x4
3653 #define I915_SHRINK_ACTIVE 0x8
3654 #define I915_SHRINK_VMAPS 0x10
3655 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3656 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3657 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3660 /* i915_gem_tiling.c */
3661 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3663 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3665 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3666 i915_gem_object_is_tiled(obj);
3669 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3670 unsigned int tiling, unsigned int stride);
3671 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3672 unsigned int tiling, unsigned int stride);
3674 /* i915_debugfs.c */
3675 #ifdef CONFIG_DEBUG_FS
3676 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3677 int i915_debugfs_connector_add(struct drm_connector *connector);
3678 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3680 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3681 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3683 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3686 /* i915_gpu_error.c */
3687 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3690 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3691 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3692 const struct i915_gpu_state *gpu);
3693 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3694 struct drm_i915_private *i915,
3695 size_t count, loff_t pos);
3696 static inline void i915_error_state_buf_release(
3697 struct drm_i915_error_state_buf *eb)
3702 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3703 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3705 const char *error_msg);
3707 static inline struct i915_gpu_state *
3708 i915_gpu_state_get(struct i915_gpu_state *gpu)
3710 kref_get(&gpu->ref);
3714 void __i915_gpu_state_free(struct kref *kref);
3715 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3718 kref_put(&gpu->ref, __i915_gpu_state_free);
3721 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3722 void i915_reset_error_state(struct drm_i915_private *i915);
3726 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3728 const char *error_msg)
3732 static inline struct i915_gpu_state *
3733 i915_first_error_state(struct drm_i915_private *i915)
3738 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3744 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3746 /* i915_cmd_parser.c */
3747 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3748 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3749 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3750 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3751 struct drm_i915_gem_object *batch_obj,
3752 struct drm_i915_gem_object *shadow_batch_obj,
3753 u32 batch_start_offset,
3758 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3759 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3760 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3761 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3763 /* i915_suspend.c */
3764 extern int i915_save_state(struct drm_i915_private *dev_priv);
3765 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3768 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3769 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3771 /* intel_lpe_audio.c */
3772 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3773 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3774 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3775 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3776 enum pipe pipe, enum port port,
3777 const void *eld, int ls_clock, bool dp_output);
3780 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3781 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3782 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3785 extern struct i2c_adapter *
3786 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3787 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3788 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3789 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3791 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3793 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3796 void intel_bios_init(struct drm_i915_private *dev_priv);
3797 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3798 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3799 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3800 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3801 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3802 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3803 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3804 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3806 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3810 /* intel_opregion.c */
3812 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3813 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3814 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3815 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3816 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3818 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3820 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3822 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3823 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3824 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3825 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3829 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3834 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3838 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3846 extern void intel_register_dsm_handler(void);
3847 extern void intel_unregister_dsm_handler(void);
3849 static inline void intel_register_dsm_handler(void) { return; }
3850 static inline void intel_unregister_dsm_handler(void) { return; }
3851 #endif /* CONFIG_ACPI */
3853 /* intel_device_info.c */
3854 static inline struct intel_device_info *
3855 mkwrite_device_info(struct drm_i915_private *dev_priv)
3857 return (struct intel_device_info *)&dev_priv->info;
3860 const char *intel_platform_name(enum intel_platform platform);
3861 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3862 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3865 extern void intel_modeset_init_hw(struct drm_device *dev);
3866 extern int intel_modeset_init(struct drm_device *dev);
3867 extern void intel_modeset_gem_init(struct drm_device *dev);
3868 extern void intel_modeset_cleanup(struct drm_device *dev);
3869 extern int intel_connector_register(struct drm_connector *);
3870 extern void intel_connector_unregister(struct drm_connector *);
3871 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3873 extern void intel_display_resume(struct drm_device *dev);
3874 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3875 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3876 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3877 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3878 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3879 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3882 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3883 struct drm_file *file);
3886 extern struct intel_overlay_error_state *
3887 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3888 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3889 struct intel_overlay_error_state *error);
3891 extern struct intel_display_error_state *
3892 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3893 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3894 struct intel_display_error_state *error);
3896 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3897 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3898 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3899 u32 reply_mask, u32 reply, int timeout_base_ms);
3901 /* intel_sideband.c */
3902 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3903 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3904 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3905 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3906 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3907 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3908 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3909 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3910 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3911 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3912 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3913 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3914 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3915 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3916 enum intel_sbi_destination destination);
3917 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3918 enum intel_sbi_destination destination);
3919 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3920 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3922 /* intel_dpio_phy.c */
3923 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3924 enum dpio_phy *phy, enum dpio_channel *ch);
3925 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3926 enum port port, u32 margin, u32 scale,
3927 u32 enable, u32 deemphasis);
3928 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3929 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3930 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3932 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3934 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3935 uint8_t lane_count);
3936 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3937 uint8_t lane_lat_optim_mask);
3938 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3940 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3941 u32 deemph_reg_value, u32 margin_reg_value,
3942 bool uniq_trans_scale);
3943 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3945 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3946 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3947 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3948 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3950 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3951 u32 demph_reg_value, u32 preemph_reg_value,
3952 u32 uniqtranscale_reg_value, u32 tx3_demph);
3953 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3954 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3955 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3957 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3958 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3959 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3960 const i915_reg_t reg);
3962 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3963 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3965 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3966 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3967 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3968 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3970 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3971 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3972 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3973 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3975 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3976 * will be implemented using 2 32-bit writes in an arbitrary order with
3977 * an arbitrary delay between them. This can cause the hardware to
3978 * act upon the intermediate value, possibly leading to corruption and
3979 * machine death. For this reason we do not support I915_WRITE64, or
3980 * dev_priv->uncore.funcs.mmio_writeq.
3982 * When reading a 64-bit value as two 32-bit values, the delay may cause
3983 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3984 * occasionally a 64-bit register does not actualy support a full readq
3985 * and must be read using two 32-bit reads.
3987 * You have been warned.
3989 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3991 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3992 u32 upper, lower, old_upper, loop = 0; \
3993 upper = I915_READ(upper_reg); \
3995 old_upper = upper; \
3996 lower = I915_READ(lower_reg); \
3997 upper = I915_READ(upper_reg); \
3998 } while (upper != old_upper && loop++ < 2); \
3999 (u64)upper << 32 | lower; })
4001 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
4002 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
4004 #define __raw_read(x, s) \
4005 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
4008 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
4011 #define __raw_write(x, s) \
4012 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
4013 i915_reg_t reg, uint##x##_t val) \
4015 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
4030 /* These are untraced mmio-accessors that are only valid to be used inside
4031 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4034 * Think twice, and think again, before using these.
4036 * As an example, these accessors can possibly be used between:
4038 * spin_lock_irq(&dev_priv->uncore.lock);
4039 * intel_uncore_forcewake_get__locked();
4043 * intel_uncore_forcewake_put__locked();
4044 * spin_unlock_irq(&dev_priv->uncore.lock);
4047 * Note: some registers may not need forcewake held, so
4048 * intel_uncore_forcewake_{get,put} can be omitted, see
4049 * intel_uncore_forcewake_for_reg().
4051 * Certain architectures will die if the same cacheline is concurrently accessed
4052 * by different clients (e.g. on Ivybridge). Access to registers should
4053 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4054 * a more localised lock guarding all access to that bank of registers.
4056 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4057 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4058 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4059 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4061 /* "Broadcast RGB" property */
4062 #define INTEL_BROADCAST_RGB_AUTO 0
4063 #define INTEL_BROADCAST_RGB_FULL 1
4064 #define INTEL_BROADCAST_RGB_LIMITED 2
4066 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
4068 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4069 return VLV_VGACNTRL;
4070 else if (INTEL_GEN(dev_priv) >= 5)
4071 return CPU_VGACNTRL;
4076 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
4078 unsigned long j = msecs_to_jiffies(m);
4080 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4083 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
4085 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
4088 static inline unsigned long
4089 timespec_to_jiffies_timeout(const struct timespec *value)
4091 unsigned long j = timespec_to_jiffies(value);
4093 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4097 * If you need to wait X milliseconds between events A and B, but event B
4098 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4099 * when event A happened, then just before event B you call this function and
4100 * pass the timestamp as the first argument, and X as the second argument.
4103 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4105 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4108 * Don't re-read the value of "jiffies" every time since it may change
4109 * behind our back and break the math.
4111 tmp_jiffies = jiffies;
4112 target_jiffies = timestamp_jiffies +
4113 msecs_to_jiffies_timeout(to_wait_ms);
4115 if (time_after(target_jiffies, tmp_jiffies)) {
4116 remaining_jiffies = target_jiffies - tmp_jiffies;
4117 while (remaining_jiffies)
4119 schedule_timeout_uninterruptible(remaining_jiffies);
4124 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4126 struct intel_engine_cs *engine = req->engine;
4129 /* Note that the engine may have wrapped around the seqno, and
4130 * so our request->global_seqno will be ahead of the hardware,
4131 * even though it completed the request before wrapping. We catch
4132 * this by kicking all the waiters before resetting the seqno
4133 * in hardware, and also signal the fence.
4135 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4138 /* The request was dequeued before we were awoken. We check after
4139 * inspecting the hw to confirm that this was the same request
4140 * that generated the HWS update. The memory barriers within
4141 * the request execution are sufficient to ensure that a check
4142 * after reading the value from hw matches this request.
4144 seqno = i915_gem_request_global_seqno(req);
4148 /* Before we do the heavier coherent read of the seqno,
4149 * check the value (hopefully) in the CPU cacheline.
4151 if (__i915_gem_request_completed(req, seqno))
4154 /* Ensure our read of the seqno is coherent so that we
4155 * do not "miss an interrupt" (i.e. if this is the last
4156 * request and the seqno write from the GPU is not visible
4157 * by the time the interrupt fires, we will see that the
4158 * request is incomplete and go back to sleep awaiting
4159 * another interrupt that will never come.)
4161 * Strictly, we only need to do this once after an interrupt,
4162 * but it is easier and safer to do it every time the waiter
4165 if (engine->irq_seqno_barrier &&
4166 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4167 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4169 /* The ordering of irq_posted versus applying the barrier
4170 * is crucial. The clearing of the current irq_posted must
4171 * be visible before we perform the barrier operation,
4172 * such that if a subsequent interrupt arrives, irq_posted
4173 * is reasserted and our task rewoken (which causes us to
4174 * do another __i915_request_irq_complete() immediately
4175 * and reapply the barrier). Conversely, if the clear
4176 * occurs after the barrier, then an interrupt that arrived
4177 * whilst we waited on the barrier would not trigger a
4178 * barrier on the next pass, and the read may not see the
4181 engine->irq_seqno_barrier(engine);
4183 /* If we consume the irq, but we are no longer the bottom-half,
4184 * the real bottom-half may not have serialised their own
4185 * seqno check with the irq-barrier (i.e. may have inspected
4186 * the seqno before we believe it coherent since they see
4187 * irq_posted == false but we are still running).
4189 spin_lock_irq(&b->irq_lock);
4190 if (b->irq_wait && b->irq_wait->tsk != current)
4191 /* Note that if the bottom-half is changed as we
4192 * are sending the wake-up, the new bottom-half will
4193 * be woken by whomever made the change. We only have
4194 * to worry about when we steal the irq-posted for
4197 wake_up_process(b->irq_wait->tsk);
4198 spin_unlock_irq(&b->irq_lock);
4200 if (__i915_gem_request_completed(req, seqno))
4207 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4208 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4210 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4211 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4212 * perform the operation. To check beforehand, pass in the parameters to
4213 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4214 * you only need to pass in the minor offsets, page-aligned pointers are
4217 * For just checking for SSE4.1, in the foreknowledge that the future use
4218 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4220 #define i915_can_memcpy_from_wc(dst, src, len) \
4221 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4223 #define i915_has_memcpy_from_wc() \
4224 i915_memcpy_from_wc(NULL, NULL, 0)
4227 int remap_io_mapping(struct vm_area_struct *vma,
4228 unsigned long addr, unsigned long pfn, unsigned long size,
4229 struct io_mapping *iomap);
4231 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4233 return (obj->cache_level != I915_CACHE_NONE ||
4234 HAS_LLC(to_i915(obj->base.dev)));