drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hash.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/mm_types.h>
  44 #include <linux/perf_event.h>
  45 #include <linux/pm_qos.h>
  46 #include <linux/dma-resv.h>
  47 #include <linux/shmem_fs.h>
  48 #include <linux/stackdepot.h>
  49
  50 #include <drm/intel-gtt.h>
  51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  52 #include <drm/drm_gem.h>
  53 #include <drm/drm_auth.h>
  54 #include <drm/drm_cache.h>
  55 #include <drm/drm_util.h>
  56 #include <drm/drm_dsc.h>
  57 #include <drm/drm_atomic.h>
  58 #include <drm/drm_connector.h>
  59 #include <drm/i915_mei_hdcp_interface.h>
  60
  61 #include "i915_fixed.h"
  62 #include "i915_params.h"
  63 #include "i915_reg.h"
  64 #include "i915_utils.h"
  65
  66 #include "display/intel_bios.h"
  67 #include "display/intel_display.h"
  68 #include "display/intel_display_power.h"
  69 #include "display/intel_dpll_mgr.h"
  70 #include "display/intel_dsb.h"
  71 #include "display/intel_frontbuffer.h"
  72 #include "display/intel_gmbus.h"
  73 #include "display/intel_opregion.h"
  74
  75 #include "gem/i915_gem_context_types.h"
  76 #include "gem/i915_gem_shrinker.h"
  77 #include "gem/i915_gem_stolen.h"
  78
  79 #include "gt/intel_lrc.h"
  80 #include "gt/intel_engine.h"
  81 #include "gt/intel_gt_types.h"
  82 #include "gt/intel_workarounds.h"
  83 #include "gt/uc/intel_uc.h"
  84
  85 #include "intel_device_info.h"
  86 #include "intel_pch.h"
  87 #include "intel_runtime_pm.h"
  88 #include "intel_memory_region.h"
  89 #include "intel_uncore.h"
  90 #include "intel_wakeref.h"
  91 #include "intel_wopcm.h"
  92
  93 #include "i915_gem.h"
  94 #include "i915_gem_fence_reg.h"
  95 #include "i915_gem_gtt.h"
  96 #include "i915_gpu_error.h"
  97 #include "i915_perf_types.h"
  98 #include "i915_request.h"
  99 #include "i915_scheduler.h"
 100 #include "gt/intel_timeline.h"
 101 #include "i915_vma.h"
 102 #include "i915_irq.h"
 103
 104 #include "intel_gvt.h"
 105
 106 /* General customization:
 107  */
 108
 109 #define DRIVER_NAME             "i915"
 110 #define DRIVER_DESC             "Intel Graphics"
 111 #define DRIVER_DATE             "20191007"
 112 #define DRIVER_TIMESTAMP        1570451087
 113
 114 struct drm_i915_gem_object;
 115
 116 enum hpd_pin {
 117         HPD_NONE = 0,
 118         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 119         HPD_CRT,
 120         HPD_SDVO_B,
 121         HPD_SDVO_C,
 122         HPD_PORT_A,
 123         HPD_PORT_B,
 124         HPD_PORT_C,
 125         HPD_PORT_D,
 126         HPD_PORT_E,
 127         HPD_PORT_F,
 128         HPD_PORT_G,
 129         HPD_PORT_H,
 130         HPD_PORT_I,
 131
 132         HPD_NUM_PINS
 133 };
 134
 135 #define for_each_hpd_pin(__pin) \
 136         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 137
 138 /* Threshold == 5 for long IRQs, 50 for short */
 139 #define HPD_STORM_DEFAULT_THRESHOLD 50
 140
 141 struct i915_hotplug {
 142         struct delayed_work hotplug_work;
 143
 144         struct {
 145                 unsigned long last_jiffies;
 146                 int count;
 147                 enum {
 148                         HPD_ENABLED = 0,
 149                         HPD_DISABLED = 1,
 150                         HPD_MARK_DISABLED = 2
 151                 } state;
 152         } stats[HPD_NUM_PINS];
 153         u32 event_bits;
 154         u32 retry_bits;
 155         struct delayed_work reenable_work;
 156
 157         u32 long_port_mask;
 158         u32 short_port_mask;
 159         struct work_struct dig_port_work;
 160
 161         struct work_struct poll_init_work;
 162         bool poll_enabled;
 163
 164         unsigned int hpd_storm_threshold;
 165         /* Whether or not to count short HPD IRQs in HPD storms */
 166         u8 hpd_short_storm_enabled;
 167
 168         /*
 169          * if we get a HPD irq from DP and a HPD irq from non-DP
 170          * the non-DP HPD could block the workqueue on a mode config
 171          * mutex getting, that userspace may have taken. However
 172          * userspace is waiting on the DP workqueue to run which is
 173          * blocked behind the non-DP one.
 174          */
 175         struct workqueue_struct *dp_wq;
 176 };
 177
 178 #define I915_GEM_GPU_DOMAINS \
 179         (I915_GEM_DOMAIN_RENDER | \
 180          I915_GEM_DOMAIN_SAMPLER | \
 181          I915_GEM_DOMAIN_COMMAND | \
 182          I915_GEM_DOMAIN_INSTRUCTION | \
 183          I915_GEM_DOMAIN_VERTEX)
 184
 185 struct drm_i915_private;
 186 struct i915_mm_struct;
 187 struct i915_mmu_object;
 188
 189 struct drm_i915_file_private {
 190         struct drm_i915_private *dev_priv;
 191
 192         union {
 193                 struct drm_file *file;
 194                 struct rcu_head rcu;
 195         };
 196
 197         struct {
 198                 spinlock_t lock;
 199                 struct list_head request_list;
 200         } mm;
 201
 202         struct idr context_idr;
 203         struct mutex context_idr_lock; /* guards context_idr */
 204
 205         struct idr vm_idr;
 206         struct mutex vm_idr_lock; /* guards vm_idr */
 207
 208         unsigned int bsd_engine;
 209
 210 /*
 211  * Every context ban increments per client ban score. Also
 212  * hangs in short succession increments ban score. If ban threshold
 213  * is reached, client is considered banned and submitting more work
 214  * will fail. This is a stop gap measure to limit the badly behaving
 215  * clients access to gpu. Note that unbannable contexts never increment
 216  * the client ban score.
 217  */
 218 #define I915_CLIENT_SCORE_HANG_FAST     1
 219 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 220 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 221 #define I915_CLIENT_SCORE_BANNED        9
 222         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 223         atomic_t ban_score;
 224         unsigned long hang_timestamp;
 225 };
 226
 227 /* Interface history:
 228  *
 229  * 1.1: Original.
 230  * 1.2: Add Power Management
 231  * 1.3: Add vblank support
 232  * 1.4: Fix cmdbuffer path, add heap destroy
 233  * 1.5: Add vblank pipe configuration
 234  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 235  *      - Support vertical blank on secondary display pipe
 236  */
 237 #define DRIVER_MAJOR            1
 238 #define DRIVER_MINOR            6
 239 #define DRIVER_PATCHLEVEL       0
 240
 241 struct intel_overlay;
 242 struct intel_overlay_error_state;
 243
 244 struct sdvo_device_mapping {
 245         u8 initialized;
 246         u8 dvo_port;
 247         u8 slave_addr;
 248         u8 dvo_wiring;
 249         u8 i2c_pin;
 250         u8 ddc_pin;
 251 };
 252
 253 struct intel_connector;
 254 struct intel_encoder;
 255 struct intel_atomic_state;
 256 struct intel_crtc_state;
 257 struct intel_initial_plane_config;
 258 struct intel_crtc;
 259 struct intel_limit;
 260 struct dpll;
 261 struct intel_cdclk_state;
 262
 263 struct drm_i915_display_funcs {
 264         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 265                           struct intel_cdclk_state *cdclk_state);
 266         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 267                           const struct intel_cdclk_state *cdclk_state,
 268                           enum pipe pipe);
 269         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 270                              enum i9xx_plane_id i9xx_plane);
 271         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 272         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 273         void (*initial_watermarks)(struct intel_atomic_state *state,
 274                                    struct intel_crtc_state *crtc_state);
 275         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 276                                          struct intel_crtc_state *crtc_state);
 277         void (*optimize_watermarks)(struct intel_atomic_state *state,
 278                                     struct intel_crtc_state *crtc_state);
 279         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 280         void (*update_wm)(struct intel_crtc *crtc);
 281         int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
 282         u8 (*calc_voltage_level)(int cdclk);
 283         /* Returns the active state of the crtc, and if the crtc is active,
 284          * fills out the pipe-config with the hw state. */
 285         bool (*get_pipe_config)(struct intel_crtc *,
 286                                 struct intel_crtc_state *);
 287         void (*get_initial_plane_config)(struct intel_crtc *,
 288                                          struct intel_initial_plane_config *);
 289         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 290                                   struct intel_crtc_state *crtc_state);
 291         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
 292                             struct intel_atomic_state *old_state);
 293         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 294                              struct intel_atomic_state *old_state);
 295         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 296         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 297         void (*audio_codec_enable)(struct intel_encoder *encoder,
 298                                    const struct intel_crtc_state *crtc_state,
 299                                    const struct drm_connector_state *conn_state);
 300         void (*audio_codec_disable)(struct intel_encoder *encoder,
 301                                     const struct intel_crtc_state *old_crtc_state,
 302                                     const struct drm_connector_state *old_conn_state);
 303         void (*fdi_link_train)(struct intel_crtc *crtc,
 304                                const struct intel_crtc_state *crtc_state);
 305         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 306         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 307         /* clock updates for mode set */
 308         /* cursor updates */
 309         /* render clock increase/decrease */
 310         /* display clock increase/decrease */
 311         /* pll clock increase/decrease */
 312
 313         int (*color_check)(struct intel_crtc_state *crtc_state);
 314         /*
 315          * Program double buffered color management registers during
 316          * vblank evasion. The registers should then latch during the
 317          * next vblank start, alongside any other double buffered registers
 318          * involved with the same commit.
 319          */
 320         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 321         /*
 322          * Load LUTs (and other single buffered color management
 323          * registers). Will (hopefully) be called during the vblank
 324          * following the latching of any double buffered registers
 325          * involved with the same commit.
 326          */
 327         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 328         void (*read_luts)(struct intel_crtc_state *crtc_state);
 329 };
 330
 331 struct intel_csr {
 332         struct work_struct work;
 333         const char *fw_path;
 334         u32 required_version;
 335         u32 max_fw_size; /* bytes */
 336         u32 *dmc_payload;
 337         u32 dmc_fw_size; /* dwords */
 338         u32 version;
 339         u32 mmio_count;
 340         i915_reg_t mmioaddr[20];
 341         u32 mmiodata[20];
 342         u32 dc_state;
 343         u32 target_dc_state;
 344         u32 allowed_dc_mask;
 345         intel_wakeref_t wakeref;
 346 };
 347
 348 enum i915_cache_level {
 349         I915_CACHE_NONE = 0,
 350         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 351         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 352                               caches, eg sampler/render caches, and the
 353                               large Last-Level-Cache. LLC is coherent with
 354                               the CPU, but L3 is only visible to the GPU. */
 355         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 356 };
 357
 358 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 359
 360 struct intel_fbc {
 361         /* This is always the inner lock when overlapping with struct_mutex and
 362          * it's the outer lock when overlapping with stolen_lock. */
 363         struct mutex lock;
 364         unsigned threshold;
 365         unsigned int possible_framebuffer_bits;
 366         unsigned int busy_bits;
 367         unsigned int visible_pipes_mask;
 368         struct intel_crtc *crtc;
 369
 370         struct drm_mm_node compressed_fb;
 371         struct drm_mm_node *compressed_llb;
 372
 373         bool false_color;
 374
 375         bool enabled;
 376         bool active;
 377         bool flip_pending;
 378
 379         bool underrun_detected;
 380         struct work_struct underrun_work;
 381
 382         /*
 383          * Due to the atomic rules we can't access some structures without the
 384          * appropriate locking, so we cache information here in order to avoid
 385          * these problems.
 386          */
 387         struct intel_fbc_state_cache {
 388                 struct i915_vma *vma;
 389                 unsigned long flags;
 390
 391                 struct {
 392                         unsigned int mode_flags;
 393                         u32 hsw_bdw_pixel_rate;
 394                 } crtc;
 395
 396                 struct {
 397                         unsigned int rotation;
 398                         int src_w;
 399                         int src_h;
 400                         bool visible;
 401                         /*
 402                          * Display surface base address adjustement for
 403                          * pageflips. Note that on gen4+ this only adjusts up
 404                          * to a tile, offsets within a tile are handled in
 405                          * the hw itself (with the TILEOFF register).
 406                          */
 407                         int adjusted_x;
 408                         int adjusted_y;
 409
 410                         int y;
 411
 412                         u16 pixel_blend_mode;
 413                 } plane;
 414
 415                 struct {
 416                         const struct drm_format_info *format;
 417                         unsigned int stride;
 418                 } fb;
 419         } state_cache;
 420
 421         /*
 422          * This structure contains everything that's relevant to program the
 423          * hardware registers. When we want to figure out if we need to disable
 424          * and re-enable FBC for a new configuration we just check if there's
 425          * something different in the struct. The genx_fbc_activate functions
 426          * are supposed to read from it in order to program the registers.
 427          */
 428         struct intel_fbc_reg_params {
 429                 struct i915_vma *vma;
 430                 unsigned long flags;
 431
 432                 struct {
 433                         enum pipe pipe;
 434                         enum i9xx_plane_id i9xx_plane;
 435                         unsigned int fence_y_offset;
 436                 } crtc;
 437
 438                 struct {
 439                         const struct drm_format_info *format;
 440                         unsigned int stride;
 441                 } fb;
 442
 443                 int cfb_size;
 444                 unsigned int gen9_wa_cfb_stride;
 445         } params;
 446
 447         const char *no_fbc_reason;
 448 };
 449
 450 /*
 451  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 452  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 453  * parsing for same resolution.
 454  */
 455 enum drrs_refresh_rate_type {
 456         DRRS_HIGH_RR,
 457         DRRS_LOW_RR,
 458         DRRS_MAX_RR, /* RR count */
 459 };
 460
 461 enum drrs_support_type {
 462         DRRS_NOT_SUPPORTED = 0,
 463         STATIC_DRRS_SUPPORT = 1,
 464         SEAMLESS_DRRS_SUPPORT = 2
 465 };
 466
 467 struct intel_dp;
 468 struct i915_drrs {
 469         struct mutex mutex;
 470         struct delayed_work work;
 471         struct intel_dp *dp;
 472         unsigned busy_frontbuffer_bits;
 473         enum drrs_refresh_rate_type refresh_rate_type;
 474         enum drrs_support_type type;
 475 };
 476
 477 struct i915_psr {
 478         struct mutex lock;
 479
 480 #define I915_PSR_DEBUG_MODE_MASK        0x0f
 481 #define I915_PSR_DEBUG_DEFAULT          0x00
 482 #define I915_PSR_DEBUG_DISABLE          0x01
 483 #define I915_PSR_DEBUG_ENABLE           0x02
 484 #define I915_PSR_DEBUG_FORCE_PSR1       0x03
 485 #define I915_PSR_DEBUG_IRQ              0x10
 486
 487         u32 debug;
 488         bool sink_support;
 489         bool enabled;
 490         struct intel_dp *dp;
 491         enum pipe pipe;
 492         enum transcoder transcoder;
 493         bool active;
 494         struct work_struct work;
 495         unsigned busy_frontbuffer_bits;
 496         bool sink_psr2_support;
 497         bool link_standby;
 498         bool colorimetry_support;
 499         bool psr2_enabled;
 500         u8 sink_sync_latency;
 501         ktime_t last_entry_attempt;
 502         ktime_t last_exit;
 503         bool sink_not_reliable;
 504         bool irq_aux_error;
 505         u16 su_x_granularity;
 506         bool dc3co_enabled;
 507         u32 dc3co_exit_delay;
 508         struct delayed_work idle_work;
 509 };
 510
 511 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 512 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 513 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 514 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 515 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 516 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 517
 518 struct intel_fbdev;
 519 struct intel_fbc_work;
 520
 521 struct intel_gmbus {
 522         struct i2c_adapter adapter;
 523 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 524         u32 force_bit;
 525         u32 reg0;
 526         i915_reg_t gpio_reg;
 527         struct i2c_algo_bit_data bit_algo;
 528         struct drm_i915_private *dev_priv;
 529 };
 530
 531 struct i915_suspend_saved_registers {
 532         u32 saveDSPARB;
 533         u32 saveFBC_CONTROL;
 534         u32 saveCACHE_MODE_0;
 535         u32 saveMI_ARB_STATE;
 536         u32 saveSWF0[16];
 537         u32 saveSWF1[16];
 538         u32 saveSWF3[3];
 539         u64 saveFENCE[I915_MAX_NUM_FENCES];
 540         u32 savePCH_PORT_HOTPLUG;
 541         u16 saveGCDGMBUS;
 542 };
 543
 544 struct vlv_s0ix_state;
 545
 546 struct intel_rps_ei {
 547         ktime_t ktime;
 548         u32 render_c0;
 549         u32 media_c0;
 550 };
 551
 552 struct intel_rps {
 553         struct mutex lock; /* protects enabling and the worker */
 554
 555         /*
 556          * work, interrupts_enabled and pm_iir are protected by
 557          * dev_priv->irq_lock
 558          */
 559         struct work_struct work;
 560         bool interrupts_enabled;
 561         u32 pm_iir;
 562
 563         /* PM interrupt bits that should never be masked */
 564         u32 pm_intrmsk_mbz;
 565
 566         /* Frequencies are stored in potentially platform dependent multiples.
 567          * In other words, *_freq needs to be multiplied by X to be interesting.
 568          * Soft limits are those which are used for the dynamic reclocking done
 569          * by the driver (raise frequencies under heavy loads, and lower for
 570          * lighter loads). Hard limits are those imposed by the hardware.
 571          *
 572          * A distinction is made for overclocking, which is never enabled by
 573          * default, and is considered to be above the hard limit if it's
 574          * possible at all.
 575          */
 576         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
 577         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
 578         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
 579         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
 580         u8 min_freq;            /* AKA RPn. Minimum frequency */
 581         u8 boost_freq;          /* Frequency to request when wait boosting */
 582         u8 idle_freq;           /* Frequency to request when we are idle */
 583         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
 584         u8 rp1_freq;            /* "less than" RP0 power/freqency */
 585         u8 rp0_freq;            /* Non-overclocked max frequency. */
 586         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
 587
 588         int last_adj;
 589
 590         struct {
 591                 struct mutex mutex;
 592
 593                 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
 594                 unsigned int interactive;
 595
 596                 u8 up_threshold; /* Current %busy required to uplock */
 597                 u8 down_threshold; /* Current %busy required to downclock */
 598         } power;
 599
 600         bool enabled;
 601         atomic_t num_waiters;
 602         atomic_t boosts;
 603
 604         /* manual wa residency calculations */
 605         struct intel_rps_ei ei;
 606 };
 607
 608 struct intel_llc_pstate {
 609         bool enabled;
 610 };
 611
 612 struct intel_gen6_power_mgmt {
 613         struct intel_rps rps;
 614         struct intel_llc_pstate llc_pstate;
 615 };
 616
 617 /* defined intel_pm.c */
 618 extern spinlock_t mchdev_lock;
 619
 620 struct intel_ilk_power_mgmt {
 621         u8 cur_delay;
 622         u8 min_delay;
 623         u8 max_delay;
 624         u8 fmax;
 625         u8 fstart;
 626
 627         u64 last_count1;
 628         unsigned long last_time1;
 629         unsigned long chipset_power;
 630         u64 last_count2;
 631         u64 last_time2;
 632         unsigned long gfx_power;
 633         u8 corr;
 634
 635         int c_m;
 636         int r_t;
 637 };
 638
 639 #define MAX_L3_SLICES 2
 640 struct intel_l3_parity {
 641         u32 *remap_info[MAX_L3_SLICES];
 642         struct work_struct error_work;
 643         int which_slice;
 644 };
 645
 646 struct i915_gem_mm {
 647         /** Memory allocator for GTT stolen memory */
 648         struct drm_mm stolen;
 649         /** Protects the usage of the GTT stolen memory allocator. This is
 650          * always the inner lock when overlapping with struct_mutex. */
 651         struct mutex stolen_lock;
 652
 653         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 654         spinlock_t obj_lock;
 655
 656         /**
 657          * List of objects which are purgeable.
 658          */
 659         struct list_head purge_list;
 660
 661         /**
 662          * List of objects which have allocated pages and are shrinkable.
 663          */
 664         struct list_head shrink_list;
 665
 666         /**
 667          * List of objects which are pending destruction.
 668          */
 669         struct llist_head free_list;
 670         struct work_struct free_work;
 671         /**
 672          * Count of objects pending destructions. Used to skip needlessly
 673          * waiting on an RCU barrier if no objects are waiting to be freed.
 674          */
 675         atomic_t free_count;
 676
 677         /**
 678          * Small stash of WC pages
 679          */
 680         struct pagestash wc_stash;
 681
 682         /**
 683          * tmpfs instance used for shmem backed objects
 684          */
 685         struct vfsmount *gemfs;
 686
 687         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 688
 689         struct notifier_block oom_notifier;
 690         struct notifier_block vmap_notifier;
 691         struct shrinker shrinker;
 692
 693         /**
 694          * Workqueue to fault in userptr pages, flushed by the execbuf
 695          * when required but otherwise left to userspace to try again
 696          * on EAGAIN.
 697          */
 698         struct workqueue_struct *userptr_wq;
 699
 700         /* shrinker accounting, also useful for userland debugging */
 701         u64 shrink_memory;
 702         u32 shrink_count;
 703 };
 704
 705 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 706
 707 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
 708 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
 709
 710 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
 711 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
 712
 713 #define I915_ENGINE_WEDGED_TIMEOUT  (60 * HZ)  /* Reset but no recovery? */
 714
 715 struct ddi_vbt_port_info {
 716         /* Non-NULL if port present. */
 717         const struct child_device_config *child;
 718
 719         int max_tmds_clock;
 720
 721         /*
 722          * This is an index in the HDMI/DVI DDI buffer translation table.
 723          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
 724          * populate this field.
 725          */
 726 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
 727         u8 hdmi_level_shift;
 728
 729         u8 supports_dvi:1;
 730         u8 supports_hdmi:1;
 731         u8 supports_dp:1;
 732         u8 supports_edp:1;
 733         u8 supports_typec_usb:1;
 734         u8 supports_tbt:1;
 735
 736         u8 alternate_aux_channel;
 737         u8 alternate_ddc_pin;
 738
 739         u8 dp_boost_level;
 740         u8 hdmi_boost_level;
 741         int dp_max_link_rate;           /* 0 for not limited by VBT */
 742 };
 743
 744 enum psr_lines_to_wait {
 745         PSR_0_LINES_TO_WAIT = 0,
 746         PSR_1_LINE_TO_WAIT,
 747         PSR_4_LINES_TO_WAIT,
 748         PSR_8_LINES_TO_WAIT
 749 };
 750
 751 struct intel_vbt_data {
 752         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 753         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 754
 755         /* Feature bits */
 756         unsigned int int_tv_support:1;
 757         unsigned int lvds_dither:1;
 758         unsigned int int_crt_support:1;
 759         unsigned int lvds_use_ssc:1;
 760         unsigned int int_lvds_support:1;
 761         unsigned int display_clock_mode:1;
 762         unsigned int fdi_rx_polarity_inverted:1;
 763         unsigned int panel_type:4;
 764         int lvds_ssc_freq;
 765         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 766         enum drm_panel_orientation orientation;
 767
 768         enum drrs_support_type drrs_type;
 769
 770         struct {
 771                 int rate;
 772                 int lanes;
 773                 int preemphasis;
 774                 int vswing;
 775                 bool low_vswing;
 776                 bool initialized;
 777                 int bpp;
 778                 struct edp_power_seq pps;
 779         } edp;
 780
 781         struct {
 782                 bool enable;
 783                 bool full_link;
 784                 bool require_aux_wakeup;
 785                 int idle_frames;
 786                 enum psr_lines_to_wait lines_to_wait;
 787                 int tp1_wakeup_time_us;
 788                 int tp2_tp3_wakeup_time_us;
 789                 int psr2_tp2_tp3_wakeup_time_us;
 790         } psr;
 791
 792         struct {
 793                 u16 pwm_freq_hz;
 794                 bool present;
 795                 bool active_low_pwm;
 796                 u8 min_brightness;      /* min_brightness/255 of max */
 797                 u8 controller;          /* brightness controller number */
 798                 enum intel_backlight_type type;
 799         } backlight;
 800
 801         /* MIPI DSI */
 802         struct {
 803                 u16 panel_id;
 804                 struct mipi_config *config;
 805                 struct mipi_pps_data *pps;
 806                 u16 bl_ports;
 807                 u16 cabc_ports;
 808                 u8 seq_version;
 809                 u32 size;
 810                 u8 *data;
 811                 const u8 *sequence[MIPI_SEQ_MAX];
 812                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 813                 enum drm_panel_orientation orientation;
 814         } dsi;
 815
 816         int crt_ddc_pin;
 817
 818         int child_dev_num;
 819         struct child_device_config *child_dev;
 820
 821         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 822         struct sdvo_device_mapping sdvo_mappings[2];
 823 };
 824
 825 enum intel_ddb_partitioning {
 826         INTEL_DDB_PART_1_2,
 827         INTEL_DDB_PART_5_6, /* IVB+ */
 828 };
 829
 830 struct intel_wm_level {
 831         bool enable;
 832         u32 pri_val;
 833         u32 spr_val;
 834         u32 cur_val;
 835         u32 fbc_val;
 836 };
 837
 838 struct ilk_wm_values {
 839         u32 wm_pipe[3];
 840         u32 wm_lp[3];
 841         u32 wm_lp_spr[3];
 842         u32 wm_linetime[3];
 843         bool enable_fbc_wm;
 844         enum intel_ddb_partitioning partitioning;
 845 };
 846
 847 struct g4x_pipe_wm {
 848         u16 plane[I915_MAX_PLANES];
 849         u16 fbc;
 850 };
 851
 852 struct g4x_sr_wm {
 853         u16 plane;
 854         u16 cursor;
 855         u16 fbc;
 856 };
 857
 858 struct vlv_wm_ddl_values {
 859         u8 plane[I915_MAX_PLANES];
 860 };
 861
 862 struct vlv_wm_values {
 863         struct g4x_pipe_wm pipe[3];
 864         struct g4x_sr_wm sr;
 865         struct vlv_wm_ddl_values ddl[3];
 866         u8 level;
 867         bool cxsr;
 868 };
 869
 870 struct g4x_wm_values {
 871         struct g4x_pipe_wm pipe[2];
 872         struct g4x_sr_wm sr;
 873         struct g4x_sr_wm hpll;
 874         bool cxsr;
 875         bool hpll_en;
 876         bool fbc_en;
 877 };
 878
 879 struct skl_ddb_entry {
 880         u16 start, end; /* in number of blocks, 'end' is exclusive */
 881 };
 882
 883 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 884 {
 885         return entry->end - entry->start;
 886 }
 887
 888 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 889                                        const struct skl_ddb_entry *e2)
 890 {
 891         if (e1->start == e2->start && e1->end == e2->end)
 892                 return true;
 893
 894         return false;
 895 }
 896
 897 struct skl_ddb_allocation {
 898         u8 enabled_slices; /* GEN11 has configurable 2 slices */
 899 };
 900
 901 struct skl_ddb_values {
 902         unsigned dirty_pipes;
 903         struct skl_ddb_allocation ddb;
 904 };
 905
 906 struct skl_wm_level {
 907         u16 min_ddb_alloc;
 908         u16 plane_res_b;
 909         u8 plane_res_l;
 910         bool plane_en;
 911         bool ignore_lines;
 912 };
 913
 914 /* Stores plane specific WM parameters */
 915 struct skl_wm_params {
 916         bool x_tiled, y_tiled;
 917         bool rc_surface;
 918         bool is_planar;
 919         u32 width;
 920         u8 cpp;
 921         u32 plane_pixel_rate;
 922         u32 y_min_scanlines;
 923         u32 plane_bytes_per_line;
 924         uint_fixed_16_16_t plane_blocks_per_line;
 925         uint_fixed_16_16_t y_tile_minimum;
 926         u32 linetime_us;
 927         u32 dbuf_block_size;
 928 };
 929
 930 enum intel_pipe_crc_source {
 931         INTEL_PIPE_CRC_SOURCE_NONE,
 932         INTEL_PIPE_CRC_SOURCE_PLANE1,
 933         INTEL_PIPE_CRC_SOURCE_PLANE2,
 934         INTEL_PIPE_CRC_SOURCE_PLANE3,
 935         INTEL_PIPE_CRC_SOURCE_PLANE4,
 936         INTEL_PIPE_CRC_SOURCE_PLANE5,
 937         INTEL_PIPE_CRC_SOURCE_PLANE6,
 938         INTEL_PIPE_CRC_SOURCE_PLANE7,
 939         INTEL_PIPE_CRC_SOURCE_PIPE,
 940         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
 941         INTEL_PIPE_CRC_SOURCE_TV,
 942         INTEL_PIPE_CRC_SOURCE_DP_B,
 943         INTEL_PIPE_CRC_SOURCE_DP_C,
 944         INTEL_PIPE_CRC_SOURCE_DP_D,
 945         INTEL_PIPE_CRC_SOURCE_AUTO,
 946         INTEL_PIPE_CRC_SOURCE_MAX,
 947 };
 948
 949 #define INTEL_PIPE_CRC_ENTRIES_NR       128
 950 struct intel_pipe_crc {
 951         spinlock_t lock;
 952         int skipped;
 953         enum intel_pipe_crc_source source;
 954 };
 955
 956 struct i915_frontbuffer_tracking {
 957         spinlock_t lock;
 958
 959         /*
 960          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 961          * scheduled flips.
 962          */
 963         unsigned busy_bits;
 964         unsigned flip_bits;
 965 };
 966
 967 struct i915_virtual_gpu {
 968         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 969         bool active;
 970         u32 caps;
 971 };
 972
 973 /* used in computing the new watermarks state */
 974 struct intel_wm_config {
 975         unsigned int num_pipes_active;
 976         bool sprites_enabled;
 977         bool sprites_scaled;
 978 };
 979
 980 struct intel_cdclk_state {
 981         unsigned int cdclk, vco, ref, bypass;
 982         u8 voltage_level;
 983 };
 984
 985 struct drm_i915_private {
 986         struct drm_device drm;
 987
 988         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 989         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 990         struct intel_driver_caps caps;
 991
 992         /**
 993          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 994          * end of stolen which we can optionally use to create GEM objects
 995          * backed by stolen memory. Note that stolen_usable_size tells us
 996          * exactly how much of this we are actually allowed to use, given that
 997          * some portion of it is in fact reserved for use by hardware functions.
 998          */
 999         struct resource dsm;
1000         /**
1001          * Reseved portion of Data Stolen Memory
1002          */
1003         struct resource dsm_reserved;
1004
1005         /*
1006          * Stolen memory is segmented in hardware with different portions
1007          * offlimits to certain functions.
1008          *
1009          * The drm_mm is initialised to the total accessible range, as found
1010          * from the PCI config. On Broadwell+, this is further restricted to
1011          * avoid the first page! The upper end of stolen memory is reserved for
1012          * hardware functions and similarly removed from the accessible range.
1013          */
1014         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
1015
1016         struct intel_uncore uncore;
1017         struct intel_uncore_mmio_debug mmio_debug;
1018
1019         struct i915_virtual_gpu vgpu;
1020
1021         struct intel_gvt *gvt;
1022
1023         struct intel_wopcm wopcm;
1024
1025         struct intel_csr csr;
1026
1027         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1028
1029         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1030          * controller on different i2c buses. */
1031         struct mutex gmbus_mutex;
1032
1033         /**
1034          * Base address of where the gmbus and gpio blocks are located (either
1035          * on PCH or on SoC for platforms without PCH).
1036          */
1037         u32 gpio_mmio_base;
1038
1039         u32 hsw_psr_mmio_adjust;
1040
1041         /* MMIO base address for MIPI regs */
1042         u32 mipi_mmio_base;
1043
1044         u32 pps_mmio_base;
1045
1046         wait_queue_head_t gmbus_wait_queue;
1047
1048         struct pci_dev *bridge_dev;
1049
1050         /* Context used internally to idle the GPU and setup initial state */
1051         struct i915_gem_context *kernel_context;
1052
1053         struct intel_engine_cs *engine[I915_NUM_ENGINES];
1054         struct rb_root uabi_engines;
1055
1056         struct resource mch_res;
1057
1058         /* protects the irq masks */
1059         spinlock_t irq_lock;
1060
1061         bool display_irqs_enabled;
1062
1063         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1064         struct pm_qos_request pm_qos;
1065
1066         /* Sideband mailbox protection */
1067         struct mutex sb_lock;
1068         struct pm_qos_request sb_qos;
1069
1070         /** Cached value of IMR to avoid reads in updating the bitfield */
1071         union {
1072                 u32 irq_mask;
1073                 u32 de_irq_mask[I915_MAX_PIPES];
1074         };
1075         u32 pm_rps_events;
1076         u32 pipestat_irq_mask[I915_MAX_PIPES];
1077
1078         struct i915_hotplug hotplug;
1079         struct intel_fbc fbc;
1080         struct i915_drrs drrs;
1081         struct intel_opregion opregion;
1082         struct intel_vbt_data vbt;
1083
1084         bool preserve_bios_swizzle;
1085
1086         /* overlay */
1087         struct intel_overlay *overlay;
1088
1089         /* backlight registers and fields in struct intel_panel */
1090         struct mutex backlight_lock;
1091
1092         /* protects panel power sequencer state */
1093         struct mutex pps_mutex;
1094
1095         unsigned int fsb_freq, mem_freq, is_ddr3;
1096         unsigned int skl_preferred_vco_freq;
1097         unsigned int max_cdclk_freq;
1098
1099         unsigned int max_dotclk_freq;
1100         unsigned int rawclk_freq;
1101         unsigned int hpll_freq;
1102         unsigned int fdi_pll_freq;
1103         unsigned int czclk_freq;
1104
1105         struct {
1106                 /*
1107                  * The current logical cdclk state.
1108                  * See intel_atomic_state.cdclk.logical
1109                  *
1110                  * For reading holding any crtc lock is sufficient,
1111                  * for writing must hold all of them.
1112                  */
1113                 struct intel_cdclk_state logical;
1114                 /*
1115                  * The current actual cdclk state.
1116                  * See intel_atomic_state.cdclk.actual
1117                  */
1118                 struct intel_cdclk_state actual;
1119                 /* The current hardware cdclk state */
1120                 struct intel_cdclk_state hw;
1121
1122                 /* cdclk, divider, and ratio table from bspec */
1123                 const struct intel_cdclk_vals *table;
1124
1125                 int force_min_cdclk;
1126         } cdclk;
1127
1128         /**
1129          * wq - Driver workqueue for GEM.
1130          *
1131          * NOTE: Work items scheduled here are not allowed to grab any modeset
1132          * locks, for otherwise the flushing done in the pageflip code will
1133          * result in deadlocks.
1134          */
1135         struct workqueue_struct *wq;
1136
1137         /* ordered wq for modesets */
1138         struct workqueue_struct *modeset_wq;
1139         /* unbound hipri wq for page flips/plane updates */
1140         struct workqueue_struct *flip_wq;
1141
1142         /* Display functions */
1143         struct drm_i915_display_funcs display;
1144
1145         /* PCH chipset type */
1146         enum intel_pch pch_type;
1147         unsigned short pch_id;
1148
1149         unsigned long quirks;
1150
1151         struct drm_atomic_state *modeset_restore_state;
1152         struct drm_modeset_acquire_ctx reset_ctx;
1153
1154         struct i915_ggtt ggtt; /* VM representing the global address space */
1155
1156         struct i915_gem_mm mm;
1157         DECLARE_HASHTABLE(mm_structs, 7);
1158         struct mutex mm_lock;
1159
1160         /* Kernel Modesetting */
1161
1162         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1163         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1164
1165 #ifdef CONFIG_DEBUG_FS
1166         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1167 #endif
1168
1169         /* dpll and cdclk state is protected by connection_mutex */
1170         int num_shared_dpll;
1171         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1172         const struct intel_dpll_mgr *dpll_mgr;
1173
1174         /*
1175          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1176          * Must be global rather than per dpll, because on some platforms
1177          * plls share registers.
1178          */
1179         struct mutex dpll_lock;
1180
1181         u8 active_pipes;
1182         /* minimum acceptable cdclk for each pipe */
1183         int min_cdclk[I915_MAX_PIPES];
1184         /* minimum acceptable voltage level for each pipe */
1185         u8 min_voltage_level[I915_MAX_PIPES];
1186
1187         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1188
1189         struct i915_wa_list gt_wa_list;
1190
1191         struct i915_frontbuffer_tracking fb_tracking;
1192
1193         struct intel_atomic_helper {
1194                 struct llist_head free_list;
1195                 struct work_struct free_work;
1196         } atomic_helper;
1197
1198         u16 orig_clock;
1199
1200         bool mchbar_need_disable;
1201
1202         struct intel_l3_parity l3_parity;
1203
1204         /*
1205          * edram size in MB.
1206          * Cannot be determined by PCIID. You must always read a register.
1207          */
1208         u32 edram_size_mb;
1209
1210         /* gen6+ GT PM state */
1211         struct intel_gen6_power_mgmt gt_pm;
1212
1213         /* ilk-only ips/rps state. Everything in here is protected by the global
1214          * mchdev_lock in intel_pm.c */
1215         struct intel_ilk_power_mgmt ips;
1216
1217         struct i915_power_domains power_domains;
1218
1219         struct i915_psr psr;
1220
1221         struct i915_gpu_error gpu_error;
1222
1223         struct drm_i915_gem_object *vlv_pctx;
1224
1225         /* list of fbdev register on this device */
1226         struct intel_fbdev *fbdev;
1227         struct work_struct fbdev_suspend_work;
1228
1229         struct drm_property *broadcast_rgb_property;
1230         struct drm_property *force_audio_property;
1231
1232         /* hda/i915 audio component */
1233         struct i915_audio_component *audio_component;
1234         bool audio_component_registered;
1235         /**
1236          * av_mutex - mutex for audio/video sync
1237          *
1238          */
1239         struct mutex av_mutex;
1240         int audio_power_refcount;
1241         u32 audio_freq_cntrl;
1242
1243         u32 fdi_rx_config;
1244
1245         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1246         u32 chv_phy_control;
1247         /*
1248          * Shadows for CHV DPLL_MD regs to keep the state
1249          * checker somewhat working in the presence hardware
1250          * crappiness (can't read out DPLL_MD for pipes B & C).
1251          */
1252         u32 chv_dpll_md[I915_MAX_PIPES];
1253         u32 bxt_phy_grc;
1254
1255         u32 suspend_count;
1256         bool power_domains_suspended;
1257         struct i915_suspend_saved_registers regfile;
1258         struct vlv_s0ix_state *vlv_s0ix_state;
1259
1260         enum {
1261                 I915_SAGV_UNKNOWN = 0,
1262                 I915_SAGV_DISABLED,
1263                 I915_SAGV_ENABLED,
1264                 I915_SAGV_NOT_CONTROLLED
1265         } sagv_status;
1266
1267         u32 sagv_block_time_us;
1268
1269         struct {
1270                 /*
1271                  * Raw watermark latency values:
1272                  * in 0.1us units for WM0,
1273                  * in 0.5us units for WM1+.
1274                  */
1275                 /* primary */
1276                 u16 pri_latency[5];
1277                 /* sprite */
1278                 u16 spr_latency[5];
1279                 /* cursor */
1280                 u16 cur_latency[5];
1281                 /*
1282                  * Raw watermark memory latency values
1283                  * for SKL for all 8 levels
1284                  * in 1us units.
1285                  */
1286                 u16 skl_latency[8];
1287
1288                 /* current hardware state */
1289                 union {
1290                         struct ilk_wm_values hw;
1291                         struct skl_ddb_values skl_hw;
1292                         struct vlv_wm_values vlv;
1293                         struct g4x_wm_values g4x;
1294                 };
1295
1296                 u8 max_level;
1297
1298                 /*
1299                  * Should be held around atomic WM register writing; also
1300                  * protects * intel_crtc->wm.active and
1301                  * crtc_state->wm.need_postvbl_update.
1302                  */
1303                 struct mutex wm_mutex;
1304
1305                 /*
1306                  * Set during HW readout of watermarks/DDB.  Some platforms
1307                  * need to know when we're still using BIOS-provided values
1308                  * (which we don't fully trust).
1309                  */
1310                 bool distrust_bios_wm;
1311         } wm;
1312
1313         struct dram_info {
1314                 bool valid;
1315                 bool is_16gb_dimm;
1316                 u8 num_channels;
1317                 u8 ranks;
1318                 u32 bandwidth_kbps;
1319                 bool symmetric_memory;
1320                 enum intel_dram_type {
1321                         INTEL_DRAM_UNKNOWN,
1322                         INTEL_DRAM_DDR3,
1323                         INTEL_DRAM_DDR4,
1324                         INTEL_DRAM_LPDDR3,
1325                         INTEL_DRAM_LPDDR4
1326                 } type;
1327         } dram_info;
1328
1329         struct intel_bw_info {
1330                 unsigned int deratedbw[3]; /* for each QGV point */
1331                 u8 num_qgv_points;
1332                 u8 num_planes;
1333         } max_bw[6];
1334
1335         struct drm_private_obj bw_obj;
1336
1337         struct intel_runtime_pm runtime_pm;
1338
1339         struct i915_perf perf;
1340
1341         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1342         struct intel_gt gt;
1343
1344         struct {
1345                 struct notifier_block pm_notifier;
1346
1347                 struct i915_gem_contexts {
1348                         spinlock_t lock; /* locks list */
1349                         struct list_head list;
1350
1351                         struct llist_head free_list;
1352                         struct work_struct free_work;
1353                 } contexts;
1354         } gem;
1355
1356         /* For i915gm/i945gm vblank irq workaround */
1357         u8 vblank_enabled;
1358
1359         /* perform PHY state sanity checks? */
1360         bool chv_phy_assert[2];
1361
1362         bool ipc_enabled;
1363
1364         /* Used to save the pipe-to-encoder mapping for audio */
1365         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1366
1367         /* necessary resource sharing with HDMI LPE audio driver. */
1368         struct {
1369                 struct platform_device *platdev;
1370                 int     irq;
1371         } lpe_audio;
1372
1373         struct i915_pmu pmu;
1374
1375         struct i915_hdcp_comp_master *hdcp_master;
1376         bool hdcp_comp_added;
1377
1378         /* Mutex to protect the above hdcp component related values. */
1379         struct mutex hdcp_comp_mutex;
1380
1381         /*
1382          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1383          * will be rejected. Instead look for a better place.
1384          */
1385 };
1386
1387 struct dram_dimm_info {
1388         u8 size, width, ranks;
1389 };
1390
1391 struct dram_channel_info {
1392         struct dram_dimm_info dimm_l, dimm_s;
1393         u8 ranks;
1394         bool is_16gb_dimm;
1395 };
1396
1397 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1398 {
1399         return container_of(dev, struct drm_i915_private, drm);
1400 }
1401
1402 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1403 {
1404         return dev_get_drvdata(kdev);
1405 }
1406
1407 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1408 {
1409         return pci_get_drvdata(pdev);
1410 }
1411
1412 /* Simple iterator over all initialised engines */
1413 #define for_each_engine(engine__, dev_priv__, id__) \
1414         for ((id__) = 0; \
1415              (id__) < I915_NUM_ENGINES; \
1416              (id__)++) \
1417                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1418
1419 /* Iterator over subset of engines selected by mask */
1420 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1421         for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1422              (tmp__) ? \
1423              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1424              0;)
1425
1426 #define rb_to_uabi_engine(rb) \
1427         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1428
1429 #define for_each_uabi_engine(engine__, i915__) \
1430         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1431              (engine__); \
1432              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1433
1434 #define I915_GTT_OFFSET_NONE ((u32)-1)
1435
1436 /*
1437  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1438  * considered to be the frontbuffer for the given plane interface-wise. This
1439  * doesn't mean that the hw necessarily already scans it out, but that any
1440  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1441  *
1442  * We have one bit per pipe and per scanout plane type.
1443  */
1444 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1445 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1446         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1447         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1448         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1449 })
1450 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1451         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1452 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1453         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1454                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1455
1456 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1457 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1458 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1459
1460 #define INTEL_GEN(dev_priv)     (INTEL_INFO(dev_priv)->gen)
1461 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1462
1463 #define REVID_FOREVER           0xff
1464 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
1465
1466 #define INTEL_GEN_MASK(s, e) ( \
1467         BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1468         BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1469         GENMASK((e) - 1, (s) - 1))
1470
1471 /* Returns true if Gen is in inclusive range [Start, End] */
1472 #define IS_GEN_RANGE(dev_priv, s, e) \
1473         (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1474
1475 #define IS_GEN(dev_priv, n) \
1476         (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1477          INTEL_INFO(dev_priv)->gen == (n))
1478
1479 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1480
1481 /*
1482  * Return true if revision is in range [since,until] inclusive.
1483  *
1484  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1485  */
1486 #define IS_REVID(p, since, until) \
1487         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1488
1489 static __always_inline unsigned int
1490 __platform_mask_index(const struct intel_runtime_info *info,
1491                       enum intel_platform p)
1492 {
1493         const unsigned int pbits =
1494                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1495
1496         /* Expand the platform_mask array if this fails. */
1497         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1498                      pbits * ARRAY_SIZE(info->platform_mask));
1499
1500         return p / pbits;
1501 }
1502
1503 static __always_inline unsigned int
1504 __platform_mask_bit(const struct intel_runtime_info *info,
1505                     enum intel_platform p)
1506 {
1507         const unsigned int pbits =
1508                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1509
1510         return p % pbits + INTEL_SUBPLATFORM_BITS;
1511 }
1512
1513 static inline u32
1514 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1515 {
1516         const unsigned int pi = __platform_mask_index(info, p);
1517
1518         return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1519 }
1520
1521 static __always_inline bool
1522 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1523 {
1524         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1525         const unsigned int pi = __platform_mask_index(info, p);
1526         const unsigned int pb = __platform_mask_bit(info, p);
1527
1528         BUILD_BUG_ON(!__builtin_constant_p(p));
1529
1530         return info->platform_mask[pi] & BIT(pb);
1531 }
1532
1533 static __always_inline bool
1534 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1535                enum intel_platform p, unsigned int s)
1536 {
1537         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1538         const unsigned int pi = __platform_mask_index(info, p);
1539         const unsigned int pb = __platform_mask_bit(info, p);
1540         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1541         const u32 mask = info->platform_mask[pi];
1542
1543         BUILD_BUG_ON(!__builtin_constant_p(p));
1544         BUILD_BUG_ON(!__builtin_constant_p(s));
1545         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1546
1547         /* Shift and test on the MSB position so sign flag can be used. */
1548         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1549 }
1550
1551 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1552
1553 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1554 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1555 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1556 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1557 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1558 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1559 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1560 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1561 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1562 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1563 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1564 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1565 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1566 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1567 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1568 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1569 #define IS_IRONLAKE_M(dev_priv) \
1570         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1571 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1572 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1573                                  INTEL_INFO(dev_priv)->gt == 1)
1574 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1575 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1576 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1577 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1578 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1579 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1580 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1581 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1582 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1583 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1584 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1585 #define IS_ELKHARTLAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1586 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1587 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1588                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1589 #define IS_BDW_ULT(dev_priv) \
1590         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1591 #define IS_BDW_ULX(dev_priv) \
1592         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1593 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1594                                  INTEL_INFO(dev_priv)->gt == 3)
1595 #define IS_HSW_ULT(dev_priv) \
1596         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1597 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1598                                  INTEL_INFO(dev_priv)->gt == 3)
1599 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1600                                  INTEL_INFO(dev_priv)->gt == 1)
1601 /* ULX machines are also considered ULT. */
1602 #define IS_HSW_ULX(dev_priv) \
1603         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1604 #define IS_SKL_ULT(dev_priv) \
1605         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1606 #define IS_SKL_ULX(dev_priv) \
1607         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1608 #define IS_KBL_ULT(dev_priv) \
1609         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1610 #define IS_KBL_ULX(dev_priv) \
1611         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1612 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1613                                  INTEL_INFO(dev_priv)->gt == 2)
1614 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1615                                  INTEL_INFO(dev_priv)->gt == 3)
1616 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1617                                  INTEL_INFO(dev_priv)->gt == 4)
1618 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1619                                  INTEL_INFO(dev_priv)->gt == 2)
1620 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1621                                  INTEL_INFO(dev_priv)->gt == 3)
1622 #define IS_CFL_ULT(dev_priv) \
1623         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1624 #define IS_CFL_ULX(dev_priv) \
1625         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1626 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1627                                  INTEL_INFO(dev_priv)->gt == 2)
1628 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1629                                  INTEL_INFO(dev_priv)->gt == 3)
1630 #define IS_CNL_WITH_PORT_F(dev_priv) \
1631         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1632 #define IS_ICL_WITH_PORT_F(dev_priv) \
1633         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1634
1635 #define SKL_REVID_A0            0x0
1636 #define SKL_REVID_B0            0x1
1637 #define SKL_REVID_C0            0x2
1638 #define SKL_REVID_D0            0x3
1639 #define SKL_REVID_E0            0x4
1640 #define SKL_REVID_F0            0x5
1641 #define SKL_REVID_G0            0x6
1642 #define SKL_REVID_H0            0x7
1643
1644 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1645
1646 #define BXT_REVID_A0            0x0
1647 #define BXT_REVID_A1            0x1
1648 #define BXT_REVID_B0            0x3
1649 #define BXT_REVID_B_LAST        0x8
1650 #define BXT_REVID_C0            0x9
1651
1652 #define IS_BXT_REVID(dev_priv, since, until) \
1653         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1654
1655 #define KBL_REVID_A0            0x0
1656 #define KBL_REVID_B0            0x1
1657 #define KBL_REVID_C0            0x2
1658 #define KBL_REVID_D0            0x3
1659 #define KBL_REVID_E0            0x4
1660
1661 #define IS_KBL_REVID(dev_priv, since, until) \
1662         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1663
1664 #define GLK_REVID_A0            0x0
1665 #define GLK_REVID_A1            0x1
1666
1667 #define IS_GLK_REVID(dev_priv, since, until) \
1668         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1669
1670 #define CNL_REVID_A0            0x0
1671 #define CNL_REVID_B0            0x1
1672 #define CNL_REVID_C0            0x2
1673
1674 #define IS_CNL_REVID(p, since, until) \
1675         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1676
1677 #define ICL_REVID_A0            0x0
1678 #define ICL_REVID_A2            0x1
1679 #define ICL_REVID_B0            0x3
1680 #define ICL_REVID_B2            0x4
1681 #define ICL_REVID_C0            0x5
1682
1683 #define IS_ICL_REVID(p, since, until) \
1684         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1685
1686 #define TGL_REVID_A0            0x0
1687
1688 #define IS_TGL_REVID(p, since, until) \
1689         (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1690
1691 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1692 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1693 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1694
1695 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1696
1697 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({                \
1698         unsigned int first__ = (first);                                 \
1699         unsigned int count__ = (count);                                 \
1700         (INTEL_INFO(dev_priv)->engine_mask &                            \
1701          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1702 })
1703 #define VDBOX_MASK(dev_priv) \
1704         ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1705 #define VEBOX_MASK(dev_priv) \
1706         ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1707
1708 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1709 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1710 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1711 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
1712                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1713
1714 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1715
1716 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1717                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1718 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1719                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1720 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1721                 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1722
1723 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1724
1725 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1726 #define HAS_PPGTT(dev_priv) \
1727         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1728 #define HAS_FULL_PPGTT(dev_priv) \
1729         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1730
1731 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1732         GEM_BUG_ON((sizes) == 0); \
1733         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1734 })
1735
1736 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1737 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1738                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1739
1740 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1741 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1742
1743 /* WaRsDisableCoarsePowerGating:skl,cnl */
1744 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1745         (IS_CANNONLAKE(dev_priv) || \
1746          IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
1747
1748 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1749 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1750                                         IS_GEMINILAKE(dev_priv) || \
1751                                         IS_KABYLAKE(dev_priv))
1752
1753 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1754  * rows, which changed the alignment requirements and fence programming.
1755  */
1756 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1757                                          !(IS_I915G(dev_priv) || \
1758                                          IS_I915GM(dev_priv)))
1759 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1760 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1761
1762 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1763 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1764 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1765
1766 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1767
1768 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1769
1770 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1771 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1772 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1773 #define HAS_TRANSCODER_EDP(dev_priv)     (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
1774
1775 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1776 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1777 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1778
1779 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1780
1781 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
1782
1783 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1784 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1785
1786 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1787
1788 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1789
1790 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1791
1792 /* Having GuC is not the same as using GuC */
1793 #define USES_GUC(dev_priv)              intel_uc_uses_guc(&(dev_priv)->gt.uc)
1794 #define USES_GUC_SUBMISSION(dev_priv)   intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
1795
1796 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1797
1798 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1799
1800
1801 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1802
1803 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1804
1805 /* DPF == dynamic parity feature */
1806 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1807 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1808                                  2 : HAS_L3_DPF(dev_priv))
1809
1810 #define GT_FREQUENCY_MULTIPLIER 50
1811 #define GEN9_FREQ_SCALER 3
1812
1813 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1814
1815 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1816
1817 /* Only valid when HAS_DISPLAY() is true */
1818 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1819
1820 static inline bool intel_vtd_active(void)
1821 {
1822 #ifdef CONFIG_INTEL_IOMMU
1823         if (intel_iommu_gfx_mapped)
1824                 return true;
1825 #endif
1826         return false;
1827 }
1828
1829 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1830 {
1831         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1832 }
1833
1834 static inline bool
1835 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1836 {
1837         return IS_BROXTON(dev_priv) && intel_vtd_active();
1838 }
1839
1840 /* i915_drv.c */
1841 #ifdef CONFIG_COMPAT
1842 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
1843 #else
1844 #define i915_compat_ioctl NULL
1845 #endif
1846 extern const struct dev_pm_ops i915_pm_ops;
1847
1848 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1849 void i915_driver_remove(struct drm_i915_private *i915);
1850
1851 int i915_resume_switcheroo(struct drm_i915_private *i915);
1852 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1853
1854 void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
1855 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1856
1857 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
1858 {
1859         return dev_priv->gvt;
1860 }
1861
1862 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
1863 {
1864         return dev_priv->vgpu.active;
1865 }
1866
1867 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1868                         struct drm_file *file_priv);
1869
1870 /* i915_gem.c */
1871 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1872 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1873 void i915_gem_sanitize(struct drm_i915_private *i915);
1874 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1875 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1876 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1877 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1878
1879 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1880 {
1881         /*
1882          * A single pass should suffice to release all the freed objects (along
1883          * most call paths) , but be a little more paranoid in that freeing
1884          * the objects does take a little amount of time, during which the rcu
1885          * callbacks could have added new objects into the freed list, and
1886          * armed the work again.
1887          */
1888         while (atomic_read(&i915->mm.free_count)) {
1889                 flush_work(&i915->mm.free_work);
1890                 rcu_barrier();
1891         }
1892 }
1893
1894 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1895 {
1896         /*
1897          * Similar to objects above (see i915_gem_drain_freed-objects), in
1898          * general we have workers that are armed by RCU and then rearm
1899          * themselves in their callbacks. To be paranoid, we need to
1900          * drain the workqueue a second time after waiting for the RCU
1901          * grace period so that we catch work queued via RCU from the first
1902          * pass. As neither drain_workqueue() nor flush_workqueue() report
1903          * a result, we make an assumption that we only don't require more
1904          * than 3 passes to catch all _recursive_ RCU delayed work.
1905          *
1906          */
1907         int pass = 3;
1908         do {
1909                 flush_workqueue(i915->wq);
1910                 rcu_barrier();
1911                 i915_gem_drain_freed_objects(i915);
1912         } while (--pass);
1913         drain_workqueue(i915->wq);
1914 }
1915
1916 struct i915_vma * __must_check
1917 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1918                          const struct i915_ggtt_view *view,
1919                          u64 size,
1920                          u64 alignment,
1921                          u64 flags);
1922
1923 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1924                            unsigned long flags);
1925 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1926
1927 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1928
1929 static inline int __must_check
1930 i915_mutex_lock_interruptible(struct drm_device *dev)
1931 {
1932         return mutex_lock_interruptible(&dev->struct_mutex);
1933 }
1934
1935 int i915_gem_dumb_create(struct drm_file *file_priv,
1936                          struct drm_device *dev,
1937                          struct drm_mode_create_dumb *args);
1938 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1939                       u32 handle, u64 *offset);
1940 int i915_gem_mmap_gtt_version(void);
1941
1942 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1943
1944 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1945 {
1946         return atomic_read(&error->reset_count);
1947 }
1948
1949 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1950                                           struct intel_engine_cs *engine)
1951 {
1952         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1953 }
1954
1955 void i915_gem_init_mmio(struct drm_i915_private *i915);
1956 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1957 void i915_gem_driver_register(struct drm_i915_private *i915);
1958 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1959 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1960 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1961 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1962 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1963 void i915_gem_resume(struct drm_i915_private *dev_priv);
1964 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
1965
1966 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1967 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1968
1969 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1970                                     enum i915_cache_level cache_level);
1971
1972 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1973                                 struct dma_buf *dma_buf);
1974
1975 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1976
1977 static inline struct i915_gem_context *
1978 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1979 {
1980         return idr_find(&file_priv->context_idr, id);
1981 }
1982
1983 static inline struct i915_gem_context *
1984 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1985 {
1986         struct i915_gem_context *ctx;
1987
1988         rcu_read_lock();
1989         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1990         if (ctx && !kref_get_unless_zero(&ctx->ref))
1991                 ctx = NULL;
1992         rcu_read_unlock();
1993
1994         return ctx;
1995 }
1996
1997 /* i915_gem_evict.c */
1998 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1999                                           u64 min_size, u64 alignment,
2000                                           unsigned long color,
2001                                           u64 start, u64 end,
2002                                           unsigned flags);
2003 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
2004                                          struct drm_mm_node *node,
2005                                          unsigned int flags);
2006 int i915_gem_evict_vm(struct i915_address_space *vm);
2007
2008 void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
2009 int i915_gem_init_memory_regions(struct drm_i915_private *i915);
2010
2011 /* i915_gem_internal.c */
2012 struct drm_i915_gem_object *
2013 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2014                                 phys_addr_t size);
2015
2016 /* i915_gem_tiling.c */
2017 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2018 {
2019         struct drm_i915_private *i915 = to_i915(obj->base.dev);
2020
2021         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2022                 i915_gem_object_is_tiled(obj);
2023 }
2024
2025 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2026                         unsigned int tiling, unsigned int stride);
2027 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2028                              unsigned int tiling, unsigned int stride);
2029
2030 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2031
2032 /* i915_cmd_parser.c */
2033 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2034 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2035 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
2036 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
2037                             struct drm_i915_gem_object *batch_obj,
2038                             struct drm_i915_gem_object *shadow_batch_obj,
2039                             u32 batch_start_offset,
2040                             u32 batch_len,
2041                             bool is_master);
2042
2043 /* intel_device_info.c */
2044 static inline struct intel_device_info *
2045 mkwrite_device_info(struct drm_i915_private *dev_priv)
2046 {
2047         return (struct intel_device_info *)INTEL_INFO(dev_priv);
2048 }
2049
2050 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2051                         struct drm_file *file);
2052
2053 #define __I915_REG_OP(op__, dev_priv__, ...) \
2054         intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2055
2056 #define I915_READ(reg__)         __I915_REG_OP(read, dev_priv, (reg__))
2057 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2058
2059 #define POSTING_READ(reg__)     __I915_REG_OP(posting_read, dev_priv, (reg__))
2060
2061 /* These are untraced mmio-accessors that are only valid to be used inside
2062  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
2063  * controlled.
2064  *
2065  * Think twice, and think again, before using these.
2066  *
2067  * As an example, these accessors can possibly be used between:
2068  *
2069  * spin_lock_irq(&dev_priv->uncore.lock);
2070  * intel_uncore_forcewake_get__locked();
2071  *
2072  * and
2073  *
2074  * intel_uncore_forcewake_put__locked();
2075  * spin_unlock_irq(&dev_priv->uncore.lock);
2076  *
2077  *
2078  * Note: some registers may not need forcewake held, so
2079  * intel_uncore_forcewake_{get,put} can be omitted, see
2080  * intel_uncore_forcewake_for_reg().
2081  *
2082  * Certain architectures will die if the same cacheline is concurrently accessed
2083  * by different clients (e.g. on Ivybridge). Access to registers should
2084  * therefore generally be serialised, by either the dev_priv->uncore.lock or
2085  * a more localised lock guarding all access to that bank of registers.
2086  */
2087 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2088 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2089
2090 /* register wait wrappers for display regs */
2091 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
2092         intel_wait_for_register(&(dev_priv_)->uncore, \
2093                                 (reg_), (mask_), (value_), (timeout_))
2094
2095 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({      \
2096         u32 mask__ = (mask_);                                           \
2097         intel_de_wait_for_register((dev_priv_), (reg_),                 \
2098                                    mask__, mask__, (timeout_)); \
2099 })
2100
2101 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
2102         intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_))
2103
2104 /* i915_mm.c */
2105 int remap_io_mapping(struct vm_area_struct *vma,
2106                      unsigned long addr, unsigned long pfn, unsigned long size,
2107                      struct io_mapping *iomap);
2108
2109 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2110 {
2111         if (INTEL_GEN(i915) >= 10)
2112                 return CNL_HWS_CSB_WRITE_INDEX;
2113         else
2114                 return I915_HWS_CSB_WRITE_INDEX;
2115 }
2116
2117 static inline enum i915_map_type
2118 i915_coherent_map_type(struct drm_i915_private *i915)
2119 {
2120         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2121 }
2122
2123 #endif