drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hash.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/mm_types.h>
  44 #include <linux/perf_event.h>
  45 #include <linux/pm_qos.h>
  46 #include <linux/dma-resv.h>
  47 #include <linux/shmem_fs.h>
  48 #include <linux/stackdepot.h>
  49
  50 #include <drm/intel-gtt.h>
  51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  52 #include <drm/drm_gem.h>
  53 #include <drm/drm_auth.h>
  54 #include <drm/drm_cache.h>
  55 #include <drm/drm_util.h>
  56 #include <drm/drm_dsc.h>
  57 #include <drm/drm_atomic.h>
  58 #include <drm/drm_connector.h>
  59 #include <drm/i915_mei_hdcp_interface.h>
  60
  61 #include "i915_fixed.h"
  62 #include "i915_params.h"
  63 #include "i915_reg.h"
  64 #include "i915_utils.h"
  65
  66 #include "display/intel_bios.h"
  67 #include "display/intel_display.h"
  68 #include "display/intel_display_power.h"
  69 #include "display/intel_dpll_mgr.h"
  70 #include "display/intel_dsb.h"
  71 #include "display/intel_frontbuffer.h"
  72 #include "display/intel_gmbus.h"
  73 #include "display/intel_opregion.h"
  74
  75 #include "gem/i915_gem_context_types.h"
  76 #include "gem/i915_gem_shrinker.h"
  77 #include "gem/i915_gem_stolen.h"
  78
  79 #include "gt/intel_lrc.h"
  80 #include "gt/intel_engine.h"
  81 #include "gt/intel_gt_types.h"
  82 #include "gt/intel_workarounds.h"
  83 #include "gt/uc/intel_uc.h"
  84
  85 #include "intel_device_info.h"
  86 #include "intel_pch.h"
  87 #include "intel_runtime_pm.h"
  88 #include "intel_memory_region.h"
  89 #include "intel_uncore.h"
  90 #include "intel_wakeref.h"
  91 #include "intel_wopcm.h"
  92
  93 #include "i915_gem.h"
  94 #include "i915_gem_fence_reg.h"
  95 #include "i915_gem_gtt.h"
  96 #include "i915_gpu_error.h"
  97 #include "i915_perf_types.h"
  98 #include "i915_request.h"
  99 #include "i915_scheduler.h"
 100 #include "gt/intel_timeline.h"
 101 #include "i915_vma.h"
 102 #include "i915_irq.h"
 103
 104 #include "intel_gvt.h"
 105
 106 /* General customization:
 107  */
 108
 109 #define DRIVER_NAME             "i915"
 110 #define DRIVER_DESC             "Intel Graphics"
 111 #define DRIVER_DATE             "20191007"
 112 #define DRIVER_TIMESTAMP        1570451087
 113
 114 struct drm_i915_gem_object;
 115
 116 enum hpd_pin {
 117         HPD_NONE = 0,
 118         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 119         HPD_CRT,
 120         HPD_SDVO_B,
 121         HPD_SDVO_C,
 122         HPD_PORT_A,
 123         HPD_PORT_B,
 124         HPD_PORT_C,
 125         HPD_PORT_D,
 126         HPD_PORT_E,
 127         HPD_PORT_F,
 128         HPD_PORT_G,
 129         HPD_PORT_H,
 130         HPD_PORT_I,
 131
 132         HPD_NUM_PINS
 133 };
 134
 135 #define for_each_hpd_pin(__pin) \
 136         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 137
 138 /* Threshold == 5 for long IRQs, 50 for short */
 139 #define HPD_STORM_DEFAULT_THRESHOLD 50
 140
 141 struct i915_hotplug {
 142         struct delayed_work hotplug_work;
 143
 144         struct {
 145                 unsigned long last_jiffies;
 146                 int count;
 147                 enum {
 148                         HPD_ENABLED = 0,
 149                         HPD_DISABLED = 1,
 150                         HPD_MARK_DISABLED = 2
 151                 } state;
 152         } stats[HPD_NUM_PINS];
 153         u32 event_bits;
 154         u32 retry_bits;
 155         struct delayed_work reenable_work;
 156
 157         u32 long_port_mask;
 158         u32 short_port_mask;
 159         struct work_struct dig_port_work;
 160
 161         struct work_struct poll_init_work;
 162         bool poll_enabled;
 163
 164         unsigned int hpd_storm_threshold;
 165         /* Whether or not to count short HPD IRQs in HPD storms */
 166         u8 hpd_short_storm_enabled;
 167
 168         /*
 169          * if we get a HPD irq from DP and a HPD irq from non-DP
 170          * the non-DP HPD could block the workqueue on a mode config
 171          * mutex getting, that userspace may have taken. However
 172          * userspace is waiting on the DP workqueue to run which is
 173          * blocked behind the non-DP one.
 174          */
 175         struct workqueue_struct *dp_wq;
 176 };
 177
 178 #define I915_GEM_GPU_DOMAINS \
 179         (I915_GEM_DOMAIN_RENDER | \
 180          I915_GEM_DOMAIN_SAMPLER | \
 181          I915_GEM_DOMAIN_COMMAND | \
 182          I915_GEM_DOMAIN_INSTRUCTION | \
 183          I915_GEM_DOMAIN_VERTEX)
 184
 185 struct drm_i915_private;
 186 struct i915_mm_struct;
 187 struct i915_mmu_object;
 188
 189 struct drm_i915_file_private {
 190         struct drm_i915_private *dev_priv;
 191
 192         union {
 193                 struct drm_file *file;
 194                 struct rcu_head rcu;
 195         };
 196
 197         struct {
 198                 spinlock_t lock;
 199                 struct list_head request_list;
 200         } mm;
 201
 202         struct idr context_idr;
 203         struct mutex context_idr_lock; /* guards context_idr */
 204
 205         struct idr vm_idr;
 206         struct mutex vm_idr_lock; /* guards vm_idr */
 207
 208         unsigned int bsd_engine;
 209
 210 /*
 211  * Every context ban increments per client ban score. Also
 212  * hangs in short succession increments ban score. If ban threshold
 213  * is reached, client is considered banned and submitting more work
 214  * will fail. This is a stop gap measure to limit the badly behaving
 215  * clients access to gpu. Note that unbannable contexts never increment
 216  * the client ban score.
 217  */
 218 #define I915_CLIENT_SCORE_HANG_FAST     1
 219 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 220 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 221 #define I915_CLIENT_SCORE_BANNED        9
 222         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 223         atomic_t ban_score;
 224         unsigned long hang_timestamp;
 225 };
 226
 227 /* Interface history:
 228  *
 229  * 1.1: Original.
 230  * 1.2: Add Power Management
 231  * 1.3: Add vblank support
 232  * 1.4: Fix cmdbuffer path, add heap destroy
 233  * 1.5: Add vblank pipe configuration
 234  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 235  *      - Support vertical blank on secondary display pipe
 236  */
 237 #define DRIVER_MAJOR            1
 238 #define DRIVER_MINOR            6
 239 #define DRIVER_PATCHLEVEL       0
 240
 241 struct intel_overlay;
 242 struct intel_overlay_error_state;
 243
 244 struct sdvo_device_mapping {
 245         u8 initialized;
 246         u8 dvo_port;
 247         u8 slave_addr;
 248         u8 dvo_wiring;
 249         u8 i2c_pin;
 250         u8 ddc_pin;
 251 };
 252
 253 struct intel_connector;
 254 struct intel_encoder;
 255 struct intel_atomic_state;
 256 struct intel_crtc_state;
 257 struct intel_initial_plane_config;
 258 struct intel_crtc;
 259 struct intel_limit;
 260 struct dpll;
 261 struct intel_cdclk_state;
 262
 263 struct drm_i915_display_funcs {
 264         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 265                           struct intel_cdclk_state *cdclk_state);
 266         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 267                           const struct intel_cdclk_state *cdclk_state,
 268                           enum pipe pipe);
 269         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 270                              enum i9xx_plane_id i9xx_plane);
 271         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 272         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 273         void (*initial_watermarks)(struct intel_atomic_state *state,
 274                                    struct intel_crtc_state *crtc_state);
 275         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 276                                          struct intel_crtc_state *crtc_state);
 277         void (*optimize_watermarks)(struct intel_atomic_state *state,
 278                                     struct intel_crtc_state *crtc_state);
 279         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 280         void (*update_wm)(struct intel_crtc *crtc);
 281         int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
 282         u8 (*calc_voltage_level)(int cdclk);
 283         /* Returns the active state of the crtc, and if the crtc is active,
 284          * fills out the pipe-config with the hw state. */
 285         bool (*get_pipe_config)(struct intel_crtc *,
 286                                 struct intel_crtc_state *);
 287         void (*get_initial_plane_config)(struct intel_crtc *,
 288                                          struct intel_initial_plane_config *);
 289         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 290                                   struct intel_crtc_state *crtc_state);
 291         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
 292                             struct intel_atomic_state *old_state);
 293         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 294                              struct intel_atomic_state *old_state);
 295         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 296         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 297         void (*audio_codec_enable)(struct intel_encoder *encoder,
 298                                    const struct intel_crtc_state *crtc_state,
 299                                    const struct drm_connector_state *conn_state);
 300         void (*audio_codec_disable)(struct intel_encoder *encoder,
 301                                     const struct intel_crtc_state *old_crtc_state,
 302                                     const struct drm_connector_state *old_conn_state);
 303         void (*fdi_link_train)(struct intel_crtc *crtc,
 304                                const struct intel_crtc_state *crtc_state);
 305         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 306         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 307         /* clock updates for mode set */
 308         /* cursor updates */
 309         /* render clock increase/decrease */
 310         /* display clock increase/decrease */
 311         /* pll clock increase/decrease */
 312
 313         int (*color_check)(struct intel_crtc_state *crtc_state);
 314         /*
 315          * Program double buffered color management registers during
 316          * vblank evasion. The registers should then latch during the
 317          * next vblank start, alongside any other double buffered registers
 318          * involved with the same commit.
 319          */
 320         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 321         /*
 322          * Load LUTs (and other single buffered color management
 323          * registers). Will (hopefully) be called during the vblank
 324          * following the latching of any double buffered registers
 325          * involved with the same commit.
 326          */
 327         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 328         void (*read_luts)(struct intel_crtc_state *crtc_state);
 329 };
 330
 331 struct intel_csr {
 332         struct work_struct work;
 333         const char *fw_path;
 334         u32 required_version;
 335         u32 max_fw_size; /* bytes */
 336         u32 *dmc_payload;
 337         u32 dmc_fw_size; /* dwords */
 338         u32 version;
 339         u32 mmio_count;
 340         i915_reg_t mmioaddr[20];
 341         u32 mmiodata[20];
 342         u32 dc_state;
 343         u32 target_dc_state;
 344         u32 allowed_dc_mask;
 345         intel_wakeref_t wakeref;
 346 };
 347
 348 enum i915_cache_level {
 349         I915_CACHE_NONE = 0,
 350         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 351         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 352                               caches, eg sampler/render caches, and the
 353                               large Last-Level-Cache. LLC is coherent with
 354                               the CPU, but L3 is only visible to the GPU. */
 355         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 356 };
 357
 358 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 359
 360 struct intel_fbc {
 361         /* This is always the inner lock when overlapping with struct_mutex and
 362          * it's the outer lock when overlapping with stolen_lock. */
 363         struct mutex lock;
 364         unsigned threshold;
 365         unsigned int possible_framebuffer_bits;
 366         unsigned int busy_bits;
 367         unsigned int visible_pipes_mask;
 368         struct intel_crtc *crtc;
 369
 370         struct drm_mm_node compressed_fb;
 371         struct drm_mm_node *compressed_llb;
 372
 373         bool false_color;
 374
 375         bool enabled;
 376         bool active;
 377         bool flip_pending;
 378
 379         bool underrun_detected;
 380         struct work_struct underrun_work;
 381
 382         /*
 383          * Due to the atomic rules we can't access some structures without the
 384          * appropriate locking, so we cache information here in order to avoid
 385          * these problems.
 386          */
 387         struct intel_fbc_state_cache {
 388                 struct i915_vma *vma;
 389                 unsigned long flags;
 390
 391                 struct {
 392                         unsigned int mode_flags;
 393                         u32 hsw_bdw_pixel_rate;
 394                 } crtc;
 395
 396                 struct {
 397                         unsigned int rotation;
 398                         int src_w;
 399                         int src_h;
 400                         bool visible;
 401                         /*
 402                          * Display surface base address adjustement for
 403                          * pageflips. Note that on gen4+ this only adjusts up
 404                          * to a tile, offsets within a tile are handled in
 405                          * the hw itself (with the TILEOFF register).
 406                          */
 407                         int adjusted_x;
 408                         int adjusted_y;
 409
 410                         int y;
 411
 412                         u16 pixel_blend_mode;
 413                 } plane;
 414
 415                 struct {
 416                         const struct drm_format_info *format;
 417                         unsigned int stride;
 418                 } fb;
 419         } state_cache;
 420
 421         /*
 422          * This structure contains everything that's relevant to program the
 423          * hardware registers. When we want to figure out if we need to disable
 424          * and re-enable FBC for a new configuration we just check if there's
 425          * something different in the struct. The genx_fbc_activate functions
 426          * are supposed to read from it in order to program the registers.
 427          */
 428         struct intel_fbc_reg_params {
 429                 struct i915_vma *vma;
 430                 unsigned long flags;
 431
 432                 struct {
 433                         enum pipe pipe;
 434                         enum i9xx_plane_id i9xx_plane;
 435                         unsigned int fence_y_offset;
 436                 } crtc;
 437
 438                 struct {
 439                         const struct drm_format_info *format;
 440                         unsigned int stride;
 441                 } fb;
 442
 443                 int cfb_size;
 444                 unsigned int gen9_wa_cfb_stride;
 445         } params;
 446
 447         const char *no_fbc_reason;
 448 };
 449
 450 /*
 451  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 452  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 453  * parsing for same resolution.
 454  */
 455 enum drrs_refresh_rate_type {
 456         DRRS_HIGH_RR,
 457         DRRS_LOW_RR,
 458         DRRS_MAX_RR, /* RR count */
 459 };
 460
 461 enum drrs_support_type {
 462         DRRS_NOT_SUPPORTED = 0,
 463         STATIC_DRRS_SUPPORT = 1,
 464         SEAMLESS_DRRS_SUPPORT = 2
 465 };
 466
 467 struct intel_dp;
 468 struct i915_drrs {
 469         struct mutex mutex;
 470         struct delayed_work work;
 471         struct intel_dp *dp;
 472         unsigned busy_frontbuffer_bits;
 473         enum drrs_refresh_rate_type refresh_rate_type;
 474         enum drrs_support_type type;
 475 };
 476
 477 struct i915_psr {
 478         struct mutex lock;
 479
 480 #define I915_PSR_DEBUG_MODE_MASK        0x0f
 481 #define I915_PSR_DEBUG_DEFAULT          0x00
 482 #define I915_PSR_DEBUG_DISABLE          0x01
 483 #define I915_PSR_DEBUG_ENABLE           0x02
 484 #define I915_PSR_DEBUG_FORCE_PSR1       0x03
 485 #define I915_PSR_DEBUG_IRQ              0x10
 486
 487         u32 debug;
 488         bool sink_support;
 489         bool enabled;
 490         struct intel_dp *dp;
 491         enum pipe pipe;
 492         enum transcoder transcoder;
 493         bool active;
 494         struct work_struct work;
 495         unsigned busy_frontbuffer_bits;
 496         bool sink_psr2_support;
 497         bool link_standby;
 498         bool colorimetry_support;
 499         bool psr2_enabled;
 500         u8 sink_sync_latency;
 501         ktime_t last_entry_attempt;
 502         ktime_t last_exit;
 503         bool sink_not_reliable;
 504         bool irq_aux_error;
 505         u16 su_x_granularity;
 506         bool dc3co_enabled;
 507         u32 dc3co_exit_delay;
 508         struct delayed_work idle_work;
 509 };
 510
 511 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 512 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 513 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 514 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 515 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 516 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 517
 518 struct intel_fbdev;
 519 struct intel_fbc_work;
 520
 521 struct intel_gmbus {
 522         struct i2c_adapter adapter;
 523 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 524         u32 force_bit;
 525         u32 reg0;
 526         i915_reg_t gpio_reg;
 527         struct i2c_algo_bit_data bit_algo;
 528         struct drm_i915_private *dev_priv;
 529 };
 530
 531 struct i915_suspend_saved_registers {
 532         u32 saveDSPARB;
 533         u32 saveFBC_CONTROL;
 534         u32 saveCACHE_MODE_0;
 535         u32 saveMI_ARB_STATE;
 536         u32 saveSWF0[16];
 537         u32 saveSWF1[16];
 538         u32 saveSWF3[3];
 539         u64 saveFENCE[I915_MAX_NUM_FENCES];
 540         u32 savePCH_PORT_HOTPLUG;
 541         u16 saveGCDGMBUS;
 542 };
 543
 544 struct vlv_s0ix_state;
 545
 546 struct intel_rps_ei {
 547         ktime_t ktime;
 548         u32 render_c0;
 549         u32 media_c0;
 550 };
 551
 552 struct intel_rps {
 553         struct mutex lock; /* protects enabling and the worker */
 554
 555         /*
 556          * work, interrupts_enabled and pm_iir are protected by
 557          * dev_priv->irq_lock
 558          */
 559         struct work_struct work;
 560         bool interrupts_enabled;
 561         u32 pm_iir;
 562
 563         /* PM interrupt bits that should never be masked */
 564         u32 pm_intrmsk_mbz;
 565
 566         /* Frequencies are stored in potentially platform dependent multiples.
 567          * In other words, *_freq needs to be multiplied by X to be interesting.
 568          * Soft limits are those which are used for the dynamic reclocking done
 569          * by the driver (raise frequencies under heavy loads, and lower for
 570          * lighter loads). Hard limits are those imposed by the hardware.
 571          *
 572          * A distinction is made for overclocking, which is never enabled by
 573          * default, and is considered to be above the hard limit if it's
 574          * possible at all.
 575          */
 576         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
 577         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
 578         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
 579         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
 580         u8 min_freq;            /* AKA RPn. Minimum frequency */
 581         u8 boost_freq;          /* Frequency to request when wait boosting */
 582         u8 idle_freq;           /* Frequency to request when we are idle */
 583         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
 584         u8 rp1_freq;            /* "less than" RP0 power/freqency */
 585         u8 rp0_freq;            /* Non-overclocked max frequency. */
 586         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
 587
 588         int last_adj;
 589
 590         struct {
 591                 struct mutex mutex;
 592
 593                 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
 594                 unsigned int interactive;
 595
 596                 u8 up_threshold; /* Current %busy required to uplock */
 597                 u8 down_threshold; /* Current %busy required to downclock */
 598         } power;
 599
 600         bool enabled;
 601         atomic_t num_waiters;
 602         atomic_t boosts;
 603
 604         /* manual wa residency calculations */
 605         struct intel_rps_ei ei;
 606 };
 607
 608 struct intel_llc_pstate {
 609         bool enabled;
 610 };
 611
 612 struct intel_gen6_power_mgmt {
 613         struct intel_rps rps;
 614         struct intel_llc_pstate llc_pstate;
 615 };
 616
 617 /* defined intel_pm.c */
 618 extern spinlock_t mchdev_lock;
 619
 620 struct intel_ilk_power_mgmt {
 621         u8 cur_delay;
 622         u8 min_delay;
 623         u8 max_delay;
 624         u8 fmax;
 625         u8 fstart;
 626
 627         u64 last_count1;
 628         unsigned long last_time1;
 629         unsigned long chipset_power;
 630         u64 last_count2;
 631         u64 last_time2;
 632         unsigned long gfx_power;
 633         u8 corr;
 634
 635         int c_m;
 636         int r_t;
 637 };
 638
 639 #define MAX_L3_SLICES 2
 640 struct intel_l3_parity {
 641         u32 *remap_info[MAX_L3_SLICES];
 642         struct work_struct error_work;
 643         int which_slice;
 644 };
 645
 646 struct i915_gem_mm {
 647         /** Memory allocator for GTT stolen memory */
 648         struct drm_mm stolen;
 649         /** Protects the usage of the GTT stolen memory allocator. This is
 650          * always the inner lock when overlapping with struct_mutex. */
 651         struct mutex stolen_lock;
 652
 653         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 654         spinlock_t obj_lock;
 655
 656         /**
 657          * List of objects which are purgeable.
 658          */
 659         struct list_head purge_list;
 660
 661         /**
 662          * List of objects which have allocated pages and are shrinkable.
 663          */
 664         struct list_head shrink_list;
 665
 666         /**
 667          * List of objects which are pending destruction.
 668          */
 669         struct llist_head free_list;
 670         struct work_struct free_work;
 671         /**
 672          * Count of objects pending destructions. Used to skip needlessly
 673          * waiting on an RCU barrier if no objects are waiting to be freed.
 674          */
 675         atomic_t free_count;
 676
 677         /**
 678          * Small stash of WC pages
 679          */
 680         struct pagestash wc_stash;
 681
 682         /**
 683          * tmpfs instance used for shmem backed objects
 684          */
 685         struct vfsmount *gemfs;
 686
 687         struct notifier_block oom_notifier;
 688         struct notifier_block vmap_notifier;
 689         struct shrinker shrinker;
 690
 691         /**
 692          * Workqueue to fault in userptr pages, flushed by the execbuf
 693          * when required but otherwise left to userspace to try again
 694          * on EAGAIN.
 695          */
 696         struct workqueue_struct *userptr_wq;
 697
 698         /* shrinker accounting, also useful for userland debugging */
 699         u64 shrink_memory;
 700         u32 shrink_count;
 701 };
 702
 703 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 704
 705 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
 706 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
 707
 708 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
 709 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
 710
 711 #define I915_ENGINE_WEDGED_TIMEOUT  (60 * HZ)  /* Reset but no recovery? */
 712
 713 struct ddi_vbt_port_info {
 714         /* Non-NULL if port present. */
 715         const struct child_device_config *child;
 716
 717         int max_tmds_clock;
 718
 719         /*
 720          * This is an index in the HDMI/DVI DDI buffer translation table.
 721          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
 722          * populate this field.
 723          */
 724 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
 725         u8 hdmi_level_shift;
 726
 727         u8 supports_dvi:1;
 728         u8 supports_hdmi:1;
 729         u8 supports_dp:1;
 730         u8 supports_edp:1;
 731         u8 supports_typec_usb:1;
 732         u8 supports_tbt:1;
 733
 734         u8 alternate_aux_channel;
 735         u8 alternate_ddc_pin;
 736
 737         u8 dp_boost_level;
 738         u8 hdmi_boost_level;
 739         int dp_max_link_rate;           /* 0 for not limited by VBT */
 740 };
 741
 742 enum psr_lines_to_wait {
 743         PSR_0_LINES_TO_WAIT = 0,
 744         PSR_1_LINE_TO_WAIT,
 745         PSR_4_LINES_TO_WAIT,
 746         PSR_8_LINES_TO_WAIT
 747 };
 748
 749 struct intel_vbt_data {
 750         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 751         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 752
 753         /* Feature bits */
 754         unsigned int int_tv_support:1;
 755         unsigned int lvds_dither:1;
 756         unsigned int int_crt_support:1;
 757         unsigned int lvds_use_ssc:1;
 758         unsigned int int_lvds_support:1;
 759         unsigned int display_clock_mode:1;
 760         unsigned int fdi_rx_polarity_inverted:1;
 761         unsigned int panel_type:4;
 762         int lvds_ssc_freq;
 763         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 764         enum drm_panel_orientation orientation;
 765
 766         enum drrs_support_type drrs_type;
 767
 768         struct {
 769                 int rate;
 770                 int lanes;
 771                 int preemphasis;
 772                 int vswing;
 773                 bool low_vswing;
 774                 bool initialized;
 775                 int bpp;
 776                 struct edp_power_seq pps;
 777         } edp;
 778
 779         struct {
 780                 bool enable;
 781                 bool full_link;
 782                 bool require_aux_wakeup;
 783                 int idle_frames;
 784                 enum psr_lines_to_wait lines_to_wait;
 785                 int tp1_wakeup_time_us;
 786                 int tp2_tp3_wakeup_time_us;
 787                 int psr2_tp2_tp3_wakeup_time_us;
 788         } psr;
 789
 790         struct {
 791                 u16 pwm_freq_hz;
 792                 bool present;
 793                 bool active_low_pwm;
 794                 u8 min_brightness;      /* min_brightness/255 of max */
 795                 u8 controller;          /* brightness controller number */
 796                 enum intel_backlight_type type;
 797         } backlight;
 798
 799         /* MIPI DSI */
 800         struct {
 801                 u16 panel_id;
 802                 struct mipi_config *config;
 803                 struct mipi_pps_data *pps;
 804                 u16 bl_ports;
 805                 u16 cabc_ports;
 806                 u8 seq_version;
 807                 u32 size;
 808                 u8 *data;
 809                 const u8 *sequence[MIPI_SEQ_MAX];
 810                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 811                 enum drm_panel_orientation orientation;
 812         } dsi;
 813
 814         int crt_ddc_pin;
 815
 816         int child_dev_num;
 817         struct child_device_config *child_dev;
 818
 819         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 820         struct sdvo_device_mapping sdvo_mappings[2];
 821 };
 822
 823 enum intel_ddb_partitioning {
 824         INTEL_DDB_PART_1_2,
 825         INTEL_DDB_PART_5_6, /* IVB+ */
 826 };
 827
 828 struct intel_wm_level {
 829         bool enable;
 830         u32 pri_val;
 831         u32 spr_val;
 832         u32 cur_val;
 833         u32 fbc_val;
 834 };
 835
 836 struct ilk_wm_values {
 837         u32 wm_pipe[3];
 838         u32 wm_lp[3];
 839         u32 wm_lp_spr[3];
 840         u32 wm_linetime[3];
 841         bool enable_fbc_wm;
 842         enum intel_ddb_partitioning partitioning;
 843 };
 844
 845 struct g4x_pipe_wm {
 846         u16 plane[I915_MAX_PLANES];
 847         u16 fbc;
 848 };
 849
 850 struct g4x_sr_wm {
 851         u16 plane;
 852         u16 cursor;
 853         u16 fbc;
 854 };
 855
 856 struct vlv_wm_ddl_values {
 857         u8 plane[I915_MAX_PLANES];
 858 };
 859
 860 struct vlv_wm_values {
 861         struct g4x_pipe_wm pipe[3];
 862         struct g4x_sr_wm sr;
 863         struct vlv_wm_ddl_values ddl[3];
 864         u8 level;
 865         bool cxsr;
 866 };
 867
 868 struct g4x_wm_values {
 869         struct g4x_pipe_wm pipe[2];
 870         struct g4x_sr_wm sr;
 871         struct g4x_sr_wm hpll;
 872         bool cxsr;
 873         bool hpll_en;
 874         bool fbc_en;
 875 };
 876
 877 struct skl_ddb_entry {
 878         u16 start, end; /* in number of blocks, 'end' is exclusive */
 879 };
 880
 881 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 882 {
 883         return entry->end - entry->start;
 884 }
 885
 886 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 887                                        const struct skl_ddb_entry *e2)
 888 {
 889         if (e1->start == e2->start && e1->end == e2->end)
 890                 return true;
 891
 892         return false;
 893 }
 894
 895 struct skl_ddb_allocation {
 896         u8 enabled_slices; /* GEN11 has configurable 2 slices */
 897 };
 898
 899 struct skl_ddb_values {
 900         unsigned dirty_pipes;
 901         struct skl_ddb_allocation ddb;
 902 };
 903
 904 struct skl_wm_level {
 905         u16 min_ddb_alloc;
 906         u16 plane_res_b;
 907         u8 plane_res_l;
 908         bool plane_en;
 909         bool ignore_lines;
 910 };
 911
 912 /* Stores plane specific WM parameters */
 913 struct skl_wm_params {
 914         bool x_tiled, y_tiled;
 915         bool rc_surface;
 916         bool is_planar;
 917         u32 width;
 918         u8 cpp;
 919         u32 plane_pixel_rate;
 920         u32 y_min_scanlines;
 921         u32 plane_bytes_per_line;
 922         uint_fixed_16_16_t plane_blocks_per_line;
 923         uint_fixed_16_16_t y_tile_minimum;
 924         u32 linetime_us;
 925         u32 dbuf_block_size;
 926 };
 927
 928 enum intel_pipe_crc_source {
 929         INTEL_PIPE_CRC_SOURCE_NONE,
 930         INTEL_PIPE_CRC_SOURCE_PLANE1,
 931         INTEL_PIPE_CRC_SOURCE_PLANE2,
 932         INTEL_PIPE_CRC_SOURCE_PLANE3,
 933         INTEL_PIPE_CRC_SOURCE_PLANE4,
 934         INTEL_PIPE_CRC_SOURCE_PLANE5,
 935         INTEL_PIPE_CRC_SOURCE_PLANE6,
 936         INTEL_PIPE_CRC_SOURCE_PLANE7,
 937         INTEL_PIPE_CRC_SOURCE_PIPE,
 938         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
 939         INTEL_PIPE_CRC_SOURCE_TV,
 940         INTEL_PIPE_CRC_SOURCE_DP_B,
 941         INTEL_PIPE_CRC_SOURCE_DP_C,
 942         INTEL_PIPE_CRC_SOURCE_DP_D,
 943         INTEL_PIPE_CRC_SOURCE_AUTO,
 944         INTEL_PIPE_CRC_SOURCE_MAX,
 945 };
 946
 947 #define INTEL_PIPE_CRC_ENTRIES_NR       128
 948 struct intel_pipe_crc {
 949         spinlock_t lock;
 950         int skipped;
 951         enum intel_pipe_crc_source source;
 952 };
 953
 954 struct i915_frontbuffer_tracking {
 955         spinlock_t lock;
 956
 957         /*
 958          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 959          * scheduled flips.
 960          */
 961         unsigned busy_bits;
 962         unsigned flip_bits;
 963 };
 964
 965 struct i915_virtual_gpu {
 966         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 967         bool active;
 968         u32 caps;
 969 };
 970
 971 /* used in computing the new watermarks state */
 972 struct intel_wm_config {
 973         unsigned int num_pipes_active;
 974         bool sprites_enabled;
 975         bool sprites_scaled;
 976 };
 977
 978 struct intel_cdclk_state {
 979         unsigned int cdclk, vco, ref, bypass;
 980         u8 voltage_level;
 981 };
 982
 983 struct drm_i915_private {
 984         struct drm_device drm;
 985
 986         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 987         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 988         struct intel_driver_caps caps;
 989
 990         /**
 991          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 992          * end of stolen which we can optionally use to create GEM objects
 993          * backed by stolen memory. Note that stolen_usable_size tells us
 994          * exactly how much of this we are actually allowed to use, given that
 995          * some portion of it is in fact reserved for use by hardware functions.
 996          */
 997         struct resource dsm;
 998         /**
 999          * Reseved portion of Data Stolen Memory
1000          */
1001         struct resource dsm_reserved;
1002
1003         /*
1004          * Stolen memory is segmented in hardware with different portions
1005          * offlimits to certain functions.
1006          *
1007          * The drm_mm is initialised to the total accessible range, as found
1008          * from the PCI config. On Broadwell+, this is further restricted to
1009          * avoid the first page! The upper end of stolen memory is reserved for
1010          * hardware functions and similarly removed from the accessible range.
1011          */
1012         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
1013
1014         struct intel_uncore uncore;
1015         struct intel_uncore_mmio_debug mmio_debug;
1016
1017         struct i915_virtual_gpu vgpu;
1018
1019         struct intel_gvt *gvt;
1020
1021         struct intel_wopcm wopcm;
1022
1023         struct intel_csr csr;
1024
1025         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1026
1027         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1028          * controller on different i2c buses. */
1029         struct mutex gmbus_mutex;
1030
1031         /**
1032          * Base address of where the gmbus and gpio blocks are located (either
1033          * on PCH or on SoC for platforms without PCH).
1034          */
1035         u32 gpio_mmio_base;
1036
1037         u32 hsw_psr_mmio_adjust;
1038
1039         /* MMIO base address for MIPI regs */
1040         u32 mipi_mmio_base;
1041
1042         u32 pps_mmio_base;
1043
1044         wait_queue_head_t gmbus_wait_queue;
1045
1046         struct pci_dev *bridge_dev;
1047
1048         /* Context used internally to idle the GPU and setup initial state */
1049         struct i915_gem_context *kernel_context;
1050
1051         struct intel_engine_cs *engine[I915_NUM_ENGINES];
1052         struct rb_root uabi_engines;
1053
1054         struct resource mch_res;
1055
1056         /* protects the irq masks */
1057         spinlock_t irq_lock;
1058
1059         bool display_irqs_enabled;
1060
1061         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1062         struct pm_qos_request pm_qos;
1063
1064         /* Sideband mailbox protection */
1065         struct mutex sb_lock;
1066         struct pm_qos_request sb_qos;
1067
1068         /** Cached value of IMR to avoid reads in updating the bitfield */
1069         union {
1070                 u32 irq_mask;
1071                 u32 de_irq_mask[I915_MAX_PIPES];
1072         };
1073         u32 pm_rps_events;
1074         u32 pipestat_irq_mask[I915_MAX_PIPES];
1075
1076         struct i915_hotplug hotplug;
1077         struct intel_fbc fbc;
1078         struct i915_drrs drrs;
1079         struct intel_opregion opregion;
1080         struct intel_vbt_data vbt;
1081
1082         bool preserve_bios_swizzle;
1083
1084         /* overlay */
1085         struct intel_overlay *overlay;
1086
1087         /* backlight registers and fields in struct intel_panel */
1088         struct mutex backlight_lock;
1089
1090         /* protects panel power sequencer state */
1091         struct mutex pps_mutex;
1092
1093         unsigned int fsb_freq, mem_freq, is_ddr3;
1094         unsigned int skl_preferred_vco_freq;
1095         unsigned int max_cdclk_freq;
1096
1097         unsigned int max_dotclk_freq;
1098         unsigned int rawclk_freq;
1099         unsigned int hpll_freq;
1100         unsigned int fdi_pll_freq;
1101         unsigned int czclk_freq;
1102
1103         struct {
1104                 /*
1105                  * The current logical cdclk state.
1106                  * See intel_atomic_state.cdclk.logical
1107                  *
1108                  * For reading holding any crtc lock is sufficient,
1109                  * for writing must hold all of them.
1110                  */
1111                 struct intel_cdclk_state logical;
1112                 /*
1113                  * The current actual cdclk state.
1114                  * See intel_atomic_state.cdclk.actual
1115                  */
1116                 struct intel_cdclk_state actual;
1117                 /* The current hardware cdclk state */
1118                 struct intel_cdclk_state hw;
1119
1120                 /* cdclk, divider, and ratio table from bspec */
1121                 const struct intel_cdclk_vals *table;
1122
1123                 int force_min_cdclk;
1124         } cdclk;
1125
1126         /**
1127          * wq - Driver workqueue for GEM.
1128          *
1129          * NOTE: Work items scheduled here are not allowed to grab any modeset
1130          * locks, for otherwise the flushing done in the pageflip code will
1131          * result in deadlocks.
1132          */
1133         struct workqueue_struct *wq;
1134
1135         /* ordered wq for modesets */
1136         struct workqueue_struct *modeset_wq;
1137         /* unbound hipri wq for page flips/plane updates */
1138         struct workqueue_struct *flip_wq;
1139
1140         /* Display functions */
1141         struct drm_i915_display_funcs display;
1142
1143         /* PCH chipset type */
1144         enum intel_pch pch_type;
1145         unsigned short pch_id;
1146
1147         unsigned long quirks;
1148
1149         struct drm_atomic_state *modeset_restore_state;
1150         struct drm_modeset_acquire_ctx reset_ctx;
1151
1152         struct i915_ggtt ggtt; /* VM representing the global address space */
1153
1154         struct i915_gem_mm mm;
1155         DECLARE_HASHTABLE(mm_structs, 7);
1156         struct mutex mm_lock;
1157
1158         /* Kernel Modesetting */
1159
1160         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1161         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1162
1163 #ifdef CONFIG_DEBUG_FS
1164         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1165 #endif
1166
1167         /* dpll and cdclk state is protected by connection_mutex */
1168         int num_shared_dpll;
1169         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1170         const struct intel_dpll_mgr *dpll_mgr;
1171
1172         /*
1173          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1174          * Must be global rather than per dpll, because on some platforms
1175          * plls share registers.
1176          */
1177         struct mutex dpll_lock;
1178
1179         u8 active_pipes;
1180         /* minimum acceptable cdclk for each pipe */
1181         int min_cdclk[I915_MAX_PIPES];
1182         /* minimum acceptable voltage level for each pipe */
1183         u8 min_voltage_level[I915_MAX_PIPES];
1184
1185         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1186
1187         struct i915_wa_list gt_wa_list;
1188
1189         struct i915_frontbuffer_tracking fb_tracking;
1190
1191         struct intel_atomic_helper {
1192                 struct llist_head free_list;
1193                 struct work_struct free_work;
1194         } atomic_helper;
1195
1196         u16 orig_clock;
1197
1198         bool mchbar_need_disable;
1199
1200         struct intel_l3_parity l3_parity;
1201
1202         /*
1203          * edram size in MB.
1204          * Cannot be determined by PCIID. You must always read a register.
1205          */
1206         u32 edram_size_mb;
1207
1208         /* gen6+ GT PM state */
1209         struct intel_gen6_power_mgmt gt_pm;
1210
1211         /* ilk-only ips/rps state. Everything in here is protected by the global
1212          * mchdev_lock in intel_pm.c */
1213         struct intel_ilk_power_mgmt ips;
1214
1215         struct i915_power_domains power_domains;
1216
1217         struct i915_psr psr;
1218
1219         struct i915_gpu_error gpu_error;
1220
1221         struct drm_i915_gem_object *vlv_pctx;
1222
1223         /* list of fbdev register on this device */
1224         struct intel_fbdev *fbdev;
1225         struct work_struct fbdev_suspend_work;
1226
1227         struct drm_property *broadcast_rgb_property;
1228         struct drm_property *force_audio_property;
1229
1230         /* hda/i915 audio component */
1231         struct i915_audio_component *audio_component;
1232         bool audio_component_registered;
1233         /**
1234          * av_mutex - mutex for audio/video sync
1235          *
1236          */
1237         struct mutex av_mutex;
1238         int audio_power_refcount;
1239         u32 audio_freq_cntrl;
1240
1241         u32 fdi_rx_config;
1242
1243         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1244         u32 chv_phy_control;
1245         /*
1246          * Shadows for CHV DPLL_MD regs to keep the state
1247          * checker somewhat working in the presence hardware
1248          * crappiness (can't read out DPLL_MD for pipes B & C).
1249          */
1250         u32 chv_dpll_md[I915_MAX_PIPES];
1251         u32 bxt_phy_grc;
1252
1253         u32 suspend_count;
1254         bool power_domains_suspended;
1255         struct i915_suspend_saved_registers regfile;
1256         struct vlv_s0ix_state *vlv_s0ix_state;
1257
1258         enum {
1259                 I915_SAGV_UNKNOWN = 0,
1260                 I915_SAGV_DISABLED,
1261                 I915_SAGV_ENABLED,
1262                 I915_SAGV_NOT_CONTROLLED
1263         } sagv_status;
1264
1265         u32 sagv_block_time_us;
1266
1267         struct {
1268                 /*
1269                  * Raw watermark latency values:
1270                  * in 0.1us units for WM0,
1271                  * in 0.5us units for WM1+.
1272                  */
1273                 /* primary */
1274                 u16 pri_latency[5];
1275                 /* sprite */
1276                 u16 spr_latency[5];
1277                 /* cursor */
1278                 u16 cur_latency[5];
1279                 /*
1280                  * Raw watermark memory latency values
1281                  * for SKL for all 8 levels
1282                  * in 1us units.
1283                  */
1284                 u16 skl_latency[8];
1285
1286                 /* current hardware state */
1287                 union {
1288                         struct ilk_wm_values hw;
1289                         struct skl_ddb_values skl_hw;
1290                         struct vlv_wm_values vlv;
1291                         struct g4x_wm_values g4x;
1292                 };
1293
1294                 u8 max_level;
1295
1296                 /*
1297                  * Should be held around atomic WM register writing; also
1298                  * protects * intel_crtc->wm.active and
1299                  * crtc_state->wm.need_postvbl_update.
1300                  */
1301                 struct mutex wm_mutex;
1302
1303                 /*
1304                  * Set during HW readout of watermarks/DDB.  Some platforms
1305                  * need to know when we're still using BIOS-provided values
1306                  * (which we don't fully trust).
1307                  */
1308                 bool distrust_bios_wm;
1309         } wm;
1310
1311         struct dram_info {
1312                 bool valid;
1313                 bool is_16gb_dimm;
1314                 u8 num_channels;
1315                 u8 ranks;
1316                 u32 bandwidth_kbps;
1317                 bool symmetric_memory;
1318                 enum intel_dram_type {
1319                         INTEL_DRAM_UNKNOWN,
1320                         INTEL_DRAM_DDR3,
1321                         INTEL_DRAM_DDR4,
1322                         INTEL_DRAM_LPDDR3,
1323                         INTEL_DRAM_LPDDR4
1324                 } type;
1325         } dram_info;
1326
1327         struct intel_bw_info {
1328                 unsigned int deratedbw[3]; /* for each QGV point */
1329                 u8 num_qgv_points;
1330                 u8 num_planes;
1331         } max_bw[6];
1332
1333         struct drm_private_obj bw_obj;
1334
1335         struct intel_runtime_pm runtime_pm;
1336
1337         struct i915_perf perf;
1338
1339         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1340         struct intel_gt gt;
1341
1342         struct {
1343                 struct notifier_block pm_notifier;
1344
1345                 struct i915_gem_contexts {
1346                         spinlock_t lock; /* locks list */
1347                         struct list_head list;
1348
1349                         struct llist_head free_list;
1350                         struct work_struct free_work;
1351                 } contexts;
1352         } gem;
1353
1354         /* For i915gm/i945gm vblank irq workaround */
1355         u8 vblank_enabled;
1356
1357         /* perform PHY state sanity checks? */
1358         bool chv_phy_assert[2];
1359
1360         bool ipc_enabled;
1361
1362         /* Used to save the pipe-to-encoder mapping for audio */
1363         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1364
1365         /* necessary resource sharing with HDMI LPE audio driver. */
1366         struct {
1367                 struct platform_device *platdev;
1368                 int     irq;
1369         } lpe_audio;
1370
1371         struct i915_pmu pmu;
1372
1373         struct i915_hdcp_comp_master *hdcp_master;
1374         bool hdcp_comp_added;
1375
1376         /* Mutex to protect the above hdcp component related values. */
1377         struct mutex hdcp_comp_mutex;
1378
1379         /*
1380          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1381          * will be rejected. Instead look for a better place.
1382          */
1383 };
1384
1385 struct dram_dimm_info {
1386         u8 size, width, ranks;
1387 };
1388
1389 struct dram_channel_info {
1390         struct dram_dimm_info dimm_l, dimm_s;
1391         u8 ranks;
1392         bool is_16gb_dimm;
1393 };
1394
1395 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1396 {
1397         return container_of(dev, struct drm_i915_private, drm);
1398 }
1399
1400 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1401 {
1402         return dev_get_drvdata(kdev);
1403 }
1404
1405 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1406 {
1407         return pci_get_drvdata(pdev);
1408 }
1409
1410 /* Simple iterator over all initialised engines */
1411 #define for_each_engine(engine__, dev_priv__, id__) \
1412         for ((id__) = 0; \
1413              (id__) < I915_NUM_ENGINES; \
1414              (id__)++) \
1415                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1416
1417 /* Iterator over subset of engines selected by mask */
1418 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1419         for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1420              (tmp__) ? \
1421              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1422              0;)
1423
1424 #define rb_to_uabi_engine(rb) \
1425         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1426
1427 #define for_each_uabi_engine(engine__, i915__) \
1428         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1429              (engine__); \
1430              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1431
1432 #define I915_GTT_OFFSET_NONE ((u32)-1)
1433
1434 /*
1435  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1436  * considered to be the frontbuffer for the given plane interface-wise. This
1437  * doesn't mean that the hw necessarily already scans it out, but that any
1438  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1439  *
1440  * We have one bit per pipe and per scanout plane type.
1441  */
1442 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1443 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1444         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1445         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1446         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1447 })
1448 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1449         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1450 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1451         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1452                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1453
1454 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1455 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1456 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1457
1458 #define INTEL_GEN(dev_priv)     (INTEL_INFO(dev_priv)->gen)
1459 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1460
1461 #define REVID_FOREVER           0xff
1462 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
1463
1464 #define INTEL_GEN_MASK(s, e) ( \
1465         BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1466         BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1467         GENMASK((e) - 1, (s) - 1))
1468
1469 /* Returns true if Gen is in inclusive range [Start, End] */
1470 #define IS_GEN_RANGE(dev_priv, s, e) \
1471         (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1472
1473 #define IS_GEN(dev_priv, n) \
1474         (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1475          INTEL_INFO(dev_priv)->gen == (n))
1476
1477 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1478
1479 /*
1480  * Return true if revision is in range [since,until] inclusive.
1481  *
1482  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1483  */
1484 #define IS_REVID(p, since, until) \
1485         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1486
1487 static __always_inline unsigned int
1488 __platform_mask_index(const struct intel_runtime_info *info,
1489                       enum intel_platform p)
1490 {
1491         const unsigned int pbits =
1492                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1493
1494         /* Expand the platform_mask array if this fails. */
1495         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1496                      pbits * ARRAY_SIZE(info->platform_mask));
1497
1498         return p / pbits;
1499 }
1500
1501 static __always_inline unsigned int
1502 __platform_mask_bit(const struct intel_runtime_info *info,
1503                     enum intel_platform p)
1504 {
1505         const unsigned int pbits =
1506                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1507
1508         return p % pbits + INTEL_SUBPLATFORM_BITS;
1509 }
1510
1511 static inline u32
1512 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1513 {
1514         const unsigned int pi = __platform_mask_index(info, p);
1515
1516         return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1517 }
1518
1519 static __always_inline bool
1520 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1521 {
1522         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1523         const unsigned int pi = __platform_mask_index(info, p);
1524         const unsigned int pb = __platform_mask_bit(info, p);
1525
1526         BUILD_BUG_ON(!__builtin_constant_p(p));
1527
1528         return info->platform_mask[pi] & BIT(pb);
1529 }
1530
1531 static __always_inline bool
1532 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1533                enum intel_platform p, unsigned int s)
1534 {
1535         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1536         const unsigned int pi = __platform_mask_index(info, p);
1537         const unsigned int pb = __platform_mask_bit(info, p);
1538         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1539         const u32 mask = info->platform_mask[pi];
1540
1541         BUILD_BUG_ON(!__builtin_constant_p(p));
1542         BUILD_BUG_ON(!__builtin_constant_p(s));
1543         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1544
1545         /* Shift and test on the MSB position so sign flag can be used. */
1546         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1547 }
1548
1549 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1550
1551 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1552 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1553 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1554 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1555 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1556 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1557 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1558 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1559 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1560 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1561 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1562 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1563 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1564 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1565 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1566 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1567 #define IS_IRONLAKE_M(dev_priv) \
1568         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1569 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1570 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1571                                  INTEL_INFO(dev_priv)->gt == 1)
1572 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1573 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1574 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1575 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1576 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1577 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1578 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1579 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1580 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1581 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1582 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1583 #define IS_ELKHARTLAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1584 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1585 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1586                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1587 #define IS_BDW_ULT(dev_priv) \
1588         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1589 #define IS_BDW_ULX(dev_priv) \
1590         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1591 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1592                                  INTEL_INFO(dev_priv)->gt == 3)
1593 #define IS_HSW_ULT(dev_priv) \
1594         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1595 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1596                                  INTEL_INFO(dev_priv)->gt == 3)
1597 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1598                                  INTEL_INFO(dev_priv)->gt == 1)
1599 /* ULX machines are also considered ULT. */
1600 #define IS_HSW_ULX(dev_priv) \
1601         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1602 #define IS_SKL_ULT(dev_priv) \
1603         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1604 #define IS_SKL_ULX(dev_priv) \
1605         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1606 #define IS_KBL_ULT(dev_priv) \
1607         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1608 #define IS_KBL_ULX(dev_priv) \
1609         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1610 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1611                                  INTEL_INFO(dev_priv)->gt == 2)
1612 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1613                                  INTEL_INFO(dev_priv)->gt == 3)
1614 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1615                                  INTEL_INFO(dev_priv)->gt == 4)
1616 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1617                                  INTEL_INFO(dev_priv)->gt == 2)
1618 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1619                                  INTEL_INFO(dev_priv)->gt == 3)
1620 #define IS_CFL_ULT(dev_priv) \
1621         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1622 #define IS_CFL_ULX(dev_priv) \
1623         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1624 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1625                                  INTEL_INFO(dev_priv)->gt == 2)
1626 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1627                                  INTEL_INFO(dev_priv)->gt == 3)
1628 #define IS_CNL_WITH_PORT_F(dev_priv) \
1629         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1630 #define IS_ICL_WITH_PORT_F(dev_priv) \
1631         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1632
1633 #define SKL_REVID_A0            0x0
1634 #define SKL_REVID_B0            0x1
1635 #define SKL_REVID_C0            0x2
1636 #define SKL_REVID_D0            0x3
1637 #define SKL_REVID_E0            0x4
1638 #define SKL_REVID_F0            0x5
1639 #define SKL_REVID_G0            0x6
1640 #define SKL_REVID_H0            0x7
1641
1642 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1643
1644 #define BXT_REVID_A0            0x0
1645 #define BXT_REVID_A1            0x1
1646 #define BXT_REVID_B0            0x3
1647 #define BXT_REVID_B_LAST        0x8
1648 #define BXT_REVID_C0            0x9
1649
1650 #define IS_BXT_REVID(dev_priv, since, until) \
1651         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1652
1653 #define KBL_REVID_A0            0x0
1654 #define KBL_REVID_B0            0x1
1655 #define KBL_REVID_C0            0x2
1656 #define KBL_REVID_D0            0x3
1657 #define KBL_REVID_E0            0x4
1658
1659 #define IS_KBL_REVID(dev_priv, since, until) \
1660         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1661
1662 #define GLK_REVID_A0            0x0
1663 #define GLK_REVID_A1            0x1
1664
1665 #define IS_GLK_REVID(dev_priv, since, until) \
1666         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1667
1668 #define CNL_REVID_A0            0x0
1669 #define CNL_REVID_B0            0x1
1670 #define CNL_REVID_C0            0x2
1671
1672 #define IS_CNL_REVID(p, since, until) \
1673         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1674
1675 #define ICL_REVID_A0            0x0
1676 #define ICL_REVID_A2            0x1
1677 #define ICL_REVID_B0            0x3
1678 #define ICL_REVID_B2            0x4
1679 #define ICL_REVID_C0            0x5
1680
1681 #define IS_ICL_REVID(p, since, until) \
1682         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1683
1684 #define TGL_REVID_A0            0x0
1685
1686 #define IS_TGL_REVID(p, since, until) \
1687         (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1688
1689 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1690 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1691 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1692
1693 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1694
1695 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({                \
1696         unsigned int first__ = (first);                                 \
1697         unsigned int count__ = (count);                                 \
1698         (INTEL_INFO(dev_priv)->engine_mask &                            \
1699          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1700 })
1701 #define VDBOX_MASK(dev_priv) \
1702         ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1703 #define VEBOX_MASK(dev_priv) \
1704         ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1705
1706 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1707 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1708 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1709 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
1710                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1711
1712 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1713
1714 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1715                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1716 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1717                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1718 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1719                 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1720
1721 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1722
1723 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1724 #define HAS_PPGTT(dev_priv) \
1725         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1726 #define HAS_FULL_PPGTT(dev_priv) \
1727         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1728
1729 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1730         GEM_BUG_ON((sizes) == 0); \
1731         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1732 })
1733
1734 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1735 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1736                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1737
1738 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1739 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1740
1741 /* WaRsDisableCoarsePowerGating:skl,cnl */
1742 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1743         (IS_CANNONLAKE(dev_priv) || \
1744          IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
1745
1746 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1747 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1748                                         IS_GEMINILAKE(dev_priv) || \
1749                                         IS_KABYLAKE(dev_priv))
1750
1751 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1752  * rows, which changed the alignment requirements and fence programming.
1753  */
1754 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1755                                          !(IS_I915G(dev_priv) || \
1756                                          IS_I915GM(dev_priv)))
1757 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1758 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1759
1760 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1761 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1762 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1763
1764 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1765
1766 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1767
1768 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1769 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1770 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1771 #define HAS_TRANSCODER_EDP(dev_priv)     (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
1772
1773 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1774 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1775 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1776
1777 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1778
1779 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
1780
1781 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1782 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1783
1784 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1785
1786 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1787
1788 /* Having GuC is not the same as using GuC */
1789 #define USES_GUC(dev_priv)              intel_uc_uses_guc(&(dev_priv)->gt.uc)
1790 #define USES_GUC_SUBMISSION(dev_priv)   intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
1791
1792 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1793
1794 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1795
1796
1797 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1798
1799 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1800
1801 /* DPF == dynamic parity feature */
1802 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1803 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1804                                  2 : HAS_L3_DPF(dev_priv))
1805
1806 #define GT_FREQUENCY_MULTIPLIER 50
1807 #define GEN9_FREQ_SCALER 3
1808
1809 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1810
1811 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1812
1813 /* Only valid when HAS_DISPLAY() is true */
1814 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1815
1816 static inline bool intel_vtd_active(void)
1817 {
1818 #ifdef CONFIG_INTEL_IOMMU
1819         if (intel_iommu_gfx_mapped)
1820                 return true;
1821 #endif
1822         return false;
1823 }
1824
1825 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1826 {
1827         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1828 }
1829
1830 static inline bool
1831 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1832 {
1833         return IS_BROXTON(dev_priv) && intel_vtd_active();
1834 }
1835
1836 /* i915_drv.c */
1837 #ifdef CONFIG_COMPAT
1838 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
1839 #else
1840 #define i915_compat_ioctl NULL
1841 #endif
1842 extern const struct dev_pm_ops i915_pm_ops;
1843
1844 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1845 void i915_driver_remove(struct drm_i915_private *i915);
1846
1847 int i915_resume_switcheroo(struct drm_i915_private *i915);
1848 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1849
1850 void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
1851 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1852
1853 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
1854 {
1855         return dev_priv->gvt;
1856 }
1857
1858 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
1859 {
1860         return dev_priv->vgpu.active;
1861 }
1862
1863 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1864                         struct drm_file *file_priv);
1865
1866 /* i915_gem.c */
1867 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1868 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1869 void i915_gem_sanitize(struct drm_i915_private *i915);
1870 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1871 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1872 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1873 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1874
1875 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1876 {
1877         /*
1878          * A single pass should suffice to release all the freed objects (along
1879          * most call paths) , but be a little more paranoid in that freeing
1880          * the objects does take a little amount of time, during which the rcu
1881          * callbacks could have added new objects into the freed list, and
1882          * armed the work again.
1883          */
1884         while (atomic_read(&i915->mm.free_count)) {
1885                 flush_work(&i915->mm.free_work);
1886                 rcu_barrier();
1887         }
1888 }
1889
1890 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1891 {
1892         /*
1893          * Similar to objects above (see i915_gem_drain_freed-objects), in
1894          * general we have workers that are armed by RCU and then rearm
1895          * themselves in their callbacks. To be paranoid, we need to
1896          * drain the workqueue a second time after waiting for the RCU
1897          * grace period so that we catch work queued via RCU from the first
1898          * pass. As neither drain_workqueue() nor flush_workqueue() report
1899          * a result, we make an assumption that we only don't require more
1900          * than 3 passes to catch all _recursive_ RCU delayed work.
1901          *
1902          */
1903         int pass = 3;
1904         do {
1905                 flush_workqueue(i915->wq);
1906                 rcu_barrier();
1907                 i915_gem_drain_freed_objects(i915);
1908         } while (--pass);
1909         drain_workqueue(i915->wq);
1910 }
1911
1912 struct i915_vma * __must_check
1913 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1914                          const struct i915_ggtt_view *view,
1915                          u64 size,
1916                          u64 alignment,
1917                          u64 flags);
1918
1919 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1920                            unsigned long flags);
1921 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1922
1923 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1924
1925 static inline int __must_check
1926 i915_mutex_lock_interruptible(struct drm_device *dev)
1927 {
1928         return mutex_lock_interruptible(&dev->struct_mutex);
1929 }
1930
1931 int i915_gem_dumb_create(struct drm_file *file_priv,
1932                          struct drm_device *dev,
1933                          struct drm_mode_create_dumb *args);
1934 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1935                       u32 handle, u64 *offset);
1936 int i915_gem_mmap_gtt_version(void);
1937
1938 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1939
1940 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1941 {
1942         return atomic_read(&error->reset_count);
1943 }
1944
1945 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1946                                           struct intel_engine_cs *engine)
1947 {
1948         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1949 }
1950
1951 void i915_gem_init_mmio(struct drm_i915_private *i915);
1952 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1953 void i915_gem_driver_register(struct drm_i915_private *i915);
1954 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1955 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1956 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1957 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1958 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1959 void i915_gem_resume(struct drm_i915_private *dev_priv);
1960 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
1961
1962 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1963 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1964
1965 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1966                                     enum i915_cache_level cache_level);
1967
1968 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1969                                 struct dma_buf *dma_buf);
1970
1971 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1972
1973 static inline struct i915_gem_context *
1974 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1975 {
1976         return idr_find(&file_priv->context_idr, id);
1977 }
1978
1979 static inline struct i915_gem_context *
1980 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1981 {
1982         struct i915_gem_context *ctx;
1983
1984         rcu_read_lock();
1985         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1986         if (ctx && !kref_get_unless_zero(&ctx->ref))
1987                 ctx = NULL;
1988         rcu_read_unlock();
1989
1990         return ctx;
1991 }
1992
1993 /* i915_gem_evict.c */
1994 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1995                                           u64 min_size, u64 alignment,
1996                                           unsigned long color,
1997                                           u64 start, u64 end,
1998                                           unsigned flags);
1999 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
2000                                          struct drm_mm_node *node,
2001                                          unsigned int flags);
2002 int i915_gem_evict_vm(struct i915_address_space *vm);
2003
2004 /* i915_gem_internal.c */
2005 struct drm_i915_gem_object *
2006 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2007                                 phys_addr_t size);
2008
2009 /* i915_gem_tiling.c */
2010 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2011 {
2012         struct drm_i915_private *i915 = to_i915(obj->base.dev);
2013
2014         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2015                 i915_gem_object_is_tiled(obj);
2016 }
2017
2018 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2019                         unsigned int tiling, unsigned int stride);
2020 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2021                              unsigned int tiling, unsigned int stride);
2022
2023 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2024
2025 /* i915_cmd_parser.c */
2026 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2027 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2028 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
2029 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
2030                             struct drm_i915_gem_object *batch_obj,
2031                             struct drm_i915_gem_object *shadow_batch_obj,
2032                             u32 batch_start_offset,
2033                             u32 batch_len,
2034                             bool is_master);
2035
2036 /* intel_device_info.c */
2037 static inline struct intel_device_info *
2038 mkwrite_device_info(struct drm_i915_private *dev_priv)
2039 {
2040         return (struct intel_device_info *)INTEL_INFO(dev_priv);
2041 }
2042
2043 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2044                         struct drm_file *file);
2045
2046 #define __I915_REG_OP(op__, dev_priv__, ...) \
2047         intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2048
2049 #define I915_READ(reg__)         __I915_REG_OP(read, dev_priv, (reg__))
2050 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2051
2052 #define POSTING_READ(reg__)     __I915_REG_OP(posting_read, dev_priv, (reg__))
2053
2054 /* These are untraced mmio-accessors that are only valid to be used inside
2055  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
2056  * controlled.
2057  *
2058  * Think twice, and think again, before using these.
2059  *
2060  * As an example, these accessors can possibly be used between:
2061  *
2062  * spin_lock_irq(&dev_priv->uncore.lock);
2063  * intel_uncore_forcewake_get__locked();
2064  *
2065  * and
2066  *
2067  * intel_uncore_forcewake_put__locked();
2068  * spin_unlock_irq(&dev_priv->uncore.lock);
2069  *
2070  *
2071  * Note: some registers may not need forcewake held, so
2072  * intel_uncore_forcewake_{get,put} can be omitted, see
2073  * intel_uncore_forcewake_for_reg().
2074  *
2075  * Certain architectures will die if the same cacheline is concurrently accessed
2076  * by different clients (e.g. on Ivybridge). Access to registers should
2077  * therefore generally be serialised, by either the dev_priv->uncore.lock or
2078  * a more localised lock guarding all access to that bank of registers.
2079  */
2080 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2081 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2082
2083 /* register wait wrappers for display regs */
2084 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
2085         intel_wait_for_register(&(dev_priv_)->uncore, \
2086                                 (reg_), (mask_), (value_), (timeout_))
2087
2088 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({      \
2089         u32 mask__ = (mask_);                                           \
2090         intel_de_wait_for_register((dev_priv_), (reg_),                 \
2091                                    mask__, mask__, (timeout_)); \
2092 })
2093
2094 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
2095         intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_))
2096
2097 /* i915_mm.c */
2098 int remap_io_mapping(struct vm_area_struct *vma,
2099                      unsigned long addr, unsigned long pfn, unsigned long size,
2100                      struct io_mapping *iomap);
2101
2102 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2103 {
2104         if (INTEL_GEN(i915) >= 10)
2105                 return CNL_HWS_CSB_WRITE_INDEX;
2106         else
2107                 return I915_HWS_CSB_WRITE_INDEX;
2108 }
2109
2110 static inline enum i915_map_type
2111 i915_coherent_map_type(struct drm_i915_private *i915)
2112 {
2113         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2114 }
2115
2116 #endif