drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hash.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/mm_types.h>
  44 #include <linux/perf_event.h>
  45 #include <linux/pm_qos.h>
  46 #include <linux/dma-resv.h>
  47 #include <linux/shmem_fs.h>
  48 #include <linux/stackdepot.h>
  49
  50 #include <drm/intel-gtt.h>
  51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  52 #include <drm/drm_gem.h>
  53 #include <drm/drm_auth.h>
  54 #include <drm/drm_cache.h>
  55 #include <drm/drm_util.h>
  56 #include <drm/drm_dsc.h>
  57 #include <drm/drm_atomic.h>
  58 #include <drm/drm_connector.h>
  59 #include <drm/i915_mei_hdcp_interface.h>
  60
  61 #include "i915_fixed.h"
  62 #include "i915_params.h"
  63 #include "i915_reg.h"
  64 #include "i915_utils.h"
  65
  66 #include "display/intel_bios.h"
  67 #include "display/intel_display.h"
  68 #include "display/intel_display_power.h"
  69 #include "display/intel_dpll_mgr.h"
  70 #include "display/intel_dsb.h"
  71 #include "display/intel_frontbuffer.h"
  72 #include "display/intel_gmbus.h"
  73 #include "display/intel_opregion.h"
  74
  75 #include "gem/i915_gem_context_types.h"
  76 #include "gem/i915_gem_shrinker.h"
  77 #include "gem/i915_gem_stolen.h"
  78
  79 #include "gt/intel_lrc.h"
  80 #include "gt/intel_engine.h"
  81 #include "gt/intel_gt_types.h"
  82 #include "gt/intel_workarounds.h"
  83 #include "gt/uc/intel_uc.h"
  84
  85 #include "intel_device_info.h"
  86 #include "intel_pch.h"
  87 #include "intel_runtime_pm.h"
  88 #include "intel_memory_region.h"
  89 #include "intel_uncore.h"
  90 #include "intel_wakeref.h"
  91 #include "intel_wopcm.h"
  92
  93 #include "i915_gem.h"
  94 #include "i915_gem_fence_reg.h"
  95 #include "i915_gem_gtt.h"
  96 #include "i915_gpu_error.h"
  97 #include "i915_perf_types.h"
  98 #include "i915_request.h"
  99 #include "i915_scheduler.h"
 100 #include "gt/intel_timeline.h"
 101 #include "i915_vma.h"
 102 #include "i915_irq.h"
 103
 104 #include "intel_region_lmem.h"
 105
 106 #include "intel_gvt.h"
 107
 108 /* General customization:
 109  */
 110
 111 #define DRIVER_NAME             "i915"
 112 #define DRIVER_DESC             "Intel Graphics"
 113 #define DRIVER_DATE             "20191101"
 114 #define DRIVER_TIMESTAMP        1572604873
 115
 116 struct drm_i915_gem_object;
 117
 118 enum hpd_pin {
 119         HPD_NONE = 0,
 120         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 121         HPD_CRT,
 122         HPD_SDVO_B,
 123         HPD_SDVO_C,
 124         HPD_PORT_A,
 125         HPD_PORT_B,
 126         HPD_PORT_C,
 127         HPD_PORT_D,
 128         HPD_PORT_E,
 129         HPD_PORT_F,
 130         HPD_PORT_G,
 131         HPD_PORT_H,
 132         HPD_PORT_I,
 133
 134         HPD_NUM_PINS
 135 };
 136
 137 #define for_each_hpd_pin(__pin) \
 138         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 139
 140 /* Threshold == 5 for long IRQs, 50 for short */
 141 #define HPD_STORM_DEFAULT_THRESHOLD 50
 142
 143 struct i915_hotplug {
 144         struct delayed_work hotplug_work;
 145
 146         struct {
 147                 unsigned long last_jiffies;
 148                 int count;
 149                 enum {
 150                         HPD_ENABLED = 0,
 151                         HPD_DISABLED = 1,
 152                         HPD_MARK_DISABLED = 2
 153                 } state;
 154         } stats[HPD_NUM_PINS];
 155         u32 event_bits;
 156         u32 retry_bits;
 157         struct delayed_work reenable_work;
 158
 159         u32 long_port_mask;
 160         u32 short_port_mask;
 161         struct work_struct dig_port_work;
 162
 163         struct work_struct poll_init_work;
 164         bool poll_enabled;
 165
 166         unsigned int hpd_storm_threshold;
 167         /* Whether or not to count short HPD IRQs in HPD storms */
 168         u8 hpd_short_storm_enabled;
 169
 170         /*
 171          * if we get a HPD irq from DP and a HPD irq from non-DP
 172          * the non-DP HPD could block the workqueue on a mode config
 173          * mutex getting, that userspace may have taken. However
 174          * userspace is waiting on the DP workqueue to run which is
 175          * blocked behind the non-DP one.
 176          */
 177         struct workqueue_struct *dp_wq;
 178 };
 179
 180 #define I915_GEM_GPU_DOMAINS \
 181         (I915_GEM_DOMAIN_RENDER | \
 182          I915_GEM_DOMAIN_SAMPLER | \
 183          I915_GEM_DOMAIN_COMMAND | \
 184          I915_GEM_DOMAIN_INSTRUCTION | \
 185          I915_GEM_DOMAIN_VERTEX)
 186
 187 struct drm_i915_private;
 188 struct i915_mm_struct;
 189 struct i915_mmu_object;
 190
 191 struct drm_i915_file_private {
 192         struct drm_i915_private *dev_priv;
 193
 194         union {
 195                 struct drm_file *file;
 196                 struct rcu_head rcu;
 197         };
 198
 199         struct {
 200                 spinlock_t lock;
 201                 struct list_head request_list;
 202         } mm;
 203
 204         struct idr context_idr;
 205         struct mutex context_idr_lock; /* guards context_idr */
 206
 207         struct idr vm_idr;
 208         struct mutex vm_idr_lock; /* guards vm_idr */
 209
 210         unsigned int bsd_engine;
 211
 212 /*
 213  * Every context ban increments per client ban score. Also
 214  * hangs in short succession increments ban score. If ban threshold
 215  * is reached, client is considered banned and submitting more work
 216  * will fail. This is a stop gap measure to limit the badly behaving
 217  * clients access to gpu. Note that unbannable contexts never increment
 218  * the client ban score.
 219  */
 220 #define I915_CLIENT_SCORE_HANG_FAST     1
 221 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 222 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 223 #define I915_CLIENT_SCORE_BANNED        9
 224         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 225         atomic_t ban_score;
 226         unsigned long hang_timestamp;
 227 };
 228
 229 /* Interface history:
 230  *
 231  * 1.1: Original.
 232  * 1.2: Add Power Management
 233  * 1.3: Add vblank support
 234  * 1.4: Fix cmdbuffer path, add heap destroy
 235  * 1.5: Add vblank pipe configuration
 236  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 237  *      - Support vertical blank on secondary display pipe
 238  */
 239 #define DRIVER_MAJOR            1
 240 #define DRIVER_MINOR            6
 241 #define DRIVER_PATCHLEVEL       0
 242
 243 struct intel_overlay;
 244 struct intel_overlay_error_state;
 245
 246 struct sdvo_device_mapping {
 247         u8 initialized;
 248         u8 dvo_port;
 249         u8 slave_addr;
 250         u8 dvo_wiring;
 251         u8 i2c_pin;
 252         u8 ddc_pin;
 253 };
 254
 255 struct intel_connector;
 256 struct intel_encoder;
 257 struct intel_atomic_state;
 258 struct intel_crtc_state;
 259 struct intel_initial_plane_config;
 260 struct intel_crtc;
 261 struct intel_limit;
 262 struct dpll;
 263 struct intel_cdclk_state;
 264
 265 struct drm_i915_display_funcs {
 266         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 267                           struct intel_cdclk_state *cdclk_state);
 268         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 269                           const struct intel_cdclk_state *cdclk_state,
 270                           enum pipe pipe);
 271         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 272                              enum i9xx_plane_id i9xx_plane);
 273         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 274         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 275         void (*initial_watermarks)(struct intel_atomic_state *state,
 276                                    struct intel_crtc_state *crtc_state);
 277         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 278                                          struct intel_crtc_state *crtc_state);
 279         void (*optimize_watermarks)(struct intel_atomic_state *state,
 280                                     struct intel_crtc_state *crtc_state);
 281         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 282         void (*update_wm)(struct intel_crtc *crtc);
 283         int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
 284         u8 (*calc_voltage_level)(int cdclk);
 285         /* Returns the active state of the crtc, and if the crtc is active,
 286          * fills out the pipe-config with the hw state. */
 287         bool (*get_pipe_config)(struct intel_crtc *,
 288                                 struct intel_crtc_state *);
 289         void (*get_initial_plane_config)(struct intel_crtc *,
 290                                          struct intel_initial_plane_config *);
 291         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 292                                   struct intel_crtc_state *crtc_state);
 293         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
 294                             struct intel_atomic_state *old_state);
 295         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 296                              struct intel_atomic_state *old_state);
 297         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 298         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 299         void (*audio_codec_enable)(struct intel_encoder *encoder,
 300                                    const struct intel_crtc_state *crtc_state,
 301                                    const struct drm_connector_state *conn_state);
 302         void (*audio_codec_disable)(struct intel_encoder *encoder,
 303                                     const struct intel_crtc_state *old_crtc_state,
 304                                     const struct drm_connector_state *old_conn_state);
 305         void (*fdi_link_train)(struct intel_crtc *crtc,
 306                                const struct intel_crtc_state *crtc_state);
 307         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 308         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 309         /* clock updates for mode set */
 310         /* cursor updates */
 311         /* render clock increase/decrease */
 312         /* display clock increase/decrease */
 313         /* pll clock increase/decrease */
 314
 315         int (*color_check)(struct intel_crtc_state *crtc_state);
 316         /*
 317          * Program double buffered color management registers during
 318          * vblank evasion. The registers should then latch during the
 319          * next vblank start, alongside any other double buffered registers
 320          * involved with the same commit.
 321          */
 322         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 323         /*
 324          * Load LUTs (and other single buffered color management
 325          * registers). Will (hopefully) be called during the vblank
 326          * following the latching of any double buffered registers
 327          * involved with the same commit.
 328          */
 329         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 330         void (*read_luts)(struct intel_crtc_state *crtc_state);
 331 };
 332
 333 struct intel_csr {
 334         struct work_struct work;
 335         const char *fw_path;
 336         u32 required_version;
 337         u32 max_fw_size; /* bytes */
 338         u32 *dmc_payload;
 339         u32 dmc_fw_size; /* dwords */
 340         u32 version;
 341         u32 mmio_count;
 342         i915_reg_t mmioaddr[20];
 343         u32 mmiodata[20];
 344         u32 dc_state;
 345         u32 target_dc_state;
 346         u32 allowed_dc_mask;
 347         intel_wakeref_t wakeref;
 348 };
 349
 350 enum i915_cache_level {
 351         I915_CACHE_NONE = 0,
 352         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 353         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 354                               caches, eg sampler/render caches, and the
 355                               large Last-Level-Cache. LLC is coherent with
 356                               the CPU, but L3 is only visible to the GPU. */
 357         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 358 };
 359
 360 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 361
 362 struct intel_fbc {
 363         /* This is always the inner lock when overlapping with struct_mutex and
 364          * it's the outer lock when overlapping with stolen_lock. */
 365         struct mutex lock;
 366         unsigned threshold;
 367         unsigned int possible_framebuffer_bits;
 368         unsigned int busy_bits;
 369         unsigned int visible_pipes_mask;
 370         struct intel_crtc *crtc;
 371
 372         struct drm_mm_node compressed_fb;
 373         struct drm_mm_node *compressed_llb;
 374
 375         bool false_color;
 376
 377         bool enabled;
 378         bool active;
 379         bool flip_pending;
 380
 381         bool underrun_detected;
 382         struct work_struct underrun_work;
 383
 384         /*
 385          * Due to the atomic rules we can't access some structures without the
 386          * appropriate locking, so we cache information here in order to avoid
 387          * these problems.
 388          */
 389         struct intel_fbc_state_cache {
 390                 struct i915_vma *vma;
 391                 unsigned long flags;
 392
 393                 struct {
 394                         unsigned int mode_flags;
 395                         u32 hsw_bdw_pixel_rate;
 396                 } crtc;
 397
 398                 struct {
 399                         unsigned int rotation;
 400                         int src_w;
 401                         int src_h;
 402                         bool visible;
 403                         /*
 404                          * Display surface base address adjustement for
 405                          * pageflips. Note that on gen4+ this only adjusts up
 406                          * to a tile, offsets within a tile are handled in
 407                          * the hw itself (with the TILEOFF register).
 408                          */
 409                         int adjusted_x;
 410                         int adjusted_y;
 411
 412                         int y;
 413
 414                         u16 pixel_blend_mode;
 415                 } plane;
 416
 417                 struct {
 418                         const struct drm_format_info *format;
 419                         unsigned int stride;
 420                 } fb;
 421         } state_cache;
 422
 423         /*
 424          * This structure contains everything that's relevant to program the
 425          * hardware registers. When we want to figure out if we need to disable
 426          * and re-enable FBC for a new configuration we just check if there's
 427          * something different in the struct. The genx_fbc_activate functions
 428          * are supposed to read from it in order to program the registers.
 429          */
 430         struct intel_fbc_reg_params {
 431                 struct i915_vma *vma;
 432                 unsigned long flags;
 433
 434                 struct {
 435                         enum pipe pipe;
 436                         enum i9xx_plane_id i9xx_plane;
 437                         unsigned int fence_y_offset;
 438                 } crtc;
 439
 440                 struct {
 441                         const struct drm_format_info *format;
 442                         unsigned int stride;
 443                 } fb;
 444
 445                 int cfb_size;
 446                 unsigned int gen9_wa_cfb_stride;
 447         } params;
 448
 449         const char *no_fbc_reason;
 450 };
 451
 452 /*
 453  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 454  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 455  * parsing for same resolution.
 456  */
 457 enum drrs_refresh_rate_type {
 458         DRRS_HIGH_RR,
 459         DRRS_LOW_RR,
 460         DRRS_MAX_RR, /* RR count */
 461 };
 462
 463 enum drrs_support_type {
 464         DRRS_NOT_SUPPORTED = 0,
 465         STATIC_DRRS_SUPPORT = 1,
 466         SEAMLESS_DRRS_SUPPORT = 2
 467 };
 468
 469 struct intel_dp;
 470 struct i915_drrs {
 471         struct mutex mutex;
 472         struct delayed_work work;
 473         struct intel_dp *dp;
 474         unsigned busy_frontbuffer_bits;
 475         enum drrs_refresh_rate_type refresh_rate_type;
 476         enum drrs_support_type type;
 477 };
 478
 479 struct i915_psr {
 480         struct mutex lock;
 481
 482 #define I915_PSR_DEBUG_MODE_MASK        0x0f
 483 #define I915_PSR_DEBUG_DEFAULT          0x00
 484 #define I915_PSR_DEBUG_DISABLE          0x01
 485 #define I915_PSR_DEBUG_ENABLE           0x02
 486 #define I915_PSR_DEBUG_FORCE_PSR1       0x03
 487 #define I915_PSR_DEBUG_IRQ              0x10
 488
 489         u32 debug;
 490         bool sink_support;
 491         bool enabled;
 492         struct intel_dp *dp;
 493         enum pipe pipe;
 494         enum transcoder transcoder;
 495         bool active;
 496         struct work_struct work;
 497         unsigned busy_frontbuffer_bits;
 498         bool sink_psr2_support;
 499         bool link_standby;
 500         bool colorimetry_support;
 501         bool psr2_enabled;
 502         u8 sink_sync_latency;
 503         ktime_t last_entry_attempt;
 504         ktime_t last_exit;
 505         bool sink_not_reliable;
 506         bool irq_aux_error;
 507         u16 su_x_granularity;
 508         bool dc3co_enabled;
 509         u32 dc3co_exit_delay;
 510         struct delayed_work idle_work;
 511 };
 512
 513 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 514 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 515 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 516 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 517 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 518 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 519
 520 struct intel_fbdev;
 521 struct intel_fbc_work;
 522
 523 struct intel_gmbus {
 524         struct i2c_adapter adapter;
 525 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 526         u32 force_bit;
 527         u32 reg0;
 528         i915_reg_t gpio_reg;
 529         struct i2c_algo_bit_data bit_algo;
 530         struct drm_i915_private *dev_priv;
 531 };
 532
 533 struct i915_suspend_saved_registers {
 534         u32 saveDSPARB;
 535         u32 saveFBC_CONTROL;
 536         u32 saveCACHE_MODE_0;
 537         u32 saveMI_ARB_STATE;
 538         u32 saveSWF0[16];
 539         u32 saveSWF1[16];
 540         u32 saveSWF3[3];
 541         u64 saveFENCE[I915_MAX_NUM_FENCES];
 542         u32 savePCH_PORT_HOTPLUG;
 543         u16 saveGCDGMBUS;
 544 };
 545
 546 struct vlv_s0ix_state;
 547
 548 #define MAX_L3_SLICES 2
 549 struct intel_l3_parity {
 550         u32 *remap_info[MAX_L3_SLICES];
 551         struct work_struct error_work;
 552         int which_slice;
 553 };
 554
 555 struct i915_gem_mm {
 556         /** Memory allocator for GTT stolen memory */
 557         struct drm_mm stolen;
 558         /** Protects the usage of the GTT stolen memory allocator. This is
 559          * always the inner lock when overlapping with struct_mutex. */
 560         struct mutex stolen_lock;
 561
 562         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 563         spinlock_t obj_lock;
 564
 565         /**
 566          * List of objects which are purgeable.
 567          */
 568         struct list_head purge_list;
 569
 570         /**
 571          * List of objects which have allocated pages and are shrinkable.
 572          */
 573         struct list_head shrink_list;
 574
 575         /**
 576          * List of objects which are pending destruction.
 577          */
 578         struct llist_head free_list;
 579         struct work_struct free_work;
 580         /**
 581          * Count of objects pending destructions. Used to skip needlessly
 582          * waiting on an RCU barrier if no objects are waiting to be freed.
 583          */
 584         atomic_t free_count;
 585
 586         /**
 587          * Small stash of WC pages
 588          */
 589         struct pagestash wc_stash;
 590
 591         /**
 592          * tmpfs instance used for shmem backed objects
 593          */
 594         struct vfsmount *gemfs;
 595
 596         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 597
 598         struct notifier_block oom_notifier;
 599         struct notifier_block vmap_notifier;
 600         struct shrinker shrinker;
 601
 602         /**
 603          * Workqueue to fault in userptr pages, flushed by the execbuf
 604          * when required but otherwise left to userspace to try again
 605          * on EAGAIN.
 606          */
 607         struct workqueue_struct *userptr_wq;
 608
 609         /* shrinker accounting, also useful for userland debugging */
 610         u64 shrink_memory;
 611         u32 shrink_count;
 612 };
 613
 614 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 615
 616 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
 617 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
 618
 619 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
 620 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
 621
 622 #define I915_ENGINE_WEDGED_TIMEOUT  (60 * HZ)  /* Reset but no recovery? */
 623
 624 struct ddi_vbt_port_info {
 625         /* Non-NULL if port present. */
 626         const struct child_device_config *child;
 627
 628         int max_tmds_clock;
 629
 630         /* This is an index in the HDMI/DVI DDI buffer translation table. */
 631         u8 hdmi_level_shift;
 632         u8 hdmi_level_shift_set:1;
 633
 634         u8 supports_dvi:1;
 635         u8 supports_hdmi:1;
 636         u8 supports_dp:1;
 637         u8 supports_edp:1;
 638         u8 supports_typec_usb:1;
 639         u8 supports_tbt:1;
 640
 641         u8 alternate_aux_channel;
 642         u8 alternate_ddc_pin;
 643
 644         u8 dp_boost_level;
 645         u8 hdmi_boost_level;
 646         int dp_max_link_rate;           /* 0 for not limited by VBT */
 647 };
 648
 649 enum psr_lines_to_wait {
 650         PSR_0_LINES_TO_WAIT = 0,
 651         PSR_1_LINE_TO_WAIT,
 652         PSR_4_LINES_TO_WAIT,
 653         PSR_8_LINES_TO_WAIT
 654 };
 655
 656 struct intel_vbt_data {
 657         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 658         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 659
 660         /* Feature bits */
 661         unsigned int int_tv_support:1;
 662         unsigned int lvds_dither:1;
 663         unsigned int int_crt_support:1;
 664         unsigned int lvds_use_ssc:1;
 665         unsigned int int_lvds_support:1;
 666         unsigned int display_clock_mode:1;
 667         unsigned int fdi_rx_polarity_inverted:1;
 668         unsigned int panel_type:4;
 669         int lvds_ssc_freq;
 670         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 671         enum drm_panel_orientation orientation;
 672
 673         enum drrs_support_type drrs_type;
 674
 675         struct {
 676                 int rate;
 677                 int lanes;
 678                 int preemphasis;
 679                 int vswing;
 680                 bool low_vswing;
 681                 bool initialized;
 682                 int bpp;
 683                 struct edp_power_seq pps;
 684         } edp;
 685
 686         struct {
 687                 bool enable;
 688                 bool full_link;
 689                 bool require_aux_wakeup;
 690                 int idle_frames;
 691                 enum psr_lines_to_wait lines_to_wait;
 692                 int tp1_wakeup_time_us;
 693                 int tp2_tp3_wakeup_time_us;
 694                 int psr2_tp2_tp3_wakeup_time_us;
 695         } psr;
 696
 697         struct {
 698                 u16 pwm_freq_hz;
 699                 bool present;
 700                 bool active_low_pwm;
 701                 u8 min_brightness;      /* min_brightness/255 of max */
 702                 u8 controller;          /* brightness controller number */
 703                 enum intel_backlight_type type;
 704         } backlight;
 705
 706         /* MIPI DSI */
 707         struct {
 708                 u16 panel_id;
 709                 struct mipi_config *config;
 710                 struct mipi_pps_data *pps;
 711                 u16 bl_ports;
 712                 u16 cabc_ports;
 713                 u8 seq_version;
 714                 u32 size;
 715                 u8 *data;
 716                 const u8 *sequence[MIPI_SEQ_MAX];
 717                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 718                 enum drm_panel_orientation orientation;
 719         } dsi;
 720
 721         int crt_ddc_pin;
 722
 723         struct list_head display_devices;
 724
 725         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 726         struct sdvo_device_mapping sdvo_mappings[2];
 727 };
 728
 729 enum intel_ddb_partitioning {
 730         INTEL_DDB_PART_1_2,
 731         INTEL_DDB_PART_5_6, /* IVB+ */
 732 };
 733
 734 struct intel_wm_level {
 735         bool enable;
 736         u32 pri_val;
 737         u32 spr_val;
 738         u32 cur_val;
 739         u32 fbc_val;
 740 };
 741
 742 struct ilk_wm_values {
 743         u32 wm_pipe[3];
 744         u32 wm_lp[3];
 745         u32 wm_lp_spr[3];
 746         u32 wm_linetime[3];
 747         bool enable_fbc_wm;
 748         enum intel_ddb_partitioning partitioning;
 749 };
 750
 751 struct g4x_pipe_wm {
 752         u16 plane[I915_MAX_PLANES];
 753         u16 fbc;
 754 };
 755
 756 struct g4x_sr_wm {
 757         u16 plane;
 758         u16 cursor;
 759         u16 fbc;
 760 };
 761
 762 struct vlv_wm_ddl_values {
 763         u8 plane[I915_MAX_PLANES];
 764 };
 765
 766 struct vlv_wm_values {
 767         struct g4x_pipe_wm pipe[3];
 768         struct g4x_sr_wm sr;
 769         struct vlv_wm_ddl_values ddl[3];
 770         u8 level;
 771         bool cxsr;
 772 };
 773
 774 struct g4x_wm_values {
 775         struct g4x_pipe_wm pipe[2];
 776         struct g4x_sr_wm sr;
 777         struct g4x_sr_wm hpll;
 778         bool cxsr;
 779         bool hpll_en;
 780         bool fbc_en;
 781 };
 782
 783 struct skl_ddb_entry {
 784         u16 start, end; /* in number of blocks, 'end' is exclusive */
 785 };
 786
 787 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 788 {
 789         return entry->end - entry->start;
 790 }
 791
 792 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 793                                        const struct skl_ddb_entry *e2)
 794 {
 795         if (e1->start == e2->start && e1->end == e2->end)
 796                 return true;
 797
 798         return false;
 799 }
 800
 801 struct skl_ddb_allocation {
 802         u8 enabled_slices; /* GEN11 has configurable 2 slices */
 803 };
 804
 805 struct skl_ddb_values {
 806         unsigned dirty_pipes;
 807         struct skl_ddb_allocation ddb;
 808 };
 809
 810 struct skl_wm_level {
 811         u16 min_ddb_alloc;
 812         u16 plane_res_b;
 813         u8 plane_res_l;
 814         bool plane_en;
 815         bool ignore_lines;
 816 };
 817
 818 /* Stores plane specific WM parameters */
 819 struct skl_wm_params {
 820         bool x_tiled, y_tiled;
 821         bool rc_surface;
 822         bool is_planar;
 823         u32 width;
 824         u8 cpp;
 825         u32 plane_pixel_rate;
 826         u32 y_min_scanlines;
 827         u32 plane_bytes_per_line;
 828         uint_fixed_16_16_t plane_blocks_per_line;
 829         uint_fixed_16_16_t y_tile_minimum;
 830         u32 linetime_us;
 831         u32 dbuf_block_size;
 832 };
 833
 834 enum intel_pipe_crc_source {
 835         INTEL_PIPE_CRC_SOURCE_NONE,
 836         INTEL_PIPE_CRC_SOURCE_PLANE1,
 837         INTEL_PIPE_CRC_SOURCE_PLANE2,
 838         INTEL_PIPE_CRC_SOURCE_PLANE3,
 839         INTEL_PIPE_CRC_SOURCE_PLANE4,
 840         INTEL_PIPE_CRC_SOURCE_PLANE5,
 841         INTEL_PIPE_CRC_SOURCE_PLANE6,
 842         INTEL_PIPE_CRC_SOURCE_PLANE7,
 843         INTEL_PIPE_CRC_SOURCE_PIPE,
 844         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
 845         INTEL_PIPE_CRC_SOURCE_TV,
 846         INTEL_PIPE_CRC_SOURCE_DP_B,
 847         INTEL_PIPE_CRC_SOURCE_DP_C,
 848         INTEL_PIPE_CRC_SOURCE_DP_D,
 849         INTEL_PIPE_CRC_SOURCE_AUTO,
 850         INTEL_PIPE_CRC_SOURCE_MAX,
 851 };
 852
 853 #define INTEL_PIPE_CRC_ENTRIES_NR       128
 854 struct intel_pipe_crc {
 855         spinlock_t lock;
 856         int skipped;
 857         enum intel_pipe_crc_source source;
 858 };
 859
 860 struct i915_frontbuffer_tracking {
 861         spinlock_t lock;
 862
 863         /*
 864          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 865          * scheduled flips.
 866          */
 867         unsigned busy_bits;
 868         unsigned flip_bits;
 869 };
 870
 871 struct i915_virtual_gpu {
 872         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 873         bool active;
 874         u32 caps;
 875 };
 876
 877 /* used in computing the new watermarks state */
 878 struct intel_wm_config {
 879         unsigned int num_pipes_active;
 880         bool sprites_enabled;
 881         bool sprites_scaled;
 882 };
 883
 884 struct intel_cdclk_state {
 885         unsigned int cdclk, vco, ref, bypass;
 886         u8 voltage_level;
 887 };
 888
 889 struct i915_selftest_stash {
 890         atomic_t counter;
 891 };
 892
 893 struct drm_i915_private {
 894         struct drm_device drm;
 895
 896         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 897         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 898         struct intel_driver_caps caps;
 899
 900         /**
 901          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 902          * end of stolen which we can optionally use to create GEM objects
 903          * backed by stolen memory. Note that stolen_usable_size tells us
 904          * exactly how much of this we are actually allowed to use, given that
 905          * some portion of it is in fact reserved for use by hardware functions.
 906          */
 907         struct resource dsm;
 908         /**
 909          * Reseved portion of Data Stolen Memory
 910          */
 911         struct resource dsm_reserved;
 912
 913         /*
 914          * Stolen memory is segmented in hardware with different portions
 915          * offlimits to certain functions.
 916          *
 917          * The drm_mm is initialised to the total accessible range, as found
 918          * from the PCI config. On Broadwell+, this is further restricted to
 919          * avoid the first page! The upper end of stolen memory is reserved for
 920          * hardware functions and similarly removed from the accessible range.
 921          */
 922         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 923
 924         struct intel_uncore uncore;
 925         struct intel_uncore_mmio_debug mmio_debug;
 926
 927         struct i915_virtual_gpu vgpu;
 928
 929         struct intel_gvt *gvt;
 930
 931         struct intel_wopcm wopcm;
 932
 933         struct intel_csr csr;
 934
 935         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 936
 937         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 938          * controller on different i2c buses. */
 939         struct mutex gmbus_mutex;
 940
 941         /**
 942          * Base address of where the gmbus and gpio blocks are located (either
 943          * on PCH or on SoC for platforms without PCH).
 944          */
 945         u32 gpio_mmio_base;
 946
 947         u32 hsw_psr_mmio_adjust;
 948
 949         /* MMIO base address for MIPI regs */
 950         u32 mipi_mmio_base;
 951
 952         u32 pps_mmio_base;
 953
 954         wait_queue_head_t gmbus_wait_queue;
 955
 956         struct pci_dev *bridge_dev;
 957
 958         /* Context used internally to idle the GPU and setup initial state */
 959         struct i915_gem_context *kernel_context;
 960
 961         struct intel_engine_cs *engine[I915_NUM_ENGINES];
 962         struct rb_root uabi_engines;
 963
 964         struct resource mch_res;
 965
 966         /* protects the irq masks */
 967         spinlock_t irq_lock;
 968
 969         bool display_irqs_enabled;
 970
 971         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
 972         struct pm_qos_request pm_qos;
 973
 974         /* Sideband mailbox protection */
 975         struct mutex sb_lock;
 976         struct pm_qos_request sb_qos;
 977
 978         /** Cached value of IMR to avoid reads in updating the bitfield */
 979         union {
 980                 u32 irq_mask;
 981                 u32 de_irq_mask[I915_MAX_PIPES];
 982         };
 983         u32 pipestat_irq_mask[I915_MAX_PIPES];
 984
 985         struct i915_hotplug hotplug;
 986         struct intel_fbc fbc;
 987         struct i915_drrs drrs;
 988         struct intel_opregion opregion;
 989         struct intel_vbt_data vbt;
 990
 991         bool preserve_bios_swizzle;
 992
 993         /* overlay */
 994         struct intel_overlay *overlay;
 995
 996         /* backlight registers and fields in struct intel_panel */
 997         struct mutex backlight_lock;
 998
 999         /* protects panel power sequencer state */
1000         struct mutex pps_mutex;
1001
1002         unsigned int fsb_freq, mem_freq, is_ddr3;
1003         unsigned int skl_preferred_vco_freq;
1004         unsigned int max_cdclk_freq;
1005
1006         unsigned int max_dotclk_freq;
1007         unsigned int rawclk_freq;
1008         unsigned int hpll_freq;
1009         unsigned int fdi_pll_freq;
1010         unsigned int czclk_freq;
1011
1012         /*
1013          * For reading holding any crtc lock is sufficient,
1014          * for writing must hold all of them.
1015          */
1016         struct {
1017                 /*
1018                  * The current logical cdclk state.
1019                  * See intel_atomic_state.cdclk.logical
1020                  */
1021                 struct intel_cdclk_state logical;
1022                 /*
1023                  * The current actual cdclk state.
1024                  * See intel_atomic_state.cdclk.actual
1025                  */
1026                 struct intel_cdclk_state actual;
1027                 /* The current hardware cdclk state */
1028                 struct intel_cdclk_state hw;
1029
1030                 /* cdclk, divider, and ratio table from bspec */
1031                 const struct intel_cdclk_vals *table;
1032
1033                 int force_min_cdclk;
1034         } cdclk;
1035
1036         /**
1037          * wq - Driver workqueue for GEM.
1038          *
1039          * NOTE: Work items scheduled here are not allowed to grab any modeset
1040          * locks, for otherwise the flushing done in the pageflip code will
1041          * result in deadlocks.
1042          */
1043         struct workqueue_struct *wq;
1044
1045         /* ordered wq for modesets */
1046         struct workqueue_struct *modeset_wq;
1047         /* unbound hipri wq for page flips/plane updates */
1048         struct workqueue_struct *flip_wq;
1049
1050         /* Display functions */
1051         struct drm_i915_display_funcs display;
1052
1053         /* PCH chipset type */
1054         enum intel_pch pch_type;
1055         unsigned short pch_id;
1056
1057         unsigned long quirks;
1058
1059         struct drm_atomic_state *modeset_restore_state;
1060         struct drm_modeset_acquire_ctx reset_ctx;
1061
1062         struct i915_ggtt ggtt; /* VM representing the global address space */
1063
1064         struct i915_gem_mm mm;
1065         DECLARE_HASHTABLE(mm_structs, 7);
1066         struct mutex mm_lock;
1067
1068         /* Kernel Modesetting */
1069
1070         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1071         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1072
1073 #ifdef CONFIG_DEBUG_FS
1074         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1075 #endif
1076
1077         /* dpll and cdclk state is protected by connection_mutex */
1078         int num_shared_dpll;
1079         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1080         const struct intel_dpll_mgr *dpll_mgr;
1081
1082         /*
1083          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1084          * Must be global rather than per dpll, because on some platforms
1085          * plls share registers.
1086          */
1087         struct mutex dpll_lock;
1088
1089         /*
1090          * For reading active_pipes, min_cdclk, min_voltage_level holding
1091          * any crtc lock is sufficient, for writing must hold all of them.
1092          */
1093         u8 active_pipes;
1094         /* minimum acceptable cdclk for each pipe */
1095         int min_cdclk[I915_MAX_PIPES];
1096         /* minimum acceptable voltage level for each pipe */
1097         u8 min_voltage_level[I915_MAX_PIPES];
1098
1099         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1100
1101         struct i915_wa_list gt_wa_list;
1102
1103         struct i915_frontbuffer_tracking fb_tracking;
1104
1105         struct intel_atomic_helper {
1106                 struct llist_head free_list;
1107                 struct work_struct free_work;
1108         } atomic_helper;
1109
1110         u16 orig_clock;
1111
1112         bool mchbar_need_disable;
1113
1114         struct intel_l3_parity l3_parity;
1115
1116         /*
1117          * edram size in MB.
1118          * Cannot be determined by PCIID. You must always read a register.
1119          */
1120         u32 edram_size_mb;
1121
1122         struct i915_power_domains power_domains;
1123
1124         struct i915_psr psr;
1125
1126         struct i915_gpu_error gpu_error;
1127
1128         struct drm_i915_gem_object *vlv_pctx;
1129
1130         /* list of fbdev register on this device */
1131         struct intel_fbdev *fbdev;
1132         struct work_struct fbdev_suspend_work;
1133
1134         struct drm_property *broadcast_rgb_property;
1135         struct drm_property *force_audio_property;
1136
1137         /* hda/i915 audio component */
1138         struct i915_audio_component *audio_component;
1139         bool audio_component_registered;
1140         /**
1141          * av_mutex - mutex for audio/video sync
1142          *
1143          */
1144         struct mutex av_mutex;
1145         int audio_power_refcount;
1146         u32 audio_freq_cntrl;
1147
1148         u32 fdi_rx_config;
1149
1150         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1151         u32 chv_phy_control;
1152         /*
1153          * Shadows for CHV DPLL_MD regs to keep the state
1154          * checker somewhat working in the presence hardware
1155          * crappiness (can't read out DPLL_MD for pipes B & C).
1156          */
1157         u32 chv_dpll_md[I915_MAX_PIPES];
1158         u32 bxt_phy_grc;
1159
1160         u32 suspend_count;
1161         bool power_domains_suspended;
1162         struct i915_suspend_saved_registers regfile;
1163         struct vlv_s0ix_state *vlv_s0ix_state;
1164
1165         enum {
1166                 I915_SAGV_UNKNOWN = 0,
1167                 I915_SAGV_DISABLED,
1168                 I915_SAGV_ENABLED,
1169                 I915_SAGV_NOT_CONTROLLED
1170         } sagv_status;
1171
1172         u32 sagv_block_time_us;
1173
1174         struct {
1175                 /*
1176                  * Raw watermark latency values:
1177                  * in 0.1us units for WM0,
1178                  * in 0.5us units for WM1+.
1179                  */
1180                 /* primary */
1181                 u16 pri_latency[5];
1182                 /* sprite */
1183                 u16 spr_latency[5];
1184                 /* cursor */
1185                 u16 cur_latency[5];
1186                 /*
1187                  * Raw watermark memory latency values
1188                  * for SKL for all 8 levels
1189                  * in 1us units.
1190                  */
1191                 u16 skl_latency[8];
1192
1193                 /* current hardware state */
1194                 union {
1195                         struct ilk_wm_values hw;
1196                         struct skl_ddb_values skl_hw;
1197                         struct vlv_wm_values vlv;
1198                         struct g4x_wm_values g4x;
1199                 };
1200
1201                 u8 max_level;
1202
1203                 /*
1204                  * Should be held around atomic WM register writing; also
1205                  * protects * intel_crtc->wm.active and
1206                  * crtc_state->wm.need_postvbl_update.
1207                  */
1208                 struct mutex wm_mutex;
1209
1210                 /*
1211                  * Set during HW readout of watermarks/DDB.  Some platforms
1212                  * need to know when we're still using BIOS-provided values
1213                  * (which we don't fully trust).
1214                  */
1215                 bool distrust_bios_wm;
1216         } wm;
1217
1218         struct dram_info {
1219                 bool valid;
1220                 bool is_16gb_dimm;
1221                 u8 num_channels;
1222                 u8 ranks;
1223                 u32 bandwidth_kbps;
1224                 bool symmetric_memory;
1225                 enum intel_dram_type {
1226                         INTEL_DRAM_UNKNOWN,
1227                         INTEL_DRAM_DDR3,
1228                         INTEL_DRAM_DDR4,
1229                         INTEL_DRAM_LPDDR3,
1230                         INTEL_DRAM_LPDDR4
1231                 } type;
1232         } dram_info;
1233
1234         struct intel_bw_info {
1235                 unsigned int deratedbw[3]; /* for each QGV point */
1236                 u8 num_qgv_points;
1237                 u8 num_planes;
1238         } max_bw[6];
1239
1240         struct drm_private_obj bw_obj;
1241
1242         struct intel_runtime_pm runtime_pm;
1243
1244         struct i915_perf perf;
1245
1246         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1247         struct intel_gt gt;
1248
1249         struct {
1250                 struct i915_gem_contexts {
1251                         spinlock_t lock; /* locks list */
1252                         struct list_head list;
1253
1254                         struct llist_head free_list;
1255                         struct work_struct free_work;
1256                 } contexts;
1257         } gem;
1258
1259         u8 pch_ssc_use;
1260
1261         /* For i915gm/i945gm vblank irq workaround */
1262         u8 vblank_enabled;
1263
1264         /* perform PHY state sanity checks? */
1265         bool chv_phy_assert[2];
1266
1267         bool ipc_enabled;
1268
1269         /* Used to save the pipe-to-encoder mapping for audio */
1270         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1271
1272         /* necessary resource sharing with HDMI LPE audio driver. */
1273         struct {
1274                 struct platform_device *platdev;
1275                 int     irq;
1276         } lpe_audio;
1277
1278         struct i915_pmu pmu;
1279
1280         struct i915_hdcp_comp_master *hdcp_master;
1281         bool hdcp_comp_added;
1282
1283         /* Mutex to protect the above hdcp component related values. */
1284         struct mutex hdcp_comp_mutex;
1285
1286         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1287
1288         /*
1289          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1290          * will be rejected. Instead look for a better place.
1291          */
1292 };
1293
1294 struct dram_dimm_info {
1295         u8 size, width, ranks;
1296 };
1297
1298 struct dram_channel_info {
1299         struct dram_dimm_info dimm_l, dimm_s;
1300         u8 ranks;
1301         bool is_16gb_dimm;
1302 };
1303
1304 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1305 {
1306         return container_of(dev, struct drm_i915_private, drm);
1307 }
1308
1309 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1310 {
1311         return dev_get_drvdata(kdev);
1312 }
1313
1314 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1315 {
1316         return pci_get_drvdata(pdev);
1317 }
1318
1319 /* Simple iterator over all initialised engines */
1320 #define for_each_engine(engine__, dev_priv__, id__) \
1321         for ((id__) = 0; \
1322              (id__) < I915_NUM_ENGINES; \
1323              (id__)++) \
1324                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1325
1326 /* Iterator over subset of engines selected by mask */
1327 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1328         for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1329              (tmp__) ? \
1330              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1331              0;)
1332
1333 #define rb_to_uabi_engine(rb) \
1334         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1335
1336 #define for_each_uabi_engine(engine__, i915__) \
1337         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1338              (engine__); \
1339              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1340
1341 #define I915_GTT_OFFSET_NONE ((u32)-1)
1342
1343 /*
1344  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1345  * considered to be the frontbuffer for the given plane interface-wise. This
1346  * doesn't mean that the hw necessarily already scans it out, but that any
1347  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1348  *
1349  * We have one bit per pipe and per scanout plane type.
1350  */
1351 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1352 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1353         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1354         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1355         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1356 })
1357 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1358         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1359 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1360         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1361                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1362
1363 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1364 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1365 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1366
1367 #define INTEL_GEN(dev_priv)     (INTEL_INFO(dev_priv)->gen)
1368 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1369
1370 #define REVID_FOREVER           0xff
1371 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
1372
1373 #define INTEL_GEN_MASK(s, e) ( \
1374         BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1375         BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1376         GENMASK((e) - 1, (s) - 1))
1377
1378 /* Returns true if Gen is in inclusive range [Start, End] */
1379 #define IS_GEN_RANGE(dev_priv, s, e) \
1380         (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1381
1382 #define IS_GEN(dev_priv, n) \
1383         (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1384          INTEL_INFO(dev_priv)->gen == (n))
1385
1386 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1387
1388 /*
1389  * Return true if revision is in range [since,until] inclusive.
1390  *
1391  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1392  */
1393 #define IS_REVID(p, since, until) \
1394         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1395
1396 static __always_inline unsigned int
1397 __platform_mask_index(const struct intel_runtime_info *info,
1398                       enum intel_platform p)
1399 {
1400         const unsigned int pbits =
1401                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1402
1403         /* Expand the platform_mask array if this fails. */
1404         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1405                      pbits * ARRAY_SIZE(info->platform_mask));
1406
1407         return p / pbits;
1408 }
1409
1410 static __always_inline unsigned int
1411 __platform_mask_bit(const struct intel_runtime_info *info,
1412                     enum intel_platform p)
1413 {
1414         const unsigned int pbits =
1415                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1416
1417         return p % pbits + INTEL_SUBPLATFORM_BITS;
1418 }
1419
1420 static inline u32
1421 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1422 {
1423         const unsigned int pi = __platform_mask_index(info, p);
1424
1425         return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1426 }
1427
1428 static __always_inline bool
1429 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1430 {
1431         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1432         const unsigned int pi = __platform_mask_index(info, p);
1433         const unsigned int pb = __platform_mask_bit(info, p);
1434
1435         BUILD_BUG_ON(!__builtin_constant_p(p));
1436
1437         return info->platform_mask[pi] & BIT(pb);
1438 }
1439
1440 static __always_inline bool
1441 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1442                enum intel_platform p, unsigned int s)
1443 {
1444         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1445         const unsigned int pi = __platform_mask_index(info, p);
1446         const unsigned int pb = __platform_mask_bit(info, p);
1447         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1448         const u32 mask = info->platform_mask[pi];
1449
1450         BUILD_BUG_ON(!__builtin_constant_p(p));
1451         BUILD_BUG_ON(!__builtin_constant_p(s));
1452         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1453
1454         /* Shift and test on the MSB position so sign flag can be used. */
1455         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1456 }
1457
1458 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1459 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1460
1461 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1462 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1463 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1464 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1465 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1466 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1467 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1468 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1469 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1470 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1471 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1472 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1473 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1474 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1475 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1476 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1477 #define IS_IRONLAKE_M(dev_priv) \
1478         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1479 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1480 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1481                                  INTEL_INFO(dev_priv)->gt == 1)
1482 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1483 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1484 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1485 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1486 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1487 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1488 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1489 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1490 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1491 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1492 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1493 #define IS_ELKHARTLAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1494 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1495 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1496                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1497 #define IS_BDW_ULT(dev_priv) \
1498         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1499 #define IS_BDW_ULX(dev_priv) \
1500         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1501 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1502                                  INTEL_INFO(dev_priv)->gt == 3)
1503 #define IS_HSW_ULT(dev_priv) \
1504         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1505 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1506                                  INTEL_INFO(dev_priv)->gt == 3)
1507 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1508                                  INTEL_INFO(dev_priv)->gt == 1)
1509 /* ULX machines are also considered ULT. */
1510 #define IS_HSW_ULX(dev_priv) \
1511         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1512 #define IS_SKL_ULT(dev_priv) \
1513         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1514 #define IS_SKL_ULX(dev_priv) \
1515         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1516 #define IS_KBL_ULT(dev_priv) \
1517         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1518 #define IS_KBL_ULX(dev_priv) \
1519         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1520 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1521                                  INTEL_INFO(dev_priv)->gt == 2)
1522 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1523                                  INTEL_INFO(dev_priv)->gt == 3)
1524 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1525                                  INTEL_INFO(dev_priv)->gt == 4)
1526 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1527                                  INTEL_INFO(dev_priv)->gt == 2)
1528 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1529                                  INTEL_INFO(dev_priv)->gt == 3)
1530 #define IS_CFL_ULT(dev_priv) \
1531         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1532 #define IS_CFL_ULX(dev_priv) \
1533         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1534 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1535                                  INTEL_INFO(dev_priv)->gt == 2)
1536 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1537                                  INTEL_INFO(dev_priv)->gt == 3)
1538 #define IS_CNL_WITH_PORT_F(dev_priv) \
1539         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1540 #define IS_ICL_WITH_PORT_F(dev_priv) \
1541         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1542
1543 #define SKL_REVID_A0            0x0
1544 #define SKL_REVID_B0            0x1
1545 #define SKL_REVID_C0            0x2
1546 #define SKL_REVID_D0            0x3
1547 #define SKL_REVID_E0            0x4
1548 #define SKL_REVID_F0            0x5
1549 #define SKL_REVID_G0            0x6
1550 #define SKL_REVID_H0            0x7
1551
1552 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1553
1554 #define BXT_REVID_A0            0x0
1555 #define BXT_REVID_A1            0x1
1556 #define BXT_REVID_B0            0x3
1557 #define BXT_REVID_B_LAST        0x8
1558 #define BXT_REVID_C0            0x9
1559
1560 #define IS_BXT_REVID(dev_priv, since, until) \
1561         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1562
1563 #define KBL_REVID_A0            0x0
1564 #define KBL_REVID_B0            0x1
1565 #define KBL_REVID_C0            0x2
1566 #define KBL_REVID_D0            0x3
1567 #define KBL_REVID_E0            0x4
1568
1569 #define IS_KBL_REVID(dev_priv, since, until) \
1570         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1571
1572 #define GLK_REVID_A0            0x0
1573 #define GLK_REVID_A1            0x1
1574
1575 #define IS_GLK_REVID(dev_priv, since, until) \
1576         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1577
1578 #define CNL_REVID_A0            0x0
1579 #define CNL_REVID_B0            0x1
1580 #define CNL_REVID_C0            0x2
1581
1582 #define IS_CNL_REVID(p, since, until) \
1583         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1584
1585 #define ICL_REVID_A0            0x0
1586 #define ICL_REVID_A2            0x1
1587 #define ICL_REVID_B0            0x3
1588 #define ICL_REVID_B2            0x4
1589 #define ICL_REVID_C0            0x5
1590
1591 #define IS_ICL_REVID(p, since, until) \
1592         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1593
1594 #define TGL_REVID_A0            0x0
1595
1596 #define IS_TGL_REVID(p, since, until) \
1597         (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1598
1599 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1600 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1601 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1602
1603 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1604
1605 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({                \
1606         unsigned int first__ = (first);                                 \
1607         unsigned int count__ = (count);                                 \
1608         (INTEL_INFO(dev_priv)->engine_mask &                            \
1609          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1610 })
1611 #define VDBOX_MASK(dev_priv) \
1612         ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1613 #define VEBOX_MASK(dev_priv) \
1614         ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1615
1616 /*
1617  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1618  * All later gens can run the final buffer from the ppgtt
1619  */
1620 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1621
1622 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1623 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1624 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1625 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1626 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
1627                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1628
1629 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1630
1631 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1632                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1633 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1634                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1635 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1636                 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1637
1638 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1639
1640 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1641 #define HAS_PPGTT(dev_priv) \
1642         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1643 #define HAS_FULL_PPGTT(dev_priv) \
1644         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1645
1646 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1647         GEM_BUG_ON((sizes) == 0); \
1648         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1649 })
1650
1651 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1652 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1653                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1654
1655 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1656 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1657
1658 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
1659         (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1660
1661 /* WaRsDisableCoarsePowerGating:skl,cnl */
1662 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1663         (IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9))
1664
1665 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1666 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1667                                         IS_GEMINILAKE(dev_priv) || \
1668                                         IS_KABYLAKE(dev_priv))
1669
1670 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1671  * rows, which changed the alignment requirements and fence programming.
1672  */
1673 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1674                                          !(IS_I915G(dev_priv) || \
1675                                          IS_I915GM(dev_priv)))
1676 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1677 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1678
1679 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1680 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1681 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1682
1683 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1684
1685 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1686
1687 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1688 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1689 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1690 #define HAS_TRANSCODER_EDP(dev_priv)     (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
1691
1692 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1693 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1694 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1695
1696 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1697
1698 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
1699
1700 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1701 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1702
1703 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1704
1705 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1706 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1707
1708 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1709
1710 /* Having GuC is not the same as using GuC */
1711 #define USES_GUC(dev_priv)              intel_uc_uses_guc(&(dev_priv)->gt.uc)
1712 #define USES_GUC_SUBMISSION(dev_priv)   intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
1713
1714 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1715
1716 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1717
1718
1719 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1720
1721 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1722
1723 /* DPF == dynamic parity feature */
1724 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1725 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1726                                  2 : HAS_L3_DPF(dev_priv))
1727
1728 #define GT_FREQUENCY_MULTIPLIER 50
1729 #define GEN9_FREQ_SCALER 3
1730
1731 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1732
1733 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1734
1735 /* Only valid when HAS_DISPLAY() is true */
1736 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1737
1738 static inline bool intel_vtd_active(void)
1739 {
1740 #ifdef CONFIG_INTEL_IOMMU
1741         if (intel_iommu_gfx_mapped)
1742                 return true;
1743 #endif
1744         return false;
1745 }
1746
1747 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1748 {
1749         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1750 }
1751
1752 static inline bool
1753 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1754 {
1755         return IS_BROXTON(dev_priv) && intel_vtd_active();
1756 }
1757
1758 /* i915_drv.c */
1759 #ifdef CONFIG_COMPAT
1760 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
1761 #else
1762 #define i915_compat_ioctl NULL
1763 #endif
1764 extern const struct dev_pm_ops i915_pm_ops;
1765
1766 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1767 void i915_driver_remove(struct drm_i915_private *i915);
1768
1769 int i915_resume_switcheroo(struct drm_i915_private *i915);
1770 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1771
1772 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1773
1774 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
1775 {
1776         return dev_priv->gvt;
1777 }
1778
1779 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
1780 {
1781         return dev_priv->vgpu.active;
1782 }
1783
1784 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1785                         struct drm_file *file_priv);
1786
1787 /* i915_gem.c */
1788 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1789 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1790 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1791 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1792 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1793 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1794
1795 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1796
1797 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1798 {
1799         /*
1800          * A single pass should suffice to release all the freed objects (along
1801          * most call paths) , but be a little more paranoid in that freeing
1802          * the objects does take a little amount of time, during which the rcu
1803          * callbacks could have added new objects into the freed list, and
1804          * armed the work again.
1805          */
1806         while (atomic_read(&i915->mm.free_count)) {
1807                 flush_work(&i915->mm.free_work);
1808                 rcu_barrier();
1809         }
1810 }
1811
1812 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1813 {
1814         /*
1815          * Similar to objects above (see i915_gem_drain_freed-objects), in
1816          * general we have workers that are armed by RCU and then rearm
1817          * themselves in their callbacks. To be paranoid, we need to
1818          * drain the workqueue a second time after waiting for the RCU
1819          * grace period so that we catch work queued via RCU from the first
1820          * pass. As neither drain_workqueue() nor flush_workqueue() report
1821          * a result, we make an assumption that we only don't require more
1822          * than 3 passes to catch all _recursive_ RCU delayed work.
1823          *
1824          */
1825         int pass = 3;
1826         do {
1827                 flush_workqueue(i915->wq);
1828                 rcu_barrier();
1829                 i915_gem_drain_freed_objects(i915);
1830         } while (--pass);
1831         drain_workqueue(i915->wq);
1832 }
1833
1834 struct i915_vma * __must_check
1835 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1836                          const struct i915_ggtt_view *view,
1837                          u64 size,
1838                          u64 alignment,
1839                          u64 flags);
1840
1841 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1842                            unsigned long flags);
1843 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1844
1845 struct i915_vma * __must_check
1846 i915_gem_object_pin(struct drm_i915_gem_object *obj,
1847                     struct i915_address_space *vm,
1848                     const struct i915_ggtt_view *view,
1849                     u64 size,
1850                     u64 alignment,
1851                     u64 flags);
1852
1853 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1854
1855 static inline int __must_check
1856 i915_mutex_lock_interruptible(struct drm_device *dev)
1857 {
1858         return mutex_lock_interruptible(&dev->struct_mutex);
1859 }
1860
1861 int i915_gem_dumb_create(struct drm_file *file_priv,
1862                          struct drm_device *dev,
1863                          struct drm_mode_create_dumb *args);
1864 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1865                       u32 handle, u64 *offset);
1866 int i915_gem_mmap_gtt_version(void);
1867
1868 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1869
1870 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1871 {
1872         return atomic_read(&error->reset_count);
1873 }
1874
1875 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1876                                           struct intel_engine_cs *engine)
1877 {
1878         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1879 }
1880
1881 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1882 void i915_gem_driver_register(struct drm_i915_private *i915);
1883 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1884 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1885 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1886 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1887 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1888 void i915_gem_resume(struct drm_i915_private *dev_priv);
1889 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
1890
1891 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1892 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1893
1894 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1895                                     enum i915_cache_level cache_level);
1896
1897 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1898                                 struct dma_buf *dma_buf);
1899
1900 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1901
1902 static inline struct i915_gem_context *
1903 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1904 {
1905         return idr_find(&file_priv->context_idr, id);
1906 }
1907
1908 static inline struct i915_gem_context *
1909 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1910 {
1911         struct i915_gem_context *ctx;
1912
1913         rcu_read_lock();
1914         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1915         if (ctx && !kref_get_unless_zero(&ctx->ref))
1916                 ctx = NULL;
1917         rcu_read_unlock();
1918
1919         return ctx;
1920 }
1921
1922 /* i915_gem_evict.c */
1923 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1924                                           u64 min_size, u64 alignment,
1925                                           unsigned long color,
1926                                           u64 start, u64 end,
1927                                           unsigned flags);
1928 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1929                                          struct drm_mm_node *node,
1930                                          unsigned int flags);
1931 int i915_gem_evict_vm(struct i915_address_space *vm);
1932
1933 /* i915_gem_internal.c */
1934 struct drm_i915_gem_object *
1935 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1936                                 phys_addr_t size);
1937
1938 /* i915_gem_tiling.c */
1939 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1940 {
1941         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1942
1943         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1944                 i915_gem_object_is_tiled(obj);
1945 }
1946
1947 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1948                         unsigned int tiling, unsigned int stride);
1949 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1950                              unsigned int tiling, unsigned int stride);
1951
1952 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1953
1954 /* i915_cmd_parser.c */
1955 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1956 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1957 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1958 int intel_engine_cmd_parser(struct i915_gem_context *cxt,
1959                             struct intel_engine_cs *engine,
1960                             struct drm_i915_gem_object *batch_obj,
1961                             u64 user_batch_start,
1962                             u32 batch_start_offset,
1963                             u32 batch_len,
1964                             struct drm_i915_gem_object *shadow_batch_obj,
1965                             u64 shadow_batch_start);
1966
1967 /* intel_device_info.c */
1968 static inline struct intel_device_info *
1969 mkwrite_device_info(struct drm_i915_private *dev_priv)
1970 {
1971         return (struct intel_device_info *)INTEL_INFO(dev_priv);
1972 }
1973
1974 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1975                         struct drm_file *file);
1976
1977 #define __I915_REG_OP(op__, dev_priv__, ...) \
1978         intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
1979
1980 #define I915_READ(reg__)         __I915_REG_OP(read, dev_priv, (reg__))
1981 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1982
1983 #define POSTING_READ(reg__)     __I915_REG_OP(posting_read, dev_priv, (reg__))
1984
1985 /* These are untraced mmio-accessors that are only valid to be used inside
1986  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
1987  * controlled.
1988  *
1989  * Think twice, and think again, before using these.
1990  *
1991  * As an example, these accessors can possibly be used between:
1992  *
1993  * spin_lock_irq(&dev_priv->uncore.lock);
1994  * intel_uncore_forcewake_get__locked();
1995  *
1996  * and
1997  *
1998  * intel_uncore_forcewake_put__locked();
1999  * spin_unlock_irq(&dev_priv->uncore.lock);
2000  *
2001  *
2002  * Note: some registers may not need forcewake held, so
2003  * intel_uncore_forcewake_{get,put} can be omitted, see
2004  * intel_uncore_forcewake_for_reg().
2005  *
2006  * Certain architectures will die if the same cacheline is concurrently accessed
2007  * by different clients (e.g. on Ivybridge). Access to registers should
2008  * therefore generally be serialised, by either the dev_priv->uncore.lock or
2009  * a more localised lock guarding all access to that bank of registers.
2010  */
2011 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2012 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2013
2014 /* register wait wrappers for display regs */
2015 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
2016         intel_wait_for_register(&(dev_priv_)->uncore, \
2017                                 (reg_), (mask_), (value_), (timeout_))
2018
2019 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({      \
2020         u32 mask__ = (mask_);                                           \
2021         intel_de_wait_for_register((dev_priv_), (reg_),                 \
2022                                    mask__, mask__, (timeout_)); \
2023 })
2024
2025 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
2026         intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_))
2027
2028 /* i915_mm.c */
2029 int remap_io_mapping(struct vm_area_struct *vma,
2030                      unsigned long addr, unsigned long pfn, unsigned long size,
2031                      struct io_mapping *iomap);
2032
2033 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2034 {
2035         if (INTEL_GEN(i915) >= 10)
2036                 return CNL_HWS_CSB_WRITE_INDEX;
2037         else
2038                 return I915_HWS_CSB_WRITE_INDEX;
2039 }
2040
2041 static inline enum i915_map_type
2042 i915_coherent_map_type(struct drm_i915_private *i915)
2043 {
2044         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2045 }
2046
2047 #endif