1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/dma-resv.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_atomic.h>
58 #include <drm/drm_connector.h>
59 #include <drm/i915_mei_hdcp_interface.h>
61 #include "i915_fixed.h"
62 #include "i915_params.h"
64 #include "i915_utils.h"
66 #include "display/intel_bios.h"
67 #include "display/intel_display.h"
68 #include "display/intel_display_power.h"
69 #include "display/intel_dpll_mgr.h"
70 #include "display/intel_dsb.h"
71 #include "display/intel_frontbuffer.h"
72 #include "display/intel_gmbus.h"
73 #include "display/intel_opregion.h"
75 #include "gem/i915_gem_context_types.h"
76 #include "gem/i915_gem_shrinker.h"
77 #include "gem/i915_gem_stolen.h"
79 #include "gt/intel_lrc.h"
80 #include "gt/intel_engine.h"
81 #include "gt/intel_gt_types.h"
82 #include "gt/intel_workarounds.h"
83 #include "gt/uc/intel_uc.h"
85 #include "intel_device_info.h"
86 #include "intel_pch.h"
87 #include "intel_runtime_pm.h"
88 #include "intel_memory_region.h"
89 #include "intel_uncore.h"
90 #include "intel_wakeref.h"
91 #include "intel_wopcm.h"
94 #include "i915_gem_fence_reg.h"
95 #include "i915_gem_gtt.h"
96 #include "i915_gpu_error.h"
97 #include "i915_perf_types.h"
98 #include "i915_request.h"
99 #include "i915_scheduler.h"
100 #include "gt/intel_timeline.h"
101 #include "i915_vma.h"
102 #include "i915_irq.h"
104 #include "intel_region_lmem.h"
106 #include "intel_gvt.h"
108 /* General customization:
111 #define DRIVER_NAME "i915"
112 #define DRIVER_DESC "Intel Graphics"
113 #define DRIVER_DATE "20191101"
114 #define DRIVER_TIMESTAMP 1572604873
116 struct drm_i915_gem_object;
120 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
137 #define for_each_hpd_pin(__pin) \
138 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
140 /* Threshold == 5 for long IRQs, 50 for short */
141 #define HPD_STORM_DEFAULT_THRESHOLD 50
143 struct i915_hotplug {
144 struct delayed_work hotplug_work;
147 unsigned long last_jiffies;
152 HPD_MARK_DISABLED = 2
154 } stats[HPD_NUM_PINS];
157 struct delayed_work reenable_work;
161 struct work_struct dig_port_work;
163 struct work_struct poll_init_work;
166 unsigned int hpd_storm_threshold;
167 /* Whether or not to count short HPD IRQs in HPD storms */
168 u8 hpd_short_storm_enabled;
171 * if we get a HPD irq from DP and a HPD irq from non-DP
172 * the non-DP HPD could block the workqueue on a mode config
173 * mutex getting, that userspace may have taken. However
174 * userspace is waiting on the DP workqueue to run which is
175 * blocked behind the non-DP one.
177 struct workqueue_struct *dp_wq;
180 #define I915_GEM_GPU_DOMAINS \
181 (I915_GEM_DOMAIN_RENDER | \
182 I915_GEM_DOMAIN_SAMPLER | \
183 I915_GEM_DOMAIN_COMMAND | \
184 I915_GEM_DOMAIN_INSTRUCTION | \
185 I915_GEM_DOMAIN_VERTEX)
187 struct drm_i915_private;
188 struct i915_mm_struct;
189 struct i915_mmu_object;
191 struct drm_i915_file_private {
192 struct drm_i915_private *dev_priv;
195 struct drm_file *file;
201 struct list_head request_list;
204 struct idr context_idr;
205 struct mutex context_idr_lock; /* guards context_idr */
208 struct mutex vm_idr_lock; /* guards vm_idr */
210 unsigned int bsd_engine;
213 * Every context ban increments per client ban score. Also
214 * hangs in short succession increments ban score. If ban threshold
215 * is reached, client is considered banned and submitting more work
216 * will fail. This is a stop gap measure to limit the badly behaving
217 * clients access to gpu. Note that unbannable contexts never increment
218 * the client ban score.
220 #define I915_CLIENT_SCORE_HANG_FAST 1
221 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
222 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
223 #define I915_CLIENT_SCORE_BANNED 9
224 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
226 unsigned long hang_timestamp;
229 /* Interface history:
232 * 1.2: Add Power Management
233 * 1.3: Add vblank support
234 * 1.4: Fix cmdbuffer path, add heap destroy
235 * 1.5: Add vblank pipe configuration
236 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
237 * - Support vertical blank on secondary display pipe
239 #define DRIVER_MAJOR 1
240 #define DRIVER_MINOR 6
241 #define DRIVER_PATCHLEVEL 0
243 struct intel_overlay;
244 struct intel_overlay_error_state;
246 struct sdvo_device_mapping {
255 struct intel_connector;
256 struct intel_encoder;
257 struct intel_atomic_state;
258 struct intel_crtc_state;
259 struct intel_initial_plane_config;
263 struct intel_cdclk_state;
265 struct drm_i915_display_funcs {
266 void (*get_cdclk)(struct drm_i915_private *dev_priv,
267 struct intel_cdclk_state *cdclk_state);
268 void (*set_cdclk)(struct drm_i915_private *dev_priv,
269 const struct intel_cdclk_state *cdclk_state,
271 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
272 enum i9xx_plane_id i9xx_plane);
273 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
274 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
275 void (*initial_watermarks)(struct intel_atomic_state *state,
276 struct intel_crtc_state *crtc_state);
277 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
278 struct intel_crtc_state *crtc_state);
279 void (*optimize_watermarks)(struct intel_atomic_state *state,
280 struct intel_crtc_state *crtc_state);
281 int (*compute_global_watermarks)(struct intel_atomic_state *state);
282 void (*update_wm)(struct intel_crtc *crtc);
283 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
284 u8 (*calc_voltage_level)(int cdclk);
285 /* Returns the active state of the crtc, and if the crtc is active,
286 * fills out the pipe-config with the hw state. */
287 bool (*get_pipe_config)(struct intel_crtc *,
288 struct intel_crtc_state *);
289 void (*get_initial_plane_config)(struct intel_crtc *,
290 struct intel_initial_plane_config *);
291 int (*crtc_compute_clock)(struct intel_crtc *crtc,
292 struct intel_crtc_state *crtc_state);
293 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
294 struct intel_atomic_state *old_state);
295 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
296 struct intel_atomic_state *old_state);
297 void (*commit_modeset_enables)(struct intel_atomic_state *state);
298 void (*commit_modeset_disables)(struct intel_atomic_state *state);
299 void (*audio_codec_enable)(struct intel_encoder *encoder,
300 const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 void (*audio_codec_disable)(struct intel_encoder *encoder,
303 const struct intel_crtc_state *old_crtc_state,
304 const struct drm_connector_state *old_conn_state);
305 void (*fdi_link_train)(struct intel_crtc *crtc,
306 const struct intel_crtc_state *crtc_state);
307 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
308 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
309 /* clock updates for mode set */
311 /* render clock increase/decrease */
312 /* display clock increase/decrease */
313 /* pll clock increase/decrease */
315 int (*color_check)(struct intel_crtc_state *crtc_state);
317 * Program double buffered color management registers during
318 * vblank evasion. The registers should then latch during the
319 * next vblank start, alongside any other double buffered registers
320 * involved with the same commit.
322 void (*color_commit)(const struct intel_crtc_state *crtc_state);
324 * Load LUTs (and other single buffered color management
325 * registers). Will (hopefully) be called during the vblank
326 * following the latching of any double buffered registers
327 * involved with the same commit.
329 void (*load_luts)(const struct intel_crtc_state *crtc_state);
330 void (*read_luts)(struct intel_crtc_state *crtc_state);
334 struct work_struct work;
336 u32 required_version;
337 u32 max_fw_size; /* bytes */
339 u32 dmc_fw_size; /* dwords */
342 i915_reg_t mmioaddr[20];
347 intel_wakeref_t wakeref;
350 enum i915_cache_level {
352 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
353 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
354 caches, eg sampler/render caches, and the
355 large Last-Level-Cache. LLC is coherent with
356 the CPU, but L3 is only visible to the GPU. */
357 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
360 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
363 /* This is always the inner lock when overlapping with struct_mutex and
364 * it's the outer lock when overlapping with stolen_lock. */
367 unsigned int possible_framebuffer_bits;
368 unsigned int busy_bits;
369 unsigned int visible_pipes_mask;
370 struct intel_crtc *crtc;
372 struct drm_mm_node compressed_fb;
373 struct drm_mm_node *compressed_llb;
381 bool underrun_detected;
382 struct work_struct underrun_work;
385 * Due to the atomic rules we can't access some structures without the
386 * appropriate locking, so we cache information here in order to avoid
389 struct intel_fbc_state_cache {
390 struct i915_vma *vma;
394 unsigned int mode_flags;
395 u32 hsw_bdw_pixel_rate;
399 unsigned int rotation;
404 * Display surface base address adjustement for
405 * pageflips. Note that on gen4+ this only adjusts up
406 * to a tile, offsets within a tile are handled in
407 * the hw itself (with the TILEOFF register).
414 u16 pixel_blend_mode;
418 const struct drm_format_info *format;
424 * This structure contains everything that's relevant to program the
425 * hardware registers. When we want to figure out if we need to disable
426 * and re-enable FBC for a new configuration we just check if there's
427 * something different in the struct. The genx_fbc_activate functions
428 * are supposed to read from it in order to program the registers.
430 struct intel_fbc_reg_params {
431 struct i915_vma *vma;
436 enum i9xx_plane_id i9xx_plane;
437 unsigned int fence_y_offset;
441 const struct drm_format_info *format;
446 unsigned int gen9_wa_cfb_stride;
449 const char *no_fbc_reason;
453 * HIGH_RR is the highest eDP panel refresh rate read from EDID
454 * LOW_RR is the lowest eDP panel refresh rate found from EDID
455 * parsing for same resolution.
457 enum drrs_refresh_rate_type {
460 DRRS_MAX_RR, /* RR count */
463 enum drrs_support_type {
464 DRRS_NOT_SUPPORTED = 0,
465 STATIC_DRRS_SUPPORT = 1,
466 SEAMLESS_DRRS_SUPPORT = 2
472 struct delayed_work work;
474 unsigned busy_frontbuffer_bits;
475 enum drrs_refresh_rate_type refresh_rate_type;
476 enum drrs_support_type type;
482 #define I915_PSR_DEBUG_MODE_MASK 0x0f
483 #define I915_PSR_DEBUG_DEFAULT 0x00
484 #define I915_PSR_DEBUG_DISABLE 0x01
485 #define I915_PSR_DEBUG_ENABLE 0x02
486 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
487 #define I915_PSR_DEBUG_IRQ 0x10
494 enum transcoder transcoder;
496 struct work_struct work;
497 unsigned busy_frontbuffer_bits;
498 bool sink_psr2_support;
500 bool colorimetry_support;
502 u8 sink_sync_latency;
503 ktime_t last_entry_attempt;
505 bool sink_not_reliable;
507 u16 su_x_granularity;
509 u32 dc3co_exit_delay;
510 struct delayed_work idle_work;
513 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
514 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
515 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
516 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
517 #define QUIRK_INCREASE_T12_DELAY (1<<6)
518 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
521 struct intel_fbc_work;
524 struct i2c_adapter adapter;
525 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
529 struct i2c_algo_bit_data bit_algo;
530 struct drm_i915_private *dev_priv;
533 struct i915_suspend_saved_registers {
536 u32 saveCACHE_MODE_0;
537 u32 saveMI_ARB_STATE;
541 u64 saveFENCE[I915_MAX_NUM_FENCES];
542 u32 savePCH_PORT_HOTPLUG;
546 struct vlv_s0ix_state;
548 #define MAX_L3_SLICES 2
549 struct intel_l3_parity {
550 u32 *remap_info[MAX_L3_SLICES];
551 struct work_struct error_work;
556 /** Memory allocator for GTT stolen memory */
557 struct drm_mm stolen;
558 /** Protects the usage of the GTT stolen memory allocator. This is
559 * always the inner lock when overlapping with struct_mutex. */
560 struct mutex stolen_lock;
562 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
566 * List of objects which are purgeable.
568 struct list_head purge_list;
571 * List of objects which have allocated pages and are shrinkable.
573 struct list_head shrink_list;
576 * List of objects which are pending destruction.
578 struct llist_head free_list;
579 struct work_struct free_work;
581 * Count of objects pending destructions. Used to skip needlessly
582 * waiting on an RCU barrier if no objects are waiting to be freed.
587 * Small stash of WC pages
589 struct pagestash wc_stash;
592 * tmpfs instance used for shmem backed objects
594 struct vfsmount *gemfs;
596 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
598 struct notifier_block oom_notifier;
599 struct notifier_block vmap_notifier;
600 struct shrinker shrinker;
603 * Workqueue to fault in userptr pages, flushed by the execbuf
604 * when required but otherwise left to userspace to try again
607 struct workqueue_struct *userptr_wq;
609 /* shrinker accounting, also useful for userland debugging */
614 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
616 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
617 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
619 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
620 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
622 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
624 struct ddi_vbt_port_info {
625 /* Non-NULL if port present. */
626 const struct child_device_config *child;
631 * This is an index in the HDMI/DVI DDI buffer translation table.
632 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
633 * populate this field.
635 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
642 u8 supports_typec_usb:1;
645 u8 alternate_aux_channel;
646 u8 alternate_ddc_pin;
650 int dp_max_link_rate; /* 0 for not limited by VBT */
653 enum psr_lines_to_wait {
654 PSR_0_LINES_TO_WAIT = 0,
660 struct intel_vbt_data {
661 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
662 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
665 unsigned int int_tv_support:1;
666 unsigned int lvds_dither:1;
667 unsigned int int_crt_support:1;
668 unsigned int lvds_use_ssc:1;
669 unsigned int int_lvds_support:1;
670 unsigned int display_clock_mode:1;
671 unsigned int fdi_rx_polarity_inverted:1;
672 unsigned int panel_type:4;
674 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
675 enum drm_panel_orientation orientation;
677 enum drrs_support_type drrs_type;
687 struct edp_power_seq pps;
693 bool require_aux_wakeup;
695 enum psr_lines_to_wait lines_to_wait;
696 int tp1_wakeup_time_us;
697 int tp2_tp3_wakeup_time_us;
698 int psr2_tp2_tp3_wakeup_time_us;
705 u8 min_brightness; /* min_brightness/255 of max */
706 u8 controller; /* brightness controller number */
707 enum intel_backlight_type type;
713 struct mipi_config *config;
714 struct mipi_pps_data *pps;
720 const u8 *sequence[MIPI_SEQ_MAX];
721 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
722 enum drm_panel_orientation orientation;
728 struct child_device_config *child_dev;
730 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
731 struct sdvo_device_mapping sdvo_mappings[2];
734 enum intel_ddb_partitioning {
736 INTEL_DDB_PART_5_6, /* IVB+ */
739 struct intel_wm_level {
747 struct ilk_wm_values {
753 enum intel_ddb_partitioning partitioning;
757 u16 plane[I915_MAX_PLANES];
767 struct vlv_wm_ddl_values {
768 u8 plane[I915_MAX_PLANES];
771 struct vlv_wm_values {
772 struct g4x_pipe_wm pipe[3];
774 struct vlv_wm_ddl_values ddl[3];
779 struct g4x_wm_values {
780 struct g4x_pipe_wm pipe[2];
782 struct g4x_sr_wm hpll;
788 struct skl_ddb_entry {
789 u16 start, end; /* in number of blocks, 'end' is exclusive */
792 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
794 return entry->end - entry->start;
797 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
798 const struct skl_ddb_entry *e2)
800 if (e1->start == e2->start && e1->end == e2->end)
806 struct skl_ddb_allocation {
807 u8 enabled_slices; /* GEN11 has configurable 2 slices */
810 struct skl_ddb_values {
811 unsigned dirty_pipes;
812 struct skl_ddb_allocation ddb;
815 struct skl_wm_level {
823 /* Stores plane specific WM parameters */
824 struct skl_wm_params {
825 bool x_tiled, y_tiled;
830 u32 plane_pixel_rate;
832 u32 plane_bytes_per_line;
833 uint_fixed_16_16_t plane_blocks_per_line;
834 uint_fixed_16_16_t y_tile_minimum;
839 enum intel_pipe_crc_source {
840 INTEL_PIPE_CRC_SOURCE_NONE,
841 INTEL_PIPE_CRC_SOURCE_PLANE1,
842 INTEL_PIPE_CRC_SOURCE_PLANE2,
843 INTEL_PIPE_CRC_SOURCE_PLANE3,
844 INTEL_PIPE_CRC_SOURCE_PLANE4,
845 INTEL_PIPE_CRC_SOURCE_PLANE5,
846 INTEL_PIPE_CRC_SOURCE_PLANE6,
847 INTEL_PIPE_CRC_SOURCE_PLANE7,
848 INTEL_PIPE_CRC_SOURCE_PIPE,
849 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
850 INTEL_PIPE_CRC_SOURCE_TV,
851 INTEL_PIPE_CRC_SOURCE_DP_B,
852 INTEL_PIPE_CRC_SOURCE_DP_C,
853 INTEL_PIPE_CRC_SOURCE_DP_D,
854 INTEL_PIPE_CRC_SOURCE_AUTO,
855 INTEL_PIPE_CRC_SOURCE_MAX,
858 #define INTEL_PIPE_CRC_ENTRIES_NR 128
859 struct intel_pipe_crc {
862 enum intel_pipe_crc_source source;
865 struct i915_frontbuffer_tracking {
869 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
876 struct i915_virtual_gpu {
877 struct mutex lock; /* serialises sending of g2v_notify command pkts */
882 /* used in computing the new watermarks state */
883 struct intel_wm_config {
884 unsigned int num_pipes_active;
885 bool sprites_enabled;
889 struct intel_cdclk_state {
890 unsigned int cdclk, vco, ref, bypass;
894 struct i915_selftest_stash {
898 struct drm_i915_private {
899 struct drm_device drm;
901 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
902 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
903 struct intel_driver_caps caps;
906 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
907 * end of stolen which we can optionally use to create GEM objects
908 * backed by stolen memory. Note that stolen_usable_size tells us
909 * exactly how much of this we are actually allowed to use, given that
910 * some portion of it is in fact reserved for use by hardware functions.
914 * Reseved portion of Data Stolen Memory
916 struct resource dsm_reserved;
919 * Stolen memory is segmented in hardware with different portions
920 * offlimits to certain functions.
922 * The drm_mm is initialised to the total accessible range, as found
923 * from the PCI config. On Broadwell+, this is further restricted to
924 * avoid the first page! The upper end of stolen memory is reserved for
925 * hardware functions and similarly removed from the accessible range.
927 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
929 struct intel_uncore uncore;
930 struct intel_uncore_mmio_debug mmio_debug;
932 struct i915_virtual_gpu vgpu;
934 struct intel_gvt *gvt;
936 struct intel_wopcm wopcm;
938 struct intel_csr csr;
940 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
942 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
943 * controller on different i2c buses. */
944 struct mutex gmbus_mutex;
947 * Base address of where the gmbus and gpio blocks are located (either
948 * on PCH or on SoC for platforms without PCH).
952 u32 hsw_psr_mmio_adjust;
954 /* MMIO base address for MIPI regs */
959 wait_queue_head_t gmbus_wait_queue;
961 struct pci_dev *bridge_dev;
963 /* Context used internally to idle the GPU and setup initial state */
964 struct i915_gem_context *kernel_context;
966 struct intel_engine_cs *engine[I915_NUM_ENGINES];
967 struct rb_root uabi_engines;
969 struct resource mch_res;
971 /* protects the irq masks */
974 bool display_irqs_enabled;
976 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
977 struct pm_qos_request pm_qos;
979 /* Sideband mailbox protection */
980 struct mutex sb_lock;
981 struct pm_qos_request sb_qos;
983 /** Cached value of IMR to avoid reads in updating the bitfield */
986 u32 de_irq_mask[I915_MAX_PIPES];
988 u32 pipestat_irq_mask[I915_MAX_PIPES];
990 struct i915_hotplug hotplug;
991 struct intel_fbc fbc;
992 struct i915_drrs drrs;
993 struct intel_opregion opregion;
994 struct intel_vbt_data vbt;
996 bool preserve_bios_swizzle;
999 struct intel_overlay *overlay;
1001 /* backlight registers and fields in struct intel_panel */
1002 struct mutex backlight_lock;
1004 /* protects panel power sequencer state */
1005 struct mutex pps_mutex;
1007 unsigned int fsb_freq, mem_freq, is_ddr3;
1008 unsigned int skl_preferred_vco_freq;
1009 unsigned int max_cdclk_freq;
1011 unsigned int max_dotclk_freq;
1012 unsigned int rawclk_freq;
1013 unsigned int hpll_freq;
1014 unsigned int fdi_pll_freq;
1015 unsigned int czclk_freq;
1018 * For reading holding any crtc lock is sufficient,
1019 * for writing must hold all of them.
1023 * The current logical cdclk state.
1024 * See intel_atomic_state.cdclk.logical
1026 struct intel_cdclk_state logical;
1028 * The current actual cdclk state.
1029 * See intel_atomic_state.cdclk.actual
1031 struct intel_cdclk_state actual;
1032 /* The current hardware cdclk state */
1033 struct intel_cdclk_state hw;
1035 /* cdclk, divider, and ratio table from bspec */
1036 const struct intel_cdclk_vals *table;
1038 int force_min_cdclk;
1042 * wq - Driver workqueue for GEM.
1044 * NOTE: Work items scheduled here are not allowed to grab any modeset
1045 * locks, for otherwise the flushing done in the pageflip code will
1046 * result in deadlocks.
1048 struct workqueue_struct *wq;
1050 /* ordered wq for modesets */
1051 struct workqueue_struct *modeset_wq;
1052 /* unbound hipri wq for page flips/plane updates */
1053 struct workqueue_struct *flip_wq;
1055 /* Display functions */
1056 struct drm_i915_display_funcs display;
1058 /* PCH chipset type */
1059 enum intel_pch pch_type;
1060 unsigned short pch_id;
1062 unsigned long quirks;
1064 struct drm_atomic_state *modeset_restore_state;
1065 struct drm_modeset_acquire_ctx reset_ctx;
1067 struct i915_ggtt ggtt; /* VM representing the global address space */
1069 struct i915_gem_mm mm;
1070 DECLARE_HASHTABLE(mm_structs, 7);
1071 struct mutex mm_lock;
1073 /* Kernel Modesetting */
1075 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1076 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1078 #ifdef CONFIG_DEBUG_FS
1079 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1082 /* dpll and cdclk state is protected by connection_mutex */
1083 int num_shared_dpll;
1084 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1085 const struct intel_dpll_mgr *dpll_mgr;
1088 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1089 * Must be global rather than per dpll, because on some platforms
1090 * plls share registers.
1092 struct mutex dpll_lock;
1095 * For reading active_pipes, min_cdclk, min_voltage_level holding
1096 * any crtc lock is sufficient, for writing must hold all of them.
1099 /* minimum acceptable cdclk for each pipe */
1100 int min_cdclk[I915_MAX_PIPES];
1101 /* minimum acceptable voltage level for each pipe */
1102 u8 min_voltage_level[I915_MAX_PIPES];
1104 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1106 struct i915_wa_list gt_wa_list;
1108 struct i915_frontbuffer_tracking fb_tracking;
1110 struct intel_atomic_helper {
1111 struct llist_head free_list;
1112 struct work_struct free_work;
1117 bool mchbar_need_disable;
1119 struct intel_l3_parity l3_parity;
1123 * Cannot be determined by PCIID. You must always read a register.
1127 struct i915_power_domains power_domains;
1129 struct i915_psr psr;
1131 struct i915_gpu_error gpu_error;
1133 struct drm_i915_gem_object *vlv_pctx;
1135 /* list of fbdev register on this device */
1136 struct intel_fbdev *fbdev;
1137 struct work_struct fbdev_suspend_work;
1139 struct drm_property *broadcast_rgb_property;
1140 struct drm_property *force_audio_property;
1142 /* hda/i915 audio component */
1143 struct i915_audio_component *audio_component;
1144 bool audio_component_registered;
1146 * av_mutex - mutex for audio/video sync
1149 struct mutex av_mutex;
1150 int audio_power_refcount;
1151 u32 audio_freq_cntrl;
1155 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1156 u32 chv_phy_control;
1158 * Shadows for CHV DPLL_MD regs to keep the state
1159 * checker somewhat working in the presence hardware
1160 * crappiness (can't read out DPLL_MD for pipes B & C).
1162 u32 chv_dpll_md[I915_MAX_PIPES];
1166 bool power_domains_suspended;
1167 struct i915_suspend_saved_registers regfile;
1168 struct vlv_s0ix_state *vlv_s0ix_state;
1171 I915_SAGV_UNKNOWN = 0,
1174 I915_SAGV_NOT_CONTROLLED
1177 u32 sagv_block_time_us;
1181 * Raw watermark latency values:
1182 * in 0.1us units for WM0,
1183 * in 0.5us units for WM1+.
1192 * Raw watermark memory latency values
1193 * for SKL for all 8 levels
1198 /* current hardware state */
1200 struct ilk_wm_values hw;
1201 struct skl_ddb_values skl_hw;
1202 struct vlv_wm_values vlv;
1203 struct g4x_wm_values g4x;
1209 * Should be held around atomic WM register writing; also
1210 * protects * intel_crtc->wm.active and
1211 * crtc_state->wm.need_postvbl_update.
1213 struct mutex wm_mutex;
1216 * Set during HW readout of watermarks/DDB. Some platforms
1217 * need to know when we're still using BIOS-provided values
1218 * (which we don't fully trust).
1220 bool distrust_bios_wm;
1229 bool symmetric_memory;
1230 enum intel_dram_type {
1239 struct intel_bw_info {
1240 unsigned int deratedbw[3]; /* for each QGV point */
1245 struct drm_private_obj bw_obj;
1247 struct intel_runtime_pm runtime_pm;
1249 struct i915_perf perf;
1251 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1255 struct notifier_block pm_notifier;
1257 struct i915_gem_contexts {
1258 spinlock_t lock; /* locks list */
1259 struct list_head list;
1261 struct llist_head free_list;
1262 struct work_struct free_work;
1268 /* For i915gm/i945gm vblank irq workaround */
1271 /* perform PHY state sanity checks? */
1272 bool chv_phy_assert[2];
1276 /* Used to save the pipe-to-encoder mapping for audio */
1277 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1279 /* necessary resource sharing with HDMI LPE audio driver. */
1281 struct platform_device *platdev;
1285 struct i915_pmu pmu;
1287 struct i915_hdcp_comp_master *hdcp_master;
1288 bool hdcp_comp_added;
1290 /* Mutex to protect the above hdcp component related values. */
1291 struct mutex hdcp_comp_mutex;
1293 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1296 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1297 * will be rejected. Instead look for a better place.
1301 struct dram_dimm_info {
1302 u8 size, width, ranks;
1305 struct dram_channel_info {
1306 struct dram_dimm_info dimm_l, dimm_s;
1311 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1313 return container_of(dev, struct drm_i915_private, drm);
1316 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1318 return dev_get_drvdata(kdev);
1321 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1323 return pci_get_drvdata(pdev);
1326 /* Simple iterator over all initialised engines */
1327 #define for_each_engine(engine__, dev_priv__, id__) \
1329 (id__) < I915_NUM_ENGINES; \
1331 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1333 /* Iterator over subset of engines selected by mask */
1334 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1335 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1337 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1340 #define rb_to_uabi_engine(rb) \
1341 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1343 #define for_each_uabi_engine(engine__, i915__) \
1344 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1346 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1348 #define I915_GTT_OFFSET_NONE ((u32)-1)
1351 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1352 * considered to be the frontbuffer for the given plane interface-wise. This
1353 * doesn't mean that the hw necessarily already scans it out, but that any
1354 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1356 * We have one bit per pipe and per scanout plane type.
1358 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1359 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1360 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1361 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1362 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1364 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1365 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1366 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1367 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1368 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1370 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1371 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1372 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1374 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
1375 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1377 #define REVID_FOREVER 0xff
1378 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
1380 #define INTEL_GEN_MASK(s, e) ( \
1381 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1382 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1383 GENMASK((e) - 1, (s) - 1))
1385 /* Returns true if Gen is in inclusive range [Start, End] */
1386 #define IS_GEN_RANGE(dev_priv, s, e) \
1387 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1389 #define IS_GEN(dev_priv, n) \
1390 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1391 INTEL_INFO(dev_priv)->gen == (n))
1393 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1396 * Return true if revision is in range [since,until] inclusive.
1398 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1400 #define IS_REVID(p, since, until) \
1401 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1403 static __always_inline unsigned int
1404 __platform_mask_index(const struct intel_runtime_info *info,
1405 enum intel_platform p)
1407 const unsigned int pbits =
1408 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1410 /* Expand the platform_mask array if this fails. */
1411 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1412 pbits * ARRAY_SIZE(info->platform_mask));
1417 static __always_inline unsigned int
1418 __platform_mask_bit(const struct intel_runtime_info *info,
1419 enum intel_platform p)
1421 const unsigned int pbits =
1422 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1424 return p % pbits + INTEL_SUBPLATFORM_BITS;
1428 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1430 const unsigned int pi = __platform_mask_index(info, p);
1432 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1435 static __always_inline bool
1436 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1438 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1439 const unsigned int pi = __platform_mask_index(info, p);
1440 const unsigned int pb = __platform_mask_bit(info, p);
1442 BUILD_BUG_ON(!__builtin_constant_p(p));
1444 return info->platform_mask[pi] & BIT(pb);
1447 static __always_inline bool
1448 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1449 enum intel_platform p, unsigned int s)
1451 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1452 const unsigned int pi = __platform_mask_index(info, p);
1453 const unsigned int pb = __platform_mask_bit(info, p);
1454 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1455 const u32 mask = info->platform_mask[pi];
1457 BUILD_BUG_ON(!__builtin_constant_p(p));
1458 BUILD_BUG_ON(!__builtin_constant_p(s));
1459 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1461 /* Shift and test on the MSB position so sign flag can be used. */
1462 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1465 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1466 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1468 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1469 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1470 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1471 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1472 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1473 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1474 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1475 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1476 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1477 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1478 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1479 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1480 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1481 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1482 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1483 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1484 #define IS_IRONLAKE_M(dev_priv) \
1485 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1486 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1487 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1488 INTEL_INFO(dev_priv)->gt == 1)
1489 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1490 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1491 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1492 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1493 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1494 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1495 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1496 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1497 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1498 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1499 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1500 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1501 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1502 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1503 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1504 #define IS_BDW_ULT(dev_priv) \
1505 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1506 #define IS_BDW_ULX(dev_priv) \
1507 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1508 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1509 INTEL_INFO(dev_priv)->gt == 3)
1510 #define IS_HSW_ULT(dev_priv) \
1511 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1512 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1513 INTEL_INFO(dev_priv)->gt == 3)
1514 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1515 INTEL_INFO(dev_priv)->gt == 1)
1516 /* ULX machines are also considered ULT. */
1517 #define IS_HSW_ULX(dev_priv) \
1518 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1519 #define IS_SKL_ULT(dev_priv) \
1520 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1521 #define IS_SKL_ULX(dev_priv) \
1522 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1523 #define IS_KBL_ULT(dev_priv) \
1524 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1525 #define IS_KBL_ULX(dev_priv) \
1526 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1527 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1528 INTEL_INFO(dev_priv)->gt == 2)
1529 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1530 INTEL_INFO(dev_priv)->gt == 3)
1531 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1532 INTEL_INFO(dev_priv)->gt == 4)
1533 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1534 INTEL_INFO(dev_priv)->gt == 2)
1535 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1536 INTEL_INFO(dev_priv)->gt == 3)
1537 #define IS_CFL_ULT(dev_priv) \
1538 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1539 #define IS_CFL_ULX(dev_priv) \
1540 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1541 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1542 INTEL_INFO(dev_priv)->gt == 2)
1543 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1544 INTEL_INFO(dev_priv)->gt == 3)
1545 #define IS_CNL_WITH_PORT_F(dev_priv) \
1546 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1547 #define IS_ICL_WITH_PORT_F(dev_priv) \
1548 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1550 #define SKL_REVID_A0 0x0
1551 #define SKL_REVID_B0 0x1
1552 #define SKL_REVID_C0 0x2
1553 #define SKL_REVID_D0 0x3
1554 #define SKL_REVID_E0 0x4
1555 #define SKL_REVID_F0 0x5
1556 #define SKL_REVID_G0 0x6
1557 #define SKL_REVID_H0 0x7
1559 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1561 #define BXT_REVID_A0 0x0
1562 #define BXT_REVID_A1 0x1
1563 #define BXT_REVID_B0 0x3
1564 #define BXT_REVID_B_LAST 0x8
1565 #define BXT_REVID_C0 0x9
1567 #define IS_BXT_REVID(dev_priv, since, until) \
1568 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1570 #define KBL_REVID_A0 0x0
1571 #define KBL_REVID_B0 0x1
1572 #define KBL_REVID_C0 0x2
1573 #define KBL_REVID_D0 0x3
1574 #define KBL_REVID_E0 0x4
1576 #define IS_KBL_REVID(dev_priv, since, until) \
1577 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1579 #define GLK_REVID_A0 0x0
1580 #define GLK_REVID_A1 0x1
1582 #define IS_GLK_REVID(dev_priv, since, until) \
1583 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1585 #define CNL_REVID_A0 0x0
1586 #define CNL_REVID_B0 0x1
1587 #define CNL_REVID_C0 0x2
1589 #define IS_CNL_REVID(p, since, until) \
1590 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1592 #define ICL_REVID_A0 0x0
1593 #define ICL_REVID_A2 0x1
1594 #define ICL_REVID_B0 0x3
1595 #define ICL_REVID_B2 0x4
1596 #define ICL_REVID_C0 0x5
1598 #define IS_ICL_REVID(p, since, until) \
1599 (IS_ICELAKE(p) && IS_REVID(p, since, until))
1601 #define TGL_REVID_A0 0x0
1603 #define IS_TGL_REVID(p, since, until) \
1604 (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1606 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1607 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1608 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1610 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1612 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
1613 unsigned int first__ = (first); \
1614 unsigned int count__ = (count); \
1615 (INTEL_INFO(dev_priv)->engine_mask & \
1616 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1618 #define VDBOX_MASK(dev_priv) \
1619 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1620 #define VEBOX_MASK(dev_priv) \
1621 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1623 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1624 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1625 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1626 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
1627 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1629 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1631 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1632 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1633 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1634 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1635 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1636 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1638 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1640 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1641 #define HAS_PPGTT(dev_priv) \
1642 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1643 #define HAS_FULL_PPGTT(dev_priv) \
1644 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1646 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1647 GEM_BUG_ON((sizes) == 0); \
1648 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1651 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1652 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1653 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1655 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1656 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1658 /* WaRsDisableCoarsePowerGating:skl,cnl */
1659 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1660 (IS_CANNONLAKE(dev_priv) || \
1661 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
1663 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1664 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1665 IS_GEMINILAKE(dev_priv) || \
1666 IS_KABYLAKE(dev_priv))
1668 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1669 * rows, which changed the alignment requirements and fence programming.
1671 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1672 !(IS_I915G(dev_priv) || \
1673 IS_I915GM(dev_priv)))
1674 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1675 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1677 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
1678 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1679 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1681 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1683 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1685 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1686 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1687 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1688 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
1690 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1691 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1692 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1694 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1696 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
1698 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1699 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1701 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1703 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1704 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1706 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1708 /* Having GuC is not the same as using GuC */
1709 #define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc)
1710 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
1712 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1714 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1717 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1719 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1721 /* DPF == dynamic parity feature */
1722 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1723 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1724 2 : HAS_L3_DPF(dev_priv))
1726 #define GT_FREQUENCY_MULTIPLIER 50
1727 #define GEN9_FREQ_SCALER 3
1729 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1731 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1733 /* Only valid when HAS_DISPLAY() is true */
1734 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1736 static inline bool intel_vtd_active(void)
1738 #ifdef CONFIG_INTEL_IOMMU
1739 if (intel_iommu_gfx_mapped)
1745 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1747 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1751 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1753 return IS_BROXTON(dev_priv) && intel_vtd_active();
1757 #ifdef CONFIG_COMPAT
1758 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
1760 #define i915_compat_ioctl NULL
1762 extern const struct dev_pm_ops i915_pm_ops;
1764 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1765 void i915_driver_remove(struct drm_i915_private *i915);
1767 int i915_resume_switcheroo(struct drm_i915_private *i915);
1768 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1770 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1772 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
1774 return dev_priv->gvt;
1777 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
1779 return dev_priv->vgpu.active;
1782 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1783 struct drm_file *file_priv);
1786 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1787 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1788 void i915_gem_sanitize(struct drm_i915_private *i915);
1789 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1790 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1791 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1792 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1794 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1796 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1799 * A single pass should suffice to release all the freed objects (along
1800 * most call paths) , but be a little more paranoid in that freeing
1801 * the objects does take a little amount of time, during which the rcu
1802 * callbacks could have added new objects into the freed list, and
1803 * armed the work again.
1805 while (atomic_read(&i915->mm.free_count)) {
1806 flush_work(&i915->mm.free_work);
1811 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1814 * Similar to objects above (see i915_gem_drain_freed-objects), in
1815 * general we have workers that are armed by RCU and then rearm
1816 * themselves in their callbacks. To be paranoid, we need to
1817 * drain the workqueue a second time after waiting for the RCU
1818 * grace period so that we catch work queued via RCU from the first
1819 * pass. As neither drain_workqueue() nor flush_workqueue() report
1820 * a result, we make an assumption that we only don't require more
1821 * than 3 passes to catch all _recursive_ RCU delayed work.
1826 flush_workqueue(i915->wq);
1828 i915_gem_drain_freed_objects(i915);
1830 drain_workqueue(i915->wq);
1833 struct i915_vma * __must_check
1834 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1835 const struct i915_ggtt_view *view,
1840 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1841 unsigned long flags);
1842 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1844 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1846 static inline int __must_check
1847 i915_mutex_lock_interruptible(struct drm_device *dev)
1849 return mutex_lock_interruptible(&dev->struct_mutex);
1852 int i915_gem_dumb_create(struct drm_file *file_priv,
1853 struct drm_device *dev,
1854 struct drm_mode_create_dumb *args);
1855 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1856 u32 handle, u64 *offset);
1857 int i915_gem_mmap_gtt_version(void);
1859 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1861 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1863 return atomic_read(&error->reset_count);
1866 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1867 struct intel_engine_cs *engine)
1869 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1872 void i915_gem_init_mmio(struct drm_i915_private *i915);
1873 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1874 void i915_gem_driver_register(struct drm_i915_private *i915);
1875 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1876 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1877 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1878 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1879 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1880 void i915_gem_resume(struct drm_i915_private *dev_priv);
1881 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
1883 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1884 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1886 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1887 enum i915_cache_level cache_level);
1889 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1890 struct dma_buf *dma_buf);
1892 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1894 static inline struct i915_gem_context *
1895 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1897 return idr_find(&file_priv->context_idr, id);
1900 static inline struct i915_gem_context *
1901 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1903 struct i915_gem_context *ctx;
1906 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1907 if (ctx && !kref_get_unless_zero(&ctx->ref))
1914 /* i915_gem_evict.c */
1915 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1916 u64 min_size, u64 alignment,
1917 unsigned long color,
1920 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1921 struct drm_mm_node *node,
1922 unsigned int flags);
1923 int i915_gem_evict_vm(struct i915_address_space *vm);
1925 /* i915_gem_internal.c */
1926 struct drm_i915_gem_object *
1927 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1930 /* i915_gem_tiling.c */
1931 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1933 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1935 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1936 i915_gem_object_is_tiled(obj);
1939 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1940 unsigned int tiling, unsigned int stride);
1941 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1942 unsigned int tiling, unsigned int stride);
1944 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1946 /* i915_cmd_parser.c */
1947 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1948 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1949 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1950 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1951 struct drm_i915_gem_object *batch_obj,
1952 struct drm_i915_gem_object *shadow_batch_obj,
1953 u32 batch_start_offset,
1957 /* intel_device_info.c */
1958 static inline struct intel_device_info *
1959 mkwrite_device_info(struct drm_i915_private *dev_priv)
1961 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1964 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1965 struct drm_file *file);
1967 #define __I915_REG_OP(op__, dev_priv__, ...) \
1968 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
1970 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
1971 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1973 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
1975 /* These are untraced mmio-accessors that are only valid to be used inside
1976 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
1979 * Think twice, and think again, before using these.
1981 * As an example, these accessors can possibly be used between:
1983 * spin_lock_irq(&dev_priv->uncore.lock);
1984 * intel_uncore_forcewake_get__locked();
1988 * intel_uncore_forcewake_put__locked();
1989 * spin_unlock_irq(&dev_priv->uncore.lock);
1992 * Note: some registers may not need forcewake held, so
1993 * intel_uncore_forcewake_{get,put} can be omitted, see
1994 * intel_uncore_forcewake_for_reg().
1996 * Certain architectures will die if the same cacheline is concurrently accessed
1997 * by different clients (e.g. on Ivybridge). Access to registers should
1998 * therefore generally be serialised, by either the dev_priv->uncore.lock or
1999 * a more localised lock guarding all access to that bank of registers.
2001 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2002 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2004 /* register wait wrappers for display regs */
2005 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
2006 intel_wait_for_register(&(dev_priv_)->uncore, \
2007 (reg_), (mask_), (value_), (timeout_))
2009 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \
2010 u32 mask__ = (mask_); \
2011 intel_de_wait_for_register((dev_priv_), (reg_), \
2012 mask__, mask__, (timeout_)); \
2015 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
2016 intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_))
2019 int remap_io_mapping(struct vm_area_struct *vma,
2020 unsigned long addr, unsigned long pfn, unsigned long size,
2021 struct io_mapping *iomap);
2023 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2025 if (INTEL_GEN(i915) >= 10)
2026 return CNL_HWS_CSB_WRITE_INDEX;
2028 return I915_HWS_CSB_WRITE_INDEX;
2031 static inline enum i915_map_type
2032 i915_coherent_map_type(struct drm_i915_private *i915)
2034 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;