2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
50 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
55 if (!obj->cache_coherent)
58 return obj->pin_display;
62 insert_mappable_node(struct i915_ggtt *ggtt,
63 struct drm_mm_node *node, u32 size)
65 memset(node, 0, sizeof(*node));
66 return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
67 size, 0, I915_COLOR_UNEVICTABLE,
68 0, ggtt->mappable_end,
73 remove_mappable_node(struct drm_mm_node *node)
75 drm_mm_remove_node(node);
78 /* some bookkeeping */
79 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
82 spin_lock(&dev_priv->mm.object_stat_lock);
83 dev_priv->mm.object_count++;
84 dev_priv->mm.object_memory += size;
85 spin_unlock(&dev_priv->mm.object_stat_lock);
88 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
91 spin_lock(&dev_priv->mm.object_stat_lock);
92 dev_priv->mm.object_count--;
93 dev_priv->mm.object_memory -= size;
94 spin_unlock(&dev_priv->mm.object_stat_lock);
98 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
106 * userspace. If it takes that long something really bad is going on and
107 * we should simply try to bail out and fail as gracefully as possible.
109 ret = wait_event_interruptible_timeout(error->reset_queue,
110 !i915_reset_backoff(error),
113 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
115 } else if (ret < 0) {
122 int i915_mutex_lock_interruptible(struct drm_device *dev)
124 struct drm_i915_private *dev_priv = to_i915(dev);
127 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
131 ret = mutex_lock_interruptible(&dev->struct_mutex);
139 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
142 struct drm_i915_private *dev_priv = to_i915(dev);
143 struct i915_ggtt *ggtt = &dev_priv->ggtt;
144 struct drm_i915_gem_get_aperture *args = data;
145 struct i915_vma *vma;
148 pinned = ggtt->base.reserved;
149 mutex_lock(&dev->struct_mutex);
150 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
151 if (i915_vma_is_pinned(vma))
152 pinned += vma->node.size;
153 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
154 if (i915_vma_is_pinned(vma))
155 pinned += vma->node.size;
156 mutex_unlock(&dev->struct_mutex);
158 args->aper_size = ggtt->base.total;
159 args->aper_available_size = args->aper_size - pinned;
164 static struct sg_table *
165 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
167 struct address_space *mapping = obj->base.filp->f_mapping;
168 drm_dma_handle_t *phys;
170 struct scatterlist *sg;
174 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
175 return ERR_PTR(-EINVAL);
177 /* Always aligning to the object size, allows a single allocation
178 * to handle all possible callers, and given typical object sizes,
179 * the alignment of the buddy allocation will naturally match.
181 phys = drm_pci_alloc(obj->base.dev,
183 roundup_pow_of_two(obj->base.size));
185 return ERR_PTR(-ENOMEM);
188 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
192 page = shmem_read_mapping_page(mapping, i);
198 src = kmap_atomic(page);
199 memcpy(vaddr, src, PAGE_SIZE);
200 drm_clflush_virt_range(vaddr, PAGE_SIZE);
207 i915_gem_chipset_flush(to_i915(obj->base.dev));
209 st = kmalloc(sizeof(*st), GFP_KERNEL);
211 st = ERR_PTR(-ENOMEM);
215 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
217 st = ERR_PTR(-ENOMEM);
223 sg->length = obj->base.size;
225 sg_dma_address(sg) = phys->busaddr;
226 sg_dma_len(sg) = obj->base.size;
228 obj->phys_handle = phys;
232 drm_pci_free(obj->base.dev, phys);
236 static void __start_cpu_write(struct drm_i915_gem_object *obj)
238 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
239 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
240 if (cpu_write_needs_clflush(obj))
241 obj->cache_dirty = true;
245 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
246 struct sg_table *pages,
249 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
251 if (obj->mm.madv == I915_MADV_DONTNEED)
252 obj->mm.dirty = false;
255 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
256 !obj->cache_coherent)
257 drm_clflush_sg(pages);
259 __start_cpu_write(obj);
263 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
264 struct sg_table *pages)
266 __i915_gem_object_release_shmem(obj, pages, false);
269 struct address_space *mapping = obj->base.filp->f_mapping;
270 char *vaddr = obj->phys_handle->vaddr;
273 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
277 page = shmem_read_mapping_page(mapping, i);
281 dst = kmap_atomic(page);
282 drm_clflush_virt_range(vaddr, PAGE_SIZE);
283 memcpy(dst, vaddr, PAGE_SIZE);
286 set_page_dirty(page);
287 if (obj->mm.madv == I915_MADV_WILLNEED)
288 mark_page_accessed(page);
292 obj->mm.dirty = false;
295 sg_free_table(pages);
298 drm_pci_free(obj->base.dev, obj->phys_handle);
302 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
304 i915_gem_object_unpin_pages(obj);
307 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
308 .get_pages = i915_gem_object_get_pages_phys,
309 .put_pages = i915_gem_object_put_pages_phys,
310 .release = i915_gem_object_release_phys,
313 static const struct drm_i915_gem_object_ops i915_gem_object_ops;
315 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
317 struct i915_vma *vma;
318 LIST_HEAD(still_in_list);
321 lockdep_assert_held(&obj->base.dev->struct_mutex);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret = i915_gem_object_wait(obj,
329 I915_WAIT_INTERRUPTIBLE |
332 MAX_SCHEDULE_TIMEOUT,
337 i915_gem_retire_requests(to_i915(obj->base.dev));
339 while ((vma = list_first_entry_or_null(&obj->vma_list,
342 list_move_tail(&vma->obj_link, &still_in_list);
343 ret = i915_vma_unbind(vma);
347 list_splice(&still_in_list, &obj->vma_list);
353 i915_gem_object_wait_fence(struct dma_fence *fence,
356 struct intel_rps_client *rps)
358 struct drm_i915_gem_request *rq;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
365 if (!dma_fence_is_i915(fence))
366 return dma_fence_wait_timeout(fence,
367 flags & I915_WAIT_INTERRUPTIBLE,
370 rq = to_request(fence);
371 if (i915_gem_request_completed(rq))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq->i915) >= 6)
391 gen6_rps_boost(rq, rps);
396 timeout = i915_wait_request(rq, flags, timeout);
399 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
400 i915_gem_request_retire_upto(rq);
406 i915_gem_object_wait_reservation(struct reservation_object *resv,
409 struct intel_rps_client *rps)
411 unsigned int seq = __read_seqcount_begin(&resv->seq);
412 struct dma_fence *excl;
413 bool prune_fences = false;
415 if (flags & I915_WAIT_ALL) {
416 struct dma_fence **shared;
417 unsigned int count, i;
420 ret = reservation_object_get_fences_rcu(resv,
421 &excl, &count, &shared);
425 for (i = 0; i < count; i++) {
426 timeout = i915_gem_object_wait_fence(shared[i],
432 dma_fence_put(shared[i]);
435 for (; i < count; i++)
436 dma_fence_put(shared[i]);
439 prune_fences = count && timeout >= 0;
441 excl = reservation_object_get_excl_rcu(resv);
444 if (excl && timeout >= 0) {
445 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
446 prune_fences = timeout >= 0;
451 /* Oportunistically prune the fences iff we know they have *all* been
452 * signaled and that the reservation object has not been changed (i.e.
453 * no new fences have been added).
455 if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
456 if (reservation_object_trylock(resv)) {
457 if (!__read_seqcount_retry(&resv->seq, seq))
458 reservation_object_add_excl_fence(resv, NULL);
459 reservation_object_unlock(resv);
466 static void __fence_set_priority(struct dma_fence *fence, int prio)
468 struct drm_i915_gem_request *rq;
469 struct intel_engine_cs *engine;
471 if (!dma_fence_is_i915(fence))
474 rq = to_request(fence);
476 if (!engine->schedule)
479 engine->schedule(rq, prio);
482 static void fence_set_priority(struct dma_fence *fence, int prio)
484 /* Recurse once into a fence-array */
485 if (dma_fence_is_array(fence)) {
486 struct dma_fence_array *array = to_dma_fence_array(fence);
489 for (i = 0; i < array->num_fences; i++)
490 __fence_set_priority(array->fences[i], prio);
492 __fence_set_priority(fence, prio);
497 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
501 struct dma_fence *excl;
503 if (flags & I915_WAIT_ALL) {
504 struct dma_fence **shared;
505 unsigned int count, i;
508 ret = reservation_object_get_fences_rcu(obj->resv,
509 &excl, &count, &shared);
513 for (i = 0; i < count; i++) {
514 fence_set_priority(shared[i], prio);
515 dma_fence_put(shared[i]);
520 excl = reservation_object_get_excl_rcu(obj->resv);
524 fence_set_priority(excl, prio);
531 * Waits for rendering to the object to be completed
532 * @obj: i915 gem object
533 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
534 * @timeout: how long to wait
535 * @rps: client (user process) to charge for any waitboosting
538 i915_gem_object_wait(struct drm_i915_gem_object *obj,
541 struct intel_rps_client *rps)
544 #if IS_ENABLED(CONFIG_LOCKDEP)
545 GEM_BUG_ON(debug_locks &&
546 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
547 !!(flags & I915_WAIT_LOCKED));
549 GEM_BUG_ON(timeout < 0);
551 timeout = i915_gem_object_wait_reservation(obj->resv,
554 return timeout < 0 ? timeout : 0;
557 static struct intel_rps_client *to_rps_client(struct drm_file *file)
559 struct drm_i915_file_private *fpriv = file->driver_priv;
565 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
570 if (align > obj->base.size)
573 if (obj->ops == &i915_gem_phys_ops)
576 if (obj->mm.madv != I915_MADV_WILLNEED)
579 if (obj->base.filp == NULL)
582 ret = i915_gem_object_unbind(obj);
586 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
590 GEM_BUG_ON(obj->ops != &i915_gem_object_ops);
591 obj->ops = &i915_gem_phys_ops;
593 ret = i915_gem_object_pin_pages(obj);
600 obj->ops = &i915_gem_object_ops;
605 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
606 struct drm_i915_gem_pwrite *args,
607 struct drm_file *file)
609 void *vaddr = obj->phys_handle->vaddr + args->offset;
610 char __user *user_data = u64_to_user_ptr(args->data_ptr);
612 /* We manually control the domain here and pretend that it
613 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
615 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
616 if (copy_from_user(vaddr, user_data, args->size))
619 drm_clflush_virt_range(vaddr, args->size);
620 i915_gem_chipset_flush(to_i915(obj->base.dev));
622 intel_fb_obj_flush(obj, ORIGIN_CPU);
626 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
628 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
631 void i915_gem_object_free(struct drm_i915_gem_object *obj)
633 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
634 kmem_cache_free(dev_priv->objects, obj);
638 i915_gem_create(struct drm_file *file,
639 struct drm_i915_private *dev_priv,
643 struct drm_i915_gem_object *obj;
647 size = roundup(size, PAGE_SIZE);
651 /* Allocate the new object */
652 obj = i915_gem_object_create(dev_priv, size);
656 ret = drm_gem_handle_create(file, &obj->base, &handle);
657 /* drop reference from allocate - handle holds it now */
658 i915_gem_object_put(obj);
667 i915_gem_dumb_create(struct drm_file *file,
668 struct drm_device *dev,
669 struct drm_mode_create_dumb *args)
671 /* have to work out size/pitch and return them */
672 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
673 args->size = args->pitch * args->height;
674 return i915_gem_create(file, to_i915(dev),
675 args->size, &args->handle);
678 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
680 return !(obj->cache_level == I915_CACHE_NONE ||
681 obj->cache_level == I915_CACHE_WT);
685 * Creates a new mm object and returns a handle to it.
686 * @dev: drm device pointer
687 * @data: ioctl data blob
688 * @file: drm file pointer
691 i915_gem_create_ioctl(struct drm_device *dev, void *data,
692 struct drm_file *file)
694 struct drm_i915_private *dev_priv = to_i915(dev);
695 struct drm_i915_gem_create *args = data;
697 i915_gem_flush_free_objects(dev_priv);
699 return i915_gem_create(file, dev_priv,
700 args->size, &args->handle);
703 static inline enum fb_op_origin
704 fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)
706 return (domain == I915_GEM_DOMAIN_GTT ?
707 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
711 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
713 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
715 if (!(obj->base.write_domain & flush_domains))
718 /* No actual flushing is required for the GTT write domain. Writes
719 * to it "immediately" go to main memory as far as we know, so there's
720 * no chipset flush. It also doesn't land in render cache.
722 * However, we do have to enforce the order so that all writes through
723 * the GTT land before any writes to the device, such as updates to
726 * We also have to wait a bit for the writes to land from the GTT.
727 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
728 * timing. This issue has only been observed when switching quickly
729 * between GTT writes and CPU reads from inside the kernel on recent hw,
730 * and it appears to only affect discrete GTT blocks (i.e. on LLC
731 * system agents we cannot reproduce this behaviour).
735 switch (obj->base.write_domain) {
736 case I915_GEM_DOMAIN_GTT:
737 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
738 if (intel_runtime_pm_get_if_in_use(dev_priv)) {
739 spin_lock_irq(&dev_priv->uncore.lock);
740 POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
741 spin_unlock_irq(&dev_priv->uncore.lock);
742 intel_runtime_pm_put(dev_priv);
746 intel_fb_obj_flush(obj,
747 fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
750 case I915_GEM_DOMAIN_CPU:
751 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
754 case I915_GEM_DOMAIN_RENDER:
755 if (gpu_write_needs_clflush(obj))
756 obj->cache_dirty = true;
760 obj->base.write_domain = 0;
764 __copy_to_user_swizzled(char __user *cpu_vaddr,
765 const char *gpu_vaddr, int gpu_offset,
768 int ret, cpu_offset = 0;
771 int cacheline_end = ALIGN(gpu_offset + 1, 64);
772 int this_length = min(cacheline_end - gpu_offset, length);
773 int swizzled_gpu_offset = gpu_offset ^ 64;
775 ret = __copy_to_user(cpu_vaddr + cpu_offset,
776 gpu_vaddr + swizzled_gpu_offset,
781 cpu_offset += this_length;
782 gpu_offset += this_length;
783 length -= this_length;
790 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
791 const char __user *cpu_vaddr,
794 int ret, cpu_offset = 0;
797 int cacheline_end = ALIGN(gpu_offset + 1, 64);
798 int this_length = min(cacheline_end - gpu_offset, length);
799 int swizzled_gpu_offset = gpu_offset ^ 64;
801 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
802 cpu_vaddr + cpu_offset,
807 cpu_offset += this_length;
808 gpu_offset += this_length;
809 length -= this_length;
816 * Pins the specified object's pages and synchronizes the object with
817 * GPU accesses. Sets needs_clflush to non-zero if the caller should
818 * flush the object from the CPU cache.
820 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
821 unsigned int *needs_clflush)
825 lockdep_assert_held(&obj->base.dev->struct_mutex);
828 if (!i915_gem_object_has_struct_page(obj))
831 ret = i915_gem_object_wait(obj,
832 I915_WAIT_INTERRUPTIBLE |
834 MAX_SCHEDULE_TIMEOUT,
839 ret = i915_gem_object_pin_pages(obj);
843 if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
844 ret = i915_gem_object_set_to_cpu_domain(obj, false);
851 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
853 /* If we're not in the cpu read domain, set ourself into the gtt
854 * read domain and manually flush cachelines (if required). This
855 * optimizes for the case when the gpu will dirty the data
856 * anyway again before the next pread happens.
858 if (!obj->cache_dirty &&
859 !(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
860 *needs_clflush = CLFLUSH_BEFORE;
863 /* return with the pages pinned */
867 i915_gem_object_unpin_pages(obj);
871 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
872 unsigned int *needs_clflush)
876 lockdep_assert_held(&obj->base.dev->struct_mutex);
879 if (!i915_gem_object_has_struct_page(obj))
882 ret = i915_gem_object_wait(obj,
883 I915_WAIT_INTERRUPTIBLE |
886 MAX_SCHEDULE_TIMEOUT,
891 ret = i915_gem_object_pin_pages(obj);
895 if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
896 ret = i915_gem_object_set_to_cpu_domain(obj, true);
903 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
905 /* If we're not in the cpu write domain, set ourself into the
906 * gtt write domain and manually flush cachelines (as required).
907 * This optimizes for the case when the gpu will use the data
908 * right away and we therefore have to clflush anyway.
910 if (!obj->cache_dirty) {
911 *needs_clflush |= CLFLUSH_AFTER;
914 * Same trick applies to invalidate partially written
915 * cachelines read before writing.
917 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
918 *needs_clflush |= CLFLUSH_BEFORE;
922 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
923 obj->mm.dirty = true;
924 /* return with the pages pinned */
928 i915_gem_object_unpin_pages(obj);
933 shmem_clflush_swizzled_range(char *addr, unsigned long length,
936 if (unlikely(swizzled)) {
937 unsigned long start = (unsigned long) addr;
938 unsigned long end = (unsigned long) addr + length;
940 /* For swizzling simply ensure that we always flush both
941 * channels. Lame, but simple and it works. Swizzled
942 * pwrite/pread is far from a hotpath - current userspace
943 * doesn't use it at all. */
944 start = round_down(start, 128);
945 end = round_up(end, 128);
947 drm_clflush_virt_range((void *)start, end - start);
949 drm_clflush_virt_range(addr, length);
954 /* Only difference to the fast-path function is that this can handle bit17
955 * and uses non-atomic copy and kmap functions. */
957 shmem_pread_slow(struct page *page, int offset, int length,
958 char __user *user_data,
959 bool page_do_bit17_swizzling, bool needs_clflush)
966 shmem_clflush_swizzled_range(vaddr + offset, length,
967 page_do_bit17_swizzling);
969 if (page_do_bit17_swizzling)
970 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
972 ret = __copy_to_user(user_data, vaddr + offset, length);
975 return ret ? - EFAULT : 0;
979 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
980 bool page_do_bit17_swizzling, bool needs_clflush)
985 if (!page_do_bit17_swizzling) {
986 char *vaddr = kmap_atomic(page);
989 drm_clflush_virt_range(vaddr + offset, length);
990 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
991 kunmap_atomic(vaddr);
996 return shmem_pread_slow(page, offset, length, user_data,
997 page_do_bit17_swizzling, needs_clflush);
1001 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
1002 struct drm_i915_gem_pread *args)
1004 char __user *user_data;
1006 unsigned int obj_do_bit17_swizzling;
1007 unsigned int needs_clflush;
1008 unsigned int idx, offset;
1011 obj_do_bit17_swizzling = 0;
1012 if (i915_gem_object_needs_bit17_swizzle(obj))
1013 obj_do_bit17_swizzling = BIT(17);
1015 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
1019 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
1020 mutex_unlock(&obj->base.dev->struct_mutex);
1024 remain = args->size;
1025 user_data = u64_to_user_ptr(args->data_ptr);
1026 offset = offset_in_page(args->offset);
1027 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1028 struct page *page = i915_gem_object_get_page(obj, idx);
1032 if (offset + length > PAGE_SIZE)
1033 length = PAGE_SIZE - offset;
1035 ret = shmem_pread(page, offset, length, user_data,
1036 page_to_phys(page) & obj_do_bit17_swizzling,
1042 user_data += length;
1046 i915_gem_obj_finish_shmem_access(obj);
1051 gtt_user_read(struct io_mapping *mapping,
1052 loff_t base, int offset,
1053 char __user *user_data, int length)
1056 unsigned long unwritten;
1058 /* We can use the cpu mem copy function because this is X86. */
1059 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1060 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1061 io_mapping_unmap_atomic(vaddr);
1063 vaddr = (void __force *)
1064 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1065 unwritten = copy_to_user(user_data, vaddr + offset, length);
1066 io_mapping_unmap(vaddr);
1072 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1073 const struct drm_i915_gem_pread *args)
1075 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1076 struct i915_ggtt *ggtt = &i915->ggtt;
1077 struct drm_mm_node node;
1078 struct i915_vma *vma;
1079 void __user *user_data;
1083 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1087 intel_runtime_pm_get(i915);
1088 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1089 PIN_MAPPABLE | PIN_NONBLOCK);
1091 node.start = i915_ggtt_offset(vma);
1092 node.allocated = false;
1093 ret = i915_vma_put_fence(vma);
1095 i915_vma_unpin(vma);
1100 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1103 GEM_BUG_ON(!node.allocated);
1106 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1110 mutex_unlock(&i915->drm.struct_mutex);
1112 user_data = u64_to_user_ptr(args->data_ptr);
1113 remain = args->size;
1114 offset = args->offset;
1116 while (remain > 0) {
1117 /* Operation in this page
1119 * page_base = page offset within aperture
1120 * page_offset = offset within page
1121 * page_length = bytes to copy for this page
1123 u32 page_base = node.start;
1124 unsigned page_offset = offset_in_page(offset);
1125 unsigned page_length = PAGE_SIZE - page_offset;
1126 page_length = remain < page_length ? remain : page_length;
1127 if (node.allocated) {
1129 ggtt->base.insert_page(&ggtt->base,
1130 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1131 node.start, I915_CACHE_NONE, 0);
1134 page_base += offset & PAGE_MASK;
1137 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1138 user_data, page_length)) {
1143 remain -= page_length;
1144 user_data += page_length;
1145 offset += page_length;
1148 mutex_lock(&i915->drm.struct_mutex);
1150 if (node.allocated) {
1152 ggtt->base.clear_range(&ggtt->base,
1153 node.start, node.size);
1154 remove_mappable_node(&node);
1156 i915_vma_unpin(vma);
1159 intel_runtime_pm_put(i915);
1160 mutex_unlock(&i915->drm.struct_mutex);
1166 * Reads data from the object referenced by handle.
1167 * @dev: drm device pointer
1168 * @data: ioctl data blob
1169 * @file: drm file pointer
1171 * On error, the contents of *data are undefined.
1174 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1175 struct drm_file *file)
1177 struct drm_i915_gem_pread *args = data;
1178 struct drm_i915_gem_object *obj;
1181 if (args->size == 0)
1184 if (!access_ok(VERIFY_WRITE,
1185 u64_to_user_ptr(args->data_ptr),
1189 obj = i915_gem_object_lookup(file, args->handle);
1193 /* Bounds check source. */
1194 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1199 trace_i915_gem_object_pread(obj, args->offset, args->size);
1201 ret = i915_gem_object_wait(obj,
1202 I915_WAIT_INTERRUPTIBLE,
1203 MAX_SCHEDULE_TIMEOUT,
1204 to_rps_client(file));
1208 ret = i915_gem_object_pin_pages(obj);
1212 ret = i915_gem_shmem_pread(obj, args);
1213 if (ret == -EFAULT || ret == -ENODEV)
1214 ret = i915_gem_gtt_pread(obj, args);
1216 i915_gem_object_unpin_pages(obj);
1218 i915_gem_object_put(obj);
1222 /* This is the fast write path which cannot handle
1223 * page faults in the source data
1227 ggtt_write(struct io_mapping *mapping,
1228 loff_t base, int offset,
1229 char __user *user_data, int length)
1232 unsigned long unwritten;
1234 /* We can use the cpu mem copy function because this is X86. */
1235 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1236 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1238 io_mapping_unmap_atomic(vaddr);
1240 vaddr = (void __force *)
1241 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1242 unwritten = copy_from_user(vaddr + offset, user_data, length);
1243 io_mapping_unmap(vaddr);
1250 * This is the fast pwrite path, where we copy the data directly from the
1251 * user into the GTT, uncached.
1252 * @obj: i915 GEM object
1253 * @args: pwrite arguments structure
1256 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1257 const struct drm_i915_gem_pwrite *args)
1259 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1260 struct i915_ggtt *ggtt = &i915->ggtt;
1261 struct drm_mm_node node;
1262 struct i915_vma *vma;
1264 void __user *user_data;
1267 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1271 intel_runtime_pm_get(i915);
1272 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1273 PIN_MAPPABLE | PIN_NONBLOCK);
1275 node.start = i915_ggtt_offset(vma);
1276 node.allocated = false;
1277 ret = i915_vma_put_fence(vma);
1279 i915_vma_unpin(vma);
1284 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1287 GEM_BUG_ON(!node.allocated);
1290 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1294 mutex_unlock(&i915->drm.struct_mutex);
1296 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1298 user_data = u64_to_user_ptr(args->data_ptr);
1299 offset = args->offset;
1300 remain = args->size;
1302 /* Operation in this page
1304 * page_base = page offset within aperture
1305 * page_offset = offset within page
1306 * page_length = bytes to copy for this page
1308 u32 page_base = node.start;
1309 unsigned int page_offset = offset_in_page(offset);
1310 unsigned int page_length = PAGE_SIZE - page_offset;
1311 page_length = remain < page_length ? remain : page_length;
1312 if (node.allocated) {
1313 wmb(); /* flush the write before we modify the GGTT */
1314 ggtt->base.insert_page(&ggtt->base,
1315 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1316 node.start, I915_CACHE_NONE, 0);
1317 wmb(); /* flush modifications to the GGTT (insert_page) */
1319 page_base += offset & PAGE_MASK;
1321 /* If we get a fault while copying data, then (presumably) our
1322 * source page isn't available. Return the error and we'll
1323 * retry in the slow path.
1324 * If the object is non-shmem backed, we retry again with the
1325 * path that handles page fault.
1327 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1328 user_data, page_length)) {
1333 remain -= page_length;
1334 user_data += page_length;
1335 offset += page_length;
1337 intel_fb_obj_flush(obj, ORIGIN_CPU);
1339 mutex_lock(&i915->drm.struct_mutex);
1341 if (node.allocated) {
1343 ggtt->base.clear_range(&ggtt->base,
1344 node.start, node.size);
1345 remove_mappable_node(&node);
1347 i915_vma_unpin(vma);
1350 intel_runtime_pm_put(i915);
1351 mutex_unlock(&i915->drm.struct_mutex);
1356 shmem_pwrite_slow(struct page *page, int offset, int length,
1357 char __user *user_data,
1358 bool page_do_bit17_swizzling,
1359 bool needs_clflush_before,
1360 bool needs_clflush_after)
1366 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1367 shmem_clflush_swizzled_range(vaddr + offset, length,
1368 page_do_bit17_swizzling);
1369 if (page_do_bit17_swizzling)
1370 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1373 ret = __copy_from_user(vaddr + offset, user_data, length);
1374 if (needs_clflush_after)
1375 shmem_clflush_swizzled_range(vaddr + offset, length,
1376 page_do_bit17_swizzling);
1379 return ret ? -EFAULT : 0;
1382 /* Per-page copy function for the shmem pwrite fastpath.
1383 * Flushes invalid cachelines before writing to the target if
1384 * needs_clflush_before is set and flushes out any written cachelines after
1385 * writing if needs_clflush is set.
1388 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1389 bool page_do_bit17_swizzling,
1390 bool needs_clflush_before,
1391 bool needs_clflush_after)
1396 if (!page_do_bit17_swizzling) {
1397 char *vaddr = kmap_atomic(page);
1399 if (needs_clflush_before)
1400 drm_clflush_virt_range(vaddr + offset, len);
1401 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1402 if (needs_clflush_after)
1403 drm_clflush_virt_range(vaddr + offset, len);
1405 kunmap_atomic(vaddr);
1410 return shmem_pwrite_slow(page, offset, len, user_data,
1411 page_do_bit17_swizzling,
1412 needs_clflush_before,
1413 needs_clflush_after);
1417 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1418 const struct drm_i915_gem_pwrite *args)
1420 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1421 void __user *user_data;
1423 unsigned int obj_do_bit17_swizzling;
1424 unsigned int partial_cacheline_write;
1425 unsigned int needs_clflush;
1426 unsigned int offset, idx;
1429 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1433 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1434 mutex_unlock(&i915->drm.struct_mutex);
1438 obj_do_bit17_swizzling = 0;
1439 if (i915_gem_object_needs_bit17_swizzle(obj))
1440 obj_do_bit17_swizzling = BIT(17);
1442 /* If we don't overwrite a cacheline completely we need to be
1443 * careful to have up-to-date data by first clflushing. Don't
1444 * overcomplicate things and flush the entire patch.
1446 partial_cacheline_write = 0;
1447 if (needs_clflush & CLFLUSH_BEFORE)
1448 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1450 user_data = u64_to_user_ptr(args->data_ptr);
1451 remain = args->size;
1452 offset = offset_in_page(args->offset);
1453 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1454 struct page *page = i915_gem_object_get_page(obj, idx);
1458 if (offset + length > PAGE_SIZE)
1459 length = PAGE_SIZE - offset;
1461 ret = shmem_pwrite(page, offset, length, user_data,
1462 page_to_phys(page) & obj_do_bit17_swizzling,
1463 (offset | length) & partial_cacheline_write,
1464 needs_clflush & CLFLUSH_AFTER);
1469 user_data += length;
1473 intel_fb_obj_flush(obj, ORIGIN_CPU);
1474 i915_gem_obj_finish_shmem_access(obj);
1479 * Writes data to the object referenced by handle.
1481 * @data: ioctl data blob
1484 * On error, the contents of the buffer that were to be modified are undefined.
1487 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1488 struct drm_file *file)
1490 struct drm_i915_gem_pwrite *args = data;
1491 struct drm_i915_gem_object *obj;
1494 if (args->size == 0)
1497 if (!access_ok(VERIFY_READ,
1498 u64_to_user_ptr(args->data_ptr),
1502 obj = i915_gem_object_lookup(file, args->handle);
1506 /* Bounds check destination. */
1507 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1512 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1515 if (obj->ops->pwrite)
1516 ret = obj->ops->pwrite(obj, args);
1520 ret = i915_gem_object_wait(obj,
1521 I915_WAIT_INTERRUPTIBLE |
1523 MAX_SCHEDULE_TIMEOUT,
1524 to_rps_client(file));
1528 ret = i915_gem_object_pin_pages(obj);
1533 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1534 * it would end up going through the fenced access, and we'll get
1535 * different detiling behavior between reading and writing.
1536 * pread/pwrite currently are reading and writing from the CPU
1537 * perspective, requiring manual detiling by the client.
1539 if (!i915_gem_object_has_struct_page(obj) ||
1540 cpu_write_needs_clflush(obj))
1541 /* Note that the gtt paths might fail with non-page-backed user
1542 * pointers (e.g. gtt mappings when moving data between
1543 * textures). Fallback to the shmem path in that case.
1545 ret = i915_gem_gtt_pwrite_fast(obj, args);
1547 if (ret == -EFAULT || ret == -ENOSPC) {
1548 if (obj->phys_handle)
1549 ret = i915_gem_phys_pwrite(obj, args, file);
1551 ret = i915_gem_shmem_pwrite(obj, args);
1554 i915_gem_object_unpin_pages(obj);
1556 i915_gem_object_put(obj);
1560 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1562 struct drm_i915_private *i915;
1563 struct list_head *list;
1564 struct i915_vma *vma;
1566 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1567 if (!i915_vma_is_ggtt(vma))
1570 if (i915_vma_is_active(vma))
1573 if (!drm_mm_node_allocated(&vma->node))
1576 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1579 i915 = to_i915(obj->base.dev);
1580 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1581 list_move_tail(&obj->global_link, list);
1585 * Called when user space prepares to use an object with the CPU, either
1586 * through the mmap ioctl's mapping or a GTT mapping.
1588 * @data: ioctl data blob
1592 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1593 struct drm_file *file)
1595 struct drm_i915_gem_set_domain *args = data;
1596 struct drm_i915_gem_object *obj;
1597 uint32_t read_domains = args->read_domains;
1598 uint32_t write_domain = args->write_domain;
1601 /* Only handle setting domains to types used by the CPU. */
1602 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1605 /* Having something in the write domain implies it's in the read
1606 * domain, and only that read domain. Enforce that in the request.
1608 if (write_domain != 0 && read_domains != write_domain)
1611 obj = i915_gem_object_lookup(file, args->handle);
1615 /* Try to flush the object off the GPU without holding the lock.
1616 * We will repeat the flush holding the lock in the normal manner
1617 * to catch cases where we are gazumped.
1619 err = i915_gem_object_wait(obj,
1620 I915_WAIT_INTERRUPTIBLE |
1621 (write_domain ? I915_WAIT_ALL : 0),
1622 MAX_SCHEDULE_TIMEOUT,
1623 to_rps_client(file));
1627 /* Flush and acquire obj->pages so that we are coherent through
1628 * direct access in memory with previous cached writes through
1629 * shmemfs and that our cache domain tracking remains valid.
1630 * For example, if the obj->filp was moved to swap without us
1631 * being notified and releasing the pages, we would mistakenly
1632 * continue to assume that the obj remained out of the CPU cached
1635 err = i915_gem_object_pin_pages(obj);
1639 err = i915_mutex_lock_interruptible(dev);
1643 if (read_domains & I915_GEM_DOMAIN_WC)
1644 err = i915_gem_object_set_to_wc_domain(obj, write_domain);
1645 else if (read_domains & I915_GEM_DOMAIN_GTT)
1646 err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
1648 err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
1650 /* And bump the LRU for this access */
1651 i915_gem_object_bump_inactive_ggtt(obj);
1653 mutex_unlock(&dev->struct_mutex);
1655 if (write_domain != 0)
1656 intel_fb_obj_invalidate(obj,
1657 fb_write_origin(obj, write_domain));
1660 i915_gem_object_unpin_pages(obj);
1662 i915_gem_object_put(obj);
1667 * Called when user space has done writes to this buffer
1669 * @data: ioctl data blob
1673 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1674 struct drm_file *file)
1676 struct drm_i915_gem_sw_finish *args = data;
1677 struct drm_i915_gem_object *obj;
1679 obj = i915_gem_object_lookup(file, args->handle);
1683 /* Pinned buffers may be scanout, so flush the cache */
1684 i915_gem_object_flush_if_display(obj);
1685 i915_gem_object_put(obj);
1691 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1694 * @data: ioctl data blob
1697 * While the mapping holds a reference on the contents of the object, it doesn't
1698 * imply a ref on the object itself.
1702 * DRM driver writers who look a this function as an example for how to do GEM
1703 * mmap support, please don't implement mmap support like here. The modern way
1704 * to implement DRM mmap support is with an mmap offset ioctl (like
1705 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1706 * That way debug tooling like valgrind will understand what's going on, hiding
1707 * the mmap call in a driver private ioctl will break that. The i915 driver only
1708 * does cpu mmaps this way because we didn't know better.
1711 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1712 struct drm_file *file)
1714 struct drm_i915_gem_mmap *args = data;
1715 struct drm_i915_gem_object *obj;
1718 if (args->flags & ~(I915_MMAP_WC))
1721 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1724 obj = i915_gem_object_lookup(file, args->handle);
1728 /* prime objects have no backing filp to GEM mmap
1731 if (!obj->base.filp) {
1732 i915_gem_object_put(obj);
1736 addr = vm_mmap(obj->base.filp, 0, args->size,
1737 PROT_READ | PROT_WRITE, MAP_SHARED,
1739 if (args->flags & I915_MMAP_WC) {
1740 struct mm_struct *mm = current->mm;
1741 struct vm_area_struct *vma;
1743 if (down_write_killable(&mm->mmap_sem)) {
1744 i915_gem_object_put(obj);
1747 vma = find_vma(mm, addr);
1750 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1753 up_write(&mm->mmap_sem);
1755 /* This may race, but that's ok, it only gets set */
1756 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1758 i915_gem_object_put(obj);
1759 if (IS_ERR((void *)addr))
1762 args->addr_ptr = (uint64_t) addr;
1767 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1769 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1773 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1775 * A history of the GTT mmap interface:
1777 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1778 * aligned and suitable for fencing, and still fit into the available
1779 * mappable space left by the pinned display objects. A classic problem
1780 * we called the page-fault-of-doom where we would ping-pong between
1781 * two objects that could not fit inside the GTT and so the memcpy
1782 * would page one object in at the expense of the other between every
1785 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1786 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1787 * object is too large for the available space (or simply too large
1788 * for the mappable aperture!), a view is created instead and faulted
1789 * into userspace. (This view is aligned and sized appropriately for
1792 * 2 - Recognise WC as a separate cache domain so that we can flush the
1793 * delayed writes via GTT before performing direct access via WC.
1797 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1798 * hangs on some architectures, corruption on others. An attempt to service
1799 * a GTT page fault from a snoopable object will generate a SIGBUS.
1801 * * the object must be able to fit into RAM (physical memory, though no
1802 * limited to the mappable aperture).
1807 * * a new GTT page fault will synchronize rendering from the GPU and flush
1808 * all data to system memory. Subsequent access will not be synchronized.
1810 * * all mappings are revoked on runtime device suspend.
1812 * * there are only 8, 16 or 32 fence registers to share between all users
1813 * (older machines require fence register for display and blitter access
1814 * as well). Contention of the fence registers will cause the previous users
1815 * to be unmapped and any new access will generate new page faults.
1817 * * running out of memory while servicing a fault may generate a SIGBUS,
1818 * rather than the expected SIGSEGV.
1820 int i915_gem_mmap_gtt_version(void)
1825 static inline struct i915_ggtt_view
1826 compute_partial_view(struct drm_i915_gem_object *obj,
1827 pgoff_t page_offset,
1830 struct i915_ggtt_view view;
1832 if (i915_gem_object_is_tiled(obj))
1833 chunk = roundup(chunk, tile_row_pages(obj));
1835 view.type = I915_GGTT_VIEW_PARTIAL;
1836 view.partial.offset = rounddown(page_offset, chunk);
1838 min_t(unsigned int, chunk,
1839 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1841 /* If the partial covers the entire object, just create a normal VMA. */
1842 if (chunk >= obj->base.size >> PAGE_SHIFT)
1843 view.type = I915_GGTT_VIEW_NORMAL;
1849 * i915_gem_fault - fault a page into the GTT
1852 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1853 * from userspace. The fault handler takes care of binding the object to
1854 * the GTT (if needed), allocating and programming a fence register (again,
1855 * only if needed based on whether the old reg is still valid or the object
1856 * is tiled) and inserting a new PTE into the faulting process.
1858 * Note that the faulting process may involve evicting existing objects
1859 * from the GTT and/or fence registers to make room. So performance may
1860 * suffer if the GTT working set is large or there are few fence registers
1863 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1864 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1866 int i915_gem_fault(struct vm_fault *vmf)
1868 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1869 struct vm_area_struct *area = vmf->vma;
1870 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1871 struct drm_device *dev = obj->base.dev;
1872 struct drm_i915_private *dev_priv = to_i915(dev);
1873 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1874 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1875 struct i915_vma *vma;
1876 pgoff_t page_offset;
1880 /* We don't use vmf->pgoff since that has the fake offset */
1881 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1883 trace_i915_gem_object_fault(obj, page_offset, true, write);
1885 /* Try to flush the object off the GPU first without holding the lock.
1886 * Upon acquiring the lock, we will perform our sanity checks and then
1887 * repeat the flush holding the lock in the normal manner to catch cases
1888 * where we are gazumped.
1890 ret = i915_gem_object_wait(obj,
1891 I915_WAIT_INTERRUPTIBLE,
1892 MAX_SCHEDULE_TIMEOUT,
1897 ret = i915_gem_object_pin_pages(obj);
1901 intel_runtime_pm_get(dev_priv);
1903 ret = i915_mutex_lock_interruptible(dev);
1907 /* Access to snoopable pages through the GTT is incoherent. */
1908 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1913 /* If the object is smaller than a couple of partial vma, it is
1914 * not worth only creating a single partial vma - we may as well
1915 * clear enough space for the full object.
1917 flags = PIN_MAPPABLE;
1918 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1919 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1921 /* Now pin it into the GTT as needed */
1922 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1924 /* Use a partial view if it is bigger than available space */
1925 struct i915_ggtt_view view =
1926 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
1928 /* Userspace is now writing through an untracked VMA, abandon
1929 * all hope that the hardware is able to track future writes.
1931 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1933 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1940 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1944 ret = i915_vma_get_fence(vma);
1948 /* Mark as being mmapped into userspace for later revocation */
1949 assert_rpm_wakelock_held(dev_priv);
1950 if (list_empty(&obj->userfault_link))
1951 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1953 /* Finally, remap it using the new GTT offset */
1954 ret = remap_io_mapping(area,
1955 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
1956 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1957 min_t(u64, vma->size, area->vm_end - area->vm_start),
1961 __i915_vma_unpin(vma);
1963 mutex_unlock(&dev->struct_mutex);
1965 intel_runtime_pm_put(dev_priv);
1966 i915_gem_object_unpin_pages(obj);
1971 * We eat errors when the gpu is terminally wedged to avoid
1972 * userspace unduly crashing (gl has no provisions for mmaps to
1973 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1974 * and so needs to be reported.
1976 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1977 ret = VM_FAULT_SIGBUS;
1982 * EAGAIN means the gpu is hung and we'll wait for the error
1983 * handler to reset everything when re-faulting in
1984 * i915_mutex_lock_interruptible.
1991 * EBUSY is ok: this just means that another thread
1992 * already did the job.
1994 ret = VM_FAULT_NOPAGE;
2001 ret = VM_FAULT_SIGBUS;
2004 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2005 ret = VM_FAULT_SIGBUS;
2012 * i915_gem_release_mmap - remove physical page mappings
2013 * @obj: obj in question
2015 * Preserve the reservation of the mmapping with the DRM core code, but
2016 * relinquish ownership of the pages back to the system.
2018 * It is vital that we remove the page mapping if we have mapped a tiled
2019 * object through the GTT and then lose the fence register due to
2020 * resource pressure. Similarly if the object has been moved out of the
2021 * aperture, than pages mapped into userspace must be revoked. Removing the
2022 * mapping will then trigger a page fault on the next user access, allowing
2023 * fixup by i915_gem_fault().
2026 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2028 struct drm_i915_private *i915 = to_i915(obj->base.dev);
2030 /* Serialisation between user GTT access and our code depends upon
2031 * revoking the CPU's PTE whilst the mutex is held. The next user
2032 * pagefault then has to wait until we release the mutex.
2034 * Note that RPM complicates somewhat by adding an additional
2035 * requirement that operations to the GGTT be made holding the RPM
2038 lockdep_assert_held(&i915->drm.struct_mutex);
2039 intel_runtime_pm_get(i915);
2041 if (list_empty(&obj->userfault_link))
2044 list_del_init(&obj->userfault_link);
2045 drm_vma_node_unmap(&obj->base.vma_node,
2046 obj->base.dev->anon_inode->i_mapping);
2048 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2049 * memory transactions from userspace before we return. The TLB
2050 * flushing implied above by changing the PTE above *should* be
2051 * sufficient, an extra barrier here just provides us with a bit
2052 * of paranoid documentation about our requirement to serialise
2053 * memory writes before touching registers / GSM.
2058 intel_runtime_pm_put(i915);
2061 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
2063 struct drm_i915_gem_object *obj, *on;
2067 * Only called during RPM suspend. All users of the userfault_list
2068 * must be holding an RPM wakeref to ensure that this can not
2069 * run concurrently with themselves (and use the struct_mutex for
2070 * protection between themselves).
2073 list_for_each_entry_safe(obj, on,
2074 &dev_priv->mm.userfault_list, userfault_link) {
2075 list_del_init(&obj->userfault_link);
2076 drm_vma_node_unmap(&obj->base.vma_node,
2077 obj->base.dev->anon_inode->i_mapping);
2080 /* The fence will be lost when the device powers down. If any were
2081 * in use by hardware (i.e. they are pinned), we should not be powering
2082 * down! All other fences will be reacquired by the user upon waking.
2084 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2085 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2087 /* Ideally we want to assert that the fence register is not
2088 * live at this point (i.e. that no piece of code will be
2089 * trying to write through fence + GTT, as that both violates
2090 * our tracking of activity and associated locking/barriers,
2091 * but also is illegal given that the hw is powered down).
2093 * Previously we used reg->pin_count as a "liveness" indicator.
2094 * That is not sufficient, and we need a more fine-grained
2095 * tool if we want to have a sanity check here.
2101 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2106 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2108 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2111 err = drm_gem_create_mmap_offset(&obj->base);
2115 /* Attempt to reap some mmap space from dead objects */
2117 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2121 i915_gem_drain_freed_objects(dev_priv);
2122 err = drm_gem_create_mmap_offset(&obj->base);
2126 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2131 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2133 drm_gem_free_mmap_offset(&obj->base);
2137 i915_gem_mmap_gtt(struct drm_file *file,
2138 struct drm_device *dev,
2142 struct drm_i915_gem_object *obj;
2145 obj = i915_gem_object_lookup(file, handle);
2149 ret = i915_gem_object_create_mmap_offset(obj);
2151 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2153 i915_gem_object_put(obj);
2158 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2160 * @data: GTT mapping ioctl data
2161 * @file: GEM object info
2163 * Simply returns the fake offset to userspace so it can mmap it.
2164 * The mmap call will end up in drm_gem_mmap(), which will set things
2165 * up so we can get faults in the handler above.
2167 * The fault handler will take care of binding the object into the GTT
2168 * (since it may have been evicted to make room for something), allocating
2169 * a fence register, and mapping the appropriate aperture address into
2173 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *file)
2176 struct drm_i915_gem_mmap_gtt *args = data;
2178 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2181 /* Immediately discard the backing storage */
2183 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2185 i915_gem_object_free_mmap_offset(obj);
2187 if (obj->base.filp == NULL)
2190 /* Our goal here is to return as much of the memory as
2191 * is possible back to the system as we are called from OOM.
2192 * To do this we must instruct the shmfs to drop all of its
2193 * backing pages, *now*.
2195 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2196 obj->mm.madv = __I915_MADV_PURGED;
2197 obj->mm.pages = ERR_PTR(-EFAULT);
2200 /* Try to discard unwanted pages */
2201 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2203 struct address_space *mapping;
2205 lockdep_assert_held(&obj->mm.lock);
2206 GEM_BUG_ON(obj->mm.pages);
2208 switch (obj->mm.madv) {
2209 case I915_MADV_DONTNEED:
2210 i915_gem_object_truncate(obj);
2211 case __I915_MADV_PURGED:
2215 if (obj->base.filp == NULL)
2218 mapping = obj->base.filp->f_mapping,
2219 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2223 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2224 struct sg_table *pages)
2226 struct sgt_iter sgt_iter;
2229 __i915_gem_object_release_shmem(obj, pages, true);
2231 i915_gem_gtt_finish_pages(obj, pages);
2233 if (i915_gem_object_needs_bit17_swizzle(obj))
2234 i915_gem_object_save_bit_17_swizzle(obj, pages);
2236 for_each_sgt_page(page, sgt_iter, pages) {
2238 set_page_dirty(page);
2240 if (obj->mm.madv == I915_MADV_WILLNEED)
2241 mark_page_accessed(page);
2245 obj->mm.dirty = false;
2247 sg_free_table(pages);
2251 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2253 struct radix_tree_iter iter;
2256 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2257 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2260 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2261 enum i915_mm_subclass subclass)
2263 struct sg_table *pages;
2265 if (i915_gem_object_has_pinned_pages(obj))
2268 GEM_BUG_ON(obj->bind_count);
2269 if (!READ_ONCE(obj->mm.pages))
2272 /* May be called by shrinker from within get_pages() (on another bo) */
2273 mutex_lock_nested(&obj->mm.lock, subclass);
2274 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2277 /* ->put_pages might need to allocate memory for the bit17 swizzle
2278 * array, hence protect them from being reaped by removing them from gtt
2280 pages = fetch_and_zero(&obj->mm.pages);
2283 if (obj->mm.mapping) {
2286 ptr = page_mask_bits(obj->mm.mapping);
2287 if (is_vmalloc_addr(ptr))
2290 kunmap(kmap_to_page(ptr));
2292 obj->mm.mapping = NULL;
2295 __i915_gem_object_reset_page_iter(obj);
2298 obj->ops->put_pages(obj, pages);
2301 mutex_unlock(&obj->mm.lock);
2304 static bool i915_sg_trim(struct sg_table *orig_st)
2306 struct sg_table new_st;
2307 struct scatterlist *sg, *new_sg;
2310 if (orig_st->nents == orig_st->orig_nents)
2313 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2316 new_sg = new_st.sgl;
2317 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2318 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2319 /* called before being DMA mapped, no need to copy sg->dma_* */
2320 new_sg = sg_next(new_sg);
2322 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2324 sg_free_table(orig_st);
2330 static struct sg_table *
2331 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2333 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2334 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2336 struct address_space *mapping;
2337 struct sg_table *st;
2338 struct scatterlist *sg;
2339 struct sgt_iter sgt_iter;
2341 unsigned long last_pfn = 0; /* suppress gcc warning */
2342 unsigned int max_segment;
2346 /* Assert that the object is not currently in any GPU domain. As it
2347 * wasn't in the GTT, there shouldn't be any way it could have been in
2350 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2351 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2353 max_segment = swiotlb_max_segment();
2355 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2357 st = kmalloc(sizeof(*st), GFP_KERNEL);
2359 return ERR_PTR(-ENOMEM);
2362 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2364 return ERR_PTR(-ENOMEM);
2367 /* Get the list of pages out of our struct file. They'll be pinned
2368 * at this point until we release them.
2370 * Fail silently without starting the shrinker
2372 mapping = obj->base.filp->f_mapping;
2373 noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM);
2374 noreclaim |= __GFP_NORETRY | __GFP_NOWARN;
2378 for (i = 0; i < page_count; i++) {
2379 const unsigned int shrink[] = {
2380 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE,
2383 gfp_t gfp = noreclaim;
2386 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2387 if (likely(!IS_ERR(page)))
2391 ret = PTR_ERR(page);
2395 i915_gem_shrink(dev_priv, 2 * page_count, *s++);
2398 /* We've tried hard to allocate the memory by reaping
2399 * our own buffer, now let the real VM do its job and
2400 * go down in flames if truly OOM.
2402 * However, since graphics tend to be disposable,
2403 * defer the oom here by reporting the ENOMEM back
2407 /* reclaim and warn, but no oom */
2408 gfp = mapping_gfp_mask(mapping);
2410 /* Our bo are always dirty and so we require
2411 * kswapd to reclaim our pages (direct reclaim
2412 * does not effectively begin pageout of our
2413 * buffers on its own). However, direct reclaim
2414 * only waits for kswapd when under allocation
2415 * congestion. So as a result __GFP_RECLAIM is
2416 * unreliable and fails to actually reclaim our
2417 * dirty pages -- unless you try over and over
2418 * again with !__GFP_NORETRY. However, we still
2419 * want to fail this allocation rather than
2420 * trigger the out-of-memory killer and for
2421 * this we want __GFP_RETRY_MAYFAIL.
2423 gfp |= __GFP_RETRY_MAYFAIL;
2428 sg->length >= max_segment ||
2429 page_to_pfn(page) != last_pfn + 1) {
2433 sg_set_page(sg, page, PAGE_SIZE, 0);
2435 sg->length += PAGE_SIZE;
2437 last_pfn = page_to_pfn(page);
2439 /* Check that the i965g/gm workaround works. */
2440 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2442 if (sg) /* loop terminated early; short sg table */
2445 /* Trim unused sg entries to avoid wasting memory. */
2448 ret = i915_gem_gtt_prepare_pages(obj, st);
2450 /* DMA remapping failed? One possible cause is that
2451 * it could not reserve enough large entries, asking
2452 * for PAGE_SIZE chunks instead may be helpful.
2454 if (max_segment > PAGE_SIZE) {
2455 for_each_sgt_page(page, sgt_iter, st)
2459 max_segment = PAGE_SIZE;
2462 dev_warn(&dev_priv->drm.pdev->dev,
2463 "Failed to DMA remap %lu pages\n",
2469 if (i915_gem_object_needs_bit17_swizzle(obj))
2470 i915_gem_object_do_bit_17_swizzle(obj, st);
2477 for_each_sgt_page(page, sgt_iter, st)
2482 /* shmemfs first checks if there is enough memory to allocate the page
2483 * and reports ENOSPC should there be insufficient, along with the usual
2484 * ENOMEM for a genuine allocation failure.
2486 * We use ENOSPC in our driver to mean that we have run out of aperture
2487 * space and so want to translate the error from shmemfs back to our
2488 * usual understanding of ENOMEM.
2493 return ERR_PTR(ret);
2496 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2497 struct sg_table *pages)
2499 lockdep_assert_held(&obj->mm.lock);
2501 obj->mm.get_page.sg_pos = pages->sgl;
2502 obj->mm.get_page.sg_idx = 0;
2504 obj->mm.pages = pages;
2506 if (i915_gem_object_is_tiled(obj) &&
2507 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2508 GEM_BUG_ON(obj->mm.quirked);
2509 __i915_gem_object_pin_pages(obj);
2510 obj->mm.quirked = true;
2514 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2516 struct sg_table *pages;
2518 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2520 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2521 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2525 pages = obj->ops->get_pages(obj);
2526 if (unlikely(IS_ERR(pages)))
2527 return PTR_ERR(pages);
2529 __i915_gem_object_set_pages(obj, pages);
2533 /* Ensure that the associated pages are gathered from the backing storage
2534 * and pinned into our object. i915_gem_object_pin_pages() may be called
2535 * multiple times before they are released by a single call to
2536 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2537 * either as a result of memory pressure (reaping pages under the shrinker)
2538 * or as the object is itself released.
2540 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2544 err = mutex_lock_interruptible(&obj->mm.lock);
2548 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2549 err = ____i915_gem_object_get_pages(obj);
2553 smp_mb__before_atomic();
2555 atomic_inc(&obj->mm.pages_pin_count);
2558 mutex_unlock(&obj->mm.lock);
2562 /* The 'mapping' part of i915_gem_object_pin_map() below */
2563 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2564 enum i915_map_type type)
2566 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2567 struct sg_table *sgt = obj->mm.pages;
2568 struct sgt_iter sgt_iter;
2570 struct page *stack_pages[32];
2571 struct page **pages = stack_pages;
2572 unsigned long i = 0;
2576 /* A single page can always be kmapped */
2577 if (n_pages == 1 && type == I915_MAP_WB)
2578 return kmap(sg_page(sgt->sgl));
2580 if (n_pages > ARRAY_SIZE(stack_pages)) {
2581 /* Too big for stack -- allocate temporary array instead */
2582 pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_TEMPORARY);
2587 for_each_sgt_page(page, sgt_iter, sgt)
2590 /* Check that we have the expected number of pages */
2591 GEM_BUG_ON(i != n_pages);
2595 pgprot = PAGE_KERNEL;
2598 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2601 addr = vmap(pages, n_pages, 0, pgprot);
2603 if (pages != stack_pages)
2609 /* get, pin, and map the pages of the object into kernel space */
2610 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2611 enum i915_map_type type)
2613 enum i915_map_type has_type;
2618 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2620 ret = mutex_lock_interruptible(&obj->mm.lock);
2622 return ERR_PTR(ret);
2625 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2626 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2627 ret = ____i915_gem_object_get_pages(obj);
2631 smp_mb__before_atomic();
2633 atomic_inc(&obj->mm.pages_pin_count);
2636 GEM_BUG_ON(!obj->mm.pages);
2638 ptr = page_unpack_bits(obj->mm.mapping, &has_type);
2639 if (ptr && has_type != type) {
2645 if (is_vmalloc_addr(ptr))
2648 kunmap(kmap_to_page(ptr));
2650 ptr = obj->mm.mapping = NULL;
2654 ptr = i915_gem_object_map(obj, type);
2660 obj->mm.mapping = page_pack_bits(ptr, type);
2664 mutex_unlock(&obj->mm.lock);
2668 atomic_dec(&obj->mm.pages_pin_count);
2675 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
2676 const struct drm_i915_gem_pwrite *arg)
2678 struct address_space *mapping = obj->base.filp->f_mapping;
2679 char __user *user_data = u64_to_user_ptr(arg->data_ptr);
2683 /* Before we instantiate/pin the backing store for our use, we
2684 * can prepopulate the shmemfs filp efficiently using a write into
2685 * the pagecache. We avoid the penalty of instantiating all the
2686 * pages, important if the user is just writing to a few and never
2687 * uses the object on the GPU, and using a direct write into shmemfs
2688 * allows it to avoid the cost of retrieving a page (either swapin
2689 * or clearing-before-use) before it is overwritten.
2691 if (READ_ONCE(obj->mm.pages))
2694 /* Before the pages are instantiated the object is treated as being
2695 * in the CPU domain. The pages will be clflushed as required before
2696 * use, and we can freely write into the pages directly. If userspace
2697 * races pwrite with any other operation; corruption will ensue -
2698 * that is userspace's prerogative!
2702 offset = arg->offset;
2703 pg = offset_in_page(offset);
2706 unsigned int len, unwritten;
2711 len = PAGE_SIZE - pg;
2715 err = pagecache_write_begin(obj->base.filp, mapping,
2722 unwritten = copy_from_user(vaddr + pg, user_data, len);
2725 err = pagecache_write_end(obj->base.filp, mapping,
2726 offset, len, len - unwritten,
2743 static bool ban_context(const struct i915_gem_context *ctx)
2745 return (i915_gem_context_is_bannable(ctx) &&
2746 ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD);
2749 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
2751 ctx->guilty_count++;
2752 ctx->ban_score += CONTEXT_SCORE_GUILTY;
2753 if (ban_context(ctx))
2754 i915_gem_context_set_banned(ctx);
2756 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2757 ctx->name, ctx->ban_score,
2758 yesno(i915_gem_context_is_banned(ctx)));
2760 if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv))
2763 ctx->file_priv->context_bans++;
2764 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2765 ctx->name, ctx->file_priv->context_bans);
2768 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
2770 ctx->active_count++;
2773 struct drm_i915_gem_request *
2774 i915_gem_find_active_request(struct intel_engine_cs *engine)
2776 struct drm_i915_gem_request *request, *active = NULL;
2777 unsigned long flags;
2779 /* We are called by the error capture and reset at a random
2780 * point in time. In particular, note that neither is crucially
2781 * ordered with an interrupt. After a hang, the GPU is dead and we
2782 * assume that no more writes can happen (we waited long enough for
2783 * all writes that were in transaction to be flushed) - adding an
2784 * extra delay for a recent interrupt is pointless. Hence, we do
2785 * not need an engine->irq_seqno_barrier() before the seqno reads.
2787 spin_lock_irqsave(&engine->timeline->lock, flags);
2788 list_for_each_entry(request, &engine->timeline->requests, link) {
2789 if (__i915_gem_request_completed(request,
2790 request->global_seqno))
2793 GEM_BUG_ON(request->engine != engine);
2794 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
2795 &request->fence.flags));
2800 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2805 static bool engine_stalled(struct intel_engine_cs *engine)
2807 if (!engine->hangcheck.stalled)
2810 /* Check for possible seqno movement after hang declaration */
2811 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2812 DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2820 * Ensure irq handler finishes, and not run again.
2821 * Also return the active request so that we only search for it once.
2823 struct drm_i915_gem_request *
2824 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
2826 struct drm_i915_gem_request *request = NULL;
2828 /* Prevent the signaler thread from updating the request
2829 * state (by calling dma_fence_signal) as we are processing
2830 * the reset. The write from the GPU of the seqno is
2831 * asynchronous and the signaler thread may see a different
2832 * value to us and declare the request complete, even though
2833 * the reset routine have picked that request as the active
2834 * (incomplete) request. This conflict is not handled
2837 kthread_park(engine->breadcrumbs.signaler);
2839 /* Prevent request submission to the hardware until we have
2840 * completed the reset in i915_gem_reset_finish(). If a request
2841 * is completed by one engine, it may then queue a request
2842 * to a second via its engine->irq_tasklet *just* as we are
2843 * calling engine->init_hw() and also writing the ELSP.
2844 * Turning off the engine->irq_tasklet until the reset is over
2845 * prevents the race.
2847 tasklet_kill(&engine->irq_tasklet);
2848 tasklet_disable(&engine->irq_tasklet);
2850 if (engine->irq_seqno_barrier)
2851 engine->irq_seqno_barrier(engine);
2853 if (engine_stalled(engine)) {
2854 request = i915_gem_find_active_request(engine);
2855 if (request && request->fence.error == -EIO)
2856 request = ERR_PTR(-EIO); /* Previous reset failed! */
2862 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
2864 struct intel_engine_cs *engine;
2865 struct drm_i915_gem_request *request;
2866 enum intel_engine_id id;
2869 for_each_engine(engine, dev_priv, id) {
2870 request = i915_gem_reset_prepare_engine(engine);
2871 if (IS_ERR(request)) {
2872 err = PTR_ERR(request);
2876 engine->hangcheck.active_request = request;
2879 i915_gem_revoke_fences(dev_priv);
2884 static void skip_request(struct drm_i915_gem_request *request)
2886 void *vaddr = request->ring->vaddr;
2889 /* As this request likely depends on state from the lost
2890 * context, clear out all the user operations leaving the
2891 * breadcrumb at the end (so we get the fence notifications).
2893 head = request->head;
2894 if (request->postfix < head) {
2895 memset(vaddr + head, 0, request->ring->size - head);
2898 memset(vaddr + head, 0, request->postfix - head);
2900 dma_fence_set_error(&request->fence, -EIO);
2903 static void engine_skip_context(struct drm_i915_gem_request *request)
2905 struct intel_engine_cs *engine = request->engine;
2906 struct i915_gem_context *hung_ctx = request->ctx;
2907 struct intel_timeline *timeline;
2908 unsigned long flags;
2910 timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
2912 spin_lock_irqsave(&engine->timeline->lock, flags);
2913 spin_lock(&timeline->lock);
2915 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2916 if (request->ctx == hung_ctx)
2917 skip_request(request);
2919 list_for_each_entry(request, &timeline->requests, link)
2920 skip_request(request);
2922 spin_unlock(&timeline->lock);
2923 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2926 /* Returns true if the request was guilty of hang */
2927 static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
2929 /* Read once and return the resolution */
2930 const bool guilty = !i915_gem_request_completed(request);
2932 /* The guilty request will get skipped on a hung engine.
2934 * Users of client default contexts do not rely on logical
2935 * state preserved between batches so it is safe to execute
2936 * queued requests following the hang. Non default contexts
2937 * rely on preserved state, so skipping a batch loses the
2938 * evolution of the state and it needs to be considered corrupted.
2939 * Executing more queued batches on top of corrupted state is
2940 * risky. But we take the risk by trying to advance through
2941 * the queued requests in order to make the client behaviour
2942 * more predictable around resets, by not throwing away random
2943 * amount of batches it has prepared for execution. Sophisticated
2944 * clients can use gem_reset_stats_ioctl and dma fence status
2945 * (exported via sync_file info ioctl on explicit fences) to observe
2946 * when it loses the context state and should rebuild accordingly.
2948 * The context ban, and ultimately the client ban, mechanism are safety
2949 * valves if client submission ends up resulting in nothing more than
2954 i915_gem_context_mark_guilty(request->ctx);
2955 skip_request(request);
2957 i915_gem_context_mark_innocent(request->ctx);
2958 dma_fence_set_error(&request->fence, -EAGAIN);
2964 void i915_gem_reset_engine(struct intel_engine_cs *engine,
2965 struct drm_i915_gem_request *request)
2967 if (request && i915_gem_reset_request(request)) {
2968 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2969 engine->name, request->global_seqno);
2971 /* If this context is now banned, skip all pending requests. */
2972 if (i915_gem_context_is_banned(request->ctx))
2973 engine_skip_context(request);
2976 /* Setup the CS to resume from the breadcrumb of the hung request */
2977 engine->reset_hw(engine, request);
2980 void i915_gem_reset(struct drm_i915_private *dev_priv)
2982 struct intel_engine_cs *engine;
2983 enum intel_engine_id id;
2985 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2987 i915_gem_retire_requests(dev_priv);
2989 for_each_engine(engine, dev_priv, id) {
2990 struct i915_gem_context *ctx;
2992 i915_gem_reset_engine(engine, engine->hangcheck.active_request);
2993 ctx = fetch_and_zero(&engine->last_retired_context);
2995 engine->context_unpin(engine, ctx);
2998 i915_gem_restore_fences(dev_priv);
3000 if (dev_priv->gt.awake) {
3001 intel_sanitize_gt_powersave(dev_priv);
3002 intel_enable_gt_powersave(dev_priv);
3003 if (INTEL_GEN(dev_priv) >= 6)
3004 gen6_rps_busy(dev_priv);
3008 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
3010 tasklet_enable(&engine->irq_tasklet);
3011 kthread_unpark(engine->breadcrumbs.signaler);
3014 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
3016 struct intel_engine_cs *engine;
3017 enum intel_engine_id id;
3019 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3021 for_each_engine(engine, dev_priv, id) {
3022 engine->hangcheck.active_request = NULL;
3023 i915_gem_reset_finish_engine(engine);
3027 static void nop_submit_request(struct drm_i915_gem_request *request)
3029 dma_fence_set_error(&request->fence, -EIO);
3030 i915_gem_request_submit(request);
3031 intel_engine_init_global_seqno(request->engine, request->global_seqno);
3034 static void engine_set_wedged(struct intel_engine_cs *engine)
3036 struct drm_i915_gem_request *request;
3037 unsigned long flags;
3039 /* We need to be sure that no thread is running the old callback as
3040 * we install the nop handler (otherwise we would submit a request
3041 * to hardware that will never complete). In order to prevent this
3042 * race, we wait until the machine is idle before making the swap
3043 * (using stop_machine()).
3045 engine->submit_request = nop_submit_request;
3047 /* Mark all executing requests as skipped */
3048 spin_lock_irqsave(&engine->timeline->lock, flags);
3049 list_for_each_entry(request, &engine->timeline->requests, link)
3050 if (!i915_gem_request_completed(request))
3051 dma_fence_set_error(&request->fence, -EIO);
3052 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3055 * Clear the execlists queue up before freeing the requests, as those
3056 * are the ones that keep the context and ringbuffer backing objects
3060 if (i915.enable_execlists) {
3061 struct execlist_port *port = engine->execlist_port;
3062 unsigned long flags;
3065 spin_lock_irqsave(&engine->timeline->lock, flags);
3067 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
3068 i915_gem_request_put(port_request(&port[n]));
3069 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
3070 engine->execlist_queue = RB_ROOT;
3071 engine->execlist_first = NULL;
3073 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3075 /* The port is checked prior to scheduling a tasklet, but
3076 * just in case we have suspended the tasklet to do the
3077 * wedging make sure that when it wakes, it decides there
3078 * is no work to do by clearing the irq_posted bit.
3080 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
3083 /* Mark all pending requests as complete so that any concurrent
3084 * (lockless) lookup doesn't try and wait upon the request as we
3087 intel_engine_init_global_seqno(engine,
3088 intel_engine_last_submit(engine));
3091 static int __i915_gem_set_wedged_BKL(void *data)
3093 struct drm_i915_private *i915 = data;
3094 struct intel_engine_cs *engine;
3095 enum intel_engine_id id;
3097 set_bit(I915_WEDGED, &i915->gpu_error.flags);
3098 for_each_engine(engine, i915, id)
3099 engine_set_wedged(engine);
3104 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
3106 stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
3109 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
3111 struct i915_gem_timeline *tl;
3114 lockdep_assert_held(&i915->drm.struct_mutex);
3115 if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
3118 /* Before unwedging, make sure that all pending operations
3119 * are flushed and errored out - we may have requests waiting upon
3120 * third party fences. We marked all inflight requests as EIO, and
3121 * every execbuf since returned EIO, for consistency we want all
3122 * the currently pending requests to also be marked as EIO, which
3123 * is done inside our nop_submit_request - and so we must wait.
3125 * No more can be submitted until we reset the wedged bit.
3127 list_for_each_entry(tl, &i915->gt.timelines, link) {
3128 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3129 struct drm_i915_gem_request *rq;
3131 rq = i915_gem_active_peek(&tl->engine[i].last_request,
3132 &i915->drm.struct_mutex);
3136 /* We can't use our normal waiter as we want to
3137 * avoid recursively trying to handle the current
3138 * reset. The basic dma_fence_default_wait() installs
3139 * a callback for dma_fence_signal(), which is
3140 * triggered by our nop handler (indirectly, the
3141 * callback enables the signaler thread which is
3142 * woken by the nop_submit_request() advancing the seqno
3143 * and when the seqno passes the fence, the signaler
3144 * then signals the fence waking us up).
3146 if (dma_fence_default_wait(&rq->fence, true,
3147 MAX_SCHEDULE_TIMEOUT) < 0)
3152 /* Undo nop_submit_request. We prevent all new i915 requests from
3153 * being queued (by disallowing execbuf whilst wedged) so having
3154 * waited for all active requests above, we know the system is idle
3155 * and do not have to worry about a thread being inside
3156 * engine->submit_request() as we swap over. So unlike installing
3157 * the nop_submit_request on reset, we can do this from normal
3158 * context and do not require stop_machine().
3160 intel_engines_reset_default_submission(i915);
3161 i915_gem_contexts_lost(i915);
3163 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3164 clear_bit(I915_WEDGED, &i915->gpu_error.flags);
3170 i915_gem_retire_work_handler(struct work_struct *work)
3172 struct drm_i915_private *dev_priv =
3173 container_of(work, typeof(*dev_priv), gt.retire_work.work);
3174 struct drm_device *dev = &dev_priv->drm;
3176 /* Come back later if the device is busy... */
3177 if (mutex_trylock(&dev->struct_mutex)) {
3178 i915_gem_retire_requests(dev_priv);
3179 mutex_unlock(&dev->struct_mutex);
3182 /* Keep the retire handler running until we are finally idle.
3183 * We do not need to do this test under locking as in the worst-case
3184 * we queue the retire worker once too often.
3186 if (READ_ONCE(dev_priv->gt.awake)) {
3187 i915_queue_hangcheck(dev_priv);
3188 queue_delayed_work(dev_priv->wq,
3189 &dev_priv->gt.retire_work,
3190 round_jiffies_up_relative(HZ));
3195 i915_gem_idle_work_handler(struct work_struct *work)
3197 struct drm_i915_private *dev_priv =
3198 container_of(work, typeof(*dev_priv), gt.idle_work.work);
3199 struct drm_device *dev = &dev_priv->drm;
3200 bool rearm_hangcheck;
3202 if (!READ_ONCE(dev_priv->gt.awake))
3206 * Wait for last execlists context complete, but bail out in case a
3207 * new request is submitted.
3209 wait_for(intel_engines_are_idle(dev_priv), 10);
3210 if (READ_ONCE(dev_priv->gt.active_requests))
3214 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
3216 if (!mutex_trylock(&dev->struct_mutex)) {
3217 /* Currently busy, come back later */
3218 mod_delayed_work(dev_priv->wq,
3219 &dev_priv->gt.idle_work,
3220 msecs_to_jiffies(50));
3225 * New request retired after this work handler started, extend active
3226 * period until next instance of the work.
3228 if (work_pending(work))
3231 if (dev_priv->gt.active_requests)
3234 if (wait_for(intel_engines_are_idle(dev_priv), 10))
3235 DRM_ERROR("Timeout waiting for engines to idle\n");
3237 intel_engines_mark_idle(dev_priv);
3238 i915_gem_timelines_mark_idle(dev_priv);
3240 GEM_BUG_ON(!dev_priv->gt.awake);
3241 dev_priv->gt.awake = false;
3242 rearm_hangcheck = false;
3244 if (INTEL_GEN(dev_priv) >= 6)
3245 gen6_rps_idle(dev_priv);
3246 intel_runtime_pm_put(dev_priv);
3248 mutex_unlock(&dev->struct_mutex);
3251 if (rearm_hangcheck) {
3252 GEM_BUG_ON(!dev_priv->gt.awake);
3253 i915_queue_hangcheck(dev_priv);
3257 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3259 struct drm_i915_gem_object *obj = to_intel_bo(gem);
3260 struct drm_i915_file_private *fpriv = file->driver_priv;
3261 struct i915_vma *vma, *vn;
3263 mutex_lock(&obj->base.dev->struct_mutex);
3264 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
3265 if (vma->vm->file == fpriv)
3266 i915_vma_close(vma);
3268 vma = obj->vma_hashed;
3269 if (vma && vma->ctx->file_priv == fpriv)
3270 i915_vma_unlink_ctx(vma);
3272 if (i915_gem_object_is_active(obj) &&
3273 !i915_gem_object_has_active_reference(obj)) {
3274 i915_gem_object_set_active_reference(obj);
3275 i915_gem_object_get(obj);
3277 mutex_unlock(&obj->base.dev->struct_mutex);
3280 static unsigned long to_wait_timeout(s64 timeout_ns)
3283 return MAX_SCHEDULE_TIMEOUT;
3285 if (timeout_ns == 0)
3288 return nsecs_to_jiffies_timeout(timeout_ns);
3292 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3293 * @dev: drm device pointer
3294 * @data: ioctl data blob
3295 * @file: drm file pointer
3297 * Returns 0 if successful, else an error is returned with the remaining time in
3298 * the timeout parameter.
3299 * -ETIME: object is still busy after timeout
3300 * -ERESTARTSYS: signal interrupted the wait
3301 * -ENONENT: object doesn't exist
3302 * Also possible, but rare:
3303 * -EAGAIN: GPU wedged
3305 * -ENODEV: Internal IRQ fail
3306 * -E?: The add request failed
3308 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3309 * non-zero timeout parameter the wait ioctl will wait for the given number of
3310 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3311 * without holding struct_mutex the object may become re-busied before this
3312 * function completes. A similar but shorter * race condition exists in the busy
3316 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3318 struct drm_i915_gem_wait *args = data;
3319 struct drm_i915_gem_object *obj;
3323 if (args->flags != 0)
3326 obj = i915_gem_object_lookup(file, args->bo_handle);
3330 start = ktime_get();
3332 ret = i915_gem_object_wait(obj,
3333 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3334 to_wait_timeout(args->timeout_ns),
3335 to_rps_client(file));
3337 if (args->timeout_ns > 0) {
3338 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3339 if (args->timeout_ns < 0)
3340 args->timeout_ns = 0;
3343 * Apparently ktime isn't accurate enough and occasionally has a
3344 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3345 * things up to make the test happy. We allow up to 1 jiffy.
3347 * This is a regression from the timespec->ktime conversion.
3349 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3350 args->timeout_ns = 0;
3353 i915_gem_object_put(obj);
3357 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3361 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3362 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3370 static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)
3372 return wait_for(intel_engine_is_idle(engine), timeout_ms);
3375 static int wait_for_engines(struct drm_i915_private *i915)
3377 struct intel_engine_cs *engine;
3378 enum intel_engine_id id;
3380 for_each_engine(engine, i915, id) {
3381 if (GEM_WARN_ON(wait_for_engine(engine, 50))) {
3382 i915_gem_set_wedged(i915);
3386 GEM_BUG_ON(intel_engine_get_seqno(engine) !=
3387 intel_engine_last_submit(engine));
3393 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3397 /* If the device is asleep, we have no requests outstanding */
3398 if (!READ_ONCE(i915->gt.awake))
3401 if (flags & I915_WAIT_LOCKED) {
3402 struct i915_gem_timeline *tl;
3404 lockdep_assert_held(&i915->drm.struct_mutex);
3406 list_for_each_entry(tl, &i915->gt.timelines, link) {
3407 ret = wait_for_timeline(tl, flags);
3412 i915_gem_retire_requests(i915);
3413 GEM_BUG_ON(i915->gt.active_requests);
3415 ret = wait_for_engines(i915);
3417 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3423 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
3426 * We manually flush the CPU domain so that we can override and
3427 * force the flush for the display, and perform it asyncrhonously.
3429 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3430 if (obj->cache_dirty)
3431 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
3432 obj->base.write_domain = 0;
3435 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
3437 if (!READ_ONCE(obj->pin_display))
3440 mutex_lock(&obj->base.dev->struct_mutex);
3441 __i915_gem_object_flush_for_display(obj);
3442 mutex_unlock(&obj->base.dev->struct_mutex);
3446 * Moves a single object to the WC read, and possibly write domain.
3447 * @obj: object to act on
3448 * @write: ask for write access or read only
3450 * This function returns when the move is complete, including waiting on
3454 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
3458 lockdep_assert_held(&obj->base.dev->struct_mutex);
3460 ret = i915_gem_object_wait(obj,
3461 I915_WAIT_INTERRUPTIBLE |
3463 (write ? I915_WAIT_ALL : 0),
3464 MAX_SCHEDULE_TIMEOUT,
3469 if (obj->base.write_domain == I915_GEM_DOMAIN_WC)
3472 /* Flush and acquire obj->pages so that we are coherent through
3473 * direct access in memory with previous cached writes through
3474 * shmemfs and that our cache domain tracking remains valid.
3475 * For example, if the obj->filp was moved to swap without us
3476 * being notified and releasing the pages, we would mistakenly
3477 * continue to assume that the obj remained out of the CPU cached
3480 ret = i915_gem_object_pin_pages(obj);
3484 flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
3486 /* Serialise direct access to this object with the barriers for
3487 * coherent writes from the GPU, by effectively invalidating the
3488 * WC domain upon first access.
3490 if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0)
3493 /* It should now be out of any other write domains, and we can update
3494 * the domain values for our changes.
3496 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0);
3497 obj->base.read_domains |= I915_GEM_DOMAIN_WC;
3499 obj->base.read_domains = I915_GEM_DOMAIN_WC;
3500 obj->base.write_domain = I915_GEM_DOMAIN_WC;
3501 obj->mm.dirty = true;
3504 i915_gem_object_unpin_pages(obj);
3509 * Moves a single object to the GTT read, and possibly write domain.
3510 * @obj: object to act on
3511 * @write: ask for write access or read only
3513 * This function returns when the move is complete, including waiting on
3517 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3521 lockdep_assert_held(&obj->base.dev->struct_mutex);
3523 ret = i915_gem_object_wait(obj,
3524 I915_WAIT_INTERRUPTIBLE |
3526 (write ? I915_WAIT_ALL : 0),
3527 MAX_SCHEDULE_TIMEOUT,
3532 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3535 /* Flush and acquire obj->pages so that we are coherent through
3536 * direct access in memory with previous cached writes through
3537 * shmemfs and that our cache domain tracking remains valid.
3538 * For example, if the obj->filp was moved to swap without us
3539 * being notified and releasing the pages, we would mistakenly
3540 * continue to assume that the obj remained out of the CPU cached
3543 ret = i915_gem_object_pin_pages(obj);
3547 flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
3549 /* Serialise direct access to this object with the barriers for
3550 * coherent writes from the GPU, by effectively invalidating the
3551 * GTT domain upon first access.
3553 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3556 /* It should now be out of any other write domains, and we can update
3557 * the domain values for our changes.
3559 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3560 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3562 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3563 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3564 obj->mm.dirty = true;
3567 i915_gem_object_unpin_pages(obj);
3572 * Changes the cache-level of an object across all VMA.
3573 * @obj: object to act on
3574 * @cache_level: new cache level to set for the object
3576 * After this function returns, the object will be in the new cache-level
3577 * across all GTT and the contents of the backing storage will be coherent,
3578 * with respect to the new cache-level. In order to keep the backing storage
3579 * coherent for all users, we only allow a single cache level to be set
3580 * globally on the object and prevent it from being changed whilst the
3581 * hardware is reading from the object. That is if the object is currently
3582 * on the scanout it will be set to uncached (or equivalent display
3583 * cache coherency) and all non-MOCS GPU access will also be uncached so
3584 * that all direct access to the scanout remains coherent.
3586 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3587 enum i915_cache_level cache_level)
3589 struct i915_vma *vma;
3592 lockdep_assert_held(&obj->base.dev->struct_mutex);
3594 if (obj->cache_level == cache_level)
3597 /* Inspect the list of currently bound VMA and unbind any that would
3598 * be invalid given the new cache-level. This is principally to
3599 * catch the issue of the CS prefetch crossing page boundaries and
3600 * reading an invalid PTE on older architectures.
3603 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3604 if (!drm_mm_node_allocated(&vma->node))
3607 if (i915_vma_is_pinned(vma)) {
3608 DRM_DEBUG("can not change the cache level of pinned objects\n");
3612 if (i915_gem_valid_gtt_space(vma, cache_level))
3615 ret = i915_vma_unbind(vma);
3619 /* As unbinding may affect other elements in the
3620 * obj->vma_list (due to side-effects from retiring
3621 * an active vma), play safe and restart the iterator.
3626 /* We can reuse the existing drm_mm nodes but need to change the
3627 * cache-level on the PTE. We could simply unbind them all and
3628 * rebind with the correct cache-level on next use. However since
3629 * we already have a valid slot, dma mapping, pages etc, we may as
3630 * rewrite the PTE in the belief that doing so tramples upon less
3631 * state and so involves less work.
3633 if (obj->bind_count) {
3634 /* Before we change the PTE, the GPU must not be accessing it.
3635 * If we wait upon the object, we know that all the bound
3636 * VMA are no longer active.
3638 ret = i915_gem_object_wait(obj,
3639 I915_WAIT_INTERRUPTIBLE |
3642 MAX_SCHEDULE_TIMEOUT,
3647 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3648 cache_level != I915_CACHE_NONE) {
3649 /* Access to snoopable pages through the GTT is
3650 * incoherent and on some machines causes a hard
3651 * lockup. Relinquish the CPU mmaping to force
3652 * userspace to refault in the pages and we can
3653 * then double check if the GTT mapping is still
3654 * valid for that pointer access.
3656 i915_gem_release_mmap(obj);
3658 /* As we no longer need a fence for GTT access,
3659 * we can relinquish it now (and so prevent having
3660 * to steal a fence from someone else on the next
3661 * fence request). Note GPU activity would have
3662 * dropped the fence as all snoopable access is
3663 * supposed to be linear.
3665 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3666 ret = i915_vma_put_fence(vma);
3671 /* We either have incoherent backing store and
3672 * so no GTT access or the architecture is fully
3673 * coherent. In such cases, existing GTT mmaps
3674 * ignore the cache bit in the PTE and we can
3675 * rewrite it without confusing the GPU or having
3676 * to force userspace to fault back in its mmaps.
3680 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3681 if (!drm_mm_node_allocated(&vma->node))
3684 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3690 list_for_each_entry(vma, &obj->vma_list, obj_link)
3691 vma->node.color = cache_level;
3692 obj->cache_level = cache_level;
3693 obj->cache_coherent = i915_gem_object_is_coherent(obj);
3694 obj->cache_dirty = true; /* Always invalidate stale cachelines */
3699 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3700 struct drm_file *file)
3702 struct drm_i915_gem_caching *args = data;
3703 struct drm_i915_gem_object *obj;
3707 obj = i915_gem_object_lookup_rcu(file, args->handle);
3713 switch (obj->cache_level) {
3714 case I915_CACHE_LLC:
3715 case I915_CACHE_L3_LLC:
3716 args->caching = I915_CACHING_CACHED;
3720 args->caching = I915_CACHING_DISPLAY;
3724 args->caching = I915_CACHING_NONE;
3732 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3733 struct drm_file *file)
3735 struct drm_i915_private *i915 = to_i915(dev);
3736 struct drm_i915_gem_caching *args = data;
3737 struct drm_i915_gem_object *obj;
3738 enum i915_cache_level level;
3741 switch (args->caching) {
3742 case I915_CACHING_NONE:
3743 level = I915_CACHE_NONE;
3745 case I915_CACHING_CACHED:
3747 * Due to a HW issue on BXT A stepping, GPU stores via a
3748 * snooped mapping may leave stale data in a corresponding CPU
3749 * cacheline, whereas normally such cachelines would get
3752 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3755 level = I915_CACHE_LLC;
3757 case I915_CACHING_DISPLAY:
3758 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3764 obj = i915_gem_object_lookup(file, args->handle);
3768 if (obj->cache_level == level)
3771 ret = i915_gem_object_wait(obj,
3772 I915_WAIT_INTERRUPTIBLE,
3773 MAX_SCHEDULE_TIMEOUT,
3774 to_rps_client(file));
3778 ret = i915_mutex_lock_interruptible(dev);
3782 ret = i915_gem_object_set_cache_level(obj, level);
3783 mutex_unlock(&dev->struct_mutex);
3786 i915_gem_object_put(obj);
3791 * Prepare buffer for display plane (scanout, cursors, etc).
3792 * Can be called from an uninterruptible phase (modesetting) and allows
3793 * any flushes to be pipelined (for pageflips).
3796 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3798 const struct i915_ggtt_view *view)
3800 struct i915_vma *vma;
3803 lockdep_assert_held(&obj->base.dev->struct_mutex);
3805 /* Mark the pin_display early so that we account for the
3806 * display coherency whilst setting up the cache domains.
3810 /* The display engine is not coherent with the LLC cache on gen6. As
3811 * a result, we make sure that the pinning that is about to occur is
3812 * done with uncached PTEs. This is lowest common denominator for all
3815 * However for gen6+, we could do better by using the GFDT bit instead
3816 * of uncaching, which would allow us to flush all the LLC-cached data
3817 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3819 ret = i915_gem_object_set_cache_level(obj,
3820 HAS_WT(to_i915(obj->base.dev)) ?
3821 I915_CACHE_WT : I915_CACHE_NONE);
3824 goto err_unpin_display;
3827 /* As the user may map the buffer once pinned in the display plane
3828 * (e.g. libkms for the bootup splash), we have to ensure that we
3829 * always use map_and_fenceable for all scanout buffers. However,
3830 * it may simply be too big to fit into mappable, in which case
3831 * put it anyway and hope that userspace can cope (but always first
3832 * try to preserve the existing ABI).
3834 vma = ERR_PTR(-ENOSPC);
3835 if (!view || view->type == I915_GGTT_VIEW_NORMAL)
3836 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3837 PIN_MAPPABLE | PIN_NONBLOCK);
3839 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3842 /* Valleyview is definitely limited to scanning out the first
3843 * 512MiB. Lets presume this behaviour was inherited from the
3844 * g4x display engine and that all earlier gen are similarly
3845 * limited. Testing suggests that it is a little more
3846 * complicated than this. For example, Cherryview appears quite
3847 * happy to scanout from anywhere within its global aperture.
3850 if (HAS_GMCH_DISPLAY(i915))
3851 flags = PIN_MAPPABLE;
3852 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3855 goto err_unpin_display;
3857 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3859 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3860 __i915_gem_object_flush_for_display(obj);
3861 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
3863 /* It should now be out of any other write domains, and we can update
3864 * the domain values for our changes.
3866 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3876 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3878 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
3880 if (WARN_ON(vma->obj->pin_display == 0))
3883 if (--vma->obj->pin_display == 0)
3884 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
3886 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3887 i915_gem_object_bump_inactive_ggtt(vma->obj);
3889 i915_vma_unpin(vma);
3893 * Moves a single object to the CPU read, and possibly write domain.
3894 * @obj: object to act on
3895 * @write: requesting write or read-only access
3897 * This function returns when the move is complete, including waiting on
3901 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3905 lockdep_assert_held(&obj->base.dev->struct_mutex);
3907 ret = i915_gem_object_wait(obj,
3908 I915_WAIT_INTERRUPTIBLE |
3910 (write ? I915_WAIT_ALL : 0),
3911 MAX_SCHEDULE_TIMEOUT,
3916 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3918 /* Flush the CPU cache if it's still invalid. */
3919 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3920 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3921 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3924 /* It should now be out of any other write domains, and we can update
3925 * the domain values for our changes.
3927 GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3929 /* If we're writing through the CPU, then the GPU read domains will
3930 * need to be invalidated at next use.
3933 __start_cpu_write(obj);
3938 /* Throttle our rendering by waiting until the ring has completed our requests
3939 * emitted over 20 msec ago.
3941 * Note that if we were to use the current jiffies each time around the loop,
3942 * we wouldn't escape the function with any frames outstanding if the time to
3943 * render a frame was over 20ms.
3945 * This should get us reasonable parallelism between CPU and GPU but also
3946 * relatively low latency when blocking on a particular request to finish.
3949 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3951 struct drm_i915_private *dev_priv = to_i915(dev);
3952 struct drm_i915_file_private *file_priv = file->driver_priv;
3953 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3954 struct drm_i915_gem_request *request, *target = NULL;
3957 /* ABI: return -EIO if already wedged */
3958 if (i915_terminally_wedged(&dev_priv->gpu_error))
3961 spin_lock(&file_priv->mm.lock);
3962 list_for_each_entry(request, &file_priv->mm.request_list, client_link) {
3963 if (time_after_eq(request->emitted_jiffies, recent_enough))
3967 list_del(&target->client_link);
3968 target->file_priv = NULL;
3974 i915_gem_request_get(target);
3975 spin_unlock(&file_priv->mm.lock);
3980 ret = i915_wait_request(target,
3981 I915_WAIT_INTERRUPTIBLE,
3982 MAX_SCHEDULE_TIMEOUT);
3983 i915_gem_request_put(target);
3985 return ret < 0 ? ret : 0;
3989 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3990 const struct i915_ggtt_view *view,
3995 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3996 struct i915_address_space *vm = &dev_priv->ggtt.base;
3997 struct i915_vma *vma;
4000 lockdep_assert_held(&obj->base.dev->struct_mutex);
4002 vma = i915_vma_instance(obj, vm, view);
4003 if (unlikely(IS_ERR(vma)))
4006 if (i915_vma_misplaced(vma, size, alignment, flags)) {
4007 if (flags & PIN_NONBLOCK &&
4008 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
4009 return ERR_PTR(-ENOSPC);
4011 if (flags & PIN_MAPPABLE) {
4012 /* If the required space is larger than the available
4013 * aperture, we will not able to find a slot for the
4014 * object and unbinding the object now will be in
4015 * vain. Worse, doing so may cause us to ping-pong
4016 * the object in and out of the Global GTT and
4017 * waste a lot of cycles under the mutex.
4019 if (vma->fence_size > dev_priv->ggtt.mappable_end)
4020 return ERR_PTR(-E2BIG);
4022 /* If NONBLOCK is set the caller is optimistically
4023 * trying to cache the full object within the mappable
4024 * aperture, and *must* have a fallback in place for
4025 * situations where we cannot bind the object. We
4026 * can be a little more lax here and use the fallback
4027 * more often to avoid costly migrations of ourselves
4028 * and other objects within the aperture.
4030 * Half-the-aperture is used as a simple heuristic.
4031 * More interesting would to do search for a free
4032 * block prior to making the commitment to unbind.
4033 * That caters for the self-harm case, and with a
4034 * little more heuristics (e.g. NOFAULT, NOEVICT)
4035 * we could try to minimise harm to others.
4037 if (flags & PIN_NONBLOCK &&
4038 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
4039 return ERR_PTR(-ENOSPC);
4042 WARN(i915_vma_is_pinned(vma),
4043 "bo is already pinned in ggtt with incorrect alignment:"
4044 " offset=%08x, req.alignment=%llx,"
4045 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
4046 i915_ggtt_offset(vma), alignment,
4047 !!(flags & PIN_MAPPABLE),
4048 i915_vma_is_map_and_fenceable(vma));
4049 ret = i915_vma_unbind(vma);
4051 return ERR_PTR(ret);
4054 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
4056 return ERR_PTR(ret);
4061 static __always_inline unsigned int __busy_read_flag(unsigned int id)
4063 /* Note that we could alias engines in the execbuf API, but
4064 * that would be very unwise as it prevents userspace from
4065 * fine control over engine selection. Ahem.
4067 * This should be something like EXEC_MAX_ENGINE instead of
4070 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
4071 return 0x10000 << id;
4074 static __always_inline unsigned int __busy_write_id(unsigned int id)
4076 /* The uABI guarantees an active writer is also amongst the read
4077 * engines. This would be true if we accessed the activity tracking
4078 * under the lock, but as we perform the lookup of the object and
4079 * its activity locklessly we can not guarantee that the last_write
4080 * being active implies that we have set the same engine flag from
4081 * last_read - hence we always set both read and write busy for
4084 return id | __busy_read_flag(id);
4087 static __always_inline unsigned int
4088 __busy_set_if_active(const struct dma_fence *fence,
4089 unsigned int (*flag)(unsigned int id))
4091 struct drm_i915_gem_request *rq;
4093 /* We have to check the current hw status of the fence as the uABI
4094 * guarantees forward progress. We could rely on the idle worker
4095 * to eventually flush us, but to minimise latency just ask the
4098 * Note we only report on the status of native fences.
4100 if (!dma_fence_is_i915(fence))
4103 /* opencode to_request() in order to avoid const warnings */
4104 rq = container_of(fence, struct drm_i915_gem_request, fence);
4105 if (i915_gem_request_completed(rq))
4108 return flag(rq->engine->uabi_id);
4111 static __always_inline unsigned int
4112 busy_check_reader(const struct dma_fence *fence)
4114 return __busy_set_if_active(fence, __busy_read_flag);
4117 static __always_inline unsigned int
4118 busy_check_writer(const struct dma_fence *fence)
4123 return __busy_set_if_active(fence, __busy_write_id);
4127 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4128 struct drm_file *file)
4130 struct drm_i915_gem_busy *args = data;
4131 struct drm_i915_gem_object *obj;
4132 struct reservation_object_list *list;
4138 obj = i915_gem_object_lookup_rcu(file, args->handle);
4142 /* A discrepancy here is that we do not report the status of
4143 * non-i915 fences, i.e. even though we may report the object as idle,
4144 * a call to set-domain may still stall waiting for foreign rendering.
4145 * This also means that wait-ioctl may report an object as busy,
4146 * where busy-ioctl considers it idle.
4148 * We trade the ability to warn of foreign fences to report on which
4149 * i915 engines are active for the object.
4151 * Alternatively, we can trade that extra information on read/write
4154 * !reservation_object_test_signaled_rcu(obj->resv, true);
4155 * to report the overall busyness. This is what the wait-ioctl does.
4159 seq = raw_read_seqcount(&obj->resv->seq);
4161 /* Translate the exclusive fence to the READ *and* WRITE engine */
4162 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
4164 /* Translate shared fences to READ set of engines */
4165 list = rcu_dereference(obj->resv->fence);
4167 unsigned int shared_count = list->shared_count, i;
4169 for (i = 0; i < shared_count; ++i) {
4170 struct dma_fence *fence =
4171 rcu_dereference(list->shared[i]);
4173 args->busy |= busy_check_reader(fence);
4177 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
4187 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4188 struct drm_file *file_priv)
4190 return i915_gem_ring_throttle(dev, file_priv);
4194 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4195 struct drm_file *file_priv)
4197 struct drm_i915_private *dev_priv = to_i915(dev);
4198 struct drm_i915_gem_madvise *args = data;
4199 struct drm_i915_gem_object *obj;
4202 switch (args->madv) {
4203 case I915_MADV_DONTNEED:
4204 case I915_MADV_WILLNEED:
4210 obj = i915_gem_object_lookup(file_priv, args->handle);
4214 err = mutex_lock_interruptible(&obj->mm.lock);
4218 if (obj->mm.pages &&
4219 i915_gem_object_is_tiled(obj) &&
4220 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4221 if (obj->mm.madv == I915_MADV_WILLNEED) {
4222 GEM_BUG_ON(!obj->mm.quirked);
4223 __i915_gem_object_unpin_pages(obj);
4224 obj->mm.quirked = false;
4226 if (args->madv == I915_MADV_WILLNEED) {
4227 GEM_BUG_ON(obj->mm.quirked);
4228 __i915_gem_object_pin_pages(obj);
4229 obj->mm.quirked = true;
4233 if (obj->mm.madv != __I915_MADV_PURGED)
4234 obj->mm.madv = args->madv;
4236 /* if the object is no longer attached, discard its backing storage */
4237 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
4238 i915_gem_object_truncate(obj);
4240 args->retained = obj->mm.madv != __I915_MADV_PURGED;
4241 mutex_unlock(&obj->mm.lock);
4244 i915_gem_object_put(obj);
4249 frontbuffer_retire(struct i915_gem_active *active,
4250 struct drm_i915_gem_request *request)
4252 struct drm_i915_gem_object *obj =
4253 container_of(active, typeof(*obj), frontbuffer_write);
4255 intel_fb_obj_flush(obj, ORIGIN_CS);
4258 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4259 const struct drm_i915_gem_object_ops *ops)
4261 mutex_init(&obj->mm.lock);
4263 INIT_LIST_HEAD(&obj->global_link);
4264 INIT_LIST_HEAD(&obj->userfault_link);
4265 INIT_LIST_HEAD(&obj->vma_list);
4266 INIT_LIST_HEAD(&obj->batch_pool_link);
4270 reservation_object_init(&obj->__builtin_resv);
4271 obj->resv = &obj->__builtin_resv;
4273 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4274 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
4276 obj->mm.madv = I915_MADV_WILLNEED;
4277 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4278 mutex_init(&obj->mm.get_page.lock);
4280 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4283 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4284 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4285 I915_GEM_OBJECT_IS_SHRINKABLE,
4287 .get_pages = i915_gem_object_get_pages_gtt,
4288 .put_pages = i915_gem_object_put_pages_gtt,
4290 .pwrite = i915_gem_object_pwrite_gtt,
4293 struct drm_i915_gem_object *
4294 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4296 struct drm_i915_gem_object *obj;
4297 struct address_space *mapping;
4301 /* There is a prevalence of the assumption that we fit the object's
4302 * page count inside a 32bit _signed_ variable. Let's document this and
4303 * catch if we ever need to fix it. In the meantime, if you do spot
4304 * such a local variable, please consider fixing!
4306 if (size >> PAGE_SHIFT > INT_MAX)
4307 return ERR_PTR(-E2BIG);
4309 if (overflows_type(size, obj->base.size))
4310 return ERR_PTR(-E2BIG);
4312 obj = i915_gem_object_alloc(dev_priv);
4314 return ERR_PTR(-ENOMEM);
4316 ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
4320 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4321 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4322 /* 965gm cannot relocate objects above 4GiB. */
4323 mask &= ~__GFP_HIGHMEM;
4324 mask |= __GFP_DMA32;
4327 mapping = obj->base.filp->f_mapping;
4328 mapping_set_gfp_mask(mapping, mask);
4329 GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
4331 i915_gem_object_init(obj, &i915_gem_object_ops);
4333 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4334 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4336 if (HAS_LLC(dev_priv)) {
4337 /* On some devices, we can have the GPU use the LLC (the CPU
4338 * cache) for about a 10% performance improvement
4339 * compared to uncached. Graphics requests other than
4340 * display scanout are coherent with the CPU in
4341 * accessing this cache. This means in this mode we
4342 * don't need to clflush on the CPU side, and on the
4343 * GPU side we only need to flush internal caches to
4344 * get data visible to the CPU.
4346 * However, we maintain the display planes as UC, and so
4347 * need to rebind when first used as such.
4349 obj->cache_level = I915_CACHE_LLC;
4351 obj->cache_level = I915_CACHE_NONE;
4353 obj->cache_coherent = i915_gem_object_is_coherent(obj);
4354 obj->cache_dirty = !obj->cache_coherent;
4356 trace_i915_gem_object_create(obj);
4361 i915_gem_object_free(obj);
4362 return ERR_PTR(ret);
4365 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4367 /* If we are the last user of the backing storage (be it shmemfs
4368 * pages or stolen etc), we know that the pages are going to be
4369 * immediately released. In this case, we can then skip copying
4370 * back the contents from the GPU.
4373 if (obj->mm.madv != I915_MADV_WILLNEED)
4376 if (obj->base.filp == NULL)
4379 /* At first glance, this looks racy, but then again so would be
4380 * userspace racing mmap against close. However, the first external
4381 * reference to the filp can only be obtained through the
4382 * i915_gem_mmap_ioctl() which safeguards us against the user
4383 * acquiring such a reference whilst we are in the middle of
4384 * freeing the object.
4386 return atomic_long_read(&obj->base.filp->f_count) == 1;
4389 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4390 struct llist_node *freed)
4392 struct drm_i915_gem_object *obj, *on;
4394 mutex_lock(&i915->drm.struct_mutex);
4395 intel_runtime_pm_get(i915);
4396 llist_for_each_entry(obj, freed, freed) {
4397 struct i915_vma *vma, *vn;
4399 trace_i915_gem_object_destroy(obj);
4401 GEM_BUG_ON(i915_gem_object_is_active(obj));
4402 list_for_each_entry_safe(vma, vn,
4403 &obj->vma_list, obj_link) {
4404 GEM_BUG_ON(i915_vma_is_active(vma));
4405 vma->flags &= ~I915_VMA_PIN_MASK;
4406 i915_vma_close(vma);
4408 GEM_BUG_ON(!list_empty(&obj->vma_list));
4409 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4411 list_del(&obj->global_link);
4413 intel_runtime_pm_put(i915);
4414 mutex_unlock(&i915->drm.struct_mutex);
4418 llist_for_each_entry_safe(obj, on, freed, freed) {
4419 GEM_BUG_ON(obj->bind_count);
4420 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4422 if (obj->ops->release)
4423 obj->ops->release(obj);
4425 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4426 atomic_set(&obj->mm.pages_pin_count, 0);
4427 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4428 GEM_BUG_ON(obj->mm.pages);
4430 if (obj->base.import_attach)
4431 drm_prime_gem_destroy(&obj->base, NULL);
4433 reservation_object_fini(&obj->__builtin_resv);
4434 drm_gem_object_release(&obj->base);
4435 i915_gem_info_remove_obj(i915, obj->base.size);
4438 i915_gem_object_free(obj);
4442 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4444 struct llist_node *freed;
4446 freed = llist_del_all(&i915->mm.free_list);
4447 if (unlikely(freed))
4448 __i915_gem_free_objects(i915, freed);
4451 static void __i915_gem_free_work(struct work_struct *work)
4453 struct drm_i915_private *i915 =
4454 container_of(work, struct drm_i915_private, mm.free_work);
4455 struct llist_node *freed;
4457 /* All file-owned VMA should have been released by this point through
4458 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4459 * However, the object may also be bound into the global GTT (e.g.
4460 * older GPUs without per-process support, or for direct access through
4461 * the GTT either for the user or for scanout). Those VMA still need to
4465 while ((freed = llist_del_all(&i915->mm.free_list))) {
4466 __i915_gem_free_objects(i915, freed);
4472 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4474 struct drm_i915_gem_object *obj =
4475 container_of(head, typeof(*obj), rcu);
4476 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4478 /* We can't simply use call_rcu() from i915_gem_free_object()
4479 * as we need to block whilst unbinding, and the call_rcu
4480 * task may be called from softirq context. So we take a
4481 * detour through a worker.
4483 if (llist_add(&obj->freed, &i915->mm.free_list))
4484 schedule_work(&i915->mm.free_work);
4487 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4489 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4491 if (obj->mm.quirked)
4492 __i915_gem_object_unpin_pages(obj);
4494 if (discard_backing_storage(obj))
4495 obj->mm.madv = I915_MADV_DONTNEED;
4497 /* Before we free the object, make sure any pure RCU-only
4498 * read-side critical sections are complete, e.g.
4499 * i915_gem_busy_ioctl(). For the corresponding synchronized
4500 * lookup see i915_gem_object_lookup_rcu().
4502 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4505 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4507 lockdep_assert_held(&obj->base.dev->struct_mutex);
4509 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4510 if (i915_gem_object_is_active(obj))
4511 i915_gem_object_set_active_reference(obj);
4513 i915_gem_object_put(obj);
4516 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4518 struct intel_engine_cs *engine;
4519 enum intel_engine_id id;
4521 for_each_engine(engine, dev_priv, id)
4522 GEM_BUG_ON(engine->last_retired_context &&
4523 !i915_gem_context_is_kernel(engine->last_retired_context));
4526 void i915_gem_sanitize(struct drm_i915_private *i915)
4529 * If we inherit context state from the BIOS or earlier occupants
4530 * of the GPU, the GPU may be in an inconsistent state when we
4531 * try to take over. The only way to remove the earlier state
4532 * is by resetting. However, resetting on earlier gen is tricky as
4533 * it may impact the display and we are uncertain about the stability
4534 * of the reset, so this could be applied to even earlier gen.
4536 if (INTEL_GEN(i915) >= 5) {
4537 int reset = intel_gpu_reset(i915, ALL_ENGINES);
4538 WARN_ON(reset && reset != -ENODEV);
4542 int i915_gem_suspend(struct drm_i915_private *dev_priv)
4544 struct drm_device *dev = &dev_priv->drm;
4547 intel_runtime_pm_get(dev_priv);
4548 intel_suspend_gt_powersave(dev_priv);
4550 mutex_lock(&dev->struct_mutex);
4552 /* We have to flush all the executing contexts to main memory so
4553 * that they can saved in the hibernation image. To ensure the last
4554 * context image is coherent, we have to switch away from it. That
4555 * leaves the dev_priv->kernel_context still active when
4556 * we actually suspend, and its image in memory may not match the GPU
4557 * state. Fortunately, the kernel_context is disposable and we do
4558 * not rely on its state.
4560 ret = i915_gem_switch_to_kernel_context(dev_priv);
4564 ret = i915_gem_wait_for_idle(dev_priv,
4565 I915_WAIT_INTERRUPTIBLE |
4570 assert_kernel_context_is_current(dev_priv);
4571 i915_gem_contexts_lost(dev_priv);
4572 mutex_unlock(&dev->struct_mutex);
4574 intel_guc_suspend(dev_priv);
4576 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4577 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4579 /* As the idle_work is rearming if it detects a race, play safe and
4580 * repeat the flush until it is definitely idle.
4582 while (flush_delayed_work(&dev_priv->gt.idle_work))
4585 /* Assert that we sucessfully flushed all the work and
4586 * reset the GPU back to its idle, low power state.
4588 WARN_ON(dev_priv->gt.awake);
4589 WARN_ON(!intel_engines_are_idle(dev_priv));
4592 * Neither the BIOS, ourselves or any other kernel
4593 * expects the system to be in execlists mode on startup,
4594 * so we need to reset the GPU back to legacy mode. And the only
4595 * known way to disable logical contexts is through a GPU reset.
4597 * So in order to leave the system in a known default configuration,
4598 * always reset the GPU upon unload and suspend. Afterwards we then
4599 * clean up the GEM state tracking, flushing off the requests and
4600 * leaving the system in a known idle state.
4602 * Note that is of the upmost importance that the GPU is idle and
4603 * all stray writes are flushed *before* we dismantle the backing
4604 * storage for the pinned objects.
4606 * However, since we are uncertain that resetting the GPU on older
4607 * machines is a good idea, we don't - just in case it leaves the
4608 * machine in an unusable condition.
4610 i915_gem_sanitize(dev_priv);
4614 mutex_unlock(&dev->struct_mutex);
4616 intel_runtime_pm_put(dev_priv);
4620 void i915_gem_resume(struct drm_i915_private *dev_priv)
4622 struct drm_device *dev = &dev_priv->drm;
4624 WARN_ON(dev_priv->gt.awake);
4626 mutex_lock(&dev->struct_mutex);
4627 i915_gem_restore_gtt_mappings(dev_priv);
4629 /* As we didn't flush the kernel context before suspend, we cannot
4630 * guarantee that the context image is complete. So let's just reset
4631 * it and start again.
4633 dev_priv->gt.resume(dev_priv);
4635 mutex_unlock(&dev->struct_mutex);
4638 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4640 if (INTEL_GEN(dev_priv) < 5 ||
4641 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4644 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4645 DISP_TILE_SURFACE_SWIZZLING);
4647 if (IS_GEN5(dev_priv))
4650 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4651 if (IS_GEN6(dev_priv))
4652 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4653 else if (IS_GEN7(dev_priv))
4654 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4655 else if (IS_GEN8(dev_priv))
4656 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4661 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4663 I915_WRITE(RING_CTL(base), 0);
4664 I915_WRITE(RING_HEAD(base), 0);
4665 I915_WRITE(RING_TAIL(base), 0);
4666 I915_WRITE(RING_START(base), 0);
4669 static void init_unused_rings(struct drm_i915_private *dev_priv)
4671 if (IS_I830(dev_priv)) {
4672 init_unused_ring(dev_priv, PRB1_BASE);
4673 init_unused_ring(dev_priv, SRB0_BASE);
4674 init_unused_ring(dev_priv, SRB1_BASE);
4675 init_unused_ring(dev_priv, SRB2_BASE);
4676 init_unused_ring(dev_priv, SRB3_BASE);
4677 } else if (IS_GEN2(dev_priv)) {
4678 init_unused_ring(dev_priv, SRB0_BASE);
4679 init_unused_ring(dev_priv, SRB1_BASE);
4680 } else if (IS_GEN3(dev_priv)) {
4681 init_unused_ring(dev_priv, PRB1_BASE);
4682 init_unused_ring(dev_priv, PRB2_BASE);
4686 static int __i915_gem_restart_engines(void *data)
4688 struct drm_i915_private *i915 = data;
4689 struct intel_engine_cs *engine;
4690 enum intel_engine_id id;
4693 for_each_engine(engine, i915, id) {
4694 err = engine->init_hw(engine);
4702 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
4706 dev_priv->gt.last_init_time = ktime_get();
4708 /* Double layer security blanket, see i915_gem_init() */
4709 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4711 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4712 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4714 if (IS_HASWELL(dev_priv))
4715 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4716 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4718 if (HAS_PCH_NOP(dev_priv)) {
4719 if (IS_IVYBRIDGE(dev_priv)) {
4720 u32 temp = I915_READ(GEN7_MSG_CTL);
4721 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4722 I915_WRITE(GEN7_MSG_CTL, temp);
4723 } else if (INTEL_GEN(dev_priv) >= 7) {
4724 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4725 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4726 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4730 i915_gem_init_swizzling(dev_priv);
4733 * At least 830 can leave some of the unused rings
4734 * "active" (ie. head != tail) after resume which
4735 * will prevent c3 entry. Makes sure all unused rings
4738 init_unused_rings(dev_priv);
4740 BUG_ON(!dev_priv->kernel_context);
4742 ret = i915_ppgtt_init_hw(dev_priv);
4744 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4748 /* Need to do basic initialisation of all rings first: */
4749 ret = __i915_gem_restart_engines(dev_priv);
4753 intel_mocs_init_l3cc_table(dev_priv);
4755 /* We can't enable contexts until all firmware is loaded */
4756 ret = intel_uc_init_hw(dev_priv);
4761 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4765 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4767 if (INTEL_INFO(dev_priv)->gen < 6)
4770 /* TODO: make semaphores and Execlists play nicely together */
4771 if (i915.enable_execlists)
4777 /* Enable semaphores on SNB when IO remapping is off */
4778 if (IS_GEN6(dev_priv) && intel_vtd_active())
4784 int i915_gem_init(struct drm_i915_private *dev_priv)
4788 mutex_lock(&dev_priv->drm.struct_mutex);
4790 dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
4792 if (!i915.enable_execlists) {
4793 dev_priv->gt.resume = intel_legacy_submission_resume;
4794 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4796 dev_priv->gt.resume = intel_lr_context_resume;
4797 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4800 /* This is just a security blanket to placate dragons.
4801 * On some systems, we very sporadically observe that the first TLBs
4802 * used by the CS may be stale, despite us poking the TLB reset. If
4803 * we hold the forcewake during initialisation these problems
4804 * just magically go away.
4806 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4808 ret = i915_gem_init_userptr(dev_priv);
4812 ret = i915_gem_init_ggtt(dev_priv);
4816 ret = i915_gem_contexts_init(dev_priv);
4820 ret = intel_engines_init(dev_priv);
4824 ret = i915_gem_init_hw(dev_priv);
4826 /* Allow engine initialisation to fail by marking the GPU as
4827 * wedged. But we only want to do this where the GPU is angry,
4828 * for all other failure, such as an allocation failure, bail.
4830 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4831 i915_gem_set_wedged(dev_priv);
4836 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4837 mutex_unlock(&dev_priv->drm.struct_mutex);
4842 void i915_gem_init_mmio(struct drm_i915_private *i915)
4844 i915_gem_sanitize(i915);
4848 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
4850 struct intel_engine_cs *engine;
4851 enum intel_engine_id id;
4853 for_each_engine(engine, dev_priv, id)
4854 dev_priv->gt.cleanup_engine(engine);
4858 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4862 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4863 !IS_CHERRYVIEW(dev_priv))
4864 dev_priv->num_fence_regs = 32;
4865 else if (INTEL_INFO(dev_priv)->gen >= 4 ||
4866 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4867 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
4868 dev_priv->num_fence_regs = 16;
4870 dev_priv->num_fence_regs = 8;
4872 if (intel_vgpu_active(dev_priv))
4873 dev_priv->num_fence_regs =
4874 I915_READ(vgtif_reg(avail_rs.fence_num));
4876 /* Initialize fence registers to zero */
4877 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4878 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4880 fence->i915 = dev_priv;
4882 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4884 i915_gem_restore_fences(dev_priv);
4886 i915_gem_detect_bit_6_swizzle(dev_priv);
4890 i915_gem_load_init(struct drm_i915_private *dev_priv)
4894 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4895 if (!dev_priv->objects)
4898 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4899 if (!dev_priv->vmas)
4902 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4903 SLAB_HWCACHE_ALIGN |
4904 SLAB_RECLAIM_ACCOUNT |
4905 SLAB_TYPESAFE_BY_RCU);
4906 if (!dev_priv->requests)
4909 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4910 SLAB_HWCACHE_ALIGN |
4911 SLAB_RECLAIM_ACCOUNT);
4912 if (!dev_priv->dependencies)
4915 dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN);
4916 if (!dev_priv->priorities)
4917 goto err_dependencies;
4919 mutex_lock(&dev_priv->drm.struct_mutex);
4920 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4921 err = i915_gem_timeline_init__global(dev_priv);
4922 mutex_unlock(&dev_priv->drm.struct_mutex);
4924 goto err_priorities;
4926 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4927 init_llist_head(&dev_priv->mm.free_list);
4928 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4929 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4930 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4931 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4932 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4933 i915_gem_retire_work_handler);
4934 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4935 i915_gem_idle_work_handler);
4936 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4937 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4939 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4941 spin_lock_init(&dev_priv->fb_tracking.lock);
4946 kmem_cache_destroy(dev_priv->priorities);
4948 kmem_cache_destroy(dev_priv->dependencies);
4950 kmem_cache_destroy(dev_priv->requests);
4952 kmem_cache_destroy(dev_priv->vmas);
4954 kmem_cache_destroy(dev_priv->objects);
4959 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
4961 i915_gem_drain_freed_objects(dev_priv);
4962 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4963 WARN_ON(dev_priv->mm.object_count);
4965 mutex_lock(&dev_priv->drm.struct_mutex);
4966 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4967 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4968 mutex_unlock(&dev_priv->drm.struct_mutex);
4970 kmem_cache_destroy(dev_priv->priorities);
4971 kmem_cache_destroy(dev_priv->dependencies);
4972 kmem_cache_destroy(dev_priv->requests);
4973 kmem_cache_destroy(dev_priv->vmas);
4974 kmem_cache_destroy(dev_priv->objects);
4976 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4980 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4982 /* Discard all purgeable objects, let userspace recover those as
4983 * required after resuming.
4985 i915_gem_shrink_all(dev_priv);
4990 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4992 struct drm_i915_gem_object *obj;
4993 struct list_head *phases[] = {
4994 &dev_priv->mm.unbound_list,
4995 &dev_priv->mm.bound_list,
4999 /* Called just before we write the hibernation image.
5001 * We need to update the domain tracking to reflect that the CPU
5002 * will be accessing all the pages to create and restore from the
5003 * hibernation, and so upon restoration those pages will be in the
5006 * To make sure the hibernation image contains the latest state,
5007 * we update that state just before writing out the image.
5009 * To try and reduce the hibernation image, we manually shrink
5010 * the objects as well, see i915_gem_freeze()
5013 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
5014 i915_gem_drain_freed_objects(dev_priv);
5016 mutex_lock(&dev_priv->drm.struct_mutex);
5017 for (p = phases; *p; p++) {
5018 list_for_each_entry(obj, *p, global_link)
5019 __start_cpu_write(obj);
5021 mutex_unlock(&dev_priv->drm.struct_mutex);
5026 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5028 struct drm_i915_file_private *file_priv = file->driver_priv;
5029 struct drm_i915_gem_request *request;
5031 /* Clean up our request list when the client is going away, so that
5032 * later retire_requests won't dereference our soon-to-be-gone
5035 spin_lock(&file_priv->mm.lock);
5036 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
5037 request->file_priv = NULL;
5038 spin_unlock(&file_priv->mm.lock);
5041 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
5043 struct drm_i915_file_private *file_priv;
5048 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5052 file->driver_priv = file_priv;
5053 file_priv->dev_priv = i915;
5054 file_priv->file = file;
5056 spin_lock_init(&file_priv->mm.lock);
5057 INIT_LIST_HEAD(&file_priv->mm.request_list);
5059 file_priv->bsd_engine = -1;
5061 ret = i915_gem_context_open(i915, file);
5069 * i915_gem_track_fb - update frontbuffer tracking
5070 * @old: current GEM buffer for the frontbuffer slots
5071 * @new: new GEM buffer for the frontbuffer slots
5072 * @frontbuffer_bits: bitmask of frontbuffer slots
5074 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5075 * from @old and setting them in @new. Both @old and @new can be NULL.
5077 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5078 struct drm_i915_gem_object *new,
5079 unsigned frontbuffer_bits)
5081 /* Control of individual bits within the mask are guarded by
5082 * the owning plane->mutex, i.e. we can never see concurrent
5083 * manipulation of individual bits. But since the bitfield as a whole
5084 * is updated using RMW, we need to use atomics in order to update
5087 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
5088 sizeof(atomic_t) * BITS_PER_BYTE);
5091 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
5092 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
5096 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
5097 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
5101 /* Allocate a new GEM object and fill it with the supplied data */
5102 struct drm_i915_gem_object *
5103 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
5104 const void *data, size_t size)
5106 struct drm_i915_gem_object *obj;
5111 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
5115 GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
5117 file = obj->base.filp;
5120 unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
5122 void *pgdata, *vaddr;
5124 err = pagecache_write_begin(file, file->f_mapping,
5131 memcpy(vaddr, data, len);
5134 err = pagecache_write_end(file, file->f_mapping,
5148 i915_gem_object_put(obj);
5149 return ERR_PTR(err);
5152 struct scatterlist *
5153 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
5155 unsigned int *offset)
5157 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
5158 struct scatterlist *sg;
5159 unsigned int idx, count;
5162 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
5163 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
5165 /* As we iterate forward through the sg, we record each entry in a
5166 * radixtree for quick repeated (backwards) lookups. If we have seen
5167 * this index previously, we will have an entry for it.
5169 * Initial lookup is O(N), but this is amortized to O(1) for
5170 * sequential page access (where each new request is consecutive
5171 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
5172 * i.e. O(1) with a large constant!
5174 if (n < READ_ONCE(iter->sg_idx))
5177 mutex_lock(&iter->lock);
5179 /* We prefer to reuse the last sg so that repeated lookup of this
5180 * (or the subsequent) sg are fast - comparing against the last
5181 * sg is faster than going through the radixtree.
5186 count = __sg_page_count(sg);
5188 while (idx + count <= n) {
5189 unsigned long exception, i;
5192 /* If we cannot allocate and insert this entry, or the
5193 * individual pages from this range, cancel updating the
5194 * sg_idx so that on this lookup we are forced to linearly
5195 * scan onwards, but on future lookups we will try the
5196 * insertion again (in which case we need to be careful of
5197 * the error return reporting that we have already inserted
5200 ret = radix_tree_insert(&iter->radix, idx, sg);
5201 if (ret && ret != -EEXIST)
5205 RADIX_TREE_EXCEPTIONAL_ENTRY |
5206 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
5207 for (i = 1; i < count; i++) {
5208 ret = radix_tree_insert(&iter->radix, idx + i,
5210 if (ret && ret != -EEXIST)
5215 sg = ____sg_next(sg);
5216 count = __sg_page_count(sg);
5223 mutex_unlock(&iter->lock);
5225 if (unlikely(n < idx)) /* insertion completed by another thread */
5228 /* In case we failed to insert the entry into the radixtree, we need
5229 * to look beyond the current sg.
5231 while (idx + count <= n) {
5233 sg = ____sg_next(sg);
5234 count = __sg_page_count(sg);
5243 sg = radix_tree_lookup(&iter->radix, n);
5246 /* If this index is in the middle of multi-page sg entry,
5247 * the radixtree will contain an exceptional entry that points
5248 * to the start of that range. We will return the pointer to
5249 * the base page and the offset of this page within the
5253 if (unlikely(radix_tree_exception(sg))) {
5254 unsigned long base =
5255 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
5257 sg = radix_tree_lookup(&iter->radix, base);
5269 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
5271 struct scatterlist *sg;
5272 unsigned int offset;
5274 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
5276 sg = i915_gem_object_get_sg(obj, n, &offset);
5277 return nth_page(sg_page(sg), offset);
5280 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5282 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
5287 page = i915_gem_object_get_page(obj, n);
5289 set_page_dirty(page);
5295 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
5298 struct scatterlist *sg;
5299 unsigned int offset;
5301 sg = i915_gem_object_get_sg(obj, n, &offset);
5302 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
5305 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5306 #include "selftests/scatterlist.c"
5307 #include "selftests/mock_gem_device.c"
5308 #include "selftests/huge_gem_object.c"
5309 #include "selftests/i915_gem_object.c"
5310 #include "selftests/i915_gem_coherency.c"