drivers/gpu/drm/i915/i915_gem_fence_reg.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <drm/i915_drm.h>
  25
  26 #include "i915_drv.h"
  27 #include "i915_scatterlist.h"
  28 #include "i915_vgpu.h"
  29
  30 /**
  31  * DOC: fence register handling
  32  *
  33  * Important to avoid confusions: "fences" in the i915 driver are not execution
  34  * fences used to track command completion but hardware detiler objects which
  35  * wrap a given range of the global GTT. Each platform has only a fairly limited
  36  * set of these objects.
  37  *
  38  * Fences are used to detile GTT memory mappings. They're also connected to the
  39  * hardware frontbuffer render tracking and hence interact with frontbuffer
  40  * compression. Furthermore on older platforms fences are required for tiled
  41  * objects used by the display engine. They can also be used by the render
  42  * engine - they're required for blitter commands and are optional for render
  43  * commands. But on gen4+ both display (with the exception of fbc) and rendering
  44  * have their own tiling state bits and don't need fences.
  45  *
  46  * Also note that fences only support X and Y tiling and hence can't be used for
  47  * the fancier new tiling formats like W, Ys and Yf.
  48  *
  49  * Finally note that because fences are such a restricted resource they're
  50  * dynamically associated with objects. Furthermore fence state is committed to
  51  * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
  52  * explicitly call i915_gem_object_get_fence() to synchronize fencing status
  53  * for cpu access. Also note that some code wants an unfenced view, for those
  54  * cases the fence can be removed forcefully with i915_gem_object_put_fence().
  55  *
  56  * Internally these functions will synchronize with userspace access by removing
  57  * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
  58  */
  59
  60 #define pipelined 0
  61
  62 static struct drm_i915_private *fence_to_i915(struct i915_fence_reg *fence)
  63 {
  64         return fence->ggtt->vm.i915;
  65 }
  66
  67 static struct intel_uncore *fence_to_uncore(struct i915_fence_reg *fence)
  68 {
  69         return fence->ggtt->vm.gt->uncore;
  70 }
  71
  72 static void i965_write_fence_reg(struct i915_fence_reg *fence,
  73                                  struct i915_vma *vma)
  74 {
  75         i915_reg_t fence_reg_lo, fence_reg_hi;
  76         int fence_pitch_shift;
  77         u64 val;
  78
  79         if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
  80                 fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
  81                 fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
  82                 fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
  83
  84         } else {
  85                 fence_reg_lo = FENCE_REG_965_LO(fence->id);
  86                 fence_reg_hi = FENCE_REG_965_HI(fence->id);
  87                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
  88         }
  89
  90         val = 0;
  91         if (vma) {
  92                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
  93
  94                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
  95                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, I965_FENCE_PAGE));
  96                 GEM_BUG_ON(!IS_ALIGNED(vma->fence_size, I965_FENCE_PAGE));
  97                 GEM_BUG_ON(!IS_ALIGNED(stride, 128));
  98
  99                 val = (vma->node.start + vma->fence_size - I965_FENCE_PAGE) << 32;
 100                 val |= vma->node.start;
 101                 val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
 102                 if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
 103                         val |= BIT(I965_FENCE_TILING_Y_SHIFT);
 104                 val |= I965_FENCE_REG_VALID;
 105         }
 106
 107         if (!pipelined) {
 108                 struct intel_uncore *uncore = fence_to_uncore(fence);
 109
 110                 /*
 111                  * To w/a incoherency with non-atomic 64-bit register updates,
 112                  * we split the 64-bit update into two 32-bit writes. In order
 113                  * for a partial fence not to be evaluated between writes, we
 114                  * precede the update with write to turn off the fence register,
 115                  * and only enable the fence as the last step.
 116                  *
 117                  * For extra levels of paranoia, we make sure each step lands
 118                  * before applying the next step.
 119                  */
 120                 intel_uncore_write_fw(uncore, fence_reg_lo, 0);
 121                 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
 122
 123                 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val));
 124                 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val));
 125                 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
 126         }
 127 }
 128
 129 static void i915_write_fence_reg(struct i915_fence_reg *fence,
 130                                  struct i915_vma *vma)
 131 {
 132         u32 val;
 133
 134         val = 0;
 135         if (vma) {
 136                 unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
 137                 bool is_y_tiled = tiling == I915_TILING_Y;
 138                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
 139
 140                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 141                 GEM_BUG_ON(vma->node.start & ~I915_FENCE_START_MASK);
 142                 GEM_BUG_ON(!is_power_of_2(vma->fence_size));
 143                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
 144
 145                 if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence_to_i915(fence)))
 146                         stride /= 128;
 147                 else
 148                         stride /= 512;
 149                 GEM_BUG_ON(!is_power_of_2(stride));
 150
 151                 val = vma->node.start;
 152                 if (is_y_tiled)
 153                         val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 154                 val |= I915_FENCE_SIZE_BITS(vma->fence_size);
 155                 val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
 156
 157                 val |= I830_FENCE_REG_VALID;
 158         }
 159
 160         if (!pipelined) {
 161                 struct intel_uncore *uncore = fence_to_uncore(fence);
 162                 i915_reg_t reg = FENCE_REG(fence->id);
 163
 164                 intel_uncore_write_fw(uncore, reg, val);
 165                 intel_uncore_posting_read_fw(uncore, reg);
 166         }
 167 }
 168
 169 static void i830_write_fence_reg(struct i915_fence_reg *fence,
 170                                  struct i915_vma *vma)
 171 {
 172         u32 val;
 173
 174         val = 0;
 175         if (vma) {
 176                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
 177
 178                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 179                 GEM_BUG_ON(vma->node.start & ~I830_FENCE_START_MASK);
 180                 GEM_BUG_ON(!is_power_of_2(vma->fence_size));
 181                 GEM_BUG_ON(!is_power_of_2(stride / 128));
 182                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
 183
 184                 val = vma->node.start;
 185                 if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
 186                         val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 187                 val |= I830_FENCE_SIZE_BITS(vma->fence_size);
 188                 val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
 189                 val |= I830_FENCE_REG_VALID;
 190         }
 191
 192         if (!pipelined) {
 193                 struct intel_uncore *uncore = fence_to_uncore(fence);
 194                 i915_reg_t reg = FENCE_REG(fence->id);
 195
 196                 intel_uncore_write_fw(uncore, reg, val);
 197                 intel_uncore_posting_read_fw(uncore, reg);
 198         }
 199 }
 200
 201 static void fence_write(struct i915_fence_reg *fence,
 202                         struct i915_vma *vma)
 203 {
 204         struct drm_i915_private *i915 = fence_to_i915(fence);
 205
 206         /*
 207          * Previous access through the fence register is marshalled by
 208          * the mb() inside the fault handlers (i915_gem_release_mmaps)
 209          * and explicitly managed for internal users.
 210          */
 211
 212         if (IS_GEN(i915, 2))
 213                 i830_write_fence_reg(fence, vma);
 214         else if (IS_GEN(i915, 3))
 215                 i915_write_fence_reg(fence, vma);
 216         else
 217                 i965_write_fence_reg(fence, vma);
 218
 219         /*
 220          * Access through the fenced region afterwards is
 221          * ordered by the posting reads whilst writing the registers.
 222          */
 223
 224         fence->dirty = false;
 225 }
 226
 227 static int fence_update(struct i915_fence_reg *fence,
 228                         struct i915_vma *vma)
 229 {
 230         struct i915_ggtt *ggtt = fence->ggtt;
 231         struct intel_uncore *uncore = fence_to_uncore(fence);
 232         intel_wakeref_t wakeref;
 233         struct i915_vma *old;
 234         int ret;
 235
 236         if (vma) {
 237                 if (!i915_vma_is_map_and_fenceable(vma))
 238                         return -EINVAL;
 239
 240                 if (WARN(!i915_gem_object_get_stride(vma->obj) ||
 241                          !i915_gem_object_get_tiling(vma->obj),
 242                          "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
 243                          i915_gem_object_get_stride(vma->obj),
 244                          i915_gem_object_get_tiling(vma->obj)))
 245                         return -EINVAL;
 246
 247                 ret = i915_vma_sync(vma);
 248                 if (ret)
 249                         return ret;
 250         }
 251
 252         old = xchg(&fence->vma, NULL);
 253         if (old) {
 254                 /* XXX Ideally we would move the waiting to outside the mutex */
 255                 ret = i915_vma_sync(old);
 256                 if (ret) {
 257                         fence->vma = old;
 258                         return ret;
 259                 }
 260
 261                 i915_vma_flush_writes(old);
 262
 263                 /*
 264                  * Ensure that all userspace CPU access is completed before
 265                  * stealing the fence.
 266                  */
 267                 if (old != vma) {
 268                         GEM_BUG_ON(old->fence != fence);
 269                         i915_vma_revoke_mmap(old);
 270                         old->fence = NULL;
 271                 }
 272
 273                 list_move(&fence->link, &ggtt->fence_list);
 274         }
 275
 276         /*
 277          * We only need to update the register itself if the device is awake.
 278          * If the device is currently powered down, we will defer the write
 279          * to the runtime resume, see i915_gem_restore_fences().
 280          *
 281          * This only works for removing the fence register, on acquisition
 282          * the caller must hold the rpm wakeref. The fence register must
 283          * be cleared before we can use any other fences to ensure that
 284          * the new fences do not overlap the elided clears, confusing HW.
 285          */
 286         wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm);
 287         if (!wakeref) {
 288                 GEM_BUG_ON(vma);
 289                 return 0;
 290         }
 291
 292         WRITE_ONCE(fence->vma, vma);
 293         fence_write(fence, vma);
 294
 295         if (vma) {
 296                 vma->fence = fence;
 297                 list_move_tail(&fence->link, &ggtt->fence_list);
 298         }
 299
 300         intel_runtime_pm_put(uncore->rpm, wakeref);
 301         return 0;
 302 }
 303
 304 /**
 305  * i915_vma_revoke_fence - force-remove fence for a VMA
 306  * @vma: vma to map linearly (not through a fence reg)
 307  *
 308  * This function force-removes any fence from the given object, which is useful
 309  * if the kernel wants to do untiled GTT access.
 310  *
 311  * Returns:
 312  *
 313  * 0 on success, negative error code on failure.
 314  */
 315 int i915_vma_revoke_fence(struct i915_vma *vma)
 316 {
 317         struct i915_fence_reg *fence = vma->fence;
 318
 319         lockdep_assert_held(&vma->vm->mutex);
 320         if (!fence)
 321                 return 0;
 322
 323         if (atomic_read(&fence->pin_count))
 324                 return -EBUSY;
 325
 326         return fence_update(fence, NULL);
 327 }
 328
 329 static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt)
 330 {
 331         struct i915_fence_reg *fence;
 332
 333         list_for_each_entry(fence, &ggtt->fence_list, link) {
 334                 GEM_BUG_ON(fence->vma && fence->vma->fence != fence);
 335
 336                 if (atomic_read(&fence->pin_count))
 337                         continue;
 338
 339                 return fence;
 340         }
 341
 342         /* Wait for completion of pending flips which consume fences */
 343         if (intel_has_pending_fb_unpin(ggtt->vm.i915))
 344                 return ERR_PTR(-EAGAIN);
 345
 346         return ERR_PTR(-EDEADLK);
 347 }
 348
 349 int __i915_vma_pin_fence(struct i915_vma *vma)
 350 {
 351         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm);
 352         struct i915_fence_reg *fence;
 353         struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
 354         int err;
 355
 356         lockdep_assert_held(&vma->vm->mutex);
 357
 358         /* Just update our place in the LRU if our fence is getting reused. */
 359         if (vma->fence) {
 360                 fence = vma->fence;
 361                 GEM_BUG_ON(fence->vma != vma);
 362                 atomic_inc(&fence->pin_count);
 363                 if (!fence->dirty) {
 364                         list_move_tail(&fence->link, &ggtt->fence_list);
 365                         return 0;
 366                 }
 367         } else if (set) {
 368                 fence = fence_find(ggtt);
 369                 if (IS_ERR(fence))
 370                         return PTR_ERR(fence);
 371
 372                 GEM_BUG_ON(atomic_read(&fence->pin_count));
 373                 atomic_inc(&fence->pin_count);
 374         } else {
 375                 return 0;
 376         }
 377
 378         err = fence_update(fence, set);
 379         if (err)
 380                 goto out_unpin;
 381
 382         GEM_BUG_ON(fence->vma != set);
 383         GEM_BUG_ON(vma->fence != (set ? fence : NULL));
 384
 385         if (set)
 386                 return 0;
 387
 388 out_unpin:
 389         atomic_dec(&fence->pin_count);
 390         return err;
 391 }
 392
 393 /**
 394  * i915_vma_pin_fence - set up fencing for a vma
 395  * @vma: vma to map through a fence reg
 396  *
 397  * When mapping objects through the GTT, userspace wants to be able to write
 398  * to them without having to worry about swizzling if the object is tiled.
 399  * This function walks the fence regs looking for a free one for @obj,
 400  * stealing one if it can't find any.
 401  *
 402  * It then sets up the reg based on the object's properties: address, pitch
 403  * and tiling format.
 404  *
 405  * For an untiled surface, this removes any existing fence.
 406  *
 407  * Returns:
 408  *
 409  * 0 on success, negative error code on failure.
 410  */
 411 int i915_vma_pin_fence(struct i915_vma *vma)
 412 {
 413         int err;
 414
 415         /*
 416          * Note that we revoke fences on runtime suspend. Therefore the user
 417          * must keep the device awake whilst using the fence.
 418          */
 419         assert_rpm_wakelock_held(vma->vm->gt->uncore->rpm);
 420         GEM_BUG_ON(!i915_vma_is_pinned(vma));
 421         GEM_BUG_ON(!i915_vma_is_ggtt(vma));
 422
 423         err = mutex_lock_interruptible(&vma->vm->mutex);
 424         if (err)
 425                 return err;
 426
 427         err = __i915_vma_pin_fence(vma);
 428         mutex_unlock(&vma->vm->mutex);
 429
 430         return err;
 431 }
 432
 433 /**
 434  * i915_reserve_fence - Reserve a fence for vGPU
 435  * @ggtt: Global GTT
 436  *
 437  * This function walks the fence regs looking for a free one and remove
 438  * it from the fence_list. It is used to reserve fence for vGPU to use.
 439  */
 440 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt)
 441 {
 442         struct i915_fence_reg *fence;
 443         int count;
 444         int ret;
 445
 446         lockdep_assert_held(&ggtt->vm.mutex);
 447
 448         /* Keep at least one fence available for the display engine. */
 449         count = 0;
 450         list_for_each_entry(fence, &ggtt->fence_list, link)
 451                 count += !atomic_read(&fence->pin_count);
 452         if (count <= 1)
 453                 return ERR_PTR(-ENOSPC);
 454
 455         fence = fence_find(ggtt);
 456         if (IS_ERR(fence))
 457                 return fence;
 458
 459         if (fence->vma) {
 460                 /* Force-remove fence from VMA */
 461                 ret = fence_update(fence, NULL);
 462                 if (ret)
 463                         return ERR_PTR(ret);
 464         }
 465
 466         list_del(&fence->link);
 467
 468         return fence;
 469 }
 470
 471 /**
 472  * i915_unreserve_fence - Reclaim a reserved fence
 473  * @fence: the fence reg
 474  *
 475  * This function add a reserved fence register from vGPU to the fence_list.
 476  */
 477 void i915_unreserve_fence(struct i915_fence_reg *fence)
 478 {
 479         struct i915_ggtt *ggtt = fence->ggtt;
 480
 481         lockdep_assert_held(&ggtt->vm.mutex);
 482
 483         list_add(&fence->link, &ggtt->fence_list);
 484 }
 485
 486 /**
 487  * i915_gem_restore_fences - restore fence state
 488  * @ggtt: Global GTT
 489  *
 490  * Restore the hw fence state to match the software tracking again, to be called
 491  * after a gpu reset and on resume. Note that on runtime suspend we only cancel
 492  * the fences, to be reacquired by the user later.
 493  */
 494 void i915_gem_restore_fences(struct i915_ggtt *ggtt)
 495 {
 496         int i;
 497
 498         rcu_read_lock(); /* keep obj alive as we dereference */
 499         for (i = 0; i < ggtt->num_fences; i++) {
 500                 struct i915_fence_reg *reg = &ggtt->fence_regs[i];
 501                 struct i915_vma *vma = READ_ONCE(reg->vma);
 502
 503                 GEM_BUG_ON(vma && vma->fence != reg);
 504
 505                 /*
 506                  * Commit delayed tiling changes if we have an object still
 507                  * attached to the fence, otherwise just clear the fence.
 508                  */
 509                 if (vma && !i915_gem_object_is_tiled(vma->obj))
 510                         vma = NULL;
 511
 512                 fence_write(reg, vma);
 513         }
 514         rcu_read_unlock();
 515 }
 516
 517 /**
 518  * DOC: tiling swizzling details
 519  *
 520  * The idea behind tiling is to increase cache hit rates by rearranging
 521  * pixel data so that a group of pixel accesses are in the same cacheline.
 522  * Performance improvement from doing this on the back/depth buffer are on
 523  * the order of 30%.
 524  *
 525  * Intel architectures make this somewhat more complicated, though, by
 526  * adjustments made to addressing of data when the memory is in interleaved
 527  * mode (matched pairs of DIMMS) to improve memory bandwidth.
 528  * For interleaved memory, the CPU sends every sequential 64 bytes
 529  * to an alternate memory channel so it can get the bandwidth from both.
 530  *
 531  * The GPU also rearranges its accesses for increased bandwidth to interleaved
 532  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 533  * it does it a little differently, since one walks addresses not just in the
 534  * X direction but also Y.  So, along with alternating channels when bit
 535  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 536  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 537  * are common to both the 915 and 965-class hardware.
 538  *
 539  * The CPU also sometimes XORs in higher bits as well, to improve
 540  * bandwidth doing strided access like we do so frequently in graphics.  This
 541  * is called "Channel XOR Randomization" in the MCH documentation.  The result
 542  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 543  * decode.
 544  *
 545  * All of this bit 6 XORing has an effect on our memory management,
 546  * as we need to make sure that the 3d driver can correctly address object
 547  * contents.
 548  *
 549  * If we don't have interleaved memory, all tiling is safe and no swizzling is
 550  * required.
 551  *
 552  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 553  * 17 is not just a page offset, so as we page an object out and back in,
 554  * individual pages in it will have different bit 17 addresses, resulting in
 555  * each 64 bytes being swapped with its neighbor!
 556  *
 557  * Otherwise, if interleaved, we have to tell the 3d driver what the address
 558  * swizzling it needs to do is, since it's writing with the CPU to the pages
 559  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 560  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 561  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 562  * to match what the GPU expects.
 563  */
 564
 565 /**
 566  * detect_bit_6_swizzle - detect bit 6 swizzling pattern
 567  * @ggtt: Global GGTT
 568  *
 569  * Detects bit 6 swizzling of address lookup between IGD access and CPU
 570  * access through main memory.
 571  */
 572 static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 573 {
 574         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 575         struct drm_i915_private *i915 = ggtt->vm.i915;
 576         u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 577         u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 578
 579         if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
 580                 /*
 581                  * On BDW+, swizzling is not used. We leave the CPU memory
 582                  * controller in charge of optimizing memory accesses without
 583                  * the extra address manipulation GPU side.
 584                  *
 585                  * VLV and CHV don't have GPU swizzling.
 586                  */
 587                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 588                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 589         } else if (INTEL_GEN(i915) >= 6) {
 590                 if (i915->preserve_bios_swizzle) {
 591                         if (intel_uncore_read(uncore, DISP_ARB_CTL) &
 592                             DISP_TILE_SURFACE_SWIZZLING) {
 593                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 594                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 595                         } else {
 596                                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 597                                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 598                         }
 599                 } else {
 600                         u32 dimm_c0, dimm_c1;
 601                         dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0);
 602                         dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1);
 603                         dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 604                         dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 605                         /*
 606                          * Enable swizzling when the channels are populated
 607                          * with identically sized dimms. We don't need to check
 608                          * the 3rd channel because no cpu with gpu attached
 609                          * ships in that configuration. Also, swizzling only
 610                          * makes sense for 2 channels anyway.
 611                          */
 612                         if (dimm_c0 == dimm_c1) {
 613                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 614                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 615                         } else {
 616                                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 617                                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 618                         }
 619                 }
 620         } else if (IS_GEN(i915, 5)) {
 621                 /*
 622                  * On Ironlake whatever DRAM config, GPU always do
 623                  * same swizzling setup.
 624                  */
 625                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 626                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 627         } else if (IS_GEN(i915, 2)) {
 628                 /*
 629                  * As far as we know, the 865 doesn't have these bit 6
 630                  * swizzling issues.
 631                  */
 632                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 633                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 634         } else if (IS_G45(i915) || IS_I965G(i915) || IS_G33(i915)) {
 635                 /*
 636                  * The 965, G33, and newer, have a very flexible memory
 637                  * configuration.  It will enable dual-channel mode
 638                  * (interleaving) on as much memory as it can, and the GPU
 639                  * will additionally sometimes enable different bit 6
 640                  * swizzling for tiled objects from the CPU.
 641                  *
 642                  * Here's what I found on the G965:
 643                  *    slot fill         memory size  swizzling
 644                  * 0A   0B   1A   1B    1-ch   2-ch
 645                  * 512  0    0    0     512    0     O
 646                  * 512  0    512  0     16     1008  X
 647                  * 512  0    0    512   16     1008  X
 648                  * 0    512  0    512   16     1008  X
 649                  * 1024 1024 1024 0     2048   1024  O
 650                  *
 651                  * We could probably detect this based on either the DRB
 652                  * matching, which was the case for the swizzling required in
 653                  * the table above, or from the 1-ch value being less than
 654                  * the minimum size of a rank.
 655                  *
 656                  * Reports indicate that the swizzling actually
 657                  * varies depending upon page placement inside the
 658                  * channels, i.e. we see swizzled pages where the
 659                  * banks of memory are paired and unswizzled on the
 660                  * uneven portion, so leave that as unknown.
 661                  */
 662                 if (intel_uncore_read(uncore, C0DRB3) ==
 663                     intel_uncore_read(uncore, C1DRB3)) {
 664                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 665                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 666                 }
 667         } else {
 668                 u32 dcc = intel_uncore_read(uncore, DCC);
 669
 670                 /*
 671                  * On 9xx chipsets, channel interleave by the CPU is
 672                  * determined by DCC.  For single-channel, neither the CPU
 673                  * nor the GPU do swizzling.  For dual channel interleaved,
 674                  * the GPU's interleave is bit 9 and 10 for X tiled, and bit
 675                  * 9 for Y tiled.  The CPU's interleave is independent, and
 676                  * can be based on either bit 11 (haven't seen this yet) or
 677                  * bit 17 (common).
 678                  */
 679                 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
 680                 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
 681                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
 682                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 683                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 684                         break;
 685                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
 686                         if (dcc & DCC_CHANNEL_XOR_DISABLE) {
 687                                 /*
 688                                  * This is the base swizzling by the GPU for
 689                                  * tiled buffers.
 690                                  */
 691                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 692                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 693                         } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
 694                                 /* Bit 11 swizzling by the CPU in addition. */
 695                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
 696                                 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
 697                         } else {
 698                                 /* Bit 17 swizzling by the CPU in addition. */
 699                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 700                                 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 701                         }
 702                         break;
 703                 }
 704
 705                 /* check for L-shaped memory aka modified enhanced addressing */
 706                 if (IS_GEN(i915, 4) &&
 707                     !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
 708                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 709                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 710                 }
 711
 712                 if (dcc == 0xffffffff) {
 713                         DRM_ERROR("Couldn't read from MCHBAR.  "
 714                                   "Disabling tiling.\n");
 715                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 716                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 717                 }
 718         }
 719
 720         if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
 721             swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
 722                 /*
 723                  * Userspace likes to explode if it sees unknown swizzling,
 724                  * so lie. We will finish the lie when reporting through
 725                  * the get-tiling-ioctl by reporting the physical swizzle
 726                  * mode as unknown instead.
 727                  *
 728                  * As we don't strictly know what the swizzling is, it may be
 729                  * bit17 dependent, and so we need to also prevent the pages
 730                  * from being moved.
 731                  */
 732                 i915->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
 733                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 734                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 735         }
 736
 737         i915->ggtt.bit_6_swizzle_x = swizzle_x;
 738         i915->ggtt.bit_6_swizzle_y = swizzle_y;
 739 }
 740
 741 /*
 742  * Swap every 64 bytes of this page around, to account for it having a new
 743  * bit 17 of its physical address and therefore being interpreted differently
 744  * by the GPU.
 745  */
 746 static void i915_gem_swizzle_page(struct page *page)
 747 {
 748         char temp[64];
 749         char *vaddr;
 750         int i;
 751
 752         vaddr = kmap(page);
 753
 754         for (i = 0; i < PAGE_SIZE; i += 128) {
 755                 memcpy(temp, &vaddr[i], 64);
 756                 memcpy(&vaddr[i], &vaddr[i + 64], 64);
 757                 memcpy(&vaddr[i + 64], temp, 64);
 758         }
 759
 760         kunmap(page);
 761 }
 762
 763 /**
 764  * i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling
 765  * @obj: i915 GEM buffer object
 766  * @pages: the scattergather list of physical pages
 767  *
 768  * This function fixes up the swizzling in case any page frame number for this
 769  * object has changed in bit 17 since that state has been saved with
 770  * i915_gem_object_save_bit_17_swizzle().
 771  *
 772  * This is called when pinning backing storage again, since the kernel is free
 773  * to move unpinned backing storage around (either by directly moving pages or
 774  * by swapping them out and back in again).
 775  */
 776 void
 777 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
 778                                   struct sg_table *pages)
 779 {
 780         struct sgt_iter sgt_iter;
 781         struct page *page;
 782         int i;
 783
 784         if (obj->bit_17 == NULL)
 785                 return;
 786
 787         i = 0;
 788         for_each_sgt_page(page, sgt_iter, pages) {
 789                 char new_bit_17 = page_to_phys(page) >> 17;
 790                 if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {
 791                         i915_gem_swizzle_page(page);
 792                         set_page_dirty(page);
 793                 }
 794                 i++;
 795         }
 796 }
 797
 798 /**
 799  * i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling
 800  * @obj: i915 GEM buffer object
 801  * @pages: the scattergather list of physical pages
 802  *
 803  * This function saves the bit 17 of each page frame number so that swizzling
 804  * can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must
 805  * be called before the backing storage can be unpinned.
 806  */
 807 void
 808 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 809                                     struct sg_table *pages)
 810 {
 811         const unsigned int page_count = obj->base.size >> PAGE_SHIFT;
 812         struct sgt_iter sgt_iter;
 813         struct page *page;
 814         int i;
 815
 816         if (obj->bit_17 == NULL) {
 817                 obj->bit_17 = bitmap_zalloc(page_count, GFP_KERNEL);
 818                 if (obj->bit_17 == NULL) {
 819                         DRM_ERROR("Failed to allocate memory for bit 17 "
 820                                   "record\n");
 821                         return;
 822                 }
 823         }
 824
 825         i = 0;
 826
 827         for_each_sgt_page(page, sgt_iter, pages) {
 828                 if (page_to_phys(page) & (1 << 17))
 829                         __set_bit(i, obj->bit_17);
 830                 else
 831                         __clear_bit(i, obj->bit_17);
 832                 i++;
 833         }
 834 }
 835
 836 void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
 837 {
 838         struct drm_i915_private *i915 = ggtt->vm.i915;
 839         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 840         int num_fences;
 841         int i;
 842
 843         INIT_LIST_HEAD(&ggtt->fence_list);
 844         INIT_LIST_HEAD(&ggtt->userfault_list);
 845         intel_wakeref_auto_init(&ggtt->userfault_wakeref, uncore->rpm);
 846
 847         detect_bit_6_swizzle(ggtt);
 848
 849         if (!i915_ggtt_has_aperture(ggtt))
 850                 num_fences = 0;
 851         else if (INTEL_GEN(i915) >= 7 &&
 852                  !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
 853                 num_fences = 32;
 854         else if (INTEL_GEN(i915) >= 4 ||
 855                  IS_I945G(i915) || IS_I945GM(i915) ||
 856                  IS_G33(i915) || IS_PINEVIEW(i915))
 857                 num_fences = 16;
 858         else
 859                 num_fences = 8;
 860
 861         if (intel_vgpu_active(i915))
 862                 num_fences = intel_uncore_read(uncore,
 863                                                vgtif_reg(avail_rs.fence_num));
 864
 865         /* Initialize fence registers to zero */
 866         for (i = 0; i < num_fences; i++) {
 867                 struct i915_fence_reg *fence = &ggtt->fence_regs[i];
 868
 869                 fence->ggtt = ggtt;
 870                 fence->id = i;
 871                 list_add_tail(&fence->link, &ggtt->fence_list);
 872         }
 873         ggtt->num_fences = num_fences;
 874
 875         i915_gem_restore_fences(ggtt);
 876 }
 877
 878 void intel_gt_init_swizzling(struct intel_gt *gt)
 879 {
 880         struct drm_i915_private *i915 = gt->i915;
 881         struct intel_uncore *uncore = gt->uncore;
 882
 883         if (INTEL_GEN(i915) < 5 ||
 884             i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 885                 return;
 886
 887         intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
 888
 889         if (IS_GEN(i915, 5))
 890                 return;
 891
 892         intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
 893
 894         if (IS_GEN(i915, 6))
 895                 intel_uncore_write(uncore,
 896                                    ARB_MODE,
 897                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
 898         else if (IS_GEN(i915, 7))
 899                 intel_uncore_write(uncore,
 900                                    ARB_MODE,
 901                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
 902         else if (IS_GEN(i915, 8))
 903                 intel_uncore_write(uncore,
 904                                    GAMTARBMODE,
 905                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
 906         else
 907                 MISSING_CASE(INTEL_GEN(i915));
 908 }