2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/slab.h> /* fault-inject.h is not standalone! */
28 #include <linux/fault-inject.h>
29 #include <linux/log2.h>
30 #include <linux/random.h>
31 #include <linux/seq_file.h>
32 #include <linux/stop_machine.h>
34 #include <asm/set_memory.h>
36 #include <drm/i915_drm.h>
39 #include "i915_vgpu.h"
40 #include "i915_reset.h"
41 #include "i915_trace.h"
42 #include "intel_drv.h"
43 #include "intel_frontbuffer.h"
45 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
48 * DOC: Global GTT views
50 * Background and previous state
52 * Historically objects could exists (be bound) in global GTT space only as
53 * singular instances with a view representing all of the object's backing pages
54 * in a linear fashion. This view will be called a normal view.
56 * To support multiple views of the same object, where the number of mapped
57 * pages is not equal to the backing store, or where the layout of the pages
58 * is not linear, concept of a GGTT view was added.
60 * One example of an alternative view is a stereo display driven by a single
61 * image. In this case we would have a framebuffer looking like this
67 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
68 * rendering. In contrast, fed to the display engine would be an alternative
69 * view which could look something like this:
74 * In this example both the size and layout of pages in the alternative view is
75 * different from the normal view.
77 * Implementation and usage
79 * GGTT views are implemented using VMAs and are distinguished via enum
80 * i915_ggtt_view_type and struct i915_ggtt_view.
82 * A new flavour of core GEM functions which work with GGTT bound objects were
83 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
84 * renaming in large amounts of code. They take the struct i915_ggtt_view
85 * parameter encapsulating all metadata required to implement a view.
87 * As a helper for callers which are only interested in the normal view,
88 * globally const i915_ggtt_view_normal singleton instance exists. All old core
89 * GEM API functions, the ones not taking the view parameter, are operating on,
90 * or with the normal GGTT view.
92 * Code wanting to add or use a new GGTT view needs to:
94 * 1. Add a new enum with a suitable name.
95 * 2. Extend the metadata in the i915_ggtt_view structure if required.
96 * 3. Add support to i915_get_vma_pages().
98 * New views are required to build a scatter-gather table from within the
99 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
100 * exists for the lifetime of an VMA.
102 * Core API is designed to have copy semantics which means that passed in
103 * struct i915_ggtt_view does not need to be persistent (left around after
104 * calling the core API functions).
109 i915_get_ggtt_vma_pages(struct i915_vma *vma);
111 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
114 * Note that as an uncached mmio write, this will flush the
115 * WCB of the writes into the GGTT before it triggers the invalidate.
117 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
120 static void guc_ggtt_invalidate(struct drm_i915_private *dev_priv)
122 gen6_ggtt_invalidate(dev_priv);
123 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
126 static void gmch_ggtt_invalidate(struct drm_i915_private *dev_priv)
128 intel_gtt_chipset_flush();
131 static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
133 i915->ggtt.invalidate(i915);
136 static int ppgtt_bind_vma(struct i915_vma *vma,
137 enum i915_cache_level cache_level,
143 if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
144 err = vma->vm->allocate_va_range(vma->vm,
145 vma->node.start, vma->size);
150 /* Applicable to VLV, and gen8+ */
152 if (i915_gem_object_is_readonly(vma->obj))
153 pte_flags |= PTE_READ_ONLY;
155 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
160 static void ppgtt_unbind_vma(struct i915_vma *vma)
162 vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
165 static int ppgtt_set_pages(struct i915_vma *vma)
167 GEM_BUG_ON(vma->pages);
169 vma->pages = vma->obj->mm.pages;
171 vma->page_sizes = vma->obj->mm.page_sizes;
176 static void clear_pages(struct i915_vma *vma)
178 GEM_BUG_ON(!vma->pages);
180 if (vma->pages != vma->obj->mm.pages) {
181 sg_free_table(vma->pages);
186 memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
189 static u64 gen8_pte_encode(dma_addr_t addr,
190 enum i915_cache_level level,
193 gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
195 if (unlikely(flags & PTE_READ_ONLY))
199 case I915_CACHE_NONE:
200 pte |= PPAT_UNCACHED;
203 pte |= PPAT_DISPLAY_ELLC;
213 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
214 const enum i915_cache_level level)
216 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
218 if (level != I915_CACHE_NONE)
219 pde |= PPAT_CACHED_PDE;
221 pde |= PPAT_UNCACHED;
225 #define gen8_pdpe_encode gen8_pde_encode
226 #define gen8_pml4e_encode gen8_pde_encode
228 static u64 snb_pte_encode(dma_addr_t addr,
229 enum i915_cache_level level,
232 gen6_pte_t pte = GEN6_PTE_VALID;
233 pte |= GEN6_PTE_ADDR_ENCODE(addr);
236 case I915_CACHE_L3_LLC:
238 pte |= GEN6_PTE_CACHE_LLC;
240 case I915_CACHE_NONE:
241 pte |= GEN6_PTE_UNCACHED;
250 static u64 ivb_pte_encode(dma_addr_t addr,
251 enum i915_cache_level level,
254 gen6_pte_t pte = GEN6_PTE_VALID;
255 pte |= GEN6_PTE_ADDR_ENCODE(addr);
258 case I915_CACHE_L3_LLC:
259 pte |= GEN7_PTE_CACHE_L3_LLC;
262 pte |= GEN6_PTE_CACHE_LLC;
264 case I915_CACHE_NONE:
265 pte |= GEN6_PTE_UNCACHED;
274 static u64 byt_pte_encode(dma_addr_t addr,
275 enum i915_cache_level level,
278 gen6_pte_t pte = GEN6_PTE_VALID;
279 pte |= GEN6_PTE_ADDR_ENCODE(addr);
281 if (!(flags & PTE_READ_ONLY))
282 pte |= BYT_PTE_WRITEABLE;
284 if (level != I915_CACHE_NONE)
285 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
290 static u64 hsw_pte_encode(dma_addr_t addr,
291 enum i915_cache_level level,
294 gen6_pte_t pte = GEN6_PTE_VALID;
295 pte |= HSW_PTE_ADDR_ENCODE(addr);
297 if (level != I915_CACHE_NONE)
298 pte |= HSW_WB_LLC_AGE3;
303 static u64 iris_pte_encode(dma_addr_t addr,
304 enum i915_cache_level level,
307 gen6_pte_t pte = GEN6_PTE_VALID;
308 pte |= HSW_PTE_ADDR_ENCODE(addr);
311 case I915_CACHE_NONE:
314 pte |= HSW_WT_ELLC_LLC_AGE3;
317 pte |= HSW_WB_ELLC_LLC_AGE3;
324 static void stash_init(struct pagestash *stash)
326 pagevec_init(&stash->pvec);
327 spin_lock_init(&stash->lock);
330 static struct page *stash_pop_page(struct pagestash *stash)
332 struct page *page = NULL;
334 spin_lock(&stash->lock);
335 if (likely(stash->pvec.nr))
336 page = stash->pvec.pages[--stash->pvec.nr];
337 spin_unlock(&stash->lock);
342 static void stash_push_pagevec(struct pagestash *stash, struct pagevec *pvec)
346 spin_lock_nested(&stash->lock, SINGLE_DEPTH_NESTING);
348 nr = min_t(int, pvec->nr, pagevec_space(&stash->pvec));
349 memcpy(stash->pvec.pages + stash->pvec.nr,
350 pvec->pages + pvec->nr - nr,
351 sizeof(pvec->pages[0]) * nr);
352 stash->pvec.nr += nr;
354 spin_unlock(&stash->lock);
359 static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
361 struct pagevec stack;
364 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
365 i915_gem_shrink_all(vm->i915);
367 page = stash_pop_page(&vm->free_pages);
372 return alloc_page(gfp);
374 /* Look in our global stash of WC pages... */
375 page = stash_pop_page(&vm->i915->mm.wc_stash);
380 * Otherwise batch allocate pages to amortize cost of set_pages_wc.
382 * We have to be careful as page allocation may trigger the shrinker
383 * (via direct reclaim) which will fill up the WC stash underneath us.
384 * So we add our WB pages into a temporary pvec on the stack and merge
385 * them into the WC stash after all the allocations are complete.
387 pagevec_init(&stack);
391 page = alloc_page(gfp);
395 stack.pages[stack.nr++] = page;
396 } while (pagevec_space(&stack));
398 if (stack.nr && !set_pages_array_wc(stack.pages, stack.nr)) {
399 page = stack.pages[--stack.nr];
401 /* Merge spare WC pages to the global stash */
402 stash_push_pagevec(&vm->i915->mm.wc_stash, &stack);
404 /* Push any surplus WC pages onto the local VM stash */
406 stash_push_pagevec(&vm->free_pages, &stack);
409 /* Return unwanted leftovers */
410 if (unlikely(stack.nr)) {
411 WARN_ON_ONCE(set_pages_array_wb(stack.pages, stack.nr));
412 __pagevec_release(&stack);
418 static void vm_free_pages_release(struct i915_address_space *vm,
421 struct pagevec *pvec = &vm->free_pages.pvec;
422 struct pagevec stack;
424 lockdep_assert_held(&vm->free_pages.lock);
425 GEM_BUG_ON(!pagevec_count(pvec));
427 if (vm->pt_kmap_wc) {
429 * When we use WC, first fill up the global stash and then
430 * only if full immediately free the overflow.
432 stash_push_pagevec(&vm->i915->mm.wc_stash, pvec);
435 * As we have made some room in the VM's free_pages,
436 * we can wait for it to fill again. Unless we are
437 * inside i915_address_space_fini() and must
438 * immediately release the pages!
440 if (pvec->nr <= (immediate ? 0 : PAGEVEC_SIZE - 1))
444 * We have to drop the lock to allow ourselves to sleep,
445 * so take a copy of the pvec and clear the stash for
446 * others to use it as we sleep.
449 pagevec_reinit(pvec);
450 spin_unlock(&vm->free_pages.lock);
453 set_pages_array_wb(pvec->pages, pvec->nr);
455 spin_lock(&vm->free_pages.lock);
458 __pagevec_release(pvec);
461 static void vm_free_page(struct i915_address_space *vm, struct page *page)
464 * On !llc, we need to change the pages back to WB. We only do so
465 * in bulk, so we rarely need to change the page attributes here,
466 * but doing so requires a stop_machine() from deep inside arch/x86/mm.
467 * To make detection of the possible sleep more likely, use an
468 * unconditional might_sleep() for everybody.
471 spin_lock(&vm->free_pages.lock);
472 if (!pagevec_add(&vm->free_pages.pvec, page))
473 vm_free_pages_release(vm, false);
474 spin_unlock(&vm->free_pages.lock);
477 static void i915_address_space_init(struct i915_address_space *vm, int subclass)
480 * The vm->mutex must be reclaim safe (for use in the shrinker).
481 * Do a dummy acquire now under fs_reclaim so that any allocation
482 * attempt holding the lock is immediately reported by lockdep.
484 mutex_init(&vm->mutex);
485 lockdep_set_subclass(&vm->mutex, subclass);
486 i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex);
488 GEM_BUG_ON(!vm->total);
489 drm_mm_init(&vm->mm, 0, vm->total);
490 vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
492 stash_init(&vm->free_pages);
494 INIT_LIST_HEAD(&vm->unbound_list);
495 INIT_LIST_HEAD(&vm->bound_list);
498 static void i915_address_space_fini(struct i915_address_space *vm)
500 spin_lock(&vm->free_pages.lock);
501 if (pagevec_count(&vm->free_pages.pvec))
502 vm_free_pages_release(vm, true);
503 GEM_BUG_ON(pagevec_count(&vm->free_pages.pvec));
504 spin_unlock(&vm->free_pages.lock);
506 drm_mm_takedown(&vm->mm);
508 mutex_destroy(&vm->mutex);
511 static int __setup_page_dma(struct i915_address_space *vm,
512 struct i915_page_dma *p,
515 p->page = vm_alloc_page(vm, gfp | I915_GFP_ALLOW_FAIL);
516 if (unlikely(!p->page))
519 p->daddr = dma_map_page_attrs(vm->dma,
520 p->page, 0, PAGE_SIZE,
521 PCI_DMA_BIDIRECTIONAL,
522 DMA_ATTR_SKIP_CPU_SYNC |
524 if (unlikely(dma_mapping_error(vm->dma, p->daddr))) {
525 vm_free_page(vm, p->page);
532 static int setup_page_dma(struct i915_address_space *vm,
533 struct i915_page_dma *p)
535 return __setup_page_dma(vm, p, __GFP_HIGHMEM);
538 static void cleanup_page_dma(struct i915_address_space *vm,
539 struct i915_page_dma *p)
541 dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
542 vm_free_page(vm, p->page);
545 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
547 #define setup_px(vm, px) setup_page_dma((vm), px_base(px))
548 #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
549 #define fill_px(vm, px, v) fill_page_dma((vm), px_base(px), (v))
550 #define fill32_px(vm, px, v) fill_page_dma_32((vm), px_base(px), (v))
552 static void fill_page_dma(struct i915_address_space *vm,
553 struct i915_page_dma *p,
556 u64 * const vaddr = kmap_atomic(p->page);
558 memset64(vaddr, val, PAGE_SIZE / sizeof(val));
560 kunmap_atomic(vaddr);
563 static void fill_page_dma_32(struct i915_address_space *vm,
564 struct i915_page_dma *p,
567 fill_page_dma(vm, p, (u64)v << 32 | v);
571 setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
576 * In order to utilize 64K pages for an object with a size < 2M, we will
577 * need to support a 64K scratch page, given that every 16th entry for a
578 * page-table operating in 64K mode must point to a properly aligned 64K
579 * region, including any PTEs which happen to point to scratch.
581 * This is only relevant for the 48b PPGTT where we support
582 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the
583 * scratch (read-only) between all vm, we create one 64k scratch page
586 size = I915_GTT_PAGE_SIZE_4K;
587 if (i915_vm_is_4lvl(vm) &&
588 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
589 size = I915_GTT_PAGE_SIZE_64K;
592 gfp |= __GFP_ZERO | __GFP_RETRY_MAYFAIL;
595 int order = get_order(size);
599 page = alloc_pages(gfp, order);
603 addr = dma_map_page_attrs(vm->dma,
605 PCI_DMA_BIDIRECTIONAL,
606 DMA_ATTR_SKIP_CPU_SYNC |
608 if (unlikely(dma_mapping_error(vm->dma, addr)))
611 if (unlikely(!IS_ALIGNED(addr, size)))
614 vm->scratch_page.page = page;
615 vm->scratch_page.daddr = addr;
616 vm->scratch_order = order;
620 dma_unmap_page(vm->dma, addr, size, PCI_DMA_BIDIRECTIONAL);
622 __free_pages(page, order);
624 if (size == I915_GTT_PAGE_SIZE_4K)
627 size = I915_GTT_PAGE_SIZE_4K;
628 gfp &= ~__GFP_NOWARN;
632 static void cleanup_scratch_page(struct i915_address_space *vm)
634 struct i915_page_dma *p = &vm->scratch_page;
635 int order = vm->scratch_order;
637 dma_unmap_page(vm->dma, p->daddr, BIT(order) << PAGE_SHIFT,
638 PCI_DMA_BIDIRECTIONAL);
639 __free_pages(p->page, order);
642 static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
644 struct i915_page_table *pt;
646 pt = kmalloc(sizeof(*pt), I915_GFP_ALLOW_FAIL);
648 return ERR_PTR(-ENOMEM);
650 if (unlikely(setup_px(vm, pt))) {
652 return ERR_PTR(-ENOMEM);
659 static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt)
665 static void gen8_initialize_pt(struct i915_address_space *vm,
666 struct i915_page_table *pt)
668 fill_px(vm, pt, vm->scratch_pte);
671 static void gen6_initialize_pt(struct i915_address_space *vm,
672 struct i915_page_table *pt)
674 fill32_px(vm, pt, vm->scratch_pte);
677 static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
679 struct i915_page_directory *pd;
681 pd = kzalloc(sizeof(*pd), I915_GFP_ALLOW_FAIL);
683 return ERR_PTR(-ENOMEM);
685 if (unlikely(setup_px(vm, pd))) {
687 return ERR_PTR(-ENOMEM);
694 static void free_pd(struct i915_address_space *vm,
695 struct i915_page_directory *pd)
701 static void gen8_initialize_pd(struct i915_address_space *vm,
702 struct i915_page_directory *pd)
705 gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC));
706 memset_p((void **)pd->page_table, vm->scratch_pt, I915_PDES);
709 static int __pdp_init(struct i915_address_space *vm,
710 struct i915_page_directory_pointer *pdp)
712 const unsigned int pdpes = i915_pdpes_per_pdp(vm);
714 pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory),
715 I915_GFP_ALLOW_FAIL);
716 if (unlikely(!pdp->page_directory))
719 memset_p((void **)pdp->page_directory, vm->scratch_pd, pdpes);
724 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
726 kfree(pdp->page_directory);
727 pdp->page_directory = NULL;
730 static struct i915_page_directory_pointer *
731 alloc_pdp(struct i915_address_space *vm)
733 struct i915_page_directory_pointer *pdp;
736 GEM_BUG_ON(!i915_vm_is_4lvl(vm));
738 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
740 return ERR_PTR(-ENOMEM);
742 ret = __pdp_init(vm, pdp);
746 ret = setup_px(vm, pdp);
760 static void free_pdp(struct i915_address_space *vm,
761 struct i915_page_directory_pointer *pdp)
765 if (!i915_vm_is_4lvl(vm))
772 static void gen8_initialize_pdp(struct i915_address_space *vm,
773 struct i915_page_directory_pointer *pdp)
775 gen8_ppgtt_pdpe_t scratch_pdpe;
777 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
779 fill_px(vm, pdp, scratch_pdpe);
782 static void gen8_initialize_pml4(struct i915_address_space *vm,
783 struct i915_pml4 *pml4)
786 gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC));
787 memset_p((void **)pml4->pdps, vm->scratch_pdp, GEN8_PML4ES_PER_PML4);
791 * PDE TLBs are a pain to invalidate on GEN8+. When we modify
792 * the page table structures, we mark them dirty so that
793 * context switching/execlist queuing code takes extra steps
794 * to ensure that tlbs are flushed.
796 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
798 ppgtt->pd_dirty_engines = ALL_ENGINES;
801 /* Removes entries from a single page table, releasing it if it's empty.
802 * Caller can use the return value to update higher-level entries.
804 static bool gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
805 struct i915_page_table *pt,
806 u64 start, u64 length)
808 unsigned int num_entries = gen8_pte_count(start, length);
811 GEM_BUG_ON(num_entries > pt->used_ptes);
813 pt->used_ptes -= num_entries;
817 vaddr = kmap_atomic_px(pt);
818 memset64(vaddr + gen8_pte_index(start), vm->scratch_pte, num_entries);
819 kunmap_atomic(vaddr);
824 static void gen8_ppgtt_set_pde(struct i915_address_space *vm,
825 struct i915_page_directory *pd,
826 struct i915_page_table *pt,
831 pd->page_table[pde] = pt;
833 vaddr = kmap_atomic_px(pd);
834 vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC);
835 kunmap_atomic(vaddr);
838 static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
839 struct i915_page_directory *pd,
840 u64 start, u64 length)
842 struct i915_page_table *pt;
845 gen8_for_each_pde(pt, pd, start, length, pde) {
846 GEM_BUG_ON(pt == vm->scratch_pt);
848 if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
851 gen8_ppgtt_set_pde(vm, pd, vm->scratch_pt, pde);
852 GEM_BUG_ON(!pd->used_pdes);
858 return !pd->used_pdes;
861 static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm,
862 struct i915_page_directory_pointer *pdp,
863 struct i915_page_directory *pd,
866 gen8_ppgtt_pdpe_t *vaddr;
868 pdp->page_directory[pdpe] = pd;
869 if (!i915_vm_is_4lvl(vm))
872 vaddr = kmap_atomic_px(pdp);
873 vaddr[pdpe] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
874 kunmap_atomic(vaddr);
877 /* Removes entries from a single page dir pointer, releasing it if it's empty.
878 * Caller can use the return value to update higher-level entries
880 static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
881 struct i915_page_directory_pointer *pdp,
882 u64 start, u64 length)
884 struct i915_page_directory *pd;
887 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
888 GEM_BUG_ON(pd == vm->scratch_pd);
890 if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
893 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
894 GEM_BUG_ON(!pdp->used_pdpes);
900 return !pdp->used_pdpes;
903 static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm,
904 u64 start, u64 length)
906 gen8_ppgtt_clear_pdp(vm, &i915_vm_to_ppgtt(vm)->pdp, start, length);
909 static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
910 struct i915_page_directory_pointer *pdp,
913 gen8_ppgtt_pml4e_t *vaddr;
915 pml4->pdps[pml4e] = pdp;
917 vaddr = kmap_atomic_px(pml4);
918 vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
919 kunmap_atomic(vaddr);
922 /* Removes entries from a single pml4.
923 * This is the top-level structure in 4-level page tables used on gen8+.
924 * Empty entries are always scratch pml4e.
926 static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
927 u64 start, u64 length)
929 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
930 struct i915_pml4 *pml4 = &ppgtt->pml4;
931 struct i915_page_directory_pointer *pdp;
934 GEM_BUG_ON(!i915_vm_is_4lvl(vm));
936 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
937 GEM_BUG_ON(pdp == vm->scratch_pdp);
939 if (!gen8_ppgtt_clear_pdp(vm, pdp, start, length))
942 gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
948 static inline struct sgt_dma {
949 struct scatterlist *sg;
951 } sgt_dma(struct i915_vma *vma) {
952 struct scatterlist *sg = vma->pages->sgl;
953 dma_addr_t addr = sg_dma_address(sg);
954 return (struct sgt_dma) { sg, addr, addr + sg->length };
957 struct gen8_insert_pte {
964 static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start)
966 return (struct gen8_insert_pte) {
967 gen8_pml4e_index(start),
968 gen8_pdpe_index(start),
969 gen8_pde_index(start),
970 gen8_pte_index(start),
974 static __always_inline bool
975 gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
976 struct i915_page_directory_pointer *pdp,
977 struct sgt_dma *iter,
978 struct gen8_insert_pte *idx,
979 enum i915_cache_level cache_level,
982 struct i915_page_directory *pd;
983 const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
987 GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
988 pd = pdp->page_directory[idx->pdpe];
989 vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
991 vaddr[idx->pte] = pte_encode | iter->dma;
993 iter->dma += I915_GTT_PAGE_SIZE;
994 if (iter->dma >= iter->max) {
995 iter->sg = __sg_next(iter->sg);
1001 iter->dma = sg_dma_address(iter->sg);
1002 iter->max = iter->dma + iter->sg->length;
1005 if (++idx->pte == GEN8_PTES) {
1008 if (++idx->pde == I915_PDES) {
1011 /* Limited by sg length for 3lvl */
1012 if (++idx->pdpe == GEN8_PML4ES_PER_PML4) {
1018 GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
1019 pd = pdp->page_directory[idx->pdpe];
1022 kunmap_atomic(vaddr);
1023 vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
1026 kunmap_atomic(vaddr);
1031 static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
1032 struct i915_vma *vma,
1033 enum i915_cache_level cache_level,
1036 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1037 struct sgt_dma iter = sgt_dma(vma);
1038 struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
1040 gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
1041 cache_level, flags);
1043 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
1046 static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
1047 struct i915_page_directory_pointer **pdps,
1048 struct sgt_dma *iter,
1049 enum i915_cache_level cache_level,
1052 const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
1053 u64 start = vma->node.start;
1054 dma_addr_t rem = iter->sg->length;
1057 struct gen8_insert_pte idx = gen8_insert_pte(start);
1058 struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
1059 struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
1060 unsigned int page_size;
1061 bool maybe_64K = false;
1062 gen8_pte_t encode = pte_encode;
1066 if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
1067 IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
1068 rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) {
1071 page_size = I915_GTT_PAGE_SIZE_2M;
1073 encode |= GEN8_PDE_PS_2M;
1075 vaddr = kmap_atomic_px(pd);
1077 struct i915_page_table *pt = pd->page_table[idx.pde];
1081 page_size = I915_GTT_PAGE_SIZE;
1084 vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
1085 IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
1086 (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
1087 rem >= (max - index) * I915_GTT_PAGE_SIZE))
1090 vaddr = kmap_atomic_px(pt);
1094 GEM_BUG_ON(iter->sg->length < page_size);
1095 vaddr[index++] = encode | iter->dma;
1098 iter->dma += page_size;
1100 if (iter->dma >= iter->max) {
1101 iter->sg = __sg_next(iter->sg);
1105 rem = iter->sg->length;
1106 iter->dma = sg_dma_address(iter->sg);
1107 iter->max = iter->dma + rem;
1109 if (maybe_64K && index < max &&
1110 !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
1111 (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
1112 rem >= (max - index) * I915_GTT_PAGE_SIZE)))
1115 if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
1118 } while (rem >= page_size && index < max);
1120 kunmap_atomic(vaddr);
1123 * Is it safe to mark the 2M block as 64K? -- Either we have
1124 * filled whole page-table with 64K entries, or filled part of
1125 * it and have reached the end of the sg table and we have
1130 (i915_vm_has_scratch_64K(vma->vm) &&
1131 !iter->sg && IS_ALIGNED(vma->node.start +
1133 I915_GTT_PAGE_SIZE_2M)))) {
1134 vaddr = kmap_atomic_px(pd);
1135 vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
1136 kunmap_atomic(vaddr);
1137 page_size = I915_GTT_PAGE_SIZE_64K;
1140 * We write all 4K page entries, even when using 64K
1141 * pages. In order to verify that the HW isn't cheating
1142 * by using the 4K PTE instead of the 64K PTE, we want
1143 * to remove all the surplus entries. If the HW skipped
1144 * the 64K PTE, it will read/write into the scratch page
1145 * instead - which we detect as missing results during
1148 if (I915_SELFTEST_ONLY(vma->vm->scrub_64K)) {
1151 encode = vma->vm->scratch_pte;
1152 vaddr = kmap_atomic_px(pd->page_table[idx.pde]);
1154 for (i = 1; i < index; i += 16)
1155 memset64(vaddr + i, encode, 15);
1157 kunmap_atomic(vaddr);
1161 vma->page_sizes.gtt |= page_size;
1165 static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
1166 struct i915_vma *vma,
1167 enum i915_cache_level cache_level,
1170 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1171 struct sgt_dma iter = sgt_dma(vma);
1172 struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
1174 if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
1175 gen8_ppgtt_insert_huge_entries(vma, pdps, &iter, cache_level,
1178 struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
1180 while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
1181 &iter, &idx, cache_level,
1183 GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
1185 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
1189 static void gen8_free_page_tables(struct i915_address_space *vm,
1190 struct i915_page_directory *pd)
1194 for (i = 0; i < I915_PDES; i++) {
1195 if (pd->page_table[i] != vm->scratch_pt)
1196 free_pt(vm, pd->page_table[i]);
1200 static int gen8_init_scratch(struct i915_address_space *vm)
1205 * If everybody agrees to not to write into the scratch page,
1206 * we can reuse it for all vm, keeping contexts and processes separate.
1208 if (vm->has_read_only &&
1209 vm->i915->kernel_context &&
1210 vm->i915->kernel_context->ppgtt) {
1211 struct i915_address_space *clone =
1212 &vm->i915->kernel_context->ppgtt->vm;
1214 GEM_BUG_ON(!clone->has_read_only);
1216 vm->scratch_order = clone->scratch_order;
1217 vm->scratch_pte = clone->scratch_pte;
1218 vm->scratch_pt = clone->scratch_pt;
1219 vm->scratch_pd = clone->scratch_pd;
1220 vm->scratch_pdp = clone->scratch_pdp;
1224 ret = setup_scratch_page(vm, __GFP_HIGHMEM);
1229 gen8_pte_encode(vm->scratch_page.daddr,
1233 vm->scratch_pt = alloc_pt(vm);
1234 if (IS_ERR(vm->scratch_pt)) {
1235 ret = PTR_ERR(vm->scratch_pt);
1236 goto free_scratch_page;
1239 vm->scratch_pd = alloc_pd(vm);
1240 if (IS_ERR(vm->scratch_pd)) {
1241 ret = PTR_ERR(vm->scratch_pd);
1245 if (i915_vm_is_4lvl(vm)) {
1246 vm->scratch_pdp = alloc_pdp(vm);
1247 if (IS_ERR(vm->scratch_pdp)) {
1248 ret = PTR_ERR(vm->scratch_pdp);
1253 gen8_initialize_pt(vm, vm->scratch_pt);
1254 gen8_initialize_pd(vm, vm->scratch_pd);
1255 if (i915_vm_is_4lvl(vm))
1256 gen8_initialize_pdp(vm, vm->scratch_pdp);
1261 free_pd(vm, vm->scratch_pd);
1263 free_pt(vm, vm->scratch_pt);
1265 cleanup_scratch_page(vm);
1270 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
1272 struct i915_address_space *vm = &ppgtt->vm;
1273 struct drm_i915_private *dev_priv = vm->i915;
1274 enum vgt_g2v_type msg;
1277 if (i915_vm_is_4lvl(vm)) {
1278 const u64 daddr = px_dma(&ppgtt->pml4);
1280 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
1281 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
1283 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
1284 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
1286 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1287 const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
1289 I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
1290 I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
1293 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
1294 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
1297 I915_WRITE(vgtif_reg(g2v_notify), msg);
1302 static void gen8_free_scratch(struct i915_address_space *vm)
1304 if (!vm->scratch_page.daddr)
1307 if (i915_vm_is_4lvl(vm))
1308 free_pdp(vm, vm->scratch_pdp);
1309 free_pd(vm, vm->scratch_pd);
1310 free_pt(vm, vm->scratch_pt);
1311 cleanup_scratch_page(vm);
1314 static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm,
1315 struct i915_page_directory_pointer *pdp)
1317 const unsigned int pdpes = i915_pdpes_per_pdp(vm);
1320 for (i = 0; i < pdpes; i++) {
1321 if (pdp->page_directory[i] == vm->scratch_pd)
1324 gen8_free_page_tables(vm, pdp->page_directory[i]);
1325 free_pd(vm, pdp->page_directory[i]);
1331 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
1335 for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
1336 if (ppgtt->pml4.pdps[i] == ppgtt->vm.scratch_pdp)
1339 gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, ppgtt->pml4.pdps[i]);
1342 cleanup_px(&ppgtt->vm, &ppgtt->pml4);
1345 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
1347 struct drm_i915_private *dev_priv = vm->i915;
1348 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1350 if (intel_vgpu_active(dev_priv))
1351 gen8_ppgtt_notify_vgt(ppgtt, false);
1353 if (i915_vm_is_4lvl(vm))
1354 gen8_ppgtt_cleanup_4lvl(ppgtt);
1356 gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, &ppgtt->pdp);
1358 gen8_free_scratch(vm);
1361 static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm,
1362 struct i915_page_directory *pd,
1363 u64 start, u64 length)
1365 struct i915_page_table *pt;
1369 gen8_for_each_pde(pt, pd, start, length, pde) {
1370 int count = gen8_pte_count(start, length);
1372 if (pt == vm->scratch_pt) {
1381 if (count < GEN8_PTES || intel_vgpu_active(vm->i915))
1382 gen8_initialize_pt(vm, pt);
1384 gen8_ppgtt_set_pde(vm, pd, pt, pde);
1385 GEM_BUG_ON(pd->used_pdes > I915_PDES);
1388 pt->used_ptes += count;
1393 gen8_ppgtt_clear_pd(vm, pd, from, start - from);
1397 static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm,
1398 struct i915_page_directory_pointer *pdp,
1399 u64 start, u64 length)
1401 struct i915_page_directory *pd;
1406 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1407 if (pd == vm->scratch_pd) {
1416 gen8_initialize_pd(vm, pd);
1417 gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
1418 GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm));
1421 ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
1429 if (!pd->used_pdes) {
1430 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
1431 GEM_BUG_ON(!pdp->used_pdpes);
1436 gen8_ppgtt_clear_pdp(vm, pdp, from, start - from);
1440 static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm,
1441 u64 start, u64 length)
1443 return gen8_ppgtt_alloc_pdp(vm,
1444 &i915_vm_to_ppgtt(vm)->pdp, start, length);
1447 static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
1448 u64 start, u64 length)
1450 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1451 struct i915_pml4 *pml4 = &ppgtt->pml4;
1452 struct i915_page_directory_pointer *pdp;
1457 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1458 if (pml4->pdps[pml4e] == vm->scratch_pdp) {
1459 pdp = alloc_pdp(vm);
1463 gen8_initialize_pdp(vm, pdp);
1464 gen8_ppgtt_set_pml4e(pml4, pdp, pml4e);
1467 ret = gen8_ppgtt_alloc_pdp(vm, pdp, start, length);
1475 if (!pdp->used_pdpes) {
1476 gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
1480 gen8_ppgtt_clear_4lvl(vm, from, start - from);
1484 static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
1486 struct i915_address_space *vm = &ppgtt->vm;
1487 struct i915_page_directory_pointer *pdp = &ppgtt->pdp;
1488 struct i915_page_directory *pd;
1489 u64 start = 0, length = ppgtt->vm.total;
1493 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1498 gen8_initialize_pd(vm, pd);
1499 gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
1503 pdp->used_pdpes++; /* never remove */
1508 gen8_for_each_pdpe(pd, pdp, from, start, pdpe) {
1509 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
1512 pdp->used_pdpes = 0;
1516 static void ppgtt_init(struct drm_i915_private *i915,
1517 struct i915_hw_ppgtt *ppgtt)
1519 kref_init(&ppgtt->ref);
1521 ppgtt->vm.i915 = i915;
1522 ppgtt->vm.dma = &i915->drm.pdev->dev;
1523 ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
1525 i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
1527 ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma;
1528 ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
1529 ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
1530 ppgtt->vm.vma_ops.clear_pages = clear_pages;
1534 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1535 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1536 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1540 static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
1542 struct i915_hw_ppgtt *ppgtt;
1545 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1547 return ERR_PTR(-ENOMEM);
1549 ppgtt_init(i915, ppgtt);
1552 * From bdw, there is hw support for read-only pages in the PPGTT.
1554 * Gen11 has HSDES#:1807136187 unresolved. Disable ro support
1557 ppgtt->vm.has_read_only = INTEL_GEN(i915) != 11;
1559 /* There are only few exceptions for gen >=6. chv and bxt.
1560 * And we are not sure about the latter so play safe for now.
1562 if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
1563 ppgtt->vm.pt_kmap_wc = true;
1565 err = gen8_init_scratch(&ppgtt->vm);
1569 if (i915_vm_is_4lvl(&ppgtt->vm)) {
1570 err = setup_px(&ppgtt->vm, &ppgtt->pml4);
1574 gen8_initialize_pml4(&ppgtt->vm, &ppgtt->pml4);
1576 ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
1577 ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
1578 ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
1580 err = __pdp_init(&ppgtt->vm, &ppgtt->pdp);
1584 if (intel_vgpu_active(i915)) {
1585 err = gen8_preallocate_top_level_pdp(ppgtt);
1587 __pdp_fini(&ppgtt->pdp);
1592 ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
1593 ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
1594 ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
1597 if (intel_vgpu_active(i915))
1598 gen8_ppgtt_notify_vgt(ppgtt, true);
1600 ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
1605 gen8_free_scratch(&ppgtt->vm);
1608 return ERR_PTR(err);
1611 /* Write pde (index) from the page directory @pd to the page table @pt */
1612 static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
1613 const unsigned int pde,
1614 const struct i915_page_table *pt)
1616 /* Caller needs to make sure the write completes if necessary */
1617 iowrite32(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
1618 ppgtt->pd_addr + pde);
1621 static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
1623 struct intel_engine_cs *engine;
1624 u32 ecochk, ecobits;
1625 enum intel_engine_id id;
1627 ecobits = I915_READ(GAC_ECO_BITS);
1628 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1630 ecochk = I915_READ(GAM_ECOCHK);
1631 if (IS_HASWELL(dev_priv)) {
1632 ecochk |= ECOCHK_PPGTT_WB_HSW;
1634 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1635 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1637 I915_WRITE(GAM_ECOCHK, ecochk);
1639 for_each_engine(engine, dev_priv, id) {
1640 /* GFX_MODE is per-ring on gen7+ */
1641 I915_WRITE(RING_MODE_GEN7(engine),
1642 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1646 static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
1648 u32 ecochk, gab_ctl, ecobits;
1650 ecobits = I915_READ(GAC_ECO_BITS);
1651 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1652 ECOBITS_PPGTT_CACHE64B);
1654 gab_ctl = I915_READ(GAB_CTL);
1655 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1657 ecochk = I915_READ(GAM_ECOCHK);
1658 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1660 if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
1661 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1664 /* PPGTT support for Sandybdrige/Gen6 and later */
1665 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1666 u64 start, u64 length)
1668 struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
1669 unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
1670 unsigned int pde = first_entry / GEN6_PTES;
1671 unsigned int pte = first_entry % GEN6_PTES;
1672 unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
1673 const gen6_pte_t scratch_pte = vm->scratch_pte;
1675 while (num_entries) {
1676 struct i915_page_table *pt = ppgtt->base.pd.page_table[pde++];
1677 const unsigned int count = min(num_entries, GEN6_PTES - pte);
1680 GEM_BUG_ON(pt == vm->scratch_pt);
1682 num_entries -= count;
1684 GEM_BUG_ON(count > pt->used_ptes);
1685 pt->used_ptes -= count;
1687 ppgtt->scan_for_unused_pt = true;
1690 * Note that the hw doesn't support removing PDE on the fly
1691 * (they are cached inside the context with no means to
1692 * invalidate the cache), so we can only reset the PTE
1693 * entries back to scratch.
1696 vaddr = kmap_atomic_px(pt);
1697 memset32(vaddr + pte, scratch_pte, count);
1698 kunmap_atomic(vaddr);
1704 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1705 struct i915_vma *vma,
1706 enum i915_cache_level cache_level,
1709 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1710 unsigned first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
1711 unsigned act_pt = first_entry / GEN6_PTES;
1712 unsigned act_pte = first_entry % GEN6_PTES;
1713 const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
1714 struct sgt_dma iter = sgt_dma(vma);
1717 GEM_BUG_ON(ppgtt->pd.page_table[act_pt] == vm->scratch_pt);
1719 vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]);
1721 vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
1723 iter.dma += I915_GTT_PAGE_SIZE;
1724 if (iter.dma == iter.max) {
1725 iter.sg = __sg_next(iter.sg);
1729 iter.dma = sg_dma_address(iter.sg);
1730 iter.max = iter.dma + iter.sg->length;
1733 if (++act_pte == GEN6_PTES) {
1734 kunmap_atomic(vaddr);
1735 vaddr = kmap_atomic_px(ppgtt->pd.page_table[++act_pt]);
1739 kunmap_atomic(vaddr);
1741 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
1744 static int gen6_alloc_va_range(struct i915_address_space *vm,
1745 u64 start, u64 length)
1747 struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
1748 struct i915_page_table *pt;
1753 gen6_for_each_pde(pt, &ppgtt->base.pd, start, length, pde) {
1754 const unsigned int count = gen6_pte_count(start, length);
1756 if (pt == vm->scratch_pt) {
1761 gen6_initialize_pt(vm, pt);
1762 ppgtt->base.pd.page_table[pde] = pt;
1764 if (i915_vma_is_bound(ppgtt->vma,
1765 I915_VMA_GLOBAL_BIND)) {
1766 gen6_write_pde(ppgtt, pde, pt);
1770 GEM_BUG_ON(pt->used_ptes);
1773 pt->used_ptes += count;
1777 mark_tlbs_dirty(&ppgtt->base);
1778 gen6_ggtt_invalidate(ppgtt->base.vm.i915);
1784 gen6_ppgtt_clear_range(vm, from, start - from);
1788 static int gen6_ppgtt_init_scratch(struct gen6_hw_ppgtt *ppgtt)
1790 struct i915_address_space * const vm = &ppgtt->base.vm;
1791 struct i915_page_table *unused;
1795 ret = setup_scratch_page(vm, __GFP_HIGHMEM);
1799 vm->scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
1803 vm->scratch_pt = alloc_pt(vm);
1804 if (IS_ERR(vm->scratch_pt)) {
1805 cleanup_scratch_page(vm);
1806 return PTR_ERR(vm->scratch_pt);
1809 gen6_initialize_pt(vm, vm->scratch_pt);
1810 gen6_for_all_pdes(unused, &ppgtt->base.pd, pde)
1811 ppgtt->base.pd.page_table[pde] = vm->scratch_pt;
1816 static void gen6_ppgtt_free_scratch(struct i915_address_space *vm)
1818 free_pt(vm, vm->scratch_pt);
1819 cleanup_scratch_page(vm);
1822 static void gen6_ppgtt_free_pd(struct gen6_hw_ppgtt *ppgtt)
1824 struct i915_page_table *pt;
1827 gen6_for_all_pdes(pt, &ppgtt->base.pd, pde)
1828 if (pt != ppgtt->base.vm.scratch_pt)
1829 free_pt(&ppgtt->base.vm, pt);
1832 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1834 struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
1836 i915_vma_destroy(ppgtt->vma);
1838 gen6_ppgtt_free_pd(ppgtt);
1839 gen6_ppgtt_free_scratch(vm);
1842 static int pd_vma_set_pages(struct i915_vma *vma)
1844 vma->pages = ERR_PTR(-ENODEV);
1848 static void pd_vma_clear_pages(struct i915_vma *vma)
1850 GEM_BUG_ON(!vma->pages);
1855 static int pd_vma_bind(struct i915_vma *vma,
1856 enum i915_cache_level cache_level,
1859 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm);
1860 struct gen6_hw_ppgtt *ppgtt = vma->private;
1861 u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE;
1862 struct i915_page_table *pt;
1865 ppgtt->base.pd.base.ggtt_offset = ggtt_offset * sizeof(gen6_pte_t);
1866 ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + ggtt_offset;
1868 gen6_for_all_pdes(pt, &ppgtt->base.pd, pde)
1869 gen6_write_pde(ppgtt, pde, pt);
1871 mark_tlbs_dirty(&ppgtt->base);
1872 gen6_ggtt_invalidate(ppgtt->base.vm.i915);
1877 static void pd_vma_unbind(struct i915_vma *vma)
1879 struct gen6_hw_ppgtt *ppgtt = vma->private;
1880 struct i915_page_table * const scratch_pt = ppgtt->base.vm.scratch_pt;
1881 struct i915_page_table *pt;
1884 if (!ppgtt->scan_for_unused_pt)
1887 /* Free all no longer used page tables */
1888 gen6_for_all_pdes(pt, &ppgtt->base.pd, pde) {
1889 if (pt->used_ptes || pt == scratch_pt)
1892 free_pt(&ppgtt->base.vm, pt);
1893 ppgtt->base.pd.page_table[pde] = scratch_pt;
1896 ppgtt->scan_for_unused_pt = false;
1899 static const struct i915_vma_ops pd_vma_ops = {
1900 .set_pages = pd_vma_set_pages,
1901 .clear_pages = pd_vma_clear_pages,
1902 .bind_vma = pd_vma_bind,
1903 .unbind_vma = pd_vma_unbind,
1906 static struct i915_vma *pd_vma_create(struct gen6_hw_ppgtt *ppgtt, int size)
1908 struct drm_i915_private *i915 = ppgtt->base.vm.i915;
1909 struct i915_ggtt *ggtt = &i915->ggtt;
1910 struct i915_vma *vma;
1912 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
1913 GEM_BUG_ON(size > ggtt->vm.total);
1915 vma = i915_vma_alloc();
1917 return ERR_PTR(-ENOMEM);
1919 i915_active_init(i915, &vma->active, NULL);
1920 INIT_ACTIVE_REQUEST(&vma->last_fence);
1922 vma->vm = &ggtt->vm;
1923 vma->ops = &pd_vma_ops;
1924 vma->private = ppgtt;
1927 vma->fence_size = size;
1928 vma->flags = I915_VMA_GGTT;
1929 vma->ggtt_view.type = I915_GGTT_VIEW_ROTATED; /* prevent fencing */
1931 INIT_LIST_HEAD(&vma->obj_link);
1933 mutex_lock(&vma->vm->mutex);
1934 list_add(&vma->vm_link, &vma->vm->unbound_list);
1935 mutex_unlock(&vma->vm->mutex);
1940 int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
1942 struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
1945 GEM_BUG_ON(ppgtt->base.vm.closed);
1948 * Workaround the limited maximum vma->pin_count and the aliasing_ppgtt
1949 * which will be pinned into every active context.
1950 * (When vma->pin_count becomes atomic, I expect we will naturally
1951 * need a larger, unpacked, type and kill this redundancy.)
1953 if (ppgtt->pin_count++)
1957 * PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1958 * allocator works in address space sizes, so it's multiplied by page
1959 * size. We allocate at the top of the GTT to avoid fragmentation.
1961 err = i915_vma_pin(ppgtt->vma,
1963 PIN_GLOBAL | PIN_HIGH);
1970 ppgtt->pin_count = 0;
1974 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
1976 struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
1978 GEM_BUG_ON(!ppgtt->pin_count);
1979 if (--ppgtt->pin_count)
1982 i915_vma_unpin(ppgtt->vma);
1985 void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base)
1987 struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
1989 if (!ppgtt->pin_count)
1992 ppgtt->pin_count = 0;
1993 i915_vma_unpin(ppgtt->vma);
1996 static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
1998 struct i915_ggtt * const ggtt = &i915->ggtt;
1999 struct gen6_hw_ppgtt *ppgtt;
2002 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2004 return ERR_PTR(-ENOMEM);
2006 ppgtt_init(i915, &ppgtt->base);
2008 ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
2009 ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
2010 ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
2011 ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
2013 ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
2015 err = gen6_ppgtt_init_scratch(ppgtt);
2019 ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
2020 if (IS_ERR(ppgtt->vma)) {
2021 err = PTR_ERR(ppgtt->vma);
2025 return &ppgtt->base;
2028 gen6_ppgtt_free_scratch(&ppgtt->base.vm);
2031 return ERR_PTR(err);
2034 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
2036 /* This function is for gtt related workarounds. This function is
2037 * called on driver load and after a GPU reset, so you can place
2038 * workarounds here even if they get overwritten by GPU reset.
2040 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
2041 if (IS_BROADWELL(dev_priv))
2042 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2043 else if (IS_CHERRYVIEW(dev_priv))
2044 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2045 else if (IS_GEN9_LP(dev_priv))
2046 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2047 else if (INTEL_GEN(dev_priv) >= 9)
2048 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2051 * To support 64K PTEs we need to first enable the use of the
2052 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical
2053 * mmio, otherwise the page-walker will simply ignore the IPS bit. This
2054 * shouldn't be needed after GEN10.
2056 * 64K pages were first introduced from BDW+, although technically they
2057 * only *work* from gen9+. For pre-BDW we instead have the option for
2058 * 32K pages, but we don't currently have any support for it in our
2061 if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
2062 INTEL_GEN(dev_priv) <= 10)
2063 I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
2064 I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
2065 GAMW_ECO_ENABLE_64K_IPS_FIELD);
2068 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
2070 gtt_write_workarounds(dev_priv);
2072 if (IS_GEN(dev_priv, 6))
2073 gen6_ppgtt_enable(dev_priv);
2074 else if (IS_GEN(dev_priv, 7))
2075 gen7_ppgtt_enable(dev_priv);
2080 static struct i915_hw_ppgtt *
2081 __hw_ppgtt_create(struct drm_i915_private *i915)
2083 if (INTEL_GEN(i915) < 8)
2084 return gen6_ppgtt_create(i915);
2086 return gen8_ppgtt_create(i915);
2089 struct i915_hw_ppgtt *
2090 i915_ppgtt_create(struct drm_i915_private *i915)
2092 struct i915_hw_ppgtt *ppgtt;
2094 ppgtt = __hw_ppgtt_create(i915);
2098 trace_i915_ppgtt_create(&ppgtt->vm);
2103 static void ppgtt_destroy_vma(struct i915_address_space *vm)
2105 struct list_head *phases[] = {
2112 for (phase = phases; *phase; phase++) {
2113 struct i915_vma *vma, *vn;
2115 list_for_each_entry_safe(vma, vn, *phase, vm_link)
2116 i915_vma_destroy(vma);
2120 void i915_ppgtt_release(struct kref *kref)
2122 struct i915_hw_ppgtt *ppgtt =
2123 container_of(kref, struct i915_hw_ppgtt, ref);
2125 trace_i915_ppgtt_release(&ppgtt->vm);
2127 ppgtt_destroy_vma(&ppgtt->vm);
2129 GEM_BUG_ON(!list_empty(&ppgtt->vm.bound_list));
2130 GEM_BUG_ON(!list_empty(&ppgtt->vm.unbound_list));
2132 ppgtt->vm.cleanup(&ppgtt->vm);
2133 i915_address_space_fini(&ppgtt->vm);
2137 /* Certain Gen5 chipsets require require idling the GPU before
2138 * unmapping anything from the GTT when VT-d is enabled.
2140 static bool needs_idle_maps(struct drm_i915_private *dev_priv)
2142 /* Query intel_iommu to see if we need the workaround. Presumably that
2145 return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
2148 static void gen6_check_faults(struct drm_i915_private *dev_priv)
2150 struct intel_engine_cs *engine;
2151 enum intel_engine_id id;
2154 for_each_engine(engine, dev_priv, id) {
2155 fault = I915_READ(RING_FAULT_REG(engine));
2156 if (fault & RING_FAULT_VALID) {
2157 DRM_DEBUG_DRIVER("Unexpected fault\n"
2159 "\tAddress space: %s\n"
2163 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2164 RING_FAULT_SRCID(fault),
2165 RING_FAULT_FAULT_TYPE(fault));
2170 static void gen8_check_faults(struct drm_i915_private *dev_priv)
2172 u32 fault = I915_READ(GEN8_RING_FAULT_REG);
2174 if (fault & RING_FAULT_VALID) {
2175 u32 fault_data0, fault_data1;
2178 fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
2179 fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
2180 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
2181 ((u64)fault_data0 << 12);
2183 DRM_DEBUG_DRIVER("Unexpected fault\n"
2184 "\tAddr: 0x%08x_%08x\n"
2185 "\tAddress space: %s\n"
2189 upper_32_bits(fault_addr),
2190 lower_32_bits(fault_addr),
2191 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
2192 GEN8_RING_FAULT_ENGINE_ID(fault),
2193 RING_FAULT_SRCID(fault),
2194 RING_FAULT_FAULT_TYPE(fault));
2198 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
2200 /* From GEN8 onwards we only have one 'All Engine Fault Register' */
2201 if (INTEL_GEN(dev_priv) >= 8)
2202 gen8_check_faults(dev_priv);
2203 else if (INTEL_GEN(dev_priv) >= 6)
2204 gen6_check_faults(dev_priv);
2208 i915_clear_error_registers(dev_priv);
2211 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
2213 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2215 /* Don't bother messing with faults pre GEN6 as we have little
2216 * documentation supporting that it's a good idea.
2218 if (INTEL_GEN(dev_priv) < 6)
2221 i915_check_and_clear_faults(dev_priv);
2223 ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
2225 i915_ggtt_invalidate(dev_priv);
2228 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
2229 struct sg_table *pages)
2232 if (dma_map_sg_attrs(&obj->base.dev->pdev->dev,
2233 pages->sgl, pages->nents,
2234 PCI_DMA_BIDIRECTIONAL,
2239 * If the DMA remap fails, one cause can be that we have
2240 * too many objects pinned in a small remapping table,
2241 * such as swiotlb. Incrementally purge all other objects and
2242 * try again - if there are no more pages to remove from
2243 * the DMA remapper, i915_gem_shrink will return 0.
2245 GEM_BUG_ON(obj->mm.pages == pages);
2246 } while (i915_gem_shrink(to_i915(obj->base.dev),
2247 obj->base.size >> PAGE_SHIFT, NULL,
2249 I915_SHRINK_UNBOUND));
2254 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2259 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
2262 enum i915_cache_level level,
2265 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2266 gen8_pte_t __iomem *pte =
2267 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
2269 gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
2271 ggtt->invalidate(vm->i915);
2274 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2275 struct i915_vma *vma,
2276 enum i915_cache_level level,
2279 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2280 struct sgt_iter sgt_iter;
2281 gen8_pte_t __iomem *gtt_entries;
2282 const gen8_pte_t pte_encode = gen8_pte_encode(0, level, 0);
2286 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
2287 * not to allow the user to override access to a read only page.
2290 gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
2291 gtt_entries += vma->node.start / I915_GTT_PAGE_SIZE;
2292 for_each_sgt_dma(addr, sgt_iter, vma->pages)
2293 gen8_set_pte(gtt_entries++, pte_encode | addr);
2296 * We want to flush the TLBs only after we're certain all the PTE
2297 * updates have finished.
2299 ggtt->invalidate(vm->i915);
2302 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
2305 enum i915_cache_level level,
2308 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2309 gen6_pte_t __iomem *pte =
2310 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
2312 iowrite32(vm->pte_encode(addr, level, flags), pte);
2314 ggtt->invalidate(vm->i915);
2318 * Binds an object into the global gtt with the specified cache level. The object
2319 * will be accessible to the GPU via commands whose operands reference offsets
2320 * within the global GTT as well as accessible by the GPU through the GMADR
2321 * mapped BAR (dev_priv->mm.gtt->gtt).
2323 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2324 struct i915_vma *vma,
2325 enum i915_cache_level level,
2328 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2329 gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm;
2330 unsigned int i = vma->node.start / I915_GTT_PAGE_SIZE;
2331 struct sgt_iter iter;
2333 for_each_sgt_dma(addr, iter, vma->pages)
2334 iowrite32(vm->pte_encode(addr, level, flags), &entries[i++]);
2337 * We want to flush the TLBs only after we're certain all the PTE
2338 * updates have finished.
2340 ggtt->invalidate(vm->i915);
2343 static void nop_clear_range(struct i915_address_space *vm,
2344 u64 start, u64 length)
2348 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2349 u64 start, u64 length)
2351 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2352 unsigned first_entry = start / I915_GTT_PAGE_SIZE;
2353 unsigned num_entries = length / I915_GTT_PAGE_SIZE;
2354 const gen8_pte_t scratch_pte = vm->scratch_pte;
2355 gen8_pte_t __iomem *gtt_base =
2356 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2357 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2360 if (WARN(num_entries > max_entries,
2361 "First entry = %d; Num entries = %d (max=%d)\n",
2362 first_entry, num_entries, max_entries))
2363 num_entries = max_entries;
2365 for (i = 0; i < num_entries; i++)
2366 gen8_set_pte(>t_base[i], scratch_pte);
2369 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
2371 struct drm_i915_private *dev_priv = vm->i915;
2374 * Make sure the internal GAM fifo has been cleared of all GTT
2375 * writes before exiting stop_machine(). This guarantees that
2376 * any aperture accesses waiting to start in another process
2377 * cannot back up behind the GTT writes causing a hang.
2378 * The register can be any arbitrary GAM register.
2380 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2383 struct insert_page {
2384 struct i915_address_space *vm;
2387 enum i915_cache_level level;
2390 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
2392 struct insert_page *arg = _arg;
2394 gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
2395 bxt_vtd_ggtt_wa(arg->vm);
2400 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
2403 enum i915_cache_level level,
2406 struct insert_page arg = { vm, addr, offset, level };
2408 stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
2411 struct insert_entries {
2412 struct i915_address_space *vm;
2413 struct i915_vma *vma;
2414 enum i915_cache_level level;
2418 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
2420 struct insert_entries *arg = _arg;
2422 gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, arg->flags);
2423 bxt_vtd_ggtt_wa(arg->vm);
2428 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2429 struct i915_vma *vma,
2430 enum i915_cache_level level,
2433 struct insert_entries arg = { vm, vma, level, flags };
2435 stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
2438 struct clear_range {
2439 struct i915_address_space *vm;
2444 static int bxt_vtd_ggtt_clear_range__cb(void *_arg)
2446 struct clear_range *arg = _arg;
2448 gen8_ggtt_clear_range(arg->vm, arg->start, arg->length);
2449 bxt_vtd_ggtt_wa(arg->vm);
2454 static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm,
2458 struct clear_range arg = { vm, start, length };
2460 stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL);
2463 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2464 u64 start, u64 length)
2466 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2467 unsigned first_entry = start / I915_GTT_PAGE_SIZE;
2468 unsigned num_entries = length / I915_GTT_PAGE_SIZE;
2469 gen6_pte_t scratch_pte, __iomem *gtt_base =
2470 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2471 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2474 if (WARN(num_entries > max_entries,
2475 "First entry = %d; Num entries = %d (max=%d)\n",
2476 first_entry, num_entries, max_entries))
2477 num_entries = max_entries;
2479 scratch_pte = vm->scratch_pte;
2481 for (i = 0; i < num_entries; i++)
2482 iowrite32(scratch_pte, >t_base[i]);
2485 static void i915_ggtt_insert_page(struct i915_address_space *vm,
2488 enum i915_cache_level cache_level,
2491 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2492 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2494 intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
2497 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2498 struct i915_vma *vma,
2499 enum i915_cache_level cache_level,
2502 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2503 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2505 intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
2509 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2510 u64 start, u64 length)
2512 intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
2515 static int ggtt_bind_vma(struct i915_vma *vma,
2516 enum i915_cache_level cache_level,
2519 struct drm_i915_private *i915 = vma->vm->i915;
2520 struct drm_i915_gem_object *obj = vma->obj;
2521 intel_wakeref_t wakeref;
2524 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
2526 if (i915_gem_object_is_readonly(obj))
2527 pte_flags |= PTE_READ_ONLY;
2529 with_intel_runtime_pm(i915, wakeref)
2530 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
2532 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
2535 * Without aliasing PPGTT there's no difference between
2536 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2537 * upgrade to both bound if we bind either to avoid double-binding.
2539 vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
2544 static void ggtt_unbind_vma(struct i915_vma *vma)
2546 struct drm_i915_private *i915 = vma->vm->i915;
2547 intel_wakeref_t wakeref;
2549 with_intel_runtime_pm(i915, wakeref)
2550 vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
2553 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2554 enum i915_cache_level cache_level,
2557 struct drm_i915_private *i915 = vma->vm->i915;
2561 /* Currently applicable only to VLV */
2563 if (i915_gem_object_is_readonly(vma->obj))
2564 pte_flags |= PTE_READ_ONLY;
2566 if (flags & I915_VMA_LOCAL_BIND) {
2567 struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
2569 if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
2570 ret = appgtt->vm.allocate_va_range(&appgtt->vm,
2577 appgtt->vm.insert_entries(&appgtt->vm, vma, cache_level,
2581 if (flags & I915_VMA_GLOBAL_BIND) {
2582 intel_wakeref_t wakeref;
2584 with_intel_runtime_pm(i915, wakeref) {
2585 vma->vm->insert_entries(vma->vm, vma,
2586 cache_level, pte_flags);
2593 static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
2595 struct drm_i915_private *i915 = vma->vm->i915;
2597 if (vma->flags & I915_VMA_GLOBAL_BIND) {
2598 struct i915_address_space *vm = vma->vm;
2599 intel_wakeref_t wakeref;
2601 with_intel_runtime_pm(i915, wakeref)
2602 vm->clear_range(vm, vma->node.start, vma->size);
2605 if (vma->flags & I915_VMA_LOCAL_BIND) {
2606 struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->vm;
2608 vm->clear_range(vm, vma->node.start, vma->size);
2612 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
2613 struct sg_table *pages)
2615 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2616 struct device *kdev = &dev_priv->drm.pdev->dev;
2617 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2619 if (unlikely(ggtt->do_idle_maps)) {
2620 if (i915_gem_wait_for_idle(dev_priv, 0, MAX_SCHEDULE_TIMEOUT)) {
2621 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2622 /* Wait a bit, in hopes it avoids the hang */
2627 dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL);
2630 static int ggtt_set_pages(struct i915_vma *vma)
2634 GEM_BUG_ON(vma->pages);
2636 ret = i915_get_ggtt_vma_pages(vma);
2640 vma->page_sizes = vma->obj->mm.page_sizes;
2645 static void i915_gtt_color_adjust(const struct drm_mm_node *node,
2646 unsigned long color,
2650 if (node->allocated && node->color != color)
2651 *start += I915_GTT_PAGE_SIZE;
2653 /* Also leave a space between the unallocated reserved node after the
2654 * GTT and any objects within the GTT, i.e. we use the color adjustment
2655 * to insert a guard page to prevent prefetches crossing over the
2658 node = list_next_entry(node, node_list);
2659 if (node->color != color)
2660 *end -= I915_GTT_PAGE_SIZE;
2663 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
2665 struct i915_ggtt *ggtt = &i915->ggtt;
2666 struct i915_hw_ppgtt *ppgtt;
2669 ppgtt = i915_ppgtt_create(i915);
2671 return PTR_ERR(ppgtt);
2673 if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
2679 * Note we only pre-allocate as far as the end of the global
2680 * GTT. On 48b / 4-level page-tables, the difference is very,
2681 * very significant! We have to preallocate as GVT/vgpu does
2682 * not like the page directory disappearing.
2684 err = ppgtt->vm.allocate_va_range(&ppgtt->vm, 0, ggtt->vm.total);
2688 i915->mm.aliasing_ppgtt = ppgtt;
2690 GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
2691 ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
2693 GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
2694 ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
2699 i915_ppgtt_put(ppgtt);
2703 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
2705 struct i915_ggtt *ggtt = &i915->ggtt;
2706 struct i915_hw_ppgtt *ppgtt;
2708 ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
2712 i915_ppgtt_put(ppgtt);
2714 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
2715 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
2718 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
2720 /* Let GEM Manage all of the aperture.
2722 * However, leave one page at the end still bound to the scratch page.
2723 * There are a number of places where the hardware apparently prefetches
2724 * past the end of the object, and we've seen multiple hangs with the
2725 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2726 * aperture. One page should be enough to keep any prefetching inside
2729 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2730 unsigned long hole_start, hole_end;
2731 struct drm_mm_node *entry;
2735 * GuC requires all resources that we're sharing with it to be placed in
2736 * non-WOPCM memory. If GuC is not present or not in use we still need a
2737 * small bias as ring wraparound at offset 0 sometimes hangs. No idea
2740 ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
2741 intel_guc_reserved_gtt_size(&dev_priv->guc));
2743 ret = intel_vgt_balloon(dev_priv);
2747 /* Reserve a mappable slot for our lockless error capture */
2748 ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
2749 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
2750 0, ggtt->mappable_end,
2755 /* Clear any non-preallocated blocks */
2756 drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
2757 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2758 hole_start, hole_end);
2759 ggtt->vm.clear_range(&ggtt->vm, hole_start,
2760 hole_end - hole_start);
2763 /* And finally clear the reserved guard page */
2764 ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
2766 if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
2767 ret = i915_gem_init_aliasing_ppgtt(dev_priv);
2775 drm_mm_remove_node(&ggtt->error_capture);
2780 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2781 * @dev_priv: i915 device
2783 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
2785 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2786 struct i915_vma *vma, *vn;
2787 struct pagevec *pvec;
2789 ggtt->vm.closed = true;
2791 mutex_lock(&dev_priv->drm.struct_mutex);
2792 i915_gem_fini_aliasing_ppgtt(dev_priv);
2794 list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
2795 WARN_ON(i915_vma_unbind(vma));
2797 if (drm_mm_node_allocated(&ggtt->error_capture))
2798 drm_mm_remove_node(&ggtt->error_capture);
2800 if (drm_mm_initialized(&ggtt->vm.mm)) {
2801 intel_vgt_deballoon(dev_priv);
2802 i915_address_space_fini(&ggtt->vm);
2805 ggtt->vm.cleanup(&ggtt->vm);
2807 pvec = &dev_priv->mm.wc_stash.pvec;
2809 set_pages_array_wb(pvec->pages, pvec->nr);
2810 __pagevec_release(pvec);
2813 mutex_unlock(&dev_priv->drm.struct_mutex);
2815 arch_phys_wc_del(ggtt->mtrr);
2816 io_mapping_fini(&ggtt->iomap);
2818 i915_gem_cleanup_stolen(dev_priv);
2821 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2823 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2824 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2825 return snb_gmch_ctl << 20;
2828 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2830 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2831 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2833 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2835 #ifdef CONFIG_X86_32
2836 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
2837 if (bdw_gmch_ctl > 4)
2841 return bdw_gmch_ctl << 20;
2844 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2846 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2847 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2850 return 1 << (20 + gmch_ctrl);
2855 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
2857 struct drm_i915_private *dev_priv = ggtt->vm.i915;
2858 struct pci_dev *pdev = dev_priv->drm.pdev;
2859 phys_addr_t phys_addr;
2862 /* For Modern GENs the PTEs and register space are split in the BAR */
2863 phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
2866 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
2867 * will be dropped. For WC mappings in general we have 64 byte burst
2868 * writes when the WC buffer is flushed, so we can't use it, but have to
2869 * resort to an uncached mapping. The WC issue is easily caught by the
2870 * readback check when writing GTT PTE entries.
2872 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
2873 ggtt->gsm = ioremap_nocache(phys_addr, size);
2875 ggtt->gsm = ioremap_wc(phys_addr, size);
2877 DRM_ERROR("Failed to map the ggtt page table\n");
2881 ret = setup_scratch_page(&ggtt->vm, GFP_DMA32);
2883 DRM_ERROR("Scratch setup failed\n");
2884 /* iounmap will also get called at remove, but meh */
2889 ggtt->vm.scratch_pte =
2890 ggtt->vm.pte_encode(ggtt->vm.scratch_page.daddr,
2891 I915_CACHE_NONE, 0);
2896 static struct intel_ppat_entry *
2897 __alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
2899 struct intel_ppat_entry *entry = &ppat->entries[index];
2901 GEM_BUG_ON(index >= ppat->max_entries);
2902 GEM_BUG_ON(test_bit(index, ppat->used));
2905 entry->value = value;
2906 kref_init(&entry->ref);
2907 set_bit(index, ppat->used);
2908 set_bit(index, ppat->dirty);
2913 static void __free_ppat_entry(struct intel_ppat_entry *entry)
2915 struct intel_ppat *ppat = entry->ppat;
2916 unsigned int index = entry - ppat->entries;
2918 GEM_BUG_ON(index >= ppat->max_entries);
2919 GEM_BUG_ON(!test_bit(index, ppat->used));
2921 entry->value = ppat->clear_value;
2922 clear_bit(index, ppat->used);
2923 set_bit(index, ppat->dirty);
2927 * intel_ppat_get - get a usable PPAT entry
2928 * @i915: i915 device instance
2929 * @value: the PPAT value required by the caller
2931 * The function tries to search if there is an existing PPAT entry which
2932 * matches with the required value. If perfectly matched, the existing PPAT
2933 * entry will be used. If only partially matched, it will try to check if
2934 * there is any available PPAT index. If yes, it will allocate a new PPAT
2935 * index for the required entry and update the HW. If not, the partially
2936 * matched entry will be used.
2938 const struct intel_ppat_entry *
2939 intel_ppat_get(struct drm_i915_private *i915, u8 value)
2941 struct intel_ppat *ppat = &i915->ppat;
2942 struct intel_ppat_entry *entry = NULL;
2943 unsigned int scanned, best_score;
2946 GEM_BUG_ON(!ppat->max_entries);
2948 scanned = best_score = 0;
2949 for_each_set_bit(i, ppat->used, ppat->max_entries) {
2952 score = ppat->match(ppat->entries[i].value, value);
2953 if (score > best_score) {
2954 entry = &ppat->entries[i];
2955 if (score == INTEL_PPAT_PERFECT_MATCH) {
2956 kref_get(&entry->ref);
2964 if (scanned == ppat->max_entries) {
2966 return ERR_PTR(-ENOSPC);
2968 kref_get(&entry->ref);
2972 i = find_first_zero_bit(ppat->used, ppat->max_entries);
2973 entry = __alloc_ppat_entry(ppat, i, value);
2974 ppat->update_hw(i915);
2978 static void release_ppat(struct kref *kref)
2980 struct intel_ppat_entry *entry =
2981 container_of(kref, struct intel_ppat_entry, ref);
2982 struct drm_i915_private *i915 = entry->ppat->i915;
2984 __free_ppat_entry(entry);
2985 entry->ppat->update_hw(i915);
2989 * intel_ppat_put - put back the PPAT entry got from intel_ppat_get()
2990 * @entry: an intel PPAT entry
2992 * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the
2993 * entry is dynamically allocated, its reference count will be decreased. Once
2994 * the reference count becomes into zero, the PPAT index becomes free again.
2996 void intel_ppat_put(const struct intel_ppat_entry *entry)
2998 struct intel_ppat *ppat = entry->ppat;
2999 unsigned int index = entry - ppat->entries;
3001 GEM_BUG_ON(!ppat->max_entries);
3003 kref_put(&ppat->entries[index].ref, release_ppat);
3006 static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv)
3008 struct intel_ppat *ppat = &dev_priv->ppat;
3011 for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
3012 I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
3013 clear_bit(i, ppat->dirty);
3017 static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv)
3019 struct intel_ppat *ppat = &dev_priv->ppat;
3023 for (i = 0; i < ppat->max_entries; i++)
3024 pat |= GEN8_PPAT(i, ppat->entries[i].value);
3026 bitmap_clear(ppat->dirty, 0, ppat->max_entries);
3028 I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
3029 I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
3032 static unsigned int bdw_private_pat_match(u8 src, u8 dst)
3034 unsigned int score = 0;
3041 /* Cache attribute has to be matched. */
3042 if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
3047 if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst))
3050 if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst))
3053 if (score == (AGE_MATCH | TC_MATCH | CA_MATCH))
3054 return INTEL_PPAT_PERFECT_MATCH;
3059 static unsigned int chv_private_pat_match(u8 src, u8 dst)
3061 return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ?
3062 INTEL_PPAT_PERFECT_MATCH : 0;
3065 static void cnl_setup_private_ppat(struct intel_ppat *ppat)
3067 ppat->max_entries = 8;
3068 ppat->update_hw = cnl_private_pat_update_hw;
3069 ppat->match = bdw_private_pat_match;
3070 ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
3072 __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
3073 __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
3074 __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
3075 __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
3076 __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
3077 __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
3078 __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
3079 __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
3082 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
3083 * bits. When using advanced contexts each context stores its own PAT, but
3084 * writing this data shouldn't be harmful even in those cases. */
3085 static void bdw_setup_private_ppat(struct intel_ppat *ppat)
3087 ppat->max_entries = 8;
3088 ppat->update_hw = bdw_private_pat_update_hw;
3089 ppat->match = bdw_private_pat_match;
3090 ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
3092 if (!HAS_PPGTT(ppat->i915)) {
3093 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
3094 * so RTL will always use the value corresponding to
3096 * So let's disable cache for GGTT to avoid screen corruptions.
3097 * MOCS still can be used though.
3098 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
3099 * before this patch, i.e. the same uncached + snooping access
3100 * like on gen6/7 seems to be in effect.
3101 * - So this just fixes blitter/render access. Again it looks
3102 * like it's not just uncached access, but uncached + snooping.
3103 * So we can still hold onto all our assumptions wrt cpu
3104 * clflushing on LLC machines.
3106 __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
3110 __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); /* for normal objects, no eLLC */
3111 __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); /* for something pointing to ptes? */
3112 __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); /* for scanout with eLLC */
3113 __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); /* Uncached objects, mostly for scanout */
3114 __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
3115 __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
3116 __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
3117 __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
3120 static void chv_setup_private_ppat(struct intel_ppat *ppat)
3122 ppat->max_entries = 8;
3123 ppat->update_hw = bdw_private_pat_update_hw;
3124 ppat->match = chv_private_pat_match;
3125 ppat->clear_value = CHV_PPAT_SNOOP;
3128 * Map WB on BDW to snooped on CHV.
3130 * Only the snoop bit has meaning for CHV, the rest is
3133 * The hardware will never snoop for certain types of accesses:
3134 * - CPU GTT (GMADR->GGTT->no snoop->memory)
3135 * - PPGTT page tables
3136 * - some other special cycles
3138 * As with BDW, we also need to consider the following for GT accesses:
3139 * "For GGTT, there is NO pat_sel[2:0] from the entry,
3140 * so RTL will always use the value corresponding to
3142 * Which means we must set the snoop bit in PAT entry 0
3143 * in order to keep the global status page working.
3146 __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
3147 __alloc_ppat_entry(ppat, 1, 0);
3148 __alloc_ppat_entry(ppat, 2, 0);
3149 __alloc_ppat_entry(ppat, 3, 0);
3150 __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
3151 __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
3152 __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
3153 __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
3156 static void gen6_gmch_remove(struct i915_address_space *vm)
3158 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
3161 cleanup_scratch_page(vm);
3164 static void setup_private_pat(struct drm_i915_private *dev_priv)
3166 struct intel_ppat *ppat = &dev_priv->ppat;
3169 ppat->i915 = dev_priv;
3171 if (INTEL_GEN(dev_priv) >= 10)
3172 cnl_setup_private_ppat(ppat);
3173 else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
3174 chv_setup_private_ppat(ppat);
3176 bdw_setup_private_ppat(ppat);
3178 GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES);
3180 for_each_clear_bit(i, ppat->used, ppat->max_entries) {
3181 ppat->entries[i].value = ppat->clear_value;
3182 ppat->entries[i].ppat = ppat;
3183 set_bit(i, ppat->dirty);
3186 ppat->update_hw(dev_priv);
3189 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
3191 struct drm_i915_private *dev_priv = ggtt->vm.i915;
3192 struct pci_dev *pdev = dev_priv->drm.pdev;
3197 /* TODO: We're not aware of mappable constraints on gen8 yet */
3199 (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
3200 pci_resource_len(pdev, 2));
3201 ggtt->mappable_end = resource_size(&ggtt->gmadr);
3203 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
3205 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
3207 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
3209 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3210 if (IS_CHERRYVIEW(dev_priv))
3211 size = chv_get_total_gtt_size(snb_gmch_ctl);
3213 size = gen8_get_total_gtt_size(snb_gmch_ctl);
3215 ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
3216 ggtt->vm.cleanup = gen6_gmch_remove;
3217 ggtt->vm.insert_page = gen8_ggtt_insert_page;
3218 ggtt->vm.clear_range = nop_clear_range;
3219 if (intel_scanout_needs_vtd_wa(dev_priv))
3220 ggtt->vm.clear_range = gen8_ggtt_clear_range;
3222 ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
3224 /* Serialize GTT updates with aperture access on BXT if VT-d is on. */
3225 if (intel_ggtt_update_needs_vtd_wa(dev_priv) ||
3226 IS_CHERRYVIEW(dev_priv) /* fails with concurrent use/update */) {
3227 ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
3228 ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL;
3229 if (ggtt->vm.clear_range != nop_clear_range)
3230 ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;
3232 /* Prevent recursively calling stop_machine() and deadlocks. */
3233 dev_info(dev_priv->drm.dev,
3234 "Disabling error capture for VT-d workaround\n");
3235 i915_disable_error_state(dev_priv, -ENODEV);
3238 ggtt->invalidate = gen6_ggtt_invalidate;
3240 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
3241 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
3242 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
3243 ggtt->vm.vma_ops.clear_pages = clear_pages;
3245 ggtt->vm.pte_encode = gen8_pte_encode;
3247 setup_private_pat(dev_priv);
3249 return ggtt_probe_common(ggtt, size);
3252 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
3254 struct drm_i915_private *dev_priv = ggtt->vm.i915;
3255 struct pci_dev *pdev = dev_priv->drm.pdev;
3261 (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
3262 pci_resource_len(pdev, 2));
3263 ggtt->mappable_end = resource_size(&ggtt->gmadr);
3265 /* 64/512MB is the current min/max we actually know of, but this is just
3266 * a coarse sanity check.
3268 if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
3269 DRM_ERROR("Unknown GMADR size (%pa)\n", &ggtt->mappable_end);
3273 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
3275 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
3277 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
3278 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3280 size = gen6_get_total_gtt_size(snb_gmch_ctl);
3281 ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
3283 ggtt->vm.clear_range = gen6_ggtt_clear_range;
3284 ggtt->vm.insert_page = gen6_ggtt_insert_page;
3285 ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
3286 ggtt->vm.cleanup = gen6_gmch_remove;
3288 ggtt->invalidate = gen6_ggtt_invalidate;
3290 if (HAS_EDRAM(dev_priv))
3291 ggtt->vm.pte_encode = iris_pte_encode;
3292 else if (IS_HASWELL(dev_priv))
3293 ggtt->vm.pte_encode = hsw_pte_encode;
3294 else if (IS_VALLEYVIEW(dev_priv))
3295 ggtt->vm.pte_encode = byt_pte_encode;
3296 else if (INTEL_GEN(dev_priv) >= 7)
3297 ggtt->vm.pte_encode = ivb_pte_encode;
3299 ggtt->vm.pte_encode = snb_pte_encode;
3301 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
3302 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
3303 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
3304 ggtt->vm.vma_ops.clear_pages = clear_pages;
3306 return ggtt_probe_common(ggtt, size);
3309 static void i915_gmch_remove(struct i915_address_space *vm)
3311 intel_gmch_remove();
3314 static int i915_gmch_probe(struct i915_ggtt *ggtt)
3316 struct drm_i915_private *dev_priv = ggtt->vm.i915;
3317 phys_addr_t gmadr_base;
3320 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL);
3322 DRM_ERROR("failed to set up gmch\n");
3326 intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
3329 (struct resource) DEFINE_RES_MEM(gmadr_base,
3330 ggtt->mappable_end);
3332 ggtt->do_idle_maps = needs_idle_maps(dev_priv);
3333 ggtt->vm.insert_page = i915_ggtt_insert_page;
3334 ggtt->vm.insert_entries = i915_ggtt_insert_entries;
3335 ggtt->vm.clear_range = i915_ggtt_clear_range;
3336 ggtt->vm.cleanup = i915_gmch_remove;
3338 ggtt->invalidate = gmch_ggtt_invalidate;
3340 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
3341 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
3342 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
3343 ggtt->vm.vma_ops.clear_pages = clear_pages;
3345 if (unlikely(ggtt->do_idle_maps))
3346 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3352 * i915_ggtt_probe_hw - Probe GGTT hardware location
3353 * @dev_priv: i915 device
3355 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
3357 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3360 ggtt->vm.i915 = dev_priv;
3361 ggtt->vm.dma = &dev_priv->drm.pdev->dev;
3363 if (INTEL_GEN(dev_priv) <= 5)
3364 ret = i915_gmch_probe(ggtt);
3365 else if (INTEL_GEN(dev_priv) < 8)
3366 ret = gen6_gmch_probe(ggtt);
3368 ret = gen8_gmch_probe(ggtt);
3372 /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
3373 * This is easier than doing range restriction on the fly, as we
3374 * currently don't have any bits spare to pass in this upper
3377 if (USES_GUC(dev_priv)) {
3378 ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP);
3379 ggtt->mappable_end =
3380 min_t(u64, ggtt->mappable_end, ggtt->vm.total);
3383 if ((ggtt->vm.total - 1) >> 32) {
3384 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3385 " of address space! Found %lldM!\n",
3386 ggtt->vm.total >> 20);
3387 ggtt->vm.total = 1ULL << 32;
3388 ggtt->mappable_end =
3389 min_t(u64, ggtt->mappable_end, ggtt->vm.total);
3392 if (ggtt->mappable_end > ggtt->vm.total) {
3393 DRM_ERROR("mappable aperture extends past end of GGTT,"
3394 " aperture=%pa, total=%llx\n",
3395 &ggtt->mappable_end, ggtt->vm.total);
3396 ggtt->mappable_end = ggtt->vm.total;
3399 /* GMADR is the PCI mmio aperture into the global GTT. */
3400 DRM_DEBUG_DRIVER("GGTT size = %lluM\n", ggtt->vm.total >> 20);
3401 DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
3402 DRM_DEBUG_DRIVER("DSM size = %lluM\n",
3403 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
3404 if (intel_vtd_active())
3405 DRM_INFO("VT-d active for gfx access\n");
3411 * i915_ggtt_init_hw - Initialize GGTT hardware
3412 * @dev_priv: i915 device
3414 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
3416 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3419 stash_init(&dev_priv->mm.wc_stash);
3421 /* Note that we use page colouring to enforce a guard page at the
3422 * end of the address space. This is required as the CS may prefetch
3423 * beyond the end of the batch buffer, across the page boundary,
3424 * and beyond the end of the GTT if we do not provide a guard.
3426 mutex_lock(&dev_priv->drm.struct_mutex);
3427 i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
3429 ggtt->vm.is_ggtt = true;
3431 /* Only VLV supports read-only GGTT mappings */
3432 ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
3434 if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
3435 ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
3436 mutex_unlock(&dev_priv->drm.struct_mutex);
3438 if (!io_mapping_init_wc(&dev_priv->ggtt.iomap,
3439 dev_priv->ggtt.gmadr.start,
3440 dev_priv->ggtt.mappable_end)) {
3442 goto out_gtt_cleanup;
3445 ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
3448 * Initialise stolen early so that we may reserve preallocated
3449 * objects for the BIOS to KMS transition.
3451 ret = i915_gem_init_stolen(dev_priv);
3453 goto out_gtt_cleanup;
3458 ggtt->vm.cleanup(&ggtt->vm);
3462 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
3464 if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
3470 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
3472 GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
3474 i915->ggtt.invalidate = guc_ggtt_invalidate;
3476 i915_ggtt_invalidate(i915);
3479 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
3481 /* XXX Temporary pardon for error unload */
3482 if (i915->ggtt.invalidate == gen6_ggtt_invalidate)
3485 /* We should only be called after i915_ggtt_enable_guc() */
3486 GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
3488 i915->ggtt.invalidate = gen6_ggtt_invalidate;
3490 i915_ggtt_invalidate(i915);
3493 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
3495 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3496 struct i915_vma *vma, *vn;
3498 i915_check_and_clear_faults(dev_priv);
3500 mutex_lock(&ggtt->vm.mutex);
3502 /* First fill our portion of the GTT with scratch pages */
3503 ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
3504 ggtt->vm.closed = true; /* skip rewriting PTE on VMA unbind */
3506 /* clflush objects bound into the GGTT and rebind them. */
3507 list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link) {
3508 struct drm_i915_gem_object *obj = vma->obj;
3510 if (!(vma->flags & I915_VMA_GLOBAL_BIND))
3513 mutex_unlock(&ggtt->vm.mutex);
3515 if (!i915_vma_unbind(vma))
3518 WARN_ON(i915_vma_bind(vma,
3519 obj ? obj->cache_level : 0,
3522 WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
3525 mutex_lock(&ggtt->vm.mutex);
3528 ggtt->vm.closed = false;
3529 i915_ggtt_invalidate(dev_priv);
3531 mutex_unlock(&ggtt->vm.mutex);
3533 if (INTEL_GEN(dev_priv) >= 8) {
3534 struct intel_ppat *ppat = &dev_priv->ppat;
3536 bitmap_set(ppat->dirty, 0, ppat->max_entries);
3537 dev_priv->ppat.update_hw(dev_priv);
3542 static struct scatterlist *
3543 rotate_pages(struct drm_i915_gem_object *obj, unsigned int offset,
3544 unsigned int width, unsigned int height,
3545 unsigned int stride,
3546 struct sg_table *st, struct scatterlist *sg)
3548 unsigned int column, row;
3549 unsigned int src_idx;
3551 for (column = 0; column < width; column++) {
3552 src_idx = stride * (height - 1) + column + offset;
3553 for (row = 0; row < height; row++) {
3555 /* We don't need the pages, but need to initialize
3556 * the entries so the sg list can be happily traversed.
3557 * The only thing we need are DMA addresses.
3559 sg_set_page(sg, NULL, I915_GTT_PAGE_SIZE, 0);
3560 sg_dma_address(sg) =
3561 i915_gem_object_get_dma_address(obj, src_idx);
3562 sg_dma_len(sg) = I915_GTT_PAGE_SIZE;
3571 static noinline struct sg_table *
3572 intel_rotate_pages(struct intel_rotation_info *rot_info,
3573 struct drm_i915_gem_object *obj)
3575 unsigned int size = intel_rotation_info_size(rot_info);
3576 struct sg_table *st;
3577 struct scatterlist *sg;
3581 /* Allocate target SG list. */
3582 st = kmalloc(sizeof(*st), GFP_KERNEL);
3586 ret = sg_alloc_table(st, size, GFP_KERNEL);
3593 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
3594 sg = rotate_pages(obj, rot_info->plane[i].offset,
3595 rot_info->plane[i].width, rot_info->plane[i].height,
3596 rot_info->plane[i].stride, st, sg);
3605 DRM_DEBUG_DRIVER("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3606 obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
3608 return ERR_PTR(ret);
3611 static noinline struct sg_table *
3612 intel_partial_pages(const struct i915_ggtt_view *view,
3613 struct drm_i915_gem_object *obj)
3615 struct sg_table *st;
3616 struct scatterlist *sg, *iter;
3617 unsigned int count = view->partial.size;
3618 unsigned int offset;
3621 st = kmalloc(sizeof(*st), GFP_KERNEL);
3625 ret = sg_alloc_table(st, count, GFP_KERNEL);
3629 iter = i915_gem_object_get_sg(obj, view->partial.offset, &offset);
3637 len = min(iter->length - (offset << PAGE_SHIFT),
3638 count << PAGE_SHIFT);
3639 sg_set_page(sg, NULL, len, 0);
3640 sg_dma_address(sg) =
3641 sg_dma_address(iter) + (offset << PAGE_SHIFT);
3642 sg_dma_len(sg) = len;
3645 count -= len >> PAGE_SHIFT;
3648 i915_sg_trim(st); /* Drop any unused tail entries. */
3654 iter = __sg_next(iter);
3661 return ERR_PTR(ret);
3665 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3669 /* The vma->pages are only valid within the lifespan of the borrowed
3670 * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
3671 * must be the vma->pages. A simple rule is that vma->pages must only
3672 * be accessed when the obj->mm.pages are pinned.
3674 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj));
3676 switch (vma->ggtt_view.type) {
3678 GEM_BUG_ON(vma->ggtt_view.type);
3680 case I915_GGTT_VIEW_NORMAL:
3681 vma->pages = vma->obj->mm.pages;
3684 case I915_GGTT_VIEW_ROTATED:
3686 intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
3689 case I915_GGTT_VIEW_PARTIAL:
3690 vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
3695 if (IS_ERR(vma->pages)) {
3696 ret = PTR_ERR(vma->pages);
3698 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3699 vma->ggtt_view.type, ret);
3705 * i915_gem_gtt_reserve - reserve a node in an address_space (GTT)
3706 * @vm: the &struct i915_address_space
3707 * @node: the &struct drm_mm_node (typically i915_vma.mode)
3708 * @size: how much space to allocate inside the GTT,
3709 * must be #I915_GTT_PAGE_SIZE aligned
3710 * @offset: where to insert inside the GTT,
3711 * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node
3712 * (@offset + @size) must fit within the address space
3713 * @color: color to apply to node, if this node is not from a VMA,
3714 * color must be #I915_COLOR_UNEVICTABLE
3715 * @flags: control search and eviction behaviour
3717 * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside
3718 * the address space (using @size and @color). If the @node does not fit, it
3719 * tries to evict any overlapping nodes from the GTT, including any
3720 * neighbouring nodes if the colors do not match (to ensure guard pages between
3721 * differing domains). See i915_gem_evict_for_node() for the gory details
3722 * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on
3723 * evicting active overlapping objects, and any overlapping node that is pinned
3724 * or marked as unevictable will also result in failure.
3726 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3727 * asked to wait for eviction and interrupted.
3729 int i915_gem_gtt_reserve(struct i915_address_space *vm,
3730 struct drm_mm_node *node,
3731 u64 size, u64 offset, unsigned long color,
3737 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
3738 GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
3739 GEM_BUG_ON(range_overflows(offset, size, vm->total));
3740 GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->vm);
3741 GEM_BUG_ON(drm_mm_node_allocated(node));
3744 node->start = offset;
3745 node->color = color;
3747 err = drm_mm_reserve_node(&vm->mm, node);
3751 if (flags & PIN_NOEVICT)
3754 err = i915_gem_evict_for_node(vm, node, flags);
3756 err = drm_mm_reserve_node(&vm->mm, node);
3761 static u64 random_offset(u64 start, u64 end, u64 len, u64 align)
3765 GEM_BUG_ON(range_overflows(start, len, end));
3766 GEM_BUG_ON(round_up(start, align) > round_down(end - len, align));
3768 range = round_down(end - len, align) - round_up(start, align);
3770 if (sizeof(unsigned long) == sizeof(u64)) {
3771 addr = get_random_long();
3773 addr = get_random_int();
3774 if (range > U32_MAX) {
3776 addr |= get_random_int();
3779 div64_u64_rem(addr, range, &addr);
3783 return round_up(start, align);
3787 * i915_gem_gtt_insert - insert a node into an address_space (GTT)
3788 * @vm: the &struct i915_address_space
3789 * @node: the &struct drm_mm_node (typically i915_vma.node)
3790 * @size: how much space to allocate inside the GTT,
3791 * must be #I915_GTT_PAGE_SIZE aligned
3792 * @alignment: required alignment of starting offset, may be 0 but
3793 * if specified, this must be a power-of-two and at least
3794 * #I915_GTT_MIN_ALIGNMENT
3795 * @color: color to apply to node
3796 * @start: start of any range restriction inside GTT (0 for all),
3797 * must be #I915_GTT_PAGE_SIZE aligned
3798 * @end: end of any range restriction inside GTT (U64_MAX for all),
3799 * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX
3800 * @flags: control search and eviction behaviour
3802 * i915_gem_gtt_insert() first searches for an available hole into which
3803 * is can insert the node. The hole address is aligned to @alignment and
3804 * its @size must then fit entirely within the [@start, @end] bounds. The
3805 * nodes on either side of the hole must match @color, or else a guard page
3806 * will be inserted between the two nodes (or the node evicted). If no
3807 * suitable hole is found, first a victim is randomly selected and tested
3808 * for eviction, otherwise then the LRU list of objects within the GTT
3809 * is scanned to find the first set of replacement nodes to create the hole.
3810 * Those old overlapping nodes are evicted from the GTT (and so must be
3811 * rebound before any future use). Any node that is currently pinned cannot
3812 * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently
3813 * active and #PIN_NONBLOCK is specified, that node is also skipped when
3814 * searching for an eviction candidate. See i915_gem_evict_something() for
3815 * the gory details on the eviction algorithm.
3817 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3818 * asked to wait for eviction and interrupted.
3820 int i915_gem_gtt_insert(struct i915_address_space *vm,
3821 struct drm_mm_node *node,
3822 u64 size, u64 alignment, unsigned long color,
3823 u64 start, u64 end, unsigned int flags)
3825 enum drm_mm_insert_mode mode;
3829 lockdep_assert_held(&vm->i915->drm.struct_mutex);
3831 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
3832 GEM_BUG_ON(alignment && !is_power_of_2(alignment));
3833 GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
3834 GEM_BUG_ON(start >= end);
3835 GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
3836 GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
3837 GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->vm);
3838 GEM_BUG_ON(drm_mm_node_allocated(node));
3840 if (unlikely(range_overflows(start, size, end)))
3843 if (unlikely(round_up(start, alignment) > round_down(end - size, alignment)))
3846 mode = DRM_MM_INSERT_BEST;
3847 if (flags & PIN_HIGH)
3848 mode = DRM_MM_INSERT_HIGHEST;
3849 if (flags & PIN_MAPPABLE)
3850 mode = DRM_MM_INSERT_LOW;
3852 /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks,
3853 * so we know that we always have a minimum alignment of 4096.
3854 * The drm_mm range manager is optimised to return results
3855 * with zero alignment, so where possible use the optimal
3858 BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE);
3859 if (alignment <= I915_GTT_MIN_ALIGNMENT)
3862 err = drm_mm_insert_node_in_range(&vm->mm, node,
3863 size, alignment, color,
3868 if (mode & DRM_MM_INSERT_ONCE) {
3869 err = drm_mm_insert_node_in_range(&vm->mm, node,
3870 size, alignment, color,
3872 DRM_MM_INSERT_BEST);
3877 if (flags & PIN_NOEVICT)
3880 /* No free space, pick a slot at random.
3882 * There is a pathological case here using a GTT shared between
3883 * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt):
3885 * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->|
3886 * (64k objects) (448k objects)
3888 * Now imagine that the eviction LRU is ordered top-down (just because
3889 * pathology meets real life), and that we need to evict an object to
3890 * make room inside the aperture. The eviction scan then has to walk
3891 * the 448k list before it finds one within range. And now imagine that
3892 * it has to search for a new hole between every byte inside the memcpy,
3893 * for several simultaneous clients.
3895 * On a full-ppgtt system, if we have run out of available space, there
3896 * will be lots and lots of objects in the eviction list! Again,
3897 * searching that LRU list may be slow if we are also applying any
3898 * range restrictions (e.g. restriction to low 4GiB) and so, for
3899 * simplicity and similarilty between different GTT, try the single
3900 * random replacement first.
3902 offset = random_offset(start, end,
3903 size, alignment ?: I915_GTT_MIN_ALIGNMENT);
3904 err = i915_gem_gtt_reserve(vm, node, size, offset, color, flags);
3908 /* Randomly selected placement is pinned, do a search */
3909 err = i915_gem_evict_something(vm, size, alignment, color,
3914 return drm_mm_insert_node_in_range(&vm->mm, node,
3915 size, alignment, color,
3916 start, end, DRM_MM_INSERT_EVICT);
3919 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3920 #include "selftests/mock_gtt.c"
3921 #include "selftests/i915_gem_gtt.c"