2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
37 #include <linux/io-mapping.h>
39 #include <linux/pagevec.h>
41 #include "i915_request.h"
42 #include "i915_reset.h"
43 #include "i915_selftest.h"
44 #include "i915_timeline.h"
46 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
47 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
48 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
50 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
51 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
53 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
55 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
57 #define I915_FENCE_REG_NONE -1
58 #define I915_MAX_NUM_FENCES 32
59 /* 32 fences + sign bit for FENCE_REG_NONE */
60 #define I915_MAX_NUM_FENCE_BITS 6
62 struct drm_i915_file_private;
63 struct drm_i915_fence_reg;
66 typedef u32 gen6_pte_t;
67 typedef u64 gen8_pte_t;
68 typedef u64 gen8_pde_t;
69 typedef u64 gen8_ppgtt_pdpe_t;
70 typedef u64 gen8_ppgtt_pml4e_t;
72 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
74 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
75 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
76 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
77 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
78 #define GEN6_PTE_CACHE_LLC (2 << 1)
79 #define GEN6_PTE_UNCACHED (1 << 1)
80 #define GEN6_PTE_VALID (1 << 0)
82 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
83 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
85 #define I915_PDE_MASK (I915_PDES - 1)
86 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
88 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
89 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
90 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
91 #define GEN6_PDE_SHIFT 22
92 #define GEN6_PDE_VALID (1 << 0)
94 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
96 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
97 #define BYT_PTE_WRITEABLE (1 << 1)
99 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
100 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
102 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
103 (((bits) & 0x8) << (11 - 3)))
104 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
105 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
106 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
107 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
108 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
109 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
110 #define HSW_PTE_UNCACHED (0)
111 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
112 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
114 /* GEN8 32b style address is defined as a 3 level page table:
115 * 31:30 | 29:21 | 20:12 | 11:0
116 * PDPE | PDE | PTE | offset
117 * The difference as compared to normal x86 3 level page table is the PDPEs are
118 * programmed via register.
120 #define GEN8_3LVL_PDPES 4
121 #define GEN8_PDE_SHIFT 21
122 #define GEN8_PDE_MASK 0x1ff
123 #define GEN8_PTE_SHIFT 12
124 #define GEN8_PTE_MASK 0x1ff
125 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
127 /* GEN8 48b style address is defined as a 4 level page table:
128 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
129 * PML4E | PDPE | PDE | PTE | offset
131 #define GEN8_PML4ES_PER_PML4 512
132 #define GEN8_PML4E_SHIFT 39
133 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
134 #define GEN8_PDPE_SHIFT 30
135 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
137 #define GEN8_PDPE_MASK 0x1ff
139 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
140 #define PPAT_CACHED_PDE 0 /* WB LLC */
141 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
142 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
144 #define CHV_PPAT_SNOOP (1<<6)
145 #define GEN8_PPAT_AGE(x) ((x)<<4)
146 #define GEN8_PPAT_LLCeLLC (3<<2)
147 #define GEN8_PPAT_LLCELLC (2<<2)
148 #define GEN8_PPAT_LLC (1<<2)
149 #define GEN8_PPAT_WB (3<<0)
150 #define GEN8_PPAT_WT (2<<0)
151 #define GEN8_PPAT_WC (1<<0)
152 #define GEN8_PPAT_UC (0<<0)
153 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
154 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
156 #define GEN8_PPAT_GET_CA(x) ((x) & 3)
157 #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2))
158 #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
159 #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
161 #define GEN8_PDE_IPS_64K BIT(11)
162 #define GEN8_PDE_PS_2M BIT(7)
166 struct intel_rotation_info {
167 struct intel_rotation_plane_info {
169 unsigned int width, height, stride, offset;
173 struct intel_partial_info {
178 enum i915_ggtt_view_type {
179 I915_GGTT_VIEW_NORMAL = 0,
180 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
181 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
184 static inline void assert_i915_gem_gtt_types(void)
186 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
187 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
189 /* As we encode the size of each branch inside the union into its type,
190 * we have to be careful that each branch has a unique size.
192 switch ((enum i915_ggtt_view_type)0) {
193 case I915_GGTT_VIEW_NORMAL:
194 case I915_GGTT_VIEW_PARTIAL:
195 case I915_GGTT_VIEW_ROTATED:
196 /* gcc complains if these are identical cases */
201 struct i915_ggtt_view {
202 enum i915_ggtt_view_type type;
204 /* Members need to contain no holes/padding */
205 struct intel_partial_info partial;
206 struct intel_rotation_info rotated;
210 enum i915_cache_level;
214 struct i915_page_dma {
219 /* For gen6/gen7 only. This is the offset in the GGTT
220 * where the page directory entries for PPGTT begin
226 #define px_base(px) (&(px)->base)
227 #define px_dma(px) (px_base(px)->daddr)
229 struct i915_page_table {
230 struct i915_page_dma base;
231 unsigned int used_ptes;
234 struct i915_page_directory {
235 struct i915_page_dma base;
237 struct i915_page_table *page_table[I915_PDES]; /* PDEs */
238 unsigned int used_pdes;
241 struct i915_page_directory_pointer {
242 struct i915_page_dma base;
243 struct i915_page_directory **page_directory;
244 unsigned int used_pdpes;
248 struct i915_page_dma base;
249 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
252 struct i915_vma_ops {
253 /* Map an object into an address space with the given cache flags. */
254 int (*bind_vma)(struct i915_vma *vma,
255 enum i915_cache_level cache_level,
258 * Unmap an object from an address space. This usually consists of
259 * setting the valid PTE entries to a reserved scratch page.
261 void (*unbind_vma)(struct i915_vma *vma);
263 int (*set_pages)(struct i915_vma *vma);
264 void (*clear_pages)(struct i915_vma *vma);
272 struct i915_address_space {
274 struct drm_i915_private *i915;
276 /* Every address space belongs to a struct file - except for the global
277 * GTT that is owned by the driver (and so @file is set to NULL). In
278 * principle, no information should leak from one context to another
279 * (or between files/processes etc) unless explicitly shared by the
280 * owner. Tracking the owner is important in order to free up per-file
281 * objects along with the file, to aide resource tracking, and to
284 struct drm_i915_file_private *file;
285 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
286 u64 reserved; /* size addr space reserved */
290 struct mutex mutex; /* protects vma and our lists */
291 #define VM_CLASS_GGTT 0
292 #define VM_CLASS_PPGTT 1
296 struct i915_page_dma scratch_page;
297 struct i915_page_table *scratch_pt;
298 struct i915_page_directory *scratch_pd;
299 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
302 * List of vma currently bound.
304 struct list_head bound_list;
307 * List of vma that are not unbound.
309 struct list_head unbound_list;
311 struct pagestash free_pages;
316 /* Some systems require uncached updates of the page directories */
319 /* Some systems support read-only mappings for GGTT and/or PPGTT */
320 bool has_read_only:1;
322 u64 (*pte_encode)(dma_addr_t addr,
323 enum i915_cache_level level,
324 u32 flags); /* Create a valid PTE */
325 #define PTE_READ_ONLY (1<<0)
327 int (*allocate_va_range)(struct i915_address_space *vm,
328 u64 start, u64 length);
329 void (*clear_range)(struct i915_address_space *vm,
330 u64 start, u64 length);
331 void (*insert_page)(struct i915_address_space *vm,
334 enum i915_cache_level cache_level,
336 void (*insert_entries)(struct i915_address_space *vm,
337 struct i915_vma *vma,
338 enum i915_cache_level cache_level,
340 void (*cleanup)(struct i915_address_space *vm);
342 struct i915_vma_ops vma_ops;
344 I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
345 I915_SELFTEST_DECLARE(bool scrub_64K);
348 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
351 i915_vm_is_4lvl(const struct i915_address_space *vm)
353 return (vm->total - 1) >> 32;
357 i915_vm_has_scratch_64K(struct i915_address_space *vm)
359 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
362 /* The Graphics Translation Table is the way in which GEN hardware translates a
363 * Graphics Virtual Address into a Physical Address. In addition to the normal
364 * collateral associated with any va->pa translations GEN hardware also has a
365 * portion of the GTT which can be mapped by the CPU and remain both coherent
366 * and correct (in cases like swizzling). That region is referred to as GMADR in
370 struct i915_address_space vm;
372 struct io_mapping iomap; /* Mapping to our CPU mappable region */
373 struct resource gmadr; /* GMADR resource */
374 resource_size_t mappable_end; /* End offset that we can CPU map */
376 /** "Graphics Stolen Memory" holds the global PTEs */
378 void (*invalidate)(struct drm_i915_private *dev_priv);
386 struct drm_mm_node error_capture;
389 struct i915_hw_ppgtt {
390 struct i915_address_space vm;
393 intel_engine_mask_t pd_dirty_engines;
395 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */
396 struct i915_page_directory_pointer pdp; /* GEN8+ */
397 struct i915_page_directory pd; /* GEN6-7 */
403 struct gen6_hw_ppgtt {
404 struct i915_hw_ppgtt base;
406 struct i915_vma *vma;
407 gen6_pte_t __iomem *pd_addr;
409 unsigned int pin_count;
410 bool scan_for_unused_pt;
413 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base)
415 static inline struct gen6_hw_ppgtt *to_gen6_ppgtt(struct i915_hw_ppgtt *base)
417 BUILD_BUG_ON(offsetof(struct gen6_hw_ppgtt, base));
418 return __to_gen6_ppgtt(base);
422 * gen6_for_each_pde() iterates over every pde from start until start+length.
423 * If start and start+length are not perfectly divisible, the macro will round
424 * down and up as needed. Start=0 and length=2G effectively iterates over
425 * every PDE in the system. The macro modifies ALL its parameters except 'pd',
426 * so each of the other parameters should preferably be a simple variable, or
427 * at most an lvalue with no side-effects!
429 #define gen6_for_each_pde(pt, pd, start, length, iter) \
430 for (iter = gen6_pde_index(start); \
431 length > 0 && iter < I915_PDES && \
432 (pt = (pd)->page_table[iter], true); \
433 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
434 temp = min(temp - start, length); \
435 start += temp, length -= temp; }), ++iter)
437 #define gen6_for_all_pdes(pt, pd, iter) \
439 iter < I915_PDES && \
440 (pt = (pd)->page_table[iter], true); \
443 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
445 const u32 mask = NUM_PTE(pde_shift) - 1;
447 return (address >> PAGE_SHIFT) & mask;
450 /* Helper to counts the number of PTEs within the given length. This count
451 * does not cross a page table boundary, so the max value would be
452 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
454 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
456 const u64 mask = ~((1ULL << pde_shift) - 1);
459 GEM_BUG_ON(length == 0);
460 GEM_BUG_ON(offset_in_page(addr | length));
464 if ((addr & mask) != (end & mask))
465 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
467 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
470 static inline u32 i915_pde_index(u64 addr, u32 shift)
472 return (addr >> shift) & I915_PDE_MASK;
475 static inline u32 gen6_pte_index(u32 addr)
477 return i915_pte_index(addr, GEN6_PDE_SHIFT);
480 static inline u32 gen6_pte_count(u32 addr, u32 length)
482 return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
485 static inline u32 gen6_pde_index(u32 addr)
487 return i915_pde_index(addr, GEN6_PDE_SHIFT);
490 static inline unsigned int
491 i915_pdpes_per_pdp(const struct i915_address_space *vm)
493 if (i915_vm_is_4lvl(vm))
494 return GEN8_PML4ES_PER_PML4;
496 return GEN8_3LVL_PDPES;
499 /* Equivalent to the gen6 version, For each pde iterates over every pde
500 * between from start until start + length. On gen8+ it simply iterates
501 * over every page directory entry in a page directory.
503 #define gen8_for_each_pde(pt, pd, start, length, iter) \
504 for (iter = gen8_pde_index(start); \
505 length > 0 && iter < I915_PDES && \
506 (pt = (pd)->page_table[iter], true); \
507 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
508 temp = min(temp - start, length); \
509 start += temp, length -= temp; }), ++iter)
511 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
512 for (iter = gen8_pdpe_index(start); \
513 length > 0 && iter < i915_pdpes_per_pdp(vm) && \
514 (pd = (pdp)->page_directory[iter], true); \
515 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
516 temp = min(temp - start, length); \
517 start += temp, length -= temp; }), ++iter)
519 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
520 for (iter = gen8_pml4e_index(start); \
521 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
522 (pdp = (pml4)->pdps[iter], true); \
523 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
524 temp = min(temp - start, length); \
525 start += temp, length -= temp; }), ++iter)
527 static inline u32 gen8_pte_index(u64 address)
529 return i915_pte_index(address, GEN8_PDE_SHIFT);
532 static inline u32 gen8_pde_index(u64 address)
534 return i915_pde_index(address, GEN8_PDE_SHIFT);
537 static inline u32 gen8_pdpe_index(u64 address)
539 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
542 static inline u32 gen8_pml4e_index(u64 address)
544 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
547 static inline u64 gen8_pte_count(u64 address, u64 length)
549 return i915_pte_count(address, length, GEN8_PDE_SHIFT);
552 static inline dma_addr_t
553 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
555 return px_dma(ppgtt->pdp.page_directory[n]);
558 static inline struct i915_ggtt *
559 i915_vm_to_ggtt(struct i915_address_space *vm)
561 GEM_BUG_ON(!i915_is_ggtt(vm));
562 return container_of(vm, struct i915_ggtt, vm);
565 #define INTEL_MAX_PPAT_ENTRIES 8
566 #define INTEL_PPAT_PERFECT_MATCH (~0U)
570 struct intel_ppat_entry {
571 struct intel_ppat *ppat;
577 struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES];
578 DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES);
579 DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES);
580 unsigned int max_entries;
583 * Return a score to show how two PPAT values match,
584 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match
586 unsigned int (*match)(u8 src, u8 dst);
587 void (*update_hw)(struct drm_i915_private *i915);
589 struct drm_i915_private *i915;
592 const struct intel_ppat_entry *
593 intel_ppat_get(struct drm_i915_private *i915, u8 value);
594 void intel_ppat_put(const struct intel_ppat_entry *entry);
596 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
597 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
599 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
600 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
601 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
602 void i915_ggtt_enable_guc(struct drm_i915_private *i915);
603 void i915_ggtt_disable_guc(struct drm_i915_private *i915);
604 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
605 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
607 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
609 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
610 void i915_ppgtt_release(struct kref *kref);
612 static inline struct i915_hw_ppgtt *i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
614 kref_get(&ppgtt->ref);
618 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
621 kref_put(&ppgtt->ref, i915_ppgtt_release);
624 int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
625 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
626 void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base);
628 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
629 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
630 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
632 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
633 struct sg_table *pages);
634 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
635 struct sg_table *pages);
637 int i915_gem_gtt_reserve(struct i915_address_space *vm,
638 struct drm_mm_node *node,
639 u64 size, u64 offset, unsigned long color,
642 int i915_gem_gtt_insert(struct i915_address_space *vm,
643 struct drm_mm_node *node,
644 u64 size, u64 alignment, unsigned long color,
645 u64 start, u64 end, unsigned int flags);
647 /* Flags used by pin/bind&friends. */
648 #define PIN_NONBLOCK BIT_ULL(0)
649 #define PIN_NONFAULT BIT_ULL(1)
650 #define PIN_NOEVICT BIT_ULL(2)
651 #define PIN_MAPPABLE BIT_ULL(3)
652 #define PIN_ZONE_4G BIT_ULL(4)
653 #define PIN_HIGH BIT_ULL(5)
654 #define PIN_OFFSET_BIAS BIT_ULL(6)
655 #define PIN_OFFSET_FIXED BIT_ULL(7)
657 #define PIN_MBZ BIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */
658 #define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */
659 #define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */
660 #define PIN_UPDATE BIT_ULL(11)
662 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)