2 * Copyright © 2008-2015 Intel Corporation
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/prefetch.h>
26 #include <linux/dma-fence-array.h>
30 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
35 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
37 return to_request(fence)->timeline->common->name;
40 static bool i915_fence_signaled(struct dma_fence *fence)
42 return i915_gem_request_completed(to_request(fence));
45 static bool i915_fence_enable_signaling(struct dma_fence *fence)
47 if (i915_fence_signaled(fence))
50 intel_engine_enable_signaling(to_request(fence));
54 static signed long i915_fence_wait(struct dma_fence *fence,
58 return i915_wait_request(to_request(fence), interruptible, timeout);
61 static void i915_fence_release(struct dma_fence *fence)
63 struct drm_i915_gem_request *req = to_request(fence);
65 kmem_cache_free(req->i915->requests, req);
68 const struct dma_fence_ops i915_fence_ops = {
69 .get_driver_name = i915_fence_get_driver_name,
70 .get_timeline_name = i915_fence_get_timeline_name,
71 .enable_signaling = i915_fence_enable_signaling,
72 .signaled = i915_fence_signaled,
73 .wait = i915_fence_wait,
74 .release = i915_fence_release,
77 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
78 struct drm_file *file)
80 struct drm_i915_private *dev_private;
81 struct drm_i915_file_private *file_priv;
83 WARN_ON(!req || !file || req->file_priv);
91 dev_private = req->i915;
92 file_priv = file->driver_priv;
94 spin_lock(&file_priv->mm.lock);
95 req->file_priv = file_priv;
96 list_add_tail(&req->client_list, &file_priv->mm.request_list);
97 spin_unlock(&file_priv->mm.lock);
103 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
105 struct drm_i915_file_private *file_priv = request->file_priv;
110 spin_lock(&file_priv->mm.lock);
111 list_del(&request->client_list);
112 request->file_priv = NULL;
113 spin_unlock(&file_priv->mm.lock);
116 static struct i915_dependency *
117 i915_dependency_alloc(struct drm_i915_private *i915)
119 return kmem_cache_alloc(i915->dependencies, GFP_KERNEL);
123 i915_dependency_free(struct drm_i915_private *i915,
124 struct i915_dependency *dep)
126 kmem_cache_free(i915->dependencies, dep);
130 __i915_priotree_add_dependency(struct i915_priotree *pt,
131 struct i915_priotree *signal,
132 struct i915_dependency *dep,
135 INIT_LIST_HEAD(&dep->dfs_link);
136 list_add(&dep->wait_link, &signal->waiters_list);
137 list_add(&dep->signal_link, &pt->signalers_list);
138 dep->signaler = signal;
143 i915_priotree_add_dependency(struct drm_i915_private *i915,
144 struct i915_priotree *pt,
145 struct i915_priotree *signal)
147 struct i915_dependency *dep;
149 dep = i915_dependency_alloc(i915);
153 __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC);
158 i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt)
160 struct i915_dependency *dep, *next;
162 GEM_BUG_ON(!RB_EMPTY_NODE(&pt->node));
164 /* Everyone we depended upon (the fences we wait to be signaled)
165 * should retire before us and remove themselves from our list.
166 * However, retirement is run independently on each timeline and
167 * so we may be called out-of-order.
169 list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) {
170 list_del(&dep->wait_link);
171 if (dep->flags & I915_DEPENDENCY_ALLOC)
172 i915_dependency_free(i915, dep);
175 /* Remove ourselves from everyone who depends upon us */
176 list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) {
177 list_del(&dep->signal_link);
178 if (dep->flags & I915_DEPENDENCY_ALLOC)
179 i915_dependency_free(i915, dep);
184 i915_priotree_init(struct i915_priotree *pt)
186 INIT_LIST_HEAD(&pt->signalers_list);
187 INIT_LIST_HEAD(&pt->waiters_list);
188 RB_CLEAR_NODE(&pt->node);
189 pt->priority = INT_MIN;
192 void i915_gem_retire_noop(struct i915_gem_active *active,
193 struct drm_i915_gem_request *request)
195 /* Space left intentionally blank */
198 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
200 struct i915_gem_active *active, *next;
202 lockdep_assert_held(&request->i915->drm.struct_mutex);
203 GEM_BUG_ON(!i915_sw_fence_done(&request->submit));
204 GEM_BUG_ON(!i915_sw_fence_done(&request->execute));
205 GEM_BUG_ON(!i915_gem_request_completed(request));
206 GEM_BUG_ON(!request->i915->gt.active_requests);
208 trace_i915_gem_request_retire(request);
210 spin_lock_irq(&request->engine->timeline->lock);
211 list_del_init(&request->link);
212 spin_unlock_irq(&request->engine->timeline->lock);
214 /* We know the GPU must have read the request to have
215 * sent us the seqno + interrupt, so use the position
216 * of tail of the request to update the last known position
219 * Note this requires that we are always called in request
222 list_del(&request->ring_link);
223 request->ring->last_retired_head = request->postfix;
224 if (!--request->i915->gt.active_requests) {
225 GEM_BUG_ON(!request->i915->gt.awake);
226 mod_delayed_work(request->i915->wq,
227 &request->i915->gt.idle_work,
228 msecs_to_jiffies(100));
231 /* Walk through the active list, calling retire on each. This allows
232 * objects to track their GPU activity and mark themselves as idle
233 * when their *last* active request is completed (updating state
234 * tracking lists for eviction, active references for GEM, etc).
236 * As the ->retire() may free the node, we decouple it first and
237 * pass along the auxiliary information (to avoid dereferencing
238 * the node after the callback).
240 list_for_each_entry_safe(active, next, &request->active_list, link) {
241 /* In microbenchmarks or focusing upon time inside the kernel,
242 * we may spend an inordinate amount of time simply handling
243 * the retirement of requests and processing their callbacks.
244 * Of which, this loop itself is particularly hot due to the
245 * cache misses when jumping around the list of i915_gem_active.
246 * So we try to keep this loop as streamlined as possible and
247 * also prefetch the next i915_gem_active to try and hide
248 * the likely cache miss.
252 INIT_LIST_HEAD(&active->link);
253 RCU_INIT_POINTER(active->request, NULL);
255 active->retire(active, request);
258 i915_gem_request_remove_from_client(request);
260 if (request->previous_context) {
261 if (i915.enable_execlists)
262 intel_lr_context_unpin(request->previous_context,
266 /* Retirement decays the ban score as it is a sign of ctx progress */
267 if (request->ctx->ban_score > 0)
268 request->ctx->ban_score--;
270 i915_gem_context_put(request->ctx);
272 dma_fence_signal(&request->fence);
274 i915_priotree_fini(request->i915, &request->priotree);
275 i915_gem_request_put(request);
278 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
280 struct intel_engine_cs *engine = req->engine;
281 struct drm_i915_gem_request *tmp;
283 lockdep_assert_held(&req->i915->drm.struct_mutex);
284 if (list_empty(&req->link))
288 tmp = list_first_entry(&engine->timeline->requests,
291 i915_gem_request_retire(tmp);
292 } while (tmp != req);
295 static int i915_gem_check_wedge(struct drm_i915_private *dev_priv)
297 struct i915_gpu_error *error = &dev_priv->gpu_error;
299 if (i915_terminally_wedged(error))
302 if (i915_reset_in_progress(error)) {
303 /* Non-interruptible callers can't handle -EAGAIN, hence return
304 * -EIO unconditionally for these.
306 if (!dev_priv->mm.interruptible)
315 static int i915_gem_init_global_seqno(struct drm_i915_private *i915, u32 seqno)
317 struct i915_gem_timeline *timeline = &i915->gt.global_timeline;
318 struct intel_engine_cs *engine;
319 enum intel_engine_id id;
322 /* Carefully retire all requests without writing to the rings */
323 ret = i915_gem_wait_for_idle(i915,
324 I915_WAIT_INTERRUPTIBLE |
329 i915_gem_retire_requests(i915);
330 GEM_BUG_ON(i915->gt.active_requests > 1);
332 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
333 if (!i915_seqno_passed(seqno, atomic_read(&timeline->seqno))) {
334 while (intel_breadcrumbs_busy(i915))
335 cond_resched(); /* spin until threads are complete */
337 atomic_set(&timeline->seqno, seqno);
339 /* Finally reset hw state */
340 for_each_engine(engine, i915, id)
341 intel_engine_init_global_seqno(engine, seqno);
343 list_for_each_entry(timeline, &i915->gt.timelines, link) {
344 for_each_engine(engine, i915, id) {
345 struct intel_timeline *tl = &timeline->engine[id];
347 memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno));
354 int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
356 struct drm_i915_private *dev_priv = to_i915(dev);
358 lockdep_assert_held(&dev_priv->drm.struct_mutex);
363 /* HWS page needs to be set less than what we
364 * will inject to ring
366 return i915_gem_init_global_seqno(dev_priv, seqno - 1);
369 static int reserve_global_seqno(struct drm_i915_private *i915)
371 u32 active_requests = ++i915->gt.active_requests;
372 u32 seqno = atomic_read(&i915->gt.global_timeline.seqno);
375 /* Reservation is fine until we need to wrap around */
376 if (likely(seqno + active_requests > seqno))
379 ret = i915_gem_init_global_seqno(i915, 0);
381 i915->gt.active_requests--;
388 static u32 __timeline_get_seqno(struct i915_gem_timeline *tl)
390 /* seqno only incremented under a mutex */
391 return ++tl->seqno.counter;
394 static u32 timeline_get_seqno(struct i915_gem_timeline *tl)
396 return atomic_inc_return(&tl->seqno);
399 void __i915_gem_request_submit(struct drm_i915_gem_request *request)
401 struct intel_engine_cs *engine = request->engine;
402 struct intel_timeline *timeline;
405 /* Transfer from per-context onto the global per-engine timeline */
406 timeline = engine->timeline;
407 GEM_BUG_ON(timeline == request->timeline);
408 assert_spin_locked(&timeline->lock);
410 seqno = timeline_get_seqno(timeline->common);
412 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
414 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno, seqno));
415 request->previous_seqno = timeline->last_submitted_seqno;
416 timeline->last_submitted_seqno = seqno;
418 /* We may be recursing from the signal callback of another i915 fence */
419 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
420 request->global_seqno = seqno;
421 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
422 intel_engine_enable_signaling(request);
423 spin_unlock(&request->lock);
425 GEM_BUG_ON(!request->global_seqno);
426 engine->emit_breadcrumb(request,
427 request->ring->vaddr + request->postfix);
429 spin_lock(&request->timeline->lock);
430 list_move_tail(&request->link, &timeline->requests);
431 spin_unlock(&request->timeline->lock);
433 i915_sw_fence_commit(&request->execute);
436 void i915_gem_request_submit(struct drm_i915_gem_request *request)
438 struct intel_engine_cs *engine = request->engine;
441 /* Will be called from irq-context when using foreign fences. */
442 spin_lock_irqsave(&engine->timeline->lock, flags);
444 __i915_gem_request_submit(request);
446 spin_unlock_irqrestore(&engine->timeline->lock, flags);
449 static int __i915_sw_fence_call
450 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
452 if (state == FENCE_COMPLETE) {
453 struct drm_i915_gem_request *request =
454 container_of(fence, typeof(*request), submit);
456 request->engine->submit_request(request);
462 static int __i915_sw_fence_call
463 execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
469 * i915_gem_request_alloc - allocate a request structure
471 * @engine: engine that we wish to issue the request on.
472 * @ctx: context that the request will be associated with.
473 * This can be NULL if the request is not directly related to
474 * any specific user context, in which case this function will
475 * choose an appropriate context to use.
477 * Returns a pointer to the allocated request if successful,
478 * or an error code if not.
480 struct drm_i915_gem_request *
481 i915_gem_request_alloc(struct intel_engine_cs *engine,
482 struct i915_gem_context *ctx)
484 struct drm_i915_private *dev_priv = engine->i915;
485 struct drm_i915_gem_request *req;
488 lockdep_assert_held(&dev_priv->drm.struct_mutex);
490 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
491 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
494 ret = i915_gem_check_wedge(dev_priv);
498 ret = reserve_global_seqno(dev_priv);
502 /* Move the oldest request to the slab-cache (if not in use!) */
503 req = list_first_entry_or_null(&engine->timeline->requests,
505 if (req && __i915_gem_request_completed(req))
506 i915_gem_request_retire(req);
508 /* Beware: Dragons be flying overhead.
510 * We use RCU to look up requests in flight. The lookups may
511 * race with the request being allocated from the slab freelist.
512 * That is the request we are writing to here, may be in the process
513 * of being read by __i915_gem_active_get_rcu(). As such,
514 * we have to be very careful when overwriting the contents. During
515 * the RCU lookup, we change chase the request->engine pointer,
516 * read the request->global_seqno and increment the reference count.
518 * The reference count is incremented atomically. If it is zero,
519 * the lookup knows the request is unallocated and complete. Otherwise,
520 * it is either still in use, or has been reallocated and reset
521 * with dma_fence_init(). This increment is safe for release as we
522 * check that the request we have a reference to and matches the active
525 * Before we increment the refcount, we chase the request->engine
526 * pointer. We must not call kmem_cache_zalloc() or else we set
527 * that pointer to NULL and cause a crash during the lookup. If
528 * we see the request is completed (based on the value of the
529 * old engine and seqno), the lookup is complete and reports NULL.
530 * If we decide the request is not completed (new engine or seqno),
531 * then we grab a reference and double check that it is still the
532 * active request - which it won't be and restart the lookup.
534 * Do not use kmem_cache_zalloc() here!
536 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
542 req->timeline = i915_gem_context_lookup_timeline(ctx, engine);
543 GEM_BUG_ON(req->timeline == engine->timeline);
545 spin_lock_init(&req->lock);
546 dma_fence_init(&req->fence,
549 req->timeline->fence_context,
550 __timeline_get_seqno(req->timeline->common));
552 i915_sw_fence_init(&req->submit, submit_notify);
553 i915_sw_fence_init(&req->execute, execute_notify);
554 /* Ensure that the execute fence completes after the submit fence -
555 * as we complete the execute fence from within the submit fence
556 * callback, its completion would otherwise be visible first.
558 i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq);
560 i915_priotree_init(&req->priotree);
562 INIT_LIST_HEAD(&req->active_list);
563 req->i915 = dev_priv;
564 req->engine = engine;
565 req->ctx = i915_gem_context_get(ctx);
567 /* No zalloc, must clear what we need by hand */
568 req->global_seqno = 0;
569 req->previous_context = NULL;
570 req->file_priv = NULL;
574 * Reserve space in the ring buffer for all the commands required to
575 * eventually emit this request. This is to guarantee that the
576 * i915_add_request() call can't fail. Note that the reserve may need
577 * to be redone if the request is not actually submitted straight
578 * away, e.g. because a GPU scheduler has deferred it.
580 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
581 GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
583 if (i915.enable_execlists)
584 ret = intel_logical_ring_alloc_request_extras(req);
586 ret = intel_ring_alloc_request_extras(req);
590 /* Record the position of the start of the request so that
591 * should we detect the updated seqno part-way through the
592 * GPU processing the request, we never over-estimate the
593 * position of the head.
595 req->head = req->ring->tail;
600 i915_gem_context_put(ctx);
601 kmem_cache_free(dev_priv->requests, req);
603 dev_priv->gt.active_requests--;
608 i915_gem_request_await_request(struct drm_i915_gem_request *to,
609 struct drm_i915_gem_request *from)
613 GEM_BUG_ON(to == from);
615 if (to->engine->schedule) {
616 ret = i915_priotree_add_dependency(to->i915,
623 if (to->timeline == from->timeline)
626 if (to->engine == from->engine) {
627 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
630 return ret < 0 ? ret : 0;
633 if (!from->global_seqno) {
634 ret = i915_sw_fence_await_dma_fence(&to->submit,
637 return ret < 0 ? ret : 0;
640 if (from->global_seqno <= to->timeline->sync_seqno[from->engine->id])
643 trace_i915_gem_ring_sync_to(to, from);
644 if (!i915.semaphores) {
645 if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
646 ret = i915_sw_fence_await_dma_fence(&to->submit,
653 ret = to->engine->semaphore.sync_to(to, from);
658 to->timeline->sync_seqno[from->engine->id] = from->global_seqno;
663 i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req,
664 struct dma_fence *fence)
666 struct dma_fence_array *array;
670 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
673 if (dma_fence_is_i915(fence))
674 return i915_gem_request_await_request(req, to_request(fence));
676 if (!dma_fence_is_array(fence)) {
677 ret = i915_sw_fence_await_dma_fence(&req->submit,
678 fence, I915_FENCE_TIMEOUT,
680 return ret < 0 ? ret : 0;
683 /* Note that if the fence-array was created in signal-on-any mode,
684 * we should *not* decompose it into its individual fences. However,
685 * we don't currently store which mode the fence-array is operating
686 * in. Fortunately, the only user of signal-on-any is private to
687 * amdgpu and we should not see any incoming fence-array from
688 * sync-file being in signal-on-any mode.
691 array = to_dma_fence_array(fence);
692 for (i = 0; i < array->num_fences; i++) {
693 struct dma_fence *child = array->fences[i];
695 if (dma_fence_is_i915(child))
696 ret = i915_gem_request_await_request(req,
699 ret = i915_sw_fence_await_dma_fence(&req->submit,
700 child, I915_FENCE_TIMEOUT,
710 * i915_gem_request_await_object - set this request to (async) wait upon a bo
712 * @to: request we are wishing to use
713 * @obj: object which may be in use on another ring.
715 * This code is meant to abstract object synchronization with the GPU.
716 * Conceptually we serialise writes between engines inside the GPU.
717 * We only allow one engine to write into a buffer at any time, but
718 * multiple readers. To ensure each has a coherent view of memory, we must:
720 * - If there is an outstanding write request to the object, the new
721 * request must wait for it to complete (either CPU or in hw, requests
722 * on the same ring will be naturally ordered).
724 * - If we are a write request (pending_write_domain is set), the new
725 * request must wait for outstanding read requests to complete.
727 * Returns 0 if successful, else propagates up the lower layer error.
730 i915_gem_request_await_object(struct drm_i915_gem_request *to,
731 struct drm_i915_gem_object *obj,
734 struct dma_fence *excl;
738 struct dma_fence **shared;
739 unsigned int count, i;
741 ret = reservation_object_get_fences_rcu(obj->resv,
742 &excl, &count, &shared);
746 for (i = 0; i < count; i++) {
747 ret = i915_gem_request_await_dma_fence(to, shared[i]);
751 dma_fence_put(shared[i]);
754 for (; i < count; i++)
755 dma_fence_put(shared[i]);
758 excl = reservation_object_get_excl_rcu(obj->resv);
763 ret = i915_gem_request_await_dma_fence(to, excl);
771 static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
773 struct drm_i915_private *dev_priv = engine->i915;
775 if (dev_priv->gt.awake)
778 GEM_BUG_ON(!dev_priv->gt.active_requests);
780 intel_runtime_pm_get_noresume(dev_priv);
781 dev_priv->gt.awake = true;
783 intel_enable_gt_powersave(dev_priv);
784 i915_update_gfx_val(dev_priv);
785 if (INTEL_GEN(dev_priv) >= 6)
786 gen6_rps_busy(dev_priv);
788 queue_delayed_work(dev_priv->wq,
789 &dev_priv->gt.retire_work,
790 round_jiffies_up_relative(HZ));
794 * NB: This function is not allowed to fail. Doing so would mean the the
795 * request is not being tracked for completion but the work itself is
796 * going to happen on the hardware. This would be a Bad Thing(tm).
798 void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
800 struct intel_engine_cs *engine = request->engine;
801 struct intel_ring *ring = request->ring;
802 struct intel_timeline *timeline = request->timeline;
803 struct drm_i915_gem_request *prev;
806 lockdep_assert_held(&request->i915->drm.struct_mutex);
807 trace_i915_gem_request_add(request);
810 * To ensure that this call will not fail, space for its emissions
811 * should already have been reserved in the ring buffer. Let the ring
812 * know that it is time to use that space up.
814 request->reserved_space = 0;
817 * Emit any outstanding flushes - execbuf can fail to emit the flush
818 * after having emitted the batchbuffer command. Hence we need to fix
819 * things up similar to emitting the lazy request. The difference here
820 * is that the flush _must_ happen before the next request, no matter
824 err = engine->emit_flush(request, EMIT_FLUSH);
826 /* Not allowed to fail! */
827 WARN(err, "engine->emit_flush() failed: %d!\n", err);
830 /* Record the position of the start of the breadcrumb so that
831 * should we detect the updated seqno part-way through the
832 * GPU processing the request, we never over-estimate the
833 * position of the ring's HEAD.
835 err = intel_ring_begin(request, engine->emit_breadcrumb_sz);
837 request->postfix = ring->tail;
838 ring->tail += engine->emit_breadcrumb_sz * sizeof(u32);
840 /* Seal the request and mark it as pending execution. Note that
841 * we may inspect this state, without holding any locks, during
842 * hangcheck. Hence we apply the barrier to ensure that we do not
843 * see a more recent value in the hws than we are tracking.
846 prev = i915_gem_active_raw(&timeline->last_request,
847 &request->i915->drm.struct_mutex);
849 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
851 if (engine->schedule)
852 __i915_priotree_add_dependency(&request->priotree,
858 spin_lock_irq(&timeline->lock);
859 list_add_tail(&request->link, &timeline->requests);
860 spin_unlock_irq(&timeline->lock);
862 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
863 request->fence.seqno));
865 timeline->last_submitted_seqno = request->fence.seqno;
866 i915_gem_active_set(&timeline->last_request, request);
868 list_add_tail(&request->ring_link, &ring->request_list);
869 request->emitted_jiffies = jiffies;
871 i915_gem_mark_busy(engine);
873 /* Let the backend know a new request has arrived that may need
874 * to adjust the existing execution schedule due to a high priority
875 * request - i.e. we may want to preempt the current request in order
876 * to run a high priority dependency chain *before* we can execute this
879 * This is called before the request is ready to run so that we can
880 * decide whether to preempt the entire chain so that it is ready to
881 * run at the earliest possible convenience.
883 if (engine->schedule)
884 engine->schedule(request, request->ctx->priority);
887 i915_sw_fence_commit(&request->submit);
888 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
891 static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
895 spin_lock_irqsave(&q->lock, flags);
896 if (list_empty(&wait->task_list))
897 __add_wait_queue(q, wait);
898 spin_unlock_irqrestore(&q->lock, flags);
901 static unsigned long local_clock_us(unsigned int *cpu)
905 /* Cheaply and approximately convert from nanoseconds to microseconds.
906 * The result and subsequent calculations are also defined in the same
907 * approximate microseconds units. The principal source of timing
908 * error here is from the simple truncation.
910 * Note that local_clock() is only defined wrt to the current CPU;
911 * the comparisons are no longer valid if we switch CPUs. Instead of
912 * blocking preemption for the entire busywait, we can detect the CPU
913 * switch and use that as indicator of system load and a reason to
914 * stop busywaiting, see busywait_stop().
917 t = local_clock() >> 10;
923 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
925 unsigned int this_cpu;
927 if (time_after(local_clock_us(&this_cpu), timeout))
930 return this_cpu != cpu;
933 bool __i915_spin_request(const struct drm_i915_gem_request *req,
934 int state, unsigned long timeout_us)
938 /* When waiting for high frequency requests, e.g. during synchronous
939 * rendering split between the CPU and GPU, the finite amount of time
940 * required to set up the irq and wait upon it limits the response
941 * rate. By busywaiting on the request completion for a short while we
942 * can service the high frequency waits as quick as possible. However,
943 * if it is a slow request, we want to sleep as quickly as possible.
944 * The tradeoff between waiting and sleeping is roughly the time it
945 * takes to sleep on a request, on the order of a microsecond.
948 timeout_us += local_clock_us(&cpu);
950 if (__i915_gem_request_completed(req))
953 if (signal_pending_state(state, current))
956 if (busywait_stop(timeout_us, cpu))
959 cpu_relax_lowlatency();
960 } while (!need_resched());
966 __i915_request_wait_for_execute(struct drm_i915_gem_request *request,
970 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
971 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
972 wait_queue_head_t *q = &request->i915->gpu_error.wait_queue;
976 if (flags & I915_WAIT_LOCKED)
977 add_wait_queue(q, &reset);
980 prepare_to_wait(&request->execute.wait, &wait, state);
982 if (i915_sw_fence_done(&request->execute))
985 if (flags & I915_WAIT_LOCKED &&
986 i915_reset_in_progress(&request->i915->gpu_error)) {
987 __set_current_state(TASK_RUNNING);
988 i915_reset(request->i915);
989 reset_wait_queue(q, &reset);
993 if (signal_pending_state(state, current)) {
994 timeout = -ERESTARTSYS;
998 timeout = io_schedule_timeout(timeout);
1000 finish_wait(&request->execute.wait, &wait);
1002 if (flags & I915_WAIT_LOCKED)
1003 remove_wait_queue(q, &reset);
1009 * i915_wait_request - wait until execution of request has finished
1010 * @req: the request to wait upon
1011 * @flags: how to wait
1012 * @timeout: how long to wait in jiffies
1014 * i915_wait_request() waits for the request to be completed, for a
1015 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1018 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1019 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1020 * must not specify that the wait is locked.
1022 * Returns the remaining time (in jiffies) if the request completed, which may
1023 * be zero or -ETIME if the request is unfinished after the timeout expires.
1024 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1025 * pending before the request completes.
1027 long i915_wait_request(struct drm_i915_gem_request *req,
1031 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1032 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1034 struct intel_wait wait;
1037 #if IS_ENABLED(CONFIG_LOCKDEP)
1038 GEM_BUG_ON(debug_locks &&
1039 !!lockdep_is_held(&req->i915->drm.struct_mutex) !=
1040 !!(flags & I915_WAIT_LOCKED));
1042 GEM_BUG_ON(timeout < 0);
1044 if (i915_gem_request_completed(req))
1050 trace_i915_gem_request_wait_begin(req);
1052 if (!i915_sw_fence_done(&req->execute)) {
1053 timeout = __i915_request_wait_for_execute(req, flags, timeout);
1057 GEM_BUG_ON(!i915_sw_fence_done(&req->execute));
1059 GEM_BUG_ON(!i915_sw_fence_done(&req->submit));
1060 GEM_BUG_ON(!req->global_seqno);
1062 /* Optimistic short spin before touching IRQs */
1063 if (i915_spin_request(req, state, 5))
1066 set_current_state(state);
1067 if (flags & I915_WAIT_LOCKED)
1068 add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1070 intel_wait_init(&wait, req->global_seqno);
1071 if (intel_engine_add_wait(req->engine, &wait))
1072 /* In order to check that we haven't missed the interrupt
1073 * as we enabled it, we need to kick ourselves to do a
1074 * coherent check on the seqno before we sleep.
1079 if (signal_pending_state(state, current)) {
1080 timeout = -ERESTARTSYS;
1089 timeout = io_schedule_timeout(timeout);
1091 if (intel_wait_complete(&wait))
1094 set_current_state(state);
1097 /* Carefully check if the request is complete, giving time
1098 * for the seqno to be visible following the interrupt.
1099 * We also have to check in case we are kicked by the GPU
1100 * reset in order to drop the struct_mutex.
1102 if (__i915_request_irq_complete(req))
1105 /* If the GPU is hung, and we hold the lock, reset the GPU
1106 * and then check for completion. On a full reset, the engine's
1107 * HW seqno will be advanced passed us and we are complete.
1108 * If we do a partial reset, we have to wait for the GPU to
1109 * resume and update the breadcrumb.
1111 * If we don't hold the mutex, we can just wait for the worker
1112 * to come along and update the breadcrumb (either directly
1113 * itself, or indirectly by recovering the GPU).
1115 if (flags & I915_WAIT_LOCKED &&
1116 i915_reset_in_progress(&req->i915->gpu_error)) {
1117 __set_current_state(TASK_RUNNING);
1118 i915_reset(req->i915);
1119 reset_wait_queue(&req->i915->gpu_error.wait_queue,
1124 /* Only spin if we know the GPU is processing this request */
1125 if (i915_spin_request(req, state, 2))
1129 intel_engine_remove_wait(req->engine, &wait);
1130 if (flags & I915_WAIT_LOCKED)
1131 remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1132 __set_current_state(TASK_RUNNING);
1135 trace_i915_gem_request_wait_end(req);
1140 static void engine_retire_requests(struct intel_engine_cs *engine)
1142 struct drm_i915_gem_request *request, *next;
1144 list_for_each_entry_safe(request, next,
1145 &engine->timeline->requests, link) {
1146 if (!__i915_gem_request_completed(request))
1149 i915_gem_request_retire(request);
1153 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
1155 struct intel_engine_cs *engine;
1156 enum intel_engine_id id;
1158 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1160 if (!dev_priv->gt.active_requests)
1163 for_each_engine(engine, dev_priv, id)
1164 engine_retire_requests(engine);